1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/firmware.h> 10 #include <linux/of.h> 11 #include <linux/property.h> 12 #include <linux/dmi.h> 13 #include <linux/ctype.h> 14 #include <linux/pm_qos.h> 15 #include <linux/nvmem-consumer.h> 16 #include <asm/byteorder.h> 17 18 #include "core.h" 19 #include "mac.h" 20 #include "htc.h" 21 #include "hif.h" 22 #include "wmi.h" 23 #include "bmi.h" 24 #include "debug.h" 25 #include "htt.h" 26 #include "testmode.h" 27 #include "wmi-ops.h" 28 #include "coredump.h" 29 30 unsigned int ath10k_debug_mask; 31 EXPORT_SYMBOL(ath10k_debug_mask); 32 33 static unsigned int ath10k_cryptmode_param; 34 static bool uart_print; 35 static bool skip_otp; 36 static bool rawmode; 37 static bool fw_diag_log; 38 39 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 40 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 41 42 /* FIXME: most of these should be readonly */ 43 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 44 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 45 module_param(uart_print, bool, 0644); 46 module_param(skip_otp, bool, 0644); 47 module_param(rawmode, bool, 0644); 48 module_param(fw_diag_log, bool, 0644); 49 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 50 51 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 52 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 53 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 54 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 55 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath"); 56 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 57 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 58 59 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 60 { 61 .id = QCA988X_HW_2_0_VERSION, 62 .dev_id = QCA988X_2_0_DEVICE_ID, 63 .bus = ATH10K_BUS_PCI, 64 .name = "qca988x hw2.0", 65 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 66 .uart_pin = 7, 67 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 68 .otp_exe_param = 0, 69 .channel_counters_freq_hz = 88000, 70 .max_probe_resp_desc_thres = 0, 71 .cal_data_len = 2116, 72 .fw = { 73 .dir = QCA988X_HW_2_0_FW_DIR, 74 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 75 .board_size = QCA988X_BOARD_DATA_SZ, 76 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 77 }, 78 .rx_desc_ops = &qca988x_rx_desc_ops, 79 .hw_ops = &qca988x_ops, 80 .decap_align_bytes = 4, 81 .spectral_bin_discard = 0, 82 .spectral_bin_offset = 0, 83 .vht160_mcs_rx_highest = 0, 84 .vht160_mcs_tx_highest = 0, 85 .n_cipher_suites = 8, 86 .ast_skid_limit = 0x10, 87 .num_wds_entries = 0x20, 88 .target_64bit = false, 89 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 90 .shadow_reg_support = false, 91 .rri_on_ddr = false, 92 .hw_filter_reset_required = true, 93 .fw_diag_ce_download = false, 94 .credit_size_workaround = false, 95 .tx_stats_over_pktlog = true, 96 .dynamic_sar_support = false, 97 .hw_restart_disconnect = false, 98 }, 99 { 100 .id = QCA988X_HW_2_0_VERSION, 101 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 102 .name = "qca988x hw2.0 ubiquiti", 103 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 104 .uart_pin = 7, 105 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 106 .otp_exe_param = 0, 107 .channel_counters_freq_hz = 88000, 108 .max_probe_resp_desc_thres = 0, 109 .cal_data_len = 2116, 110 .fw = { 111 .dir = QCA988X_HW_2_0_FW_DIR, 112 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 113 .board_size = QCA988X_BOARD_DATA_SZ, 114 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 115 }, 116 .rx_desc_ops = &qca988x_rx_desc_ops, 117 .hw_ops = &qca988x_ops, 118 .decap_align_bytes = 4, 119 .spectral_bin_discard = 0, 120 .spectral_bin_offset = 0, 121 .vht160_mcs_rx_highest = 0, 122 .vht160_mcs_tx_highest = 0, 123 .n_cipher_suites = 8, 124 .ast_skid_limit = 0x10, 125 .num_wds_entries = 0x20, 126 .target_64bit = false, 127 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 128 .shadow_reg_support = false, 129 .rri_on_ddr = false, 130 .hw_filter_reset_required = true, 131 .fw_diag_ce_download = false, 132 .credit_size_workaround = false, 133 .tx_stats_over_pktlog = true, 134 .dynamic_sar_support = false, 135 .hw_restart_disconnect = false, 136 }, 137 { 138 .id = QCA9887_HW_1_0_VERSION, 139 .dev_id = QCA9887_1_0_DEVICE_ID, 140 .bus = ATH10K_BUS_PCI, 141 .name = "qca9887 hw1.0", 142 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 143 .uart_pin = 7, 144 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 145 .otp_exe_param = 0, 146 .channel_counters_freq_hz = 88000, 147 .max_probe_resp_desc_thres = 0, 148 .cal_data_len = 2116, 149 .fw = { 150 .dir = QCA9887_HW_1_0_FW_DIR, 151 .board = QCA9887_HW_1_0_BOARD_DATA_FILE, 152 .board_size = QCA9887_BOARD_DATA_SZ, 153 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 154 }, 155 .rx_desc_ops = &qca988x_rx_desc_ops, 156 .hw_ops = &qca988x_ops, 157 .decap_align_bytes = 4, 158 .spectral_bin_discard = 0, 159 .spectral_bin_offset = 0, 160 .vht160_mcs_rx_highest = 0, 161 .vht160_mcs_tx_highest = 0, 162 .n_cipher_suites = 8, 163 .ast_skid_limit = 0x10, 164 .num_wds_entries = 0x20, 165 .target_64bit = false, 166 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 167 .shadow_reg_support = false, 168 .rri_on_ddr = false, 169 .hw_filter_reset_required = true, 170 .fw_diag_ce_download = false, 171 .credit_size_workaround = false, 172 .tx_stats_over_pktlog = false, 173 .dynamic_sar_support = false, 174 .hw_restart_disconnect = false, 175 }, 176 { 177 .id = QCA6174_HW_3_2_VERSION, 178 .dev_id = QCA6174_3_2_DEVICE_ID, 179 .bus = ATH10K_BUS_SDIO, 180 .name = "qca6174 hw3.2 sdio", 181 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 182 .uart_pin = 19, 183 .otp_exe_param = 0, 184 .channel_counters_freq_hz = 88000, 185 .max_probe_resp_desc_thres = 0, 186 .cal_data_len = 0, 187 .fw = { 188 .dir = QCA6174_HW_3_0_FW_DIR, 189 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 190 .board_size = QCA6174_BOARD_DATA_SZ, 191 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 192 }, 193 .rx_desc_ops = &qca988x_rx_desc_ops, 194 .hw_ops = &qca6174_sdio_ops, 195 .hw_clk = qca6174_clk, 196 .target_cpu_freq = 176000000, 197 .decap_align_bytes = 4, 198 .n_cipher_suites = 8, 199 .num_peers = 10, 200 .ast_skid_limit = 0x10, 201 .num_wds_entries = 0x20, 202 .uart_pin_workaround = true, 203 .tx_stats_over_pktlog = false, 204 .credit_size_workaround = false, 205 .bmi_large_size_download = true, 206 .supports_peer_stats_info = true, 207 .dynamic_sar_support = true, 208 .hw_restart_disconnect = false, 209 }, 210 { 211 .id = QCA6174_HW_2_1_VERSION, 212 .dev_id = QCA6164_2_1_DEVICE_ID, 213 .bus = ATH10K_BUS_PCI, 214 .name = "qca6164 hw2.1", 215 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 216 .uart_pin = 6, 217 .otp_exe_param = 0, 218 .channel_counters_freq_hz = 88000, 219 .max_probe_resp_desc_thres = 0, 220 .cal_data_len = 8124, 221 .fw = { 222 .dir = QCA6174_HW_2_1_FW_DIR, 223 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 224 .board_size = QCA6174_BOARD_DATA_SZ, 225 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 226 }, 227 .rx_desc_ops = &qca988x_rx_desc_ops, 228 .hw_ops = &qca988x_ops, 229 .decap_align_bytes = 4, 230 .spectral_bin_discard = 0, 231 .spectral_bin_offset = 0, 232 .vht160_mcs_rx_highest = 0, 233 .vht160_mcs_tx_highest = 0, 234 .n_cipher_suites = 8, 235 .ast_skid_limit = 0x10, 236 .num_wds_entries = 0x20, 237 .target_64bit = false, 238 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 239 .shadow_reg_support = false, 240 .rri_on_ddr = false, 241 .hw_filter_reset_required = true, 242 .fw_diag_ce_download = false, 243 .credit_size_workaround = false, 244 .tx_stats_over_pktlog = false, 245 .dynamic_sar_support = false, 246 .hw_restart_disconnect = false, 247 }, 248 { 249 .id = QCA6174_HW_2_1_VERSION, 250 .dev_id = QCA6174_2_1_DEVICE_ID, 251 .bus = ATH10K_BUS_PCI, 252 .name = "qca6174 hw2.1", 253 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 254 .uart_pin = 6, 255 .otp_exe_param = 0, 256 .channel_counters_freq_hz = 88000, 257 .max_probe_resp_desc_thres = 0, 258 .cal_data_len = 8124, 259 .fw = { 260 .dir = QCA6174_HW_2_1_FW_DIR, 261 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 262 .board_size = QCA6174_BOARD_DATA_SZ, 263 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 264 }, 265 .rx_desc_ops = &qca988x_rx_desc_ops, 266 .hw_ops = &qca988x_ops, 267 .decap_align_bytes = 4, 268 .spectral_bin_discard = 0, 269 .spectral_bin_offset = 0, 270 .vht160_mcs_rx_highest = 0, 271 .vht160_mcs_tx_highest = 0, 272 .n_cipher_suites = 8, 273 .ast_skid_limit = 0x10, 274 .num_wds_entries = 0x20, 275 .target_64bit = false, 276 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 277 .shadow_reg_support = false, 278 .rri_on_ddr = false, 279 .hw_filter_reset_required = true, 280 .fw_diag_ce_download = false, 281 .credit_size_workaround = false, 282 .tx_stats_over_pktlog = false, 283 .dynamic_sar_support = false, 284 .hw_restart_disconnect = false, 285 }, 286 { 287 .id = QCA6174_HW_3_0_VERSION, 288 .dev_id = QCA6174_2_1_DEVICE_ID, 289 .bus = ATH10K_BUS_PCI, 290 .name = "qca6174 hw3.0", 291 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 292 .uart_pin = 6, 293 .otp_exe_param = 0, 294 .channel_counters_freq_hz = 88000, 295 .max_probe_resp_desc_thres = 0, 296 .cal_data_len = 8124, 297 .fw = { 298 .dir = QCA6174_HW_3_0_FW_DIR, 299 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 300 .board_size = QCA6174_BOARD_DATA_SZ, 301 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 302 }, 303 .rx_desc_ops = &qca988x_rx_desc_ops, 304 .hw_ops = &qca988x_ops, 305 .decap_align_bytes = 4, 306 .spectral_bin_discard = 0, 307 .spectral_bin_offset = 0, 308 .vht160_mcs_rx_highest = 0, 309 .vht160_mcs_tx_highest = 0, 310 .n_cipher_suites = 8, 311 .ast_skid_limit = 0x10, 312 .num_wds_entries = 0x20, 313 .target_64bit = false, 314 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 315 .shadow_reg_support = false, 316 .rri_on_ddr = false, 317 .hw_filter_reset_required = true, 318 .fw_diag_ce_download = false, 319 .credit_size_workaround = false, 320 .tx_stats_over_pktlog = false, 321 .dynamic_sar_support = false, 322 .hw_restart_disconnect = false, 323 }, 324 { 325 .id = QCA6174_HW_3_2_VERSION, 326 .dev_id = QCA6174_2_1_DEVICE_ID, 327 .bus = ATH10K_BUS_PCI, 328 .name = "qca6174 hw3.2", 329 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 330 .uart_pin = 6, 331 .otp_exe_param = 0, 332 .channel_counters_freq_hz = 88000, 333 .max_probe_resp_desc_thres = 0, 334 .cal_data_len = 8124, 335 .fw = { 336 /* uses same binaries as hw3.0 */ 337 .dir = QCA6174_HW_3_0_FW_DIR, 338 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 339 .board_size = QCA6174_BOARD_DATA_SZ, 340 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 341 }, 342 .rx_desc_ops = &qca988x_rx_desc_ops, 343 .hw_ops = &qca6174_ops, 344 .hw_clk = qca6174_clk, 345 .target_cpu_freq = 176000000, 346 .decap_align_bytes = 4, 347 .spectral_bin_discard = 0, 348 .spectral_bin_offset = 0, 349 .vht160_mcs_rx_highest = 0, 350 .vht160_mcs_tx_highest = 0, 351 .n_cipher_suites = 8, 352 .ast_skid_limit = 0x10, 353 .num_wds_entries = 0x20, 354 .target_64bit = false, 355 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 356 .shadow_reg_support = false, 357 .rri_on_ddr = false, 358 .hw_filter_reset_required = true, 359 .fw_diag_ce_download = true, 360 .credit_size_workaround = false, 361 .tx_stats_over_pktlog = false, 362 .supports_peer_stats_info = true, 363 .dynamic_sar_support = true, 364 .hw_restart_disconnect = false, 365 }, 366 { 367 .id = QCA99X0_HW_2_0_DEV_VERSION, 368 .dev_id = QCA99X0_2_0_DEVICE_ID, 369 .bus = ATH10K_BUS_PCI, 370 .name = "qca99x0 hw2.0", 371 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 372 .uart_pin = 7, 373 .otp_exe_param = 0x00000700, 374 .continuous_frag_desc = true, 375 .cck_rate_map_rev2 = true, 376 .channel_counters_freq_hz = 150000, 377 .max_probe_resp_desc_thres = 24, 378 .tx_chain_mask = 0xf, 379 .rx_chain_mask = 0xf, 380 .max_spatial_stream = 4, 381 .cal_data_len = 12064, 382 .fw = { 383 .dir = QCA99X0_HW_2_0_FW_DIR, 384 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, 385 .board_size = QCA99X0_BOARD_DATA_SZ, 386 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 387 }, 388 .sw_decrypt_mcast_mgmt = true, 389 .rx_desc_ops = &qca99x0_rx_desc_ops, 390 .hw_ops = &qca99x0_ops, 391 .decap_align_bytes = 1, 392 .spectral_bin_discard = 4, 393 .spectral_bin_offset = 0, 394 .vht160_mcs_rx_highest = 0, 395 .vht160_mcs_tx_highest = 0, 396 .n_cipher_suites = 11, 397 .ast_skid_limit = 0x10, 398 .num_wds_entries = 0x20, 399 .target_64bit = false, 400 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 401 .shadow_reg_support = false, 402 .rri_on_ddr = false, 403 .hw_filter_reset_required = true, 404 .fw_diag_ce_download = false, 405 .credit_size_workaround = false, 406 .tx_stats_over_pktlog = false, 407 .dynamic_sar_support = false, 408 .hw_restart_disconnect = false, 409 }, 410 { 411 .id = QCA9984_HW_1_0_DEV_VERSION, 412 .dev_id = QCA9984_1_0_DEVICE_ID, 413 .bus = ATH10K_BUS_PCI, 414 .name = "qca9984/qca9994 hw1.0", 415 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 416 .uart_pin = 7, 417 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 418 .otp_exe_param = 0x00000700, 419 .continuous_frag_desc = true, 420 .cck_rate_map_rev2 = true, 421 .channel_counters_freq_hz = 150000, 422 .max_probe_resp_desc_thres = 24, 423 .tx_chain_mask = 0xf, 424 .rx_chain_mask = 0xf, 425 .max_spatial_stream = 4, 426 .cal_data_len = 12064, 427 .fw = { 428 .dir = QCA9984_HW_1_0_FW_DIR, 429 .board = QCA9984_HW_1_0_BOARD_DATA_FILE, 430 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE, 431 .board_size = QCA99X0_BOARD_DATA_SZ, 432 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 433 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 434 }, 435 .sw_decrypt_mcast_mgmt = true, 436 .rx_desc_ops = &qca99x0_rx_desc_ops, 437 .hw_ops = &qca99x0_ops, 438 .decap_align_bytes = 1, 439 .spectral_bin_discard = 12, 440 .spectral_bin_offset = 8, 441 442 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 443 * or 2x2 160Mhz, long-guard-interval. 444 */ 445 .vht160_mcs_rx_highest = 1560, 446 .vht160_mcs_tx_highest = 1560, 447 .n_cipher_suites = 11, 448 .ast_skid_limit = 0x10, 449 .num_wds_entries = 0x20, 450 .target_64bit = false, 451 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 452 .shadow_reg_support = false, 453 .rri_on_ddr = false, 454 .hw_filter_reset_required = true, 455 .fw_diag_ce_download = false, 456 .credit_size_workaround = false, 457 .tx_stats_over_pktlog = false, 458 .dynamic_sar_support = false, 459 .hw_restart_disconnect = false, 460 }, 461 { 462 .id = QCA9888_HW_2_0_DEV_VERSION, 463 .dev_id = QCA9888_2_0_DEVICE_ID, 464 .bus = ATH10K_BUS_PCI, 465 .name = "qca9888 hw2.0", 466 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 467 .uart_pin = 7, 468 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 469 .otp_exe_param = 0x00000700, 470 .continuous_frag_desc = true, 471 .channel_counters_freq_hz = 150000, 472 .max_probe_resp_desc_thres = 24, 473 .tx_chain_mask = 3, 474 .rx_chain_mask = 3, 475 .max_spatial_stream = 2, 476 .cal_data_len = 12064, 477 .fw = { 478 .dir = QCA9888_HW_2_0_FW_DIR, 479 .board = QCA9888_HW_2_0_BOARD_DATA_FILE, 480 .board_size = QCA99X0_BOARD_DATA_SZ, 481 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 482 }, 483 .sw_decrypt_mcast_mgmt = true, 484 .rx_desc_ops = &qca99x0_rx_desc_ops, 485 .hw_ops = &qca99x0_ops, 486 .decap_align_bytes = 1, 487 .spectral_bin_discard = 12, 488 .spectral_bin_offset = 8, 489 490 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 491 * 1x1 160Mhz, long-guard-interval. 492 */ 493 .vht160_mcs_rx_highest = 780, 494 .vht160_mcs_tx_highest = 780, 495 .n_cipher_suites = 11, 496 .ast_skid_limit = 0x10, 497 .num_wds_entries = 0x20, 498 .target_64bit = false, 499 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 500 .shadow_reg_support = false, 501 .rri_on_ddr = false, 502 .hw_filter_reset_required = true, 503 .fw_diag_ce_download = false, 504 .credit_size_workaround = false, 505 .tx_stats_over_pktlog = false, 506 .dynamic_sar_support = false, 507 .hw_restart_disconnect = false, 508 }, 509 { 510 .id = QCA9377_HW_1_0_DEV_VERSION, 511 .dev_id = QCA9377_1_0_DEVICE_ID, 512 .bus = ATH10K_BUS_PCI, 513 .name = "qca9377 hw1.0", 514 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 515 .uart_pin = 6, 516 .otp_exe_param = 0, 517 .channel_counters_freq_hz = 88000, 518 .max_probe_resp_desc_thres = 0, 519 .cal_data_len = 8124, 520 .fw = { 521 .dir = QCA9377_HW_1_0_FW_DIR, 522 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 523 .board_size = QCA9377_BOARD_DATA_SZ, 524 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 525 }, 526 .rx_desc_ops = &qca988x_rx_desc_ops, 527 .hw_ops = &qca988x_ops, 528 .decap_align_bytes = 4, 529 .spectral_bin_discard = 0, 530 .spectral_bin_offset = 0, 531 .vht160_mcs_rx_highest = 0, 532 .vht160_mcs_tx_highest = 0, 533 .n_cipher_suites = 8, 534 .ast_skid_limit = 0x10, 535 .num_wds_entries = 0x20, 536 .target_64bit = false, 537 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 538 .shadow_reg_support = false, 539 .rri_on_ddr = false, 540 .hw_filter_reset_required = true, 541 .fw_diag_ce_download = false, 542 .credit_size_workaround = false, 543 .tx_stats_over_pktlog = false, 544 .dynamic_sar_support = false, 545 .hw_restart_disconnect = false, 546 }, 547 { 548 .id = QCA9377_HW_1_1_DEV_VERSION, 549 .dev_id = QCA9377_1_0_DEVICE_ID, 550 .bus = ATH10K_BUS_PCI, 551 .name = "qca9377 hw1.1", 552 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 553 .uart_pin = 6, 554 .otp_exe_param = 0, 555 .channel_counters_freq_hz = 88000, 556 .max_probe_resp_desc_thres = 0, 557 .cal_data_len = 8124, 558 .fw = { 559 .dir = QCA9377_HW_1_0_FW_DIR, 560 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 561 .board_size = QCA9377_BOARD_DATA_SZ, 562 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 563 }, 564 .rx_desc_ops = &qca988x_rx_desc_ops, 565 .hw_ops = &qca6174_ops, 566 .hw_clk = qca6174_clk, 567 .target_cpu_freq = 176000000, 568 .decap_align_bytes = 4, 569 .spectral_bin_discard = 0, 570 .spectral_bin_offset = 0, 571 .vht160_mcs_rx_highest = 0, 572 .vht160_mcs_tx_highest = 0, 573 .n_cipher_suites = 8, 574 .ast_skid_limit = 0x10, 575 .num_wds_entries = 0x20, 576 .target_64bit = false, 577 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 578 .shadow_reg_support = false, 579 .rri_on_ddr = false, 580 .hw_filter_reset_required = true, 581 .fw_diag_ce_download = true, 582 .credit_size_workaround = false, 583 .tx_stats_over_pktlog = false, 584 .dynamic_sar_support = false, 585 .hw_restart_disconnect = false, 586 }, 587 { 588 .id = QCA9377_HW_1_1_DEV_VERSION, 589 .dev_id = QCA9377_1_0_DEVICE_ID, 590 .bus = ATH10K_BUS_SDIO, 591 .name = "qca9377 hw1.1 sdio", 592 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 593 .uart_pin = 19, 594 .otp_exe_param = 0, 595 .channel_counters_freq_hz = 88000, 596 .max_probe_resp_desc_thres = 0, 597 .cal_data_len = 8124, 598 .fw = { 599 .dir = QCA9377_HW_1_0_FW_DIR, 600 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 601 .board_size = QCA9377_BOARD_DATA_SZ, 602 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 603 }, 604 .rx_desc_ops = &qca988x_rx_desc_ops, 605 .hw_ops = &qca6174_ops, 606 .hw_clk = qca6174_clk, 607 .target_cpu_freq = 176000000, 608 .decap_align_bytes = 4, 609 .n_cipher_suites = 8, 610 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 611 .ast_skid_limit = 0x10, 612 .num_wds_entries = 0x20, 613 .uart_pin_workaround = true, 614 .credit_size_workaround = true, 615 .dynamic_sar_support = false, 616 .hw_restart_disconnect = false, 617 }, 618 { 619 .id = QCA4019_HW_1_0_DEV_VERSION, 620 .dev_id = 0, 621 .bus = ATH10K_BUS_AHB, 622 .name = "qca4019 hw1.0", 623 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 624 .uart_pin = 7, 625 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 626 .otp_exe_param = 0x0010000, 627 .continuous_frag_desc = true, 628 .cck_rate_map_rev2 = true, 629 .channel_counters_freq_hz = 125000, 630 .max_probe_resp_desc_thres = 24, 631 .tx_chain_mask = 0x3, 632 .rx_chain_mask = 0x3, 633 .max_spatial_stream = 2, 634 .cal_data_len = 12064, 635 .fw = { 636 .dir = QCA4019_HW_1_0_FW_DIR, 637 .board = QCA4019_HW_1_0_BOARD_DATA_FILE, 638 .board_size = QCA4019_BOARD_DATA_SZ, 639 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 640 }, 641 .sw_decrypt_mcast_mgmt = true, 642 .rx_desc_ops = &qca99x0_rx_desc_ops, 643 .hw_ops = &qca99x0_ops, 644 .decap_align_bytes = 1, 645 .spectral_bin_discard = 4, 646 .spectral_bin_offset = 0, 647 .vht160_mcs_rx_highest = 0, 648 .vht160_mcs_tx_highest = 0, 649 .n_cipher_suites = 11, 650 .ast_skid_limit = 0x10, 651 .num_wds_entries = 0x20, 652 .target_64bit = false, 653 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 654 .shadow_reg_support = false, 655 .rri_on_ddr = false, 656 .hw_filter_reset_required = true, 657 .fw_diag_ce_download = false, 658 .credit_size_workaround = false, 659 .tx_stats_over_pktlog = false, 660 .dynamic_sar_support = false, 661 .hw_restart_disconnect = false, 662 }, 663 { 664 .id = WCN3990_HW_1_0_DEV_VERSION, 665 .dev_id = 0, 666 .bus = ATH10K_BUS_SNOC, 667 .name = "wcn3990 hw1.0", 668 .continuous_frag_desc = true, 669 .tx_chain_mask = 0x7, 670 .rx_chain_mask = 0x7, 671 .max_spatial_stream = 4, 672 .fw = { 673 .dir = WCN3990_HW_1_0_FW_DIR, 674 }, 675 .sw_decrypt_mcast_mgmt = true, 676 .rx_desc_ops = &wcn3990_rx_desc_ops, 677 .hw_ops = &wcn3990_ops, 678 .decap_align_bytes = 1, 679 .num_peers = TARGET_HL_TLV_NUM_PEERS, 680 .n_cipher_suites = 11, 681 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 682 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 683 .target_64bit = true, 684 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 685 .shadow_reg_support = true, 686 .rri_on_ddr = true, 687 .hw_filter_reset_required = false, 688 .fw_diag_ce_download = false, 689 .credit_size_workaround = false, 690 .tx_stats_over_pktlog = false, 691 .dynamic_sar_support = true, 692 .hw_restart_disconnect = true, 693 }, 694 }; 695 696 static const char *const ath10k_core_fw_feature_str[] = { 697 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 698 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 699 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 700 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 701 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 702 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 703 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 704 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 705 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 706 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 707 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 708 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 709 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 710 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 711 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 712 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 713 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 714 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 715 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 716 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 717 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 718 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 719 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 720 }; 721 722 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 723 size_t buf_len, 724 enum ath10k_fw_features feat) 725 { 726 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 727 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 728 ATH10K_FW_FEATURE_COUNT); 729 730 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 731 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 732 return scnprintf(buf, buf_len, "bit%d", feat); 733 } 734 735 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 736 } 737 738 void ath10k_core_get_fw_features_str(struct ath10k *ar, 739 char *buf, 740 size_t buf_len) 741 { 742 size_t len = 0; 743 int i; 744 745 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 746 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 747 if (len > 0) 748 len += scnprintf(buf + len, buf_len - len, ","); 749 750 len += ath10k_core_get_fw_feature_str(buf + len, 751 buf_len - len, 752 i); 753 } 754 } 755 } 756 757 static void ath10k_send_suspend_complete(struct ath10k *ar) 758 { 759 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 760 761 complete(&ar->target_suspend); 762 } 763 764 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 765 { 766 bool mtu_workaround = ar->hw_params.credit_size_workaround; 767 int ret; 768 u32 param = 0; 769 770 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 771 if (ret) 772 return ret; 773 774 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 775 if (ret) 776 return ret; 777 778 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 779 if (ret) 780 return ret; 781 782 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 783 784 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 785 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 786 else 787 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 788 789 if (mode == ATH10K_FIRMWARE_MODE_UTF) 790 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 791 else 792 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 793 794 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 795 if (ret) 796 return ret; 797 798 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 799 if (ret) 800 return ret; 801 802 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 803 804 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 805 if (ret) 806 return ret; 807 808 return 0; 809 } 810 811 static int ath10k_init_configure_target(struct ath10k *ar) 812 { 813 u32 param_host; 814 int ret; 815 816 /* tell target which HTC version it is used*/ 817 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 818 HTC_PROTOCOL_VERSION); 819 if (ret) { 820 ath10k_err(ar, "settings HTC version failed\n"); 821 return ret; 822 } 823 824 /* set the firmware mode to STA/IBSS/AP */ 825 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 826 if (ret) { 827 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 828 return ret; 829 } 830 831 /* TODO following parameters need to be re-visited. */ 832 /* num_device */ 833 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 834 /* Firmware mode */ 835 /* FIXME: Why FW_MODE_AP ??.*/ 836 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 837 /* mac_addr_method */ 838 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 839 /* firmware_bridge */ 840 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 841 /* fwsubmode */ 842 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 843 844 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 845 if (ret) { 846 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 847 return ret; 848 } 849 850 /* We do all byte-swapping on the host */ 851 ret = ath10k_bmi_write32(ar, hi_be, 0); 852 if (ret) { 853 ath10k_err(ar, "setting host CPU BE mode failed\n"); 854 return ret; 855 } 856 857 /* FW descriptor/Data swap flags */ 858 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 859 860 if (ret) { 861 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 862 return ret; 863 } 864 865 /* Some devices have a special sanity check that verifies the PCI 866 * Device ID is written to this host interest var. It is known to be 867 * required to boot QCA6164. 868 */ 869 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 870 ar->dev_id); 871 if (ret) { 872 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 873 return ret; 874 } 875 876 return 0; 877 } 878 879 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 880 const char *dir, 881 const char *file) 882 { 883 char filename[100]; 884 const struct firmware *fw; 885 int ret; 886 887 if (file == NULL) 888 return ERR_PTR(-ENOENT); 889 890 if (dir == NULL) 891 dir = "."; 892 893 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 894 ret = firmware_request_nowarn(&fw, filename, ar->dev); 895 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 896 filename, ret); 897 898 if (ret) 899 return ERR_PTR(ret); 900 901 return fw; 902 } 903 904 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 905 size_t data_len) 906 { 907 u32 board_data_size = ar->hw_params.fw.board_size; 908 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 909 u32 board_ext_data_addr; 910 int ret; 911 912 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 913 if (ret) { 914 ath10k_err(ar, "could not read board ext data addr (%d)\n", 915 ret); 916 return ret; 917 } 918 919 ath10k_dbg(ar, ATH10K_DBG_BOOT, 920 "boot push board extended data addr 0x%x\n", 921 board_ext_data_addr); 922 923 if (board_ext_data_addr == 0) 924 return 0; 925 926 if (data_len != (board_data_size + board_ext_data_size)) { 927 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 928 data_len, board_data_size, board_ext_data_size); 929 return -EINVAL; 930 } 931 932 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 933 data + board_data_size, 934 board_ext_data_size); 935 if (ret) { 936 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 937 return ret; 938 } 939 940 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 941 (board_ext_data_size << 16) | 1); 942 if (ret) { 943 ath10k_err(ar, "could not write board ext data bit (%d)\n", 944 ret); 945 return ret; 946 } 947 948 return 0; 949 } 950 951 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 952 { 953 u32 result, address; 954 u8 board_id, chip_id; 955 bool ext_bid_support; 956 int ret, bmi_board_id_param; 957 958 address = ar->hw_params.patch_load_addr; 959 960 if (!ar->normal_mode_fw.fw_file.otp_data || 961 !ar->normal_mode_fw.fw_file.otp_len) { 962 ath10k_warn(ar, 963 "failed to retrieve board id because of invalid otp\n"); 964 return -ENODATA; 965 } 966 967 if (ar->id.bmi_ids_valid) { 968 ath10k_dbg(ar, ATH10K_DBG_BOOT, 969 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 970 ar->id.bmi_board_id, ar->id.bmi_chip_id); 971 goto skip_otp_download; 972 } 973 974 ath10k_dbg(ar, ATH10K_DBG_BOOT, 975 "boot upload otp to 0x%x len %zd for board id\n", 976 address, ar->normal_mode_fw.fw_file.otp_len); 977 978 ret = ath10k_bmi_fast_download(ar, address, 979 ar->normal_mode_fw.fw_file.otp_data, 980 ar->normal_mode_fw.fw_file.otp_len); 981 if (ret) { 982 ath10k_err(ar, "could not write otp for board id check: %d\n", 983 ret); 984 return ret; 985 } 986 987 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 988 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 989 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 990 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 991 else 992 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 993 994 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 995 if (ret) { 996 ath10k_err(ar, "could not execute otp for board id check: %d\n", 997 ret); 998 return ret; 999 } 1000 1001 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1002 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1003 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1004 1005 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1006 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1007 result, board_id, chip_id, ext_bid_support); 1008 1009 ar->id.ext_bid_supported = ext_bid_support; 1010 1011 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1012 (board_id == 0)) { 1013 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1014 "board id does not exist in otp, ignore it\n"); 1015 return -EOPNOTSUPP; 1016 } 1017 1018 ar->id.bmi_ids_valid = true; 1019 ar->id.bmi_board_id = board_id; 1020 ar->id.bmi_chip_id = chip_id; 1021 1022 skip_otp_download: 1023 1024 return 0; 1025 } 1026 1027 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1028 { 1029 struct ath10k *ar = data; 1030 const char *bdf_ext; 1031 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1032 u8 bdf_enabled; 1033 int i; 1034 1035 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1036 return; 1037 1038 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1039 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1040 "wrong smbios bdf ext type length (%d).\n", 1041 hdr->length); 1042 return; 1043 } 1044 1045 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1046 if (!bdf_enabled) { 1047 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1048 return; 1049 } 1050 1051 /* Only one string exists (per spec) */ 1052 bdf_ext = (char *)hdr + hdr->length; 1053 1054 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1055 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1056 "bdf variant magic does not match.\n"); 1057 return; 1058 } 1059 1060 for (i = 0; i < strlen(bdf_ext); i++) { 1061 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1062 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1063 "bdf variant name contains non ascii chars.\n"); 1064 return; 1065 } 1066 } 1067 1068 /* Copy extension name without magic suffix */ 1069 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1070 sizeof(ar->id.bdf_ext)) < 0) { 1071 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1072 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1073 bdf_ext); 1074 return; 1075 } 1076 1077 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1078 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1079 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1080 } 1081 1082 static int ath10k_core_check_smbios(struct ath10k *ar) 1083 { 1084 ar->id.bdf_ext[0] = '\0'; 1085 dmi_walk(ath10k_core_check_bdfext, ar); 1086 1087 if (ar->id.bdf_ext[0] == '\0') 1088 return -ENODATA; 1089 1090 return 0; 1091 } 1092 1093 int ath10k_core_check_dt(struct ath10k *ar) 1094 { 1095 struct device_node *node; 1096 const char *variant = NULL; 1097 1098 node = ar->dev->of_node; 1099 if (!node) 1100 return -ENOENT; 1101 1102 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1103 &variant); 1104 if (!variant) 1105 return -ENODATA; 1106 1107 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1108 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1109 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1110 variant); 1111 1112 return 0; 1113 } 1114 EXPORT_SYMBOL(ath10k_core_check_dt); 1115 1116 static int ath10k_download_fw(struct ath10k *ar) 1117 { 1118 u32 address, data_len; 1119 const void *data; 1120 int ret; 1121 struct pm_qos_request latency_qos; 1122 1123 address = ar->hw_params.patch_load_addr; 1124 1125 data = ar->running_fw->fw_file.firmware_data; 1126 data_len = ar->running_fw->fw_file.firmware_len; 1127 1128 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1129 if (ret) { 1130 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1131 ret); 1132 return ret; 1133 } 1134 1135 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1136 "boot uploading firmware image %pK len %d\n", 1137 data, data_len); 1138 1139 /* Check if device supports to download firmware via 1140 * diag copy engine. Downloading firmware via diag CE 1141 * greatly reduces the time to download firmware. 1142 */ 1143 if (ar->hw_params.fw_diag_ce_download) { 1144 ret = ath10k_hw_diag_fast_download(ar, address, 1145 data, data_len); 1146 if (ret == 0) 1147 /* firmware upload via diag ce was successful */ 1148 return 0; 1149 1150 ath10k_warn(ar, 1151 "failed to upload firmware via diag ce, trying BMI: %d", 1152 ret); 1153 } 1154 1155 memset(&latency_qos, 0, sizeof(latency_qos)); 1156 cpu_latency_qos_add_request(&latency_qos, 0); 1157 1158 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1159 1160 cpu_latency_qos_remove_request(&latency_qos); 1161 1162 return ret; 1163 } 1164 1165 void ath10k_core_free_board_files(struct ath10k *ar) 1166 { 1167 if (!IS_ERR(ar->normal_mode_fw.board)) 1168 release_firmware(ar->normal_mode_fw.board); 1169 1170 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1171 release_firmware(ar->normal_mode_fw.ext_board); 1172 1173 ar->normal_mode_fw.board = NULL; 1174 ar->normal_mode_fw.board_data = NULL; 1175 ar->normal_mode_fw.board_len = 0; 1176 ar->normal_mode_fw.ext_board = NULL; 1177 ar->normal_mode_fw.ext_board_data = NULL; 1178 ar->normal_mode_fw.ext_board_len = 0; 1179 } 1180 EXPORT_SYMBOL(ath10k_core_free_board_files); 1181 1182 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1183 { 1184 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1185 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1186 1187 if (!IS_ERR(ar->cal_file)) 1188 release_firmware(ar->cal_file); 1189 1190 if (!IS_ERR(ar->pre_cal_file)) 1191 release_firmware(ar->pre_cal_file); 1192 1193 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1194 1195 ar->normal_mode_fw.fw_file.otp_data = NULL; 1196 ar->normal_mode_fw.fw_file.otp_len = 0; 1197 1198 ar->normal_mode_fw.fw_file.firmware = NULL; 1199 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1200 ar->normal_mode_fw.fw_file.firmware_len = 0; 1201 1202 ar->cal_file = NULL; 1203 ar->pre_cal_file = NULL; 1204 } 1205 1206 static int ath10k_fetch_cal_file(struct ath10k *ar) 1207 { 1208 char filename[100]; 1209 1210 /* pre-cal-<bus>-<id>.bin */ 1211 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1212 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1213 1214 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1215 if (!IS_ERR(ar->pre_cal_file)) 1216 goto success; 1217 1218 /* cal-<bus>-<id>.bin */ 1219 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1220 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1221 1222 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1223 if (IS_ERR(ar->cal_file)) 1224 /* calibration file is optional, don't print any warnings */ 1225 return PTR_ERR(ar->cal_file); 1226 success: 1227 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1228 ATH10K_FW_DIR, filename); 1229 1230 return 0; 1231 } 1232 1233 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1234 { 1235 const struct firmware *fw; 1236 1237 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1238 if (!ar->hw_params.fw.board) { 1239 ath10k_err(ar, "failed to find board file fw entry\n"); 1240 return -EINVAL; 1241 } 1242 1243 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1244 ar->hw_params.fw.dir, 1245 ar->hw_params.fw.board); 1246 if (IS_ERR(ar->normal_mode_fw.board)) 1247 return PTR_ERR(ar->normal_mode_fw.board); 1248 1249 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1250 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1251 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1252 if (!ar->hw_params.fw.eboard) { 1253 ath10k_err(ar, "failed to find eboard file fw entry\n"); 1254 return -EINVAL; 1255 } 1256 1257 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1258 ar->hw_params.fw.eboard); 1259 ar->normal_mode_fw.ext_board = fw; 1260 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1261 return PTR_ERR(ar->normal_mode_fw.ext_board); 1262 1263 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1264 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1271 const void *buf, size_t buf_len, 1272 const char *boardname, 1273 int bd_ie_type) 1274 { 1275 const struct ath10k_fw_ie *hdr; 1276 bool name_match_found; 1277 int ret, board_ie_id; 1278 size_t board_ie_len; 1279 const void *board_ie_data; 1280 1281 name_match_found = false; 1282 1283 /* go through ATH10K_BD_IE_BOARD_ elements */ 1284 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1285 hdr = buf; 1286 board_ie_id = le32_to_cpu(hdr->id); 1287 board_ie_len = le32_to_cpu(hdr->len); 1288 board_ie_data = hdr->data; 1289 1290 buf_len -= sizeof(*hdr); 1291 buf += sizeof(*hdr); 1292 1293 if (buf_len < ALIGN(board_ie_len, 4)) { 1294 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1295 buf_len, ALIGN(board_ie_len, 4)); 1296 ret = -EINVAL; 1297 goto out; 1298 } 1299 1300 switch (board_ie_id) { 1301 case ATH10K_BD_IE_BOARD_NAME: 1302 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1303 board_ie_data, board_ie_len); 1304 1305 if (board_ie_len != strlen(boardname)) 1306 break; 1307 1308 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1309 if (ret) 1310 break; 1311 1312 name_match_found = true; 1313 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1314 "boot found match for name '%s'", 1315 boardname); 1316 break; 1317 case ATH10K_BD_IE_BOARD_DATA: 1318 if (!name_match_found) 1319 /* no match found */ 1320 break; 1321 1322 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1323 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1324 "boot found board data for '%s'", 1325 boardname); 1326 1327 ar->normal_mode_fw.board_data = board_ie_data; 1328 ar->normal_mode_fw.board_len = board_ie_len; 1329 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1330 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1331 "boot found eboard data for '%s'", 1332 boardname); 1333 1334 ar->normal_mode_fw.ext_board_data = board_ie_data; 1335 ar->normal_mode_fw.ext_board_len = board_ie_len; 1336 } 1337 1338 ret = 0; 1339 goto out; 1340 default: 1341 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1342 board_ie_id); 1343 break; 1344 } 1345 1346 /* jump over the padding */ 1347 board_ie_len = ALIGN(board_ie_len, 4); 1348 1349 buf_len -= board_ie_len; 1350 buf += board_ie_len; 1351 } 1352 1353 /* no match found */ 1354 ret = -ENOENT; 1355 1356 out: 1357 return ret; 1358 } 1359 1360 static int ath10k_core_search_bd(struct ath10k *ar, 1361 const char *boardname, 1362 const u8 *data, 1363 size_t len) 1364 { 1365 size_t ie_len; 1366 struct ath10k_fw_ie *hdr; 1367 int ret = -ENOENT, ie_id; 1368 1369 while (len > sizeof(struct ath10k_fw_ie)) { 1370 hdr = (struct ath10k_fw_ie *)data; 1371 ie_id = le32_to_cpu(hdr->id); 1372 ie_len = le32_to_cpu(hdr->len); 1373 1374 len -= sizeof(*hdr); 1375 data = hdr->data; 1376 1377 if (len < ALIGN(ie_len, 4)) { 1378 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1379 ie_id, ie_len, len); 1380 return -EINVAL; 1381 } 1382 1383 switch (ie_id) { 1384 case ATH10K_BD_IE_BOARD: 1385 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1386 boardname, 1387 ATH10K_BD_IE_BOARD); 1388 if (ret == -ENOENT) 1389 /* no match found, continue */ 1390 break; 1391 1392 /* either found or error, so stop searching */ 1393 goto out; 1394 case ATH10K_BD_IE_BOARD_EXT: 1395 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1396 boardname, 1397 ATH10K_BD_IE_BOARD_EXT); 1398 if (ret == -ENOENT) 1399 /* no match found, continue */ 1400 break; 1401 1402 /* either found or error, so stop searching */ 1403 goto out; 1404 } 1405 1406 /* jump over the padding */ 1407 ie_len = ALIGN(ie_len, 4); 1408 1409 len -= ie_len; 1410 data += ie_len; 1411 } 1412 1413 out: 1414 /* return result of parse_bd_ie_board() or -ENOENT */ 1415 return ret; 1416 } 1417 1418 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1419 const char *boardname, 1420 const char *fallback_boardname1, 1421 const char *fallback_boardname2, 1422 const char *filename) 1423 { 1424 size_t len, magic_len; 1425 const u8 *data; 1426 int ret; 1427 1428 /* Skip if already fetched during board data download */ 1429 if (!ar->normal_mode_fw.board) 1430 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1431 ar->hw_params.fw.dir, 1432 filename); 1433 if (IS_ERR(ar->normal_mode_fw.board)) 1434 return PTR_ERR(ar->normal_mode_fw.board); 1435 1436 data = ar->normal_mode_fw.board->data; 1437 len = ar->normal_mode_fw.board->size; 1438 1439 /* magic has extra null byte padded */ 1440 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1441 if (len < magic_len) { 1442 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1443 ar->hw_params.fw.dir, filename, len); 1444 ret = -EINVAL; 1445 goto err; 1446 } 1447 1448 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1449 ath10k_err(ar, "found invalid board magic\n"); 1450 ret = -EINVAL; 1451 goto err; 1452 } 1453 1454 /* magic is padded to 4 bytes */ 1455 magic_len = ALIGN(magic_len, 4); 1456 if (len < magic_len) { 1457 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1458 ar->hw_params.fw.dir, filename, len); 1459 ret = -EINVAL; 1460 goto err; 1461 } 1462 1463 data += magic_len; 1464 len -= magic_len; 1465 1466 /* attempt to find boardname in the IE list */ 1467 ret = ath10k_core_search_bd(ar, boardname, data, len); 1468 1469 /* if we didn't find it and have a fallback name, try that */ 1470 if (ret == -ENOENT && fallback_boardname1) 1471 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1472 1473 if (ret == -ENOENT && fallback_boardname2) 1474 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1475 1476 if (ret == -ENOENT) { 1477 ath10k_err(ar, 1478 "failed to fetch board data for %s from %s/%s\n", 1479 boardname, ar->hw_params.fw.dir, filename); 1480 ret = -ENODATA; 1481 } 1482 1483 if (ret) 1484 goto err; 1485 1486 return 0; 1487 1488 err: 1489 ath10k_core_free_board_files(ar); 1490 return ret; 1491 } 1492 1493 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1494 size_t name_len, bool with_variant, 1495 bool with_chip_id) 1496 { 1497 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1498 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1499 1500 if (with_variant && ar->id.bdf_ext[0] != '\0') 1501 scnprintf(variant, sizeof(variant), ",variant=%s", 1502 ar->id.bdf_ext); 1503 1504 if (ar->id.bmi_ids_valid) { 1505 scnprintf(name, name_len, 1506 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1507 ath10k_bus_str(ar->hif.bus), 1508 ar->id.bmi_chip_id, 1509 ar->id.bmi_board_id, variant); 1510 goto out; 1511 } 1512 1513 if (ar->id.qmi_ids_valid) { 1514 if (with_chip_id) 1515 scnprintf(name, name_len, 1516 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1517 ath10k_bus_str(ar->hif.bus), 1518 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1519 variant); 1520 else 1521 scnprintf(name, name_len, 1522 "bus=%s,qmi-board-id=%x", 1523 ath10k_bus_str(ar->hif.bus), 1524 ar->id.qmi_board_id); 1525 goto out; 1526 } 1527 1528 scnprintf(name, name_len, 1529 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1530 ath10k_bus_str(ar->hif.bus), 1531 ar->id.vendor, ar->id.device, 1532 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1533 out: 1534 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1535 1536 return 0; 1537 } 1538 1539 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1540 size_t name_len) 1541 { 1542 if (ar->id.bmi_ids_valid) { 1543 scnprintf(name, name_len, 1544 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1545 ath10k_bus_str(ar->hif.bus), 1546 ar->id.bmi_chip_id, 1547 ar->id.bmi_eboard_id); 1548 1549 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1550 return 0; 1551 } 1552 /* Fallback if returned board id is zero */ 1553 return -1; 1554 } 1555 1556 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1557 { 1558 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1559 int ret; 1560 1561 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1562 /* With variant and chip id */ 1563 ret = ath10k_core_create_board_name(ar, boardname, 1564 sizeof(boardname), true, 1565 true); 1566 if (ret) { 1567 ath10k_err(ar, "failed to create board name: %d", ret); 1568 return ret; 1569 } 1570 1571 /* Without variant and only chip-id */ 1572 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1573 sizeof(boardname), false, 1574 true); 1575 if (ret) { 1576 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1577 ret); 1578 return ret; 1579 } 1580 1581 /* Without variant and without chip-id */ 1582 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1583 sizeof(boardname), false, 1584 false); 1585 if (ret) { 1586 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1587 ret); 1588 return ret; 1589 } 1590 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1591 ret = ath10k_core_create_eboard_name(ar, boardname, 1592 sizeof(boardname)); 1593 if (ret) { 1594 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1595 goto fallback; 1596 } 1597 } 1598 1599 ar->bd_api = 2; 1600 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1601 fallback_boardname1, 1602 fallback_boardname2, 1603 ATH10K_BOARD_API2_FILE); 1604 if (!ret) 1605 goto success; 1606 1607 fallback: 1608 ar->bd_api = 1; 1609 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1610 if (ret) { 1611 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1612 ar->hw_params.fw.dir); 1613 return ret; 1614 } 1615 1616 success: 1617 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1618 return 0; 1619 } 1620 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1621 1622 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1623 { 1624 u32 result, address; 1625 u8 ext_board_id; 1626 int ret; 1627 1628 address = ar->hw_params.patch_load_addr; 1629 1630 if (!ar->normal_mode_fw.fw_file.otp_data || 1631 !ar->normal_mode_fw.fw_file.otp_len) { 1632 ath10k_warn(ar, 1633 "failed to retrieve extended board id due to otp binary missing\n"); 1634 return -ENODATA; 1635 } 1636 1637 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1638 "boot upload otp to 0x%x len %zd for ext board id\n", 1639 address, ar->normal_mode_fw.fw_file.otp_len); 1640 1641 ret = ath10k_bmi_fast_download(ar, address, 1642 ar->normal_mode_fw.fw_file.otp_data, 1643 ar->normal_mode_fw.fw_file.otp_len); 1644 if (ret) { 1645 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1646 ret); 1647 return ret; 1648 } 1649 1650 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1651 if (ret) { 1652 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1653 ret); 1654 return ret; 1655 } 1656 1657 if (!result) { 1658 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1659 "ext board id does not exist in otp, ignore it\n"); 1660 return -EOPNOTSUPP; 1661 } 1662 1663 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1664 1665 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1666 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1667 result, ext_board_id); 1668 1669 ar->id.bmi_eboard_id = ext_board_id; 1670 1671 return 0; 1672 } 1673 1674 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1675 size_t data_len) 1676 { 1677 u32 board_data_size = ar->hw_params.fw.board_size; 1678 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1679 u32 board_address; 1680 u32 ext_board_address; 1681 int ret; 1682 1683 ret = ath10k_push_board_ext_data(ar, data, data_len); 1684 if (ret) { 1685 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1686 goto exit; 1687 } 1688 1689 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1690 if (ret) { 1691 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1692 goto exit; 1693 } 1694 1695 ret = ath10k_bmi_write_memory(ar, board_address, data, 1696 min_t(u32, board_data_size, 1697 data_len)); 1698 if (ret) { 1699 ath10k_err(ar, "could not write board data (%d)\n", ret); 1700 goto exit; 1701 } 1702 1703 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1704 if (ret) { 1705 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1706 goto exit; 1707 } 1708 1709 if (!ar->id.ext_bid_supported) 1710 goto exit; 1711 1712 /* Extended board data download */ 1713 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1714 if (ret == -EOPNOTSUPP) { 1715 /* Not fetching ext_board_data if ext board id is 0 */ 1716 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1717 return 0; 1718 } else if (ret) { 1719 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1720 goto exit; 1721 } 1722 1723 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1724 if (ret) 1725 goto exit; 1726 1727 if (ar->normal_mode_fw.ext_board_data) { 1728 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1729 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1730 "boot writing ext board data to addr 0x%x", 1731 ext_board_address); 1732 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1733 ar->normal_mode_fw.ext_board_data, 1734 min_t(u32, eboard_data_size, data_len)); 1735 if (ret) 1736 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1737 } 1738 1739 exit: 1740 return ret; 1741 } 1742 1743 static int ath10k_download_and_run_otp(struct ath10k *ar) 1744 { 1745 u32 result, address = ar->hw_params.patch_load_addr; 1746 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1747 int ret; 1748 1749 ret = ath10k_download_board_data(ar, 1750 ar->running_fw->board_data, 1751 ar->running_fw->board_len); 1752 if (ret) { 1753 ath10k_err(ar, "failed to download board data: %d\n", ret); 1754 return ret; 1755 } 1756 1757 /* OTP is optional */ 1758 1759 if (!ar->running_fw->fw_file.otp_data || 1760 !ar->running_fw->fw_file.otp_len) { 1761 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1762 ar->running_fw->fw_file.otp_data, 1763 ar->running_fw->fw_file.otp_len); 1764 return 0; 1765 } 1766 1767 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1768 address, ar->running_fw->fw_file.otp_len); 1769 1770 ret = ath10k_bmi_fast_download(ar, address, 1771 ar->running_fw->fw_file.otp_data, 1772 ar->running_fw->fw_file.otp_len); 1773 if (ret) { 1774 ath10k_err(ar, "could not write otp (%d)\n", ret); 1775 return ret; 1776 } 1777 1778 /* As of now pre-cal is valid for 10_4 variants */ 1779 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1780 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1781 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1782 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1783 1784 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1785 if (ret) { 1786 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1787 return ret; 1788 } 1789 1790 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1791 1792 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1793 ar->running_fw->fw_file.fw_features)) && 1794 result != 0) { 1795 ath10k_err(ar, "otp calibration failed: %d", result); 1796 return -EINVAL; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int ath10k_download_cal_file(struct ath10k *ar, 1803 const struct firmware *file) 1804 { 1805 int ret; 1806 1807 if (!file) 1808 return -ENOENT; 1809 1810 if (IS_ERR(file)) 1811 return PTR_ERR(file); 1812 1813 ret = ath10k_download_board_data(ar, file->data, file->size); 1814 if (ret) { 1815 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1816 return ret; 1817 } 1818 1819 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1820 1821 return 0; 1822 } 1823 1824 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1825 { 1826 struct device_node *node; 1827 int data_len; 1828 void *data; 1829 int ret; 1830 1831 node = ar->dev->of_node; 1832 if (!node) 1833 /* Device Tree is optional, don't print any warnings if 1834 * there's no node for ath10k. 1835 */ 1836 return -ENOENT; 1837 1838 if (!of_get_property(node, dt_name, &data_len)) { 1839 /* The calibration data node is optional */ 1840 return -ENOENT; 1841 } 1842 1843 if (data_len != ar->hw_params.cal_data_len) { 1844 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1845 data_len); 1846 ret = -EMSGSIZE; 1847 goto out; 1848 } 1849 1850 data = kmalloc(data_len, GFP_KERNEL); 1851 if (!data) { 1852 ret = -ENOMEM; 1853 goto out; 1854 } 1855 1856 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1857 if (ret) { 1858 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1859 ret); 1860 goto out_free; 1861 } 1862 1863 ret = ath10k_download_board_data(ar, data, data_len); 1864 if (ret) { 1865 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1866 ret); 1867 goto out_free; 1868 } 1869 1870 ret = 0; 1871 1872 out_free: 1873 kfree(data); 1874 1875 out: 1876 return ret; 1877 } 1878 1879 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1880 { 1881 size_t data_len; 1882 void *data = NULL; 1883 int ret; 1884 1885 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1886 if (ret) { 1887 if (ret != -EOPNOTSUPP) 1888 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1889 ret); 1890 goto out_free; 1891 } 1892 1893 ret = ath10k_download_board_data(ar, data, data_len); 1894 if (ret) { 1895 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1896 ret); 1897 goto out_free; 1898 } 1899 1900 ret = 0; 1901 1902 out_free: 1903 kfree(data); 1904 1905 return ret; 1906 } 1907 1908 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1909 { 1910 struct nvmem_cell *cell; 1911 void *buf; 1912 size_t len; 1913 int ret; 1914 1915 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1916 if (IS_ERR(cell)) { 1917 ret = PTR_ERR(cell); 1918 return ret; 1919 } 1920 1921 buf = nvmem_cell_read(cell, &len); 1922 if (IS_ERR(buf)) 1923 return PTR_ERR(buf); 1924 1925 if (ar->hw_params.cal_data_len != len) { 1926 kfree(buf); 1927 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1928 cell_name, len, ar->hw_params.cal_data_len); 1929 return -EMSGSIZE; 1930 } 1931 1932 ret = ath10k_download_board_data(ar, buf, len); 1933 kfree(buf); 1934 if (ret) 1935 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 1936 cell_name, ret); 1937 1938 return ret; 1939 } 1940 1941 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1942 struct ath10k_fw_file *fw_file) 1943 { 1944 size_t magic_len, len, ie_len; 1945 int ie_id, i, index, bit, ret; 1946 struct ath10k_fw_ie *hdr; 1947 const u8 *data; 1948 __le32 *timestamp, *version; 1949 1950 /* first fetch the firmware file (firmware-*.bin) */ 1951 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1952 name); 1953 if (IS_ERR(fw_file->firmware)) 1954 return PTR_ERR(fw_file->firmware); 1955 1956 data = fw_file->firmware->data; 1957 len = fw_file->firmware->size; 1958 1959 /* magic also includes the null byte, check that as well */ 1960 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 1961 1962 if (len < magic_len) { 1963 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 1964 ar->hw_params.fw.dir, name, len); 1965 ret = -EINVAL; 1966 goto err; 1967 } 1968 1969 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 1970 ath10k_err(ar, "invalid firmware magic\n"); 1971 ret = -EINVAL; 1972 goto err; 1973 } 1974 1975 /* jump over the padding */ 1976 magic_len = ALIGN(magic_len, 4); 1977 1978 len -= magic_len; 1979 data += magic_len; 1980 1981 /* loop elements */ 1982 while (len > sizeof(struct ath10k_fw_ie)) { 1983 hdr = (struct ath10k_fw_ie *)data; 1984 1985 ie_id = le32_to_cpu(hdr->id); 1986 ie_len = le32_to_cpu(hdr->len); 1987 1988 len -= sizeof(*hdr); 1989 data += sizeof(*hdr); 1990 1991 if (len < ie_len) { 1992 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 1993 ie_id, len, ie_len); 1994 ret = -EINVAL; 1995 goto err; 1996 } 1997 1998 switch (ie_id) { 1999 case ATH10K_FW_IE_FW_VERSION: 2000 if (ie_len > sizeof(fw_file->fw_version) - 1) 2001 break; 2002 2003 memcpy(fw_file->fw_version, data, ie_len); 2004 fw_file->fw_version[ie_len] = '\0'; 2005 2006 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2007 "found fw version %s\n", 2008 fw_file->fw_version); 2009 break; 2010 case ATH10K_FW_IE_TIMESTAMP: 2011 if (ie_len != sizeof(u32)) 2012 break; 2013 2014 timestamp = (__le32 *)data; 2015 2016 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2017 le32_to_cpup(timestamp)); 2018 break; 2019 case ATH10K_FW_IE_FEATURES: 2020 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2021 "found firmware features ie (%zd B)\n", 2022 ie_len); 2023 2024 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2025 index = i / 8; 2026 bit = i % 8; 2027 2028 if (index == ie_len) 2029 break; 2030 2031 if (data[index] & (1 << bit)) { 2032 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2033 "Enabling feature bit: %i\n", 2034 i); 2035 __set_bit(i, fw_file->fw_features); 2036 } 2037 } 2038 2039 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2040 fw_file->fw_features, 2041 sizeof(fw_file->fw_features)); 2042 break; 2043 case ATH10K_FW_IE_FW_IMAGE: 2044 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2045 "found fw image ie (%zd B)\n", 2046 ie_len); 2047 2048 fw_file->firmware_data = data; 2049 fw_file->firmware_len = ie_len; 2050 2051 break; 2052 case ATH10K_FW_IE_OTP_IMAGE: 2053 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2054 "found otp image ie (%zd B)\n", 2055 ie_len); 2056 2057 fw_file->otp_data = data; 2058 fw_file->otp_len = ie_len; 2059 2060 break; 2061 case ATH10K_FW_IE_WMI_OP_VERSION: 2062 if (ie_len != sizeof(u32)) 2063 break; 2064 2065 version = (__le32 *)data; 2066 2067 fw_file->wmi_op_version = le32_to_cpup(version); 2068 2069 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2070 fw_file->wmi_op_version); 2071 break; 2072 case ATH10K_FW_IE_HTT_OP_VERSION: 2073 if (ie_len != sizeof(u32)) 2074 break; 2075 2076 version = (__le32 *)data; 2077 2078 fw_file->htt_op_version = le32_to_cpup(version); 2079 2080 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2081 fw_file->htt_op_version); 2082 break; 2083 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2084 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2085 "found fw code swap image ie (%zd B)\n", 2086 ie_len); 2087 fw_file->codeswap_data = data; 2088 fw_file->codeswap_len = ie_len; 2089 break; 2090 default: 2091 ath10k_warn(ar, "Unknown FW IE: %u\n", 2092 le32_to_cpu(hdr->id)); 2093 break; 2094 } 2095 2096 /* jump over the padding */ 2097 ie_len = ALIGN(ie_len, 4); 2098 2099 len -= ie_len; 2100 data += ie_len; 2101 } 2102 2103 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2104 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2105 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2106 ar->hw_params.fw.dir, name); 2107 ret = -ENOMEDIUM; 2108 goto err; 2109 } 2110 2111 return 0; 2112 2113 err: 2114 ath10k_core_free_firmware_files(ar); 2115 return ret; 2116 } 2117 2118 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2119 size_t fw_name_len, int fw_api) 2120 { 2121 switch (ar->hif.bus) { 2122 case ATH10K_BUS_SDIO: 2123 case ATH10K_BUS_USB: 2124 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2125 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2126 fw_api); 2127 break; 2128 case ATH10K_BUS_PCI: 2129 case ATH10K_BUS_AHB: 2130 case ATH10K_BUS_SNOC: 2131 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2132 ATH10K_FW_FILE_BASE, fw_api); 2133 break; 2134 } 2135 } 2136 2137 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2138 { 2139 int ret, i; 2140 char fw_name[100]; 2141 2142 /* calibration file is optional, don't check for any errors */ 2143 ath10k_fetch_cal_file(ar); 2144 2145 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2146 ar->fw_api = i; 2147 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2148 ar->fw_api); 2149 2150 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2151 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2152 &ar->normal_mode_fw.fw_file); 2153 if (!ret) 2154 goto success; 2155 } 2156 2157 /* we end up here if we couldn't fetch any firmware */ 2158 2159 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2160 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2161 ret); 2162 2163 return ret; 2164 2165 success: 2166 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2167 2168 return 0; 2169 } 2170 2171 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2172 { 2173 int ret; 2174 2175 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2176 if (ret == 0) { 2177 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2178 goto success; 2179 } else if (ret == -EPROBE_DEFER) { 2180 return ret; 2181 } 2182 2183 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2184 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2185 ret); 2186 2187 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2188 if (ret == 0) { 2189 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2190 goto success; 2191 } 2192 2193 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2194 "boot did not find a pre calibration file, try DT next: %d\n", 2195 ret); 2196 2197 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2198 if (ret) { 2199 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2200 "unable to load pre cal data from DT: %d\n", ret); 2201 return ret; 2202 } 2203 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2204 2205 success: 2206 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2207 ath10k_cal_mode_str(ar->cal_mode)); 2208 2209 return 0; 2210 } 2211 2212 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2213 { 2214 int ret; 2215 2216 ret = ath10k_core_pre_cal_download(ar); 2217 if (ret) { 2218 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2219 "failed to load pre cal data: %d\n", ret); 2220 return ret; 2221 } 2222 2223 ret = ath10k_core_get_board_id_from_otp(ar); 2224 if (ret) { 2225 ath10k_err(ar, "failed to get board id: %d\n", ret); 2226 return ret; 2227 } 2228 2229 ret = ath10k_download_and_run_otp(ar); 2230 if (ret) { 2231 ath10k_err(ar, "failed to run otp: %d\n", ret); 2232 return ret; 2233 } 2234 2235 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2236 "pre cal configuration done successfully\n"); 2237 2238 return 0; 2239 } 2240 2241 static int ath10k_download_cal_data(struct ath10k *ar) 2242 { 2243 int ret; 2244 2245 ret = ath10k_core_pre_cal_config(ar); 2246 if (ret == 0) 2247 return 0; 2248 2249 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2250 "pre cal download procedure failed, try cal file: %d\n", 2251 ret); 2252 2253 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2254 if (ret == 0) { 2255 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2256 goto done; 2257 } else if (ret == -EPROBE_DEFER) { 2258 return ret; 2259 } 2260 2261 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2262 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2263 ret); 2264 2265 ret = ath10k_download_cal_file(ar, ar->cal_file); 2266 if (ret == 0) { 2267 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2268 goto done; 2269 } 2270 2271 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2272 "boot did not find a calibration file, try DT next: %d\n", 2273 ret); 2274 2275 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2276 if (ret == 0) { 2277 ar->cal_mode = ATH10K_CAL_MODE_DT; 2278 goto done; 2279 } 2280 2281 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2282 "boot did not find DT entry, try target EEPROM next: %d\n", 2283 ret); 2284 2285 ret = ath10k_download_cal_eeprom(ar); 2286 if (ret == 0) { 2287 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2288 goto done; 2289 } 2290 2291 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2292 "boot did not find target EEPROM entry, try OTP next: %d\n", 2293 ret); 2294 2295 ret = ath10k_download_and_run_otp(ar); 2296 if (ret) { 2297 ath10k_err(ar, "failed to run otp: %d\n", ret); 2298 return ret; 2299 } 2300 2301 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2302 2303 done: 2304 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2305 ath10k_cal_mode_str(ar->cal_mode)); 2306 return 0; 2307 } 2308 2309 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2310 { 2311 struct device_node *node; 2312 u8 coex_support = 0; 2313 int ret; 2314 2315 node = ar->dev->of_node; 2316 if (!node) 2317 goto out; 2318 2319 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2320 if (ret) { 2321 ar->coex_support = true; 2322 goto out; 2323 } 2324 2325 if (coex_support) { 2326 ar->coex_support = true; 2327 } else { 2328 ar->coex_support = false; 2329 ar->coex_gpio_pin = -1; 2330 goto out; 2331 } 2332 2333 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2334 &ar->coex_gpio_pin); 2335 if (ret) 2336 ar->coex_gpio_pin = -1; 2337 2338 out: 2339 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2340 ar->coex_support, ar->coex_gpio_pin); 2341 } 2342 2343 static int ath10k_init_uart(struct ath10k *ar) 2344 { 2345 int ret; 2346 2347 /* 2348 * Explicitly setting UART prints to zero as target turns it on 2349 * based on scratch registers. 2350 */ 2351 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2352 if (ret) { 2353 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2354 return ret; 2355 } 2356 2357 if (!uart_print) { 2358 if (ar->hw_params.uart_pin_workaround) { 2359 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2360 ar->hw_params.uart_pin); 2361 if (ret) { 2362 ath10k_warn(ar, "failed to set UART TX pin: %d", 2363 ret); 2364 return ret; 2365 } 2366 } 2367 2368 return 0; 2369 } 2370 2371 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2372 if (ret) { 2373 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2374 return ret; 2375 } 2376 2377 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2378 if (ret) { 2379 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2380 return ret; 2381 } 2382 2383 /* Set the UART baud rate to 19200. */ 2384 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2385 if (ret) { 2386 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2387 return ret; 2388 } 2389 2390 ath10k_info(ar, "UART prints enabled\n"); 2391 return 0; 2392 } 2393 2394 static int ath10k_init_hw_params(struct ath10k *ar) 2395 { 2396 const struct ath10k_hw_params *hw_params; 2397 int i; 2398 2399 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2400 hw_params = &ath10k_hw_params_list[i]; 2401 2402 if (hw_params->bus == ar->hif.bus && 2403 hw_params->id == ar->target_version && 2404 hw_params->dev_id == ar->dev_id) 2405 break; 2406 } 2407 2408 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2409 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2410 ar->target_version); 2411 return -EINVAL; 2412 } 2413 2414 ar->hw_params = *hw_params; 2415 2416 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2417 ar->hw_params.name, ar->target_version); 2418 2419 return 0; 2420 } 2421 2422 void ath10k_core_start_recovery(struct ath10k *ar) 2423 { 2424 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2425 ath10k_warn(ar, "already restarting\n"); 2426 return; 2427 } 2428 2429 queue_work(ar->workqueue, &ar->restart_work); 2430 } 2431 EXPORT_SYMBOL(ath10k_core_start_recovery); 2432 2433 void ath10k_core_napi_enable(struct ath10k *ar) 2434 { 2435 lockdep_assert_held(&ar->conf_mutex); 2436 2437 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2438 return; 2439 2440 napi_enable(&ar->napi); 2441 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2442 } 2443 EXPORT_SYMBOL(ath10k_core_napi_enable); 2444 2445 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2446 { 2447 lockdep_assert_held(&ar->conf_mutex); 2448 2449 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2450 return; 2451 2452 napi_synchronize(&ar->napi); 2453 napi_disable(&ar->napi); 2454 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2455 } 2456 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2457 2458 static void ath10k_core_restart(struct work_struct *work) 2459 { 2460 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2461 struct ath10k_vif *arvif; 2462 int ret; 2463 2464 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2465 2466 /* Place a barrier to make sure the compiler doesn't reorder 2467 * CRASH_FLUSH and calling other functions. 2468 */ 2469 barrier(); 2470 2471 ieee80211_stop_queues(ar->hw); 2472 ath10k_drain_tx(ar); 2473 complete(&ar->scan.started); 2474 complete(&ar->scan.completed); 2475 complete(&ar->scan.on_channel); 2476 complete(&ar->offchan_tx_completed); 2477 complete(&ar->install_key_done); 2478 complete(&ar->vdev_setup_done); 2479 complete(&ar->vdev_delete_done); 2480 complete(&ar->thermal.wmi_sync); 2481 complete(&ar->bss_survey_done); 2482 wake_up(&ar->htt.empty_tx_wq); 2483 wake_up(&ar->wmi.tx_credits_wq); 2484 wake_up(&ar->peer_mapping_wq); 2485 2486 /* TODO: We can have one instance of cancelling coverage_class_work by 2487 * moving it to ath10k_halt(), so that both stop() and restart() would 2488 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2489 * with conf_mutex it will deadlock. 2490 */ 2491 cancel_work_sync(&ar->set_coverage_class_work); 2492 2493 mutex_lock(&ar->conf_mutex); 2494 2495 switch (ar->state) { 2496 case ATH10K_STATE_ON: 2497 ar->state = ATH10K_STATE_RESTARTING; 2498 ath10k_halt(ar); 2499 ath10k_scan_finish(ar); 2500 if (ar->hw_params.hw_restart_disconnect) { 2501 list_for_each_entry(arvif, &ar->arvifs, list) { 2502 if (arvif->is_up && 2503 arvif->vdev_type == WMI_VDEV_TYPE_STA) 2504 ieee80211_hw_restart_disconnect(arvif->vif); 2505 } 2506 } 2507 2508 ieee80211_restart_hw(ar->hw); 2509 break; 2510 case ATH10K_STATE_OFF: 2511 /* this can happen if driver is being unloaded 2512 * or if the crash happens during FW probing 2513 */ 2514 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2515 break; 2516 case ATH10K_STATE_RESTARTING: 2517 /* hw restart might be requested from multiple places */ 2518 break; 2519 case ATH10K_STATE_RESTARTED: 2520 ar->state = ATH10K_STATE_WEDGED; 2521 fallthrough; 2522 case ATH10K_STATE_WEDGED: 2523 ath10k_warn(ar, "device is wedged, will not restart\n"); 2524 break; 2525 case ATH10K_STATE_UTF: 2526 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2527 break; 2528 } 2529 2530 mutex_unlock(&ar->conf_mutex); 2531 2532 ret = ath10k_coredump_submit(ar); 2533 if (ret) 2534 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2535 ret); 2536 2537 complete(&ar->driver_recovery); 2538 } 2539 2540 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2541 { 2542 struct ath10k *ar = container_of(work, struct ath10k, 2543 set_coverage_class_work); 2544 2545 if (ar->hw_params.hw_ops->set_coverage_class) 2546 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2547 } 2548 2549 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2550 { 2551 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2552 int max_num_peers; 2553 2554 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2555 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2556 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2557 return -EINVAL; 2558 } 2559 2560 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2561 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2562 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2563 return -EINVAL; 2564 } 2565 2566 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2567 switch (ath10k_cryptmode_param) { 2568 case ATH10K_CRYPT_MODE_HW: 2569 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2570 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2571 break; 2572 case ATH10K_CRYPT_MODE_SW: 2573 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2574 fw_file->fw_features)) { 2575 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2576 return -EINVAL; 2577 } 2578 2579 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2580 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2581 break; 2582 default: 2583 ath10k_info(ar, "invalid cryptmode: %d\n", 2584 ath10k_cryptmode_param); 2585 return -EINVAL; 2586 } 2587 2588 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2589 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2590 2591 if (rawmode) { 2592 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2593 fw_file->fw_features)) { 2594 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2595 return -EINVAL; 2596 } 2597 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2598 } 2599 2600 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2601 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2602 2603 /* Workaround: 2604 * 2605 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2606 * and causes enormous performance issues (malformed frames, 2607 * etc). 2608 * 2609 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2610 * albeit a bit slower compared to regular operation. 2611 */ 2612 ar->htt.max_num_amsdu = 1; 2613 } 2614 2615 /* Backwards compatibility for firmwares without 2616 * ATH10K_FW_IE_WMI_OP_VERSION. 2617 */ 2618 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2619 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2620 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2621 fw_file->fw_features)) 2622 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2623 else 2624 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2625 } else { 2626 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2627 } 2628 } 2629 2630 switch (fw_file->wmi_op_version) { 2631 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2632 max_num_peers = TARGET_NUM_PEERS; 2633 ar->max_num_stations = TARGET_NUM_STATIONS; 2634 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2635 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2636 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2637 WMI_STAT_PEER; 2638 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2639 break; 2640 case ATH10K_FW_WMI_OP_VERSION_10_1: 2641 case ATH10K_FW_WMI_OP_VERSION_10_2: 2642 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2643 if (ath10k_peer_stats_enabled(ar)) { 2644 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2645 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2646 } else { 2647 max_num_peers = TARGET_10X_NUM_PEERS; 2648 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2649 } 2650 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2651 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2652 ar->fw_stats_req_mask = WMI_STAT_PEER; 2653 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2654 break; 2655 case ATH10K_FW_WMI_OP_VERSION_TLV: 2656 max_num_peers = TARGET_TLV_NUM_PEERS; 2657 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2658 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2659 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2660 if (ar->hif.bus == ATH10K_BUS_SDIO) 2661 ar->htt.max_num_pending_tx = 2662 TARGET_TLV_NUM_MSDU_DESC_HL; 2663 else 2664 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2665 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2666 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2667 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2668 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2669 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2670 break; 2671 case ATH10K_FW_WMI_OP_VERSION_10_4: 2672 max_num_peers = TARGET_10_4_NUM_PEERS; 2673 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2674 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2675 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2676 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2677 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2678 WMI_10_4_STAT_PEER_EXTD | 2679 WMI_10_4_STAT_VDEV_EXTD; 2680 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2681 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2682 2683 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2684 fw_file->fw_features)) 2685 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2686 else 2687 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2688 break; 2689 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2690 case ATH10K_FW_WMI_OP_VERSION_MAX: 2691 default: 2692 WARN_ON(1); 2693 return -EINVAL; 2694 } 2695 2696 if (ar->hw_params.num_peers) 2697 ar->max_num_peers = ar->hw_params.num_peers; 2698 else 2699 ar->max_num_peers = max_num_peers; 2700 2701 /* Backwards compatibility for firmwares without 2702 * ATH10K_FW_IE_HTT_OP_VERSION. 2703 */ 2704 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2705 switch (fw_file->wmi_op_version) { 2706 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2707 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2708 break; 2709 case ATH10K_FW_WMI_OP_VERSION_10_1: 2710 case ATH10K_FW_WMI_OP_VERSION_10_2: 2711 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2712 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2713 break; 2714 case ATH10K_FW_WMI_OP_VERSION_TLV: 2715 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2716 break; 2717 case ATH10K_FW_WMI_OP_VERSION_10_4: 2718 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2719 case ATH10K_FW_WMI_OP_VERSION_MAX: 2720 ath10k_err(ar, "htt op version not found from fw meta data"); 2721 return -EINVAL; 2722 } 2723 } 2724 2725 return 0; 2726 } 2727 2728 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2729 { 2730 int ret; 2731 int vdev_id; 2732 int vdev_type; 2733 int vdev_subtype; 2734 const u8 *vdev_addr; 2735 2736 vdev_id = 0; 2737 vdev_type = WMI_VDEV_TYPE_STA; 2738 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2739 vdev_addr = ar->mac_addr; 2740 2741 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2742 vdev_addr); 2743 if (ret) { 2744 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2745 return ret; 2746 } 2747 2748 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2749 if (ret) { 2750 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2751 return ret; 2752 } 2753 2754 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2755 * serialized properly implicitly. 2756 * 2757 * Moreover (most) WMI commands have no explicit acknowledges. It is 2758 * possible to infer it implicitly by poking firmware with echo 2759 * command - getting a reply means all preceding comments have been 2760 * (mostly) processed. 2761 * 2762 * In case of vdev create/delete this is sufficient. 2763 * 2764 * Without this it's possible to end up with a race when HTT Rx ring is 2765 * started before vdev create/delete hack is complete allowing a short 2766 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2767 */ 2768 ret = ath10k_wmi_barrier(ar); 2769 if (ret) { 2770 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2771 return ret; 2772 } 2773 2774 return 0; 2775 } 2776 2777 static int ath10k_core_compat_services(struct ath10k *ar) 2778 { 2779 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2780 2781 /* all 10.x firmware versions support thermal throttling but don't 2782 * advertise the support via service flags so we have to hardcode 2783 * it here 2784 */ 2785 switch (fw_file->wmi_op_version) { 2786 case ATH10K_FW_WMI_OP_VERSION_10_1: 2787 case ATH10K_FW_WMI_OP_VERSION_10_2: 2788 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2789 case ATH10K_FW_WMI_OP_VERSION_10_4: 2790 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2791 break; 2792 default: 2793 break; 2794 } 2795 2796 return 0; 2797 } 2798 2799 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2800 2801 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2802 { 2803 const struct ath10k_hw_mem_layout *hw_mem; 2804 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2805 dma_addr_t paddr; 2806 void *vaddr = NULL; 2807 u8 num_read_itr; 2808 int i, ret; 2809 u32 len, remaining_len; 2810 2811 /* copy target iram feature must work also when 2812 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2813 * _ath10k_coredump_get_mem_layout() to accomplist that 2814 */ 2815 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2816 if (!hw_mem) 2817 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2818 * just silently disable the feature by doing nothing 2819 */ 2820 return 0; 2821 2822 for (i = 0; i < hw_mem->region_table.size; i++) { 2823 tmp = &hw_mem->region_table.regions[i]; 2824 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2825 mem_region = tmp; 2826 break; 2827 } 2828 } 2829 2830 if (!mem_region) 2831 return -ENOMEM; 2832 2833 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2834 if (ar->wmi.mem_chunks[i].req_id == 2835 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2836 vaddr = ar->wmi.mem_chunks[i].vaddr; 2837 len = ar->wmi.mem_chunks[i].len; 2838 break; 2839 } 2840 } 2841 2842 if (!vaddr || !len) { 2843 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2844 return -ENOMEM; 2845 } 2846 2847 len = (len < mem_region->len) ? len : mem_region->len; 2848 paddr = mem_region->start; 2849 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2850 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2851 for (i = 0; i < num_read_itr; i++) { 2852 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2853 TGT_IRAM_READ_PER_ITR); 2854 if (ret) { 2855 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2856 ret); 2857 return ret; 2858 } 2859 2860 paddr += TGT_IRAM_READ_PER_ITR; 2861 vaddr += TGT_IRAM_READ_PER_ITR; 2862 } 2863 2864 if (remaining_len) { 2865 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2866 if (ret) { 2867 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2868 ret); 2869 return ret; 2870 } 2871 } 2872 2873 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2874 2875 return 0; 2876 } 2877 2878 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2879 const struct ath10k_fw_components *fw) 2880 { 2881 int status; 2882 u32 val; 2883 2884 lockdep_assert_held(&ar->conf_mutex); 2885 2886 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2887 2888 ar->running_fw = fw; 2889 2890 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2891 ar->running_fw->fw_file.fw_features)) { 2892 ath10k_bmi_start(ar); 2893 2894 /* Enable hardware clock to speed up firmware download */ 2895 if (ar->hw_params.hw_ops->enable_pll_clk) { 2896 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2897 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2898 status); 2899 } 2900 2901 if (ath10k_init_configure_target(ar)) { 2902 status = -EINVAL; 2903 goto err; 2904 } 2905 2906 status = ath10k_download_cal_data(ar); 2907 if (status) 2908 goto err; 2909 2910 /* Some of qca988x solutions are having global reset issue 2911 * during target initialization. Bypassing PLL setting before 2912 * downloading firmware and letting the SoC run on REF_CLK is 2913 * fixing the problem. Corresponding firmware change is also 2914 * needed to set the clock source once the target is 2915 * initialized. 2916 */ 2917 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2918 ar->running_fw->fw_file.fw_features)) { 2919 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2920 if (status) { 2921 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2922 status); 2923 goto err; 2924 } 2925 } 2926 2927 status = ath10k_download_fw(ar); 2928 if (status) 2929 goto err; 2930 2931 status = ath10k_init_uart(ar); 2932 if (status) 2933 goto err; 2934 2935 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2936 status = ath10k_init_sdio(ar, mode); 2937 if (status) { 2938 ath10k_err(ar, "failed to init SDIO: %d\n", status); 2939 goto err; 2940 } 2941 } 2942 } 2943 2944 ar->htc.htc_ops.target_send_suspend_complete = 2945 ath10k_send_suspend_complete; 2946 2947 status = ath10k_htc_init(ar); 2948 if (status) { 2949 ath10k_err(ar, "could not init HTC (%d)\n", status); 2950 goto err; 2951 } 2952 2953 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2954 ar->running_fw->fw_file.fw_features)) { 2955 status = ath10k_bmi_done(ar); 2956 if (status) 2957 goto err; 2958 } 2959 2960 status = ath10k_wmi_attach(ar); 2961 if (status) { 2962 ath10k_err(ar, "WMI attach failed: %d\n", status); 2963 goto err; 2964 } 2965 2966 status = ath10k_htt_init(ar); 2967 if (status) { 2968 ath10k_err(ar, "failed to init htt: %d\n", status); 2969 goto err_wmi_detach; 2970 } 2971 2972 status = ath10k_htt_tx_start(&ar->htt); 2973 if (status) { 2974 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 2975 goto err_wmi_detach; 2976 } 2977 2978 /* If firmware indicates Full Rx Reorder support it must be used in a 2979 * slightly different manner. Let HTT code know. 2980 */ 2981 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 2982 ar->wmi.svc_map)); 2983 2984 status = ath10k_htt_rx_alloc(&ar->htt); 2985 if (status) { 2986 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 2987 goto err_htt_tx_detach; 2988 } 2989 2990 status = ath10k_hif_start(ar); 2991 if (status) { 2992 ath10k_err(ar, "could not start HIF: %d\n", status); 2993 goto err_htt_rx_detach; 2994 } 2995 2996 status = ath10k_htc_wait_target(&ar->htc); 2997 if (status) { 2998 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 2999 goto err_hif_stop; 3000 } 3001 3002 status = ath10k_hif_start_post(ar); 3003 if (status) { 3004 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3005 goto err_hif_stop; 3006 } 3007 3008 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3009 status = ath10k_htt_connect(&ar->htt); 3010 if (status) { 3011 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3012 goto err_hif_stop; 3013 } 3014 } 3015 3016 status = ath10k_wmi_connect(ar); 3017 if (status) { 3018 ath10k_err(ar, "could not connect wmi: %d\n", status); 3019 goto err_hif_stop; 3020 } 3021 3022 status = ath10k_htc_start(&ar->htc); 3023 if (status) { 3024 ath10k_err(ar, "failed to start htc: %d\n", status); 3025 goto err_hif_stop; 3026 } 3027 3028 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3029 status = ath10k_wmi_wait_for_service_ready(ar); 3030 if (status) { 3031 ath10k_warn(ar, "wmi service ready event not received"); 3032 goto err_hif_stop; 3033 } 3034 } 3035 3036 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3037 ar->hw->wiphy->fw_version); 3038 3039 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3040 ar->running_fw->fw_file.fw_features)) { 3041 status = ath10k_core_copy_target_iram(ar); 3042 if (status) { 3043 ath10k_warn(ar, "failed to copy target iram contents: %d", 3044 status); 3045 goto err_hif_stop; 3046 } 3047 } 3048 3049 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3050 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3051 val = 0; 3052 if (ath10k_peer_stats_enabled(ar)) 3053 val = WMI_10_4_PEER_STATS; 3054 3055 /* Enable vdev stats by default */ 3056 val |= WMI_10_4_VDEV_STATS; 3057 3058 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3059 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3060 3061 ath10k_core_fetch_btcoex_dt(ar); 3062 3063 /* 10.4 firmware supports BT-Coex without reloading firmware 3064 * via pdev param. To support Bluetooth coexistence pdev param, 3065 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3066 * enabled always. 3067 * 3068 * We can still enable BTCOEX if firmware has the support 3069 * eventhough btceox_support value is 3070 * ATH10K_DT_BTCOEX_NOT_FOUND 3071 */ 3072 3073 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3074 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3075 ar->running_fw->fw_file.fw_features) && 3076 ar->coex_support) 3077 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3078 3079 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3080 ar->wmi.svc_map)) 3081 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3082 3083 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3084 ar->wmi.svc_map)) 3085 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3086 3087 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3088 ar->wmi.svc_map)) 3089 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3090 3091 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3092 val |= WMI_10_4_REPORT_AIRTIME; 3093 3094 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3095 ar->wmi.svc_map)) 3096 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3097 3098 status = ath10k_mac_ext_resource_config(ar, val); 3099 if (status) { 3100 ath10k_err(ar, 3101 "failed to send ext resource cfg command : %d\n", 3102 status); 3103 goto err_hif_stop; 3104 } 3105 } 3106 3107 status = ath10k_wmi_cmd_init(ar); 3108 if (status) { 3109 ath10k_err(ar, "could not send WMI init command (%d)\n", 3110 status); 3111 goto err_hif_stop; 3112 } 3113 3114 status = ath10k_wmi_wait_for_unified_ready(ar); 3115 if (status) { 3116 ath10k_err(ar, "wmi unified ready event not received\n"); 3117 goto err_hif_stop; 3118 } 3119 3120 status = ath10k_core_compat_services(ar); 3121 if (status) { 3122 ath10k_err(ar, "compat services failed: %d\n", status); 3123 goto err_hif_stop; 3124 } 3125 3126 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3127 if (status && status != -EOPNOTSUPP) { 3128 ath10k_err(ar, 3129 "failed to set base mac address: %d\n", status); 3130 goto err_hif_stop; 3131 } 3132 3133 /* Some firmware revisions do not properly set up hardware rx filter 3134 * registers. 3135 * 3136 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3137 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3138 * any frames that matches MAC_PCU_RX_FILTER which is also 3139 * misconfigured to accept anything. 3140 * 3141 * The ADDR1 is programmed using internal firmware structure field and 3142 * can't be (easily/sanely) reached from the driver explicitly. It is 3143 * possible to implicitly make it correct by creating a dummy vdev and 3144 * then deleting it. 3145 */ 3146 if (ar->hw_params.hw_filter_reset_required && 3147 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3148 status = ath10k_core_reset_rx_filter(ar); 3149 if (status) { 3150 ath10k_err(ar, 3151 "failed to reset rx filter: %d\n", status); 3152 goto err_hif_stop; 3153 } 3154 } 3155 3156 status = ath10k_htt_rx_ring_refill(ar); 3157 if (status) { 3158 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3159 goto err_hif_stop; 3160 } 3161 3162 if (ar->max_num_vdevs >= 64) 3163 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3164 else 3165 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3166 3167 INIT_LIST_HEAD(&ar->arvifs); 3168 3169 /* we don't care about HTT in UTF mode */ 3170 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3171 status = ath10k_htt_setup(&ar->htt); 3172 if (status) { 3173 ath10k_err(ar, "failed to setup htt: %d\n", status); 3174 goto err_hif_stop; 3175 } 3176 } 3177 3178 status = ath10k_debug_start(ar); 3179 if (status) 3180 goto err_hif_stop; 3181 3182 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3183 if (status && status != -EOPNOTSUPP) { 3184 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3185 goto err_hif_stop; 3186 } 3187 3188 return 0; 3189 3190 err_hif_stop: 3191 ath10k_hif_stop(ar); 3192 err_htt_rx_detach: 3193 ath10k_htt_rx_free(&ar->htt); 3194 err_htt_tx_detach: 3195 ath10k_htt_tx_free(&ar->htt); 3196 err_wmi_detach: 3197 ath10k_wmi_detach(ar); 3198 err: 3199 return status; 3200 } 3201 EXPORT_SYMBOL(ath10k_core_start); 3202 3203 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3204 { 3205 int ret; 3206 unsigned long time_left; 3207 3208 reinit_completion(&ar->target_suspend); 3209 3210 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3211 if (ret) { 3212 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3213 return ret; 3214 } 3215 3216 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3217 3218 if (!time_left) { 3219 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3220 return -ETIMEDOUT; 3221 } 3222 3223 return 0; 3224 } 3225 3226 void ath10k_core_stop(struct ath10k *ar) 3227 { 3228 lockdep_assert_held(&ar->conf_mutex); 3229 ath10k_debug_stop(ar); 3230 3231 /* try to suspend target */ 3232 if (ar->state != ATH10K_STATE_RESTARTING && 3233 ar->state != ATH10K_STATE_UTF) 3234 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3235 3236 ath10k_hif_stop(ar); 3237 ath10k_htt_tx_stop(&ar->htt); 3238 ath10k_htt_rx_free(&ar->htt); 3239 ath10k_wmi_detach(ar); 3240 3241 ar->id.bmi_ids_valid = false; 3242 } 3243 EXPORT_SYMBOL(ath10k_core_stop); 3244 3245 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3246 * order to know what hw capabilities should be advertised to mac80211 it is 3247 * necessary to load the firmware (and tear it down immediately since start 3248 * hook will try to init it again) before registering 3249 */ 3250 static int ath10k_core_probe_fw(struct ath10k *ar) 3251 { 3252 struct bmi_target_info target_info; 3253 int ret = 0; 3254 3255 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3256 if (ret) { 3257 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3258 return ret; 3259 } 3260 3261 switch (ar->hif.bus) { 3262 case ATH10K_BUS_SDIO: 3263 memset(&target_info, 0, sizeof(target_info)); 3264 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3265 if (ret) { 3266 ath10k_err(ar, "could not get target info (%d)\n", ret); 3267 goto err_power_down; 3268 } 3269 ar->target_version = target_info.version; 3270 ar->hw->wiphy->hw_version = target_info.version; 3271 break; 3272 case ATH10K_BUS_PCI: 3273 case ATH10K_BUS_AHB: 3274 case ATH10K_BUS_USB: 3275 memset(&target_info, 0, sizeof(target_info)); 3276 ret = ath10k_bmi_get_target_info(ar, &target_info); 3277 if (ret) { 3278 ath10k_err(ar, "could not get target info (%d)\n", ret); 3279 goto err_power_down; 3280 } 3281 ar->target_version = target_info.version; 3282 ar->hw->wiphy->hw_version = target_info.version; 3283 break; 3284 case ATH10K_BUS_SNOC: 3285 memset(&target_info, 0, sizeof(target_info)); 3286 ret = ath10k_hif_get_target_info(ar, &target_info); 3287 if (ret) { 3288 ath10k_err(ar, "could not get target info (%d)\n", ret); 3289 goto err_power_down; 3290 } 3291 ar->target_version = target_info.version; 3292 ar->hw->wiphy->hw_version = target_info.version; 3293 break; 3294 default: 3295 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3296 } 3297 3298 ret = ath10k_init_hw_params(ar); 3299 if (ret) { 3300 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3301 goto err_power_down; 3302 } 3303 3304 ret = ath10k_core_fetch_firmware_files(ar); 3305 if (ret) { 3306 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3307 goto err_power_down; 3308 } 3309 3310 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3311 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3312 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3313 sizeof(ar->hw->wiphy->fw_version)); 3314 3315 ath10k_debug_print_hwfw_info(ar); 3316 3317 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3318 ar->normal_mode_fw.fw_file.fw_features)) { 3319 ret = ath10k_core_pre_cal_download(ar); 3320 if (ret) { 3321 /* pre calibration data download is not necessary 3322 * for all the chipsets. Ignore failures and continue. 3323 */ 3324 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3325 "could not load pre cal data: %d\n", ret); 3326 } 3327 3328 ret = ath10k_core_get_board_id_from_otp(ar); 3329 if (ret && ret != -EOPNOTSUPP) { 3330 ath10k_err(ar, "failed to get board id from otp: %d\n", 3331 ret); 3332 goto err_free_firmware_files; 3333 } 3334 3335 ret = ath10k_core_check_smbios(ar); 3336 if (ret) 3337 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3338 3339 ret = ath10k_core_check_dt(ar); 3340 if (ret) 3341 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3342 3343 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3344 if (ret) { 3345 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3346 goto err_free_firmware_files; 3347 } 3348 3349 ath10k_debug_print_board_info(ar); 3350 } 3351 3352 device_get_mac_address(ar->dev, ar->mac_addr); 3353 3354 ret = ath10k_core_init_firmware_features(ar); 3355 if (ret) { 3356 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3357 ret); 3358 goto err_free_firmware_files; 3359 } 3360 3361 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3362 ar->normal_mode_fw.fw_file.fw_features)) { 3363 ret = ath10k_swap_code_seg_init(ar, 3364 &ar->normal_mode_fw.fw_file); 3365 if (ret) { 3366 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3367 ret); 3368 goto err_free_firmware_files; 3369 } 3370 } 3371 3372 mutex_lock(&ar->conf_mutex); 3373 3374 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3375 &ar->normal_mode_fw); 3376 if (ret) { 3377 ath10k_err(ar, "could not init core (%d)\n", ret); 3378 goto err_unlock; 3379 } 3380 3381 ath10k_debug_print_boot_info(ar); 3382 ath10k_core_stop(ar); 3383 3384 mutex_unlock(&ar->conf_mutex); 3385 3386 ath10k_hif_power_down(ar); 3387 return 0; 3388 3389 err_unlock: 3390 mutex_unlock(&ar->conf_mutex); 3391 3392 err_free_firmware_files: 3393 ath10k_core_free_firmware_files(ar); 3394 3395 err_power_down: 3396 ath10k_hif_power_down(ar); 3397 3398 return ret; 3399 } 3400 3401 static void ath10k_core_register_work(struct work_struct *work) 3402 { 3403 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3404 int status; 3405 3406 /* peer stats are enabled by default */ 3407 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3408 3409 status = ath10k_core_probe_fw(ar); 3410 if (status) { 3411 ath10k_err(ar, "could not probe fw (%d)\n", status); 3412 goto err; 3413 } 3414 3415 status = ath10k_mac_register(ar); 3416 if (status) { 3417 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3418 goto err_release_fw; 3419 } 3420 3421 status = ath10k_coredump_register(ar); 3422 if (status) { 3423 ath10k_err(ar, "unable to register coredump\n"); 3424 goto err_unregister_mac; 3425 } 3426 3427 status = ath10k_debug_register(ar); 3428 if (status) { 3429 ath10k_err(ar, "unable to initialize debugfs\n"); 3430 goto err_unregister_coredump; 3431 } 3432 3433 status = ath10k_spectral_create(ar); 3434 if (status) { 3435 ath10k_err(ar, "failed to initialize spectral\n"); 3436 goto err_debug_destroy; 3437 } 3438 3439 status = ath10k_thermal_register(ar); 3440 if (status) { 3441 ath10k_err(ar, "could not register thermal device: %d\n", 3442 status); 3443 goto err_spectral_destroy; 3444 } 3445 3446 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3447 return; 3448 3449 err_spectral_destroy: 3450 ath10k_spectral_destroy(ar); 3451 err_debug_destroy: 3452 ath10k_debug_destroy(ar); 3453 err_unregister_coredump: 3454 ath10k_coredump_unregister(ar); 3455 err_unregister_mac: 3456 ath10k_mac_unregister(ar); 3457 err_release_fw: 3458 ath10k_core_free_firmware_files(ar); 3459 err: 3460 /* TODO: It's probably a good idea to release device from the driver 3461 * but calling device_release_driver() here will cause a deadlock. 3462 */ 3463 return; 3464 } 3465 3466 int ath10k_core_register(struct ath10k *ar, 3467 const struct ath10k_bus_params *bus_params) 3468 { 3469 ar->bus_param = *bus_params; 3470 3471 queue_work(ar->workqueue, &ar->register_work); 3472 3473 return 0; 3474 } 3475 EXPORT_SYMBOL(ath10k_core_register); 3476 3477 void ath10k_core_unregister(struct ath10k *ar) 3478 { 3479 cancel_work_sync(&ar->register_work); 3480 3481 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3482 return; 3483 3484 ath10k_thermal_unregister(ar); 3485 /* Stop spectral before unregistering from mac80211 to remove the 3486 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3487 * would be already be free'd recursively, leading to a double free. 3488 */ 3489 ath10k_spectral_destroy(ar); 3490 3491 /* We must unregister from mac80211 before we stop HTC and HIF. 3492 * Otherwise we will fail to submit commands to FW and mac80211 will be 3493 * unhappy about callback failures. 3494 */ 3495 ath10k_mac_unregister(ar); 3496 3497 ath10k_testmode_destroy(ar); 3498 3499 ath10k_core_free_firmware_files(ar); 3500 ath10k_core_free_board_files(ar); 3501 3502 ath10k_debug_unregister(ar); 3503 } 3504 EXPORT_SYMBOL(ath10k_core_unregister); 3505 3506 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3507 enum ath10k_bus bus, 3508 enum ath10k_hw_rev hw_rev, 3509 const struct ath10k_hif_ops *hif_ops) 3510 { 3511 struct ath10k *ar; 3512 int ret; 3513 3514 ar = ath10k_mac_create(priv_size); 3515 if (!ar) 3516 return NULL; 3517 3518 ar->ath_common.priv = ar; 3519 ar->ath_common.hw = ar->hw; 3520 ar->dev = dev; 3521 ar->hw_rev = hw_rev; 3522 ar->hif.ops = hif_ops; 3523 ar->hif.bus = bus; 3524 3525 switch (hw_rev) { 3526 case ATH10K_HW_QCA988X: 3527 case ATH10K_HW_QCA9887: 3528 ar->regs = &qca988x_regs; 3529 ar->hw_ce_regs = &qcax_ce_regs; 3530 ar->hw_values = &qca988x_values; 3531 break; 3532 case ATH10K_HW_QCA6174: 3533 case ATH10K_HW_QCA9377: 3534 ar->regs = &qca6174_regs; 3535 ar->hw_ce_regs = &qcax_ce_regs; 3536 ar->hw_values = &qca6174_values; 3537 break; 3538 case ATH10K_HW_QCA99X0: 3539 case ATH10K_HW_QCA9984: 3540 ar->regs = &qca99x0_regs; 3541 ar->hw_ce_regs = &qcax_ce_regs; 3542 ar->hw_values = &qca99x0_values; 3543 break; 3544 case ATH10K_HW_QCA9888: 3545 ar->regs = &qca99x0_regs; 3546 ar->hw_ce_regs = &qcax_ce_regs; 3547 ar->hw_values = &qca9888_values; 3548 break; 3549 case ATH10K_HW_QCA4019: 3550 ar->regs = &qca4019_regs; 3551 ar->hw_ce_regs = &qcax_ce_regs; 3552 ar->hw_values = &qca4019_values; 3553 break; 3554 case ATH10K_HW_WCN3990: 3555 ar->regs = &wcn3990_regs; 3556 ar->hw_ce_regs = &wcn3990_ce_regs; 3557 ar->hw_values = &wcn3990_values; 3558 break; 3559 default: 3560 ath10k_err(ar, "unsupported core hardware revision %d\n", 3561 hw_rev); 3562 ret = -ENOTSUPP; 3563 goto err_free_mac; 3564 } 3565 3566 init_completion(&ar->scan.started); 3567 init_completion(&ar->scan.completed); 3568 init_completion(&ar->scan.on_channel); 3569 init_completion(&ar->target_suspend); 3570 init_completion(&ar->driver_recovery); 3571 init_completion(&ar->wow.wakeup_completed); 3572 3573 init_completion(&ar->install_key_done); 3574 init_completion(&ar->vdev_setup_done); 3575 init_completion(&ar->vdev_delete_done); 3576 init_completion(&ar->thermal.wmi_sync); 3577 init_completion(&ar->bss_survey_done); 3578 init_completion(&ar->peer_delete_done); 3579 init_completion(&ar->peer_stats_info_complete); 3580 3581 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3582 3583 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3584 if (!ar->workqueue) 3585 goto err_free_mac; 3586 3587 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3588 if (!ar->workqueue_aux) 3589 goto err_free_wq; 3590 3591 ar->workqueue_tx_complete = 3592 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3593 if (!ar->workqueue_tx_complete) 3594 goto err_free_aux_wq; 3595 3596 mutex_init(&ar->conf_mutex); 3597 mutex_init(&ar->dump_mutex); 3598 spin_lock_init(&ar->data_lock); 3599 3600 INIT_LIST_HEAD(&ar->peers); 3601 init_waitqueue_head(&ar->peer_mapping_wq); 3602 init_waitqueue_head(&ar->htt.empty_tx_wq); 3603 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3604 3605 skb_queue_head_init(&ar->htt.rx_indication_head); 3606 3607 init_completion(&ar->offchan_tx_completed); 3608 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3609 skb_queue_head_init(&ar->offchan_tx_queue); 3610 3611 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3612 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3613 3614 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3615 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3616 INIT_WORK(&ar->set_coverage_class_work, 3617 ath10k_core_set_coverage_class_work); 3618 3619 init_dummy_netdev(&ar->napi_dev); 3620 3621 ret = ath10k_coredump_create(ar); 3622 if (ret) 3623 goto err_free_tx_complete; 3624 3625 ret = ath10k_debug_create(ar); 3626 if (ret) 3627 goto err_free_coredump; 3628 3629 return ar; 3630 3631 err_free_coredump: 3632 ath10k_coredump_destroy(ar); 3633 err_free_tx_complete: 3634 destroy_workqueue(ar->workqueue_tx_complete); 3635 err_free_aux_wq: 3636 destroy_workqueue(ar->workqueue_aux); 3637 err_free_wq: 3638 destroy_workqueue(ar->workqueue); 3639 err_free_mac: 3640 ath10k_mac_destroy(ar); 3641 3642 return NULL; 3643 } 3644 EXPORT_SYMBOL(ath10k_core_create); 3645 3646 void ath10k_core_destroy(struct ath10k *ar) 3647 { 3648 destroy_workqueue(ar->workqueue); 3649 3650 destroy_workqueue(ar->workqueue_aux); 3651 3652 destroy_workqueue(ar->workqueue_tx_complete); 3653 3654 ath10k_debug_destroy(ar); 3655 ath10k_coredump_destroy(ar); 3656 ath10k_htt_tx_destroy(&ar->htt); 3657 ath10k_wmi_free_host_mem(ar); 3658 ath10k_mac_destroy(ar); 3659 } 3660 EXPORT_SYMBOL(ath10k_core_destroy); 3661 3662 MODULE_AUTHOR("Qualcomm Atheros"); 3663 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3664 MODULE_LICENSE("Dual BSD/GPL"); 3665