1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 #include <linux/property.h> 13 #include <linux/dmi.h> 14 #include <linux/ctype.h> 15 #include <linux/pm_qos.h> 16 #include <linux/nvmem-consumer.h> 17 #include <asm/byteorder.h> 18 19 #include "core.h" 20 #include "mac.h" 21 #include "htc.h" 22 #include "hif.h" 23 #include "wmi.h" 24 #include "bmi.h" 25 #include "debug.h" 26 #include "htt.h" 27 #include "testmode.h" 28 #include "wmi-ops.h" 29 #include "coredump.h" 30 #include "leds.h" 31 32 unsigned int ath10k_debug_mask; 33 EXPORT_SYMBOL(ath10k_debug_mask); 34 35 static unsigned int ath10k_cryptmode_param; 36 static bool uart_print; 37 static bool skip_otp; 38 static bool fw_diag_log; 39 40 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ 41 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 42 43 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 44 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 45 46 /* FIXME: most of these should be readonly */ 47 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 48 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 49 module_param(uart_print, bool, 0644); 50 module_param(skip_otp, bool, 0644); 51 module_param(fw_diag_log, bool, 0644); 52 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); 53 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 54 55 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 56 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 57 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 58 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 59 MODULE_PARM_DESC(frame_mode, 60 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 61 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 62 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 63 64 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 65 { 66 .id = QCA988X_HW_2_0_VERSION, 67 .dev_id = QCA988X_2_0_DEVICE_ID, 68 .bus = ATH10K_BUS_PCI, 69 .name = "qca988x hw2.0", 70 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 71 .uart_pin = 7, 72 .led_pin = 1, 73 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 74 .otp_exe_param = 0, 75 .channel_counters_freq_hz = 88000, 76 .max_probe_resp_desc_thres = 0, 77 .cal_data_len = 2116, 78 .fw = { 79 .dir = QCA988X_HW_2_0_FW_DIR, 80 .board_size = QCA988X_BOARD_DATA_SZ, 81 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 82 }, 83 .rx_desc_ops = &qca988x_rx_desc_ops, 84 .hw_ops = &qca988x_ops, 85 .decap_align_bytes = 4, 86 .spectral_bin_discard = 0, 87 .spectral_bin_offset = 0, 88 .vht160_mcs_rx_highest = 0, 89 .vht160_mcs_tx_highest = 0, 90 .n_cipher_suites = 8, 91 .ast_skid_limit = 0x10, 92 .num_wds_entries = 0x20, 93 .target_64bit = false, 94 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 95 .shadow_reg_support = false, 96 .rri_on_ddr = false, 97 .hw_filter_reset_required = true, 98 .fw_diag_ce_download = false, 99 .credit_size_workaround = false, 100 .tx_stats_over_pktlog = true, 101 .dynamic_sar_support = false, 102 .hw_restart_disconnect = false, 103 .use_fw_tx_credits = true, 104 .delay_unmap_buffer = false, 105 .mcast_frame_registration = false, 106 }, 107 { 108 .id = QCA988X_HW_2_0_VERSION, 109 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 110 .name = "qca988x hw2.0 ubiquiti", 111 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 112 .uart_pin = 7, 113 .led_pin = 0, 114 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 115 .otp_exe_param = 0, 116 .channel_counters_freq_hz = 88000, 117 .max_probe_resp_desc_thres = 0, 118 .cal_data_len = 2116, 119 .fw = { 120 .dir = QCA988X_HW_2_0_FW_DIR, 121 .board_size = QCA988X_BOARD_DATA_SZ, 122 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 123 }, 124 .rx_desc_ops = &qca988x_rx_desc_ops, 125 .hw_ops = &qca988x_ops, 126 .decap_align_bytes = 4, 127 .spectral_bin_discard = 0, 128 .spectral_bin_offset = 0, 129 .vht160_mcs_rx_highest = 0, 130 .vht160_mcs_tx_highest = 0, 131 .n_cipher_suites = 8, 132 .ast_skid_limit = 0x10, 133 .num_wds_entries = 0x20, 134 .target_64bit = false, 135 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 136 .shadow_reg_support = false, 137 .rri_on_ddr = false, 138 .hw_filter_reset_required = true, 139 .fw_diag_ce_download = false, 140 .credit_size_workaround = false, 141 .tx_stats_over_pktlog = true, 142 .dynamic_sar_support = false, 143 .hw_restart_disconnect = false, 144 .use_fw_tx_credits = true, 145 .delay_unmap_buffer = false, 146 .mcast_frame_registration = false, 147 }, 148 { 149 .id = QCA9887_HW_1_0_VERSION, 150 .dev_id = QCA9887_1_0_DEVICE_ID, 151 .bus = ATH10K_BUS_PCI, 152 .name = "qca9887 hw1.0", 153 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 154 .uart_pin = 7, 155 .led_pin = 1, 156 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 157 .otp_exe_param = 0, 158 .channel_counters_freq_hz = 88000, 159 .max_probe_resp_desc_thres = 0, 160 .cal_data_len = 2116, 161 .fw = { 162 .dir = QCA9887_HW_1_0_FW_DIR, 163 .board_size = QCA9887_BOARD_DATA_SZ, 164 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 165 }, 166 .rx_desc_ops = &qca988x_rx_desc_ops, 167 .hw_ops = &qca988x_ops, 168 .decap_align_bytes = 4, 169 .spectral_bin_discard = 0, 170 .spectral_bin_offset = 0, 171 .vht160_mcs_rx_highest = 0, 172 .vht160_mcs_tx_highest = 0, 173 .n_cipher_suites = 8, 174 .ast_skid_limit = 0x10, 175 .num_wds_entries = 0x20, 176 .target_64bit = false, 177 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 178 .shadow_reg_support = false, 179 .rri_on_ddr = false, 180 .hw_filter_reset_required = true, 181 .fw_diag_ce_download = false, 182 .credit_size_workaround = false, 183 .tx_stats_over_pktlog = false, 184 .dynamic_sar_support = false, 185 .hw_restart_disconnect = false, 186 .use_fw_tx_credits = true, 187 .delay_unmap_buffer = false, 188 .mcast_frame_registration = false, 189 }, 190 { 191 .id = QCA6174_HW_3_2_VERSION, 192 .dev_id = QCA6174_3_2_DEVICE_ID, 193 .bus = ATH10K_BUS_SDIO, 194 .name = "qca6174 hw3.2 sdio", 195 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 196 .uart_pin = 19, 197 .led_pin = 0, 198 .otp_exe_param = 0, 199 .channel_counters_freq_hz = 88000, 200 .max_probe_resp_desc_thres = 0, 201 .cal_data_len = 0, 202 .fw = { 203 .dir = QCA6174_HW_3_0_FW_DIR, 204 .board_size = QCA6174_BOARD_DATA_SZ, 205 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 206 }, 207 .rx_desc_ops = &qca988x_rx_desc_ops, 208 .hw_ops = &qca6174_sdio_ops, 209 .hw_clk = qca6174_clk, 210 .target_cpu_freq = 176000000, 211 .decap_align_bytes = 4, 212 .n_cipher_suites = 8, 213 .num_peers = 10, 214 .ast_skid_limit = 0x10, 215 .num_wds_entries = 0x20, 216 .uart_pin_workaround = true, 217 .tx_stats_over_pktlog = false, 218 .credit_size_workaround = false, 219 .bmi_large_size_download = true, 220 .supports_peer_stats_info = true, 221 .dynamic_sar_support = true, 222 .hw_restart_disconnect = false, 223 .use_fw_tx_credits = true, 224 .delay_unmap_buffer = false, 225 .mcast_frame_registration = false, 226 }, 227 { 228 .id = QCA6174_HW_2_1_VERSION, 229 .dev_id = QCA6164_2_1_DEVICE_ID, 230 .bus = ATH10K_BUS_PCI, 231 .name = "qca6164 hw2.1", 232 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 233 .uart_pin = 6, 234 .led_pin = 0, 235 .otp_exe_param = 0, 236 .channel_counters_freq_hz = 88000, 237 .max_probe_resp_desc_thres = 0, 238 .cal_data_len = 8124, 239 .fw = { 240 .dir = QCA6174_HW_2_1_FW_DIR, 241 .board_size = QCA6174_BOARD_DATA_SZ, 242 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 243 }, 244 .rx_desc_ops = &qca988x_rx_desc_ops, 245 .hw_ops = &qca988x_ops, 246 .decap_align_bytes = 4, 247 .spectral_bin_discard = 0, 248 .spectral_bin_offset = 0, 249 .vht160_mcs_rx_highest = 0, 250 .vht160_mcs_tx_highest = 0, 251 .n_cipher_suites = 8, 252 .ast_skid_limit = 0x10, 253 .num_wds_entries = 0x20, 254 .target_64bit = false, 255 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 256 .shadow_reg_support = false, 257 .rri_on_ddr = false, 258 .hw_filter_reset_required = true, 259 .fw_diag_ce_download = false, 260 .credit_size_workaround = false, 261 .tx_stats_over_pktlog = false, 262 .dynamic_sar_support = false, 263 .hw_restart_disconnect = false, 264 .use_fw_tx_credits = true, 265 .delay_unmap_buffer = false, 266 .mcast_frame_registration = false, 267 }, 268 { 269 .id = QCA6174_HW_2_1_VERSION, 270 .dev_id = QCA6174_2_1_DEVICE_ID, 271 .bus = ATH10K_BUS_PCI, 272 .name = "qca6174 hw2.1", 273 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 274 .uart_pin = 6, 275 .led_pin = 0, 276 .otp_exe_param = 0, 277 .channel_counters_freq_hz = 88000, 278 .max_probe_resp_desc_thres = 0, 279 .cal_data_len = 8124, 280 .fw = { 281 .dir = QCA6174_HW_2_1_FW_DIR, 282 .board_size = QCA6174_BOARD_DATA_SZ, 283 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 284 }, 285 .rx_desc_ops = &qca988x_rx_desc_ops, 286 .hw_ops = &qca988x_ops, 287 .decap_align_bytes = 4, 288 .spectral_bin_discard = 0, 289 .spectral_bin_offset = 0, 290 .vht160_mcs_rx_highest = 0, 291 .vht160_mcs_tx_highest = 0, 292 .n_cipher_suites = 8, 293 .ast_skid_limit = 0x10, 294 .num_wds_entries = 0x20, 295 .target_64bit = false, 296 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 297 .shadow_reg_support = false, 298 .rri_on_ddr = false, 299 .hw_filter_reset_required = true, 300 .fw_diag_ce_download = false, 301 .credit_size_workaround = false, 302 .tx_stats_over_pktlog = false, 303 .dynamic_sar_support = false, 304 .hw_restart_disconnect = false, 305 .use_fw_tx_credits = true, 306 .delay_unmap_buffer = false, 307 .mcast_frame_registration = false, 308 }, 309 { 310 .id = QCA6174_HW_3_0_VERSION, 311 .dev_id = QCA6174_2_1_DEVICE_ID, 312 .bus = ATH10K_BUS_PCI, 313 .name = "qca6174 hw3.0", 314 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 315 .uart_pin = 6, 316 .led_pin = 0, 317 .otp_exe_param = 0, 318 .channel_counters_freq_hz = 88000, 319 .max_probe_resp_desc_thres = 0, 320 .cal_data_len = 8124, 321 .fw = { 322 .dir = QCA6174_HW_3_0_FW_DIR, 323 .board_size = QCA6174_BOARD_DATA_SZ, 324 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 325 }, 326 .rx_desc_ops = &qca988x_rx_desc_ops, 327 .hw_ops = &qca988x_ops, 328 .decap_align_bytes = 4, 329 .spectral_bin_discard = 0, 330 .spectral_bin_offset = 0, 331 .vht160_mcs_rx_highest = 0, 332 .vht160_mcs_tx_highest = 0, 333 .n_cipher_suites = 8, 334 .ast_skid_limit = 0x10, 335 .num_wds_entries = 0x20, 336 .target_64bit = false, 337 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 338 .shadow_reg_support = false, 339 .rri_on_ddr = false, 340 .hw_filter_reset_required = true, 341 .fw_diag_ce_download = false, 342 .credit_size_workaround = false, 343 .tx_stats_over_pktlog = false, 344 .dynamic_sar_support = false, 345 .hw_restart_disconnect = false, 346 .use_fw_tx_credits = true, 347 .delay_unmap_buffer = false, 348 .mcast_frame_registration = false, 349 }, 350 { 351 .id = QCA6174_HW_3_2_VERSION, 352 .dev_id = QCA6174_2_1_DEVICE_ID, 353 .bus = ATH10K_BUS_PCI, 354 .name = "qca6174 hw3.2", 355 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 356 .uart_pin = 6, 357 .led_pin = 0, 358 .otp_exe_param = 0, 359 .channel_counters_freq_hz = 88000, 360 .max_probe_resp_desc_thres = 0, 361 .cal_data_len = 8124, 362 .fw = { 363 /* uses same binaries as hw3.0 */ 364 .dir = QCA6174_HW_3_0_FW_DIR, 365 .board_size = QCA6174_BOARD_DATA_SZ, 366 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 367 }, 368 .rx_desc_ops = &qca988x_rx_desc_ops, 369 .hw_ops = &qca6174_ops, 370 .hw_clk = qca6174_clk, 371 .target_cpu_freq = 176000000, 372 .decap_align_bytes = 4, 373 .spectral_bin_discard = 0, 374 .spectral_bin_offset = 0, 375 .vht160_mcs_rx_highest = 0, 376 .vht160_mcs_tx_highest = 0, 377 .n_cipher_suites = 8, 378 .ast_skid_limit = 0x10, 379 .num_wds_entries = 0x20, 380 .target_64bit = false, 381 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 382 .shadow_reg_support = false, 383 .rri_on_ddr = false, 384 .hw_filter_reset_required = true, 385 .fw_diag_ce_download = true, 386 .credit_size_workaround = false, 387 .tx_stats_over_pktlog = false, 388 .supports_peer_stats_info = true, 389 .dynamic_sar_support = true, 390 .hw_restart_disconnect = false, 391 .use_fw_tx_credits = true, 392 .delay_unmap_buffer = false, 393 .mcast_frame_registration = true, 394 }, 395 { 396 .id = QCA99X0_HW_2_0_DEV_VERSION, 397 .dev_id = QCA99X0_2_0_DEVICE_ID, 398 .bus = ATH10K_BUS_PCI, 399 .name = "qca99x0 hw2.0", 400 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 401 .uart_pin = 7, 402 .led_pin = 17, 403 .otp_exe_param = 0x00000700, 404 .continuous_frag_desc = true, 405 .cck_rate_map_rev2 = true, 406 .channel_counters_freq_hz = 150000, 407 .max_probe_resp_desc_thres = 24, 408 .tx_chain_mask = 0xf, 409 .rx_chain_mask = 0xf, 410 .max_spatial_stream = 4, 411 .cal_data_len = 12064, 412 .fw = { 413 .dir = QCA99X0_HW_2_0_FW_DIR, 414 .board_size = QCA99X0_BOARD_DATA_SZ, 415 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 416 }, 417 .sw_decrypt_mcast_mgmt = true, 418 .rx_desc_ops = &qca99x0_rx_desc_ops, 419 .hw_ops = &qca99x0_ops, 420 .decap_align_bytes = 1, 421 .spectral_bin_discard = 4, 422 .spectral_bin_offset = 0, 423 .vht160_mcs_rx_highest = 0, 424 .vht160_mcs_tx_highest = 0, 425 .n_cipher_suites = 11, 426 .ast_skid_limit = 0x10, 427 .num_wds_entries = 0x20, 428 .target_64bit = false, 429 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 430 .shadow_reg_support = false, 431 .rri_on_ddr = false, 432 .hw_filter_reset_required = true, 433 .fw_diag_ce_download = false, 434 .credit_size_workaround = false, 435 .tx_stats_over_pktlog = false, 436 .dynamic_sar_support = false, 437 .hw_restart_disconnect = false, 438 .use_fw_tx_credits = true, 439 .delay_unmap_buffer = false, 440 .mcast_frame_registration = false, 441 }, 442 { 443 .id = QCA9984_HW_1_0_DEV_VERSION, 444 .dev_id = QCA9984_1_0_DEVICE_ID, 445 .bus = ATH10K_BUS_PCI, 446 .name = "qca9984/qca9994 hw1.0", 447 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 448 .uart_pin = 7, 449 .led_pin = 17, 450 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 451 .otp_exe_param = 0x00000700, 452 .continuous_frag_desc = true, 453 .cck_rate_map_rev2 = true, 454 .channel_counters_freq_hz = 150000, 455 .max_probe_resp_desc_thres = 24, 456 .tx_chain_mask = 0xf, 457 .rx_chain_mask = 0xf, 458 .max_spatial_stream = 4, 459 .cal_data_len = 12064, 460 .fw = { 461 .dir = QCA9984_HW_1_0_FW_DIR, 462 .board_size = QCA99X0_BOARD_DATA_SZ, 463 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 464 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 465 }, 466 .sw_decrypt_mcast_mgmt = true, 467 .rx_desc_ops = &qca99x0_rx_desc_ops, 468 .hw_ops = &qca99x0_ops, 469 .decap_align_bytes = 1, 470 .spectral_bin_discard = 12, 471 .spectral_bin_offset = 8, 472 473 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 474 * or 2x2 160Mhz, long-guard-interval. 475 */ 476 .vht160_mcs_rx_highest = 1560, 477 .vht160_mcs_tx_highest = 1560, 478 .n_cipher_suites = 11, 479 .ast_skid_limit = 0x10, 480 .num_wds_entries = 0x20, 481 .target_64bit = false, 482 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 483 .shadow_reg_support = false, 484 .rri_on_ddr = false, 485 .hw_filter_reset_required = true, 486 .fw_diag_ce_download = false, 487 .credit_size_workaround = false, 488 .tx_stats_over_pktlog = false, 489 .dynamic_sar_support = false, 490 .hw_restart_disconnect = false, 491 .use_fw_tx_credits = true, 492 .delay_unmap_buffer = false, 493 .mcast_frame_registration = false, 494 }, 495 { 496 .id = QCA9888_HW_2_0_DEV_VERSION, 497 .dev_id = QCA9888_2_0_DEVICE_ID, 498 .bus = ATH10K_BUS_PCI, 499 .name = "qca9888 hw2.0", 500 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 501 .uart_pin = 7, 502 .led_pin = 17, 503 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 504 .otp_exe_param = 0x00000700, 505 .continuous_frag_desc = true, 506 .channel_counters_freq_hz = 150000, 507 .max_probe_resp_desc_thres = 24, 508 .tx_chain_mask = 3, 509 .rx_chain_mask = 3, 510 .max_spatial_stream = 2, 511 .cal_data_len = 12064, 512 .fw = { 513 .dir = QCA9888_HW_2_0_FW_DIR, 514 .board_size = QCA99X0_BOARD_DATA_SZ, 515 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 516 }, 517 .sw_decrypt_mcast_mgmt = true, 518 .rx_desc_ops = &qca99x0_rx_desc_ops, 519 .hw_ops = &qca99x0_ops, 520 .decap_align_bytes = 1, 521 .spectral_bin_discard = 12, 522 .spectral_bin_offset = 8, 523 524 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 525 * 1x1 160Mhz, long-guard-interval. 526 */ 527 .vht160_mcs_rx_highest = 780, 528 .vht160_mcs_tx_highest = 780, 529 .n_cipher_suites = 11, 530 .ast_skid_limit = 0x10, 531 .num_wds_entries = 0x20, 532 .target_64bit = false, 533 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 534 .shadow_reg_support = false, 535 .rri_on_ddr = false, 536 .hw_filter_reset_required = true, 537 .fw_diag_ce_download = false, 538 .credit_size_workaround = false, 539 .tx_stats_over_pktlog = false, 540 .dynamic_sar_support = false, 541 .hw_restart_disconnect = false, 542 .use_fw_tx_credits = true, 543 .delay_unmap_buffer = false, 544 .mcast_frame_registration = false, 545 }, 546 { 547 .id = QCA9377_HW_1_0_DEV_VERSION, 548 .dev_id = QCA9377_1_0_DEVICE_ID, 549 .bus = ATH10K_BUS_PCI, 550 .name = "qca9377 hw1.0", 551 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 552 .uart_pin = 6, 553 .led_pin = 0, 554 .otp_exe_param = 0, 555 .channel_counters_freq_hz = 88000, 556 .max_probe_resp_desc_thres = 0, 557 .cal_data_len = 8124, 558 .fw = { 559 .dir = QCA9377_HW_1_0_FW_DIR, 560 .board_size = QCA9377_BOARD_DATA_SZ, 561 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 562 }, 563 .rx_desc_ops = &qca988x_rx_desc_ops, 564 .hw_ops = &qca988x_ops, 565 .decap_align_bytes = 4, 566 .spectral_bin_discard = 0, 567 .spectral_bin_offset = 0, 568 .vht160_mcs_rx_highest = 0, 569 .vht160_mcs_tx_highest = 0, 570 .n_cipher_suites = 8, 571 .ast_skid_limit = 0x10, 572 .num_wds_entries = 0x20, 573 .target_64bit = false, 574 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 575 .shadow_reg_support = false, 576 .rri_on_ddr = false, 577 .hw_filter_reset_required = true, 578 .fw_diag_ce_download = false, 579 .credit_size_workaround = false, 580 .tx_stats_over_pktlog = false, 581 .dynamic_sar_support = false, 582 .hw_restart_disconnect = false, 583 .use_fw_tx_credits = true, 584 .delay_unmap_buffer = false, 585 .mcast_frame_registration = false, 586 }, 587 { 588 .id = QCA9377_HW_1_1_DEV_VERSION, 589 .dev_id = QCA9377_1_0_DEVICE_ID, 590 .bus = ATH10K_BUS_PCI, 591 .name = "qca9377 hw1.1", 592 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 593 .uart_pin = 6, 594 .led_pin = 0, 595 .otp_exe_param = 0, 596 .channel_counters_freq_hz = 88000, 597 .max_probe_resp_desc_thres = 0, 598 .cal_data_len = 8124, 599 .fw = { 600 .dir = QCA9377_HW_1_0_FW_DIR, 601 .board_size = QCA9377_BOARD_DATA_SZ, 602 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 603 }, 604 .rx_desc_ops = &qca988x_rx_desc_ops, 605 .hw_ops = &qca6174_ops, 606 .hw_clk = qca6174_clk, 607 .target_cpu_freq = 176000000, 608 .decap_align_bytes = 4, 609 .spectral_bin_discard = 0, 610 .spectral_bin_offset = 0, 611 .vht160_mcs_rx_highest = 0, 612 .vht160_mcs_tx_highest = 0, 613 .n_cipher_suites = 8, 614 .ast_skid_limit = 0x10, 615 .num_wds_entries = 0x20, 616 .target_64bit = false, 617 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 618 .shadow_reg_support = false, 619 .rri_on_ddr = false, 620 .hw_filter_reset_required = true, 621 .fw_diag_ce_download = true, 622 .credit_size_workaround = false, 623 .tx_stats_over_pktlog = false, 624 .dynamic_sar_support = false, 625 .hw_restart_disconnect = false, 626 .use_fw_tx_credits = true, 627 .delay_unmap_buffer = false, 628 .mcast_frame_registration = false, 629 }, 630 { 631 .id = QCA9377_HW_1_1_DEV_VERSION, 632 .dev_id = QCA9377_1_0_DEVICE_ID, 633 .bus = ATH10K_BUS_SDIO, 634 .name = "qca9377 hw1.1 sdio", 635 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 636 .uart_pin = 19, 637 .led_pin = 0, 638 .otp_exe_param = 0, 639 .channel_counters_freq_hz = 88000, 640 .max_probe_resp_desc_thres = 0, 641 .cal_data_len = 8124, 642 .fw = { 643 .dir = QCA9377_HW_1_0_FW_DIR, 644 .board_size = QCA9377_BOARD_DATA_SZ, 645 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 646 }, 647 .rx_desc_ops = &qca988x_rx_desc_ops, 648 .hw_ops = &qca6174_ops, 649 .hw_clk = qca6174_clk, 650 .target_cpu_freq = 176000000, 651 .decap_align_bytes = 4, 652 .n_cipher_suites = 8, 653 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 654 .ast_skid_limit = 0x10, 655 .num_wds_entries = 0x20, 656 .uart_pin_workaround = true, 657 .credit_size_workaround = true, 658 .dynamic_sar_support = false, 659 .hw_restart_disconnect = false, 660 .use_fw_tx_credits = true, 661 .delay_unmap_buffer = false, 662 .mcast_frame_registration = false, 663 }, 664 { 665 .id = QCA4019_HW_1_0_DEV_VERSION, 666 .dev_id = 0, 667 .bus = ATH10K_BUS_AHB, 668 .name = "qca4019 hw1.0", 669 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 670 .uart_pin = 7, 671 .led_pin = 0, 672 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 673 .otp_exe_param = 0x0010000, 674 .continuous_frag_desc = true, 675 .cck_rate_map_rev2 = true, 676 .channel_counters_freq_hz = 125000, 677 .max_probe_resp_desc_thres = 24, 678 .tx_chain_mask = 0x3, 679 .rx_chain_mask = 0x3, 680 .max_spatial_stream = 2, 681 .cal_data_len = 12064, 682 .fw = { 683 .dir = QCA4019_HW_1_0_FW_DIR, 684 .board_size = QCA4019_BOARD_DATA_SZ, 685 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 686 }, 687 .sw_decrypt_mcast_mgmt = true, 688 .rx_desc_ops = &qca99x0_rx_desc_ops, 689 .hw_ops = &qca99x0_ops, 690 .decap_align_bytes = 1, 691 .spectral_bin_discard = 4, 692 .spectral_bin_offset = 0, 693 .vht160_mcs_rx_highest = 0, 694 .vht160_mcs_tx_highest = 0, 695 .n_cipher_suites = 11, 696 .ast_skid_limit = 0x10, 697 .num_wds_entries = 0x20, 698 .target_64bit = false, 699 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 700 .shadow_reg_support = false, 701 .rri_on_ddr = false, 702 .hw_filter_reset_required = true, 703 .fw_diag_ce_download = false, 704 .credit_size_workaround = false, 705 .tx_stats_over_pktlog = false, 706 .dynamic_sar_support = false, 707 .hw_restart_disconnect = false, 708 .use_fw_tx_credits = true, 709 .delay_unmap_buffer = false, 710 .mcast_frame_registration = false, 711 }, 712 { 713 .id = WCN3990_HW_1_0_DEV_VERSION, 714 .dev_id = 0, 715 .bus = ATH10K_BUS_SNOC, 716 .name = "wcn3990 hw1.0", 717 .led_pin = 0, 718 .continuous_frag_desc = true, 719 .tx_chain_mask = 0x7, 720 .rx_chain_mask = 0x7, 721 .max_spatial_stream = 4, 722 .fw = { 723 .dir = WCN3990_HW_1_0_FW_DIR, 724 .board_size = WCN3990_BOARD_DATA_SZ, 725 .board_ext_size = WCN3990_BOARD_EXT_DATA_SZ, 726 }, 727 .sw_decrypt_mcast_mgmt = true, 728 .rx_desc_ops = &wcn3990_rx_desc_ops, 729 .hw_ops = &wcn3990_ops, 730 .decap_align_bytes = 1, 731 .num_peers = TARGET_HL_TLV_NUM_PEERS, 732 .n_cipher_suites = 11, 733 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 734 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 735 .target_64bit = true, 736 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 737 .shadow_reg_support = true, 738 .rri_on_ddr = true, 739 .hw_filter_reset_required = false, 740 .fw_diag_ce_download = false, 741 .credit_size_workaround = false, 742 .tx_stats_over_pktlog = false, 743 .dynamic_sar_support = true, 744 .hw_restart_disconnect = true, 745 .use_fw_tx_credits = false, 746 .delay_unmap_buffer = true, 747 .mcast_frame_registration = false, 748 }, 749 }; 750 751 static const char *const ath10k_core_fw_feature_str[] = { 752 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 753 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 754 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 755 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 756 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 757 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 758 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 759 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 760 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 761 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 762 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 763 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 764 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 765 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 766 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 767 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 768 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 769 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 770 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 771 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 772 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 773 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 774 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 775 }; 776 777 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 778 size_t buf_len, 779 enum ath10k_fw_features feat) 780 { 781 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 782 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 783 ATH10K_FW_FEATURE_COUNT); 784 785 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 786 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 787 return scnprintf(buf, buf_len, "bit%d", feat); 788 } 789 790 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 791 } 792 793 void ath10k_core_get_fw_features_str(struct ath10k *ar, 794 char *buf, 795 size_t buf_len) 796 { 797 size_t len = 0; 798 int i; 799 800 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 801 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 802 if (len > 0) 803 len += scnprintf(buf + len, buf_len - len, ","); 804 805 len += ath10k_core_get_fw_feature_str(buf + len, 806 buf_len - len, 807 i); 808 } 809 } 810 } 811 812 static void ath10k_send_suspend_complete(struct ath10k *ar) 813 { 814 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 815 816 complete(&ar->target_suspend); 817 } 818 819 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 820 { 821 bool mtu_workaround = ar->hw_params.credit_size_workaround; 822 int ret; 823 u32 param = 0; 824 825 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 826 if (ret) 827 return ret; 828 829 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 830 if (ret) 831 return ret; 832 833 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 834 if (ret) 835 return ret; 836 837 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 838 839 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 840 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 841 else 842 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 843 844 if (mode == ATH10K_FIRMWARE_MODE_UTF) 845 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 846 else 847 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 848 849 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 850 if (ret) 851 return ret; 852 853 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 854 if (ret) 855 return ret; 856 857 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 858 859 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 860 if (ret) 861 return ret; 862 863 return 0; 864 } 865 866 static int ath10k_init_configure_target(struct ath10k *ar) 867 { 868 u32 param_host; 869 int ret; 870 871 /* tell target which HTC version it is used*/ 872 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 873 HTC_PROTOCOL_VERSION); 874 if (ret) { 875 ath10k_err(ar, "settings HTC version failed\n"); 876 return ret; 877 } 878 879 /* set the firmware mode to STA/IBSS/AP */ 880 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 881 if (ret) { 882 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 883 return ret; 884 } 885 886 /* TODO following parameters need to be re-visited. */ 887 /* num_device */ 888 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 889 /* Firmware mode */ 890 /* FIXME: Why FW_MODE_AP ??.*/ 891 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 892 /* mac_addr_method */ 893 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 894 /* firmware_bridge */ 895 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 896 /* fwsubmode */ 897 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 898 899 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 900 if (ret) { 901 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 902 return ret; 903 } 904 905 /* We do all byte-swapping on the host */ 906 ret = ath10k_bmi_write32(ar, hi_be, 0); 907 if (ret) { 908 ath10k_err(ar, "setting host CPU BE mode failed\n"); 909 return ret; 910 } 911 912 /* FW descriptor/Data swap flags */ 913 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 914 915 if (ret) { 916 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 917 return ret; 918 } 919 920 /* Some devices have a special sanity check that verifies the PCI 921 * Device ID is written to this host interest var. It is known to be 922 * required to boot QCA6164. 923 */ 924 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 925 ar->dev_id); 926 if (ret) { 927 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 928 return ret; 929 } 930 931 return 0; 932 } 933 934 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 935 const char *dir, 936 const char *file) 937 { 938 char filename[100]; 939 const struct firmware *fw; 940 int ret; 941 942 if (file == NULL) 943 return ERR_PTR(-ENOENT); 944 945 if (dir == NULL) 946 dir = "."; 947 948 if (ar->board_name) { 949 snprintf(filename, sizeof(filename), "%s/%s/%s", 950 dir, ar->board_name, file); 951 ret = firmware_request_nowarn(&fw, filename, ar->dev); 952 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 953 filename, ret); 954 if (!ret) 955 return fw; 956 } 957 958 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 959 ret = firmware_request_nowarn(&fw, filename, ar->dev); 960 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 961 filename, ret); 962 if (ret) 963 return ERR_PTR(ret); 964 965 return fw; 966 } 967 968 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 969 size_t data_len) 970 { 971 u32 board_data_size = ar->hw_params.fw.board_size; 972 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 973 u32 board_ext_data_addr; 974 int ret; 975 976 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 977 if (ret) { 978 ath10k_err(ar, "could not read board ext data addr (%d)\n", 979 ret); 980 return ret; 981 } 982 983 ath10k_dbg(ar, ATH10K_DBG_BOOT, 984 "boot push board extended data addr 0x%x\n", 985 board_ext_data_addr); 986 987 if (board_ext_data_addr == 0) 988 return 0; 989 990 if (data_len != (board_data_size + board_ext_data_size)) { 991 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 992 data_len, board_data_size, board_ext_data_size); 993 return -EINVAL; 994 } 995 996 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 997 data + board_data_size, 998 board_ext_data_size); 999 if (ret) { 1000 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 1001 return ret; 1002 } 1003 1004 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 1005 (board_ext_data_size << 16) | 1); 1006 if (ret) { 1007 ath10k_err(ar, "could not write board ext data bit (%d)\n", 1008 ret); 1009 return ret; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 1016 { 1017 u32 result, address; 1018 u8 board_id, chip_id; 1019 bool ext_bid_support; 1020 int ret, bmi_board_id_param; 1021 1022 address = ar->hw_params.patch_load_addr; 1023 1024 if (!ar->normal_mode_fw.fw_file.otp_data || 1025 !ar->normal_mode_fw.fw_file.otp_len) { 1026 ath10k_warn(ar, 1027 "failed to retrieve board id because of invalid otp\n"); 1028 return -ENODATA; 1029 } 1030 1031 if (ar->id.bmi_ids_valid) { 1032 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1033 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 1034 ar->id.bmi_board_id, ar->id.bmi_chip_id); 1035 goto skip_otp_download; 1036 } 1037 1038 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1039 "boot upload otp to 0x%x len %zd for board id\n", 1040 address, ar->normal_mode_fw.fw_file.otp_len); 1041 1042 ret = ath10k_bmi_fast_download(ar, address, 1043 ar->normal_mode_fw.fw_file.otp_data, 1044 ar->normal_mode_fw.fw_file.otp_len); 1045 if (ret) { 1046 ath10k_err(ar, "could not write otp for board id check: %d\n", 1047 ret); 1048 return ret; 1049 } 1050 1051 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1052 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1053 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1054 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 1055 else 1056 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 1057 1058 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 1059 if (ret) { 1060 ath10k_err(ar, "could not execute otp for board id check: %d\n", 1061 ret); 1062 return ret; 1063 } 1064 1065 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1066 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1067 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1068 1069 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1070 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1071 result, board_id, chip_id, ext_bid_support); 1072 1073 ar->id.ext_bid_supported = ext_bid_support; 1074 1075 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1076 (board_id == 0)) { 1077 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1078 "board id does not exist in otp, ignore it\n"); 1079 return -EOPNOTSUPP; 1080 } 1081 1082 ar->id.bmi_ids_valid = true; 1083 ar->id.bmi_board_id = board_id; 1084 ar->id.bmi_chip_id = chip_id; 1085 1086 skip_otp_download: 1087 1088 return 0; 1089 } 1090 1091 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1092 { 1093 struct ath10k *ar = data; 1094 const char *bdf_ext; 1095 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1096 u8 bdf_enabled; 1097 int i; 1098 1099 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1100 return; 1101 1102 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1103 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1104 "wrong smbios bdf ext type length (%d).\n", 1105 hdr->length); 1106 return; 1107 } 1108 1109 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1110 if (!bdf_enabled) { 1111 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1112 return; 1113 } 1114 1115 /* Only one string exists (per spec) */ 1116 bdf_ext = (char *)hdr + hdr->length; 1117 1118 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1119 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1120 "bdf variant magic does not match.\n"); 1121 return; 1122 } 1123 1124 for (i = 0; i < strlen(bdf_ext); i++) { 1125 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1126 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1127 "bdf variant name contains non ascii chars.\n"); 1128 return; 1129 } 1130 } 1131 1132 /* Copy extension name without magic suffix */ 1133 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1134 sizeof(ar->id.bdf_ext)) < 0) { 1135 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1136 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1137 bdf_ext); 1138 return; 1139 } 1140 1141 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1142 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1143 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1144 } 1145 1146 static int ath10k_core_check_smbios(struct ath10k *ar) 1147 { 1148 ar->id.bdf_ext[0] = '\0'; 1149 dmi_walk(ath10k_core_check_bdfext, ar); 1150 1151 if (ar->id.bdf_ext[0] == '\0') 1152 return -ENODATA; 1153 1154 return 0; 1155 } 1156 1157 int ath10k_core_check_dt(struct ath10k *ar) 1158 { 1159 struct device_node *node; 1160 const char *variant = NULL; 1161 1162 node = ar->dev->of_node; 1163 if (!node) 1164 return -ENOENT; 1165 1166 of_property_read_string(node, "qcom,calibration-variant", 1167 &variant); 1168 if (!variant) 1169 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1170 &variant); 1171 if (!variant) 1172 return -ENODATA; 1173 1174 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1175 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1176 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1177 variant); 1178 1179 return 0; 1180 } 1181 EXPORT_SYMBOL(ath10k_core_check_dt); 1182 1183 static int ath10k_download_fw(struct ath10k *ar) 1184 { 1185 u32 address, data_len; 1186 const void *data; 1187 int ret; 1188 struct pm_qos_request latency_qos; 1189 1190 address = ar->hw_params.patch_load_addr; 1191 1192 data = ar->running_fw->fw_file.firmware_data; 1193 data_len = ar->running_fw->fw_file.firmware_len; 1194 1195 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1196 if (ret) { 1197 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1198 ret); 1199 return ret; 1200 } 1201 1202 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1203 "boot uploading firmware image %pK len %d\n", 1204 data, data_len); 1205 1206 /* Check if device supports to download firmware via 1207 * diag copy engine. Downloading firmware via diag CE 1208 * greatly reduces the time to download firmware. 1209 */ 1210 if (ar->hw_params.fw_diag_ce_download) { 1211 ret = ath10k_hw_diag_fast_download(ar, address, 1212 data, data_len); 1213 if (ret == 0) 1214 /* firmware upload via diag ce was successful */ 1215 return 0; 1216 1217 ath10k_warn(ar, 1218 "failed to upload firmware via diag ce, trying BMI: %d", 1219 ret); 1220 } 1221 1222 memset(&latency_qos, 0, sizeof(latency_qos)); 1223 cpu_latency_qos_add_request(&latency_qos, 0); 1224 1225 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1226 1227 cpu_latency_qos_remove_request(&latency_qos); 1228 1229 return ret; 1230 } 1231 1232 void ath10k_core_free_board_files(struct ath10k *ar) 1233 { 1234 if (!IS_ERR(ar->normal_mode_fw.board)) 1235 release_firmware(ar->normal_mode_fw.board); 1236 1237 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1238 release_firmware(ar->normal_mode_fw.ext_board); 1239 1240 ar->normal_mode_fw.board = NULL; 1241 ar->normal_mode_fw.board_data = NULL; 1242 ar->normal_mode_fw.board_len = 0; 1243 ar->normal_mode_fw.ext_board = NULL; 1244 ar->normal_mode_fw.ext_board_data = NULL; 1245 ar->normal_mode_fw.ext_board_len = 0; 1246 } 1247 EXPORT_SYMBOL(ath10k_core_free_board_files); 1248 1249 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1250 { 1251 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1252 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1253 1254 if (!IS_ERR(ar->cal_file)) 1255 release_firmware(ar->cal_file); 1256 1257 if (!IS_ERR(ar->pre_cal_file)) 1258 release_firmware(ar->pre_cal_file); 1259 1260 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1261 1262 ar->normal_mode_fw.fw_file.otp_data = NULL; 1263 ar->normal_mode_fw.fw_file.otp_len = 0; 1264 1265 ar->normal_mode_fw.fw_file.firmware = NULL; 1266 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1267 ar->normal_mode_fw.fw_file.firmware_len = 0; 1268 1269 ar->cal_file = NULL; 1270 ar->pre_cal_file = NULL; 1271 } 1272 1273 static int ath10k_fetch_cal_file(struct ath10k *ar) 1274 { 1275 char filename[100]; 1276 1277 /* pre-cal-<bus>-<id>.bin */ 1278 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1279 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1280 1281 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1282 if (!IS_ERR(ar->pre_cal_file)) 1283 goto success; 1284 1285 /* cal-<bus>-<id>.bin */ 1286 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1287 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1288 1289 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1290 if (IS_ERR(ar->cal_file)) 1291 /* calibration file is optional, don't print any warnings */ 1292 return PTR_ERR(ar->cal_file); 1293 success: 1294 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1295 ATH10K_FW_DIR, filename); 1296 1297 return 0; 1298 } 1299 1300 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1301 { 1302 const struct firmware *fw; 1303 char boardname[100]; 1304 1305 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1306 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin", 1307 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1308 1309 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1310 ar->hw_params.fw.dir, 1311 boardname); 1312 if (IS_ERR(ar->normal_mode_fw.board)) { 1313 fw = ath10k_fetch_fw_file(ar, 1314 ar->hw_params.fw.dir, 1315 ATH10K_BOARD_DATA_FILE); 1316 ar->normal_mode_fw.board = fw; 1317 } 1318 1319 if (IS_ERR(ar->normal_mode_fw.board)) 1320 return PTR_ERR(ar->normal_mode_fw.board); 1321 1322 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1323 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1324 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1325 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1326 ATH10K_EBOARD_DATA_FILE); 1327 ar->normal_mode_fw.ext_board = fw; 1328 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1329 return PTR_ERR(ar->normal_mode_fw.ext_board); 1330 1331 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1332 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1333 } 1334 1335 return 0; 1336 } 1337 1338 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1339 const void *buf, size_t buf_len, 1340 const char *boardname, 1341 int bd_ie_type) 1342 { 1343 const struct ath10k_fw_ie *hdr; 1344 bool name_match_found; 1345 int ret, board_ie_id; 1346 size_t board_ie_len; 1347 const void *board_ie_data; 1348 1349 name_match_found = false; 1350 1351 /* go through ATH10K_BD_IE_BOARD_ elements */ 1352 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1353 hdr = buf; 1354 board_ie_id = le32_to_cpu(hdr->id); 1355 board_ie_len = le32_to_cpu(hdr->len); 1356 board_ie_data = hdr->data; 1357 1358 buf_len -= sizeof(*hdr); 1359 buf += sizeof(*hdr); 1360 1361 if (buf_len < ALIGN(board_ie_len, 4)) { 1362 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1363 buf_len, ALIGN(board_ie_len, 4)); 1364 ret = -EINVAL; 1365 goto out; 1366 } 1367 1368 switch (board_ie_id) { 1369 case ATH10K_BD_IE_BOARD_NAME: 1370 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1371 board_ie_data, board_ie_len); 1372 1373 if (board_ie_len != strlen(boardname)) 1374 break; 1375 1376 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1377 if (ret) 1378 break; 1379 1380 name_match_found = true; 1381 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1382 "boot found match for name '%s'", 1383 boardname); 1384 break; 1385 case ATH10K_BD_IE_BOARD_DATA: 1386 if (!name_match_found) 1387 /* no match found */ 1388 break; 1389 1390 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1391 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1392 "boot found board data for '%s'", 1393 boardname); 1394 1395 ar->normal_mode_fw.board_data = board_ie_data; 1396 ar->normal_mode_fw.board_len = board_ie_len; 1397 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1398 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1399 "boot found eboard data for '%s'", 1400 boardname); 1401 1402 ar->normal_mode_fw.ext_board_data = board_ie_data; 1403 ar->normal_mode_fw.ext_board_len = board_ie_len; 1404 } 1405 1406 ret = 0; 1407 goto out; 1408 default: 1409 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1410 board_ie_id); 1411 break; 1412 } 1413 1414 /* jump over the padding */ 1415 board_ie_len = ALIGN(board_ie_len, 4); 1416 1417 buf_len -= board_ie_len; 1418 buf += board_ie_len; 1419 } 1420 1421 /* no match found */ 1422 ret = -ENOENT; 1423 1424 out: 1425 return ret; 1426 } 1427 1428 static int ath10k_core_search_bd(struct ath10k *ar, 1429 const char *boardname, 1430 const u8 *data, 1431 size_t len) 1432 { 1433 size_t ie_len; 1434 struct ath10k_fw_ie *hdr; 1435 int ret = -ENOENT, ie_id; 1436 1437 while (len > sizeof(struct ath10k_fw_ie)) { 1438 hdr = (struct ath10k_fw_ie *)data; 1439 ie_id = le32_to_cpu(hdr->id); 1440 ie_len = le32_to_cpu(hdr->len); 1441 1442 len -= sizeof(*hdr); 1443 data = hdr->data; 1444 1445 if (len < ALIGN(ie_len, 4)) { 1446 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1447 ie_id, ie_len, len); 1448 return -EINVAL; 1449 } 1450 1451 switch (ie_id) { 1452 case ATH10K_BD_IE_BOARD: 1453 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1454 boardname, 1455 ATH10K_BD_IE_BOARD); 1456 if (ret == -ENOENT) 1457 /* no match found, continue */ 1458 break; 1459 1460 /* either found or error, so stop searching */ 1461 goto out; 1462 case ATH10K_BD_IE_BOARD_EXT: 1463 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1464 boardname, 1465 ATH10K_BD_IE_BOARD_EXT); 1466 if (ret == -ENOENT) 1467 /* no match found, continue */ 1468 break; 1469 1470 /* either found or error, so stop searching */ 1471 goto out; 1472 } 1473 1474 /* jump over the padding */ 1475 ie_len = ALIGN(ie_len, 4); 1476 1477 len -= ie_len; 1478 data += ie_len; 1479 } 1480 1481 out: 1482 /* return result of parse_bd_ie_board() or -ENOENT */ 1483 return ret; 1484 } 1485 1486 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1487 const char *boardname, 1488 const char *fallback_boardname1, 1489 const char *fallback_boardname2, 1490 const char *filename) 1491 { 1492 size_t len, magic_len; 1493 const u8 *data; 1494 int ret; 1495 1496 /* Skip if already fetched during board data download */ 1497 if (!ar->normal_mode_fw.board) 1498 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1499 ar->hw_params.fw.dir, 1500 filename); 1501 if (IS_ERR(ar->normal_mode_fw.board)) 1502 return PTR_ERR(ar->normal_mode_fw.board); 1503 1504 data = ar->normal_mode_fw.board->data; 1505 len = ar->normal_mode_fw.board->size; 1506 1507 /* magic has extra null byte padded */ 1508 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1509 if (len < magic_len) { 1510 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1511 ar->hw_params.fw.dir, filename, len); 1512 ret = -EINVAL; 1513 goto err; 1514 } 1515 1516 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1517 ath10k_err(ar, "found invalid board magic\n"); 1518 ret = -EINVAL; 1519 goto err; 1520 } 1521 1522 /* magic is padded to 4 bytes */ 1523 magic_len = ALIGN(magic_len, 4); 1524 if (len < magic_len) { 1525 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1526 ar->hw_params.fw.dir, filename, len); 1527 ret = -EINVAL; 1528 goto err; 1529 } 1530 1531 data += magic_len; 1532 len -= magic_len; 1533 1534 /* attempt to find boardname in the IE list */ 1535 ret = ath10k_core_search_bd(ar, boardname, data, len); 1536 1537 /* if we didn't find it and have a fallback name, try that */ 1538 if (ret == -ENOENT && fallback_boardname1) 1539 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1540 1541 if (ret == -ENOENT && fallback_boardname2) 1542 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1543 1544 if (ret == -ENOENT) { 1545 ath10k_err(ar, 1546 "failed to fetch board data for %s from %s/%s\n", 1547 boardname, ar->hw_params.fw.dir, filename); 1548 ret = -ENODATA; 1549 } 1550 1551 if (ret) 1552 goto err; 1553 1554 return 0; 1555 1556 err: 1557 ath10k_core_free_board_files(ar); 1558 return ret; 1559 } 1560 1561 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1562 size_t name_len, bool with_variant, 1563 bool with_chip_id) 1564 { 1565 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1566 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1567 1568 if (with_variant && ar->id.bdf_ext[0] != '\0') 1569 scnprintf(variant, sizeof(variant), ",variant=%s", 1570 ar->id.bdf_ext); 1571 1572 if (ar->id.bmi_ids_valid) { 1573 scnprintf(name, name_len, 1574 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1575 ath10k_bus_str(ar->hif.bus), 1576 ar->id.bmi_chip_id, 1577 ar->id.bmi_board_id, variant); 1578 goto out; 1579 } 1580 1581 if (ar->id.qmi_ids_valid) { 1582 if (with_chip_id) 1583 scnprintf(name, name_len, 1584 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1585 ath10k_bus_str(ar->hif.bus), 1586 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1587 variant); 1588 else 1589 scnprintf(name, name_len, 1590 "bus=%s,qmi-board-id=%x", 1591 ath10k_bus_str(ar->hif.bus), 1592 ar->id.qmi_board_id); 1593 goto out; 1594 } 1595 1596 scnprintf(name, name_len, 1597 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1598 ath10k_bus_str(ar->hif.bus), 1599 ar->id.vendor, ar->id.device, 1600 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1601 out: 1602 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1603 1604 return 0; 1605 } 1606 1607 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1608 size_t name_len) 1609 { 1610 if (ar->id.bmi_ids_valid) { 1611 scnprintf(name, name_len, 1612 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1613 ath10k_bus_str(ar->hif.bus), 1614 ar->id.bmi_chip_id, 1615 ar->id.bmi_eboard_id); 1616 1617 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1618 return 0; 1619 } 1620 /* Fallback if returned board id is zero */ 1621 return -1; 1622 } 1623 1624 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1625 { 1626 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1627 int ret; 1628 1629 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1630 /* With variant and chip id */ 1631 ret = ath10k_core_create_board_name(ar, boardname, 1632 sizeof(boardname), true, 1633 true); 1634 if (ret) { 1635 ath10k_err(ar, "failed to create board name: %d", ret); 1636 return ret; 1637 } 1638 1639 /* Without variant and only chip-id */ 1640 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1641 sizeof(boardname), false, 1642 true); 1643 if (ret) { 1644 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1645 ret); 1646 return ret; 1647 } 1648 1649 /* Without variant and without chip-id */ 1650 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1651 sizeof(boardname), false, 1652 false); 1653 if (ret) { 1654 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1655 ret); 1656 return ret; 1657 } 1658 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1659 ret = ath10k_core_create_eboard_name(ar, boardname, 1660 sizeof(boardname)); 1661 if (ret) { 1662 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1663 goto fallback; 1664 } 1665 } 1666 1667 ar->bd_api = 2; 1668 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1669 fallback_boardname1, 1670 fallback_boardname2, 1671 ATH10K_BOARD_API2_FILE); 1672 if (!ret) 1673 goto success; 1674 1675 fallback: 1676 ar->bd_api = 1; 1677 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1678 if (ret) { 1679 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1680 ar->hw_params.fw.dir); 1681 return ret; 1682 } 1683 1684 success: 1685 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1686 return 0; 1687 } 1688 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1689 1690 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1691 { 1692 u32 result, address; 1693 u8 ext_board_id; 1694 int ret; 1695 1696 address = ar->hw_params.patch_load_addr; 1697 1698 if (!ar->normal_mode_fw.fw_file.otp_data || 1699 !ar->normal_mode_fw.fw_file.otp_len) { 1700 ath10k_warn(ar, 1701 "failed to retrieve extended board id due to otp binary missing\n"); 1702 return -ENODATA; 1703 } 1704 1705 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1706 "boot upload otp to 0x%x len %zd for ext board id\n", 1707 address, ar->normal_mode_fw.fw_file.otp_len); 1708 1709 ret = ath10k_bmi_fast_download(ar, address, 1710 ar->normal_mode_fw.fw_file.otp_data, 1711 ar->normal_mode_fw.fw_file.otp_len); 1712 if (ret) { 1713 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1714 ret); 1715 return ret; 1716 } 1717 1718 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1719 if (ret) { 1720 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1721 ret); 1722 return ret; 1723 } 1724 1725 if (!result) { 1726 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1727 "ext board id does not exist in otp, ignore it\n"); 1728 return -EOPNOTSUPP; 1729 } 1730 1731 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1732 1733 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1734 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1735 result, ext_board_id); 1736 1737 ar->id.bmi_eboard_id = ext_board_id; 1738 1739 return 0; 1740 } 1741 1742 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1743 size_t data_len) 1744 { 1745 u32 board_data_size = ar->hw_params.fw.board_size; 1746 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1747 u32 board_address; 1748 u32 ext_board_address; 1749 int ret; 1750 1751 ret = ath10k_push_board_ext_data(ar, data, data_len); 1752 if (ret) { 1753 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1754 goto exit; 1755 } 1756 1757 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1758 if (ret) { 1759 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1760 goto exit; 1761 } 1762 1763 ret = ath10k_bmi_write_memory(ar, board_address, data, 1764 min_t(u32, board_data_size, 1765 data_len)); 1766 if (ret) { 1767 ath10k_err(ar, "could not write board data (%d)\n", ret); 1768 goto exit; 1769 } 1770 1771 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1772 if (ret) { 1773 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1774 goto exit; 1775 } 1776 1777 if (!ar->id.ext_bid_supported) 1778 goto exit; 1779 1780 /* Extended board data download */ 1781 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1782 if (ret == -EOPNOTSUPP) { 1783 /* Not fetching ext_board_data if ext board id is 0 */ 1784 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1785 return 0; 1786 } else if (ret) { 1787 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1788 goto exit; 1789 } 1790 1791 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1792 if (ret) 1793 goto exit; 1794 1795 if (ar->normal_mode_fw.ext_board_data) { 1796 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1797 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1798 "boot writing ext board data to addr 0x%x", 1799 ext_board_address); 1800 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1801 ar->normal_mode_fw.ext_board_data, 1802 min_t(u32, eboard_data_size, data_len)); 1803 if (ret) 1804 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1805 } 1806 1807 exit: 1808 return ret; 1809 } 1810 1811 static int ath10k_download_and_run_otp(struct ath10k *ar) 1812 { 1813 u32 result, address = ar->hw_params.patch_load_addr; 1814 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1815 int ret; 1816 1817 ret = ath10k_download_board_data(ar, 1818 ar->running_fw->board_data, 1819 ar->running_fw->board_len); 1820 if (ret) { 1821 ath10k_err(ar, "failed to download board data: %d\n", ret); 1822 return ret; 1823 } 1824 1825 /* OTP is optional */ 1826 1827 if (!ar->running_fw->fw_file.otp_data || 1828 !ar->running_fw->fw_file.otp_len) { 1829 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1830 ar->running_fw->fw_file.otp_data, 1831 ar->running_fw->fw_file.otp_len); 1832 return 0; 1833 } 1834 1835 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1836 address, ar->running_fw->fw_file.otp_len); 1837 1838 ret = ath10k_bmi_fast_download(ar, address, 1839 ar->running_fw->fw_file.otp_data, 1840 ar->running_fw->fw_file.otp_len); 1841 if (ret) { 1842 ath10k_err(ar, "could not write otp (%d)\n", ret); 1843 return ret; 1844 } 1845 1846 /* As of now pre-cal is valid for 10_4 variants */ 1847 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1848 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1849 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1850 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1851 1852 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1853 if (ret) { 1854 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1855 return ret; 1856 } 1857 1858 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1859 1860 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1861 ar->running_fw->fw_file.fw_features)) && 1862 result != 0) { 1863 ath10k_err(ar, "otp calibration failed: %d", result); 1864 return -EINVAL; 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int ath10k_download_cal_file(struct ath10k *ar, 1871 const struct firmware *file) 1872 { 1873 int ret; 1874 1875 if (!file) 1876 return -ENOENT; 1877 1878 if (IS_ERR(file)) 1879 return PTR_ERR(file); 1880 1881 ret = ath10k_download_board_data(ar, file->data, file->size); 1882 if (ret) { 1883 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1884 return ret; 1885 } 1886 1887 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1888 1889 return 0; 1890 } 1891 1892 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1893 { 1894 struct device_node *node; 1895 int data_len; 1896 void *data; 1897 int ret; 1898 1899 node = ar->dev->of_node; 1900 if (!node) 1901 /* Device Tree is optional, don't print any warnings if 1902 * there's no node for ath10k. 1903 */ 1904 return -ENOENT; 1905 1906 if (!of_get_property(node, dt_name, &data_len)) { 1907 /* The calibration data node is optional */ 1908 return -ENOENT; 1909 } 1910 1911 if (data_len != ar->hw_params.cal_data_len) { 1912 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1913 data_len); 1914 ret = -EMSGSIZE; 1915 goto out; 1916 } 1917 1918 data = kmalloc(data_len, GFP_KERNEL); 1919 if (!data) { 1920 ret = -ENOMEM; 1921 goto out; 1922 } 1923 1924 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1925 if (ret) { 1926 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1927 ret); 1928 goto out_free; 1929 } 1930 1931 ret = ath10k_download_board_data(ar, data, data_len); 1932 if (ret) { 1933 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1934 ret); 1935 goto out_free; 1936 } 1937 1938 ret = 0; 1939 1940 out_free: 1941 kfree(data); 1942 1943 out: 1944 return ret; 1945 } 1946 1947 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1948 { 1949 size_t data_len; 1950 void *data = NULL; 1951 int ret; 1952 1953 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1954 if (ret) { 1955 if (ret != -EOPNOTSUPP) 1956 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1957 ret); 1958 goto out_free; 1959 } 1960 1961 ret = ath10k_download_board_data(ar, data, data_len); 1962 if (ret) { 1963 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1964 ret); 1965 goto out_free; 1966 } 1967 1968 ret = 0; 1969 1970 out_free: 1971 kfree(data); 1972 1973 return ret; 1974 } 1975 1976 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1977 { 1978 struct nvmem_cell *cell; 1979 void *buf; 1980 size_t len; 1981 int ret; 1982 1983 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1984 if (IS_ERR(cell)) { 1985 ret = PTR_ERR(cell); 1986 return ret; 1987 } 1988 1989 buf = nvmem_cell_read(cell, &len); 1990 if (IS_ERR(buf)) 1991 return PTR_ERR(buf); 1992 1993 if (ar->hw_params.cal_data_len != len) { 1994 kfree(buf); 1995 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1996 cell_name, len, ar->hw_params.cal_data_len); 1997 return -EMSGSIZE; 1998 } 1999 2000 ret = ath10k_download_board_data(ar, buf, len); 2001 kfree(buf); 2002 if (ret) 2003 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 2004 cell_name, ret); 2005 2006 return ret; 2007 } 2008 2009 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 2010 struct ath10k_fw_file *fw_file) 2011 { 2012 size_t magic_len, len, ie_len; 2013 int ie_id, i, index, bit, ret; 2014 struct ath10k_fw_ie *hdr; 2015 const u8 *data; 2016 __le32 *timestamp, *version; 2017 2018 /* first fetch the firmware file (firmware-*.bin) */ 2019 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 2020 name); 2021 if (IS_ERR(fw_file->firmware)) 2022 return PTR_ERR(fw_file->firmware); 2023 2024 data = fw_file->firmware->data; 2025 len = fw_file->firmware->size; 2026 2027 /* magic also includes the null byte, check that as well */ 2028 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 2029 2030 if (len < magic_len) { 2031 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 2032 ar->hw_params.fw.dir, name, len); 2033 ret = -EINVAL; 2034 goto err; 2035 } 2036 2037 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 2038 ath10k_err(ar, "invalid firmware magic\n"); 2039 ret = -EINVAL; 2040 goto err; 2041 } 2042 2043 /* jump over the padding */ 2044 magic_len = ALIGN(magic_len, 4); 2045 2046 len -= magic_len; 2047 data += magic_len; 2048 2049 /* loop elements */ 2050 while (len > sizeof(struct ath10k_fw_ie)) { 2051 hdr = (struct ath10k_fw_ie *)data; 2052 2053 ie_id = le32_to_cpu(hdr->id); 2054 ie_len = le32_to_cpu(hdr->len); 2055 2056 len -= sizeof(*hdr); 2057 data += sizeof(*hdr); 2058 2059 if (len < ie_len) { 2060 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 2061 ie_id, len, ie_len); 2062 ret = -EINVAL; 2063 goto err; 2064 } 2065 2066 switch (ie_id) { 2067 case ATH10K_FW_IE_FW_VERSION: 2068 if (ie_len > sizeof(fw_file->fw_version) - 1) 2069 break; 2070 2071 memcpy(fw_file->fw_version, data, ie_len); 2072 fw_file->fw_version[ie_len] = '\0'; 2073 2074 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2075 "found fw version %s\n", 2076 fw_file->fw_version); 2077 break; 2078 case ATH10K_FW_IE_TIMESTAMP: 2079 if (ie_len != sizeof(u32)) 2080 break; 2081 2082 timestamp = (__le32 *)data; 2083 2084 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2085 le32_to_cpup(timestamp)); 2086 break; 2087 case ATH10K_FW_IE_FEATURES: 2088 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2089 "found firmware features ie (%zd B)\n", 2090 ie_len); 2091 2092 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2093 index = i / 8; 2094 bit = i % 8; 2095 2096 if (index == ie_len) 2097 break; 2098 2099 if (data[index] & (1 << bit)) { 2100 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2101 "Enabling feature bit: %i\n", 2102 i); 2103 __set_bit(i, fw_file->fw_features); 2104 } 2105 } 2106 2107 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2108 fw_file->fw_features, 2109 sizeof(fw_file->fw_features)); 2110 break; 2111 case ATH10K_FW_IE_FW_IMAGE: 2112 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2113 "found fw image ie (%zd B)\n", 2114 ie_len); 2115 2116 fw_file->firmware_data = data; 2117 fw_file->firmware_len = ie_len; 2118 2119 break; 2120 case ATH10K_FW_IE_OTP_IMAGE: 2121 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2122 "found otp image ie (%zd B)\n", 2123 ie_len); 2124 2125 fw_file->otp_data = data; 2126 fw_file->otp_len = ie_len; 2127 2128 break; 2129 case ATH10K_FW_IE_WMI_OP_VERSION: 2130 if (ie_len != sizeof(u32)) 2131 break; 2132 2133 version = (__le32 *)data; 2134 2135 fw_file->wmi_op_version = le32_to_cpup(version); 2136 2137 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2138 fw_file->wmi_op_version); 2139 break; 2140 case ATH10K_FW_IE_HTT_OP_VERSION: 2141 if (ie_len != sizeof(u32)) 2142 break; 2143 2144 version = (__le32 *)data; 2145 2146 fw_file->htt_op_version = le32_to_cpup(version); 2147 2148 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2149 fw_file->htt_op_version); 2150 break; 2151 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2152 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2153 "found fw code swap image ie (%zd B)\n", 2154 ie_len); 2155 fw_file->codeswap_data = data; 2156 fw_file->codeswap_len = ie_len; 2157 break; 2158 default: 2159 ath10k_warn(ar, "Unknown FW IE: %u\n", 2160 le32_to_cpu(hdr->id)); 2161 break; 2162 } 2163 2164 /* jump over the padding */ 2165 ie_len = ALIGN(ie_len, 4); 2166 2167 len -= ie_len; 2168 data += ie_len; 2169 } 2170 2171 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2172 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2173 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2174 ar->hw_params.fw.dir, name); 2175 ret = -ENOMEDIUM; 2176 goto err; 2177 } 2178 2179 return 0; 2180 2181 err: 2182 ath10k_core_free_firmware_files(ar); 2183 return ret; 2184 } 2185 2186 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2187 size_t fw_name_len, int fw_api) 2188 { 2189 switch (ar->hif.bus) { 2190 case ATH10K_BUS_SDIO: 2191 case ATH10K_BUS_USB: 2192 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2193 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2194 fw_api); 2195 break; 2196 case ATH10K_BUS_PCI: 2197 case ATH10K_BUS_AHB: 2198 case ATH10K_BUS_SNOC: 2199 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2200 ATH10K_FW_FILE_BASE, fw_api); 2201 break; 2202 } 2203 } 2204 2205 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2206 { 2207 int ret, i; 2208 char fw_name[100]; 2209 2210 /* calibration file is optional, don't check for any errors */ 2211 ath10k_fetch_cal_file(ar); 2212 2213 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2214 ar->fw_api = i; 2215 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2216 ar->fw_api); 2217 2218 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2219 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2220 &ar->normal_mode_fw.fw_file); 2221 if (!ret) 2222 goto success; 2223 } 2224 2225 /* we end up here if we couldn't fetch any firmware */ 2226 2227 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2228 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2229 ret); 2230 2231 return ret; 2232 2233 success: 2234 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2235 2236 return 0; 2237 } 2238 2239 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2240 { 2241 int ret; 2242 2243 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2244 if (ret == 0) { 2245 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2246 goto success; 2247 } else if (ret == -EPROBE_DEFER) { 2248 return ret; 2249 } 2250 2251 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2252 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2253 ret); 2254 2255 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2256 if (ret == 0) { 2257 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2258 goto success; 2259 } 2260 2261 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2262 "boot did not find a pre calibration file, try DT next: %d\n", 2263 ret); 2264 2265 ret = ath10k_download_cal_dt(ar, "qcom,pre-calibration-data"); 2266 if (ret == -ENOENT) 2267 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2268 if (ret) { 2269 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2270 "unable to load pre cal data from DT: %d\n", ret); 2271 return ret; 2272 } 2273 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2274 2275 success: 2276 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2277 ath10k_cal_mode_str(ar->cal_mode)); 2278 2279 return 0; 2280 } 2281 2282 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2283 { 2284 int ret; 2285 2286 ret = ath10k_core_pre_cal_download(ar); 2287 if (ret) { 2288 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2289 "failed to load pre cal data: %d\n", ret); 2290 return ret; 2291 } 2292 2293 ret = ath10k_core_get_board_id_from_otp(ar); 2294 if (ret) { 2295 ath10k_err(ar, "failed to get board id: %d\n", ret); 2296 return ret; 2297 } 2298 2299 ret = ath10k_download_and_run_otp(ar); 2300 if (ret) { 2301 ath10k_err(ar, "failed to run otp: %d\n", ret); 2302 return ret; 2303 } 2304 2305 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2306 "pre cal configuration done successfully\n"); 2307 2308 return 0; 2309 } 2310 2311 static int ath10k_download_cal_data(struct ath10k *ar) 2312 { 2313 int ret; 2314 2315 ret = ath10k_core_pre_cal_config(ar); 2316 if (ret == 0) 2317 return 0; 2318 2319 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2320 "pre cal download procedure failed, try cal file: %d\n", 2321 ret); 2322 2323 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2324 if (ret == 0) { 2325 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2326 goto done; 2327 } else if (ret == -EPROBE_DEFER) { 2328 return ret; 2329 } 2330 2331 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2332 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2333 ret); 2334 2335 ret = ath10k_download_cal_file(ar, ar->cal_file); 2336 if (ret == 0) { 2337 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2338 goto done; 2339 } 2340 2341 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2342 "boot did not find a calibration file, try DT next: %d\n", 2343 ret); 2344 2345 ret = ath10k_download_cal_dt(ar, "qcom,calibration-data"); 2346 if (ret == -ENOENT) 2347 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2348 if (ret == 0) { 2349 ar->cal_mode = ATH10K_CAL_MODE_DT; 2350 goto done; 2351 } 2352 2353 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2354 "boot did not find DT entry, try target EEPROM next: %d\n", 2355 ret); 2356 2357 ret = ath10k_download_cal_eeprom(ar); 2358 if (ret == 0) { 2359 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2360 goto done; 2361 } 2362 2363 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2364 "boot did not find target EEPROM entry, try OTP next: %d\n", 2365 ret); 2366 2367 ret = ath10k_download_and_run_otp(ar); 2368 if (ret) { 2369 ath10k_err(ar, "failed to run otp: %d\n", ret); 2370 return ret; 2371 } 2372 2373 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2374 2375 done: 2376 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2377 ath10k_cal_mode_str(ar->cal_mode)); 2378 return 0; 2379 } 2380 2381 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2382 { 2383 struct device_node *node; 2384 u8 coex_support = 0; 2385 int ret; 2386 2387 node = ar->dev->of_node; 2388 if (!node) 2389 goto out; 2390 2391 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2392 if (ret) { 2393 ar->coex_support = true; 2394 goto out; 2395 } 2396 2397 if (coex_support) { 2398 ar->coex_support = true; 2399 } else { 2400 ar->coex_support = false; 2401 ar->coex_gpio_pin = -1; 2402 goto out; 2403 } 2404 2405 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2406 &ar->coex_gpio_pin); 2407 if (ret) 2408 ar->coex_gpio_pin = -1; 2409 2410 out: 2411 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2412 ar->coex_support, ar->coex_gpio_pin); 2413 } 2414 2415 static int ath10k_init_uart(struct ath10k *ar) 2416 { 2417 int ret; 2418 2419 /* 2420 * Explicitly setting UART prints to zero as target turns it on 2421 * based on scratch registers. 2422 */ 2423 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2424 if (ret) { 2425 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2426 return ret; 2427 } 2428 2429 if (!uart_print) { 2430 if (ar->hw_params.uart_pin_workaround) { 2431 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2432 ar->hw_params.uart_pin); 2433 if (ret) { 2434 ath10k_warn(ar, "failed to set UART TX pin: %d", 2435 ret); 2436 return ret; 2437 } 2438 } 2439 2440 return 0; 2441 } 2442 2443 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2444 if (ret) { 2445 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2446 return ret; 2447 } 2448 2449 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2450 if (ret) { 2451 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2452 return ret; 2453 } 2454 2455 /* Set the UART baud rate to 19200. */ 2456 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2457 if (ret) { 2458 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2459 return ret; 2460 } 2461 2462 ath10k_info(ar, "UART prints enabled\n"); 2463 return 0; 2464 } 2465 2466 static int ath10k_init_hw_params(struct ath10k *ar) 2467 { 2468 const struct ath10k_hw_params *hw_params; 2469 int i; 2470 2471 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2472 hw_params = &ath10k_hw_params_list[i]; 2473 2474 if (hw_params->bus == ar->hif.bus && 2475 hw_params->id == ar->target_version && 2476 hw_params->dev_id == ar->dev_id) 2477 break; 2478 } 2479 2480 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2481 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2482 ar->target_version); 2483 return -EINVAL; 2484 } 2485 2486 ar->hw_params = *hw_params; 2487 2488 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2489 ar->hw_params.name, ar->target_version); 2490 2491 return 0; 2492 } 2493 2494 void ath10k_core_start_recovery(struct ath10k *ar) 2495 { 2496 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2497 ath10k_warn(ar, "already restarting\n"); 2498 return; 2499 } 2500 2501 queue_work(ar->workqueue, &ar->restart_work); 2502 } 2503 EXPORT_SYMBOL(ath10k_core_start_recovery); 2504 2505 void ath10k_core_napi_enable(struct ath10k *ar) 2506 { 2507 lockdep_assert_held(&ar->conf_mutex); 2508 2509 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2510 return; 2511 2512 napi_enable(&ar->napi); 2513 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2514 } 2515 EXPORT_SYMBOL(ath10k_core_napi_enable); 2516 2517 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2518 { 2519 lockdep_assert_held(&ar->conf_mutex); 2520 2521 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2522 return; 2523 2524 napi_synchronize(&ar->napi); 2525 napi_disable(&ar->napi); 2526 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2527 } 2528 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2529 2530 static void ath10k_core_restart(struct work_struct *work) 2531 { 2532 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2533 int ret; 2534 2535 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2536 2537 /* Place a barrier to make sure the compiler doesn't reorder 2538 * CRASH_FLUSH and calling other functions. 2539 */ 2540 barrier(); 2541 2542 ieee80211_stop_queues(ar->hw); 2543 ath10k_drain_tx(ar); 2544 complete(&ar->scan.started); 2545 complete(&ar->scan.completed); 2546 complete(&ar->scan.on_channel); 2547 complete(&ar->offchan_tx_completed); 2548 complete(&ar->install_key_done); 2549 complete(&ar->vdev_setup_done); 2550 complete(&ar->vdev_delete_done); 2551 complete(&ar->thermal.wmi_sync); 2552 complete(&ar->bss_survey_done); 2553 wake_up(&ar->htt.empty_tx_wq); 2554 wake_up(&ar->wmi.tx_credits_wq); 2555 wake_up(&ar->peer_mapping_wq); 2556 2557 /* TODO: We can have one instance of cancelling coverage_class_work by 2558 * moving it to ath10k_halt(), so that both stop() and restart() would 2559 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2560 * with conf_mutex it will deadlock. 2561 */ 2562 cancel_work_sync(&ar->set_coverage_class_work); 2563 2564 mutex_lock(&ar->conf_mutex); 2565 2566 switch (ar->state) { 2567 case ATH10K_STATE_ON: 2568 ar->state = ATH10K_STATE_RESTARTING; 2569 ath10k_halt(ar); 2570 ath10k_scan_finish(ar); 2571 ieee80211_restart_hw(ar->hw); 2572 break; 2573 case ATH10K_STATE_OFF: 2574 /* this can happen if driver is being unloaded 2575 * or if the crash happens during FW probing 2576 */ 2577 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2578 break; 2579 case ATH10K_STATE_RESTARTING: 2580 /* hw restart might be requested from multiple places */ 2581 break; 2582 case ATH10K_STATE_RESTARTED: 2583 ar->state = ATH10K_STATE_WEDGED; 2584 fallthrough; 2585 case ATH10K_STATE_WEDGED: 2586 ath10k_warn(ar, "device is wedged, will not restart\n"); 2587 break; 2588 case ATH10K_STATE_UTF: 2589 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2590 break; 2591 } 2592 2593 mutex_unlock(&ar->conf_mutex); 2594 2595 ret = ath10k_coredump_submit(ar); 2596 if (ret) 2597 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2598 ret); 2599 2600 complete(&ar->driver_recovery); 2601 } 2602 2603 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2604 { 2605 struct ath10k *ar = container_of(work, struct ath10k, 2606 set_coverage_class_work); 2607 2608 if (ar->hw_params.hw_ops->set_coverage_class) 2609 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2610 } 2611 2612 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2613 { 2614 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2615 int max_num_peers; 2616 2617 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2618 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2619 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2620 return -EINVAL; 2621 } 2622 2623 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2624 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2625 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2626 return -EINVAL; 2627 } 2628 2629 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2630 switch (ath10k_cryptmode_param) { 2631 case ATH10K_CRYPT_MODE_HW: 2632 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2633 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2634 break; 2635 case ATH10K_CRYPT_MODE_SW: 2636 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2637 fw_file->fw_features)) { 2638 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2639 return -EINVAL; 2640 } 2641 2642 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2643 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2644 break; 2645 default: 2646 ath10k_info(ar, "invalid cryptmode: %d\n", 2647 ath10k_cryptmode_param); 2648 return -EINVAL; 2649 } 2650 2651 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2652 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2653 2654 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) { 2655 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2656 fw_file->fw_features)) { 2657 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2658 return -EINVAL; 2659 } 2660 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2661 } 2662 2663 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2664 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2665 2666 /* Workaround: 2667 * 2668 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2669 * and causes enormous performance issues (malformed frames, 2670 * etc). 2671 * 2672 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2673 * albeit a bit slower compared to regular operation. 2674 */ 2675 ar->htt.max_num_amsdu = 1; 2676 } 2677 2678 /* Backwards compatibility for firmwares without 2679 * ATH10K_FW_IE_WMI_OP_VERSION. 2680 */ 2681 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2682 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2683 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2684 fw_file->fw_features)) 2685 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2686 else 2687 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2688 } else { 2689 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2690 } 2691 } 2692 2693 switch (fw_file->wmi_op_version) { 2694 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2695 max_num_peers = TARGET_NUM_PEERS; 2696 ar->max_num_stations = TARGET_NUM_STATIONS; 2697 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2698 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2699 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2700 WMI_STAT_PEER; 2701 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2702 break; 2703 case ATH10K_FW_WMI_OP_VERSION_10_1: 2704 case ATH10K_FW_WMI_OP_VERSION_10_2: 2705 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2706 if (ath10k_peer_stats_enabled(ar)) { 2707 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2708 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2709 } else { 2710 max_num_peers = TARGET_10X_NUM_PEERS; 2711 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2712 } 2713 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2714 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2715 ar->fw_stats_req_mask = WMI_STAT_PEER; 2716 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2717 break; 2718 case ATH10K_FW_WMI_OP_VERSION_TLV: 2719 max_num_peers = TARGET_TLV_NUM_PEERS; 2720 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2721 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2722 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2723 if (ar->hif.bus == ATH10K_BUS_SDIO) 2724 ar->htt.max_num_pending_tx = 2725 TARGET_TLV_NUM_MSDU_DESC_HL; 2726 else 2727 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2728 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2729 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2730 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2731 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2732 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2733 break; 2734 case ATH10K_FW_WMI_OP_VERSION_10_4: 2735 max_num_peers = TARGET_10_4_NUM_PEERS; 2736 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2737 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2738 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2739 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2740 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2741 WMI_10_4_STAT_PEER_EXTD | 2742 WMI_10_4_STAT_VDEV_EXTD; 2743 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2744 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2745 2746 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2747 fw_file->fw_features)) 2748 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2749 else 2750 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2751 break; 2752 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2753 case ATH10K_FW_WMI_OP_VERSION_MAX: 2754 default: 2755 WARN_ON(1); 2756 return -EINVAL; 2757 } 2758 2759 if (ar->hw_params.num_peers) 2760 ar->max_num_peers = ar->hw_params.num_peers; 2761 else 2762 ar->max_num_peers = max_num_peers; 2763 2764 /* Backwards compatibility for firmwares without 2765 * ATH10K_FW_IE_HTT_OP_VERSION. 2766 */ 2767 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2768 switch (fw_file->wmi_op_version) { 2769 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2770 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2771 break; 2772 case ATH10K_FW_WMI_OP_VERSION_10_1: 2773 case ATH10K_FW_WMI_OP_VERSION_10_2: 2774 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2775 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2776 break; 2777 case ATH10K_FW_WMI_OP_VERSION_TLV: 2778 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2779 break; 2780 case ATH10K_FW_WMI_OP_VERSION_10_4: 2781 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2782 case ATH10K_FW_WMI_OP_VERSION_MAX: 2783 ath10k_err(ar, "htt op version not found from fw meta data"); 2784 return -EINVAL; 2785 } 2786 } 2787 2788 return 0; 2789 } 2790 2791 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2792 { 2793 int ret; 2794 int vdev_id; 2795 int vdev_type; 2796 int vdev_subtype; 2797 const u8 *vdev_addr; 2798 2799 vdev_id = 0; 2800 vdev_type = WMI_VDEV_TYPE_STA; 2801 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2802 vdev_addr = ar->mac_addr; 2803 2804 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2805 vdev_addr); 2806 if (ret) { 2807 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2808 return ret; 2809 } 2810 2811 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2812 if (ret) { 2813 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2814 return ret; 2815 } 2816 2817 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2818 * serialized properly implicitly. 2819 * 2820 * Moreover (most) WMI commands have no explicit acknowledges. It is 2821 * possible to infer it implicitly by poking firmware with echo 2822 * command - getting a reply means all preceding comments have been 2823 * (mostly) processed. 2824 * 2825 * In case of vdev create/delete this is sufficient. 2826 * 2827 * Without this it's possible to end up with a race when HTT Rx ring is 2828 * started before vdev create/delete hack is complete allowing a short 2829 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2830 */ 2831 ret = ath10k_wmi_barrier(ar); 2832 if (ret) { 2833 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2834 return ret; 2835 } 2836 2837 return 0; 2838 } 2839 2840 static int ath10k_core_compat_services(struct ath10k *ar) 2841 { 2842 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2843 2844 /* all 10.x firmware versions support thermal throttling but don't 2845 * advertise the support via service flags so we have to hardcode 2846 * it here 2847 */ 2848 switch (fw_file->wmi_op_version) { 2849 case ATH10K_FW_WMI_OP_VERSION_10_1: 2850 case ATH10K_FW_WMI_OP_VERSION_10_2: 2851 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2852 case ATH10K_FW_WMI_OP_VERSION_10_4: 2853 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2854 break; 2855 default: 2856 break; 2857 } 2858 2859 return 0; 2860 } 2861 2862 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2863 2864 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2865 { 2866 const struct ath10k_hw_mem_layout *hw_mem; 2867 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2868 dma_addr_t paddr; 2869 void *vaddr = NULL; 2870 u8 num_read_itr; 2871 int i, ret; 2872 u32 len, remaining_len; 2873 2874 /* copy target iram feature must work also when 2875 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2876 * _ath10k_coredump_get_mem_layout() to accomplist that 2877 */ 2878 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2879 if (!hw_mem) 2880 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2881 * just silently disable the feature by doing nothing 2882 */ 2883 return 0; 2884 2885 for (i = 0; i < hw_mem->region_table.size; i++) { 2886 tmp = &hw_mem->region_table.regions[i]; 2887 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2888 mem_region = tmp; 2889 break; 2890 } 2891 } 2892 2893 if (!mem_region) 2894 return -ENOMEM; 2895 2896 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2897 if (ar->wmi.mem_chunks[i].req_id == 2898 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2899 vaddr = ar->wmi.mem_chunks[i].vaddr; 2900 len = ar->wmi.mem_chunks[i].len; 2901 break; 2902 } 2903 } 2904 2905 if (!vaddr || !len) { 2906 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2907 return -ENOMEM; 2908 } 2909 2910 len = (len < mem_region->len) ? len : mem_region->len; 2911 paddr = mem_region->start; 2912 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2913 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2914 for (i = 0; i < num_read_itr; i++) { 2915 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2916 TGT_IRAM_READ_PER_ITR); 2917 if (ret) { 2918 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2919 ret); 2920 return ret; 2921 } 2922 2923 paddr += TGT_IRAM_READ_PER_ITR; 2924 vaddr += TGT_IRAM_READ_PER_ITR; 2925 } 2926 2927 if (remaining_len) { 2928 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2929 if (ret) { 2930 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2931 ret); 2932 return ret; 2933 } 2934 } 2935 2936 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2937 2938 return 0; 2939 } 2940 2941 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2942 const struct ath10k_fw_components *fw) 2943 { 2944 int status; 2945 u32 val; 2946 2947 lockdep_assert_held(&ar->conf_mutex); 2948 2949 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2950 2951 ar->running_fw = fw; 2952 2953 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2954 ar->running_fw->fw_file.fw_features)) { 2955 ath10k_bmi_start(ar); 2956 2957 /* Enable hardware clock to speed up firmware download */ 2958 if (ar->hw_params.hw_ops->enable_pll_clk) { 2959 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2960 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2961 status); 2962 } 2963 2964 if (ath10k_init_configure_target(ar)) { 2965 status = -EINVAL; 2966 goto err; 2967 } 2968 2969 status = ath10k_download_cal_data(ar); 2970 if (status) 2971 goto err; 2972 2973 /* Some of qca988x solutions are having global reset issue 2974 * during target initialization. Bypassing PLL setting before 2975 * downloading firmware and letting the SoC run on REF_CLK is 2976 * fixing the problem. Corresponding firmware change is also 2977 * needed to set the clock source once the target is 2978 * initialized. 2979 */ 2980 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2981 ar->running_fw->fw_file.fw_features)) { 2982 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2983 if (status) { 2984 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2985 status); 2986 goto err; 2987 } 2988 } 2989 2990 status = ath10k_download_fw(ar); 2991 if (status) 2992 goto err; 2993 2994 status = ath10k_init_uart(ar); 2995 if (status) 2996 goto err; 2997 2998 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2999 status = ath10k_init_sdio(ar, mode); 3000 if (status) { 3001 ath10k_err(ar, "failed to init SDIO: %d\n", status); 3002 goto err; 3003 } 3004 } 3005 } 3006 3007 ar->htc.htc_ops.target_send_suspend_complete = 3008 ath10k_send_suspend_complete; 3009 3010 status = ath10k_htc_init(ar); 3011 if (status) { 3012 ath10k_err(ar, "could not init HTC (%d)\n", status); 3013 goto err; 3014 } 3015 3016 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3017 ar->running_fw->fw_file.fw_features)) { 3018 status = ath10k_bmi_done(ar); 3019 if (status) 3020 goto err; 3021 } 3022 3023 status = ath10k_wmi_attach(ar); 3024 if (status) { 3025 ath10k_err(ar, "WMI attach failed: %d\n", status); 3026 goto err; 3027 } 3028 3029 status = ath10k_htt_init(ar); 3030 if (status) { 3031 ath10k_err(ar, "failed to init htt: %d\n", status); 3032 goto err_wmi_detach; 3033 } 3034 3035 status = ath10k_htt_tx_start(&ar->htt); 3036 if (status) { 3037 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 3038 goto err_wmi_detach; 3039 } 3040 3041 /* If firmware indicates Full Rx Reorder support it must be used in a 3042 * slightly different manner. Let HTT code know. 3043 */ 3044 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 3045 ar->wmi.svc_map)); 3046 3047 status = ath10k_htt_rx_alloc(&ar->htt); 3048 if (status) { 3049 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 3050 goto err_htt_tx_detach; 3051 } 3052 3053 status = ath10k_hif_start(ar); 3054 if (status) { 3055 ath10k_err(ar, "could not start HIF: %d\n", status); 3056 goto err_htt_rx_detach; 3057 } 3058 3059 status = ath10k_htc_wait_target(&ar->htc); 3060 if (status) { 3061 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 3062 goto err_hif_stop; 3063 } 3064 3065 status = ath10k_hif_start_post(ar); 3066 if (status) { 3067 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3068 goto err_hif_stop; 3069 } 3070 3071 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3072 status = ath10k_htt_connect(&ar->htt); 3073 if (status) { 3074 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3075 goto err_hif_stop; 3076 } 3077 } 3078 3079 status = ath10k_wmi_connect(ar); 3080 if (status) { 3081 ath10k_err(ar, "could not connect wmi: %d\n", status); 3082 goto err_hif_stop; 3083 } 3084 3085 status = ath10k_htc_start(&ar->htc); 3086 if (status) { 3087 ath10k_err(ar, "failed to start htc: %d\n", status); 3088 goto err_hif_stop; 3089 } 3090 3091 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3092 status = ath10k_wmi_wait_for_service_ready(ar); 3093 if (status) { 3094 ath10k_warn(ar, "wmi service ready event not received"); 3095 goto err_hif_stop; 3096 } 3097 } 3098 3099 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3100 ar->hw->wiphy->fw_version); 3101 3102 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3103 ar->running_fw->fw_file.fw_features)) { 3104 status = ath10k_core_copy_target_iram(ar); 3105 if (status) { 3106 ath10k_warn(ar, "failed to copy target iram contents: %d", 3107 status); 3108 goto err_hif_stop; 3109 } 3110 } 3111 3112 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3113 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3114 val = 0; 3115 if (ath10k_peer_stats_enabled(ar)) 3116 val = WMI_10_4_PEER_STATS; 3117 3118 /* Enable vdev stats by default */ 3119 val |= WMI_10_4_VDEV_STATS; 3120 3121 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3122 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3123 3124 ath10k_core_fetch_btcoex_dt(ar); 3125 3126 /* 10.4 firmware supports BT-Coex without reloading firmware 3127 * via pdev param. To support Bluetooth coexistence pdev param, 3128 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3129 * enabled always. 3130 * 3131 * We can still enable BTCOEX if firmware has the support 3132 * even though btceox_support value is 3133 * ATH10K_DT_BTCOEX_NOT_FOUND 3134 */ 3135 3136 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3137 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3138 ar->running_fw->fw_file.fw_features) && 3139 ar->coex_support) 3140 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3141 3142 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3143 ar->wmi.svc_map)) 3144 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3145 3146 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3147 ar->wmi.svc_map)) 3148 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3149 3150 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3151 ar->wmi.svc_map)) 3152 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3153 3154 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3155 val |= WMI_10_4_REPORT_AIRTIME; 3156 3157 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3158 ar->wmi.svc_map)) 3159 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3160 3161 status = ath10k_mac_ext_resource_config(ar, val); 3162 if (status) { 3163 ath10k_err(ar, 3164 "failed to send ext resource cfg command : %d\n", 3165 status); 3166 goto err_hif_stop; 3167 } 3168 } 3169 3170 status = ath10k_wmi_cmd_init(ar); 3171 if (status) { 3172 ath10k_err(ar, "could not send WMI init command (%d)\n", 3173 status); 3174 goto err_hif_stop; 3175 } 3176 3177 status = ath10k_wmi_wait_for_unified_ready(ar); 3178 if (status) { 3179 ath10k_err(ar, "wmi unified ready event not received\n"); 3180 goto err_hif_stop; 3181 } 3182 3183 status = ath10k_core_compat_services(ar); 3184 if (status) { 3185 ath10k_err(ar, "compat services failed: %d\n", status); 3186 goto err_hif_stop; 3187 } 3188 3189 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3190 if (status && status != -EOPNOTSUPP) { 3191 ath10k_err(ar, 3192 "failed to set base mac address: %d\n", status); 3193 goto err_hif_stop; 3194 } 3195 3196 /* Some firmware revisions do not properly set up hardware rx filter 3197 * registers. 3198 * 3199 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3200 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3201 * any frames that matches MAC_PCU_RX_FILTER which is also 3202 * misconfigured to accept anything. 3203 * 3204 * The ADDR1 is programmed using internal firmware structure field and 3205 * can't be (easily/sanely) reached from the driver explicitly. It is 3206 * possible to implicitly make it correct by creating a dummy vdev and 3207 * then deleting it. 3208 */ 3209 if (ar->hw_params.hw_filter_reset_required && 3210 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3211 status = ath10k_core_reset_rx_filter(ar); 3212 if (status) { 3213 ath10k_err(ar, 3214 "failed to reset rx filter: %d\n", status); 3215 goto err_hif_stop; 3216 } 3217 } 3218 3219 status = ath10k_htt_rx_ring_refill(ar); 3220 if (status) { 3221 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3222 goto err_hif_stop; 3223 } 3224 3225 if (ar->max_num_vdevs >= 64) 3226 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3227 else 3228 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3229 3230 INIT_LIST_HEAD(&ar->arvifs); 3231 3232 /* we don't care about HTT in UTF mode */ 3233 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3234 status = ath10k_htt_setup(&ar->htt); 3235 if (status) { 3236 ath10k_err(ar, "failed to setup htt: %d\n", status); 3237 goto err_hif_stop; 3238 } 3239 } 3240 3241 status = ath10k_debug_start(ar); 3242 if (status) 3243 goto err_hif_stop; 3244 3245 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3246 if (status && status != -EOPNOTSUPP) { 3247 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3248 goto err_hif_stop; 3249 } 3250 3251 status = ath10k_leds_start(ar); 3252 if (status) 3253 goto err_hif_stop; 3254 3255 return 0; 3256 3257 err_hif_stop: 3258 ath10k_hif_stop(ar); 3259 err_htt_rx_detach: 3260 ath10k_htt_rx_free(&ar->htt); 3261 err_htt_tx_detach: 3262 ath10k_htt_tx_free(&ar->htt); 3263 err_wmi_detach: 3264 ath10k_wmi_detach(ar); 3265 err: 3266 return status; 3267 } 3268 EXPORT_SYMBOL(ath10k_core_start); 3269 3270 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3271 { 3272 int ret; 3273 unsigned long time_left; 3274 3275 reinit_completion(&ar->target_suspend); 3276 3277 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3278 if (ret) { 3279 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3280 return ret; 3281 } 3282 3283 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3284 3285 if (!time_left) { 3286 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3287 return -ETIMEDOUT; 3288 } 3289 3290 return 0; 3291 } 3292 3293 void ath10k_core_stop(struct ath10k *ar) 3294 { 3295 lockdep_assert_held(&ar->conf_mutex); 3296 ath10k_debug_stop(ar); 3297 3298 /* try to suspend target */ 3299 if (ar->state != ATH10K_STATE_RESTARTING && 3300 ar->state != ATH10K_STATE_UTF) 3301 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3302 3303 ath10k_hif_stop(ar); 3304 ath10k_htt_tx_stop(&ar->htt); 3305 ath10k_htt_rx_free(&ar->htt); 3306 ath10k_wmi_detach(ar); 3307 3308 ar->id.bmi_ids_valid = false; 3309 } 3310 EXPORT_SYMBOL(ath10k_core_stop); 3311 3312 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3313 * order to know what hw capabilities should be advertised to mac80211 it is 3314 * necessary to load the firmware (and tear it down immediately since start 3315 * hook will try to init it again) before registering 3316 */ 3317 static int ath10k_core_probe_fw(struct ath10k *ar) 3318 { 3319 struct bmi_target_info target_info; 3320 int ret = 0; 3321 3322 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3323 if (ret) { 3324 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3325 return ret; 3326 } 3327 3328 switch (ar->hif.bus) { 3329 case ATH10K_BUS_SDIO: 3330 memset(&target_info, 0, sizeof(target_info)); 3331 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3332 if (ret) { 3333 ath10k_err(ar, "could not get target info (%d)\n", ret); 3334 goto err_power_down; 3335 } 3336 ar->target_version = target_info.version; 3337 ar->hw->wiphy->hw_version = target_info.version; 3338 break; 3339 case ATH10K_BUS_PCI: 3340 case ATH10K_BUS_AHB: 3341 case ATH10K_BUS_USB: 3342 memset(&target_info, 0, sizeof(target_info)); 3343 ret = ath10k_bmi_get_target_info(ar, &target_info); 3344 if (ret) { 3345 ath10k_err(ar, "could not get target info (%d)\n", ret); 3346 goto err_power_down; 3347 } 3348 ar->target_version = target_info.version; 3349 ar->hw->wiphy->hw_version = target_info.version; 3350 break; 3351 case ATH10K_BUS_SNOC: 3352 memset(&target_info, 0, sizeof(target_info)); 3353 ret = ath10k_hif_get_target_info(ar, &target_info); 3354 if (ret) { 3355 ath10k_err(ar, "could not get target info (%d)\n", ret); 3356 goto err_power_down; 3357 } 3358 ar->target_version = target_info.version; 3359 ar->hw->wiphy->hw_version = target_info.version; 3360 break; 3361 default: 3362 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3363 } 3364 3365 ret = ath10k_init_hw_params(ar); 3366 if (ret) { 3367 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3368 goto err_power_down; 3369 } 3370 3371 ret = ath10k_core_fetch_firmware_files(ar); 3372 if (ret) { 3373 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3374 goto err_power_down; 3375 } 3376 3377 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3378 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3379 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3380 sizeof(ar->hw->wiphy->fw_version)); 3381 3382 ath10k_debug_print_hwfw_info(ar); 3383 3384 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3385 ar->normal_mode_fw.fw_file.fw_features)) { 3386 ret = ath10k_core_pre_cal_download(ar); 3387 if (ret) { 3388 /* pre calibration data download is not necessary 3389 * for all the chipsets. Ignore failures and continue. 3390 */ 3391 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3392 "could not load pre cal data: %d\n", ret); 3393 } 3394 3395 ret = ath10k_core_get_board_id_from_otp(ar); 3396 if (ret && ret != -EOPNOTSUPP) { 3397 ath10k_err(ar, "failed to get board id from otp: %d\n", 3398 ret); 3399 goto err_free_firmware_files; 3400 } 3401 3402 ret = ath10k_core_check_smbios(ar); 3403 if (ret) 3404 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3405 3406 ret = ath10k_core_check_dt(ar); 3407 if (ret) 3408 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3409 3410 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3411 if (ret) { 3412 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3413 goto err_free_firmware_files; 3414 } 3415 3416 ath10k_debug_print_board_info(ar); 3417 } 3418 3419 device_get_mac_address(ar->dev, ar->mac_addr); 3420 3421 ret = ath10k_core_init_firmware_features(ar); 3422 if (ret) { 3423 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3424 ret); 3425 goto err_free_firmware_files; 3426 } 3427 3428 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3429 ar->normal_mode_fw.fw_file.fw_features)) { 3430 ret = ath10k_swap_code_seg_init(ar, 3431 &ar->normal_mode_fw.fw_file); 3432 if (ret) { 3433 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3434 ret); 3435 goto err_free_firmware_files; 3436 } 3437 } 3438 3439 mutex_lock(&ar->conf_mutex); 3440 3441 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3442 &ar->normal_mode_fw); 3443 if (ret) { 3444 ath10k_err(ar, "could not init core (%d)\n", ret); 3445 goto err_unlock; 3446 } 3447 3448 ath10k_debug_print_boot_info(ar); 3449 ath10k_core_stop(ar); 3450 3451 mutex_unlock(&ar->conf_mutex); 3452 3453 ath10k_hif_power_down(ar); 3454 return 0; 3455 3456 err_unlock: 3457 mutex_unlock(&ar->conf_mutex); 3458 3459 err_free_firmware_files: 3460 ath10k_core_free_firmware_files(ar); 3461 3462 err_power_down: 3463 ath10k_hif_power_down(ar); 3464 3465 return ret; 3466 } 3467 3468 static void ath10k_core_register_work(struct work_struct *work) 3469 { 3470 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3471 int status; 3472 3473 /* peer stats are enabled by default */ 3474 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3475 3476 status = ath10k_core_probe_fw(ar); 3477 if (status) { 3478 ath10k_err(ar, "could not probe fw (%d)\n", status); 3479 goto err; 3480 } 3481 3482 status = ath10k_mac_register(ar); 3483 if (status) { 3484 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3485 goto err_release_fw; 3486 } 3487 3488 status = ath10k_coredump_register(ar); 3489 if (status) { 3490 ath10k_err(ar, "unable to register coredump\n"); 3491 goto err_unregister_mac; 3492 } 3493 3494 status = ath10k_debug_register(ar); 3495 if (status) { 3496 ath10k_err(ar, "unable to initialize debugfs\n"); 3497 goto err_unregister_coredump; 3498 } 3499 3500 status = ath10k_spectral_create(ar); 3501 if (status) { 3502 ath10k_err(ar, "failed to initialize spectral\n"); 3503 goto err_debug_destroy; 3504 } 3505 3506 status = ath10k_thermal_register(ar); 3507 if (status) { 3508 ath10k_err(ar, "could not register thermal device: %d\n", 3509 status); 3510 goto err_spectral_destroy; 3511 } 3512 3513 status = ath10k_leds_register(ar); 3514 if (status) { 3515 ath10k_err(ar, "could not register leds: %d\n", 3516 status); 3517 goto err_thermal_unregister; 3518 } 3519 3520 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3521 return; 3522 3523 err_thermal_unregister: 3524 ath10k_thermal_unregister(ar); 3525 err_spectral_destroy: 3526 ath10k_spectral_destroy(ar); 3527 err_debug_destroy: 3528 ath10k_debug_destroy(ar); 3529 err_unregister_coredump: 3530 ath10k_coredump_unregister(ar); 3531 err_unregister_mac: 3532 ath10k_mac_unregister(ar); 3533 err_release_fw: 3534 ath10k_core_free_firmware_files(ar); 3535 err: 3536 /* TODO: It's probably a good idea to release device from the driver 3537 * but calling device_release_driver() here will cause a deadlock. 3538 */ 3539 return; 3540 } 3541 3542 int ath10k_core_register(struct ath10k *ar, 3543 const struct ath10k_bus_params *bus_params) 3544 { 3545 ar->bus_param = *bus_params; 3546 3547 queue_work(ar->workqueue, &ar->register_work); 3548 3549 return 0; 3550 } 3551 EXPORT_SYMBOL(ath10k_core_register); 3552 3553 void ath10k_core_unregister(struct ath10k *ar) 3554 { 3555 cancel_work_sync(&ar->register_work); 3556 3557 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3558 return; 3559 3560 ath10k_leds_unregister(ar); 3561 3562 ath10k_thermal_unregister(ar); 3563 /* Stop spectral before unregistering from mac80211 to remove the 3564 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3565 * would be already be free'd recursively, leading to a double free. 3566 */ 3567 ath10k_spectral_destroy(ar); 3568 3569 /* We must unregister from mac80211 before we stop HTC and HIF. 3570 * Otherwise we will fail to submit commands to FW and mac80211 will be 3571 * unhappy about callback failures. 3572 */ 3573 ath10k_mac_unregister(ar); 3574 3575 ath10k_testmode_destroy(ar); 3576 3577 ath10k_core_free_firmware_files(ar); 3578 ath10k_core_free_board_files(ar); 3579 3580 ath10k_debug_unregister(ar); 3581 } 3582 EXPORT_SYMBOL(ath10k_core_unregister); 3583 3584 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3585 enum ath10k_bus bus, 3586 enum ath10k_hw_rev hw_rev, 3587 const struct ath10k_hif_ops *hif_ops) 3588 { 3589 struct ath10k *ar; 3590 int ret; 3591 3592 ar = ath10k_mac_create(priv_size); 3593 if (!ar) 3594 return NULL; 3595 3596 ar->ath_common.priv = ar; 3597 ar->ath_common.hw = ar->hw; 3598 ar->dev = dev; 3599 ar->hw_rev = hw_rev; 3600 ar->hif.ops = hif_ops; 3601 ar->hif.bus = bus; 3602 3603 switch (hw_rev) { 3604 case ATH10K_HW_QCA988X: 3605 case ATH10K_HW_QCA9887: 3606 ar->regs = &qca988x_regs; 3607 ar->hw_ce_regs = &qcax_ce_regs; 3608 ar->hw_values = &qca988x_values; 3609 break; 3610 case ATH10K_HW_QCA6174: 3611 case ATH10K_HW_QCA9377: 3612 ar->regs = &qca6174_regs; 3613 ar->hw_ce_regs = &qcax_ce_regs; 3614 ar->hw_values = &qca6174_values; 3615 break; 3616 case ATH10K_HW_QCA99X0: 3617 case ATH10K_HW_QCA9984: 3618 ar->regs = &qca99x0_regs; 3619 ar->hw_ce_regs = &qcax_ce_regs; 3620 ar->hw_values = &qca99x0_values; 3621 break; 3622 case ATH10K_HW_QCA9888: 3623 ar->regs = &qca99x0_regs; 3624 ar->hw_ce_regs = &qcax_ce_regs; 3625 ar->hw_values = &qca9888_values; 3626 break; 3627 case ATH10K_HW_QCA4019: 3628 ar->regs = &qca4019_regs; 3629 ar->hw_ce_regs = &qcax_ce_regs; 3630 ar->hw_values = &qca4019_values; 3631 break; 3632 case ATH10K_HW_WCN3990: 3633 ar->regs = &wcn3990_regs; 3634 ar->hw_ce_regs = &wcn3990_ce_regs; 3635 ar->hw_values = &wcn3990_values; 3636 break; 3637 default: 3638 ath10k_err(ar, "unsupported core hardware revision %d\n", 3639 hw_rev); 3640 ret = -EOPNOTSUPP; 3641 goto err_free_mac; 3642 } 3643 3644 init_completion(&ar->scan.started); 3645 init_completion(&ar->scan.completed); 3646 init_completion(&ar->scan.on_channel); 3647 init_completion(&ar->target_suspend); 3648 init_completion(&ar->driver_recovery); 3649 init_completion(&ar->wow.wakeup_completed); 3650 3651 init_completion(&ar->install_key_done); 3652 init_completion(&ar->vdev_setup_done); 3653 init_completion(&ar->vdev_delete_done); 3654 init_completion(&ar->thermal.wmi_sync); 3655 init_completion(&ar->bss_survey_done); 3656 init_completion(&ar->peer_delete_done); 3657 init_completion(&ar->peer_stats_info_complete); 3658 3659 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3660 3661 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3662 if (!ar->workqueue) 3663 goto err_free_mac; 3664 3665 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3666 if (!ar->workqueue_aux) 3667 goto err_free_wq; 3668 3669 ar->workqueue_tx_complete = 3670 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3671 if (!ar->workqueue_tx_complete) 3672 goto err_free_aux_wq; 3673 3674 mutex_init(&ar->conf_mutex); 3675 mutex_init(&ar->dump_mutex); 3676 spin_lock_init(&ar->data_lock); 3677 3678 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3679 spin_lock_init(&ar->queue_lock[ac]); 3680 3681 INIT_LIST_HEAD(&ar->peers); 3682 init_waitqueue_head(&ar->peer_mapping_wq); 3683 init_waitqueue_head(&ar->htt.empty_tx_wq); 3684 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3685 3686 skb_queue_head_init(&ar->htt.rx_indication_head); 3687 3688 init_completion(&ar->offchan_tx_completed); 3689 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3690 skb_queue_head_init(&ar->offchan_tx_queue); 3691 3692 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3693 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3694 3695 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3696 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3697 INIT_WORK(&ar->set_coverage_class_work, 3698 ath10k_core_set_coverage_class_work); 3699 3700 ar->napi_dev = alloc_netdev_dummy(0); 3701 if (!ar->napi_dev) 3702 goto err_free_tx_complete; 3703 3704 ret = ath10k_coredump_create(ar); 3705 if (ret) 3706 goto err_free_netdev; 3707 3708 ret = ath10k_debug_create(ar); 3709 if (ret) 3710 goto err_free_coredump; 3711 3712 return ar; 3713 3714 err_free_coredump: 3715 ath10k_coredump_destroy(ar); 3716 err_free_netdev: 3717 free_netdev(ar->napi_dev); 3718 err_free_tx_complete: 3719 destroy_workqueue(ar->workqueue_tx_complete); 3720 err_free_aux_wq: 3721 destroy_workqueue(ar->workqueue_aux); 3722 err_free_wq: 3723 destroy_workqueue(ar->workqueue); 3724 err_free_mac: 3725 ath10k_mac_destroy(ar); 3726 3727 return NULL; 3728 } 3729 EXPORT_SYMBOL(ath10k_core_create); 3730 3731 void ath10k_core_destroy(struct ath10k *ar) 3732 { 3733 destroy_workqueue(ar->workqueue); 3734 3735 destroy_workqueue(ar->workqueue_aux); 3736 3737 destroy_workqueue(ar->workqueue_tx_complete); 3738 3739 free_netdev(ar->napi_dev); 3740 ath10k_debug_destroy(ar); 3741 ath10k_coredump_destroy(ar); 3742 ath10k_htt_tx_destroy(&ar->htt); 3743 ath10k_wmi_free_host_mem(ar); 3744 ath10k_mac_destroy(ar); 3745 } 3746 EXPORT_SYMBOL(ath10k_core_destroy); 3747 3748 MODULE_AUTHOR("Qualcomm Atheros"); 3749 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3750 MODULE_LICENSE("Dual BSD/GPL"); 3751