1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 #include <linux/property.h> 13 #include <linux/dmi.h> 14 #include <linux/ctype.h> 15 #include <linux/pm_qos.h> 16 #include <linux/nvmem-consumer.h> 17 #include <asm/byteorder.h> 18 19 #include "core.h" 20 #include "mac.h" 21 #include "htc.h" 22 #include "hif.h" 23 #include "wmi.h" 24 #include "bmi.h" 25 #include "debug.h" 26 #include "htt.h" 27 #include "testmode.h" 28 #include "wmi-ops.h" 29 #include "coredump.h" 30 31 unsigned int ath10k_debug_mask; 32 EXPORT_SYMBOL(ath10k_debug_mask); 33 34 static unsigned int ath10k_cryptmode_param; 35 static bool uart_print; 36 static bool skip_otp; 37 static bool fw_diag_log; 38 39 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ 40 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 41 42 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 43 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 44 45 /* FIXME: most of these should be readonly */ 46 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 47 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 48 module_param(uart_print, bool, 0644); 49 module_param(skip_otp, bool, 0644); 50 module_param(fw_diag_log, bool, 0644); 51 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); 52 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 53 54 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 55 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 56 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 57 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 58 MODULE_PARM_DESC(frame_mode, 59 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 60 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 61 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 62 63 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 64 { 65 .id = QCA988X_HW_2_0_VERSION, 66 .dev_id = QCA988X_2_0_DEVICE_ID, 67 .bus = ATH10K_BUS_PCI, 68 .name = "qca988x hw2.0", 69 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 70 .uart_pin = 7, 71 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 72 .otp_exe_param = 0, 73 .channel_counters_freq_hz = 88000, 74 .max_probe_resp_desc_thres = 0, 75 .cal_data_len = 2116, 76 .fw = { 77 .dir = QCA988X_HW_2_0_FW_DIR, 78 .board_size = QCA988X_BOARD_DATA_SZ, 79 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 80 }, 81 .rx_desc_ops = &qca988x_rx_desc_ops, 82 .hw_ops = &qca988x_ops, 83 .decap_align_bytes = 4, 84 .spectral_bin_discard = 0, 85 .spectral_bin_offset = 0, 86 .vht160_mcs_rx_highest = 0, 87 .vht160_mcs_tx_highest = 0, 88 .n_cipher_suites = 8, 89 .ast_skid_limit = 0x10, 90 .num_wds_entries = 0x20, 91 .target_64bit = false, 92 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 93 .shadow_reg_support = false, 94 .rri_on_ddr = false, 95 .hw_filter_reset_required = true, 96 .fw_diag_ce_download = false, 97 .credit_size_workaround = false, 98 .tx_stats_over_pktlog = true, 99 .dynamic_sar_support = false, 100 .hw_restart_disconnect = false, 101 .use_fw_tx_credits = true, 102 .delay_unmap_buffer = false, 103 .mcast_frame_registration = false, 104 }, 105 { 106 .id = QCA988X_HW_2_0_VERSION, 107 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 108 .name = "qca988x hw2.0 ubiquiti", 109 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 110 .uart_pin = 7, 111 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 112 .otp_exe_param = 0, 113 .channel_counters_freq_hz = 88000, 114 .max_probe_resp_desc_thres = 0, 115 .cal_data_len = 2116, 116 .fw = { 117 .dir = QCA988X_HW_2_0_FW_DIR, 118 .board_size = QCA988X_BOARD_DATA_SZ, 119 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 120 }, 121 .rx_desc_ops = &qca988x_rx_desc_ops, 122 .hw_ops = &qca988x_ops, 123 .decap_align_bytes = 4, 124 .spectral_bin_discard = 0, 125 .spectral_bin_offset = 0, 126 .vht160_mcs_rx_highest = 0, 127 .vht160_mcs_tx_highest = 0, 128 .n_cipher_suites = 8, 129 .ast_skid_limit = 0x10, 130 .num_wds_entries = 0x20, 131 .target_64bit = false, 132 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 133 .shadow_reg_support = false, 134 .rri_on_ddr = false, 135 .hw_filter_reset_required = true, 136 .fw_diag_ce_download = false, 137 .credit_size_workaround = false, 138 .tx_stats_over_pktlog = true, 139 .dynamic_sar_support = false, 140 .hw_restart_disconnect = false, 141 .use_fw_tx_credits = true, 142 .delay_unmap_buffer = false, 143 .mcast_frame_registration = false, 144 }, 145 { 146 .id = QCA9887_HW_1_0_VERSION, 147 .dev_id = QCA9887_1_0_DEVICE_ID, 148 .bus = ATH10K_BUS_PCI, 149 .name = "qca9887 hw1.0", 150 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 151 .uart_pin = 7, 152 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 153 .otp_exe_param = 0, 154 .channel_counters_freq_hz = 88000, 155 .max_probe_resp_desc_thres = 0, 156 .cal_data_len = 2116, 157 .fw = { 158 .dir = QCA9887_HW_1_0_FW_DIR, 159 .board_size = QCA9887_BOARD_DATA_SZ, 160 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 161 }, 162 .rx_desc_ops = &qca988x_rx_desc_ops, 163 .hw_ops = &qca988x_ops, 164 .decap_align_bytes = 4, 165 .spectral_bin_discard = 0, 166 .spectral_bin_offset = 0, 167 .vht160_mcs_rx_highest = 0, 168 .vht160_mcs_tx_highest = 0, 169 .n_cipher_suites = 8, 170 .ast_skid_limit = 0x10, 171 .num_wds_entries = 0x20, 172 .target_64bit = false, 173 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 174 .shadow_reg_support = false, 175 .rri_on_ddr = false, 176 .hw_filter_reset_required = true, 177 .fw_diag_ce_download = false, 178 .credit_size_workaround = false, 179 .tx_stats_over_pktlog = false, 180 .dynamic_sar_support = false, 181 .hw_restart_disconnect = false, 182 .use_fw_tx_credits = true, 183 .delay_unmap_buffer = false, 184 .mcast_frame_registration = false, 185 }, 186 { 187 .id = QCA6174_HW_3_2_VERSION, 188 .dev_id = QCA6174_3_2_DEVICE_ID, 189 .bus = ATH10K_BUS_SDIO, 190 .name = "qca6174 hw3.2 sdio", 191 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 192 .uart_pin = 19, 193 .otp_exe_param = 0, 194 .channel_counters_freq_hz = 88000, 195 .max_probe_resp_desc_thres = 0, 196 .cal_data_len = 0, 197 .fw = { 198 .dir = QCA6174_HW_3_0_FW_DIR, 199 .board_size = QCA6174_BOARD_DATA_SZ, 200 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 201 }, 202 .rx_desc_ops = &qca988x_rx_desc_ops, 203 .hw_ops = &qca6174_sdio_ops, 204 .hw_clk = qca6174_clk, 205 .target_cpu_freq = 176000000, 206 .decap_align_bytes = 4, 207 .n_cipher_suites = 8, 208 .num_peers = 10, 209 .ast_skid_limit = 0x10, 210 .num_wds_entries = 0x20, 211 .uart_pin_workaround = true, 212 .tx_stats_over_pktlog = false, 213 .credit_size_workaround = false, 214 .bmi_large_size_download = true, 215 .supports_peer_stats_info = true, 216 .dynamic_sar_support = true, 217 .hw_restart_disconnect = false, 218 .use_fw_tx_credits = true, 219 .delay_unmap_buffer = false, 220 .mcast_frame_registration = false, 221 }, 222 { 223 .id = QCA6174_HW_2_1_VERSION, 224 .dev_id = QCA6164_2_1_DEVICE_ID, 225 .bus = ATH10K_BUS_PCI, 226 .name = "qca6164 hw2.1", 227 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 228 .uart_pin = 6, 229 .otp_exe_param = 0, 230 .channel_counters_freq_hz = 88000, 231 .max_probe_resp_desc_thres = 0, 232 .cal_data_len = 8124, 233 .fw = { 234 .dir = QCA6174_HW_2_1_FW_DIR, 235 .board_size = QCA6174_BOARD_DATA_SZ, 236 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 237 }, 238 .rx_desc_ops = &qca988x_rx_desc_ops, 239 .hw_ops = &qca988x_ops, 240 .decap_align_bytes = 4, 241 .spectral_bin_discard = 0, 242 .spectral_bin_offset = 0, 243 .vht160_mcs_rx_highest = 0, 244 .vht160_mcs_tx_highest = 0, 245 .n_cipher_suites = 8, 246 .ast_skid_limit = 0x10, 247 .num_wds_entries = 0x20, 248 .target_64bit = false, 249 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 250 .shadow_reg_support = false, 251 .rri_on_ddr = false, 252 .hw_filter_reset_required = true, 253 .fw_diag_ce_download = false, 254 .credit_size_workaround = false, 255 .tx_stats_over_pktlog = false, 256 .dynamic_sar_support = false, 257 .hw_restart_disconnect = false, 258 .use_fw_tx_credits = true, 259 .delay_unmap_buffer = false, 260 .mcast_frame_registration = false, 261 }, 262 { 263 .id = QCA6174_HW_2_1_VERSION, 264 .dev_id = QCA6174_2_1_DEVICE_ID, 265 .bus = ATH10K_BUS_PCI, 266 .name = "qca6174 hw2.1", 267 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 268 .uart_pin = 6, 269 .otp_exe_param = 0, 270 .channel_counters_freq_hz = 88000, 271 .max_probe_resp_desc_thres = 0, 272 .cal_data_len = 8124, 273 .fw = { 274 .dir = QCA6174_HW_2_1_FW_DIR, 275 .board_size = QCA6174_BOARD_DATA_SZ, 276 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 277 }, 278 .rx_desc_ops = &qca988x_rx_desc_ops, 279 .hw_ops = &qca988x_ops, 280 .decap_align_bytes = 4, 281 .spectral_bin_discard = 0, 282 .spectral_bin_offset = 0, 283 .vht160_mcs_rx_highest = 0, 284 .vht160_mcs_tx_highest = 0, 285 .n_cipher_suites = 8, 286 .ast_skid_limit = 0x10, 287 .num_wds_entries = 0x20, 288 .target_64bit = false, 289 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 290 .shadow_reg_support = false, 291 .rri_on_ddr = false, 292 .hw_filter_reset_required = true, 293 .fw_diag_ce_download = false, 294 .credit_size_workaround = false, 295 .tx_stats_over_pktlog = false, 296 .dynamic_sar_support = false, 297 .hw_restart_disconnect = false, 298 .use_fw_tx_credits = true, 299 .delay_unmap_buffer = false, 300 .mcast_frame_registration = false, 301 }, 302 { 303 .id = QCA6174_HW_3_0_VERSION, 304 .dev_id = QCA6174_2_1_DEVICE_ID, 305 .bus = ATH10K_BUS_PCI, 306 .name = "qca6174 hw3.0", 307 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 308 .uart_pin = 6, 309 .otp_exe_param = 0, 310 .channel_counters_freq_hz = 88000, 311 .max_probe_resp_desc_thres = 0, 312 .cal_data_len = 8124, 313 .fw = { 314 .dir = QCA6174_HW_3_0_FW_DIR, 315 .board_size = QCA6174_BOARD_DATA_SZ, 316 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 317 }, 318 .rx_desc_ops = &qca988x_rx_desc_ops, 319 .hw_ops = &qca988x_ops, 320 .decap_align_bytes = 4, 321 .spectral_bin_discard = 0, 322 .spectral_bin_offset = 0, 323 .vht160_mcs_rx_highest = 0, 324 .vht160_mcs_tx_highest = 0, 325 .n_cipher_suites = 8, 326 .ast_skid_limit = 0x10, 327 .num_wds_entries = 0x20, 328 .target_64bit = false, 329 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 330 .shadow_reg_support = false, 331 .rri_on_ddr = false, 332 .hw_filter_reset_required = true, 333 .fw_diag_ce_download = false, 334 .credit_size_workaround = false, 335 .tx_stats_over_pktlog = false, 336 .dynamic_sar_support = false, 337 .hw_restart_disconnect = false, 338 .use_fw_tx_credits = true, 339 .delay_unmap_buffer = false, 340 .mcast_frame_registration = false, 341 }, 342 { 343 .id = QCA6174_HW_3_2_VERSION, 344 .dev_id = QCA6174_2_1_DEVICE_ID, 345 .bus = ATH10K_BUS_PCI, 346 .name = "qca6174 hw3.2", 347 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 348 .uart_pin = 6, 349 .otp_exe_param = 0, 350 .channel_counters_freq_hz = 88000, 351 .max_probe_resp_desc_thres = 0, 352 .cal_data_len = 8124, 353 .fw = { 354 /* uses same binaries as hw3.0 */ 355 .dir = QCA6174_HW_3_0_FW_DIR, 356 .board_size = QCA6174_BOARD_DATA_SZ, 357 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 358 }, 359 .rx_desc_ops = &qca988x_rx_desc_ops, 360 .hw_ops = &qca6174_ops, 361 .hw_clk = qca6174_clk, 362 .target_cpu_freq = 176000000, 363 .decap_align_bytes = 4, 364 .spectral_bin_discard = 0, 365 .spectral_bin_offset = 0, 366 .vht160_mcs_rx_highest = 0, 367 .vht160_mcs_tx_highest = 0, 368 .n_cipher_suites = 8, 369 .ast_skid_limit = 0x10, 370 .num_wds_entries = 0x20, 371 .target_64bit = false, 372 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 373 .shadow_reg_support = false, 374 .rri_on_ddr = false, 375 .hw_filter_reset_required = true, 376 .fw_diag_ce_download = true, 377 .credit_size_workaround = false, 378 .tx_stats_over_pktlog = false, 379 .supports_peer_stats_info = true, 380 .dynamic_sar_support = true, 381 .hw_restart_disconnect = false, 382 .use_fw_tx_credits = true, 383 .delay_unmap_buffer = false, 384 .mcast_frame_registration = true, 385 }, 386 { 387 .id = QCA99X0_HW_2_0_DEV_VERSION, 388 .dev_id = QCA99X0_2_0_DEVICE_ID, 389 .bus = ATH10K_BUS_PCI, 390 .name = "qca99x0 hw2.0", 391 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 392 .uart_pin = 7, 393 .otp_exe_param = 0x00000700, 394 .continuous_frag_desc = true, 395 .cck_rate_map_rev2 = true, 396 .channel_counters_freq_hz = 150000, 397 .max_probe_resp_desc_thres = 24, 398 .tx_chain_mask = 0xf, 399 .rx_chain_mask = 0xf, 400 .max_spatial_stream = 4, 401 .cal_data_len = 12064, 402 .fw = { 403 .dir = QCA99X0_HW_2_0_FW_DIR, 404 .board_size = QCA99X0_BOARD_DATA_SZ, 405 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 406 }, 407 .sw_decrypt_mcast_mgmt = true, 408 .rx_desc_ops = &qca99x0_rx_desc_ops, 409 .hw_ops = &qca99x0_ops, 410 .decap_align_bytes = 1, 411 .spectral_bin_discard = 4, 412 .spectral_bin_offset = 0, 413 .vht160_mcs_rx_highest = 0, 414 .vht160_mcs_tx_highest = 0, 415 .n_cipher_suites = 11, 416 .ast_skid_limit = 0x10, 417 .num_wds_entries = 0x20, 418 .target_64bit = false, 419 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 420 .shadow_reg_support = false, 421 .rri_on_ddr = false, 422 .hw_filter_reset_required = true, 423 .fw_diag_ce_download = false, 424 .credit_size_workaround = false, 425 .tx_stats_over_pktlog = false, 426 .dynamic_sar_support = false, 427 .hw_restart_disconnect = false, 428 .use_fw_tx_credits = true, 429 .delay_unmap_buffer = false, 430 .mcast_frame_registration = false, 431 }, 432 { 433 .id = QCA9984_HW_1_0_DEV_VERSION, 434 .dev_id = QCA9984_1_0_DEVICE_ID, 435 .bus = ATH10K_BUS_PCI, 436 .name = "qca9984/qca9994 hw1.0", 437 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 438 .uart_pin = 7, 439 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 440 .otp_exe_param = 0x00000700, 441 .continuous_frag_desc = true, 442 .cck_rate_map_rev2 = true, 443 .channel_counters_freq_hz = 150000, 444 .max_probe_resp_desc_thres = 24, 445 .tx_chain_mask = 0xf, 446 .rx_chain_mask = 0xf, 447 .max_spatial_stream = 4, 448 .cal_data_len = 12064, 449 .fw = { 450 .dir = QCA9984_HW_1_0_FW_DIR, 451 .board_size = QCA99X0_BOARD_DATA_SZ, 452 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 453 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 454 }, 455 .sw_decrypt_mcast_mgmt = true, 456 .rx_desc_ops = &qca99x0_rx_desc_ops, 457 .hw_ops = &qca99x0_ops, 458 .decap_align_bytes = 1, 459 .spectral_bin_discard = 12, 460 .spectral_bin_offset = 8, 461 462 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 463 * or 2x2 160Mhz, long-guard-interval. 464 */ 465 .vht160_mcs_rx_highest = 1560, 466 .vht160_mcs_tx_highest = 1560, 467 .n_cipher_suites = 11, 468 .ast_skid_limit = 0x10, 469 .num_wds_entries = 0x20, 470 .target_64bit = false, 471 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 472 .shadow_reg_support = false, 473 .rri_on_ddr = false, 474 .hw_filter_reset_required = true, 475 .fw_diag_ce_download = false, 476 .credit_size_workaround = false, 477 .tx_stats_over_pktlog = false, 478 .dynamic_sar_support = false, 479 .hw_restart_disconnect = false, 480 .use_fw_tx_credits = true, 481 .delay_unmap_buffer = false, 482 .mcast_frame_registration = false, 483 }, 484 { 485 .id = QCA9888_HW_2_0_DEV_VERSION, 486 .dev_id = QCA9888_2_0_DEVICE_ID, 487 .bus = ATH10K_BUS_PCI, 488 .name = "qca9888 hw2.0", 489 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 490 .uart_pin = 7, 491 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 492 .otp_exe_param = 0x00000700, 493 .continuous_frag_desc = true, 494 .channel_counters_freq_hz = 150000, 495 .max_probe_resp_desc_thres = 24, 496 .tx_chain_mask = 3, 497 .rx_chain_mask = 3, 498 .max_spatial_stream = 2, 499 .cal_data_len = 12064, 500 .fw = { 501 .dir = QCA9888_HW_2_0_FW_DIR, 502 .board_size = QCA99X0_BOARD_DATA_SZ, 503 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 504 }, 505 .sw_decrypt_mcast_mgmt = true, 506 .rx_desc_ops = &qca99x0_rx_desc_ops, 507 .hw_ops = &qca99x0_ops, 508 .decap_align_bytes = 1, 509 .spectral_bin_discard = 12, 510 .spectral_bin_offset = 8, 511 512 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 513 * 1x1 160Mhz, long-guard-interval. 514 */ 515 .vht160_mcs_rx_highest = 780, 516 .vht160_mcs_tx_highest = 780, 517 .n_cipher_suites = 11, 518 .ast_skid_limit = 0x10, 519 .num_wds_entries = 0x20, 520 .target_64bit = false, 521 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 522 .shadow_reg_support = false, 523 .rri_on_ddr = false, 524 .hw_filter_reset_required = true, 525 .fw_diag_ce_download = false, 526 .credit_size_workaround = false, 527 .tx_stats_over_pktlog = false, 528 .dynamic_sar_support = false, 529 .hw_restart_disconnect = false, 530 .use_fw_tx_credits = true, 531 .delay_unmap_buffer = false, 532 .mcast_frame_registration = false, 533 }, 534 { 535 .id = QCA9377_HW_1_0_DEV_VERSION, 536 .dev_id = QCA9377_1_0_DEVICE_ID, 537 .bus = ATH10K_BUS_PCI, 538 .name = "qca9377 hw1.0", 539 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 540 .uart_pin = 6, 541 .otp_exe_param = 0, 542 .channel_counters_freq_hz = 88000, 543 .max_probe_resp_desc_thres = 0, 544 .cal_data_len = 8124, 545 .fw = { 546 .dir = QCA9377_HW_1_0_FW_DIR, 547 .board_size = QCA9377_BOARD_DATA_SZ, 548 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 549 }, 550 .rx_desc_ops = &qca988x_rx_desc_ops, 551 .hw_ops = &qca988x_ops, 552 .decap_align_bytes = 4, 553 .spectral_bin_discard = 0, 554 .spectral_bin_offset = 0, 555 .vht160_mcs_rx_highest = 0, 556 .vht160_mcs_tx_highest = 0, 557 .n_cipher_suites = 8, 558 .ast_skid_limit = 0x10, 559 .num_wds_entries = 0x20, 560 .target_64bit = false, 561 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 562 .shadow_reg_support = false, 563 .rri_on_ddr = false, 564 .hw_filter_reset_required = true, 565 .fw_diag_ce_download = false, 566 .credit_size_workaround = false, 567 .tx_stats_over_pktlog = false, 568 .dynamic_sar_support = false, 569 .hw_restart_disconnect = false, 570 .use_fw_tx_credits = true, 571 .delay_unmap_buffer = false, 572 .mcast_frame_registration = false, 573 }, 574 { 575 .id = QCA9377_HW_1_1_DEV_VERSION, 576 .dev_id = QCA9377_1_0_DEVICE_ID, 577 .bus = ATH10K_BUS_PCI, 578 .name = "qca9377 hw1.1", 579 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 580 .uart_pin = 6, 581 .otp_exe_param = 0, 582 .channel_counters_freq_hz = 88000, 583 .max_probe_resp_desc_thres = 0, 584 .cal_data_len = 8124, 585 .fw = { 586 .dir = QCA9377_HW_1_0_FW_DIR, 587 .board_size = QCA9377_BOARD_DATA_SZ, 588 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 589 }, 590 .rx_desc_ops = &qca988x_rx_desc_ops, 591 .hw_ops = &qca6174_ops, 592 .hw_clk = qca6174_clk, 593 .target_cpu_freq = 176000000, 594 .decap_align_bytes = 4, 595 .spectral_bin_discard = 0, 596 .spectral_bin_offset = 0, 597 .vht160_mcs_rx_highest = 0, 598 .vht160_mcs_tx_highest = 0, 599 .n_cipher_suites = 8, 600 .ast_skid_limit = 0x10, 601 .num_wds_entries = 0x20, 602 .target_64bit = false, 603 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 604 .shadow_reg_support = false, 605 .rri_on_ddr = false, 606 .hw_filter_reset_required = true, 607 .fw_diag_ce_download = true, 608 .credit_size_workaround = false, 609 .tx_stats_over_pktlog = false, 610 .dynamic_sar_support = false, 611 .hw_restart_disconnect = false, 612 .use_fw_tx_credits = true, 613 .delay_unmap_buffer = false, 614 .mcast_frame_registration = false, 615 }, 616 { 617 .id = QCA9377_HW_1_1_DEV_VERSION, 618 .dev_id = QCA9377_1_0_DEVICE_ID, 619 .bus = ATH10K_BUS_SDIO, 620 .name = "qca9377 hw1.1 sdio", 621 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 622 .uart_pin = 19, 623 .otp_exe_param = 0, 624 .channel_counters_freq_hz = 88000, 625 .max_probe_resp_desc_thres = 0, 626 .cal_data_len = 8124, 627 .fw = { 628 .dir = QCA9377_HW_1_0_FW_DIR, 629 .board_size = QCA9377_BOARD_DATA_SZ, 630 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 631 }, 632 .rx_desc_ops = &qca988x_rx_desc_ops, 633 .hw_ops = &qca6174_ops, 634 .hw_clk = qca6174_clk, 635 .target_cpu_freq = 176000000, 636 .decap_align_bytes = 4, 637 .n_cipher_suites = 8, 638 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 639 .ast_skid_limit = 0x10, 640 .num_wds_entries = 0x20, 641 .uart_pin_workaround = true, 642 .credit_size_workaround = true, 643 .dynamic_sar_support = false, 644 .hw_restart_disconnect = false, 645 .use_fw_tx_credits = true, 646 .delay_unmap_buffer = false, 647 .mcast_frame_registration = false, 648 }, 649 { 650 .id = QCA4019_HW_1_0_DEV_VERSION, 651 .dev_id = 0, 652 .bus = ATH10K_BUS_AHB, 653 .name = "qca4019 hw1.0", 654 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 655 .uart_pin = 7, 656 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 657 .otp_exe_param = 0x0010000, 658 .continuous_frag_desc = true, 659 .cck_rate_map_rev2 = true, 660 .channel_counters_freq_hz = 125000, 661 .max_probe_resp_desc_thres = 24, 662 .tx_chain_mask = 0x3, 663 .rx_chain_mask = 0x3, 664 .max_spatial_stream = 2, 665 .cal_data_len = 12064, 666 .fw = { 667 .dir = QCA4019_HW_1_0_FW_DIR, 668 .board_size = QCA4019_BOARD_DATA_SZ, 669 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 670 }, 671 .sw_decrypt_mcast_mgmt = true, 672 .rx_desc_ops = &qca99x0_rx_desc_ops, 673 .hw_ops = &qca99x0_ops, 674 .decap_align_bytes = 1, 675 .spectral_bin_discard = 4, 676 .spectral_bin_offset = 0, 677 .vht160_mcs_rx_highest = 0, 678 .vht160_mcs_tx_highest = 0, 679 .n_cipher_suites = 11, 680 .ast_skid_limit = 0x10, 681 .num_wds_entries = 0x20, 682 .target_64bit = false, 683 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 684 .shadow_reg_support = false, 685 .rri_on_ddr = false, 686 .hw_filter_reset_required = true, 687 .fw_diag_ce_download = false, 688 .credit_size_workaround = false, 689 .tx_stats_over_pktlog = false, 690 .dynamic_sar_support = false, 691 .hw_restart_disconnect = false, 692 .use_fw_tx_credits = true, 693 .delay_unmap_buffer = false, 694 .mcast_frame_registration = false, 695 }, 696 { 697 .id = WCN3990_HW_1_0_DEV_VERSION, 698 .dev_id = 0, 699 .bus = ATH10K_BUS_SNOC, 700 .name = "wcn3990 hw1.0", 701 .continuous_frag_desc = true, 702 .tx_chain_mask = 0x7, 703 .rx_chain_mask = 0x7, 704 .max_spatial_stream = 4, 705 .fw = { 706 .dir = WCN3990_HW_1_0_FW_DIR, 707 .board_size = WCN3990_BOARD_DATA_SZ, 708 .board_ext_size = WCN3990_BOARD_EXT_DATA_SZ, 709 }, 710 .sw_decrypt_mcast_mgmt = true, 711 .rx_desc_ops = &wcn3990_rx_desc_ops, 712 .hw_ops = &wcn3990_ops, 713 .decap_align_bytes = 1, 714 .num_peers = TARGET_HL_TLV_NUM_PEERS, 715 .n_cipher_suites = 11, 716 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 717 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 718 .target_64bit = true, 719 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 720 .shadow_reg_support = true, 721 .rri_on_ddr = true, 722 .hw_filter_reset_required = false, 723 .fw_diag_ce_download = false, 724 .credit_size_workaround = false, 725 .tx_stats_over_pktlog = false, 726 .dynamic_sar_support = true, 727 .hw_restart_disconnect = true, 728 .use_fw_tx_credits = false, 729 .delay_unmap_buffer = true, 730 .mcast_frame_registration = false, 731 }, 732 }; 733 734 static const char *const ath10k_core_fw_feature_str[] = { 735 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 736 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 737 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 738 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 739 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 740 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 741 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 742 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 743 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 744 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 745 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 746 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 747 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 748 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 749 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 750 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 751 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 752 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 753 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 754 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 755 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 756 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 757 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 758 }; 759 760 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 761 size_t buf_len, 762 enum ath10k_fw_features feat) 763 { 764 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 765 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 766 ATH10K_FW_FEATURE_COUNT); 767 768 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 769 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 770 return scnprintf(buf, buf_len, "bit%d", feat); 771 } 772 773 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 774 } 775 776 void ath10k_core_get_fw_features_str(struct ath10k *ar, 777 char *buf, 778 size_t buf_len) 779 { 780 size_t len = 0; 781 int i; 782 783 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 784 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 785 if (len > 0) 786 len += scnprintf(buf + len, buf_len - len, ","); 787 788 len += ath10k_core_get_fw_feature_str(buf + len, 789 buf_len - len, 790 i); 791 } 792 } 793 } 794 795 static void ath10k_send_suspend_complete(struct ath10k *ar) 796 { 797 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 798 799 complete(&ar->target_suspend); 800 } 801 802 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 803 { 804 bool mtu_workaround = ar->hw_params.credit_size_workaround; 805 int ret; 806 u32 param = 0; 807 808 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 809 if (ret) 810 return ret; 811 812 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 813 if (ret) 814 return ret; 815 816 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 817 if (ret) 818 return ret; 819 820 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 821 822 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 823 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 824 else 825 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 826 827 if (mode == ATH10K_FIRMWARE_MODE_UTF) 828 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 829 else 830 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 831 832 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 833 if (ret) 834 return ret; 835 836 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 837 if (ret) 838 return ret; 839 840 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 841 842 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 843 if (ret) 844 return ret; 845 846 return 0; 847 } 848 849 static int ath10k_init_configure_target(struct ath10k *ar) 850 { 851 u32 param_host; 852 int ret; 853 854 /* tell target which HTC version it is used*/ 855 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 856 HTC_PROTOCOL_VERSION); 857 if (ret) { 858 ath10k_err(ar, "settings HTC version failed\n"); 859 return ret; 860 } 861 862 /* set the firmware mode to STA/IBSS/AP */ 863 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 864 if (ret) { 865 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 866 return ret; 867 } 868 869 /* TODO following parameters need to be re-visited. */ 870 /* num_device */ 871 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 872 /* Firmware mode */ 873 /* FIXME: Why FW_MODE_AP ??.*/ 874 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 875 /* mac_addr_method */ 876 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 877 /* firmware_bridge */ 878 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 879 /* fwsubmode */ 880 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 881 882 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 883 if (ret) { 884 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 885 return ret; 886 } 887 888 /* We do all byte-swapping on the host */ 889 ret = ath10k_bmi_write32(ar, hi_be, 0); 890 if (ret) { 891 ath10k_err(ar, "setting host CPU BE mode failed\n"); 892 return ret; 893 } 894 895 /* FW descriptor/Data swap flags */ 896 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 897 898 if (ret) { 899 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 900 return ret; 901 } 902 903 /* Some devices have a special sanity check that verifies the PCI 904 * Device ID is written to this host interest var. It is known to be 905 * required to boot QCA6164. 906 */ 907 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 908 ar->dev_id); 909 if (ret) { 910 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 911 return ret; 912 } 913 914 return 0; 915 } 916 917 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 918 const char *dir, 919 const char *file) 920 { 921 char filename[100]; 922 const struct firmware *fw; 923 int ret; 924 925 if (file == NULL) 926 return ERR_PTR(-ENOENT); 927 928 if (dir == NULL) 929 dir = "."; 930 931 if (ar->board_name) { 932 snprintf(filename, sizeof(filename), "%s/%s/%s", 933 dir, ar->board_name, file); 934 ret = firmware_request_nowarn(&fw, filename, ar->dev); 935 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 936 filename, ret); 937 if (!ret) 938 return fw; 939 } 940 941 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 942 ret = firmware_request_nowarn(&fw, filename, ar->dev); 943 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 944 filename, ret); 945 if (ret) 946 return ERR_PTR(ret); 947 948 return fw; 949 } 950 951 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 952 size_t data_len) 953 { 954 u32 board_data_size = ar->hw_params.fw.board_size; 955 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 956 u32 board_ext_data_addr; 957 int ret; 958 959 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 960 if (ret) { 961 ath10k_err(ar, "could not read board ext data addr (%d)\n", 962 ret); 963 return ret; 964 } 965 966 ath10k_dbg(ar, ATH10K_DBG_BOOT, 967 "boot push board extended data addr 0x%x\n", 968 board_ext_data_addr); 969 970 if (board_ext_data_addr == 0) 971 return 0; 972 973 if (data_len != (board_data_size + board_ext_data_size)) { 974 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 975 data_len, board_data_size, board_ext_data_size); 976 return -EINVAL; 977 } 978 979 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 980 data + board_data_size, 981 board_ext_data_size); 982 if (ret) { 983 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 984 return ret; 985 } 986 987 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 988 (board_ext_data_size << 16) | 1); 989 if (ret) { 990 ath10k_err(ar, "could not write board ext data bit (%d)\n", 991 ret); 992 return ret; 993 } 994 995 return 0; 996 } 997 998 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 999 { 1000 u32 result, address; 1001 u8 board_id, chip_id; 1002 bool ext_bid_support; 1003 int ret, bmi_board_id_param; 1004 1005 address = ar->hw_params.patch_load_addr; 1006 1007 if (!ar->normal_mode_fw.fw_file.otp_data || 1008 !ar->normal_mode_fw.fw_file.otp_len) { 1009 ath10k_warn(ar, 1010 "failed to retrieve board id because of invalid otp\n"); 1011 return -ENODATA; 1012 } 1013 1014 if (ar->id.bmi_ids_valid) { 1015 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1016 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 1017 ar->id.bmi_board_id, ar->id.bmi_chip_id); 1018 goto skip_otp_download; 1019 } 1020 1021 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1022 "boot upload otp to 0x%x len %zd for board id\n", 1023 address, ar->normal_mode_fw.fw_file.otp_len); 1024 1025 ret = ath10k_bmi_fast_download(ar, address, 1026 ar->normal_mode_fw.fw_file.otp_data, 1027 ar->normal_mode_fw.fw_file.otp_len); 1028 if (ret) { 1029 ath10k_err(ar, "could not write otp for board id check: %d\n", 1030 ret); 1031 return ret; 1032 } 1033 1034 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1035 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1036 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1037 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 1038 else 1039 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 1040 1041 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 1042 if (ret) { 1043 ath10k_err(ar, "could not execute otp for board id check: %d\n", 1044 ret); 1045 return ret; 1046 } 1047 1048 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1049 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1050 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1051 1052 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1053 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1054 result, board_id, chip_id, ext_bid_support); 1055 1056 ar->id.ext_bid_supported = ext_bid_support; 1057 1058 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1059 (board_id == 0)) { 1060 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1061 "board id does not exist in otp, ignore it\n"); 1062 return -EOPNOTSUPP; 1063 } 1064 1065 ar->id.bmi_ids_valid = true; 1066 ar->id.bmi_board_id = board_id; 1067 ar->id.bmi_chip_id = chip_id; 1068 1069 skip_otp_download: 1070 1071 return 0; 1072 } 1073 1074 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1075 { 1076 struct ath10k *ar = data; 1077 const char *bdf_ext; 1078 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1079 u8 bdf_enabled; 1080 int i; 1081 1082 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1083 return; 1084 1085 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1086 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1087 "wrong smbios bdf ext type length (%d).\n", 1088 hdr->length); 1089 return; 1090 } 1091 1092 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1093 if (!bdf_enabled) { 1094 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1095 return; 1096 } 1097 1098 /* Only one string exists (per spec) */ 1099 bdf_ext = (char *)hdr + hdr->length; 1100 1101 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1102 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1103 "bdf variant magic does not match.\n"); 1104 return; 1105 } 1106 1107 for (i = 0; i < strlen(bdf_ext); i++) { 1108 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1109 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1110 "bdf variant name contains non ascii chars.\n"); 1111 return; 1112 } 1113 } 1114 1115 /* Copy extension name without magic suffix */ 1116 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1117 sizeof(ar->id.bdf_ext)) < 0) { 1118 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1119 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1120 bdf_ext); 1121 return; 1122 } 1123 1124 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1125 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1126 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1127 } 1128 1129 static int ath10k_core_check_smbios(struct ath10k *ar) 1130 { 1131 ar->id.bdf_ext[0] = '\0'; 1132 dmi_walk(ath10k_core_check_bdfext, ar); 1133 1134 if (ar->id.bdf_ext[0] == '\0') 1135 return -ENODATA; 1136 1137 return 0; 1138 } 1139 1140 int ath10k_core_check_dt(struct ath10k *ar) 1141 { 1142 struct device_node *node; 1143 const char *variant = NULL; 1144 1145 node = ar->dev->of_node; 1146 if (!node) 1147 return -ENOENT; 1148 1149 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1150 &variant); 1151 if (!variant) 1152 return -ENODATA; 1153 1154 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1155 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1156 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1157 variant); 1158 1159 return 0; 1160 } 1161 EXPORT_SYMBOL(ath10k_core_check_dt); 1162 1163 static int ath10k_download_fw(struct ath10k *ar) 1164 { 1165 u32 address, data_len; 1166 const void *data; 1167 int ret; 1168 struct pm_qos_request latency_qos; 1169 1170 address = ar->hw_params.patch_load_addr; 1171 1172 data = ar->running_fw->fw_file.firmware_data; 1173 data_len = ar->running_fw->fw_file.firmware_len; 1174 1175 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1176 if (ret) { 1177 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1178 ret); 1179 return ret; 1180 } 1181 1182 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1183 "boot uploading firmware image %pK len %d\n", 1184 data, data_len); 1185 1186 /* Check if device supports to download firmware via 1187 * diag copy engine. Downloading firmware via diag CE 1188 * greatly reduces the time to download firmware. 1189 */ 1190 if (ar->hw_params.fw_diag_ce_download) { 1191 ret = ath10k_hw_diag_fast_download(ar, address, 1192 data, data_len); 1193 if (ret == 0) 1194 /* firmware upload via diag ce was successful */ 1195 return 0; 1196 1197 ath10k_warn(ar, 1198 "failed to upload firmware via diag ce, trying BMI: %d", 1199 ret); 1200 } 1201 1202 memset(&latency_qos, 0, sizeof(latency_qos)); 1203 cpu_latency_qos_add_request(&latency_qos, 0); 1204 1205 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1206 1207 cpu_latency_qos_remove_request(&latency_qos); 1208 1209 return ret; 1210 } 1211 1212 void ath10k_core_free_board_files(struct ath10k *ar) 1213 { 1214 if (!IS_ERR(ar->normal_mode_fw.board)) 1215 release_firmware(ar->normal_mode_fw.board); 1216 1217 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1218 release_firmware(ar->normal_mode_fw.ext_board); 1219 1220 ar->normal_mode_fw.board = NULL; 1221 ar->normal_mode_fw.board_data = NULL; 1222 ar->normal_mode_fw.board_len = 0; 1223 ar->normal_mode_fw.ext_board = NULL; 1224 ar->normal_mode_fw.ext_board_data = NULL; 1225 ar->normal_mode_fw.ext_board_len = 0; 1226 } 1227 EXPORT_SYMBOL(ath10k_core_free_board_files); 1228 1229 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1230 { 1231 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1232 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1233 1234 if (!IS_ERR(ar->cal_file)) 1235 release_firmware(ar->cal_file); 1236 1237 if (!IS_ERR(ar->pre_cal_file)) 1238 release_firmware(ar->pre_cal_file); 1239 1240 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1241 1242 ar->normal_mode_fw.fw_file.otp_data = NULL; 1243 ar->normal_mode_fw.fw_file.otp_len = 0; 1244 1245 ar->normal_mode_fw.fw_file.firmware = NULL; 1246 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1247 ar->normal_mode_fw.fw_file.firmware_len = 0; 1248 1249 ar->cal_file = NULL; 1250 ar->pre_cal_file = NULL; 1251 } 1252 1253 static int ath10k_fetch_cal_file(struct ath10k *ar) 1254 { 1255 char filename[100]; 1256 1257 /* pre-cal-<bus>-<id>.bin */ 1258 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1259 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1260 1261 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1262 if (!IS_ERR(ar->pre_cal_file)) 1263 goto success; 1264 1265 /* cal-<bus>-<id>.bin */ 1266 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1267 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1268 1269 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1270 if (IS_ERR(ar->cal_file)) 1271 /* calibration file is optional, don't print any warnings */ 1272 return PTR_ERR(ar->cal_file); 1273 success: 1274 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1275 ATH10K_FW_DIR, filename); 1276 1277 return 0; 1278 } 1279 1280 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1281 { 1282 const struct firmware *fw; 1283 char boardname[100]; 1284 1285 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1286 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin", 1287 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1288 1289 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1290 ar->hw_params.fw.dir, 1291 boardname); 1292 if (IS_ERR(ar->normal_mode_fw.board)) { 1293 fw = ath10k_fetch_fw_file(ar, 1294 ar->hw_params.fw.dir, 1295 ATH10K_BOARD_DATA_FILE); 1296 ar->normal_mode_fw.board = fw; 1297 } 1298 1299 if (IS_ERR(ar->normal_mode_fw.board)) 1300 return PTR_ERR(ar->normal_mode_fw.board); 1301 1302 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1303 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1304 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1305 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1306 ATH10K_EBOARD_DATA_FILE); 1307 ar->normal_mode_fw.ext_board = fw; 1308 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1309 return PTR_ERR(ar->normal_mode_fw.ext_board); 1310 1311 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1312 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1313 } 1314 1315 return 0; 1316 } 1317 1318 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1319 const void *buf, size_t buf_len, 1320 const char *boardname, 1321 int bd_ie_type) 1322 { 1323 const struct ath10k_fw_ie *hdr; 1324 bool name_match_found; 1325 int ret, board_ie_id; 1326 size_t board_ie_len; 1327 const void *board_ie_data; 1328 1329 name_match_found = false; 1330 1331 /* go through ATH10K_BD_IE_BOARD_ elements */ 1332 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1333 hdr = buf; 1334 board_ie_id = le32_to_cpu(hdr->id); 1335 board_ie_len = le32_to_cpu(hdr->len); 1336 board_ie_data = hdr->data; 1337 1338 buf_len -= sizeof(*hdr); 1339 buf += sizeof(*hdr); 1340 1341 if (buf_len < ALIGN(board_ie_len, 4)) { 1342 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1343 buf_len, ALIGN(board_ie_len, 4)); 1344 ret = -EINVAL; 1345 goto out; 1346 } 1347 1348 switch (board_ie_id) { 1349 case ATH10K_BD_IE_BOARD_NAME: 1350 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1351 board_ie_data, board_ie_len); 1352 1353 if (board_ie_len != strlen(boardname)) 1354 break; 1355 1356 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1357 if (ret) 1358 break; 1359 1360 name_match_found = true; 1361 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1362 "boot found match for name '%s'", 1363 boardname); 1364 break; 1365 case ATH10K_BD_IE_BOARD_DATA: 1366 if (!name_match_found) 1367 /* no match found */ 1368 break; 1369 1370 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1371 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1372 "boot found board data for '%s'", 1373 boardname); 1374 1375 ar->normal_mode_fw.board_data = board_ie_data; 1376 ar->normal_mode_fw.board_len = board_ie_len; 1377 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1378 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1379 "boot found eboard data for '%s'", 1380 boardname); 1381 1382 ar->normal_mode_fw.ext_board_data = board_ie_data; 1383 ar->normal_mode_fw.ext_board_len = board_ie_len; 1384 } 1385 1386 ret = 0; 1387 goto out; 1388 default: 1389 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1390 board_ie_id); 1391 break; 1392 } 1393 1394 /* jump over the padding */ 1395 board_ie_len = ALIGN(board_ie_len, 4); 1396 1397 buf_len -= board_ie_len; 1398 buf += board_ie_len; 1399 } 1400 1401 /* no match found */ 1402 ret = -ENOENT; 1403 1404 out: 1405 return ret; 1406 } 1407 1408 static int ath10k_core_search_bd(struct ath10k *ar, 1409 const char *boardname, 1410 const u8 *data, 1411 size_t len) 1412 { 1413 size_t ie_len; 1414 struct ath10k_fw_ie *hdr; 1415 int ret = -ENOENT, ie_id; 1416 1417 while (len > sizeof(struct ath10k_fw_ie)) { 1418 hdr = (struct ath10k_fw_ie *)data; 1419 ie_id = le32_to_cpu(hdr->id); 1420 ie_len = le32_to_cpu(hdr->len); 1421 1422 len -= sizeof(*hdr); 1423 data = hdr->data; 1424 1425 if (len < ALIGN(ie_len, 4)) { 1426 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1427 ie_id, ie_len, len); 1428 return -EINVAL; 1429 } 1430 1431 switch (ie_id) { 1432 case ATH10K_BD_IE_BOARD: 1433 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1434 boardname, 1435 ATH10K_BD_IE_BOARD); 1436 if (ret == -ENOENT) 1437 /* no match found, continue */ 1438 break; 1439 1440 /* either found or error, so stop searching */ 1441 goto out; 1442 case ATH10K_BD_IE_BOARD_EXT: 1443 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1444 boardname, 1445 ATH10K_BD_IE_BOARD_EXT); 1446 if (ret == -ENOENT) 1447 /* no match found, continue */ 1448 break; 1449 1450 /* either found or error, so stop searching */ 1451 goto out; 1452 } 1453 1454 /* jump over the padding */ 1455 ie_len = ALIGN(ie_len, 4); 1456 1457 len -= ie_len; 1458 data += ie_len; 1459 } 1460 1461 out: 1462 /* return result of parse_bd_ie_board() or -ENOENT */ 1463 return ret; 1464 } 1465 1466 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1467 const char *boardname, 1468 const char *fallback_boardname1, 1469 const char *fallback_boardname2, 1470 const char *filename) 1471 { 1472 size_t len, magic_len; 1473 const u8 *data; 1474 int ret; 1475 1476 /* Skip if already fetched during board data download */ 1477 if (!ar->normal_mode_fw.board) 1478 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1479 ar->hw_params.fw.dir, 1480 filename); 1481 if (IS_ERR(ar->normal_mode_fw.board)) 1482 return PTR_ERR(ar->normal_mode_fw.board); 1483 1484 data = ar->normal_mode_fw.board->data; 1485 len = ar->normal_mode_fw.board->size; 1486 1487 /* magic has extra null byte padded */ 1488 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1489 if (len < magic_len) { 1490 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1491 ar->hw_params.fw.dir, filename, len); 1492 ret = -EINVAL; 1493 goto err; 1494 } 1495 1496 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1497 ath10k_err(ar, "found invalid board magic\n"); 1498 ret = -EINVAL; 1499 goto err; 1500 } 1501 1502 /* magic is padded to 4 bytes */ 1503 magic_len = ALIGN(magic_len, 4); 1504 if (len < magic_len) { 1505 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1506 ar->hw_params.fw.dir, filename, len); 1507 ret = -EINVAL; 1508 goto err; 1509 } 1510 1511 data += magic_len; 1512 len -= magic_len; 1513 1514 /* attempt to find boardname in the IE list */ 1515 ret = ath10k_core_search_bd(ar, boardname, data, len); 1516 1517 /* if we didn't find it and have a fallback name, try that */ 1518 if (ret == -ENOENT && fallback_boardname1) 1519 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1520 1521 if (ret == -ENOENT && fallback_boardname2) 1522 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1523 1524 if (ret == -ENOENT) { 1525 ath10k_err(ar, 1526 "failed to fetch board data for %s from %s/%s\n", 1527 boardname, ar->hw_params.fw.dir, filename); 1528 ret = -ENODATA; 1529 } 1530 1531 if (ret) 1532 goto err; 1533 1534 return 0; 1535 1536 err: 1537 ath10k_core_free_board_files(ar); 1538 return ret; 1539 } 1540 1541 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1542 size_t name_len, bool with_variant, 1543 bool with_chip_id) 1544 { 1545 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1546 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1547 1548 if (with_variant && ar->id.bdf_ext[0] != '\0') 1549 scnprintf(variant, sizeof(variant), ",variant=%s", 1550 ar->id.bdf_ext); 1551 1552 if (ar->id.bmi_ids_valid) { 1553 scnprintf(name, name_len, 1554 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1555 ath10k_bus_str(ar->hif.bus), 1556 ar->id.bmi_chip_id, 1557 ar->id.bmi_board_id, variant); 1558 goto out; 1559 } 1560 1561 if (ar->id.qmi_ids_valid) { 1562 if (with_chip_id) 1563 scnprintf(name, name_len, 1564 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1565 ath10k_bus_str(ar->hif.bus), 1566 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1567 variant); 1568 else 1569 scnprintf(name, name_len, 1570 "bus=%s,qmi-board-id=%x", 1571 ath10k_bus_str(ar->hif.bus), 1572 ar->id.qmi_board_id); 1573 goto out; 1574 } 1575 1576 scnprintf(name, name_len, 1577 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1578 ath10k_bus_str(ar->hif.bus), 1579 ar->id.vendor, ar->id.device, 1580 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1581 out: 1582 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1583 1584 return 0; 1585 } 1586 1587 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1588 size_t name_len) 1589 { 1590 if (ar->id.bmi_ids_valid) { 1591 scnprintf(name, name_len, 1592 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1593 ath10k_bus_str(ar->hif.bus), 1594 ar->id.bmi_chip_id, 1595 ar->id.bmi_eboard_id); 1596 1597 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1598 return 0; 1599 } 1600 /* Fallback if returned board id is zero */ 1601 return -1; 1602 } 1603 1604 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1605 { 1606 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1607 int ret; 1608 1609 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1610 /* With variant and chip id */ 1611 ret = ath10k_core_create_board_name(ar, boardname, 1612 sizeof(boardname), true, 1613 true); 1614 if (ret) { 1615 ath10k_err(ar, "failed to create board name: %d", ret); 1616 return ret; 1617 } 1618 1619 /* Without variant and only chip-id */ 1620 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1621 sizeof(boardname), false, 1622 true); 1623 if (ret) { 1624 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1625 ret); 1626 return ret; 1627 } 1628 1629 /* Without variant and without chip-id */ 1630 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1631 sizeof(boardname), false, 1632 false); 1633 if (ret) { 1634 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1635 ret); 1636 return ret; 1637 } 1638 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1639 ret = ath10k_core_create_eboard_name(ar, boardname, 1640 sizeof(boardname)); 1641 if (ret) { 1642 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1643 goto fallback; 1644 } 1645 } 1646 1647 ar->bd_api = 2; 1648 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1649 fallback_boardname1, 1650 fallback_boardname2, 1651 ATH10K_BOARD_API2_FILE); 1652 if (!ret) 1653 goto success; 1654 1655 fallback: 1656 ar->bd_api = 1; 1657 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1658 if (ret) { 1659 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1660 ar->hw_params.fw.dir); 1661 return ret; 1662 } 1663 1664 success: 1665 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1666 return 0; 1667 } 1668 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1669 1670 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1671 { 1672 u32 result, address; 1673 u8 ext_board_id; 1674 int ret; 1675 1676 address = ar->hw_params.patch_load_addr; 1677 1678 if (!ar->normal_mode_fw.fw_file.otp_data || 1679 !ar->normal_mode_fw.fw_file.otp_len) { 1680 ath10k_warn(ar, 1681 "failed to retrieve extended board id due to otp binary missing\n"); 1682 return -ENODATA; 1683 } 1684 1685 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1686 "boot upload otp to 0x%x len %zd for ext board id\n", 1687 address, ar->normal_mode_fw.fw_file.otp_len); 1688 1689 ret = ath10k_bmi_fast_download(ar, address, 1690 ar->normal_mode_fw.fw_file.otp_data, 1691 ar->normal_mode_fw.fw_file.otp_len); 1692 if (ret) { 1693 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1694 ret); 1695 return ret; 1696 } 1697 1698 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1699 if (ret) { 1700 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1701 ret); 1702 return ret; 1703 } 1704 1705 if (!result) { 1706 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1707 "ext board id does not exist in otp, ignore it\n"); 1708 return -EOPNOTSUPP; 1709 } 1710 1711 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1712 1713 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1714 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1715 result, ext_board_id); 1716 1717 ar->id.bmi_eboard_id = ext_board_id; 1718 1719 return 0; 1720 } 1721 1722 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1723 size_t data_len) 1724 { 1725 u32 board_data_size = ar->hw_params.fw.board_size; 1726 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1727 u32 board_address; 1728 u32 ext_board_address; 1729 int ret; 1730 1731 ret = ath10k_push_board_ext_data(ar, data, data_len); 1732 if (ret) { 1733 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1734 goto exit; 1735 } 1736 1737 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1738 if (ret) { 1739 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1740 goto exit; 1741 } 1742 1743 ret = ath10k_bmi_write_memory(ar, board_address, data, 1744 min_t(u32, board_data_size, 1745 data_len)); 1746 if (ret) { 1747 ath10k_err(ar, "could not write board data (%d)\n", ret); 1748 goto exit; 1749 } 1750 1751 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1752 if (ret) { 1753 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1754 goto exit; 1755 } 1756 1757 if (!ar->id.ext_bid_supported) 1758 goto exit; 1759 1760 /* Extended board data download */ 1761 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1762 if (ret == -EOPNOTSUPP) { 1763 /* Not fetching ext_board_data if ext board id is 0 */ 1764 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1765 return 0; 1766 } else if (ret) { 1767 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1768 goto exit; 1769 } 1770 1771 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1772 if (ret) 1773 goto exit; 1774 1775 if (ar->normal_mode_fw.ext_board_data) { 1776 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1777 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1778 "boot writing ext board data to addr 0x%x", 1779 ext_board_address); 1780 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1781 ar->normal_mode_fw.ext_board_data, 1782 min_t(u32, eboard_data_size, data_len)); 1783 if (ret) 1784 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1785 } 1786 1787 exit: 1788 return ret; 1789 } 1790 1791 static int ath10k_download_and_run_otp(struct ath10k *ar) 1792 { 1793 u32 result, address = ar->hw_params.patch_load_addr; 1794 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1795 int ret; 1796 1797 ret = ath10k_download_board_data(ar, 1798 ar->running_fw->board_data, 1799 ar->running_fw->board_len); 1800 if (ret) { 1801 ath10k_err(ar, "failed to download board data: %d\n", ret); 1802 return ret; 1803 } 1804 1805 /* OTP is optional */ 1806 1807 if (!ar->running_fw->fw_file.otp_data || 1808 !ar->running_fw->fw_file.otp_len) { 1809 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1810 ar->running_fw->fw_file.otp_data, 1811 ar->running_fw->fw_file.otp_len); 1812 return 0; 1813 } 1814 1815 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1816 address, ar->running_fw->fw_file.otp_len); 1817 1818 ret = ath10k_bmi_fast_download(ar, address, 1819 ar->running_fw->fw_file.otp_data, 1820 ar->running_fw->fw_file.otp_len); 1821 if (ret) { 1822 ath10k_err(ar, "could not write otp (%d)\n", ret); 1823 return ret; 1824 } 1825 1826 /* As of now pre-cal is valid for 10_4 variants */ 1827 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1828 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1829 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1830 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1831 1832 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1833 if (ret) { 1834 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1835 return ret; 1836 } 1837 1838 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1839 1840 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1841 ar->running_fw->fw_file.fw_features)) && 1842 result != 0) { 1843 ath10k_err(ar, "otp calibration failed: %d", result); 1844 return -EINVAL; 1845 } 1846 1847 return 0; 1848 } 1849 1850 static int ath10k_download_cal_file(struct ath10k *ar, 1851 const struct firmware *file) 1852 { 1853 int ret; 1854 1855 if (!file) 1856 return -ENOENT; 1857 1858 if (IS_ERR(file)) 1859 return PTR_ERR(file); 1860 1861 ret = ath10k_download_board_data(ar, file->data, file->size); 1862 if (ret) { 1863 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1864 return ret; 1865 } 1866 1867 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1868 1869 return 0; 1870 } 1871 1872 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1873 { 1874 struct device_node *node; 1875 int data_len; 1876 void *data; 1877 int ret; 1878 1879 node = ar->dev->of_node; 1880 if (!node) 1881 /* Device Tree is optional, don't print any warnings if 1882 * there's no node for ath10k. 1883 */ 1884 return -ENOENT; 1885 1886 if (!of_get_property(node, dt_name, &data_len)) { 1887 /* The calibration data node is optional */ 1888 return -ENOENT; 1889 } 1890 1891 if (data_len != ar->hw_params.cal_data_len) { 1892 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1893 data_len); 1894 ret = -EMSGSIZE; 1895 goto out; 1896 } 1897 1898 data = kmalloc(data_len, GFP_KERNEL); 1899 if (!data) { 1900 ret = -ENOMEM; 1901 goto out; 1902 } 1903 1904 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1905 if (ret) { 1906 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1907 ret); 1908 goto out_free; 1909 } 1910 1911 ret = ath10k_download_board_data(ar, data, data_len); 1912 if (ret) { 1913 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1914 ret); 1915 goto out_free; 1916 } 1917 1918 ret = 0; 1919 1920 out_free: 1921 kfree(data); 1922 1923 out: 1924 return ret; 1925 } 1926 1927 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1928 { 1929 size_t data_len; 1930 void *data = NULL; 1931 int ret; 1932 1933 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1934 if (ret) { 1935 if (ret != -EOPNOTSUPP) 1936 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1937 ret); 1938 goto out_free; 1939 } 1940 1941 ret = ath10k_download_board_data(ar, data, data_len); 1942 if (ret) { 1943 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1944 ret); 1945 goto out_free; 1946 } 1947 1948 ret = 0; 1949 1950 out_free: 1951 kfree(data); 1952 1953 return ret; 1954 } 1955 1956 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1957 { 1958 struct nvmem_cell *cell; 1959 void *buf; 1960 size_t len; 1961 int ret; 1962 1963 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1964 if (IS_ERR(cell)) { 1965 ret = PTR_ERR(cell); 1966 return ret; 1967 } 1968 1969 buf = nvmem_cell_read(cell, &len); 1970 if (IS_ERR(buf)) 1971 return PTR_ERR(buf); 1972 1973 if (ar->hw_params.cal_data_len != len) { 1974 kfree(buf); 1975 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1976 cell_name, len, ar->hw_params.cal_data_len); 1977 return -EMSGSIZE; 1978 } 1979 1980 ret = ath10k_download_board_data(ar, buf, len); 1981 kfree(buf); 1982 if (ret) 1983 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 1984 cell_name, ret); 1985 1986 return ret; 1987 } 1988 1989 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1990 struct ath10k_fw_file *fw_file) 1991 { 1992 size_t magic_len, len, ie_len; 1993 int ie_id, i, index, bit, ret; 1994 struct ath10k_fw_ie *hdr; 1995 const u8 *data; 1996 __le32 *timestamp, *version; 1997 1998 /* first fetch the firmware file (firmware-*.bin) */ 1999 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 2000 name); 2001 if (IS_ERR(fw_file->firmware)) 2002 return PTR_ERR(fw_file->firmware); 2003 2004 data = fw_file->firmware->data; 2005 len = fw_file->firmware->size; 2006 2007 /* magic also includes the null byte, check that as well */ 2008 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 2009 2010 if (len < magic_len) { 2011 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 2012 ar->hw_params.fw.dir, name, len); 2013 ret = -EINVAL; 2014 goto err; 2015 } 2016 2017 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 2018 ath10k_err(ar, "invalid firmware magic\n"); 2019 ret = -EINVAL; 2020 goto err; 2021 } 2022 2023 /* jump over the padding */ 2024 magic_len = ALIGN(magic_len, 4); 2025 2026 len -= magic_len; 2027 data += magic_len; 2028 2029 /* loop elements */ 2030 while (len > sizeof(struct ath10k_fw_ie)) { 2031 hdr = (struct ath10k_fw_ie *)data; 2032 2033 ie_id = le32_to_cpu(hdr->id); 2034 ie_len = le32_to_cpu(hdr->len); 2035 2036 len -= sizeof(*hdr); 2037 data += sizeof(*hdr); 2038 2039 if (len < ie_len) { 2040 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 2041 ie_id, len, ie_len); 2042 ret = -EINVAL; 2043 goto err; 2044 } 2045 2046 switch (ie_id) { 2047 case ATH10K_FW_IE_FW_VERSION: 2048 if (ie_len > sizeof(fw_file->fw_version) - 1) 2049 break; 2050 2051 memcpy(fw_file->fw_version, data, ie_len); 2052 fw_file->fw_version[ie_len] = '\0'; 2053 2054 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2055 "found fw version %s\n", 2056 fw_file->fw_version); 2057 break; 2058 case ATH10K_FW_IE_TIMESTAMP: 2059 if (ie_len != sizeof(u32)) 2060 break; 2061 2062 timestamp = (__le32 *)data; 2063 2064 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2065 le32_to_cpup(timestamp)); 2066 break; 2067 case ATH10K_FW_IE_FEATURES: 2068 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2069 "found firmware features ie (%zd B)\n", 2070 ie_len); 2071 2072 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2073 index = i / 8; 2074 bit = i % 8; 2075 2076 if (index == ie_len) 2077 break; 2078 2079 if (data[index] & (1 << bit)) { 2080 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2081 "Enabling feature bit: %i\n", 2082 i); 2083 __set_bit(i, fw_file->fw_features); 2084 } 2085 } 2086 2087 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2088 fw_file->fw_features, 2089 sizeof(fw_file->fw_features)); 2090 break; 2091 case ATH10K_FW_IE_FW_IMAGE: 2092 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2093 "found fw image ie (%zd B)\n", 2094 ie_len); 2095 2096 fw_file->firmware_data = data; 2097 fw_file->firmware_len = ie_len; 2098 2099 break; 2100 case ATH10K_FW_IE_OTP_IMAGE: 2101 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2102 "found otp image ie (%zd B)\n", 2103 ie_len); 2104 2105 fw_file->otp_data = data; 2106 fw_file->otp_len = ie_len; 2107 2108 break; 2109 case ATH10K_FW_IE_WMI_OP_VERSION: 2110 if (ie_len != sizeof(u32)) 2111 break; 2112 2113 version = (__le32 *)data; 2114 2115 fw_file->wmi_op_version = le32_to_cpup(version); 2116 2117 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2118 fw_file->wmi_op_version); 2119 break; 2120 case ATH10K_FW_IE_HTT_OP_VERSION: 2121 if (ie_len != sizeof(u32)) 2122 break; 2123 2124 version = (__le32 *)data; 2125 2126 fw_file->htt_op_version = le32_to_cpup(version); 2127 2128 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2129 fw_file->htt_op_version); 2130 break; 2131 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2132 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2133 "found fw code swap image ie (%zd B)\n", 2134 ie_len); 2135 fw_file->codeswap_data = data; 2136 fw_file->codeswap_len = ie_len; 2137 break; 2138 default: 2139 ath10k_warn(ar, "Unknown FW IE: %u\n", 2140 le32_to_cpu(hdr->id)); 2141 break; 2142 } 2143 2144 /* jump over the padding */ 2145 ie_len = ALIGN(ie_len, 4); 2146 2147 len -= ie_len; 2148 data += ie_len; 2149 } 2150 2151 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2152 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2153 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2154 ar->hw_params.fw.dir, name); 2155 ret = -ENOMEDIUM; 2156 goto err; 2157 } 2158 2159 return 0; 2160 2161 err: 2162 ath10k_core_free_firmware_files(ar); 2163 return ret; 2164 } 2165 2166 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2167 size_t fw_name_len, int fw_api) 2168 { 2169 switch (ar->hif.bus) { 2170 case ATH10K_BUS_SDIO: 2171 case ATH10K_BUS_USB: 2172 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2173 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2174 fw_api); 2175 break; 2176 case ATH10K_BUS_PCI: 2177 case ATH10K_BUS_AHB: 2178 case ATH10K_BUS_SNOC: 2179 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2180 ATH10K_FW_FILE_BASE, fw_api); 2181 break; 2182 } 2183 } 2184 2185 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2186 { 2187 int ret, i; 2188 char fw_name[100]; 2189 2190 /* calibration file is optional, don't check for any errors */ 2191 ath10k_fetch_cal_file(ar); 2192 2193 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2194 ar->fw_api = i; 2195 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2196 ar->fw_api); 2197 2198 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2199 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2200 &ar->normal_mode_fw.fw_file); 2201 if (!ret) 2202 goto success; 2203 } 2204 2205 /* we end up here if we couldn't fetch any firmware */ 2206 2207 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2208 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2209 ret); 2210 2211 return ret; 2212 2213 success: 2214 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2215 2216 return 0; 2217 } 2218 2219 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2220 { 2221 int ret; 2222 2223 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2224 if (ret == 0) { 2225 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2226 goto success; 2227 } else if (ret == -EPROBE_DEFER) { 2228 return ret; 2229 } 2230 2231 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2232 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2233 ret); 2234 2235 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2236 if (ret == 0) { 2237 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2238 goto success; 2239 } 2240 2241 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2242 "boot did not find a pre calibration file, try DT next: %d\n", 2243 ret); 2244 2245 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2246 if (ret) { 2247 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2248 "unable to load pre cal data from DT: %d\n", ret); 2249 return ret; 2250 } 2251 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2252 2253 success: 2254 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2255 ath10k_cal_mode_str(ar->cal_mode)); 2256 2257 return 0; 2258 } 2259 2260 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2261 { 2262 int ret; 2263 2264 ret = ath10k_core_pre_cal_download(ar); 2265 if (ret) { 2266 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2267 "failed to load pre cal data: %d\n", ret); 2268 return ret; 2269 } 2270 2271 ret = ath10k_core_get_board_id_from_otp(ar); 2272 if (ret) { 2273 ath10k_err(ar, "failed to get board id: %d\n", ret); 2274 return ret; 2275 } 2276 2277 ret = ath10k_download_and_run_otp(ar); 2278 if (ret) { 2279 ath10k_err(ar, "failed to run otp: %d\n", ret); 2280 return ret; 2281 } 2282 2283 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2284 "pre cal configuration done successfully\n"); 2285 2286 return 0; 2287 } 2288 2289 static int ath10k_download_cal_data(struct ath10k *ar) 2290 { 2291 int ret; 2292 2293 ret = ath10k_core_pre_cal_config(ar); 2294 if (ret == 0) 2295 return 0; 2296 2297 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2298 "pre cal download procedure failed, try cal file: %d\n", 2299 ret); 2300 2301 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2302 if (ret == 0) { 2303 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2304 goto done; 2305 } else if (ret == -EPROBE_DEFER) { 2306 return ret; 2307 } 2308 2309 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2310 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2311 ret); 2312 2313 ret = ath10k_download_cal_file(ar, ar->cal_file); 2314 if (ret == 0) { 2315 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2316 goto done; 2317 } 2318 2319 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2320 "boot did not find a calibration file, try DT next: %d\n", 2321 ret); 2322 2323 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2324 if (ret == 0) { 2325 ar->cal_mode = ATH10K_CAL_MODE_DT; 2326 goto done; 2327 } 2328 2329 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2330 "boot did not find DT entry, try target EEPROM next: %d\n", 2331 ret); 2332 2333 ret = ath10k_download_cal_eeprom(ar); 2334 if (ret == 0) { 2335 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2336 goto done; 2337 } 2338 2339 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2340 "boot did not find target EEPROM entry, try OTP next: %d\n", 2341 ret); 2342 2343 ret = ath10k_download_and_run_otp(ar); 2344 if (ret) { 2345 ath10k_err(ar, "failed to run otp: %d\n", ret); 2346 return ret; 2347 } 2348 2349 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2350 2351 done: 2352 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2353 ath10k_cal_mode_str(ar->cal_mode)); 2354 return 0; 2355 } 2356 2357 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2358 { 2359 struct device_node *node; 2360 u8 coex_support = 0; 2361 int ret; 2362 2363 node = ar->dev->of_node; 2364 if (!node) 2365 goto out; 2366 2367 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2368 if (ret) { 2369 ar->coex_support = true; 2370 goto out; 2371 } 2372 2373 if (coex_support) { 2374 ar->coex_support = true; 2375 } else { 2376 ar->coex_support = false; 2377 ar->coex_gpio_pin = -1; 2378 goto out; 2379 } 2380 2381 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2382 &ar->coex_gpio_pin); 2383 if (ret) 2384 ar->coex_gpio_pin = -1; 2385 2386 out: 2387 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2388 ar->coex_support, ar->coex_gpio_pin); 2389 } 2390 2391 static int ath10k_init_uart(struct ath10k *ar) 2392 { 2393 int ret; 2394 2395 /* 2396 * Explicitly setting UART prints to zero as target turns it on 2397 * based on scratch registers. 2398 */ 2399 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2400 if (ret) { 2401 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2402 return ret; 2403 } 2404 2405 if (!uart_print) { 2406 if (ar->hw_params.uart_pin_workaround) { 2407 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2408 ar->hw_params.uart_pin); 2409 if (ret) { 2410 ath10k_warn(ar, "failed to set UART TX pin: %d", 2411 ret); 2412 return ret; 2413 } 2414 } 2415 2416 return 0; 2417 } 2418 2419 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2420 if (ret) { 2421 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2422 return ret; 2423 } 2424 2425 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2426 if (ret) { 2427 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2428 return ret; 2429 } 2430 2431 /* Set the UART baud rate to 19200. */ 2432 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2433 if (ret) { 2434 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2435 return ret; 2436 } 2437 2438 ath10k_info(ar, "UART prints enabled\n"); 2439 return 0; 2440 } 2441 2442 static int ath10k_init_hw_params(struct ath10k *ar) 2443 { 2444 const struct ath10k_hw_params *hw_params; 2445 int i; 2446 2447 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2448 hw_params = &ath10k_hw_params_list[i]; 2449 2450 if (hw_params->bus == ar->hif.bus && 2451 hw_params->id == ar->target_version && 2452 hw_params->dev_id == ar->dev_id) 2453 break; 2454 } 2455 2456 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2457 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2458 ar->target_version); 2459 return -EINVAL; 2460 } 2461 2462 ar->hw_params = *hw_params; 2463 2464 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2465 ar->hw_params.name, ar->target_version); 2466 2467 return 0; 2468 } 2469 2470 void ath10k_core_start_recovery(struct ath10k *ar) 2471 { 2472 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2473 ath10k_warn(ar, "already restarting\n"); 2474 return; 2475 } 2476 2477 queue_work(ar->workqueue, &ar->restart_work); 2478 } 2479 EXPORT_SYMBOL(ath10k_core_start_recovery); 2480 2481 void ath10k_core_napi_enable(struct ath10k *ar) 2482 { 2483 lockdep_assert_held(&ar->conf_mutex); 2484 2485 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2486 return; 2487 2488 napi_enable(&ar->napi); 2489 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2490 } 2491 EXPORT_SYMBOL(ath10k_core_napi_enable); 2492 2493 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2494 { 2495 lockdep_assert_held(&ar->conf_mutex); 2496 2497 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2498 return; 2499 2500 napi_synchronize(&ar->napi); 2501 napi_disable(&ar->napi); 2502 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2503 } 2504 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2505 2506 static void ath10k_core_restart(struct work_struct *work) 2507 { 2508 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2509 int ret; 2510 2511 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2512 2513 /* Place a barrier to make sure the compiler doesn't reorder 2514 * CRASH_FLUSH and calling other functions. 2515 */ 2516 barrier(); 2517 2518 ieee80211_stop_queues(ar->hw); 2519 ath10k_drain_tx(ar); 2520 complete(&ar->scan.started); 2521 complete(&ar->scan.completed); 2522 complete(&ar->scan.on_channel); 2523 complete(&ar->offchan_tx_completed); 2524 complete(&ar->install_key_done); 2525 complete(&ar->vdev_setup_done); 2526 complete(&ar->vdev_delete_done); 2527 complete(&ar->thermal.wmi_sync); 2528 complete(&ar->bss_survey_done); 2529 wake_up(&ar->htt.empty_tx_wq); 2530 wake_up(&ar->wmi.tx_credits_wq); 2531 wake_up(&ar->peer_mapping_wq); 2532 2533 /* TODO: We can have one instance of cancelling coverage_class_work by 2534 * moving it to ath10k_halt(), so that both stop() and restart() would 2535 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2536 * with conf_mutex it will deadlock. 2537 */ 2538 cancel_work_sync(&ar->set_coverage_class_work); 2539 2540 mutex_lock(&ar->conf_mutex); 2541 2542 switch (ar->state) { 2543 case ATH10K_STATE_ON: 2544 ar->state = ATH10K_STATE_RESTARTING; 2545 ath10k_halt(ar); 2546 ath10k_scan_finish(ar); 2547 ieee80211_restart_hw(ar->hw); 2548 break; 2549 case ATH10K_STATE_OFF: 2550 /* this can happen if driver is being unloaded 2551 * or if the crash happens during FW probing 2552 */ 2553 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2554 break; 2555 case ATH10K_STATE_RESTARTING: 2556 /* hw restart might be requested from multiple places */ 2557 break; 2558 case ATH10K_STATE_RESTARTED: 2559 ar->state = ATH10K_STATE_WEDGED; 2560 fallthrough; 2561 case ATH10K_STATE_WEDGED: 2562 ath10k_warn(ar, "device is wedged, will not restart\n"); 2563 break; 2564 case ATH10K_STATE_UTF: 2565 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2566 break; 2567 } 2568 2569 mutex_unlock(&ar->conf_mutex); 2570 2571 ret = ath10k_coredump_submit(ar); 2572 if (ret) 2573 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2574 ret); 2575 2576 complete(&ar->driver_recovery); 2577 } 2578 2579 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2580 { 2581 struct ath10k *ar = container_of(work, struct ath10k, 2582 set_coverage_class_work); 2583 2584 if (ar->hw_params.hw_ops->set_coverage_class) 2585 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2586 } 2587 2588 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2589 { 2590 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2591 int max_num_peers; 2592 2593 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2594 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2595 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2596 return -EINVAL; 2597 } 2598 2599 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2600 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2601 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2602 return -EINVAL; 2603 } 2604 2605 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2606 switch (ath10k_cryptmode_param) { 2607 case ATH10K_CRYPT_MODE_HW: 2608 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2609 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2610 break; 2611 case ATH10K_CRYPT_MODE_SW: 2612 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2613 fw_file->fw_features)) { 2614 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2615 return -EINVAL; 2616 } 2617 2618 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2619 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2620 break; 2621 default: 2622 ath10k_info(ar, "invalid cryptmode: %d\n", 2623 ath10k_cryptmode_param); 2624 return -EINVAL; 2625 } 2626 2627 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2628 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2629 2630 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) { 2631 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2632 fw_file->fw_features)) { 2633 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2634 return -EINVAL; 2635 } 2636 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2637 } 2638 2639 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2640 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2641 2642 /* Workaround: 2643 * 2644 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2645 * and causes enormous performance issues (malformed frames, 2646 * etc). 2647 * 2648 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2649 * albeit a bit slower compared to regular operation. 2650 */ 2651 ar->htt.max_num_amsdu = 1; 2652 } 2653 2654 /* Backwards compatibility for firmwares without 2655 * ATH10K_FW_IE_WMI_OP_VERSION. 2656 */ 2657 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2658 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2659 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2660 fw_file->fw_features)) 2661 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2662 else 2663 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2664 } else { 2665 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2666 } 2667 } 2668 2669 switch (fw_file->wmi_op_version) { 2670 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2671 max_num_peers = TARGET_NUM_PEERS; 2672 ar->max_num_stations = TARGET_NUM_STATIONS; 2673 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2674 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2675 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2676 WMI_STAT_PEER; 2677 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2678 break; 2679 case ATH10K_FW_WMI_OP_VERSION_10_1: 2680 case ATH10K_FW_WMI_OP_VERSION_10_2: 2681 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2682 if (ath10k_peer_stats_enabled(ar)) { 2683 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2684 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2685 } else { 2686 max_num_peers = TARGET_10X_NUM_PEERS; 2687 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2688 } 2689 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2690 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2691 ar->fw_stats_req_mask = WMI_STAT_PEER; 2692 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2693 break; 2694 case ATH10K_FW_WMI_OP_VERSION_TLV: 2695 max_num_peers = TARGET_TLV_NUM_PEERS; 2696 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2697 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2698 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2699 if (ar->hif.bus == ATH10K_BUS_SDIO) 2700 ar->htt.max_num_pending_tx = 2701 TARGET_TLV_NUM_MSDU_DESC_HL; 2702 else 2703 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2704 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2705 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2706 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2707 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2708 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2709 break; 2710 case ATH10K_FW_WMI_OP_VERSION_10_4: 2711 max_num_peers = TARGET_10_4_NUM_PEERS; 2712 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2713 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2714 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2715 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2716 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2717 WMI_10_4_STAT_PEER_EXTD | 2718 WMI_10_4_STAT_VDEV_EXTD; 2719 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2720 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2721 2722 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2723 fw_file->fw_features)) 2724 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2725 else 2726 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2727 break; 2728 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2729 case ATH10K_FW_WMI_OP_VERSION_MAX: 2730 default: 2731 WARN_ON(1); 2732 return -EINVAL; 2733 } 2734 2735 if (ar->hw_params.num_peers) 2736 ar->max_num_peers = ar->hw_params.num_peers; 2737 else 2738 ar->max_num_peers = max_num_peers; 2739 2740 /* Backwards compatibility for firmwares without 2741 * ATH10K_FW_IE_HTT_OP_VERSION. 2742 */ 2743 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2744 switch (fw_file->wmi_op_version) { 2745 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2746 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2747 break; 2748 case ATH10K_FW_WMI_OP_VERSION_10_1: 2749 case ATH10K_FW_WMI_OP_VERSION_10_2: 2750 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2751 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2752 break; 2753 case ATH10K_FW_WMI_OP_VERSION_TLV: 2754 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2755 break; 2756 case ATH10K_FW_WMI_OP_VERSION_10_4: 2757 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2758 case ATH10K_FW_WMI_OP_VERSION_MAX: 2759 ath10k_err(ar, "htt op version not found from fw meta data"); 2760 return -EINVAL; 2761 } 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2768 { 2769 int ret; 2770 int vdev_id; 2771 int vdev_type; 2772 int vdev_subtype; 2773 const u8 *vdev_addr; 2774 2775 vdev_id = 0; 2776 vdev_type = WMI_VDEV_TYPE_STA; 2777 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2778 vdev_addr = ar->mac_addr; 2779 2780 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2781 vdev_addr); 2782 if (ret) { 2783 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2784 return ret; 2785 } 2786 2787 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2788 if (ret) { 2789 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2790 return ret; 2791 } 2792 2793 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2794 * serialized properly implicitly. 2795 * 2796 * Moreover (most) WMI commands have no explicit acknowledges. It is 2797 * possible to infer it implicitly by poking firmware with echo 2798 * command - getting a reply means all preceding comments have been 2799 * (mostly) processed. 2800 * 2801 * In case of vdev create/delete this is sufficient. 2802 * 2803 * Without this it's possible to end up with a race when HTT Rx ring is 2804 * started before vdev create/delete hack is complete allowing a short 2805 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2806 */ 2807 ret = ath10k_wmi_barrier(ar); 2808 if (ret) { 2809 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2810 return ret; 2811 } 2812 2813 return 0; 2814 } 2815 2816 static int ath10k_core_compat_services(struct ath10k *ar) 2817 { 2818 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2819 2820 /* all 10.x firmware versions support thermal throttling but don't 2821 * advertise the support via service flags so we have to hardcode 2822 * it here 2823 */ 2824 switch (fw_file->wmi_op_version) { 2825 case ATH10K_FW_WMI_OP_VERSION_10_1: 2826 case ATH10K_FW_WMI_OP_VERSION_10_2: 2827 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2828 case ATH10K_FW_WMI_OP_VERSION_10_4: 2829 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2830 break; 2831 default: 2832 break; 2833 } 2834 2835 return 0; 2836 } 2837 2838 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2839 2840 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2841 { 2842 const struct ath10k_hw_mem_layout *hw_mem; 2843 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2844 dma_addr_t paddr; 2845 void *vaddr = NULL; 2846 u8 num_read_itr; 2847 int i, ret; 2848 u32 len, remaining_len; 2849 2850 /* copy target iram feature must work also when 2851 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2852 * _ath10k_coredump_get_mem_layout() to accomplist that 2853 */ 2854 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2855 if (!hw_mem) 2856 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2857 * just silently disable the feature by doing nothing 2858 */ 2859 return 0; 2860 2861 for (i = 0; i < hw_mem->region_table.size; i++) { 2862 tmp = &hw_mem->region_table.regions[i]; 2863 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2864 mem_region = tmp; 2865 break; 2866 } 2867 } 2868 2869 if (!mem_region) 2870 return -ENOMEM; 2871 2872 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2873 if (ar->wmi.mem_chunks[i].req_id == 2874 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2875 vaddr = ar->wmi.mem_chunks[i].vaddr; 2876 len = ar->wmi.mem_chunks[i].len; 2877 break; 2878 } 2879 } 2880 2881 if (!vaddr || !len) { 2882 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2883 return -ENOMEM; 2884 } 2885 2886 len = (len < mem_region->len) ? len : mem_region->len; 2887 paddr = mem_region->start; 2888 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2889 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2890 for (i = 0; i < num_read_itr; i++) { 2891 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2892 TGT_IRAM_READ_PER_ITR); 2893 if (ret) { 2894 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2895 ret); 2896 return ret; 2897 } 2898 2899 paddr += TGT_IRAM_READ_PER_ITR; 2900 vaddr += TGT_IRAM_READ_PER_ITR; 2901 } 2902 2903 if (remaining_len) { 2904 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2905 if (ret) { 2906 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2907 ret); 2908 return ret; 2909 } 2910 } 2911 2912 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2913 2914 return 0; 2915 } 2916 2917 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2918 const struct ath10k_fw_components *fw) 2919 { 2920 int status; 2921 u32 val; 2922 2923 lockdep_assert_held(&ar->conf_mutex); 2924 2925 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2926 2927 ar->running_fw = fw; 2928 2929 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2930 ar->running_fw->fw_file.fw_features)) { 2931 ath10k_bmi_start(ar); 2932 2933 /* Enable hardware clock to speed up firmware download */ 2934 if (ar->hw_params.hw_ops->enable_pll_clk) { 2935 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2936 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2937 status); 2938 } 2939 2940 if (ath10k_init_configure_target(ar)) { 2941 status = -EINVAL; 2942 goto err; 2943 } 2944 2945 status = ath10k_download_cal_data(ar); 2946 if (status) 2947 goto err; 2948 2949 /* Some of qca988x solutions are having global reset issue 2950 * during target initialization. Bypassing PLL setting before 2951 * downloading firmware and letting the SoC run on REF_CLK is 2952 * fixing the problem. Corresponding firmware change is also 2953 * needed to set the clock source once the target is 2954 * initialized. 2955 */ 2956 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2957 ar->running_fw->fw_file.fw_features)) { 2958 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2959 if (status) { 2960 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2961 status); 2962 goto err; 2963 } 2964 } 2965 2966 status = ath10k_download_fw(ar); 2967 if (status) 2968 goto err; 2969 2970 status = ath10k_init_uart(ar); 2971 if (status) 2972 goto err; 2973 2974 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2975 status = ath10k_init_sdio(ar, mode); 2976 if (status) { 2977 ath10k_err(ar, "failed to init SDIO: %d\n", status); 2978 goto err; 2979 } 2980 } 2981 } 2982 2983 ar->htc.htc_ops.target_send_suspend_complete = 2984 ath10k_send_suspend_complete; 2985 2986 status = ath10k_htc_init(ar); 2987 if (status) { 2988 ath10k_err(ar, "could not init HTC (%d)\n", status); 2989 goto err; 2990 } 2991 2992 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2993 ar->running_fw->fw_file.fw_features)) { 2994 status = ath10k_bmi_done(ar); 2995 if (status) 2996 goto err; 2997 } 2998 2999 status = ath10k_wmi_attach(ar); 3000 if (status) { 3001 ath10k_err(ar, "WMI attach failed: %d\n", status); 3002 goto err; 3003 } 3004 3005 status = ath10k_htt_init(ar); 3006 if (status) { 3007 ath10k_err(ar, "failed to init htt: %d\n", status); 3008 goto err_wmi_detach; 3009 } 3010 3011 status = ath10k_htt_tx_start(&ar->htt); 3012 if (status) { 3013 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 3014 goto err_wmi_detach; 3015 } 3016 3017 /* If firmware indicates Full Rx Reorder support it must be used in a 3018 * slightly different manner. Let HTT code know. 3019 */ 3020 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 3021 ar->wmi.svc_map)); 3022 3023 status = ath10k_htt_rx_alloc(&ar->htt); 3024 if (status) { 3025 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 3026 goto err_htt_tx_detach; 3027 } 3028 3029 status = ath10k_hif_start(ar); 3030 if (status) { 3031 ath10k_err(ar, "could not start HIF: %d\n", status); 3032 goto err_htt_rx_detach; 3033 } 3034 3035 status = ath10k_htc_wait_target(&ar->htc); 3036 if (status) { 3037 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 3038 goto err_hif_stop; 3039 } 3040 3041 status = ath10k_hif_start_post(ar); 3042 if (status) { 3043 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3044 goto err_hif_stop; 3045 } 3046 3047 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3048 status = ath10k_htt_connect(&ar->htt); 3049 if (status) { 3050 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3051 goto err_hif_stop; 3052 } 3053 } 3054 3055 status = ath10k_wmi_connect(ar); 3056 if (status) { 3057 ath10k_err(ar, "could not connect wmi: %d\n", status); 3058 goto err_hif_stop; 3059 } 3060 3061 status = ath10k_htc_start(&ar->htc); 3062 if (status) { 3063 ath10k_err(ar, "failed to start htc: %d\n", status); 3064 goto err_hif_stop; 3065 } 3066 3067 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3068 status = ath10k_wmi_wait_for_service_ready(ar); 3069 if (status) { 3070 ath10k_warn(ar, "wmi service ready event not received"); 3071 goto err_hif_stop; 3072 } 3073 } 3074 3075 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3076 ar->hw->wiphy->fw_version); 3077 3078 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3079 ar->running_fw->fw_file.fw_features)) { 3080 status = ath10k_core_copy_target_iram(ar); 3081 if (status) { 3082 ath10k_warn(ar, "failed to copy target iram contents: %d", 3083 status); 3084 goto err_hif_stop; 3085 } 3086 } 3087 3088 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3089 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3090 val = 0; 3091 if (ath10k_peer_stats_enabled(ar)) 3092 val = WMI_10_4_PEER_STATS; 3093 3094 /* Enable vdev stats by default */ 3095 val |= WMI_10_4_VDEV_STATS; 3096 3097 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3098 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3099 3100 ath10k_core_fetch_btcoex_dt(ar); 3101 3102 /* 10.4 firmware supports BT-Coex without reloading firmware 3103 * via pdev param. To support Bluetooth coexistence pdev param, 3104 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3105 * enabled always. 3106 * 3107 * We can still enable BTCOEX if firmware has the support 3108 * even though btceox_support value is 3109 * ATH10K_DT_BTCOEX_NOT_FOUND 3110 */ 3111 3112 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3113 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3114 ar->running_fw->fw_file.fw_features) && 3115 ar->coex_support) 3116 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3117 3118 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3119 ar->wmi.svc_map)) 3120 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3121 3122 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3123 ar->wmi.svc_map)) 3124 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3125 3126 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3127 ar->wmi.svc_map)) 3128 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3129 3130 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3131 val |= WMI_10_4_REPORT_AIRTIME; 3132 3133 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3134 ar->wmi.svc_map)) 3135 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3136 3137 status = ath10k_mac_ext_resource_config(ar, val); 3138 if (status) { 3139 ath10k_err(ar, 3140 "failed to send ext resource cfg command : %d\n", 3141 status); 3142 goto err_hif_stop; 3143 } 3144 } 3145 3146 status = ath10k_wmi_cmd_init(ar); 3147 if (status) { 3148 ath10k_err(ar, "could not send WMI init command (%d)\n", 3149 status); 3150 goto err_hif_stop; 3151 } 3152 3153 status = ath10k_wmi_wait_for_unified_ready(ar); 3154 if (status) { 3155 ath10k_err(ar, "wmi unified ready event not received\n"); 3156 goto err_hif_stop; 3157 } 3158 3159 status = ath10k_core_compat_services(ar); 3160 if (status) { 3161 ath10k_err(ar, "compat services failed: %d\n", status); 3162 goto err_hif_stop; 3163 } 3164 3165 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3166 if (status && status != -EOPNOTSUPP) { 3167 ath10k_err(ar, 3168 "failed to set base mac address: %d\n", status); 3169 goto err_hif_stop; 3170 } 3171 3172 /* Some firmware revisions do not properly set up hardware rx filter 3173 * registers. 3174 * 3175 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3176 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3177 * any frames that matches MAC_PCU_RX_FILTER which is also 3178 * misconfigured to accept anything. 3179 * 3180 * The ADDR1 is programmed using internal firmware structure field and 3181 * can't be (easily/sanely) reached from the driver explicitly. It is 3182 * possible to implicitly make it correct by creating a dummy vdev and 3183 * then deleting it. 3184 */ 3185 if (ar->hw_params.hw_filter_reset_required && 3186 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3187 status = ath10k_core_reset_rx_filter(ar); 3188 if (status) { 3189 ath10k_err(ar, 3190 "failed to reset rx filter: %d\n", status); 3191 goto err_hif_stop; 3192 } 3193 } 3194 3195 status = ath10k_htt_rx_ring_refill(ar); 3196 if (status) { 3197 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3198 goto err_hif_stop; 3199 } 3200 3201 if (ar->max_num_vdevs >= 64) 3202 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3203 else 3204 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3205 3206 INIT_LIST_HEAD(&ar->arvifs); 3207 3208 /* we don't care about HTT in UTF mode */ 3209 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3210 status = ath10k_htt_setup(&ar->htt); 3211 if (status) { 3212 ath10k_err(ar, "failed to setup htt: %d\n", status); 3213 goto err_hif_stop; 3214 } 3215 } 3216 3217 status = ath10k_debug_start(ar); 3218 if (status) 3219 goto err_hif_stop; 3220 3221 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3222 if (status && status != -EOPNOTSUPP) { 3223 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3224 goto err_hif_stop; 3225 } 3226 3227 return 0; 3228 3229 err_hif_stop: 3230 ath10k_hif_stop(ar); 3231 err_htt_rx_detach: 3232 ath10k_htt_rx_free(&ar->htt); 3233 err_htt_tx_detach: 3234 ath10k_htt_tx_free(&ar->htt); 3235 err_wmi_detach: 3236 ath10k_wmi_detach(ar); 3237 err: 3238 return status; 3239 } 3240 EXPORT_SYMBOL(ath10k_core_start); 3241 3242 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3243 { 3244 int ret; 3245 unsigned long time_left; 3246 3247 reinit_completion(&ar->target_suspend); 3248 3249 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3250 if (ret) { 3251 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3252 return ret; 3253 } 3254 3255 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3256 3257 if (!time_left) { 3258 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3259 return -ETIMEDOUT; 3260 } 3261 3262 return 0; 3263 } 3264 3265 void ath10k_core_stop(struct ath10k *ar) 3266 { 3267 lockdep_assert_held(&ar->conf_mutex); 3268 ath10k_debug_stop(ar); 3269 3270 /* try to suspend target */ 3271 if (ar->state != ATH10K_STATE_RESTARTING && 3272 ar->state != ATH10K_STATE_UTF) 3273 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3274 3275 ath10k_hif_stop(ar); 3276 ath10k_htt_tx_stop(&ar->htt); 3277 ath10k_htt_rx_free(&ar->htt); 3278 ath10k_wmi_detach(ar); 3279 3280 ar->id.bmi_ids_valid = false; 3281 } 3282 EXPORT_SYMBOL(ath10k_core_stop); 3283 3284 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3285 * order to know what hw capabilities should be advertised to mac80211 it is 3286 * necessary to load the firmware (and tear it down immediately since start 3287 * hook will try to init it again) before registering 3288 */ 3289 static int ath10k_core_probe_fw(struct ath10k *ar) 3290 { 3291 struct bmi_target_info target_info; 3292 int ret = 0; 3293 3294 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3295 if (ret) { 3296 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3297 return ret; 3298 } 3299 3300 switch (ar->hif.bus) { 3301 case ATH10K_BUS_SDIO: 3302 memset(&target_info, 0, sizeof(target_info)); 3303 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3304 if (ret) { 3305 ath10k_err(ar, "could not get target info (%d)\n", ret); 3306 goto err_power_down; 3307 } 3308 ar->target_version = target_info.version; 3309 ar->hw->wiphy->hw_version = target_info.version; 3310 break; 3311 case ATH10K_BUS_PCI: 3312 case ATH10K_BUS_AHB: 3313 case ATH10K_BUS_USB: 3314 memset(&target_info, 0, sizeof(target_info)); 3315 ret = ath10k_bmi_get_target_info(ar, &target_info); 3316 if (ret) { 3317 ath10k_err(ar, "could not get target info (%d)\n", ret); 3318 goto err_power_down; 3319 } 3320 ar->target_version = target_info.version; 3321 ar->hw->wiphy->hw_version = target_info.version; 3322 break; 3323 case ATH10K_BUS_SNOC: 3324 memset(&target_info, 0, sizeof(target_info)); 3325 ret = ath10k_hif_get_target_info(ar, &target_info); 3326 if (ret) { 3327 ath10k_err(ar, "could not get target info (%d)\n", ret); 3328 goto err_power_down; 3329 } 3330 ar->target_version = target_info.version; 3331 ar->hw->wiphy->hw_version = target_info.version; 3332 break; 3333 default: 3334 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3335 } 3336 3337 ret = ath10k_init_hw_params(ar); 3338 if (ret) { 3339 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3340 goto err_power_down; 3341 } 3342 3343 ret = ath10k_core_fetch_firmware_files(ar); 3344 if (ret) { 3345 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3346 goto err_power_down; 3347 } 3348 3349 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3350 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3351 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3352 sizeof(ar->hw->wiphy->fw_version)); 3353 3354 ath10k_debug_print_hwfw_info(ar); 3355 3356 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3357 ar->normal_mode_fw.fw_file.fw_features)) { 3358 ret = ath10k_core_pre_cal_download(ar); 3359 if (ret) { 3360 /* pre calibration data download is not necessary 3361 * for all the chipsets. Ignore failures and continue. 3362 */ 3363 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3364 "could not load pre cal data: %d\n", ret); 3365 } 3366 3367 ret = ath10k_core_get_board_id_from_otp(ar); 3368 if (ret && ret != -EOPNOTSUPP) { 3369 ath10k_err(ar, "failed to get board id from otp: %d\n", 3370 ret); 3371 goto err_free_firmware_files; 3372 } 3373 3374 ret = ath10k_core_check_smbios(ar); 3375 if (ret) 3376 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3377 3378 ret = ath10k_core_check_dt(ar); 3379 if (ret) 3380 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3381 3382 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3383 if (ret) { 3384 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3385 goto err_free_firmware_files; 3386 } 3387 3388 ath10k_debug_print_board_info(ar); 3389 } 3390 3391 device_get_mac_address(ar->dev, ar->mac_addr); 3392 3393 ret = ath10k_core_init_firmware_features(ar); 3394 if (ret) { 3395 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3396 ret); 3397 goto err_free_firmware_files; 3398 } 3399 3400 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3401 ar->normal_mode_fw.fw_file.fw_features)) { 3402 ret = ath10k_swap_code_seg_init(ar, 3403 &ar->normal_mode_fw.fw_file); 3404 if (ret) { 3405 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3406 ret); 3407 goto err_free_firmware_files; 3408 } 3409 } 3410 3411 mutex_lock(&ar->conf_mutex); 3412 3413 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3414 &ar->normal_mode_fw); 3415 if (ret) { 3416 ath10k_err(ar, "could not init core (%d)\n", ret); 3417 goto err_unlock; 3418 } 3419 3420 ath10k_debug_print_boot_info(ar); 3421 ath10k_core_stop(ar); 3422 3423 mutex_unlock(&ar->conf_mutex); 3424 3425 ath10k_hif_power_down(ar); 3426 return 0; 3427 3428 err_unlock: 3429 mutex_unlock(&ar->conf_mutex); 3430 3431 err_free_firmware_files: 3432 ath10k_core_free_firmware_files(ar); 3433 3434 err_power_down: 3435 ath10k_hif_power_down(ar); 3436 3437 return ret; 3438 } 3439 3440 static void ath10k_core_register_work(struct work_struct *work) 3441 { 3442 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3443 int status; 3444 3445 /* peer stats are enabled by default */ 3446 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3447 3448 status = ath10k_core_probe_fw(ar); 3449 if (status) { 3450 ath10k_err(ar, "could not probe fw (%d)\n", status); 3451 goto err; 3452 } 3453 3454 status = ath10k_mac_register(ar); 3455 if (status) { 3456 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3457 goto err_release_fw; 3458 } 3459 3460 status = ath10k_coredump_register(ar); 3461 if (status) { 3462 ath10k_err(ar, "unable to register coredump\n"); 3463 goto err_unregister_mac; 3464 } 3465 3466 status = ath10k_debug_register(ar); 3467 if (status) { 3468 ath10k_err(ar, "unable to initialize debugfs\n"); 3469 goto err_unregister_coredump; 3470 } 3471 3472 status = ath10k_spectral_create(ar); 3473 if (status) { 3474 ath10k_err(ar, "failed to initialize spectral\n"); 3475 goto err_debug_destroy; 3476 } 3477 3478 status = ath10k_thermal_register(ar); 3479 if (status) { 3480 ath10k_err(ar, "could not register thermal device: %d\n", 3481 status); 3482 goto err_spectral_destroy; 3483 } 3484 3485 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3486 return; 3487 3488 err_spectral_destroy: 3489 ath10k_spectral_destroy(ar); 3490 err_debug_destroy: 3491 ath10k_debug_destroy(ar); 3492 err_unregister_coredump: 3493 ath10k_coredump_unregister(ar); 3494 err_unregister_mac: 3495 ath10k_mac_unregister(ar); 3496 err_release_fw: 3497 ath10k_core_free_firmware_files(ar); 3498 err: 3499 /* TODO: It's probably a good idea to release device from the driver 3500 * but calling device_release_driver() here will cause a deadlock. 3501 */ 3502 return; 3503 } 3504 3505 int ath10k_core_register(struct ath10k *ar, 3506 const struct ath10k_bus_params *bus_params) 3507 { 3508 ar->bus_param = *bus_params; 3509 3510 queue_work(ar->workqueue, &ar->register_work); 3511 3512 return 0; 3513 } 3514 EXPORT_SYMBOL(ath10k_core_register); 3515 3516 void ath10k_core_unregister(struct ath10k *ar) 3517 { 3518 cancel_work_sync(&ar->register_work); 3519 3520 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3521 return; 3522 3523 ath10k_thermal_unregister(ar); 3524 /* Stop spectral before unregistering from mac80211 to remove the 3525 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3526 * would be already be free'd recursively, leading to a double free. 3527 */ 3528 ath10k_spectral_destroy(ar); 3529 3530 /* We must unregister from mac80211 before we stop HTC and HIF. 3531 * Otherwise we will fail to submit commands to FW and mac80211 will be 3532 * unhappy about callback failures. 3533 */ 3534 ath10k_mac_unregister(ar); 3535 3536 ath10k_testmode_destroy(ar); 3537 3538 ath10k_core_free_firmware_files(ar); 3539 ath10k_core_free_board_files(ar); 3540 3541 ath10k_debug_unregister(ar); 3542 } 3543 EXPORT_SYMBOL(ath10k_core_unregister); 3544 3545 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3546 enum ath10k_bus bus, 3547 enum ath10k_hw_rev hw_rev, 3548 const struct ath10k_hif_ops *hif_ops) 3549 { 3550 struct ath10k *ar; 3551 int ret; 3552 3553 ar = ath10k_mac_create(priv_size); 3554 if (!ar) 3555 return NULL; 3556 3557 ar->ath_common.priv = ar; 3558 ar->ath_common.hw = ar->hw; 3559 ar->dev = dev; 3560 ar->hw_rev = hw_rev; 3561 ar->hif.ops = hif_ops; 3562 ar->hif.bus = bus; 3563 3564 switch (hw_rev) { 3565 case ATH10K_HW_QCA988X: 3566 case ATH10K_HW_QCA9887: 3567 ar->regs = &qca988x_regs; 3568 ar->hw_ce_regs = &qcax_ce_regs; 3569 ar->hw_values = &qca988x_values; 3570 break; 3571 case ATH10K_HW_QCA6174: 3572 case ATH10K_HW_QCA9377: 3573 ar->regs = &qca6174_regs; 3574 ar->hw_ce_regs = &qcax_ce_regs; 3575 ar->hw_values = &qca6174_values; 3576 break; 3577 case ATH10K_HW_QCA99X0: 3578 case ATH10K_HW_QCA9984: 3579 ar->regs = &qca99x0_regs; 3580 ar->hw_ce_regs = &qcax_ce_regs; 3581 ar->hw_values = &qca99x0_values; 3582 break; 3583 case ATH10K_HW_QCA9888: 3584 ar->regs = &qca99x0_regs; 3585 ar->hw_ce_regs = &qcax_ce_regs; 3586 ar->hw_values = &qca9888_values; 3587 break; 3588 case ATH10K_HW_QCA4019: 3589 ar->regs = &qca4019_regs; 3590 ar->hw_ce_regs = &qcax_ce_regs; 3591 ar->hw_values = &qca4019_values; 3592 break; 3593 case ATH10K_HW_WCN3990: 3594 ar->regs = &wcn3990_regs; 3595 ar->hw_ce_regs = &wcn3990_ce_regs; 3596 ar->hw_values = &wcn3990_values; 3597 break; 3598 default: 3599 ath10k_err(ar, "unsupported core hardware revision %d\n", 3600 hw_rev); 3601 ret = -EOPNOTSUPP; 3602 goto err_free_mac; 3603 } 3604 3605 init_completion(&ar->scan.started); 3606 init_completion(&ar->scan.completed); 3607 init_completion(&ar->scan.on_channel); 3608 init_completion(&ar->target_suspend); 3609 init_completion(&ar->driver_recovery); 3610 init_completion(&ar->wow.wakeup_completed); 3611 3612 init_completion(&ar->install_key_done); 3613 init_completion(&ar->vdev_setup_done); 3614 init_completion(&ar->vdev_delete_done); 3615 init_completion(&ar->thermal.wmi_sync); 3616 init_completion(&ar->bss_survey_done); 3617 init_completion(&ar->peer_delete_done); 3618 init_completion(&ar->peer_stats_info_complete); 3619 3620 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3621 3622 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3623 if (!ar->workqueue) 3624 goto err_free_mac; 3625 3626 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3627 if (!ar->workqueue_aux) 3628 goto err_free_wq; 3629 3630 ar->workqueue_tx_complete = 3631 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3632 if (!ar->workqueue_tx_complete) 3633 goto err_free_aux_wq; 3634 3635 mutex_init(&ar->conf_mutex); 3636 mutex_init(&ar->dump_mutex); 3637 spin_lock_init(&ar->data_lock); 3638 3639 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3640 spin_lock_init(&ar->queue_lock[ac]); 3641 3642 INIT_LIST_HEAD(&ar->peers); 3643 init_waitqueue_head(&ar->peer_mapping_wq); 3644 init_waitqueue_head(&ar->htt.empty_tx_wq); 3645 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3646 3647 skb_queue_head_init(&ar->htt.rx_indication_head); 3648 3649 init_completion(&ar->offchan_tx_completed); 3650 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3651 skb_queue_head_init(&ar->offchan_tx_queue); 3652 3653 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3654 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3655 3656 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3657 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3658 INIT_WORK(&ar->set_coverage_class_work, 3659 ath10k_core_set_coverage_class_work); 3660 3661 ar->napi_dev = alloc_netdev_dummy(0); 3662 if (!ar->napi_dev) 3663 goto err_free_tx_complete; 3664 3665 ret = ath10k_coredump_create(ar); 3666 if (ret) 3667 goto err_free_netdev; 3668 3669 ret = ath10k_debug_create(ar); 3670 if (ret) 3671 goto err_free_coredump; 3672 3673 return ar; 3674 3675 err_free_coredump: 3676 ath10k_coredump_destroy(ar); 3677 err_free_netdev: 3678 free_netdev(ar->napi_dev); 3679 err_free_tx_complete: 3680 destroy_workqueue(ar->workqueue_tx_complete); 3681 err_free_aux_wq: 3682 destroy_workqueue(ar->workqueue_aux); 3683 err_free_wq: 3684 destroy_workqueue(ar->workqueue); 3685 err_free_mac: 3686 ath10k_mac_destroy(ar); 3687 3688 return NULL; 3689 } 3690 EXPORT_SYMBOL(ath10k_core_create); 3691 3692 void ath10k_core_destroy(struct ath10k *ar) 3693 { 3694 destroy_workqueue(ar->workqueue); 3695 3696 destroy_workqueue(ar->workqueue_aux); 3697 3698 destroy_workqueue(ar->workqueue_tx_complete); 3699 3700 free_netdev(ar->napi_dev); 3701 ath10k_debug_destroy(ar); 3702 ath10k_coredump_destroy(ar); 3703 ath10k_htt_tx_destroy(&ar->htt); 3704 ath10k_wmi_free_host_mem(ar); 3705 ath10k_mac_destroy(ar); 3706 } 3707 EXPORT_SYMBOL(ath10k_core_destroy); 3708 3709 MODULE_AUTHOR("Qualcomm Atheros"); 3710 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3711 MODULE_LICENSE("Dual BSD/GPL"); 3712