1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/firmware.h> 10 #include <linux/of.h> 11 #include <linux/property.h> 12 #include <linux/dmi.h> 13 #include <linux/ctype.h> 14 #include <linux/pm_qos.h> 15 #include <linux/nvmem-consumer.h> 16 #include <asm/byteorder.h> 17 18 #include "core.h" 19 #include "mac.h" 20 #include "htc.h" 21 #include "hif.h" 22 #include "wmi.h" 23 #include "bmi.h" 24 #include "debug.h" 25 #include "htt.h" 26 #include "testmode.h" 27 #include "wmi-ops.h" 28 #include "coredump.h" 29 30 unsigned int ath10k_debug_mask; 31 EXPORT_SYMBOL(ath10k_debug_mask); 32 33 static unsigned int ath10k_cryptmode_param; 34 static bool uart_print; 35 static bool skip_otp; 36 static bool rawmode; 37 static bool fw_diag_log; 38 39 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 40 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 41 42 /* FIXME: most of these should be readonly */ 43 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 44 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 45 module_param(uart_print, bool, 0644); 46 module_param(skip_otp, bool, 0644); 47 module_param(rawmode, bool, 0644); 48 module_param(fw_diag_log, bool, 0644); 49 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 50 51 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 52 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 53 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 54 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 55 MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath"); 56 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 57 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 58 59 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 60 { 61 .id = QCA988X_HW_2_0_VERSION, 62 .dev_id = QCA988X_2_0_DEVICE_ID, 63 .bus = ATH10K_BUS_PCI, 64 .name = "qca988x hw2.0", 65 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 66 .uart_pin = 7, 67 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 68 .otp_exe_param = 0, 69 .channel_counters_freq_hz = 88000, 70 .max_probe_resp_desc_thres = 0, 71 .cal_data_len = 2116, 72 .fw = { 73 .dir = QCA988X_HW_2_0_FW_DIR, 74 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 75 .board_size = QCA988X_BOARD_DATA_SZ, 76 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 77 }, 78 .hw_ops = &qca988x_ops, 79 .decap_align_bytes = 4, 80 .spectral_bin_discard = 0, 81 .spectral_bin_offset = 0, 82 .vht160_mcs_rx_highest = 0, 83 .vht160_mcs_tx_highest = 0, 84 .n_cipher_suites = 8, 85 .ast_skid_limit = 0x10, 86 .num_wds_entries = 0x20, 87 .target_64bit = false, 88 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 89 .shadow_reg_support = false, 90 .rri_on_ddr = false, 91 .hw_filter_reset_required = true, 92 .fw_diag_ce_download = false, 93 .tx_stats_over_pktlog = true, 94 .dynamic_sar_support = false, 95 }, 96 { 97 .id = QCA988X_HW_2_0_VERSION, 98 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 99 .name = "qca988x hw2.0 ubiquiti", 100 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 101 .uart_pin = 7, 102 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 103 .otp_exe_param = 0, 104 .channel_counters_freq_hz = 88000, 105 .max_probe_resp_desc_thres = 0, 106 .cal_data_len = 2116, 107 .fw = { 108 .dir = QCA988X_HW_2_0_FW_DIR, 109 .board = QCA988X_HW_2_0_BOARD_DATA_FILE, 110 .board_size = QCA988X_BOARD_DATA_SZ, 111 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 112 }, 113 .hw_ops = &qca988x_ops, 114 .decap_align_bytes = 4, 115 .spectral_bin_discard = 0, 116 .spectral_bin_offset = 0, 117 .vht160_mcs_rx_highest = 0, 118 .vht160_mcs_tx_highest = 0, 119 .n_cipher_suites = 8, 120 .ast_skid_limit = 0x10, 121 .num_wds_entries = 0x20, 122 .target_64bit = false, 123 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 124 .shadow_reg_support = false, 125 .rri_on_ddr = false, 126 .hw_filter_reset_required = true, 127 .fw_diag_ce_download = false, 128 .tx_stats_over_pktlog = true, 129 .dynamic_sar_support = false, 130 }, 131 { 132 .id = QCA9887_HW_1_0_VERSION, 133 .dev_id = QCA9887_1_0_DEVICE_ID, 134 .bus = ATH10K_BUS_PCI, 135 .name = "qca9887 hw1.0", 136 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 137 .uart_pin = 7, 138 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 139 .otp_exe_param = 0, 140 .channel_counters_freq_hz = 88000, 141 .max_probe_resp_desc_thres = 0, 142 .cal_data_len = 2116, 143 .fw = { 144 .dir = QCA9887_HW_1_0_FW_DIR, 145 .board = QCA9887_HW_1_0_BOARD_DATA_FILE, 146 .board_size = QCA9887_BOARD_DATA_SZ, 147 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 148 }, 149 .hw_ops = &qca988x_ops, 150 .decap_align_bytes = 4, 151 .spectral_bin_discard = 0, 152 .spectral_bin_offset = 0, 153 .vht160_mcs_rx_highest = 0, 154 .vht160_mcs_tx_highest = 0, 155 .n_cipher_suites = 8, 156 .ast_skid_limit = 0x10, 157 .num_wds_entries = 0x20, 158 .target_64bit = false, 159 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 160 .shadow_reg_support = false, 161 .rri_on_ddr = false, 162 .hw_filter_reset_required = true, 163 .fw_diag_ce_download = false, 164 .tx_stats_over_pktlog = false, 165 .dynamic_sar_support = false, 166 }, 167 { 168 .id = QCA6174_HW_3_2_VERSION, 169 .dev_id = QCA6174_3_2_DEVICE_ID, 170 .bus = ATH10K_BUS_SDIO, 171 .name = "qca6174 hw3.2 sdio", 172 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 173 .uart_pin = 19, 174 .otp_exe_param = 0, 175 .channel_counters_freq_hz = 88000, 176 .max_probe_resp_desc_thres = 0, 177 .cal_data_len = 0, 178 .fw = { 179 .dir = QCA6174_HW_3_0_FW_DIR, 180 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 181 .board_size = QCA6174_BOARD_DATA_SZ, 182 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 183 }, 184 .hw_ops = &qca6174_sdio_ops, 185 .hw_clk = qca6174_clk, 186 .target_cpu_freq = 176000000, 187 .decap_align_bytes = 4, 188 .n_cipher_suites = 8, 189 .num_peers = 10, 190 .ast_skid_limit = 0x10, 191 .num_wds_entries = 0x20, 192 .uart_pin_workaround = true, 193 .tx_stats_over_pktlog = false, 194 .bmi_large_size_download = true, 195 .supports_peer_stats_info = true, 196 .dynamic_sar_support = true, 197 }, 198 { 199 .id = QCA6174_HW_2_1_VERSION, 200 .dev_id = QCA6164_2_1_DEVICE_ID, 201 .bus = ATH10K_BUS_PCI, 202 .name = "qca6164 hw2.1", 203 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 204 .uart_pin = 6, 205 .otp_exe_param = 0, 206 .channel_counters_freq_hz = 88000, 207 .max_probe_resp_desc_thres = 0, 208 .cal_data_len = 8124, 209 .fw = { 210 .dir = QCA6174_HW_2_1_FW_DIR, 211 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 212 .board_size = QCA6174_BOARD_DATA_SZ, 213 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 214 }, 215 .hw_ops = &qca988x_ops, 216 .decap_align_bytes = 4, 217 .spectral_bin_discard = 0, 218 .spectral_bin_offset = 0, 219 .vht160_mcs_rx_highest = 0, 220 .vht160_mcs_tx_highest = 0, 221 .n_cipher_suites = 8, 222 .ast_skid_limit = 0x10, 223 .num_wds_entries = 0x20, 224 .target_64bit = false, 225 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 226 .shadow_reg_support = false, 227 .rri_on_ddr = false, 228 .hw_filter_reset_required = true, 229 .fw_diag_ce_download = false, 230 .tx_stats_over_pktlog = false, 231 .dynamic_sar_support = false, 232 }, 233 { 234 .id = QCA6174_HW_2_1_VERSION, 235 .dev_id = QCA6174_2_1_DEVICE_ID, 236 .bus = ATH10K_BUS_PCI, 237 .name = "qca6174 hw2.1", 238 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 239 .uart_pin = 6, 240 .otp_exe_param = 0, 241 .channel_counters_freq_hz = 88000, 242 .max_probe_resp_desc_thres = 0, 243 .cal_data_len = 8124, 244 .fw = { 245 .dir = QCA6174_HW_2_1_FW_DIR, 246 .board = QCA6174_HW_2_1_BOARD_DATA_FILE, 247 .board_size = QCA6174_BOARD_DATA_SZ, 248 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 249 }, 250 .hw_ops = &qca988x_ops, 251 .decap_align_bytes = 4, 252 .spectral_bin_discard = 0, 253 .spectral_bin_offset = 0, 254 .vht160_mcs_rx_highest = 0, 255 .vht160_mcs_tx_highest = 0, 256 .n_cipher_suites = 8, 257 .ast_skid_limit = 0x10, 258 .num_wds_entries = 0x20, 259 .target_64bit = false, 260 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 261 .shadow_reg_support = false, 262 .rri_on_ddr = false, 263 .hw_filter_reset_required = true, 264 .fw_diag_ce_download = false, 265 .tx_stats_over_pktlog = false, 266 .dynamic_sar_support = false, 267 }, 268 { 269 .id = QCA6174_HW_3_0_VERSION, 270 .dev_id = QCA6174_2_1_DEVICE_ID, 271 .bus = ATH10K_BUS_PCI, 272 .name = "qca6174 hw3.0", 273 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 274 .uart_pin = 6, 275 .otp_exe_param = 0, 276 .channel_counters_freq_hz = 88000, 277 .max_probe_resp_desc_thres = 0, 278 .cal_data_len = 8124, 279 .fw = { 280 .dir = QCA6174_HW_3_0_FW_DIR, 281 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 282 .board_size = QCA6174_BOARD_DATA_SZ, 283 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 284 }, 285 .hw_ops = &qca988x_ops, 286 .decap_align_bytes = 4, 287 .spectral_bin_discard = 0, 288 .spectral_bin_offset = 0, 289 .vht160_mcs_rx_highest = 0, 290 .vht160_mcs_tx_highest = 0, 291 .n_cipher_suites = 8, 292 .ast_skid_limit = 0x10, 293 .num_wds_entries = 0x20, 294 .target_64bit = false, 295 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 296 .shadow_reg_support = false, 297 .rri_on_ddr = false, 298 .hw_filter_reset_required = true, 299 .fw_diag_ce_download = false, 300 .tx_stats_over_pktlog = false, 301 .dynamic_sar_support = false, 302 }, 303 { 304 .id = QCA6174_HW_3_2_VERSION, 305 .dev_id = QCA6174_2_1_DEVICE_ID, 306 .bus = ATH10K_BUS_PCI, 307 .name = "qca6174 hw3.2", 308 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 309 .uart_pin = 6, 310 .otp_exe_param = 0, 311 .channel_counters_freq_hz = 88000, 312 .max_probe_resp_desc_thres = 0, 313 .cal_data_len = 8124, 314 .fw = { 315 /* uses same binaries as hw3.0 */ 316 .dir = QCA6174_HW_3_0_FW_DIR, 317 .board = QCA6174_HW_3_0_BOARD_DATA_FILE, 318 .board_size = QCA6174_BOARD_DATA_SZ, 319 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 320 }, 321 .hw_ops = &qca6174_ops, 322 .hw_clk = qca6174_clk, 323 .target_cpu_freq = 176000000, 324 .decap_align_bytes = 4, 325 .spectral_bin_discard = 0, 326 .spectral_bin_offset = 0, 327 .vht160_mcs_rx_highest = 0, 328 .vht160_mcs_tx_highest = 0, 329 .n_cipher_suites = 8, 330 .ast_skid_limit = 0x10, 331 .num_wds_entries = 0x20, 332 .target_64bit = false, 333 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 334 .shadow_reg_support = false, 335 .rri_on_ddr = false, 336 .hw_filter_reset_required = true, 337 .fw_diag_ce_download = true, 338 .tx_stats_over_pktlog = false, 339 .supports_peer_stats_info = true, 340 .dynamic_sar_support = true, 341 }, 342 { 343 .id = QCA99X0_HW_2_0_DEV_VERSION, 344 .dev_id = QCA99X0_2_0_DEVICE_ID, 345 .bus = ATH10K_BUS_PCI, 346 .name = "qca99x0 hw2.0", 347 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 348 .uart_pin = 7, 349 .otp_exe_param = 0x00000700, 350 .continuous_frag_desc = true, 351 .cck_rate_map_rev2 = true, 352 .channel_counters_freq_hz = 150000, 353 .max_probe_resp_desc_thres = 24, 354 .tx_chain_mask = 0xf, 355 .rx_chain_mask = 0xf, 356 .max_spatial_stream = 4, 357 .cal_data_len = 12064, 358 .fw = { 359 .dir = QCA99X0_HW_2_0_FW_DIR, 360 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, 361 .board_size = QCA99X0_BOARD_DATA_SZ, 362 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 363 }, 364 .sw_decrypt_mcast_mgmt = true, 365 .hw_ops = &qca99x0_ops, 366 .decap_align_bytes = 1, 367 .spectral_bin_discard = 4, 368 .spectral_bin_offset = 0, 369 .vht160_mcs_rx_highest = 0, 370 .vht160_mcs_tx_highest = 0, 371 .n_cipher_suites = 11, 372 .ast_skid_limit = 0x10, 373 .num_wds_entries = 0x20, 374 .target_64bit = false, 375 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 376 .shadow_reg_support = false, 377 .rri_on_ddr = false, 378 .hw_filter_reset_required = true, 379 .fw_diag_ce_download = false, 380 .tx_stats_over_pktlog = false, 381 .dynamic_sar_support = false, 382 }, 383 { 384 .id = QCA9984_HW_1_0_DEV_VERSION, 385 .dev_id = QCA9984_1_0_DEVICE_ID, 386 .bus = ATH10K_BUS_PCI, 387 .name = "qca9984/qca9994 hw1.0", 388 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 389 .uart_pin = 7, 390 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 391 .otp_exe_param = 0x00000700, 392 .continuous_frag_desc = true, 393 .cck_rate_map_rev2 = true, 394 .channel_counters_freq_hz = 150000, 395 .max_probe_resp_desc_thres = 24, 396 .tx_chain_mask = 0xf, 397 .rx_chain_mask = 0xf, 398 .max_spatial_stream = 4, 399 .cal_data_len = 12064, 400 .fw = { 401 .dir = QCA9984_HW_1_0_FW_DIR, 402 .board = QCA9984_HW_1_0_BOARD_DATA_FILE, 403 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE, 404 .board_size = QCA99X0_BOARD_DATA_SZ, 405 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 406 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 407 }, 408 .sw_decrypt_mcast_mgmt = true, 409 .hw_ops = &qca99x0_ops, 410 .decap_align_bytes = 1, 411 .spectral_bin_discard = 12, 412 .spectral_bin_offset = 8, 413 414 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 415 * or 2x2 160Mhz, long-guard-interval. 416 */ 417 .vht160_mcs_rx_highest = 1560, 418 .vht160_mcs_tx_highest = 1560, 419 .n_cipher_suites = 11, 420 .ast_skid_limit = 0x10, 421 .num_wds_entries = 0x20, 422 .target_64bit = false, 423 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 424 .shadow_reg_support = false, 425 .rri_on_ddr = false, 426 .hw_filter_reset_required = true, 427 .fw_diag_ce_download = false, 428 .tx_stats_over_pktlog = false, 429 .dynamic_sar_support = false, 430 }, 431 { 432 .id = QCA9888_HW_2_0_DEV_VERSION, 433 .dev_id = QCA9888_2_0_DEVICE_ID, 434 .bus = ATH10K_BUS_PCI, 435 .name = "qca9888 hw2.0", 436 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 437 .uart_pin = 7, 438 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 439 .otp_exe_param = 0x00000700, 440 .continuous_frag_desc = true, 441 .channel_counters_freq_hz = 150000, 442 .max_probe_resp_desc_thres = 24, 443 .tx_chain_mask = 3, 444 .rx_chain_mask = 3, 445 .max_spatial_stream = 2, 446 .cal_data_len = 12064, 447 .fw = { 448 .dir = QCA9888_HW_2_0_FW_DIR, 449 .board = QCA9888_HW_2_0_BOARD_DATA_FILE, 450 .board_size = QCA99X0_BOARD_DATA_SZ, 451 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 452 }, 453 .sw_decrypt_mcast_mgmt = true, 454 .hw_ops = &qca99x0_ops, 455 .decap_align_bytes = 1, 456 .spectral_bin_discard = 12, 457 .spectral_bin_offset = 8, 458 459 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 460 * 1x1 160Mhz, long-guard-interval. 461 */ 462 .vht160_mcs_rx_highest = 780, 463 .vht160_mcs_tx_highest = 780, 464 .n_cipher_suites = 11, 465 .ast_skid_limit = 0x10, 466 .num_wds_entries = 0x20, 467 .target_64bit = false, 468 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 469 .shadow_reg_support = false, 470 .rri_on_ddr = false, 471 .hw_filter_reset_required = true, 472 .fw_diag_ce_download = false, 473 .tx_stats_over_pktlog = false, 474 .dynamic_sar_support = false, 475 }, 476 { 477 .id = QCA9377_HW_1_0_DEV_VERSION, 478 .dev_id = QCA9377_1_0_DEVICE_ID, 479 .bus = ATH10K_BUS_PCI, 480 .name = "qca9377 hw1.0", 481 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 482 .uart_pin = 6, 483 .otp_exe_param = 0, 484 .channel_counters_freq_hz = 88000, 485 .max_probe_resp_desc_thres = 0, 486 .cal_data_len = 8124, 487 .fw = { 488 .dir = QCA9377_HW_1_0_FW_DIR, 489 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 490 .board_size = QCA9377_BOARD_DATA_SZ, 491 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 492 }, 493 .hw_ops = &qca988x_ops, 494 .decap_align_bytes = 4, 495 .spectral_bin_discard = 0, 496 .spectral_bin_offset = 0, 497 .vht160_mcs_rx_highest = 0, 498 .vht160_mcs_tx_highest = 0, 499 .n_cipher_suites = 8, 500 .ast_skid_limit = 0x10, 501 .num_wds_entries = 0x20, 502 .target_64bit = false, 503 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 504 .shadow_reg_support = false, 505 .rri_on_ddr = false, 506 .hw_filter_reset_required = true, 507 .fw_diag_ce_download = false, 508 .tx_stats_over_pktlog = false, 509 .dynamic_sar_support = false, 510 }, 511 { 512 .id = QCA9377_HW_1_1_DEV_VERSION, 513 .dev_id = QCA9377_1_0_DEVICE_ID, 514 .bus = ATH10K_BUS_PCI, 515 .name = "qca9377 hw1.1", 516 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 517 .uart_pin = 6, 518 .otp_exe_param = 0, 519 .channel_counters_freq_hz = 88000, 520 .max_probe_resp_desc_thres = 0, 521 .cal_data_len = 8124, 522 .fw = { 523 .dir = QCA9377_HW_1_0_FW_DIR, 524 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 525 .board_size = QCA9377_BOARD_DATA_SZ, 526 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 527 }, 528 .hw_ops = &qca6174_ops, 529 .hw_clk = qca6174_clk, 530 .target_cpu_freq = 176000000, 531 .decap_align_bytes = 4, 532 .spectral_bin_discard = 0, 533 .spectral_bin_offset = 0, 534 .vht160_mcs_rx_highest = 0, 535 .vht160_mcs_tx_highest = 0, 536 .n_cipher_suites = 8, 537 .ast_skid_limit = 0x10, 538 .num_wds_entries = 0x20, 539 .target_64bit = false, 540 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 541 .shadow_reg_support = false, 542 .rri_on_ddr = false, 543 .hw_filter_reset_required = true, 544 .fw_diag_ce_download = true, 545 .tx_stats_over_pktlog = false, 546 .dynamic_sar_support = false, 547 }, 548 { 549 .id = QCA9377_HW_1_1_DEV_VERSION, 550 .dev_id = QCA9377_1_0_DEVICE_ID, 551 .bus = ATH10K_BUS_SDIO, 552 .name = "qca9377 hw1.1 sdio", 553 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 554 .uart_pin = 19, 555 .otp_exe_param = 0, 556 .channel_counters_freq_hz = 88000, 557 .max_probe_resp_desc_thres = 0, 558 .cal_data_len = 8124, 559 .fw = { 560 .dir = QCA9377_HW_1_0_FW_DIR, 561 .board = QCA9377_HW_1_0_BOARD_DATA_FILE, 562 .board_size = QCA9377_BOARD_DATA_SZ, 563 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 564 }, 565 .hw_ops = &qca6174_ops, 566 .hw_clk = qca6174_clk, 567 .target_cpu_freq = 176000000, 568 .decap_align_bytes = 4, 569 .n_cipher_suites = 8, 570 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 571 .ast_skid_limit = 0x10, 572 .num_wds_entries = 0x20, 573 .uart_pin_workaround = true, 574 .dynamic_sar_support = false, 575 }, 576 { 577 .id = QCA4019_HW_1_0_DEV_VERSION, 578 .dev_id = 0, 579 .bus = ATH10K_BUS_AHB, 580 .name = "qca4019 hw1.0", 581 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 582 .uart_pin = 7, 583 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 584 .otp_exe_param = 0x0010000, 585 .continuous_frag_desc = true, 586 .cck_rate_map_rev2 = true, 587 .channel_counters_freq_hz = 125000, 588 .max_probe_resp_desc_thres = 24, 589 .tx_chain_mask = 0x3, 590 .rx_chain_mask = 0x3, 591 .max_spatial_stream = 2, 592 .cal_data_len = 12064, 593 .fw = { 594 .dir = QCA4019_HW_1_0_FW_DIR, 595 .board = QCA4019_HW_1_0_BOARD_DATA_FILE, 596 .board_size = QCA4019_BOARD_DATA_SZ, 597 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 598 }, 599 .sw_decrypt_mcast_mgmt = true, 600 .hw_ops = &qca99x0_ops, 601 .decap_align_bytes = 1, 602 .spectral_bin_discard = 4, 603 .spectral_bin_offset = 0, 604 .vht160_mcs_rx_highest = 0, 605 .vht160_mcs_tx_highest = 0, 606 .n_cipher_suites = 11, 607 .ast_skid_limit = 0x10, 608 .num_wds_entries = 0x20, 609 .target_64bit = false, 610 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 611 .shadow_reg_support = false, 612 .rri_on_ddr = false, 613 .hw_filter_reset_required = true, 614 .fw_diag_ce_download = false, 615 .tx_stats_over_pktlog = false, 616 .dynamic_sar_support = false, 617 }, 618 { 619 .id = WCN3990_HW_1_0_DEV_VERSION, 620 .dev_id = 0, 621 .bus = ATH10K_BUS_SNOC, 622 .name = "wcn3990 hw1.0", 623 .continuous_frag_desc = true, 624 .tx_chain_mask = 0x7, 625 .rx_chain_mask = 0x7, 626 .max_spatial_stream = 4, 627 .fw = { 628 .dir = WCN3990_HW_1_0_FW_DIR, 629 }, 630 .sw_decrypt_mcast_mgmt = true, 631 .hw_ops = &wcn3990_ops, 632 .decap_align_bytes = 1, 633 .num_peers = TARGET_HL_TLV_NUM_PEERS, 634 .n_cipher_suites = 11, 635 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 636 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 637 .target_64bit = true, 638 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 639 .shadow_reg_support = true, 640 .rri_on_ddr = true, 641 .hw_filter_reset_required = false, 642 .fw_diag_ce_download = false, 643 .tx_stats_over_pktlog = false, 644 .dynamic_sar_support = true, 645 }, 646 }; 647 648 static const char *const ath10k_core_fw_feature_str[] = { 649 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 650 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 651 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 652 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 653 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 654 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 655 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 656 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 657 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 658 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 659 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 660 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 661 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 662 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 663 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 664 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 665 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 666 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 667 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 668 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 669 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 670 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 671 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 672 }; 673 674 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 675 size_t buf_len, 676 enum ath10k_fw_features feat) 677 { 678 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 679 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 680 ATH10K_FW_FEATURE_COUNT); 681 682 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 683 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 684 return scnprintf(buf, buf_len, "bit%d", feat); 685 } 686 687 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 688 } 689 690 void ath10k_core_get_fw_features_str(struct ath10k *ar, 691 char *buf, 692 size_t buf_len) 693 { 694 size_t len = 0; 695 int i; 696 697 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 698 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 699 if (len > 0) 700 len += scnprintf(buf + len, buf_len - len, ","); 701 702 len += ath10k_core_get_fw_feature_str(buf + len, 703 buf_len - len, 704 i); 705 } 706 } 707 } 708 709 static void ath10k_send_suspend_complete(struct ath10k *ar) 710 { 711 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 712 713 complete(&ar->target_suspend); 714 } 715 716 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 717 { 718 int ret; 719 u32 param = 0; 720 721 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 722 if (ret) 723 return ret; 724 725 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 726 if (ret) 727 return ret; 728 729 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 730 if (ret) 731 return ret; 732 733 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 734 735 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) 736 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 737 else 738 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 739 740 if (mode == ATH10K_FIRMWARE_MODE_UTF) 741 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 742 else 743 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 744 745 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 746 if (ret) 747 return ret; 748 749 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 750 if (ret) 751 return ret; 752 753 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 754 755 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 756 if (ret) 757 return ret; 758 759 return 0; 760 } 761 762 static int ath10k_init_configure_target(struct ath10k *ar) 763 { 764 u32 param_host; 765 int ret; 766 767 /* tell target which HTC version it is used*/ 768 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 769 HTC_PROTOCOL_VERSION); 770 if (ret) { 771 ath10k_err(ar, "settings HTC version failed\n"); 772 return ret; 773 } 774 775 /* set the firmware mode to STA/IBSS/AP */ 776 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 777 if (ret) { 778 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 779 return ret; 780 } 781 782 /* TODO following parameters need to be re-visited. */ 783 /* num_device */ 784 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 785 /* Firmware mode */ 786 /* FIXME: Why FW_MODE_AP ??.*/ 787 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 788 /* mac_addr_method */ 789 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 790 /* firmware_bridge */ 791 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 792 /* fwsubmode */ 793 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 794 795 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 796 if (ret) { 797 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 798 return ret; 799 } 800 801 /* We do all byte-swapping on the host */ 802 ret = ath10k_bmi_write32(ar, hi_be, 0); 803 if (ret) { 804 ath10k_err(ar, "setting host CPU BE mode failed\n"); 805 return ret; 806 } 807 808 /* FW descriptor/Data swap flags */ 809 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 810 811 if (ret) { 812 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 813 return ret; 814 } 815 816 /* Some devices have a special sanity check that verifies the PCI 817 * Device ID is written to this host interest var. It is known to be 818 * required to boot QCA6164. 819 */ 820 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 821 ar->dev_id); 822 if (ret) { 823 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 824 return ret; 825 } 826 827 return 0; 828 } 829 830 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 831 const char *dir, 832 const char *file) 833 { 834 char filename[100]; 835 const struct firmware *fw; 836 int ret; 837 838 if (file == NULL) 839 return ERR_PTR(-ENOENT); 840 841 if (dir == NULL) 842 dir = "."; 843 844 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 845 ret = firmware_request_nowarn(&fw, filename, ar->dev); 846 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 847 filename, ret); 848 849 if (ret) 850 return ERR_PTR(ret); 851 852 return fw; 853 } 854 855 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 856 size_t data_len) 857 { 858 u32 board_data_size = ar->hw_params.fw.board_size; 859 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 860 u32 board_ext_data_addr; 861 int ret; 862 863 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 864 if (ret) { 865 ath10k_err(ar, "could not read board ext data addr (%d)\n", 866 ret); 867 return ret; 868 } 869 870 ath10k_dbg(ar, ATH10K_DBG_BOOT, 871 "boot push board extended data addr 0x%x\n", 872 board_ext_data_addr); 873 874 if (board_ext_data_addr == 0) 875 return 0; 876 877 if (data_len != (board_data_size + board_ext_data_size)) { 878 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 879 data_len, board_data_size, board_ext_data_size); 880 return -EINVAL; 881 } 882 883 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 884 data + board_data_size, 885 board_ext_data_size); 886 if (ret) { 887 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 888 return ret; 889 } 890 891 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 892 (board_ext_data_size << 16) | 1); 893 if (ret) { 894 ath10k_err(ar, "could not write board ext data bit (%d)\n", 895 ret); 896 return ret; 897 } 898 899 return 0; 900 } 901 902 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 903 { 904 u32 result, address; 905 u8 board_id, chip_id; 906 bool ext_bid_support; 907 int ret, bmi_board_id_param; 908 909 address = ar->hw_params.patch_load_addr; 910 911 if (!ar->normal_mode_fw.fw_file.otp_data || 912 !ar->normal_mode_fw.fw_file.otp_len) { 913 ath10k_warn(ar, 914 "failed to retrieve board id because of invalid otp\n"); 915 return -ENODATA; 916 } 917 918 if (ar->id.bmi_ids_valid) { 919 ath10k_dbg(ar, ATH10K_DBG_BOOT, 920 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 921 ar->id.bmi_board_id, ar->id.bmi_chip_id); 922 goto skip_otp_download; 923 } 924 925 ath10k_dbg(ar, ATH10K_DBG_BOOT, 926 "boot upload otp to 0x%x len %zd for board id\n", 927 address, ar->normal_mode_fw.fw_file.otp_len); 928 929 ret = ath10k_bmi_fast_download(ar, address, 930 ar->normal_mode_fw.fw_file.otp_data, 931 ar->normal_mode_fw.fw_file.otp_len); 932 if (ret) { 933 ath10k_err(ar, "could not write otp for board id check: %d\n", 934 ret); 935 return ret; 936 } 937 938 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 939 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 940 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 941 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 942 else 943 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 944 945 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 946 if (ret) { 947 ath10k_err(ar, "could not execute otp for board id check: %d\n", 948 ret); 949 return ret; 950 } 951 952 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 953 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 954 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 955 956 ath10k_dbg(ar, ATH10K_DBG_BOOT, 957 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 958 result, board_id, chip_id, ext_bid_support); 959 960 ar->id.ext_bid_supported = ext_bid_support; 961 962 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 963 (board_id == 0)) { 964 ath10k_dbg(ar, ATH10K_DBG_BOOT, 965 "board id does not exist in otp, ignore it\n"); 966 return -EOPNOTSUPP; 967 } 968 969 ar->id.bmi_ids_valid = true; 970 ar->id.bmi_board_id = board_id; 971 ar->id.bmi_chip_id = chip_id; 972 973 skip_otp_download: 974 975 return 0; 976 } 977 978 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 979 { 980 struct ath10k *ar = data; 981 const char *bdf_ext; 982 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 983 u8 bdf_enabled; 984 int i; 985 986 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 987 return; 988 989 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 990 ath10k_dbg(ar, ATH10K_DBG_BOOT, 991 "wrong smbios bdf ext type length (%d).\n", 992 hdr->length); 993 return; 994 } 995 996 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 997 if (!bdf_enabled) { 998 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 999 return; 1000 } 1001 1002 /* Only one string exists (per spec) */ 1003 bdf_ext = (char *)hdr + hdr->length; 1004 1005 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1006 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1007 "bdf variant magic does not match.\n"); 1008 return; 1009 } 1010 1011 for (i = 0; i < strlen(bdf_ext); i++) { 1012 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1013 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1014 "bdf variant name contains non ascii chars.\n"); 1015 return; 1016 } 1017 } 1018 1019 /* Copy extension name without magic suffix */ 1020 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1021 sizeof(ar->id.bdf_ext)) < 0) { 1022 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1023 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1024 bdf_ext); 1025 return; 1026 } 1027 1028 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1029 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1030 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1031 } 1032 1033 static int ath10k_core_check_smbios(struct ath10k *ar) 1034 { 1035 ar->id.bdf_ext[0] = '\0'; 1036 dmi_walk(ath10k_core_check_bdfext, ar); 1037 1038 if (ar->id.bdf_ext[0] == '\0') 1039 return -ENODATA; 1040 1041 return 0; 1042 } 1043 1044 int ath10k_core_check_dt(struct ath10k *ar) 1045 { 1046 struct device_node *node; 1047 const char *variant = NULL; 1048 1049 node = ar->dev->of_node; 1050 if (!node) 1051 return -ENOENT; 1052 1053 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1054 &variant); 1055 if (!variant) 1056 return -ENODATA; 1057 1058 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1059 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1060 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1061 variant); 1062 1063 return 0; 1064 } 1065 EXPORT_SYMBOL(ath10k_core_check_dt); 1066 1067 static int ath10k_download_fw(struct ath10k *ar) 1068 { 1069 u32 address, data_len; 1070 const void *data; 1071 int ret; 1072 struct pm_qos_request latency_qos; 1073 1074 address = ar->hw_params.patch_load_addr; 1075 1076 data = ar->running_fw->fw_file.firmware_data; 1077 data_len = ar->running_fw->fw_file.firmware_len; 1078 1079 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1080 if (ret) { 1081 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1082 ret); 1083 return ret; 1084 } 1085 1086 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1087 "boot uploading firmware image %pK len %d\n", 1088 data, data_len); 1089 1090 /* Check if device supports to download firmware via 1091 * diag copy engine. Downloading firmware via diag CE 1092 * greatly reduces the time to download firmware. 1093 */ 1094 if (ar->hw_params.fw_diag_ce_download) { 1095 ret = ath10k_hw_diag_fast_download(ar, address, 1096 data, data_len); 1097 if (ret == 0) 1098 /* firmware upload via diag ce was successful */ 1099 return 0; 1100 1101 ath10k_warn(ar, 1102 "failed to upload firmware via diag ce, trying BMI: %d", 1103 ret); 1104 } 1105 1106 memset(&latency_qos, 0, sizeof(latency_qos)); 1107 cpu_latency_qos_add_request(&latency_qos, 0); 1108 1109 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1110 1111 cpu_latency_qos_remove_request(&latency_qos); 1112 1113 return ret; 1114 } 1115 1116 void ath10k_core_free_board_files(struct ath10k *ar) 1117 { 1118 if (!IS_ERR(ar->normal_mode_fw.board)) 1119 release_firmware(ar->normal_mode_fw.board); 1120 1121 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1122 release_firmware(ar->normal_mode_fw.ext_board); 1123 1124 ar->normal_mode_fw.board = NULL; 1125 ar->normal_mode_fw.board_data = NULL; 1126 ar->normal_mode_fw.board_len = 0; 1127 ar->normal_mode_fw.ext_board = NULL; 1128 ar->normal_mode_fw.ext_board_data = NULL; 1129 ar->normal_mode_fw.ext_board_len = 0; 1130 } 1131 EXPORT_SYMBOL(ath10k_core_free_board_files); 1132 1133 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1134 { 1135 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1136 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1137 1138 if (!IS_ERR(ar->cal_file)) 1139 release_firmware(ar->cal_file); 1140 1141 if (!IS_ERR(ar->pre_cal_file)) 1142 release_firmware(ar->pre_cal_file); 1143 1144 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1145 1146 ar->normal_mode_fw.fw_file.otp_data = NULL; 1147 ar->normal_mode_fw.fw_file.otp_len = 0; 1148 1149 ar->normal_mode_fw.fw_file.firmware = NULL; 1150 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1151 ar->normal_mode_fw.fw_file.firmware_len = 0; 1152 1153 ar->cal_file = NULL; 1154 ar->pre_cal_file = NULL; 1155 } 1156 1157 static int ath10k_fetch_cal_file(struct ath10k *ar) 1158 { 1159 char filename[100]; 1160 1161 /* pre-cal-<bus>-<id>.bin */ 1162 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1163 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1164 1165 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1166 if (!IS_ERR(ar->pre_cal_file)) 1167 goto success; 1168 1169 /* cal-<bus>-<id>.bin */ 1170 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1171 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1172 1173 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1174 if (IS_ERR(ar->cal_file)) 1175 /* calibration file is optional, don't print any warnings */ 1176 return PTR_ERR(ar->cal_file); 1177 success: 1178 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1179 ATH10K_FW_DIR, filename); 1180 1181 return 0; 1182 } 1183 1184 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1185 { 1186 const struct firmware *fw; 1187 1188 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1189 if (!ar->hw_params.fw.board) { 1190 ath10k_err(ar, "failed to find board file fw entry\n"); 1191 return -EINVAL; 1192 } 1193 1194 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1195 ar->hw_params.fw.dir, 1196 ar->hw_params.fw.board); 1197 if (IS_ERR(ar->normal_mode_fw.board)) 1198 return PTR_ERR(ar->normal_mode_fw.board); 1199 1200 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1201 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1202 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1203 if (!ar->hw_params.fw.eboard) { 1204 ath10k_err(ar, "failed to find eboard file fw entry\n"); 1205 return -EINVAL; 1206 } 1207 1208 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1209 ar->hw_params.fw.eboard); 1210 ar->normal_mode_fw.ext_board = fw; 1211 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1212 return PTR_ERR(ar->normal_mode_fw.ext_board); 1213 1214 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1215 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1222 const void *buf, size_t buf_len, 1223 const char *boardname, 1224 int bd_ie_type) 1225 { 1226 const struct ath10k_fw_ie *hdr; 1227 bool name_match_found; 1228 int ret, board_ie_id; 1229 size_t board_ie_len; 1230 const void *board_ie_data; 1231 1232 name_match_found = false; 1233 1234 /* go through ATH10K_BD_IE_BOARD_ elements */ 1235 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1236 hdr = buf; 1237 board_ie_id = le32_to_cpu(hdr->id); 1238 board_ie_len = le32_to_cpu(hdr->len); 1239 board_ie_data = hdr->data; 1240 1241 buf_len -= sizeof(*hdr); 1242 buf += sizeof(*hdr); 1243 1244 if (buf_len < ALIGN(board_ie_len, 4)) { 1245 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1246 buf_len, ALIGN(board_ie_len, 4)); 1247 ret = -EINVAL; 1248 goto out; 1249 } 1250 1251 switch (board_ie_id) { 1252 case ATH10K_BD_IE_BOARD_NAME: 1253 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1254 board_ie_data, board_ie_len); 1255 1256 if (board_ie_len != strlen(boardname)) 1257 break; 1258 1259 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1260 if (ret) 1261 break; 1262 1263 name_match_found = true; 1264 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1265 "boot found match for name '%s'", 1266 boardname); 1267 break; 1268 case ATH10K_BD_IE_BOARD_DATA: 1269 if (!name_match_found) 1270 /* no match found */ 1271 break; 1272 1273 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1274 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1275 "boot found board data for '%s'", 1276 boardname); 1277 1278 ar->normal_mode_fw.board_data = board_ie_data; 1279 ar->normal_mode_fw.board_len = board_ie_len; 1280 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1281 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1282 "boot found eboard data for '%s'", 1283 boardname); 1284 1285 ar->normal_mode_fw.ext_board_data = board_ie_data; 1286 ar->normal_mode_fw.ext_board_len = board_ie_len; 1287 } 1288 1289 ret = 0; 1290 goto out; 1291 default: 1292 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1293 board_ie_id); 1294 break; 1295 } 1296 1297 /* jump over the padding */ 1298 board_ie_len = ALIGN(board_ie_len, 4); 1299 1300 buf_len -= board_ie_len; 1301 buf += board_ie_len; 1302 } 1303 1304 /* no match found */ 1305 ret = -ENOENT; 1306 1307 out: 1308 return ret; 1309 } 1310 1311 static int ath10k_core_search_bd(struct ath10k *ar, 1312 const char *boardname, 1313 const u8 *data, 1314 size_t len) 1315 { 1316 size_t ie_len; 1317 struct ath10k_fw_ie *hdr; 1318 int ret = -ENOENT, ie_id; 1319 1320 while (len > sizeof(struct ath10k_fw_ie)) { 1321 hdr = (struct ath10k_fw_ie *)data; 1322 ie_id = le32_to_cpu(hdr->id); 1323 ie_len = le32_to_cpu(hdr->len); 1324 1325 len -= sizeof(*hdr); 1326 data = hdr->data; 1327 1328 if (len < ALIGN(ie_len, 4)) { 1329 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1330 ie_id, ie_len, len); 1331 return -EINVAL; 1332 } 1333 1334 switch (ie_id) { 1335 case ATH10K_BD_IE_BOARD: 1336 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1337 boardname, 1338 ATH10K_BD_IE_BOARD); 1339 if (ret == -ENOENT) 1340 /* no match found, continue */ 1341 break; 1342 1343 /* either found or error, so stop searching */ 1344 goto out; 1345 case ATH10K_BD_IE_BOARD_EXT: 1346 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1347 boardname, 1348 ATH10K_BD_IE_BOARD_EXT); 1349 if (ret == -ENOENT) 1350 /* no match found, continue */ 1351 break; 1352 1353 /* either found or error, so stop searching */ 1354 goto out; 1355 } 1356 1357 /* jump over the padding */ 1358 ie_len = ALIGN(ie_len, 4); 1359 1360 len -= ie_len; 1361 data += ie_len; 1362 } 1363 1364 out: 1365 /* return result of parse_bd_ie_board() or -ENOENT */ 1366 return ret; 1367 } 1368 1369 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1370 const char *boardname, 1371 const char *fallback_boardname1, 1372 const char *fallback_boardname2, 1373 const char *filename) 1374 { 1375 size_t len, magic_len; 1376 const u8 *data; 1377 int ret; 1378 1379 /* Skip if already fetched during board data download */ 1380 if (!ar->normal_mode_fw.board) 1381 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1382 ar->hw_params.fw.dir, 1383 filename); 1384 if (IS_ERR(ar->normal_mode_fw.board)) 1385 return PTR_ERR(ar->normal_mode_fw.board); 1386 1387 data = ar->normal_mode_fw.board->data; 1388 len = ar->normal_mode_fw.board->size; 1389 1390 /* magic has extra null byte padded */ 1391 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1392 if (len < magic_len) { 1393 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1394 ar->hw_params.fw.dir, filename, len); 1395 ret = -EINVAL; 1396 goto err; 1397 } 1398 1399 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1400 ath10k_err(ar, "found invalid board magic\n"); 1401 ret = -EINVAL; 1402 goto err; 1403 } 1404 1405 /* magic is padded to 4 bytes */ 1406 magic_len = ALIGN(magic_len, 4); 1407 if (len < magic_len) { 1408 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1409 ar->hw_params.fw.dir, filename, len); 1410 ret = -EINVAL; 1411 goto err; 1412 } 1413 1414 data += magic_len; 1415 len -= magic_len; 1416 1417 /* attempt to find boardname in the IE list */ 1418 ret = ath10k_core_search_bd(ar, boardname, data, len); 1419 1420 /* if we didn't find it and have a fallback name, try that */ 1421 if (ret == -ENOENT && fallback_boardname1) 1422 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1423 1424 if (ret == -ENOENT && fallback_boardname2) 1425 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1426 1427 if (ret == -ENOENT) { 1428 ath10k_err(ar, 1429 "failed to fetch board data for %s from %s/%s\n", 1430 boardname, ar->hw_params.fw.dir, filename); 1431 ret = -ENODATA; 1432 } 1433 1434 if (ret) 1435 goto err; 1436 1437 return 0; 1438 1439 err: 1440 ath10k_core_free_board_files(ar); 1441 return ret; 1442 } 1443 1444 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1445 size_t name_len, bool with_variant, 1446 bool with_chip_id) 1447 { 1448 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1449 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; 1450 1451 if (with_variant && ar->id.bdf_ext[0] != '\0') 1452 scnprintf(variant, sizeof(variant), ",variant=%s", 1453 ar->id.bdf_ext); 1454 1455 if (ar->id.bmi_ids_valid) { 1456 scnprintf(name, name_len, 1457 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1458 ath10k_bus_str(ar->hif.bus), 1459 ar->id.bmi_chip_id, 1460 ar->id.bmi_board_id, variant); 1461 goto out; 1462 } 1463 1464 if (ar->id.qmi_ids_valid) { 1465 if (with_chip_id) 1466 scnprintf(name, name_len, 1467 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1468 ath10k_bus_str(ar->hif.bus), 1469 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1470 variant); 1471 else 1472 scnprintf(name, name_len, 1473 "bus=%s,qmi-board-id=%x", 1474 ath10k_bus_str(ar->hif.bus), 1475 ar->id.qmi_board_id); 1476 goto out; 1477 } 1478 1479 scnprintf(name, name_len, 1480 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1481 ath10k_bus_str(ar->hif.bus), 1482 ar->id.vendor, ar->id.device, 1483 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1484 out: 1485 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1486 1487 return 0; 1488 } 1489 1490 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1491 size_t name_len) 1492 { 1493 if (ar->id.bmi_ids_valid) { 1494 scnprintf(name, name_len, 1495 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1496 ath10k_bus_str(ar->hif.bus), 1497 ar->id.bmi_chip_id, 1498 ar->id.bmi_eboard_id); 1499 1500 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1501 return 0; 1502 } 1503 /* Fallback if returned board id is zero */ 1504 return -1; 1505 } 1506 1507 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1508 { 1509 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1510 int ret; 1511 1512 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1513 /* With variant and chip id */ 1514 ret = ath10k_core_create_board_name(ar, boardname, 1515 sizeof(boardname), true, 1516 true); 1517 if (ret) { 1518 ath10k_err(ar, "failed to create board name: %d", ret); 1519 return ret; 1520 } 1521 1522 /* Without variant and only chip-id */ 1523 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1524 sizeof(boardname), false, 1525 true); 1526 if (ret) { 1527 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1528 ret); 1529 return ret; 1530 } 1531 1532 /* Without variant and without chip-id */ 1533 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1534 sizeof(boardname), false, 1535 false); 1536 if (ret) { 1537 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1538 ret); 1539 return ret; 1540 } 1541 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1542 ret = ath10k_core_create_eboard_name(ar, boardname, 1543 sizeof(boardname)); 1544 if (ret) { 1545 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1546 goto fallback; 1547 } 1548 } 1549 1550 ar->bd_api = 2; 1551 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1552 fallback_boardname1, 1553 fallback_boardname2, 1554 ATH10K_BOARD_API2_FILE); 1555 if (!ret) 1556 goto success; 1557 1558 fallback: 1559 ar->bd_api = 1; 1560 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1561 if (ret) { 1562 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1563 ar->hw_params.fw.dir); 1564 return ret; 1565 } 1566 1567 success: 1568 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1569 return 0; 1570 } 1571 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1572 1573 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1574 { 1575 u32 result, address; 1576 u8 ext_board_id; 1577 int ret; 1578 1579 address = ar->hw_params.patch_load_addr; 1580 1581 if (!ar->normal_mode_fw.fw_file.otp_data || 1582 !ar->normal_mode_fw.fw_file.otp_len) { 1583 ath10k_warn(ar, 1584 "failed to retrieve extended board id due to otp binary missing\n"); 1585 return -ENODATA; 1586 } 1587 1588 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1589 "boot upload otp to 0x%x len %zd for ext board id\n", 1590 address, ar->normal_mode_fw.fw_file.otp_len); 1591 1592 ret = ath10k_bmi_fast_download(ar, address, 1593 ar->normal_mode_fw.fw_file.otp_data, 1594 ar->normal_mode_fw.fw_file.otp_len); 1595 if (ret) { 1596 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1597 ret); 1598 return ret; 1599 } 1600 1601 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1602 if (ret) { 1603 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1604 ret); 1605 return ret; 1606 } 1607 1608 if (!result) { 1609 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1610 "ext board id does not exist in otp, ignore it\n"); 1611 return -EOPNOTSUPP; 1612 } 1613 1614 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1615 1616 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1617 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1618 result, ext_board_id); 1619 1620 ar->id.bmi_eboard_id = ext_board_id; 1621 1622 return 0; 1623 } 1624 1625 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1626 size_t data_len) 1627 { 1628 u32 board_data_size = ar->hw_params.fw.board_size; 1629 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1630 u32 board_address; 1631 u32 ext_board_address; 1632 int ret; 1633 1634 ret = ath10k_push_board_ext_data(ar, data, data_len); 1635 if (ret) { 1636 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1637 goto exit; 1638 } 1639 1640 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1641 if (ret) { 1642 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1643 goto exit; 1644 } 1645 1646 ret = ath10k_bmi_write_memory(ar, board_address, data, 1647 min_t(u32, board_data_size, 1648 data_len)); 1649 if (ret) { 1650 ath10k_err(ar, "could not write board data (%d)\n", ret); 1651 goto exit; 1652 } 1653 1654 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1655 if (ret) { 1656 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1657 goto exit; 1658 } 1659 1660 if (!ar->id.ext_bid_supported) 1661 goto exit; 1662 1663 /* Extended board data download */ 1664 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1665 if (ret == -EOPNOTSUPP) { 1666 /* Not fetching ext_board_data if ext board id is 0 */ 1667 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1668 return 0; 1669 } else if (ret) { 1670 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1671 goto exit; 1672 } 1673 1674 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1675 if (ret) 1676 goto exit; 1677 1678 if (ar->normal_mode_fw.ext_board_data) { 1679 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1680 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1681 "boot writing ext board data to addr 0x%x", 1682 ext_board_address); 1683 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1684 ar->normal_mode_fw.ext_board_data, 1685 min_t(u32, eboard_data_size, data_len)); 1686 if (ret) 1687 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1688 } 1689 1690 exit: 1691 return ret; 1692 } 1693 1694 static int ath10k_download_and_run_otp(struct ath10k *ar) 1695 { 1696 u32 result, address = ar->hw_params.patch_load_addr; 1697 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1698 int ret; 1699 1700 ret = ath10k_download_board_data(ar, 1701 ar->running_fw->board_data, 1702 ar->running_fw->board_len); 1703 if (ret) { 1704 ath10k_err(ar, "failed to download board data: %d\n", ret); 1705 return ret; 1706 } 1707 1708 /* OTP is optional */ 1709 1710 if (!ar->running_fw->fw_file.otp_data || 1711 !ar->running_fw->fw_file.otp_len) { 1712 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", 1713 ar->running_fw->fw_file.otp_data, 1714 ar->running_fw->fw_file.otp_len); 1715 return 0; 1716 } 1717 1718 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1719 address, ar->running_fw->fw_file.otp_len); 1720 1721 ret = ath10k_bmi_fast_download(ar, address, 1722 ar->running_fw->fw_file.otp_data, 1723 ar->running_fw->fw_file.otp_len); 1724 if (ret) { 1725 ath10k_err(ar, "could not write otp (%d)\n", ret); 1726 return ret; 1727 } 1728 1729 /* As of now pre-cal is valid for 10_4 variants */ 1730 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1731 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1732 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1733 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1734 1735 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1736 if (ret) { 1737 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1738 return ret; 1739 } 1740 1741 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1742 1743 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1744 ar->running_fw->fw_file.fw_features)) && 1745 result != 0) { 1746 ath10k_err(ar, "otp calibration failed: %d", result); 1747 return -EINVAL; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int ath10k_download_cal_file(struct ath10k *ar, 1754 const struct firmware *file) 1755 { 1756 int ret; 1757 1758 if (!file) 1759 return -ENOENT; 1760 1761 if (IS_ERR(file)) 1762 return PTR_ERR(file); 1763 1764 ret = ath10k_download_board_data(ar, file->data, file->size); 1765 if (ret) { 1766 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1767 return ret; 1768 } 1769 1770 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1771 1772 return 0; 1773 } 1774 1775 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1776 { 1777 struct device_node *node; 1778 int data_len; 1779 void *data; 1780 int ret; 1781 1782 node = ar->dev->of_node; 1783 if (!node) 1784 /* Device Tree is optional, don't print any warnings if 1785 * there's no node for ath10k. 1786 */ 1787 return -ENOENT; 1788 1789 if (!of_get_property(node, dt_name, &data_len)) { 1790 /* The calibration data node is optional */ 1791 return -ENOENT; 1792 } 1793 1794 if (data_len != ar->hw_params.cal_data_len) { 1795 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1796 data_len); 1797 ret = -EMSGSIZE; 1798 goto out; 1799 } 1800 1801 data = kmalloc(data_len, GFP_KERNEL); 1802 if (!data) { 1803 ret = -ENOMEM; 1804 goto out; 1805 } 1806 1807 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1808 if (ret) { 1809 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1810 ret); 1811 goto out_free; 1812 } 1813 1814 ret = ath10k_download_board_data(ar, data, data_len); 1815 if (ret) { 1816 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1817 ret); 1818 goto out_free; 1819 } 1820 1821 ret = 0; 1822 1823 out_free: 1824 kfree(data); 1825 1826 out: 1827 return ret; 1828 } 1829 1830 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1831 { 1832 size_t data_len; 1833 void *data = NULL; 1834 int ret; 1835 1836 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1837 if (ret) { 1838 if (ret != -EOPNOTSUPP) 1839 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1840 ret); 1841 goto out_free; 1842 } 1843 1844 ret = ath10k_download_board_data(ar, data, data_len); 1845 if (ret) { 1846 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1847 ret); 1848 goto out_free; 1849 } 1850 1851 ret = 0; 1852 1853 out_free: 1854 kfree(data); 1855 1856 return ret; 1857 } 1858 1859 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1860 { 1861 struct nvmem_cell *cell; 1862 void *buf; 1863 size_t len; 1864 int ret; 1865 1866 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1867 if (IS_ERR(cell)) { 1868 ret = PTR_ERR(cell); 1869 return ret; 1870 } 1871 1872 buf = nvmem_cell_read(cell, &len); 1873 if (IS_ERR(buf)) 1874 return PTR_ERR(buf); 1875 1876 if (ar->hw_params.cal_data_len != len) { 1877 kfree(buf); 1878 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1879 cell_name, len, ar->hw_params.cal_data_len); 1880 return -EMSGSIZE; 1881 } 1882 1883 ret = ath10k_download_board_data(ar, buf, len); 1884 kfree(buf); 1885 if (ret) 1886 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 1887 cell_name, ret); 1888 1889 return ret; 1890 } 1891 1892 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 1893 struct ath10k_fw_file *fw_file) 1894 { 1895 size_t magic_len, len, ie_len; 1896 int ie_id, i, index, bit, ret; 1897 struct ath10k_fw_ie *hdr; 1898 const u8 *data; 1899 __le32 *timestamp, *version; 1900 1901 /* first fetch the firmware file (firmware-*.bin) */ 1902 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1903 name); 1904 if (IS_ERR(fw_file->firmware)) 1905 return PTR_ERR(fw_file->firmware); 1906 1907 data = fw_file->firmware->data; 1908 len = fw_file->firmware->size; 1909 1910 /* magic also includes the null byte, check that as well */ 1911 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 1912 1913 if (len < magic_len) { 1914 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 1915 ar->hw_params.fw.dir, name, len); 1916 ret = -EINVAL; 1917 goto err; 1918 } 1919 1920 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 1921 ath10k_err(ar, "invalid firmware magic\n"); 1922 ret = -EINVAL; 1923 goto err; 1924 } 1925 1926 /* jump over the padding */ 1927 magic_len = ALIGN(magic_len, 4); 1928 1929 len -= magic_len; 1930 data += magic_len; 1931 1932 /* loop elements */ 1933 while (len > sizeof(struct ath10k_fw_ie)) { 1934 hdr = (struct ath10k_fw_ie *)data; 1935 1936 ie_id = le32_to_cpu(hdr->id); 1937 ie_len = le32_to_cpu(hdr->len); 1938 1939 len -= sizeof(*hdr); 1940 data += sizeof(*hdr); 1941 1942 if (len < ie_len) { 1943 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 1944 ie_id, len, ie_len); 1945 ret = -EINVAL; 1946 goto err; 1947 } 1948 1949 switch (ie_id) { 1950 case ATH10K_FW_IE_FW_VERSION: 1951 if (ie_len > sizeof(fw_file->fw_version) - 1) 1952 break; 1953 1954 memcpy(fw_file->fw_version, data, ie_len); 1955 fw_file->fw_version[ie_len] = '\0'; 1956 1957 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1958 "found fw version %s\n", 1959 fw_file->fw_version); 1960 break; 1961 case ATH10K_FW_IE_TIMESTAMP: 1962 if (ie_len != sizeof(u32)) 1963 break; 1964 1965 timestamp = (__le32 *)data; 1966 1967 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 1968 le32_to_cpup(timestamp)); 1969 break; 1970 case ATH10K_FW_IE_FEATURES: 1971 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1972 "found firmware features ie (%zd B)\n", 1973 ie_len); 1974 1975 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 1976 index = i / 8; 1977 bit = i % 8; 1978 1979 if (index == ie_len) 1980 break; 1981 1982 if (data[index] & (1 << bit)) { 1983 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1984 "Enabling feature bit: %i\n", 1985 i); 1986 __set_bit(i, fw_file->fw_features); 1987 } 1988 } 1989 1990 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 1991 fw_file->fw_features, 1992 sizeof(fw_file->fw_features)); 1993 break; 1994 case ATH10K_FW_IE_FW_IMAGE: 1995 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1996 "found fw image ie (%zd B)\n", 1997 ie_len); 1998 1999 fw_file->firmware_data = data; 2000 fw_file->firmware_len = ie_len; 2001 2002 break; 2003 case ATH10K_FW_IE_OTP_IMAGE: 2004 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2005 "found otp image ie (%zd B)\n", 2006 ie_len); 2007 2008 fw_file->otp_data = data; 2009 fw_file->otp_len = ie_len; 2010 2011 break; 2012 case ATH10K_FW_IE_WMI_OP_VERSION: 2013 if (ie_len != sizeof(u32)) 2014 break; 2015 2016 version = (__le32 *)data; 2017 2018 fw_file->wmi_op_version = le32_to_cpup(version); 2019 2020 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2021 fw_file->wmi_op_version); 2022 break; 2023 case ATH10K_FW_IE_HTT_OP_VERSION: 2024 if (ie_len != sizeof(u32)) 2025 break; 2026 2027 version = (__le32 *)data; 2028 2029 fw_file->htt_op_version = le32_to_cpup(version); 2030 2031 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2032 fw_file->htt_op_version); 2033 break; 2034 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2035 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2036 "found fw code swap image ie (%zd B)\n", 2037 ie_len); 2038 fw_file->codeswap_data = data; 2039 fw_file->codeswap_len = ie_len; 2040 break; 2041 default: 2042 ath10k_warn(ar, "Unknown FW IE: %u\n", 2043 le32_to_cpu(hdr->id)); 2044 break; 2045 } 2046 2047 /* jump over the padding */ 2048 ie_len = ALIGN(ie_len, 4); 2049 2050 len -= ie_len; 2051 data += ie_len; 2052 } 2053 2054 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2055 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2056 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2057 ar->hw_params.fw.dir, name); 2058 ret = -ENOMEDIUM; 2059 goto err; 2060 } 2061 2062 return 0; 2063 2064 err: 2065 ath10k_core_free_firmware_files(ar); 2066 return ret; 2067 } 2068 2069 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2070 size_t fw_name_len, int fw_api) 2071 { 2072 switch (ar->hif.bus) { 2073 case ATH10K_BUS_SDIO: 2074 case ATH10K_BUS_USB: 2075 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2076 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2077 fw_api); 2078 break; 2079 case ATH10K_BUS_PCI: 2080 case ATH10K_BUS_AHB: 2081 case ATH10K_BUS_SNOC: 2082 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2083 ATH10K_FW_FILE_BASE, fw_api); 2084 break; 2085 } 2086 } 2087 2088 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2089 { 2090 int ret, i; 2091 char fw_name[100]; 2092 2093 /* calibration file is optional, don't check for any errors */ 2094 ath10k_fetch_cal_file(ar); 2095 2096 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2097 ar->fw_api = i; 2098 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2099 ar->fw_api); 2100 2101 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2102 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2103 &ar->normal_mode_fw.fw_file); 2104 if (!ret) 2105 goto success; 2106 } 2107 2108 /* we end up here if we couldn't fetch any firmware */ 2109 2110 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2111 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2112 ret); 2113 2114 return ret; 2115 2116 success: 2117 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2118 2119 return 0; 2120 } 2121 2122 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2123 { 2124 int ret; 2125 2126 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2127 if (ret == 0) { 2128 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2129 goto success; 2130 } else if (ret == -EPROBE_DEFER) { 2131 return ret; 2132 } 2133 2134 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2135 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2136 ret); 2137 2138 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2139 if (ret == 0) { 2140 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2141 goto success; 2142 } 2143 2144 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2145 "boot did not find a pre calibration file, try DT next: %d\n", 2146 ret); 2147 2148 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2149 if (ret) { 2150 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2151 "unable to load pre cal data from DT: %d\n", ret); 2152 return ret; 2153 } 2154 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2155 2156 success: 2157 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2158 ath10k_cal_mode_str(ar->cal_mode)); 2159 2160 return 0; 2161 } 2162 2163 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2164 { 2165 int ret; 2166 2167 ret = ath10k_core_pre_cal_download(ar); 2168 if (ret) { 2169 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2170 "failed to load pre cal data: %d\n", ret); 2171 return ret; 2172 } 2173 2174 ret = ath10k_core_get_board_id_from_otp(ar); 2175 if (ret) { 2176 ath10k_err(ar, "failed to get board id: %d\n", ret); 2177 return ret; 2178 } 2179 2180 ret = ath10k_download_and_run_otp(ar); 2181 if (ret) { 2182 ath10k_err(ar, "failed to run otp: %d\n", ret); 2183 return ret; 2184 } 2185 2186 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2187 "pre cal configuration done successfully\n"); 2188 2189 return 0; 2190 } 2191 2192 static int ath10k_download_cal_data(struct ath10k *ar) 2193 { 2194 int ret; 2195 2196 ret = ath10k_core_pre_cal_config(ar); 2197 if (ret == 0) 2198 return 0; 2199 2200 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2201 "pre cal download procedure failed, try cal file: %d\n", 2202 ret); 2203 2204 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2205 if (ret == 0) { 2206 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2207 goto done; 2208 } else if (ret == -EPROBE_DEFER) { 2209 return ret; 2210 } 2211 2212 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2213 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2214 ret); 2215 2216 ret = ath10k_download_cal_file(ar, ar->cal_file); 2217 if (ret == 0) { 2218 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2219 goto done; 2220 } 2221 2222 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2223 "boot did not find a calibration file, try DT next: %d\n", 2224 ret); 2225 2226 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2227 if (ret == 0) { 2228 ar->cal_mode = ATH10K_CAL_MODE_DT; 2229 goto done; 2230 } 2231 2232 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2233 "boot did not find DT entry, try target EEPROM next: %d\n", 2234 ret); 2235 2236 ret = ath10k_download_cal_eeprom(ar); 2237 if (ret == 0) { 2238 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2239 goto done; 2240 } 2241 2242 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2243 "boot did not find target EEPROM entry, try OTP next: %d\n", 2244 ret); 2245 2246 ret = ath10k_download_and_run_otp(ar); 2247 if (ret) { 2248 ath10k_err(ar, "failed to run otp: %d\n", ret); 2249 return ret; 2250 } 2251 2252 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2253 2254 done: 2255 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2256 ath10k_cal_mode_str(ar->cal_mode)); 2257 return 0; 2258 } 2259 2260 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2261 { 2262 struct device_node *node; 2263 u8 coex_support = 0; 2264 int ret; 2265 2266 node = ar->dev->of_node; 2267 if (!node) 2268 goto out; 2269 2270 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2271 if (ret) { 2272 ar->coex_support = true; 2273 goto out; 2274 } 2275 2276 if (coex_support) { 2277 ar->coex_support = true; 2278 } else { 2279 ar->coex_support = false; 2280 ar->coex_gpio_pin = -1; 2281 goto out; 2282 } 2283 2284 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2285 &ar->coex_gpio_pin); 2286 if (ret) 2287 ar->coex_gpio_pin = -1; 2288 2289 out: 2290 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2291 ar->coex_support, ar->coex_gpio_pin); 2292 } 2293 2294 static int ath10k_init_uart(struct ath10k *ar) 2295 { 2296 int ret; 2297 2298 /* 2299 * Explicitly setting UART prints to zero as target turns it on 2300 * based on scratch registers. 2301 */ 2302 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2303 if (ret) { 2304 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2305 return ret; 2306 } 2307 2308 if (!uart_print) { 2309 if (ar->hw_params.uart_pin_workaround) { 2310 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2311 ar->hw_params.uart_pin); 2312 if (ret) { 2313 ath10k_warn(ar, "failed to set UART TX pin: %d", 2314 ret); 2315 return ret; 2316 } 2317 } 2318 2319 return 0; 2320 } 2321 2322 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2323 if (ret) { 2324 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2325 return ret; 2326 } 2327 2328 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2329 if (ret) { 2330 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2331 return ret; 2332 } 2333 2334 /* Set the UART baud rate to 19200. */ 2335 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2336 if (ret) { 2337 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2338 return ret; 2339 } 2340 2341 ath10k_info(ar, "UART prints enabled\n"); 2342 return 0; 2343 } 2344 2345 static int ath10k_init_hw_params(struct ath10k *ar) 2346 { 2347 const struct ath10k_hw_params *hw_params; 2348 int i; 2349 2350 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2351 hw_params = &ath10k_hw_params_list[i]; 2352 2353 if (hw_params->bus == ar->hif.bus && 2354 hw_params->id == ar->target_version && 2355 hw_params->dev_id == ar->dev_id) 2356 break; 2357 } 2358 2359 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2360 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2361 ar->target_version); 2362 return -EINVAL; 2363 } 2364 2365 ar->hw_params = *hw_params; 2366 2367 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2368 ar->hw_params.name, ar->target_version); 2369 2370 return 0; 2371 } 2372 2373 void ath10k_core_start_recovery(struct ath10k *ar) 2374 { 2375 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) { 2376 ath10k_warn(ar, "already restarting\n"); 2377 return; 2378 } 2379 2380 queue_work(ar->workqueue, &ar->restart_work); 2381 } 2382 EXPORT_SYMBOL(ath10k_core_start_recovery); 2383 2384 void ath10k_core_napi_enable(struct ath10k *ar) 2385 { 2386 lockdep_assert_held(&ar->conf_mutex); 2387 2388 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2389 return; 2390 2391 napi_enable(&ar->napi); 2392 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2393 } 2394 EXPORT_SYMBOL(ath10k_core_napi_enable); 2395 2396 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2397 { 2398 lockdep_assert_held(&ar->conf_mutex); 2399 2400 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2401 return; 2402 2403 napi_synchronize(&ar->napi); 2404 napi_disable(&ar->napi); 2405 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2406 } 2407 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2408 2409 static void ath10k_core_restart(struct work_struct *work) 2410 { 2411 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2412 int ret; 2413 2414 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2415 2416 /* Place a barrier to make sure the compiler doesn't reorder 2417 * CRASH_FLUSH and calling other functions. 2418 */ 2419 barrier(); 2420 2421 ieee80211_stop_queues(ar->hw); 2422 ath10k_drain_tx(ar); 2423 complete(&ar->scan.started); 2424 complete(&ar->scan.completed); 2425 complete(&ar->scan.on_channel); 2426 complete(&ar->offchan_tx_completed); 2427 complete(&ar->install_key_done); 2428 complete(&ar->vdev_setup_done); 2429 complete(&ar->vdev_delete_done); 2430 complete(&ar->thermal.wmi_sync); 2431 complete(&ar->bss_survey_done); 2432 wake_up(&ar->htt.empty_tx_wq); 2433 wake_up(&ar->wmi.tx_credits_wq); 2434 wake_up(&ar->peer_mapping_wq); 2435 2436 /* TODO: We can have one instance of cancelling coverage_class_work by 2437 * moving it to ath10k_halt(), so that both stop() and restart() would 2438 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2439 * with conf_mutex it will deadlock. 2440 */ 2441 cancel_work_sync(&ar->set_coverage_class_work); 2442 2443 mutex_lock(&ar->conf_mutex); 2444 2445 switch (ar->state) { 2446 case ATH10K_STATE_ON: 2447 ar->state = ATH10K_STATE_RESTARTING; 2448 ath10k_halt(ar); 2449 ath10k_scan_finish(ar); 2450 ieee80211_restart_hw(ar->hw); 2451 break; 2452 case ATH10K_STATE_OFF: 2453 /* this can happen if driver is being unloaded 2454 * or if the crash happens during FW probing 2455 */ 2456 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2457 break; 2458 case ATH10K_STATE_RESTARTING: 2459 /* hw restart might be requested from multiple places */ 2460 break; 2461 case ATH10K_STATE_RESTARTED: 2462 ar->state = ATH10K_STATE_WEDGED; 2463 fallthrough; 2464 case ATH10K_STATE_WEDGED: 2465 ath10k_warn(ar, "device is wedged, will not restart\n"); 2466 break; 2467 case ATH10K_STATE_UTF: 2468 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2469 break; 2470 } 2471 2472 mutex_unlock(&ar->conf_mutex); 2473 2474 ret = ath10k_coredump_submit(ar); 2475 if (ret) 2476 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2477 ret); 2478 2479 complete(&ar->driver_recovery); 2480 } 2481 2482 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2483 { 2484 struct ath10k *ar = container_of(work, struct ath10k, 2485 set_coverage_class_work); 2486 2487 if (ar->hw_params.hw_ops->set_coverage_class) 2488 ar->hw_params.hw_ops->set_coverage_class(ar, -1); 2489 } 2490 2491 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2492 { 2493 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2494 int max_num_peers; 2495 2496 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2497 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2498 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2499 return -EINVAL; 2500 } 2501 2502 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2503 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2504 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2505 return -EINVAL; 2506 } 2507 2508 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2509 switch (ath10k_cryptmode_param) { 2510 case ATH10K_CRYPT_MODE_HW: 2511 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2512 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2513 break; 2514 case ATH10K_CRYPT_MODE_SW: 2515 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2516 fw_file->fw_features)) { 2517 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2518 return -EINVAL; 2519 } 2520 2521 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2522 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2523 break; 2524 default: 2525 ath10k_info(ar, "invalid cryptmode: %d\n", 2526 ath10k_cryptmode_param); 2527 return -EINVAL; 2528 } 2529 2530 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2531 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2532 2533 if (rawmode) { 2534 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2535 fw_file->fw_features)) { 2536 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2537 return -EINVAL; 2538 } 2539 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2540 } 2541 2542 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2543 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2544 2545 /* Workaround: 2546 * 2547 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2548 * and causes enormous performance issues (malformed frames, 2549 * etc). 2550 * 2551 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2552 * albeit a bit slower compared to regular operation. 2553 */ 2554 ar->htt.max_num_amsdu = 1; 2555 } 2556 2557 /* Backwards compatibility for firmwares without 2558 * ATH10K_FW_IE_WMI_OP_VERSION. 2559 */ 2560 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2561 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2562 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2563 fw_file->fw_features)) 2564 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2565 else 2566 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2567 } else { 2568 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2569 } 2570 } 2571 2572 switch (fw_file->wmi_op_version) { 2573 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2574 max_num_peers = TARGET_NUM_PEERS; 2575 ar->max_num_stations = TARGET_NUM_STATIONS; 2576 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2577 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2578 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2579 WMI_STAT_PEER; 2580 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2581 break; 2582 case ATH10K_FW_WMI_OP_VERSION_10_1: 2583 case ATH10K_FW_WMI_OP_VERSION_10_2: 2584 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2585 if (ath10k_peer_stats_enabled(ar)) { 2586 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2587 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2588 } else { 2589 max_num_peers = TARGET_10X_NUM_PEERS; 2590 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2591 } 2592 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2593 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2594 ar->fw_stats_req_mask = WMI_STAT_PEER; 2595 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2596 break; 2597 case ATH10K_FW_WMI_OP_VERSION_TLV: 2598 max_num_peers = TARGET_TLV_NUM_PEERS; 2599 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2600 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2601 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2602 if (ar->hif.bus == ATH10K_BUS_SDIO) 2603 ar->htt.max_num_pending_tx = 2604 TARGET_TLV_NUM_MSDU_DESC_HL; 2605 else 2606 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2607 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2608 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2609 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2610 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2611 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2612 break; 2613 case ATH10K_FW_WMI_OP_VERSION_10_4: 2614 max_num_peers = TARGET_10_4_NUM_PEERS; 2615 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2616 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2617 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2618 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2619 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2620 WMI_10_4_STAT_PEER_EXTD | 2621 WMI_10_4_STAT_VDEV_EXTD; 2622 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2623 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2624 2625 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2626 fw_file->fw_features)) 2627 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2628 else 2629 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2630 break; 2631 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2632 case ATH10K_FW_WMI_OP_VERSION_MAX: 2633 default: 2634 WARN_ON(1); 2635 return -EINVAL; 2636 } 2637 2638 if (ar->hw_params.num_peers) 2639 ar->max_num_peers = ar->hw_params.num_peers; 2640 else 2641 ar->max_num_peers = max_num_peers; 2642 2643 /* Backwards compatibility for firmwares without 2644 * ATH10K_FW_IE_HTT_OP_VERSION. 2645 */ 2646 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2647 switch (fw_file->wmi_op_version) { 2648 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2649 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2650 break; 2651 case ATH10K_FW_WMI_OP_VERSION_10_1: 2652 case ATH10K_FW_WMI_OP_VERSION_10_2: 2653 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2654 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2655 break; 2656 case ATH10K_FW_WMI_OP_VERSION_TLV: 2657 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2658 break; 2659 case ATH10K_FW_WMI_OP_VERSION_10_4: 2660 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2661 case ATH10K_FW_WMI_OP_VERSION_MAX: 2662 ath10k_err(ar, "htt op version not found from fw meta data"); 2663 return -EINVAL; 2664 } 2665 } 2666 2667 return 0; 2668 } 2669 2670 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2671 { 2672 int ret; 2673 int vdev_id; 2674 int vdev_type; 2675 int vdev_subtype; 2676 const u8 *vdev_addr; 2677 2678 vdev_id = 0; 2679 vdev_type = WMI_VDEV_TYPE_STA; 2680 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2681 vdev_addr = ar->mac_addr; 2682 2683 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2684 vdev_addr); 2685 if (ret) { 2686 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2687 return ret; 2688 } 2689 2690 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2691 if (ret) { 2692 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2693 return ret; 2694 } 2695 2696 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2697 * serialized properly implicitly. 2698 * 2699 * Moreover (most) WMI commands have no explicit acknowledges. It is 2700 * possible to infer it implicitly by poking firmware with echo 2701 * command - getting a reply means all preceding comments have been 2702 * (mostly) processed. 2703 * 2704 * In case of vdev create/delete this is sufficient. 2705 * 2706 * Without this it's possible to end up with a race when HTT Rx ring is 2707 * started before vdev create/delete hack is complete allowing a short 2708 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2709 */ 2710 ret = ath10k_wmi_barrier(ar); 2711 if (ret) { 2712 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2713 return ret; 2714 } 2715 2716 return 0; 2717 } 2718 2719 static int ath10k_core_compat_services(struct ath10k *ar) 2720 { 2721 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2722 2723 /* all 10.x firmware versions support thermal throttling but don't 2724 * advertise the support via service flags so we have to hardcode 2725 * it here 2726 */ 2727 switch (fw_file->wmi_op_version) { 2728 case ATH10K_FW_WMI_OP_VERSION_10_1: 2729 case ATH10K_FW_WMI_OP_VERSION_10_2: 2730 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2731 case ATH10K_FW_WMI_OP_VERSION_10_4: 2732 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2733 break; 2734 default: 2735 break; 2736 } 2737 2738 return 0; 2739 } 2740 2741 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2742 2743 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2744 { 2745 const struct ath10k_hw_mem_layout *hw_mem; 2746 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2747 dma_addr_t paddr; 2748 void *vaddr = NULL; 2749 u8 num_read_itr; 2750 int i, ret; 2751 u32 len, remaining_len; 2752 2753 /* copy target iram feature must work also when 2754 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2755 * _ath10k_coredump_get_mem_layout() to accomplist that 2756 */ 2757 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2758 if (!hw_mem) 2759 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2760 * just silently disable the feature by doing nothing 2761 */ 2762 return 0; 2763 2764 for (i = 0; i < hw_mem->region_table.size; i++) { 2765 tmp = &hw_mem->region_table.regions[i]; 2766 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2767 mem_region = tmp; 2768 break; 2769 } 2770 } 2771 2772 if (!mem_region) 2773 return -ENOMEM; 2774 2775 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2776 if (ar->wmi.mem_chunks[i].req_id == 2777 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2778 vaddr = ar->wmi.mem_chunks[i].vaddr; 2779 len = ar->wmi.mem_chunks[i].len; 2780 break; 2781 } 2782 } 2783 2784 if (!vaddr || !len) { 2785 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2786 return -ENOMEM; 2787 } 2788 2789 len = (len < mem_region->len) ? len : mem_region->len; 2790 paddr = mem_region->start; 2791 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2792 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2793 for (i = 0; i < num_read_itr; i++) { 2794 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2795 TGT_IRAM_READ_PER_ITR); 2796 if (ret) { 2797 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2798 ret); 2799 return ret; 2800 } 2801 2802 paddr += TGT_IRAM_READ_PER_ITR; 2803 vaddr += TGT_IRAM_READ_PER_ITR; 2804 } 2805 2806 if (remaining_len) { 2807 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2808 if (ret) { 2809 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2810 ret); 2811 return ret; 2812 } 2813 } 2814 2815 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2816 2817 return 0; 2818 } 2819 2820 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2821 const struct ath10k_fw_components *fw) 2822 { 2823 int status; 2824 u32 val; 2825 2826 lockdep_assert_held(&ar->conf_mutex); 2827 2828 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2829 2830 ar->running_fw = fw; 2831 2832 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2833 ar->running_fw->fw_file.fw_features)) { 2834 ath10k_bmi_start(ar); 2835 2836 /* Enable hardware clock to speed up firmware download */ 2837 if (ar->hw_params.hw_ops->enable_pll_clk) { 2838 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2839 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2840 status); 2841 } 2842 2843 if (ath10k_init_configure_target(ar)) { 2844 status = -EINVAL; 2845 goto err; 2846 } 2847 2848 status = ath10k_download_cal_data(ar); 2849 if (status) 2850 goto err; 2851 2852 /* Some of qca988x solutions are having global reset issue 2853 * during target initialization. Bypassing PLL setting before 2854 * downloading firmware and letting the SoC run on REF_CLK is 2855 * fixing the problem. Corresponding firmware change is also 2856 * needed to set the clock source once the target is 2857 * initialized. 2858 */ 2859 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 2860 ar->running_fw->fw_file.fw_features)) { 2861 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 2862 if (status) { 2863 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 2864 status); 2865 goto err; 2866 } 2867 } 2868 2869 status = ath10k_download_fw(ar); 2870 if (status) 2871 goto err; 2872 2873 status = ath10k_init_uart(ar); 2874 if (status) 2875 goto err; 2876 2877 if (ar->hif.bus == ATH10K_BUS_SDIO) { 2878 status = ath10k_init_sdio(ar, mode); 2879 if (status) { 2880 ath10k_err(ar, "failed to init SDIO: %d\n", status); 2881 goto err; 2882 } 2883 } 2884 } 2885 2886 ar->htc.htc_ops.target_send_suspend_complete = 2887 ath10k_send_suspend_complete; 2888 2889 status = ath10k_htc_init(ar); 2890 if (status) { 2891 ath10k_err(ar, "could not init HTC (%d)\n", status); 2892 goto err; 2893 } 2894 2895 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2896 ar->running_fw->fw_file.fw_features)) { 2897 status = ath10k_bmi_done(ar); 2898 if (status) 2899 goto err; 2900 } 2901 2902 status = ath10k_wmi_attach(ar); 2903 if (status) { 2904 ath10k_err(ar, "WMI attach failed: %d\n", status); 2905 goto err; 2906 } 2907 2908 status = ath10k_htt_init(ar); 2909 if (status) { 2910 ath10k_err(ar, "failed to init htt: %d\n", status); 2911 goto err_wmi_detach; 2912 } 2913 2914 status = ath10k_htt_tx_start(&ar->htt); 2915 if (status) { 2916 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 2917 goto err_wmi_detach; 2918 } 2919 2920 /* If firmware indicates Full Rx Reorder support it must be used in a 2921 * slightly different manner. Let HTT code know. 2922 */ 2923 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 2924 ar->wmi.svc_map)); 2925 2926 status = ath10k_htt_rx_alloc(&ar->htt); 2927 if (status) { 2928 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 2929 goto err_htt_tx_detach; 2930 } 2931 2932 status = ath10k_hif_start(ar); 2933 if (status) { 2934 ath10k_err(ar, "could not start HIF: %d\n", status); 2935 goto err_htt_rx_detach; 2936 } 2937 2938 status = ath10k_htc_wait_target(&ar->htc); 2939 if (status) { 2940 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 2941 goto err_hif_stop; 2942 } 2943 2944 status = ath10k_hif_start_post(ar); 2945 if (status) { 2946 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 2947 goto err_hif_stop; 2948 } 2949 2950 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2951 status = ath10k_htt_connect(&ar->htt); 2952 if (status) { 2953 ath10k_err(ar, "failed to connect htt (%d)\n", status); 2954 goto err_hif_stop; 2955 } 2956 } 2957 2958 status = ath10k_wmi_connect(ar); 2959 if (status) { 2960 ath10k_err(ar, "could not connect wmi: %d\n", status); 2961 goto err_hif_stop; 2962 } 2963 2964 status = ath10k_htc_start(&ar->htc); 2965 if (status) { 2966 ath10k_err(ar, "failed to start htc: %d\n", status); 2967 goto err_hif_stop; 2968 } 2969 2970 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2971 status = ath10k_wmi_wait_for_service_ready(ar); 2972 if (status) { 2973 ath10k_warn(ar, "wmi service ready event not received"); 2974 goto err_hif_stop; 2975 } 2976 } 2977 2978 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 2979 ar->hw->wiphy->fw_version); 2980 2981 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 2982 ar->running_fw->fw_file.fw_features)) { 2983 status = ath10k_core_copy_target_iram(ar); 2984 if (status) { 2985 ath10k_warn(ar, "failed to copy target iram contents: %d", 2986 status); 2987 goto err_hif_stop; 2988 } 2989 } 2990 2991 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 2992 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 2993 val = 0; 2994 if (ath10k_peer_stats_enabled(ar)) 2995 val = WMI_10_4_PEER_STATS; 2996 2997 /* Enable vdev stats by default */ 2998 val |= WMI_10_4_VDEV_STATS; 2999 3000 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3001 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3002 3003 ath10k_core_fetch_btcoex_dt(ar); 3004 3005 /* 10.4 firmware supports BT-Coex without reloading firmware 3006 * via pdev param. To support Bluetooth coexistence pdev param, 3007 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3008 * enabled always. 3009 * 3010 * We can still enable BTCOEX if firmware has the support 3011 * eventhough btceox_support value is 3012 * ATH10K_DT_BTCOEX_NOT_FOUND 3013 */ 3014 3015 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3016 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3017 ar->running_fw->fw_file.fw_features) && 3018 ar->coex_support) 3019 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3020 3021 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3022 ar->wmi.svc_map)) 3023 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3024 3025 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3026 ar->wmi.svc_map)) 3027 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3028 3029 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3030 ar->wmi.svc_map)) 3031 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3032 3033 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3034 val |= WMI_10_4_REPORT_AIRTIME; 3035 3036 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3037 ar->wmi.svc_map)) 3038 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3039 3040 status = ath10k_mac_ext_resource_config(ar, val); 3041 if (status) { 3042 ath10k_err(ar, 3043 "failed to send ext resource cfg command : %d\n", 3044 status); 3045 goto err_hif_stop; 3046 } 3047 } 3048 3049 status = ath10k_wmi_cmd_init(ar); 3050 if (status) { 3051 ath10k_err(ar, "could not send WMI init command (%d)\n", 3052 status); 3053 goto err_hif_stop; 3054 } 3055 3056 status = ath10k_wmi_wait_for_unified_ready(ar); 3057 if (status) { 3058 ath10k_err(ar, "wmi unified ready event not received\n"); 3059 goto err_hif_stop; 3060 } 3061 3062 status = ath10k_core_compat_services(ar); 3063 if (status) { 3064 ath10k_err(ar, "compat services failed: %d\n", status); 3065 goto err_hif_stop; 3066 } 3067 3068 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3069 if (status && status != -EOPNOTSUPP) { 3070 ath10k_err(ar, 3071 "failed to set base mac address: %d\n", status); 3072 goto err_hif_stop; 3073 } 3074 3075 /* Some firmware revisions do not properly set up hardware rx filter 3076 * registers. 3077 * 3078 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3079 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3080 * any frames that matches MAC_PCU_RX_FILTER which is also 3081 * misconfigured to accept anything. 3082 * 3083 * The ADDR1 is programmed using internal firmware structure field and 3084 * can't be (easily/sanely) reached from the driver explicitly. It is 3085 * possible to implicitly make it correct by creating a dummy vdev and 3086 * then deleting it. 3087 */ 3088 if (ar->hw_params.hw_filter_reset_required && 3089 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3090 status = ath10k_core_reset_rx_filter(ar); 3091 if (status) { 3092 ath10k_err(ar, 3093 "failed to reset rx filter: %d\n", status); 3094 goto err_hif_stop; 3095 } 3096 } 3097 3098 status = ath10k_htt_rx_ring_refill(ar); 3099 if (status) { 3100 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3101 goto err_hif_stop; 3102 } 3103 3104 if (ar->max_num_vdevs >= 64) 3105 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3106 else 3107 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3108 3109 INIT_LIST_HEAD(&ar->arvifs); 3110 3111 /* we don't care about HTT in UTF mode */ 3112 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3113 status = ath10k_htt_setup(&ar->htt); 3114 if (status) { 3115 ath10k_err(ar, "failed to setup htt: %d\n", status); 3116 goto err_hif_stop; 3117 } 3118 } 3119 3120 status = ath10k_debug_start(ar); 3121 if (status) 3122 goto err_hif_stop; 3123 3124 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3125 if (status && status != -EOPNOTSUPP) { 3126 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3127 goto err_hif_stop; 3128 } 3129 3130 return 0; 3131 3132 err_hif_stop: 3133 ath10k_hif_stop(ar); 3134 err_htt_rx_detach: 3135 ath10k_htt_rx_free(&ar->htt); 3136 err_htt_tx_detach: 3137 ath10k_htt_tx_free(&ar->htt); 3138 err_wmi_detach: 3139 ath10k_wmi_detach(ar); 3140 err: 3141 return status; 3142 } 3143 EXPORT_SYMBOL(ath10k_core_start); 3144 3145 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3146 { 3147 int ret; 3148 unsigned long time_left; 3149 3150 reinit_completion(&ar->target_suspend); 3151 3152 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3153 if (ret) { 3154 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3155 return ret; 3156 } 3157 3158 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3159 3160 if (!time_left) { 3161 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3162 return -ETIMEDOUT; 3163 } 3164 3165 return 0; 3166 } 3167 3168 void ath10k_core_stop(struct ath10k *ar) 3169 { 3170 lockdep_assert_held(&ar->conf_mutex); 3171 ath10k_debug_stop(ar); 3172 3173 /* try to suspend target */ 3174 if (ar->state != ATH10K_STATE_RESTARTING && 3175 ar->state != ATH10K_STATE_UTF) 3176 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3177 3178 ath10k_hif_stop(ar); 3179 ath10k_htt_tx_stop(&ar->htt); 3180 ath10k_htt_rx_free(&ar->htt); 3181 ath10k_wmi_detach(ar); 3182 3183 ar->id.bmi_ids_valid = false; 3184 } 3185 EXPORT_SYMBOL(ath10k_core_stop); 3186 3187 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3188 * order to know what hw capabilities should be advertised to mac80211 it is 3189 * necessary to load the firmware (and tear it down immediately since start 3190 * hook will try to init it again) before registering 3191 */ 3192 static int ath10k_core_probe_fw(struct ath10k *ar) 3193 { 3194 struct bmi_target_info target_info; 3195 int ret = 0; 3196 3197 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3198 if (ret) { 3199 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3200 return ret; 3201 } 3202 3203 switch (ar->hif.bus) { 3204 case ATH10K_BUS_SDIO: 3205 memset(&target_info, 0, sizeof(target_info)); 3206 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3207 if (ret) { 3208 ath10k_err(ar, "could not get target info (%d)\n", ret); 3209 goto err_power_down; 3210 } 3211 ar->target_version = target_info.version; 3212 ar->hw->wiphy->hw_version = target_info.version; 3213 break; 3214 case ATH10K_BUS_PCI: 3215 case ATH10K_BUS_AHB: 3216 case ATH10K_BUS_USB: 3217 memset(&target_info, 0, sizeof(target_info)); 3218 ret = ath10k_bmi_get_target_info(ar, &target_info); 3219 if (ret) { 3220 ath10k_err(ar, "could not get target info (%d)\n", ret); 3221 goto err_power_down; 3222 } 3223 ar->target_version = target_info.version; 3224 ar->hw->wiphy->hw_version = target_info.version; 3225 break; 3226 case ATH10K_BUS_SNOC: 3227 memset(&target_info, 0, sizeof(target_info)); 3228 ret = ath10k_hif_get_target_info(ar, &target_info); 3229 if (ret) { 3230 ath10k_err(ar, "could not get target info (%d)\n", ret); 3231 goto err_power_down; 3232 } 3233 ar->target_version = target_info.version; 3234 ar->hw->wiphy->hw_version = target_info.version; 3235 break; 3236 default: 3237 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3238 } 3239 3240 ret = ath10k_init_hw_params(ar); 3241 if (ret) { 3242 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3243 goto err_power_down; 3244 } 3245 3246 ret = ath10k_core_fetch_firmware_files(ar); 3247 if (ret) { 3248 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3249 goto err_power_down; 3250 } 3251 3252 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3253 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3254 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3255 sizeof(ar->hw->wiphy->fw_version)); 3256 3257 ath10k_debug_print_hwfw_info(ar); 3258 3259 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3260 ar->normal_mode_fw.fw_file.fw_features)) { 3261 ret = ath10k_core_pre_cal_download(ar); 3262 if (ret) { 3263 /* pre calibration data download is not necessary 3264 * for all the chipsets. Ignore failures and continue. 3265 */ 3266 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3267 "could not load pre cal data: %d\n", ret); 3268 } 3269 3270 ret = ath10k_core_get_board_id_from_otp(ar); 3271 if (ret && ret != -EOPNOTSUPP) { 3272 ath10k_err(ar, "failed to get board id from otp: %d\n", 3273 ret); 3274 goto err_free_firmware_files; 3275 } 3276 3277 ret = ath10k_core_check_smbios(ar); 3278 if (ret) 3279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3280 3281 ret = ath10k_core_check_dt(ar); 3282 if (ret) 3283 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3284 3285 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3286 if (ret) { 3287 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3288 goto err_free_firmware_files; 3289 } 3290 3291 ath10k_debug_print_board_info(ar); 3292 } 3293 3294 device_get_mac_address(ar->dev, ar->mac_addr); 3295 3296 ret = ath10k_core_init_firmware_features(ar); 3297 if (ret) { 3298 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3299 ret); 3300 goto err_free_firmware_files; 3301 } 3302 3303 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3304 ar->normal_mode_fw.fw_file.fw_features)) { 3305 ret = ath10k_swap_code_seg_init(ar, 3306 &ar->normal_mode_fw.fw_file); 3307 if (ret) { 3308 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3309 ret); 3310 goto err_free_firmware_files; 3311 } 3312 } 3313 3314 mutex_lock(&ar->conf_mutex); 3315 3316 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3317 &ar->normal_mode_fw); 3318 if (ret) { 3319 ath10k_err(ar, "could not init core (%d)\n", ret); 3320 goto err_unlock; 3321 } 3322 3323 ath10k_debug_print_boot_info(ar); 3324 ath10k_core_stop(ar); 3325 3326 mutex_unlock(&ar->conf_mutex); 3327 3328 ath10k_hif_power_down(ar); 3329 return 0; 3330 3331 err_unlock: 3332 mutex_unlock(&ar->conf_mutex); 3333 3334 err_free_firmware_files: 3335 ath10k_core_free_firmware_files(ar); 3336 3337 err_power_down: 3338 ath10k_hif_power_down(ar); 3339 3340 return ret; 3341 } 3342 3343 static void ath10k_core_register_work(struct work_struct *work) 3344 { 3345 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3346 int status; 3347 3348 /* peer stats are enabled by default */ 3349 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3350 3351 status = ath10k_core_probe_fw(ar); 3352 if (status) { 3353 ath10k_err(ar, "could not probe fw (%d)\n", status); 3354 goto err; 3355 } 3356 3357 status = ath10k_mac_register(ar); 3358 if (status) { 3359 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3360 goto err_release_fw; 3361 } 3362 3363 status = ath10k_coredump_register(ar); 3364 if (status) { 3365 ath10k_err(ar, "unable to register coredump\n"); 3366 goto err_unregister_mac; 3367 } 3368 3369 status = ath10k_debug_register(ar); 3370 if (status) { 3371 ath10k_err(ar, "unable to initialize debugfs\n"); 3372 goto err_unregister_coredump; 3373 } 3374 3375 status = ath10k_spectral_create(ar); 3376 if (status) { 3377 ath10k_err(ar, "failed to initialize spectral\n"); 3378 goto err_debug_destroy; 3379 } 3380 3381 status = ath10k_thermal_register(ar); 3382 if (status) { 3383 ath10k_err(ar, "could not register thermal device: %d\n", 3384 status); 3385 goto err_spectral_destroy; 3386 } 3387 3388 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3389 return; 3390 3391 err_spectral_destroy: 3392 ath10k_spectral_destroy(ar); 3393 err_debug_destroy: 3394 ath10k_debug_destroy(ar); 3395 err_unregister_coredump: 3396 ath10k_coredump_unregister(ar); 3397 err_unregister_mac: 3398 ath10k_mac_unregister(ar); 3399 err_release_fw: 3400 ath10k_core_free_firmware_files(ar); 3401 err: 3402 /* TODO: It's probably a good idea to release device from the driver 3403 * but calling device_release_driver() here will cause a deadlock. 3404 */ 3405 return; 3406 } 3407 3408 int ath10k_core_register(struct ath10k *ar, 3409 const struct ath10k_bus_params *bus_params) 3410 { 3411 ar->bus_param = *bus_params; 3412 3413 queue_work(ar->workqueue, &ar->register_work); 3414 3415 return 0; 3416 } 3417 EXPORT_SYMBOL(ath10k_core_register); 3418 3419 void ath10k_core_unregister(struct ath10k *ar) 3420 { 3421 cancel_work_sync(&ar->register_work); 3422 3423 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3424 return; 3425 3426 ath10k_thermal_unregister(ar); 3427 /* Stop spectral before unregistering from mac80211 to remove the 3428 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3429 * would be already be free'd recursively, leading to a double free. 3430 */ 3431 ath10k_spectral_destroy(ar); 3432 3433 /* We must unregister from mac80211 before we stop HTC and HIF. 3434 * Otherwise we will fail to submit commands to FW and mac80211 will be 3435 * unhappy about callback failures. 3436 */ 3437 ath10k_mac_unregister(ar); 3438 3439 ath10k_testmode_destroy(ar); 3440 3441 ath10k_core_free_firmware_files(ar); 3442 ath10k_core_free_board_files(ar); 3443 3444 ath10k_debug_unregister(ar); 3445 } 3446 EXPORT_SYMBOL(ath10k_core_unregister); 3447 3448 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3449 enum ath10k_bus bus, 3450 enum ath10k_hw_rev hw_rev, 3451 const struct ath10k_hif_ops *hif_ops) 3452 { 3453 struct ath10k *ar; 3454 int ret; 3455 3456 ar = ath10k_mac_create(priv_size); 3457 if (!ar) 3458 return NULL; 3459 3460 ar->ath_common.priv = ar; 3461 ar->ath_common.hw = ar->hw; 3462 ar->dev = dev; 3463 ar->hw_rev = hw_rev; 3464 ar->hif.ops = hif_ops; 3465 ar->hif.bus = bus; 3466 3467 switch (hw_rev) { 3468 case ATH10K_HW_QCA988X: 3469 case ATH10K_HW_QCA9887: 3470 ar->regs = &qca988x_regs; 3471 ar->hw_ce_regs = &qcax_ce_regs; 3472 ar->hw_values = &qca988x_values; 3473 break; 3474 case ATH10K_HW_QCA6174: 3475 case ATH10K_HW_QCA9377: 3476 ar->regs = &qca6174_regs; 3477 ar->hw_ce_regs = &qcax_ce_regs; 3478 ar->hw_values = &qca6174_values; 3479 break; 3480 case ATH10K_HW_QCA99X0: 3481 case ATH10K_HW_QCA9984: 3482 ar->regs = &qca99x0_regs; 3483 ar->hw_ce_regs = &qcax_ce_regs; 3484 ar->hw_values = &qca99x0_values; 3485 break; 3486 case ATH10K_HW_QCA9888: 3487 ar->regs = &qca99x0_regs; 3488 ar->hw_ce_regs = &qcax_ce_regs; 3489 ar->hw_values = &qca9888_values; 3490 break; 3491 case ATH10K_HW_QCA4019: 3492 ar->regs = &qca4019_regs; 3493 ar->hw_ce_regs = &qcax_ce_regs; 3494 ar->hw_values = &qca4019_values; 3495 break; 3496 case ATH10K_HW_WCN3990: 3497 ar->regs = &wcn3990_regs; 3498 ar->hw_ce_regs = &wcn3990_ce_regs; 3499 ar->hw_values = &wcn3990_values; 3500 break; 3501 default: 3502 ath10k_err(ar, "unsupported core hardware revision %d\n", 3503 hw_rev); 3504 ret = -ENOTSUPP; 3505 goto err_free_mac; 3506 } 3507 3508 init_completion(&ar->scan.started); 3509 init_completion(&ar->scan.completed); 3510 init_completion(&ar->scan.on_channel); 3511 init_completion(&ar->target_suspend); 3512 init_completion(&ar->driver_recovery); 3513 init_completion(&ar->wow.wakeup_completed); 3514 3515 init_completion(&ar->install_key_done); 3516 init_completion(&ar->vdev_setup_done); 3517 init_completion(&ar->vdev_delete_done); 3518 init_completion(&ar->thermal.wmi_sync); 3519 init_completion(&ar->bss_survey_done); 3520 init_completion(&ar->peer_delete_done); 3521 init_completion(&ar->peer_stats_info_complete); 3522 3523 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3524 3525 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3526 if (!ar->workqueue) 3527 goto err_free_mac; 3528 3529 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3530 if (!ar->workqueue_aux) 3531 goto err_free_wq; 3532 3533 ar->workqueue_tx_complete = 3534 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3535 if (!ar->workqueue_tx_complete) 3536 goto err_free_aux_wq; 3537 3538 mutex_init(&ar->conf_mutex); 3539 mutex_init(&ar->dump_mutex); 3540 spin_lock_init(&ar->data_lock); 3541 3542 INIT_LIST_HEAD(&ar->peers); 3543 init_waitqueue_head(&ar->peer_mapping_wq); 3544 init_waitqueue_head(&ar->htt.empty_tx_wq); 3545 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3546 3547 skb_queue_head_init(&ar->htt.rx_indication_head); 3548 3549 init_completion(&ar->offchan_tx_completed); 3550 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3551 skb_queue_head_init(&ar->offchan_tx_queue); 3552 3553 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3554 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3555 3556 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3557 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3558 INIT_WORK(&ar->set_coverage_class_work, 3559 ath10k_core_set_coverage_class_work); 3560 3561 init_dummy_netdev(&ar->napi_dev); 3562 3563 ret = ath10k_coredump_create(ar); 3564 if (ret) 3565 goto err_free_tx_complete; 3566 3567 ret = ath10k_debug_create(ar); 3568 if (ret) 3569 goto err_free_coredump; 3570 3571 return ar; 3572 3573 err_free_coredump: 3574 ath10k_coredump_destroy(ar); 3575 err_free_tx_complete: 3576 destroy_workqueue(ar->workqueue_tx_complete); 3577 err_free_aux_wq: 3578 destroy_workqueue(ar->workqueue_aux); 3579 err_free_wq: 3580 destroy_workqueue(ar->workqueue); 3581 err_free_mac: 3582 ath10k_mac_destroy(ar); 3583 3584 return NULL; 3585 } 3586 EXPORT_SYMBOL(ath10k_core_create); 3587 3588 void ath10k_core_destroy(struct ath10k *ar) 3589 { 3590 destroy_workqueue(ar->workqueue); 3591 3592 destroy_workqueue(ar->workqueue_aux); 3593 3594 destroy_workqueue(ar->workqueue_tx_complete); 3595 3596 ath10k_debug_destroy(ar); 3597 ath10k_coredump_destroy(ar); 3598 ath10k_htt_tx_destroy(&ar->htt); 3599 ath10k_wmi_free_host_mem(ar); 3600 ath10k_mac_destroy(ar); 3601 } 3602 EXPORT_SYMBOL(ath10k_core_destroy); 3603 3604 MODULE_AUTHOR("Qualcomm Atheros"); 3605 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3606 MODULE_LICENSE("Dual BSD/GPL"); 3607