1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _CE_H_ 19 #define _CE_H_ 20 21 #include "hif.h" 22 23 /* Maximum number of Copy Engine's supported */ 24 #define CE_COUNT_MAX 12 25 #define CE_HTT_H2T_MSG_SRC_NENTRIES 4096 26 27 /* Descriptor rings must be aligned to this boundary */ 28 #define CE_DESC_RING_ALIGN 8 29 #define CE_SEND_FLAG_GATHER 0x00010000 30 31 /* 32 * Copy Engine support: low-level Target-side Copy Engine API. 33 * This is a hardware access layer used by code that understands 34 * how to use copy engines. 35 */ 36 37 struct ath10k_ce_pipe; 38 39 #define CE_DESC_FLAGS_GATHER (1 << 0) 40 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 41 42 /* Following desc flags are used in QCA99X0 */ 43 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2) 44 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3) 45 46 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask 47 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb 48 49 struct ce_desc { 50 __le32 addr; 51 __le16 nbytes; 52 __le16 flags; /* %CE_DESC_FLAGS_ */ 53 }; 54 55 struct ath10k_ce_ring { 56 /* Number of entries in this ring; must be power of 2 */ 57 unsigned int nentries; 58 unsigned int nentries_mask; 59 60 /* 61 * For dest ring, this is the next index to be processed 62 * by software after it was/is received into. 63 * 64 * For src ring, this is the last descriptor that was sent 65 * and completion processed by software. 66 * 67 * Regardless of src or dest ring, this is an invariant 68 * (modulo ring size): 69 * write index >= read index >= sw_index 70 */ 71 unsigned int sw_index; 72 /* cached copy */ 73 unsigned int write_index; 74 /* 75 * For src ring, this is the next index not yet processed by HW. 76 * This is a cached copy of the real HW index (read index), used 77 * for avoiding reading the HW index register more often than 78 * necessary. 79 * This extends the invariant: 80 * write index >= read index >= hw_index >= sw_index 81 * 82 * For dest ring, this is currently unused. 83 */ 84 /* cached copy */ 85 unsigned int hw_index; 86 87 /* Start of DMA-coherent area reserved for descriptors */ 88 /* Host address space */ 89 void *base_addr_owner_space_unaligned; 90 /* CE address space */ 91 u32 base_addr_ce_space_unaligned; 92 93 /* 94 * Actual start of descriptors. 95 * Aligned to descriptor-size boundary. 96 * Points into reserved DMA-coherent area, above. 97 */ 98 /* Host address space */ 99 void *base_addr_owner_space; 100 101 /* CE address space */ 102 u32 base_addr_ce_space; 103 /* 104 * Start of shadow copy of descriptors, within regular memory. 105 * Aligned to descriptor-size boundary. 106 */ 107 void *shadow_base_unaligned; 108 struct ce_desc *shadow_base; 109 110 /* keep last */ 111 void *per_transfer_context[0]; 112 }; 113 114 struct ath10k_ce_pipe { 115 struct ath10k *ar; 116 unsigned int id; 117 118 unsigned int attr_flags; 119 120 u32 ctrl_addr; 121 122 void (*send_cb)(struct ath10k_ce_pipe *); 123 void (*recv_cb)(struct ath10k_ce_pipe *); 124 125 unsigned int src_sz_max; 126 struct ath10k_ce_ring *src_ring; 127 struct ath10k_ce_ring *dest_ring; 128 }; 129 130 /* Copy Engine settable attributes */ 131 struct ce_attr; 132 133 /*==================Send====================*/ 134 135 /* ath10k_ce_send flags */ 136 #define CE_SEND_FLAG_BYTE_SWAP 1 137 138 /* 139 * Queue a source buffer to be sent to an anonymous destination buffer. 140 * ce - which copy engine to use 141 * buffer - address of buffer 142 * nbytes - number of bytes to send 143 * transfer_id - arbitrary ID; reflected to destination 144 * flags - CE_SEND_FLAG_* values 145 * Returns 0 on success; otherwise an error status. 146 * 147 * Note: If no flags are specified, use CE's default data swap mode. 148 * 149 * Implementation note: pushes 1 buffer to Source ring 150 */ 151 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 152 void *per_transfer_send_context, 153 u32 buffer, 154 unsigned int nbytes, 155 /* 14 bits */ 156 unsigned int transfer_id, 157 unsigned int flags); 158 159 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 160 void *per_transfer_context, 161 u32 buffer, 162 unsigned int nbytes, 163 unsigned int transfer_id, 164 unsigned int flags); 165 166 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe); 167 168 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 169 170 /*==================Recv=======================*/ 171 172 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); 173 int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 174 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 175 176 /* recv flags */ 177 /* Data is byte-swapped */ 178 #define CE_RECV_FLAG_SWAPPED 1 179 180 /* 181 * Supply data for the next completed unprocessed receive descriptor. 182 * Pops buffer from Dest ring. 183 */ 184 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 185 void **per_transfer_contextp, 186 u32 *bufferp, 187 unsigned int *nbytesp, 188 unsigned int *transfer_idp, 189 unsigned int *flagsp); 190 /* 191 * Supply data for the next completed unprocessed send descriptor. 192 * Pops 1 completed send buffer from Source ring. 193 */ 194 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 195 void **per_transfer_contextp, 196 u32 *bufferp, 197 unsigned int *nbytesp, 198 unsigned int *transfer_idp); 199 200 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 201 void **per_transfer_contextp, 202 u32 *bufferp, 203 unsigned int *nbytesp, 204 unsigned int *transfer_idp); 205 206 /*==================CE Engine Initialization=======================*/ 207 208 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 209 const struct ce_attr *attr); 210 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id); 211 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 212 const struct ce_attr *attr, 213 void (*send_cb)(struct ath10k_ce_pipe *), 214 void (*recv_cb)(struct ath10k_ce_pipe *)); 215 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); 216 217 /*==================CE Engine Shutdown=======================*/ 218 /* 219 * Support clean shutdown by allowing the caller to revoke 220 * receive buffers. Target DMA must be stopped before using 221 * this API. 222 */ 223 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 224 void **per_transfer_contextp, 225 u32 *bufferp); 226 227 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, 228 void **per_transfer_contextp, 229 u32 *bufferp, 230 unsigned int *nbytesp, 231 unsigned int *transfer_idp, 232 unsigned int *flagsp); 233 234 /* 235 * Support clean shutdown by allowing the caller to cancel 236 * pending sends. Target DMA must be stopped before using 237 * this API. 238 */ 239 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 240 void **per_transfer_contextp, 241 u32 *bufferp, 242 unsigned int *nbytesp, 243 unsigned int *transfer_idp); 244 245 /*==================CE Interrupt Handlers====================*/ 246 void ath10k_ce_per_engine_service_any(struct ath10k *ar); 247 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 248 int ath10k_ce_disable_interrupts(struct ath10k *ar); 249 void ath10k_ce_enable_interrupts(struct ath10k *ar); 250 251 /* ce_attr.flags values */ 252 /* Use NonSnooping PCIe accesses? */ 253 #define CE_ATTR_NO_SNOOP 1 254 255 /* Byte swap data words */ 256 #define CE_ATTR_BYTE_SWAP_DATA 2 257 258 /* Swizzle descriptors? */ 259 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4 260 261 /* no interrupt on copy completion */ 262 #define CE_ATTR_DIS_INTR 8 263 264 /* Attributes of an instance of a Copy Engine */ 265 struct ce_attr { 266 /* CE_ATTR_* values */ 267 unsigned int flags; 268 269 /* #entries in source ring - Must be a power of 2 */ 270 unsigned int src_nentries; 271 272 /* 273 * Max source send size for this CE. 274 * This is also the minimum size of a destination buffer. 275 */ 276 unsigned int src_sz_max; 277 278 /* #entries in destination ring - Must be a power of 2 */ 279 unsigned int dest_nentries; 280 }; 281 282 #define SR_BA_ADDRESS 0x0000 283 #define SR_SIZE_ADDRESS 0x0004 284 #define DR_BA_ADDRESS 0x0008 285 #define DR_SIZE_ADDRESS 0x000c 286 #define CE_CMD_ADDRESS 0x0018 287 288 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17 289 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 290 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 291 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 292 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 293 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 294 295 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16 296 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 297 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 298 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \ 299 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \ 300 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 301 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 302 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 303 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 304 305 #define CE_CTRL1_DMAX_LENGTH_MSB 15 306 #define CE_CTRL1_DMAX_LENGTH_LSB 0 307 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 308 #define CE_CTRL1_DMAX_LENGTH_GET(x) \ 309 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB) 310 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 311 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 312 313 #define CE_CTRL1_ADDRESS 0x0010 314 #define CE_CTRL1_HW_MASK 0x0007ffff 315 #define CE_CTRL1_SW_MASK 0x0007ffff 316 #define CE_CTRL1_HW_WRITE_MASK 0x00000000 317 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff 318 #define CE_CTRL1_RSTMASK 0xffffffff 319 #define CE_CTRL1_RESET 0x00000080 320 321 #define CE_CMD_HALT_STATUS_MSB 3 322 #define CE_CMD_HALT_STATUS_LSB 3 323 #define CE_CMD_HALT_STATUS_MASK 0x00000008 324 #define CE_CMD_HALT_STATUS_GET(x) \ 325 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB) 326 #define CE_CMD_HALT_STATUS_SET(x) \ 327 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK) 328 #define CE_CMD_HALT_STATUS_RESET 0 329 #define CE_CMD_HALT_MSB 0 330 #define CE_CMD_HALT_MASK 0x00000001 331 332 #define HOST_IE_COPY_COMPLETE_MSB 0 333 #define HOST_IE_COPY_COMPLETE_LSB 0 334 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001 335 #define HOST_IE_COPY_COMPLETE_GET(x) \ 336 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB) 337 #define HOST_IE_COPY_COMPLETE_SET(x) \ 338 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK) 339 #define HOST_IE_COPY_COMPLETE_RESET 0 340 #define HOST_IE_ADDRESS 0x002c 341 342 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 343 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 344 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 345 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 346 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001 347 #define HOST_IS_ADDRESS 0x0030 348 349 #define MISC_IE_ADDRESS 0x0034 350 351 #define MISC_IS_AXI_ERR_MASK 0x00000400 352 353 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200 354 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100 355 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 356 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 357 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 358 359 #define MISC_IS_ADDRESS 0x0038 360 361 #define SR_WR_INDEX_ADDRESS 0x003c 362 363 #define DST_WR_INDEX_ADDRESS 0x0040 364 365 #define CURRENT_SRRI_ADDRESS 0x0044 366 367 #define CURRENT_DRRI_ADDRESS 0x0048 368 369 #define SRC_WATERMARK_LOW_MSB 31 370 #define SRC_WATERMARK_LOW_LSB 16 371 #define SRC_WATERMARK_LOW_MASK 0xffff0000 372 #define SRC_WATERMARK_LOW_GET(x) \ 373 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB) 374 #define SRC_WATERMARK_LOW_SET(x) \ 375 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 376 #define SRC_WATERMARK_LOW_RESET 0 377 #define SRC_WATERMARK_HIGH_MSB 15 378 #define SRC_WATERMARK_HIGH_LSB 0 379 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff 380 #define SRC_WATERMARK_HIGH_GET(x) \ 381 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB) 382 #define SRC_WATERMARK_HIGH_SET(x) \ 383 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 384 #define SRC_WATERMARK_HIGH_RESET 0 385 #define SRC_WATERMARK_ADDRESS 0x004c 386 387 #define DST_WATERMARK_LOW_LSB 16 388 #define DST_WATERMARK_LOW_MASK 0xffff0000 389 #define DST_WATERMARK_LOW_SET(x) \ 390 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 391 #define DST_WATERMARK_LOW_RESET 0 392 #define DST_WATERMARK_HIGH_MSB 15 393 #define DST_WATERMARK_HIGH_LSB 0 394 #define DST_WATERMARK_HIGH_MASK 0x0000ffff 395 #define DST_WATERMARK_HIGH_GET(x) \ 396 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB) 397 #define DST_WATERMARK_HIGH_SET(x) \ 398 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 399 #define DST_WATERMARK_HIGH_RESET 0 400 #define DST_WATERMARK_ADDRESS 0x0050 401 402 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 403 { 404 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 405 } 406 407 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 408 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 409 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 410 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 411 412 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 413 MISC_IS_DST_ADDR_ERR_MASK | \ 414 MISC_IS_SRC_LEN_ERR_MASK | \ 415 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 416 MISC_IS_DST_RING_OVERFLOW_MASK | \ 417 MISC_IS_SRC_RING_OVERFLOW_MASK) 418 419 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 420 (&(((struct ce_desc *)baddr)[idx])) 421 422 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 423 (&(((struct ce_desc *)baddr)[idx])) 424 425 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 426 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 427 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 428 429 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 430 431 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 432 ar->regs->ce_wrap_intr_sum_host_msi_lsb 433 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 434 ar->regs->ce_wrap_intr_sum_host_msi_mask 435 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 436 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 437 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 438 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 439 440 #define CE_INTERRUPT_SUMMARY(ar) \ 441 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 442 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ 443 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 444 445 #endif /* _CE_H_ */ 446