1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _CE_H_ 19 #define _CE_H_ 20 21 #include "hif.h" 22 23 /* Maximum number of Copy Engine's supported */ 24 #define CE_COUNT_MAX 12 25 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192 26 27 /* Descriptor rings must be aligned to this boundary */ 28 #define CE_DESC_RING_ALIGN 8 29 #define CE_SEND_FLAG_GATHER 0x00010000 30 31 /* 32 * Copy Engine support: low-level Target-side Copy Engine API. 33 * This is a hardware access layer used by code that understands 34 * how to use copy engines. 35 */ 36 37 struct ath10k_ce_pipe; 38 39 #define CE_DESC_FLAGS_GATHER (1 << 0) 40 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 41 42 /* Following desc flags are used in QCA99X0 */ 43 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2) 44 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3) 45 46 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask 47 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb 48 49 struct ce_desc { 50 __le32 addr; 51 __le16 nbytes; 52 __le16 flags; /* %CE_DESC_FLAGS_ */ 53 }; 54 55 struct ath10k_ce_ring { 56 /* Number of entries in this ring; must be power of 2 */ 57 unsigned int nentries; 58 unsigned int nentries_mask; 59 60 /* 61 * For dest ring, this is the next index to be processed 62 * by software after it was/is received into. 63 * 64 * For src ring, this is the last descriptor that was sent 65 * and completion processed by software. 66 * 67 * Regardless of src or dest ring, this is an invariant 68 * (modulo ring size): 69 * write index >= read index >= sw_index 70 */ 71 unsigned int sw_index; 72 /* cached copy */ 73 unsigned int write_index; 74 /* 75 * For src ring, this is the next index not yet processed by HW. 76 * This is a cached copy of the real HW index (read index), used 77 * for avoiding reading the HW index register more often than 78 * necessary. 79 * This extends the invariant: 80 * write index >= read index >= hw_index >= sw_index 81 * 82 * For dest ring, this is currently unused. 83 */ 84 /* cached copy */ 85 unsigned int hw_index; 86 87 /* Start of DMA-coherent area reserved for descriptors */ 88 /* Host address space */ 89 void *base_addr_owner_space_unaligned; 90 /* CE address space */ 91 u32 base_addr_ce_space_unaligned; 92 93 /* 94 * Actual start of descriptors. 95 * Aligned to descriptor-size boundary. 96 * Points into reserved DMA-coherent area, above. 97 */ 98 /* Host address space */ 99 void *base_addr_owner_space; 100 101 /* CE address space */ 102 u32 base_addr_ce_space; 103 104 /* keep last */ 105 void *per_transfer_context[0]; 106 }; 107 108 struct ath10k_ce_pipe { 109 struct ath10k *ar; 110 unsigned int id; 111 112 unsigned int attr_flags; 113 114 u32 ctrl_addr; 115 116 void (*send_cb)(struct ath10k_ce_pipe *); 117 void (*recv_cb)(struct ath10k_ce_pipe *); 118 119 unsigned int src_sz_max; 120 struct ath10k_ce_ring *src_ring; 121 struct ath10k_ce_ring *dest_ring; 122 }; 123 124 /* Copy Engine settable attributes */ 125 struct ce_attr; 126 127 /*==================Send====================*/ 128 129 /* ath10k_ce_send flags */ 130 #define CE_SEND_FLAG_BYTE_SWAP 1 131 132 /* 133 * Queue a source buffer to be sent to an anonymous destination buffer. 134 * ce - which copy engine to use 135 * buffer - address of buffer 136 * nbytes - number of bytes to send 137 * transfer_id - arbitrary ID; reflected to destination 138 * flags - CE_SEND_FLAG_* values 139 * Returns 0 on success; otherwise an error status. 140 * 141 * Note: If no flags are specified, use CE's default data swap mode. 142 * 143 * Implementation note: pushes 1 buffer to Source ring 144 */ 145 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 146 void *per_transfer_send_context, 147 u32 buffer, 148 unsigned int nbytes, 149 /* 14 bits */ 150 unsigned int transfer_id, 151 unsigned int flags); 152 153 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 154 void *per_transfer_context, 155 u32 buffer, 156 unsigned int nbytes, 157 unsigned int transfer_id, 158 unsigned int flags); 159 160 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe); 161 162 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 163 164 /*==================Recv=======================*/ 165 166 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); 167 int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 168 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 169 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries); 170 171 /* recv flags */ 172 /* Data is byte-swapped */ 173 #define CE_RECV_FLAG_SWAPPED 1 174 175 /* 176 * Supply data for the next completed unprocessed receive descriptor. 177 * Pops buffer from Dest ring. 178 */ 179 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 180 void **per_transfer_contextp, 181 unsigned int *nbytesp); 182 /* 183 * Supply data for the next completed unprocessed send descriptor. 184 * Pops 1 completed send buffer from Source ring. 185 */ 186 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 187 void **per_transfer_contextp); 188 189 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 190 void **per_transfer_contextp); 191 192 /*==================CE Engine Initialization=======================*/ 193 194 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 195 const struct ce_attr *attr); 196 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id); 197 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 198 const struct ce_attr *attr); 199 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); 200 201 /*==================CE Engine Shutdown=======================*/ 202 /* 203 * Support clean shutdown by allowing the caller to revoke 204 * receive buffers. Target DMA must be stopped before using 205 * this API. 206 */ 207 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 208 void **per_transfer_contextp, 209 u32 *bufferp); 210 211 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, 212 void **per_transfer_contextp, 213 unsigned int *nbytesp); 214 215 /* 216 * Support clean shutdown by allowing the caller to cancel 217 * pending sends. Target DMA must be stopped before using 218 * this API. 219 */ 220 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 221 void **per_transfer_contextp, 222 u32 *bufferp, 223 unsigned int *nbytesp, 224 unsigned int *transfer_idp); 225 226 /*==================CE Interrupt Handlers====================*/ 227 void ath10k_ce_per_engine_service_any(struct ath10k *ar); 228 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 229 int ath10k_ce_disable_interrupts(struct ath10k *ar); 230 void ath10k_ce_enable_interrupts(struct ath10k *ar); 231 232 /* ce_attr.flags values */ 233 /* Use NonSnooping PCIe accesses? */ 234 #define CE_ATTR_NO_SNOOP 1 235 236 /* Byte swap data words */ 237 #define CE_ATTR_BYTE_SWAP_DATA 2 238 239 /* Swizzle descriptors? */ 240 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4 241 242 /* no interrupt on copy completion */ 243 #define CE_ATTR_DIS_INTR 8 244 245 /* Attributes of an instance of a Copy Engine */ 246 struct ce_attr { 247 /* CE_ATTR_* values */ 248 unsigned int flags; 249 250 /* #entries in source ring - Must be a power of 2 */ 251 unsigned int src_nentries; 252 253 /* 254 * Max source send size for this CE. 255 * This is also the minimum size of a destination buffer. 256 */ 257 unsigned int src_sz_max; 258 259 /* #entries in destination ring - Must be a power of 2 */ 260 unsigned int dest_nentries; 261 262 void (*send_cb)(struct ath10k_ce_pipe *); 263 void (*recv_cb)(struct ath10k_ce_pipe *); 264 }; 265 266 #define SR_BA_ADDRESS 0x0000 267 #define SR_SIZE_ADDRESS 0x0004 268 #define DR_BA_ADDRESS 0x0008 269 #define DR_SIZE_ADDRESS 0x000c 270 #define CE_CMD_ADDRESS 0x0018 271 272 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17 273 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 274 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 275 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 276 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 277 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 278 279 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16 280 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 281 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 282 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \ 283 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \ 284 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 285 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 286 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 287 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 288 289 #define CE_CTRL1_DMAX_LENGTH_MSB 15 290 #define CE_CTRL1_DMAX_LENGTH_LSB 0 291 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 292 #define CE_CTRL1_DMAX_LENGTH_GET(x) \ 293 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB) 294 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 295 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 296 297 #define CE_CTRL1_ADDRESS 0x0010 298 #define CE_CTRL1_HW_MASK 0x0007ffff 299 #define CE_CTRL1_SW_MASK 0x0007ffff 300 #define CE_CTRL1_HW_WRITE_MASK 0x00000000 301 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff 302 #define CE_CTRL1_RSTMASK 0xffffffff 303 #define CE_CTRL1_RESET 0x00000080 304 305 #define CE_CMD_HALT_STATUS_MSB 3 306 #define CE_CMD_HALT_STATUS_LSB 3 307 #define CE_CMD_HALT_STATUS_MASK 0x00000008 308 #define CE_CMD_HALT_STATUS_GET(x) \ 309 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB) 310 #define CE_CMD_HALT_STATUS_SET(x) \ 311 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK) 312 #define CE_CMD_HALT_STATUS_RESET 0 313 #define CE_CMD_HALT_MSB 0 314 #define CE_CMD_HALT_MASK 0x00000001 315 316 #define HOST_IE_COPY_COMPLETE_MSB 0 317 #define HOST_IE_COPY_COMPLETE_LSB 0 318 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001 319 #define HOST_IE_COPY_COMPLETE_GET(x) \ 320 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB) 321 #define HOST_IE_COPY_COMPLETE_SET(x) \ 322 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK) 323 #define HOST_IE_COPY_COMPLETE_RESET 0 324 #define HOST_IE_ADDRESS 0x002c 325 326 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 327 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 328 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 329 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 330 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001 331 #define HOST_IS_ADDRESS 0x0030 332 333 #define MISC_IE_ADDRESS 0x0034 334 335 #define MISC_IS_AXI_ERR_MASK 0x00000400 336 337 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200 338 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100 339 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 340 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 341 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 342 343 #define MISC_IS_ADDRESS 0x0038 344 345 #define SR_WR_INDEX_ADDRESS 0x003c 346 347 #define DST_WR_INDEX_ADDRESS 0x0040 348 349 #define CURRENT_SRRI_ADDRESS 0x0044 350 351 #define CURRENT_DRRI_ADDRESS 0x0048 352 353 #define SRC_WATERMARK_LOW_MSB 31 354 #define SRC_WATERMARK_LOW_LSB 16 355 #define SRC_WATERMARK_LOW_MASK 0xffff0000 356 #define SRC_WATERMARK_LOW_GET(x) \ 357 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB) 358 #define SRC_WATERMARK_LOW_SET(x) \ 359 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 360 #define SRC_WATERMARK_LOW_RESET 0 361 #define SRC_WATERMARK_HIGH_MSB 15 362 #define SRC_WATERMARK_HIGH_LSB 0 363 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff 364 #define SRC_WATERMARK_HIGH_GET(x) \ 365 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB) 366 #define SRC_WATERMARK_HIGH_SET(x) \ 367 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 368 #define SRC_WATERMARK_HIGH_RESET 0 369 #define SRC_WATERMARK_ADDRESS 0x004c 370 371 #define DST_WATERMARK_LOW_LSB 16 372 #define DST_WATERMARK_LOW_MASK 0xffff0000 373 #define DST_WATERMARK_LOW_SET(x) \ 374 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 375 #define DST_WATERMARK_LOW_RESET 0 376 #define DST_WATERMARK_HIGH_MSB 15 377 #define DST_WATERMARK_HIGH_LSB 0 378 #define DST_WATERMARK_HIGH_MASK 0x0000ffff 379 #define DST_WATERMARK_HIGH_GET(x) \ 380 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB) 381 #define DST_WATERMARK_HIGH_SET(x) \ 382 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 383 #define DST_WATERMARK_HIGH_RESET 0 384 #define DST_WATERMARK_ADDRESS 0x0050 385 386 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 387 { 388 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 389 } 390 391 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 392 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 393 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 394 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 395 396 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 397 MISC_IS_DST_ADDR_ERR_MASK | \ 398 MISC_IS_SRC_LEN_ERR_MASK | \ 399 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 400 MISC_IS_DST_RING_OVERFLOW_MASK | \ 401 MISC_IS_SRC_RING_OVERFLOW_MASK) 402 403 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 404 (&(((struct ce_desc *)baddr)[idx])) 405 406 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 407 (&(((struct ce_desc *)baddr)[idx])) 408 409 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 410 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 411 (((int)(toidx) - (int)(fromidx)) & (nentries_mask)) 412 413 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 414 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 415 (((idx) + (num)) & (nentries_mask)) 416 417 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 418 ar->regs->ce_wrap_intr_sum_host_msi_lsb 419 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 420 ar->regs->ce_wrap_intr_sum_host_msi_mask 421 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 422 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 423 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 424 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 425 426 #define CE_INTERRUPT_SUMMARY(ar) \ 427 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 428 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ 429 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 430 431 #endif /* _CE_H_ */ 432