1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "hif.h" 19 #include "pci.h" 20 #include "ce.h" 21 #include "debug.h" 22 23 /* 24 * Support for Copy Engine hardware, which is mainly used for 25 * communication between Host and Target over a PCIe interconnect. 26 */ 27 28 /* 29 * A single CopyEngine (CE) comprises two "rings": 30 * a source ring 31 * a destination ring 32 * 33 * Each ring consists of a number of descriptors which specify 34 * an address, length, and meta-data. 35 * 36 * Typically, one side of the PCIe interconnect (Host or Target) 37 * controls one ring and the other side controls the other ring. 38 * The source side chooses when to initiate a transfer and it 39 * chooses what to send (buffer address, length). The destination 40 * side keeps a supply of "anonymous receive buffers" available and 41 * it handles incoming data as it arrives (when the destination 42 * recieves an interrupt). 43 * 44 * The sender may send a simple buffer (address/length) or it may 45 * send a small list of buffers. When a small list is sent, hardware 46 * "gathers" these and they end up in a single destination buffer 47 * with a single interrupt. 48 * 49 * There are several "contexts" managed by this layer -- more, it 50 * may seem -- than should be needed. These are provided mainly for 51 * maximum flexibility and especially to facilitate a simpler HIF 52 * implementation. There are per-CopyEngine recv, send, and watermark 53 * contexts. These are supplied by the caller when a recv, send, 54 * or watermark handler is established and they are echoed back to 55 * the caller when the respective callbacks are invoked. There is 56 * also a per-transfer context supplied by the caller when a buffer 57 * (or sendlist) is sent and when a buffer is enqueued for recv. 58 * These per-transfer contexts are echoed back to the caller when 59 * the buffer is sent/received. 60 */ 61 62 static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, 63 u32 ce_ctrl_addr, 64 unsigned int n) 65 { 66 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n); 67 } 68 69 static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar, 70 u32 ce_ctrl_addr) 71 { 72 return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS); 73 } 74 75 static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar, 76 u32 ce_ctrl_addr, 77 unsigned int n) 78 { 79 ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n); 80 } 81 82 static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar, 83 u32 ce_ctrl_addr) 84 { 85 return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS); 86 } 87 88 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar, 89 u32 ce_ctrl_addr) 90 { 91 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS); 92 } 93 94 static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar, 95 u32 ce_ctrl_addr, 96 unsigned int addr) 97 { 98 ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr); 99 } 100 101 static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar, 102 u32 ce_ctrl_addr, 103 unsigned int n) 104 { 105 ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n); 106 } 107 108 static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar, 109 u32 ce_ctrl_addr, 110 unsigned int n) 111 { 112 u32 ctrl1_addr = ath10k_pci_read32((ar), 113 (ce_ctrl_addr) + CE_CTRL1_ADDRESS); 114 115 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, 116 (ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) | 117 CE_CTRL1_DMAX_LENGTH_SET(n)); 118 } 119 120 static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, 121 u32 ce_ctrl_addr, 122 unsigned int n) 123 { 124 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); 125 126 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, 127 (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | 128 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)); 129 } 130 131 static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 132 u32 ce_ctrl_addr, 133 unsigned int n) 134 { 135 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); 136 137 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, 138 (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | 139 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)); 140 } 141 142 static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, 143 u32 ce_ctrl_addr) 144 { 145 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS); 146 } 147 148 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar, 149 u32 ce_ctrl_addr, 150 u32 addr) 151 { 152 ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr); 153 } 154 155 static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar, 156 u32 ce_ctrl_addr, 157 unsigned int n) 158 { 159 ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n); 160 } 161 162 static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, 163 u32 ce_ctrl_addr, 164 unsigned int n) 165 { 166 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); 167 168 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, 169 (addr & ~SRC_WATERMARK_HIGH_MASK) | 170 SRC_WATERMARK_HIGH_SET(n)); 171 } 172 173 static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, 174 u32 ce_ctrl_addr, 175 unsigned int n) 176 { 177 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); 178 179 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, 180 (addr & ~SRC_WATERMARK_LOW_MASK) | 181 SRC_WATERMARK_LOW_SET(n)); 182 } 183 184 static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, 185 u32 ce_ctrl_addr, 186 unsigned int n) 187 { 188 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); 189 190 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, 191 (addr & ~DST_WATERMARK_HIGH_MASK) | 192 DST_WATERMARK_HIGH_SET(n)); 193 } 194 195 static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 196 u32 ce_ctrl_addr, 197 unsigned int n) 198 { 199 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); 200 201 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, 202 (addr & ~DST_WATERMARK_LOW_MASK) | 203 DST_WATERMARK_LOW_SET(n)); 204 } 205 206 static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar, 207 u32 ce_ctrl_addr) 208 { 209 u32 host_ie_addr = ath10k_pci_read32(ar, 210 ce_ctrl_addr + HOST_IE_ADDRESS); 211 212 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, 213 host_ie_addr | HOST_IE_COPY_COMPLETE_MASK); 214 } 215 216 static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar, 217 u32 ce_ctrl_addr) 218 { 219 u32 host_ie_addr = ath10k_pci_read32(ar, 220 ce_ctrl_addr + HOST_IE_ADDRESS); 221 222 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, 223 host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK); 224 } 225 226 static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar, 227 u32 ce_ctrl_addr) 228 { 229 u32 host_ie_addr = ath10k_pci_read32(ar, 230 ce_ctrl_addr + HOST_IE_ADDRESS); 231 232 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, 233 host_ie_addr & ~CE_WATERMARK_MASK); 234 } 235 236 static inline void ath10k_ce_error_intr_enable(struct ath10k *ar, 237 u32 ce_ctrl_addr) 238 { 239 u32 misc_ie_addr = ath10k_pci_read32(ar, 240 ce_ctrl_addr + MISC_IE_ADDRESS); 241 242 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, 243 misc_ie_addr | CE_ERROR_MASK); 244 } 245 246 static inline void ath10k_ce_error_intr_disable(struct ath10k *ar, 247 u32 ce_ctrl_addr) 248 { 249 u32 misc_ie_addr = ath10k_pci_read32(ar, 250 ce_ctrl_addr + MISC_IE_ADDRESS); 251 252 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, 253 misc_ie_addr & ~CE_ERROR_MASK); 254 } 255 256 static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, 257 u32 ce_ctrl_addr, 258 unsigned int mask) 259 { 260 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask); 261 } 262 263 /* 264 * Guts of ath10k_ce_send, used by both ath10k_ce_send and 265 * ath10k_ce_sendlist_send. 266 * The caller takes responsibility for any needed locking. 267 */ 268 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 269 void *per_transfer_context, 270 u32 buffer, 271 unsigned int nbytes, 272 unsigned int transfer_id, 273 unsigned int flags) 274 { 275 struct ath10k *ar = ce_state->ar; 276 struct ath10k_ce_ring *src_ring = ce_state->src_ring; 277 struct ce_desc *desc, sdesc; 278 unsigned int nentries_mask = src_ring->nentries_mask; 279 unsigned int sw_index = src_ring->sw_index; 280 unsigned int write_index = src_ring->write_index; 281 u32 ctrl_addr = ce_state->ctrl_addr; 282 u32 desc_flags = 0; 283 int ret = 0; 284 285 if (nbytes > ce_state->src_sz_max) 286 ath10k_warn(ar, "%s: send more we can (nbytes: %d, max: %d)\n", 287 __func__, nbytes, ce_state->src_sz_max); 288 289 if (unlikely(CE_RING_DELTA(nentries_mask, 290 write_index, sw_index - 1) <= 0)) { 291 ret = -ENOSR; 292 goto exit; 293 } 294 295 desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space, 296 write_index); 297 298 desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA); 299 300 if (flags & CE_SEND_FLAG_GATHER) 301 desc_flags |= CE_DESC_FLAGS_GATHER; 302 if (flags & CE_SEND_FLAG_BYTE_SWAP) 303 desc_flags |= CE_DESC_FLAGS_BYTE_SWAP; 304 305 sdesc.addr = __cpu_to_le32(buffer); 306 sdesc.nbytes = __cpu_to_le16(nbytes); 307 sdesc.flags = __cpu_to_le16(desc_flags); 308 309 *desc = sdesc; 310 311 src_ring->per_transfer_context[write_index] = per_transfer_context; 312 313 /* Update Source Ring Write Index */ 314 write_index = CE_RING_IDX_INCR(nentries_mask, write_index); 315 316 /* WORKAROUND */ 317 if (!(flags & CE_SEND_FLAG_GATHER)) 318 ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index); 319 320 src_ring->write_index = write_index; 321 exit: 322 return ret; 323 } 324 325 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe) 326 { 327 struct ath10k *ar = pipe->ar; 328 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 329 struct ath10k_ce_ring *src_ring = pipe->src_ring; 330 u32 ctrl_addr = pipe->ctrl_addr; 331 332 lockdep_assert_held(&ar_pci->ce_lock); 333 334 /* 335 * This function must be called only if there is an incomplete 336 * scatter-gather transfer (before index register is updated) 337 * that needs to be cleaned up. 338 */ 339 if (WARN_ON_ONCE(src_ring->write_index == src_ring->sw_index)) 340 return; 341 342 if (WARN_ON_ONCE(src_ring->write_index == 343 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr))) 344 return; 345 346 src_ring->write_index--; 347 src_ring->write_index &= src_ring->nentries_mask; 348 349 src_ring->per_transfer_context[src_ring->write_index] = NULL; 350 } 351 352 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 353 void *per_transfer_context, 354 u32 buffer, 355 unsigned int nbytes, 356 unsigned int transfer_id, 357 unsigned int flags) 358 { 359 struct ath10k *ar = ce_state->ar; 360 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 361 int ret; 362 363 spin_lock_bh(&ar_pci->ce_lock); 364 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context, 365 buffer, nbytes, transfer_id, flags); 366 spin_unlock_bh(&ar_pci->ce_lock); 367 368 return ret; 369 } 370 371 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) 372 { 373 struct ath10k *ar = pipe->ar; 374 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 375 int delta; 376 377 spin_lock_bh(&ar_pci->ce_lock); 378 delta = CE_RING_DELTA(pipe->src_ring->nentries_mask, 379 pipe->src_ring->write_index, 380 pipe->src_ring->sw_index - 1); 381 spin_unlock_bh(&ar_pci->ce_lock); 382 383 return delta; 384 } 385 386 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe) 387 { 388 struct ath10k *ar = pipe->ar; 389 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 390 struct ath10k_ce_ring *dest_ring = pipe->dest_ring; 391 unsigned int nentries_mask = dest_ring->nentries_mask; 392 unsigned int write_index = dest_ring->write_index; 393 unsigned int sw_index = dest_ring->sw_index; 394 395 lockdep_assert_held(&ar_pci->ce_lock); 396 397 return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); 398 } 399 400 int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) 401 { 402 struct ath10k *ar = pipe->ar; 403 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 404 struct ath10k_ce_ring *dest_ring = pipe->dest_ring; 405 unsigned int nentries_mask = dest_ring->nentries_mask; 406 unsigned int write_index = dest_ring->write_index; 407 unsigned int sw_index = dest_ring->sw_index; 408 struct ce_desc *base = dest_ring->base_addr_owner_space; 409 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index); 410 u32 ctrl_addr = pipe->ctrl_addr; 411 412 lockdep_assert_held(&ar_pci->ce_lock); 413 414 if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0) 415 return -ENOSPC; 416 417 desc->addr = __cpu_to_le32(paddr); 418 desc->nbytes = 0; 419 420 dest_ring->per_transfer_context[write_index] = ctx; 421 write_index = CE_RING_IDX_INCR(nentries_mask, write_index); 422 ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index); 423 dest_ring->write_index = write_index; 424 425 return 0; 426 } 427 428 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) 429 { 430 struct ath10k *ar = pipe->ar; 431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 432 int ret; 433 434 spin_lock_bh(&ar_pci->ce_lock); 435 ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr); 436 spin_unlock_bh(&ar_pci->ce_lock); 437 438 return ret; 439 } 440 441 /* 442 * Guts of ath10k_ce_completed_recv_next. 443 * The caller takes responsibility for any necessary locking. 444 */ 445 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, 446 void **per_transfer_contextp, 447 u32 *bufferp, 448 unsigned int *nbytesp, 449 unsigned int *transfer_idp, 450 unsigned int *flagsp) 451 { 452 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; 453 unsigned int nentries_mask = dest_ring->nentries_mask; 454 struct ath10k *ar = ce_state->ar; 455 unsigned int sw_index = dest_ring->sw_index; 456 457 struct ce_desc *base = dest_ring->base_addr_owner_space; 458 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); 459 struct ce_desc sdesc; 460 u16 nbytes; 461 462 /* Copy in one go for performance reasons */ 463 sdesc = *desc; 464 465 nbytes = __le16_to_cpu(sdesc.nbytes); 466 if (nbytes == 0) { 467 /* 468 * This closes a relatively unusual race where the Host 469 * sees the updated DRRI before the update to the 470 * corresponding descriptor has completed. We treat this 471 * as a descriptor that is not yet done. 472 */ 473 return -EIO; 474 } 475 476 desc->nbytes = 0; 477 478 /* Return data from completed destination descriptor */ 479 *bufferp = __le32_to_cpu(sdesc.addr); 480 *nbytesp = nbytes; 481 *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA); 482 483 if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP) 484 *flagsp = CE_RECV_FLAG_SWAPPED; 485 else 486 *flagsp = 0; 487 488 if (per_transfer_contextp) 489 *per_transfer_contextp = 490 dest_ring->per_transfer_context[sw_index]; 491 492 /* sanity */ 493 dest_ring->per_transfer_context[sw_index] = NULL; 494 495 /* Update sw_index */ 496 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 497 dest_ring->sw_index = sw_index; 498 499 return 0; 500 } 501 502 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 503 void **per_transfer_contextp, 504 u32 *bufferp, 505 unsigned int *nbytesp, 506 unsigned int *transfer_idp, 507 unsigned int *flagsp) 508 { 509 struct ath10k *ar = ce_state->ar; 510 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 511 int ret; 512 513 spin_lock_bh(&ar_pci->ce_lock); 514 ret = ath10k_ce_completed_recv_next_nolock(ce_state, 515 per_transfer_contextp, 516 bufferp, nbytesp, 517 transfer_idp, flagsp); 518 spin_unlock_bh(&ar_pci->ce_lock); 519 520 return ret; 521 } 522 523 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 524 void **per_transfer_contextp, 525 u32 *bufferp) 526 { 527 struct ath10k_ce_ring *dest_ring; 528 unsigned int nentries_mask; 529 unsigned int sw_index; 530 unsigned int write_index; 531 int ret; 532 struct ath10k *ar; 533 struct ath10k_pci *ar_pci; 534 535 dest_ring = ce_state->dest_ring; 536 537 if (!dest_ring) 538 return -EIO; 539 540 ar = ce_state->ar; 541 ar_pci = ath10k_pci_priv(ar); 542 543 spin_lock_bh(&ar_pci->ce_lock); 544 545 nentries_mask = dest_ring->nentries_mask; 546 sw_index = dest_ring->sw_index; 547 write_index = dest_ring->write_index; 548 if (write_index != sw_index) { 549 struct ce_desc *base = dest_ring->base_addr_owner_space; 550 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); 551 552 /* Return data from completed destination descriptor */ 553 *bufferp = __le32_to_cpu(desc->addr); 554 555 if (per_transfer_contextp) 556 *per_transfer_contextp = 557 dest_ring->per_transfer_context[sw_index]; 558 559 /* sanity */ 560 dest_ring->per_transfer_context[sw_index] = NULL; 561 desc->nbytes = 0; 562 563 /* Update sw_index */ 564 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 565 dest_ring->sw_index = sw_index; 566 ret = 0; 567 } else { 568 ret = -EIO; 569 } 570 571 spin_unlock_bh(&ar_pci->ce_lock); 572 573 return ret; 574 } 575 576 /* 577 * Guts of ath10k_ce_completed_send_next. 578 * The caller takes responsibility for any necessary locking. 579 */ 580 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 581 void **per_transfer_contextp) 582 { 583 struct ath10k_ce_ring *src_ring = ce_state->src_ring; 584 u32 ctrl_addr = ce_state->ctrl_addr; 585 struct ath10k *ar = ce_state->ar; 586 unsigned int nentries_mask = src_ring->nentries_mask; 587 unsigned int sw_index = src_ring->sw_index; 588 unsigned int read_index; 589 590 if (src_ring->hw_index == sw_index) { 591 /* 592 * The SW completion index has caught up with the cached 593 * version of the HW completion index. 594 * Update the cached HW completion index to see whether 595 * the SW has really caught up to the HW, or if the cached 596 * value of the HW index has become stale. 597 */ 598 599 read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr); 600 if (read_index == 0xffffffff) 601 return -ENODEV; 602 603 read_index &= nentries_mask; 604 src_ring->hw_index = read_index; 605 } 606 607 read_index = src_ring->hw_index; 608 609 if (read_index == sw_index) 610 return -EIO; 611 612 if (per_transfer_contextp) 613 *per_transfer_contextp = 614 src_ring->per_transfer_context[sw_index]; 615 616 /* sanity */ 617 src_ring->per_transfer_context[sw_index] = NULL; 618 619 /* Update sw_index */ 620 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 621 src_ring->sw_index = sw_index; 622 623 return 0; 624 } 625 626 /* NB: Modeled after ath10k_ce_completed_send_next */ 627 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 628 void **per_transfer_contextp, 629 u32 *bufferp, 630 unsigned int *nbytesp, 631 unsigned int *transfer_idp) 632 { 633 struct ath10k_ce_ring *src_ring; 634 unsigned int nentries_mask; 635 unsigned int sw_index; 636 unsigned int write_index; 637 int ret; 638 struct ath10k *ar; 639 struct ath10k_pci *ar_pci; 640 641 src_ring = ce_state->src_ring; 642 643 if (!src_ring) 644 return -EIO; 645 646 ar = ce_state->ar; 647 ar_pci = ath10k_pci_priv(ar); 648 649 spin_lock_bh(&ar_pci->ce_lock); 650 651 nentries_mask = src_ring->nentries_mask; 652 sw_index = src_ring->sw_index; 653 write_index = src_ring->write_index; 654 655 if (write_index != sw_index) { 656 struct ce_desc *base = src_ring->base_addr_owner_space; 657 struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index); 658 659 /* Return data from completed source descriptor */ 660 *bufferp = __le32_to_cpu(desc->addr); 661 *nbytesp = __le16_to_cpu(desc->nbytes); 662 *transfer_idp = MS(__le16_to_cpu(desc->flags), 663 CE_DESC_FLAGS_META_DATA); 664 665 if (per_transfer_contextp) 666 *per_transfer_contextp = 667 src_ring->per_transfer_context[sw_index]; 668 669 /* sanity */ 670 src_ring->per_transfer_context[sw_index] = NULL; 671 672 /* Update sw_index */ 673 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); 674 src_ring->sw_index = sw_index; 675 ret = 0; 676 } else { 677 ret = -EIO; 678 } 679 680 spin_unlock_bh(&ar_pci->ce_lock); 681 682 return ret; 683 } 684 685 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 686 void **per_transfer_contextp) 687 { 688 struct ath10k *ar = ce_state->ar; 689 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 690 int ret; 691 692 spin_lock_bh(&ar_pci->ce_lock); 693 ret = ath10k_ce_completed_send_next_nolock(ce_state, 694 per_transfer_contextp); 695 spin_unlock_bh(&ar_pci->ce_lock); 696 697 return ret; 698 } 699 700 /* 701 * Guts of interrupt handler for per-engine interrupts on a particular CE. 702 * 703 * Invokes registered callbacks for recv_complete, 704 * send_complete, and watermarks. 705 */ 706 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 707 { 708 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 709 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; 710 u32 ctrl_addr = ce_state->ctrl_addr; 711 712 spin_lock_bh(&ar_pci->ce_lock); 713 714 /* Clear the copy-complete interrupts that will be handled here. */ 715 ath10k_ce_engine_int_status_clear(ar, ctrl_addr, 716 HOST_IS_COPY_COMPLETE_MASK); 717 718 spin_unlock_bh(&ar_pci->ce_lock); 719 720 if (ce_state->recv_cb) 721 ce_state->recv_cb(ce_state); 722 723 if (ce_state->send_cb) 724 ce_state->send_cb(ce_state); 725 726 spin_lock_bh(&ar_pci->ce_lock); 727 728 /* 729 * Misc CE interrupts are not being handled, but still need 730 * to be cleared. 731 */ 732 ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK); 733 734 spin_unlock_bh(&ar_pci->ce_lock); 735 } 736 737 /* 738 * Handler for per-engine interrupts on ALL active CEs. 739 * This is used in cases where the system is sharing a 740 * single interrput for all CEs 741 */ 742 743 void ath10k_ce_per_engine_service_any(struct ath10k *ar) 744 { 745 int ce_id; 746 u32 intr_summary; 747 748 intr_summary = CE_INTERRUPT_SUMMARY(ar); 749 750 for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) { 751 if (intr_summary & (1 << ce_id)) 752 intr_summary &= ~(1 << ce_id); 753 else 754 /* no intr pending on this CE */ 755 continue; 756 757 ath10k_ce_per_engine_service(ar, ce_id); 758 } 759 } 760 761 /* 762 * Adjust interrupts for the copy complete handler. 763 * If it's needed for either send or recv, then unmask 764 * this interrupt; otherwise, mask it. 765 * 766 * Called with ce_lock held. 767 */ 768 static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state) 769 { 770 u32 ctrl_addr = ce_state->ctrl_addr; 771 struct ath10k *ar = ce_state->ar; 772 bool disable_copy_compl_intr = ce_state->attr_flags & CE_ATTR_DIS_INTR; 773 774 if ((!disable_copy_compl_intr) && 775 (ce_state->send_cb || ce_state->recv_cb)) 776 ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr); 777 else 778 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr); 779 780 ath10k_ce_watermark_intr_disable(ar, ctrl_addr); 781 } 782 783 int ath10k_ce_disable_interrupts(struct ath10k *ar) 784 { 785 int ce_id; 786 787 for (ce_id = 0; ce_id < CE_COUNT; ce_id++) { 788 u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id); 789 790 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr); 791 ath10k_ce_error_intr_disable(ar, ctrl_addr); 792 ath10k_ce_watermark_intr_disable(ar, ctrl_addr); 793 } 794 795 return 0; 796 } 797 798 void ath10k_ce_enable_interrupts(struct ath10k *ar) 799 { 800 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 801 int ce_id; 802 803 /* Skip the last copy engine, CE7 the diagnostic window, as that 804 * uses polling and isn't initialized for interrupts. 805 */ 806 for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++) 807 ath10k_ce_per_engine_handler_adjust(&ar_pci->ce_states[ce_id]); 808 } 809 810 static int ath10k_ce_init_src_ring(struct ath10k *ar, 811 unsigned int ce_id, 812 const struct ce_attr *attr) 813 { 814 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 815 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; 816 struct ath10k_ce_ring *src_ring = ce_state->src_ring; 817 u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); 818 819 nentries = roundup_pow_of_two(attr->src_nentries); 820 821 memset(src_ring->base_addr_owner_space, 0, 822 nentries * sizeof(struct ce_desc)); 823 824 src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr); 825 src_ring->sw_index &= src_ring->nentries_mask; 826 src_ring->hw_index = src_ring->sw_index; 827 828 src_ring->write_index = 829 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr); 830 src_ring->write_index &= src_ring->nentries_mask; 831 832 ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr, 833 src_ring->base_addr_ce_space); 834 ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries); 835 ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max); 836 ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0); 837 ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0); 838 ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries); 839 840 ath10k_dbg(ar, ATH10K_DBG_BOOT, 841 "boot init ce src ring id %d entries %d base_addr %p\n", 842 ce_id, nentries, src_ring->base_addr_owner_space); 843 844 return 0; 845 } 846 847 static int ath10k_ce_init_dest_ring(struct ath10k *ar, 848 unsigned int ce_id, 849 const struct ce_attr *attr) 850 { 851 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 852 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; 853 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; 854 u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); 855 856 nentries = roundup_pow_of_two(attr->dest_nentries); 857 858 memset(dest_ring->base_addr_owner_space, 0, 859 nentries * sizeof(struct ce_desc)); 860 861 dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr); 862 dest_ring->sw_index &= dest_ring->nentries_mask; 863 dest_ring->write_index = 864 ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr); 865 dest_ring->write_index &= dest_ring->nentries_mask; 866 867 ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr, 868 dest_ring->base_addr_ce_space); 869 ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries); 870 ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0); 871 ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0); 872 ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries); 873 874 ath10k_dbg(ar, ATH10K_DBG_BOOT, 875 "boot ce dest ring id %d entries %d base_addr %p\n", 876 ce_id, nentries, dest_ring->base_addr_owner_space); 877 878 return 0; 879 } 880 881 static struct ath10k_ce_ring * 882 ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id, 883 const struct ce_attr *attr) 884 { 885 struct ath10k_ce_ring *src_ring; 886 u32 nentries = attr->src_nentries; 887 dma_addr_t base_addr; 888 889 nentries = roundup_pow_of_two(nentries); 890 891 src_ring = kzalloc(sizeof(*src_ring) + 892 (nentries * 893 sizeof(*src_ring->per_transfer_context)), 894 GFP_KERNEL); 895 if (src_ring == NULL) 896 return ERR_PTR(-ENOMEM); 897 898 src_ring->nentries = nentries; 899 src_ring->nentries_mask = nentries - 1; 900 901 /* 902 * Legacy platforms that do not support cache 903 * coherent DMA are unsupported 904 */ 905 src_ring->base_addr_owner_space_unaligned = 906 dma_alloc_coherent(ar->dev, 907 (nentries * sizeof(struct ce_desc) + 908 CE_DESC_RING_ALIGN), 909 &base_addr, GFP_KERNEL); 910 if (!src_ring->base_addr_owner_space_unaligned) { 911 kfree(src_ring); 912 return ERR_PTR(-ENOMEM); 913 } 914 915 src_ring->base_addr_ce_space_unaligned = base_addr; 916 917 src_ring->base_addr_owner_space = PTR_ALIGN( 918 src_ring->base_addr_owner_space_unaligned, 919 CE_DESC_RING_ALIGN); 920 src_ring->base_addr_ce_space = ALIGN( 921 src_ring->base_addr_ce_space_unaligned, 922 CE_DESC_RING_ALIGN); 923 924 return src_ring; 925 } 926 927 static struct ath10k_ce_ring * 928 ath10k_ce_alloc_dest_ring(struct ath10k *ar, unsigned int ce_id, 929 const struct ce_attr *attr) 930 { 931 struct ath10k_ce_ring *dest_ring; 932 u32 nentries; 933 dma_addr_t base_addr; 934 935 nentries = roundup_pow_of_two(attr->dest_nentries); 936 937 dest_ring = kzalloc(sizeof(*dest_ring) + 938 (nentries * 939 sizeof(*dest_ring->per_transfer_context)), 940 GFP_KERNEL); 941 if (dest_ring == NULL) 942 return ERR_PTR(-ENOMEM); 943 944 dest_ring->nentries = nentries; 945 dest_ring->nentries_mask = nentries - 1; 946 947 /* 948 * Legacy platforms that do not support cache 949 * coherent DMA are unsupported 950 */ 951 dest_ring->base_addr_owner_space_unaligned = 952 dma_alloc_coherent(ar->dev, 953 (nentries * sizeof(struct ce_desc) + 954 CE_DESC_RING_ALIGN), 955 &base_addr, GFP_KERNEL); 956 if (!dest_ring->base_addr_owner_space_unaligned) { 957 kfree(dest_ring); 958 return ERR_PTR(-ENOMEM); 959 } 960 961 dest_ring->base_addr_ce_space_unaligned = base_addr; 962 963 /* 964 * Correctly initialize memory to 0 to prevent garbage 965 * data crashing system when download firmware 966 */ 967 memset(dest_ring->base_addr_owner_space_unaligned, 0, 968 nentries * sizeof(struct ce_desc) + CE_DESC_RING_ALIGN); 969 970 dest_ring->base_addr_owner_space = PTR_ALIGN( 971 dest_ring->base_addr_owner_space_unaligned, 972 CE_DESC_RING_ALIGN); 973 dest_ring->base_addr_ce_space = ALIGN( 974 dest_ring->base_addr_ce_space_unaligned, 975 CE_DESC_RING_ALIGN); 976 977 return dest_ring; 978 } 979 980 /* 981 * Initialize a Copy Engine based on caller-supplied attributes. 982 * This may be called once to initialize both source and destination 983 * rings or it may be called twice for separate source and destination 984 * initialization. It may be that only one side or the other is 985 * initialized by software/firmware. 986 */ 987 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 988 const struct ce_attr *attr) 989 { 990 int ret; 991 992 if (attr->src_nentries) { 993 ret = ath10k_ce_init_src_ring(ar, ce_id, attr); 994 if (ret) { 995 ath10k_err(ar, "Failed to initialize CE src ring for ID: %d (%d)\n", 996 ce_id, ret); 997 return ret; 998 } 999 } 1000 1001 if (attr->dest_nentries) { 1002 ret = ath10k_ce_init_dest_ring(ar, ce_id, attr); 1003 if (ret) { 1004 ath10k_err(ar, "Failed to initialize CE dest ring for ID: %d (%d)\n", 1005 ce_id, ret); 1006 return ret; 1007 } 1008 } 1009 1010 return 0; 1011 } 1012 1013 static void ath10k_ce_deinit_src_ring(struct ath10k *ar, unsigned int ce_id) 1014 { 1015 u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id); 1016 1017 ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr, 0); 1018 ath10k_ce_src_ring_size_set(ar, ctrl_addr, 0); 1019 ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, 0); 1020 ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, 0); 1021 } 1022 1023 static void ath10k_ce_deinit_dest_ring(struct ath10k *ar, unsigned int ce_id) 1024 { 1025 u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id); 1026 1027 ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr, 0); 1028 ath10k_ce_dest_ring_size_set(ar, ctrl_addr, 0); 1029 ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, 0); 1030 } 1031 1032 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id) 1033 { 1034 ath10k_ce_deinit_src_ring(ar, ce_id); 1035 ath10k_ce_deinit_dest_ring(ar, ce_id); 1036 } 1037 1038 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 1039 const struct ce_attr *attr) 1040 { 1041 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1042 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; 1043 int ret; 1044 1045 /* 1046 * Make sure there's enough CE ringbuffer entries for HTT TX to avoid 1047 * additional TX locking checks. 1048 * 1049 * For the lack of a better place do the check here. 1050 */ 1051 BUILD_BUG_ON(2*TARGET_NUM_MSDU_DESC > 1052 (CE_HTT_H2T_MSG_SRC_NENTRIES - 1)); 1053 BUILD_BUG_ON(2*TARGET_10X_NUM_MSDU_DESC > 1054 (CE_HTT_H2T_MSG_SRC_NENTRIES - 1)); 1055 BUILD_BUG_ON(2*TARGET_TLV_NUM_MSDU_DESC > 1056 (CE_HTT_H2T_MSG_SRC_NENTRIES - 1)); 1057 1058 ce_state->ar = ar; 1059 ce_state->id = ce_id; 1060 ce_state->ctrl_addr = ath10k_ce_base_address(ar, ce_id); 1061 ce_state->attr_flags = attr->flags; 1062 ce_state->src_sz_max = attr->src_sz_max; 1063 1064 if (attr->src_nentries) 1065 ce_state->send_cb = attr->send_cb; 1066 1067 if (attr->dest_nentries) 1068 ce_state->recv_cb = attr->recv_cb; 1069 1070 if (attr->src_nentries) { 1071 ce_state->src_ring = ath10k_ce_alloc_src_ring(ar, ce_id, attr); 1072 if (IS_ERR(ce_state->src_ring)) { 1073 ret = PTR_ERR(ce_state->src_ring); 1074 ath10k_err(ar, "failed to allocate copy engine source ring %d: %d\n", 1075 ce_id, ret); 1076 ce_state->src_ring = NULL; 1077 return ret; 1078 } 1079 } 1080 1081 if (attr->dest_nentries) { 1082 ce_state->dest_ring = ath10k_ce_alloc_dest_ring(ar, ce_id, 1083 attr); 1084 if (IS_ERR(ce_state->dest_ring)) { 1085 ret = PTR_ERR(ce_state->dest_ring); 1086 ath10k_err(ar, "failed to allocate copy engine destination ring %d: %d\n", 1087 ce_id, ret); 1088 ce_state->dest_ring = NULL; 1089 return ret; 1090 } 1091 } 1092 1093 return 0; 1094 } 1095 1096 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id) 1097 { 1098 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1099 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; 1100 1101 if (ce_state->src_ring) { 1102 dma_free_coherent(ar->dev, 1103 (ce_state->src_ring->nentries * 1104 sizeof(struct ce_desc) + 1105 CE_DESC_RING_ALIGN), 1106 ce_state->src_ring->base_addr_owner_space, 1107 ce_state->src_ring->base_addr_ce_space); 1108 kfree(ce_state->src_ring); 1109 } 1110 1111 if (ce_state->dest_ring) { 1112 dma_free_coherent(ar->dev, 1113 (ce_state->dest_ring->nentries * 1114 sizeof(struct ce_desc) + 1115 CE_DESC_RING_ALIGN), 1116 ce_state->dest_ring->base_addr_owner_space, 1117 ce_state->dest_ring->base_addr_ce_space); 1118 kfree(ce_state->dest_ring); 1119 } 1120 1121 ce_state->src_ring = NULL; 1122 ce_state->dest_ring = NULL; 1123 } 1124