1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH_H 18 #define ATH_H 19 20 #include <linux/skbuff.h> 21 #include <linux/if_ether.h> 22 #include <linux/spinlock.h> 23 #include <net/mac80211.h> 24 25 /* 26 * The key cache is used for h/w cipher state and also for 27 * tracking station state such as the current tx antenna. 28 * We also setup a mapping table between key cache slot indices 29 * and station state to short-circuit node lookups on rx. 30 * Different parts have different size key caches. We handle 31 * up to ATH_KEYMAX entries (could dynamically allocate state). 32 */ 33 #define ATH_KEYMAX 128 /* max key cache size we handle */ 34 35 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 36 37 struct ath_ani { 38 bool caldone; 39 unsigned int longcal_timer; 40 unsigned int shortcal_timer; 41 unsigned int resetcal_timer; 42 unsigned int checkani_timer; 43 struct timer_list timer; 44 }; 45 46 struct ath_cycle_counters { 47 u32 cycles; 48 u32 rx_busy; 49 u32 rx_frame; 50 u32 tx_frame; 51 }; 52 53 enum ath_device_state { 54 ATH_HW_UNAVAILABLE, 55 ATH_HW_INITIALIZED, 56 }; 57 58 enum ath_bus_type { 59 ATH_PCI, 60 ATH_AHB, 61 ATH_USB, 62 }; 63 64 struct reg_dmn_pair_mapping { 65 u16 regDmnEnum; 66 u16 reg_5ghz_ctl; 67 u16 reg_2ghz_ctl; 68 }; 69 70 struct ath_regulatory { 71 char alpha2[2]; 72 u16 country_code; 73 u16 max_power_level; 74 u32 tp_scale; 75 u16 current_rd; 76 u16 current_rd_ext; 77 int16_t power_limit; 78 struct reg_dmn_pair_mapping *regpair; 79 }; 80 81 enum ath_crypt_caps { 82 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0), 83 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1), 84 }; 85 86 struct ath_keyval { 87 u8 kv_type; 88 u8 kv_pad; 89 u16 kv_len; 90 u8 kv_val[16]; /* TK */ 91 u8 kv_mic[8]; /* Michael MIC key */ 92 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 93 * supports both MIC keys in the same key cache entry; 94 * in that case, kv_mic is the RX key) */ 95 }; 96 97 enum ath_cipher { 98 ATH_CIPHER_WEP = 0, 99 ATH_CIPHER_AES_OCB = 1, 100 ATH_CIPHER_AES_CCM = 2, 101 ATH_CIPHER_CKIP = 3, 102 ATH_CIPHER_TKIP = 4, 103 ATH_CIPHER_CLR = 5, 104 ATH_CIPHER_MIC = 127 105 }; 106 107 /** 108 * struct ath_ops - Register read/write operations 109 * 110 * @read: Register read 111 * @write: Register write 112 * @enable_write_buffer: Enable multiple register writes 113 * @write_flush: flush buffered register writes and disable buffering 114 */ 115 struct ath_ops { 116 unsigned int (*read)(void *, u32 reg_offset); 117 void (*write)(void *, u32 val, u32 reg_offset); 118 void (*enable_write_buffer)(void *); 119 void (*write_flush) (void *); 120 }; 121 122 struct ath_common; 123 124 struct ath_bus_ops { 125 enum ath_bus_type ath_bus_type; 126 void (*read_cachesize)(struct ath_common *common, int *csz); 127 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 128 void (*bt_coex_prep)(struct ath_common *common); 129 }; 130 131 struct ath_common { 132 void *ah; 133 void *priv; 134 struct ieee80211_hw *hw; 135 int debug_mask; 136 enum ath_device_state state; 137 138 struct ath_ani ani; 139 140 u16 cachelsz; 141 u16 curaid; 142 u8 macaddr[ETH_ALEN]; 143 u8 curbssid[ETH_ALEN]; 144 u8 bssidmask[ETH_ALEN]; 145 146 u8 tx_chainmask; 147 u8 rx_chainmask; 148 149 u32 rx_bufsize; 150 151 u32 keymax; 152 DECLARE_BITMAP(keymap, ATH_KEYMAX); 153 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX); 154 enum ath_crypt_caps crypt_caps; 155 156 unsigned int clockrate; 157 158 spinlock_t cc_lock; 159 struct ath_cycle_counters cc_ani; 160 struct ath_cycle_counters cc_survey; 161 162 struct ath_regulatory regulatory; 163 const struct ath_ops *ops; 164 const struct ath_bus_ops *bus_ops; 165 }; 166 167 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 168 u32 len, 169 gfp_t gfp_mask); 170 171 void ath_hw_setbssidmask(struct ath_common *common); 172 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key); 173 int ath_key_config(struct ath_common *common, 174 struct ieee80211_vif *vif, 175 struct ieee80211_sta *sta, 176 struct ieee80211_key_conf *key); 177 bool ath_hw_keyreset(struct ath_common *common, u16 entry); 178 void ath_hw_cycle_counters_update(struct ath_common *common); 179 int32_t ath_hw_get_listen_time(struct ath_common *common); 180 181 #endif /* ATH_H */ 182