1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c37d4a00SZhao Qiang /* 3c37d4a00SZhao Qiang * drivers/tdm/line_ctrl/slic_ds26522.h 4c37d4a00SZhao Qiang * 5c37d4a00SZhao Qiang * Copyright 2016 Freescale Semiconductor, Inc. 6c37d4a00SZhao Qiang * 7c37d4a00SZhao Qiang * Author: Zhao Qiang <B45475@freescale.com> 8c37d4a00SZhao Qiang */ 9c37d4a00SZhao Qiang 10c37d4a00SZhao Qiang #define DS26522_RF_ADDR_START 0x00 11c37d4a00SZhao Qiang #define DS26522_RF_ADDR_END 0xef 12c37d4a00SZhao Qiang #define DS26522_GLB_ADDR_START 0xf0 13c37d4a00SZhao Qiang #define DS26522_GLB_ADDR_END 0xff 14c37d4a00SZhao Qiang #define DS26522_TF_ADDR_START 0x100 15c37d4a00SZhao Qiang #define DS26522_TF_ADDR_END 0x1ef 16c37d4a00SZhao Qiang #define DS26522_LIU_ADDR_START 0x1000 17c37d4a00SZhao Qiang #define DS26522_LIU_ADDR_END 0x101f 18c37d4a00SZhao Qiang #define DS26522_TEST_ADDR_START 0x1008 19c37d4a00SZhao Qiang #define DS26522_TEST_ADDR_END 0x101f 20c37d4a00SZhao Qiang #define DS26522_BERT_ADDR_START 0x1100 21c37d4a00SZhao Qiang #define DS26522_BERT_ADDR_END 0x110f 22c37d4a00SZhao Qiang 23c37d4a00SZhao Qiang #define DS26522_RMMR_ADDR 0x80 24c37d4a00SZhao Qiang #define DS26522_RCR1_ADDR 0x81 25c37d4a00SZhao Qiang #define DS26522_RCR3_ADDR 0x83 26c37d4a00SZhao Qiang #define DS26522_RIOCR_ADDR 0x84 27c37d4a00SZhao Qiang 28c37d4a00SZhao Qiang #define DS26522_GTCR1_ADDR 0xf0 29c37d4a00SZhao Qiang #define DS26522_GFCR_ADDR 0xf1 30c37d4a00SZhao Qiang #define DS26522_GTCR2_ADDR 0xf2 31c37d4a00SZhao Qiang #define DS26522_GTCCR_ADDR 0xf3 32c37d4a00SZhao Qiang #define DS26522_GLSRR_ADDR 0xf5 33c37d4a00SZhao Qiang #define DS26522_GFSRR_ADDR 0xf6 34c37d4a00SZhao Qiang #define DS26522_IDR_ADDR 0xf8 35c37d4a00SZhao Qiang 36c37d4a00SZhao Qiang #define DS26522_E1TAF_ADDR 0x164 37c37d4a00SZhao Qiang #define DS26522_E1TNAF_ADDR 0x165 38c37d4a00SZhao Qiang #define DS26522_TMMR_ADDR 0x180 39c37d4a00SZhao Qiang #define DS26522_TCR1_ADDR 0x181 40c37d4a00SZhao Qiang #define DS26522_TIOCR_ADDR 0x184 41c37d4a00SZhao Qiang 42c37d4a00SZhao Qiang #define DS26522_LTRCR_ADDR 0x1000 43c37d4a00SZhao Qiang #define DS26522_LTITSR_ADDR 0x1001 44c37d4a00SZhao Qiang #define DS26522_LMCR_ADDR 0x1002 45c37d4a00SZhao Qiang #define DS26522_LRISMR_ADDR 0x1007 46c37d4a00SZhao Qiang 47c37d4a00SZhao Qiang #define MAX_NUM_OF_CHANNELS 8 48c37d4a00SZhao Qiang #define PQ_MDS_8E1T1_BRD_REV 0x00 49c37d4a00SZhao Qiang #define PQ_MDS_8E1T1_PLD_REV 0x00 50c37d4a00SZhao Qiang 51c37d4a00SZhao Qiang #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0 52c37d4a00SZhao Qiang #define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08 53c37d4a00SZhao Qiang #define DS26522_GTCCR_FREQSEL_1544KHZ 0x04 54c37d4a00SZhao Qiang #define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00 55c37d4a00SZhao Qiang #define DS26522_GTCCR_FREQSEL_2048KHZ 0x00 56c37d4a00SZhao Qiang 57c37d4a00SZhao Qiang #define DS26522_GFCR_BPCLK_2048KHZ 0x00 58c37d4a00SZhao Qiang 59c37d4a00SZhao Qiang #define DS26522_GTCR2_TSSYNCOUT 0x02 60c37d4a00SZhao Qiang #define DS26522_GTCR1 0x00 61c37d4a00SZhao Qiang 62c37d4a00SZhao Qiang #define DS26522_GFSRR_RESET 0x01 63c37d4a00SZhao Qiang #define DS26522_GFSRR_NORMAL 0x00 64c37d4a00SZhao Qiang 65c37d4a00SZhao Qiang #define DS26522_GLSRR_RESET 0x01 66c37d4a00SZhao Qiang #define DS26522_GLSRR_NORMAL 0x00 67c37d4a00SZhao Qiang 68c37d4a00SZhao Qiang #define DS26522_RMMR_SFTRST 0x02 69c37d4a00SZhao Qiang #define DS26522_RMMR_FRM_EN 0x80 70c37d4a00SZhao Qiang #define DS26522_RMMR_INIT_DONE 0x40 71c37d4a00SZhao Qiang #define DS26522_RMMR_T1 0x00 72c37d4a00SZhao Qiang #define DS26522_RMMR_E1 0x01 73c37d4a00SZhao Qiang 74c37d4a00SZhao Qiang #define DS26522_E1TAF_DEFAULT 0x1b 75c37d4a00SZhao Qiang #define DS26522_E1TNAF_DEFAULT 0x40 76c37d4a00SZhao Qiang 77c37d4a00SZhao Qiang #define DS26522_TMMR_SFTRST 0x02 78c37d4a00SZhao Qiang #define DS26522_TMMR_FRM_EN 0x80 79c37d4a00SZhao Qiang #define DS26522_TMMR_INIT_DONE 0x40 80c37d4a00SZhao Qiang #define DS26522_TMMR_T1 0x00 81c37d4a00SZhao Qiang #define DS26522_TMMR_E1 0x01 82c37d4a00SZhao Qiang 83c37d4a00SZhao Qiang #define DS26522_RCR1_T1_SYNCT 0x80 84c37d4a00SZhao Qiang #define DS26522_RCR1_T1_RB8ZS 0x40 85c37d4a00SZhao Qiang #define DS26522_RCR1_T1_SYNCC 0x08 86c37d4a00SZhao Qiang 87c37d4a00SZhao Qiang #define DS26522_RCR1_E1_HDB3 0x40 88c37d4a00SZhao Qiang #define DS26522_RCR1_E1_CCS 0x20 89c37d4a00SZhao Qiang 90c37d4a00SZhao Qiang #define DS26522_RIOCR_1544KHZ 0x00 91c37d4a00SZhao Qiang #define DS26522_RIOCR_2048KHZ 0x10 92c37d4a00SZhao Qiang #define DS26522_RIOCR_RSIO_OUT 0x00 93c37d4a00SZhao Qiang 94c37d4a00SZhao Qiang #define DS26522_RCR3_FLB 0x01 95c37d4a00SZhao Qiang 96c37d4a00SZhao Qiang #define DS26522_TIOCR_1544KHZ 0x00 97c37d4a00SZhao Qiang #define DS26522_TIOCR_2048KHZ 0x10 98c37d4a00SZhao Qiang #define DS26522_TIOCR_TSIO_OUT 0x04 99c37d4a00SZhao Qiang 100c37d4a00SZhao Qiang #define DS26522_TCR1_TB8ZS 0x04 101c37d4a00SZhao Qiang 102c37d4a00SZhao Qiang #define DS26522_LTRCR_T1 0x02 103c37d4a00SZhao Qiang #define DS26522_LTRCR_E1 0x00 104c37d4a00SZhao Qiang 105c37d4a00SZhao Qiang #define DS26522_LTITSR_TLIS_75OHM 0x00 106c37d4a00SZhao Qiang #define DS26522_LTITSR_LBOS_75OHM 0x00 107c37d4a00SZhao Qiang #define DS26522_LTITSR_TLIS_100OHM 0x10 108c37d4a00SZhao Qiang #define DS26522_LTITSR_TLIS_0DB_CSU 0x00 109c37d4a00SZhao Qiang 110c37d4a00SZhao Qiang #define DS26522_LRISMR_75OHM 0x00 111c37d4a00SZhao Qiang #define DS26522_LRISMR_100OHM 0x10 112c37d4a00SZhao Qiang #define DS26522_LRISMR_MAX 0x03 113c37d4a00SZhao Qiang 114c37d4a00SZhao Qiang #define DS26522_LMCR_TE 0x01 115c37d4a00SZhao Qiang 116c37d4a00SZhao Qiang enum line_rate { 117c37d4a00SZhao Qiang LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */ 118c37d4a00SZhao Qiang LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */ 119c37d4a00SZhao Qiang }; 120c37d4a00SZhao Qiang 121c37d4a00SZhao Qiang enum tdm_trans_mode { 122c37d4a00SZhao Qiang NORMAL = 0, 123c37d4a00SZhao Qiang FRAMER_LB 124c37d4a00SZhao Qiang }; 125c37d4a00SZhao Qiang 126c37d4a00SZhao Qiang enum card_support_type { 127c37d4a00SZhao Qiang LM_CARD = 0, 128c37d4a00SZhao Qiang DS26522_CARD, 129c37d4a00SZhao Qiang NO_CARD 130c37d4a00SZhao Qiang }; 131