1*c37d4a00SZhao Qiang /* 2*c37d4a00SZhao Qiang * drivers/net/wan/slic_ds26522.c 3*c37d4a00SZhao Qiang * 4*c37d4a00SZhao Qiang * Copyright (C) 2016 Freescale Semiconductor, Inc. 5*c37d4a00SZhao Qiang * 6*c37d4a00SZhao Qiang * Author:Zhao Qiang<qiang.zhao@nxp.com> 7*c37d4a00SZhao Qiang * 8*c37d4a00SZhao Qiang * This program is free software; you can redistribute it and/or modify it 9*c37d4a00SZhao Qiang * under the terms of the GNU General Public License as published by the 10*c37d4a00SZhao Qiang * Free Software Foundation; either version 2 of the License, or (at your 11*c37d4a00SZhao Qiang * option) any later version. 12*c37d4a00SZhao Qiang */ 13*c37d4a00SZhao Qiang 14*c37d4a00SZhao Qiang #include <linux/bitrev.h> 15*c37d4a00SZhao Qiang #include <linux/module.h> 16*c37d4a00SZhao Qiang #include <linux/device.h> 17*c37d4a00SZhao Qiang #include <linux/kernel.h> 18*c37d4a00SZhao Qiang #include <linux/sched.h> 19*c37d4a00SZhao Qiang #include <linux/kthread.h> 20*c37d4a00SZhao Qiang #include <linux/spi/spi.h> 21*c37d4a00SZhao Qiang #include <linux/wait.h> 22*c37d4a00SZhao Qiang #include <linux/param.h> 23*c37d4a00SZhao Qiang #include <linux/delay.h> 24*c37d4a00SZhao Qiang #include <linux/of.h> 25*c37d4a00SZhao Qiang #include <linux/of_address.h> 26*c37d4a00SZhao Qiang #include <linux/io.h> 27*c37d4a00SZhao Qiang #include "slic_ds26522.h" 28*c37d4a00SZhao Qiang 29*c37d4a00SZhao Qiang #define DRV_NAME "ds26522" 30*c37d4a00SZhao Qiang 31*c37d4a00SZhao Qiang #define SLIC_TRANS_LEN 1 32*c37d4a00SZhao Qiang #define SLIC_TWO_LEN 2 33*c37d4a00SZhao Qiang #define SLIC_THREE_LEN 3 34*c37d4a00SZhao Qiang 35*c37d4a00SZhao Qiang static struct spi_device *g_spi; 36*c37d4a00SZhao Qiang 37*c37d4a00SZhao Qiang MODULE_LICENSE("GPL"); 38*c37d4a00SZhao Qiang MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>"); 39*c37d4a00SZhao Qiang 40*c37d4a00SZhao Qiang /* the read/write format of address is 41*c37d4a00SZhao Qiang * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x 42*c37d4a00SZhao Qiang */ 43*c37d4a00SZhao Qiang static void slic_write(struct spi_device *spi, u16 addr, 44*c37d4a00SZhao Qiang u8 data) 45*c37d4a00SZhao Qiang { 46*c37d4a00SZhao Qiang u8 temp[3]; 47*c37d4a00SZhao Qiang 48*c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 49*c37d4a00SZhao Qiang data = bitrev8(data); 50*c37d4a00SZhao Qiang temp[0] = (u8)((addr >> 8) & 0x7f); 51*c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 52*c37d4a00SZhao Qiang temp[2] = data; 53*c37d4a00SZhao Qiang 54*c37d4a00SZhao Qiang /* write spi addr and value */ 55*c37d4a00SZhao Qiang spi_write(spi, &temp[0], SLIC_THREE_LEN); 56*c37d4a00SZhao Qiang } 57*c37d4a00SZhao Qiang 58*c37d4a00SZhao Qiang static u8 slic_read(struct spi_device *spi, u16 addr) 59*c37d4a00SZhao Qiang { 60*c37d4a00SZhao Qiang u8 temp[2]; 61*c37d4a00SZhao Qiang u8 data; 62*c37d4a00SZhao Qiang 63*c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 64*c37d4a00SZhao Qiang temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80); 65*c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 66*c37d4a00SZhao Qiang 67*c37d4a00SZhao Qiang spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data, 68*c37d4a00SZhao Qiang SLIC_TRANS_LEN); 69*c37d4a00SZhao Qiang 70*c37d4a00SZhao Qiang data = bitrev8(data); 71*c37d4a00SZhao Qiang return data; 72*c37d4a00SZhao Qiang } 73*c37d4a00SZhao Qiang 74*c37d4a00SZhao Qiang static bool get_slic_product_code(struct spi_device *spi) 75*c37d4a00SZhao Qiang { 76*c37d4a00SZhao Qiang u8 device_id; 77*c37d4a00SZhao Qiang 78*c37d4a00SZhao Qiang device_id = slic_read(spi, DS26522_IDR_ADDR); 79*c37d4a00SZhao Qiang if ((device_id & 0xf8) == 0x68) 80*c37d4a00SZhao Qiang return true; 81*c37d4a00SZhao Qiang else 82*c37d4a00SZhao Qiang return false; 83*c37d4a00SZhao Qiang } 84*c37d4a00SZhao Qiang 85*c37d4a00SZhao Qiang static void ds26522_e1_spec_config(struct spi_device *spi) 86*c37d4a00SZhao Qiang { 87*c37d4a00SZhao Qiang /* Receive E1 Mode, Framer Disabled */ 88*c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1); 89*c37d4a00SZhao Qiang 90*c37d4a00SZhao Qiang /* Transmit E1 Mode, Framer Disable */ 91*c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1); 92*c37d4a00SZhao Qiang 93*c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable */ 94*c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, 95*c37d4a00SZhao Qiang slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN); 96*c37d4a00SZhao Qiang 97*c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable */ 98*c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, 99*c37d4a00SZhao Qiang slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN); 100*c37d4a00SZhao Qiang 101*c37d4a00SZhao Qiang /* RCR1, receive E1 B8zs & ESF */ 102*c37d4a00SZhao Qiang slic_write(spi, DS26522_RCR1_ADDR, 103*c37d4a00SZhao Qiang DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS); 104*c37d4a00SZhao Qiang 105*c37d4a00SZhao Qiang /* RSYSCLK=2.048MHz, RSYNC-Output */ 106*c37d4a00SZhao Qiang slic_write(spi, DS26522_RIOCR_ADDR, 107*c37d4a00SZhao Qiang DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT); 108*c37d4a00SZhao Qiang 109*c37d4a00SZhao Qiang /* TCR1 Transmit E1 b8zs */ 110*c37d4a00SZhao Qiang slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS); 111*c37d4a00SZhao Qiang 112*c37d4a00SZhao Qiang /* TSYSCLK=2.048MHz, TSYNC-Output */ 113*c37d4a00SZhao Qiang slic_write(spi, DS26522_TIOCR_ADDR, 114*c37d4a00SZhao Qiang DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT); 115*c37d4a00SZhao Qiang 116*c37d4a00SZhao Qiang /* Set E1TAF */ 117*c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT); 118*c37d4a00SZhao Qiang 119*c37d4a00SZhao Qiang /* Set E1TNAF register */ 120*c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT); 121*c37d4a00SZhao Qiang 122*c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable & init Done */ 123*c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) | 124*c37d4a00SZhao Qiang DS26522_RMMR_INIT_DONE); 125*c37d4a00SZhao Qiang 126*c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable & init Done */ 127*c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) | 128*c37d4a00SZhao Qiang DS26522_TMMR_INIT_DONE); 129*c37d4a00SZhao Qiang 130*c37d4a00SZhao Qiang /* Configure LIU E1 mode */ 131*c37d4a00SZhao Qiang slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1); 132*c37d4a00SZhao Qiang 133*c37d4a00SZhao Qiang /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */ 134*c37d4a00SZhao Qiang slic_write(spi, DS26522_LTITSR_ADDR, 135*c37d4a00SZhao Qiang DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM); 136*c37d4a00SZhao Qiang 137*c37d4a00SZhao Qiang /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */ 138*c37d4a00SZhao Qiang slic_write(spi, DS26522_LRISMR_ADDR, 139*c37d4a00SZhao Qiang DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX); 140*c37d4a00SZhao Qiang 141*c37d4a00SZhao Qiang /* Enable Transmit output */ 142*c37d4a00SZhao Qiang slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE); 143*c37d4a00SZhao Qiang } 144*c37d4a00SZhao Qiang 145*c37d4a00SZhao Qiang static int slic_ds26522_init_configure(struct spi_device *spi) 146*c37d4a00SZhao Qiang { 147*c37d4a00SZhao Qiang u16 addr; 148*c37d4a00SZhao Qiang 149*c37d4a00SZhao Qiang /* set clock */ 150*c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN | 151*c37d4a00SZhao Qiang DS26522_GTCCR_BFREQSEL_2048KHZ | 152*c37d4a00SZhao Qiang DS26522_GTCCR_FREQSEL_2048KHZ); 153*c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT); 154*c37d4a00SZhao Qiang slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ); 155*c37d4a00SZhao Qiang 156*c37d4a00SZhao Qiang /* set gtcr */ 157*c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1); 158*c37d4a00SZhao Qiang 159*c37d4a00SZhao Qiang /* Global LIU Software Reset Register */ 160*c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET); 161*c37d4a00SZhao Qiang 162*c37d4a00SZhao Qiang /* Global Framer and BERT Software Reset Register */ 163*c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET); 164*c37d4a00SZhao Qiang 165*c37d4a00SZhao Qiang usleep_range(100, 120); 166*c37d4a00SZhao Qiang 167*c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL); 168*c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL); 169*c37d4a00SZhao Qiang 170*c37d4a00SZhao Qiang /* Perform RX/TX SRESET,Reset receiver */ 171*c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST); 172*c37d4a00SZhao Qiang 173*c37d4a00SZhao Qiang /* Reset tranceiver */ 174*c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST); 175*c37d4a00SZhao Qiang 176*c37d4a00SZhao Qiang usleep_range(100, 120); 177*c37d4a00SZhao Qiang 178*c37d4a00SZhao Qiang /* Zero all Framer Registers */ 179*c37d4a00SZhao Qiang for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END; 180*c37d4a00SZhao Qiang addr++) 181*c37d4a00SZhao Qiang slic_write(spi, addr, 0); 182*c37d4a00SZhao Qiang 183*c37d4a00SZhao Qiang for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END; 184*c37d4a00SZhao Qiang addr++) 185*c37d4a00SZhao Qiang slic_write(spi, addr, 0); 186*c37d4a00SZhao Qiang 187*c37d4a00SZhao Qiang for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END; 188*c37d4a00SZhao Qiang addr++) 189*c37d4a00SZhao Qiang slic_write(spi, addr, 0); 190*c37d4a00SZhao Qiang 191*c37d4a00SZhao Qiang for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END; 192*c37d4a00SZhao Qiang addr++) 193*c37d4a00SZhao Qiang slic_write(spi, addr, 0); 194*c37d4a00SZhao Qiang 195*c37d4a00SZhao Qiang /* setup ds26522 for E1 specification */ 196*c37d4a00SZhao Qiang ds26522_e1_spec_config(spi); 197*c37d4a00SZhao Qiang 198*c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, 0x00); 199*c37d4a00SZhao Qiang 200*c37d4a00SZhao Qiang return 0; 201*c37d4a00SZhao Qiang } 202*c37d4a00SZhao Qiang 203*c37d4a00SZhao Qiang static int slic_ds26522_remove(struct spi_device *spi) 204*c37d4a00SZhao Qiang { 205*c37d4a00SZhao Qiang pr_info("DS26522 module uninstalled\n"); 206*c37d4a00SZhao Qiang return 0; 207*c37d4a00SZhao Qiang } 208*c37d4a00SZhao Qiang 209*c37d4a00SZhao Qiang static int slic_ds26522_probe(struct spi_device *spi) 210*c37d4a00SZhao Qiang { 211*c37d4a00SZhao Qiang int ret = 0; 212*c37d4a00SZhao Qiang 213*c37d4a00SZhao Qiang g_spi = spi; 214*c37d4a00SZhao Qiang spi->bits_per_word = 8; 215*c37d4a00SZhao Qiang 216*c37d4a00SZhao Qiang if (!get_slic_product_code(spi)) 217*c37d4a00SZhao Qiang return ret; 218*c37d4a00SZhao Qiang 219*c37d4a00SZhao Qiang ret = slic_ds26522_init_configure(spi); 220*c37d4a00SZhao Qiang if (ret == 0) 221*c37d4a00SZhao Qiang pr_info("DS26522 cs%d configurated\n", spi->chip_select); 222*c37d4a00SZhao Qiang 223*c37d4a00SZhao Qiang return ret; 224*c37d4a00SZhao Qiang } 225*c37d4a00SZhao Qiang 226*c37d4a00SZhao Qiang static const struct of_device_id slic_ds26522_match[] = { 227*c37d4a00SZhao Qiang { 228*c37d4a00SZhao Qiang .compatible = "maxim,ds26522", 229*c37d4a00SZhao Qiang }, 230*c37d4a00SZhao Qiang {}, 231*c37d4a00SZhao Qiang }; 232*c37d4a00SZhao Qiang 233*c37d4a00SZhao Qiang static struct spi_driver slic_ds26522_driver = { 234*c37d4a00SZhao Qiang .driver = { 235*c37d4a00SZhao Qiang .name = "ds26522", 236*c37d4a00SZhao Qiang .bus = &spi_bus_type, 237*c37d4a00SZhao Qiang .owner = THIS_MODULE, 238*c37d4a00SZhao Qiang .of_match_table = slic_ds26522_match, 239*c37d4a00SZhao Qiang }, 240*c37d4a00SZhao Qiang .probe = slic_ds26522_probe, 241*c37d4a00SZhao Qiang .remove = slic_ds26522_remove, 242*c37d4a00SZhao Qiang }; 243*c37d4a00SZhao Qiang 244*c37d4a00SZhao Qiang static int __init slic_ds26522_init(void) 245*c37d4a00SZhao Qiang { 246*c37d4a00SZhao Qiang return spi_register_driver(&slic_ds26522_driver); 247*c37d4a00SZhao Qiang } 248*c37d4a00SZhao Qiang 249*c37d4a00SZhao Qiang static void __exit slic_ds26522_exit(void) 250*c37d4a00SZhao Qiang { 251*c37d4a00SZhao Qiang spi_unregister_driver(&slic_ds26522_driver); 252*c37d4a00SZhao Qiang } 253*c37d4a00SZhao Qiang 254*c37d4a00SZhao Qiang module_init(slic_ds26522_init); 255*c37d4a00SZhao Qiang module_exit(slic_ds26522_exit); 256