1*2874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2c37d4a00SZhao Qiang /* 3c37d4a00SZhao Qiang * drivers/net/wan/slic_ds26522.c 4c37d4a00SZhao Qiang * 5c37d4a00SZhao Qiang * Copyright (C) 2016 Freescale Semiconductor, Inc. 6c37d4a00SZhao Qiang * 7c37d4a00SZhao Qiang * Author:Zhao Qiang<qiang.zhao@nxp.com> 8c37d4a00SZhao Qiang */ 9c37d4a00SZhao Qiang 10c37d4a00SZhao Qiang #include <linux/bitrev.h> 11c37d4a00SZhao Qiang #include <linux/module.h> 12c37d4a00SZhao Qiang #include <linux/device.h> 13c37d4a00SZhao Qiang #include <linux/kernel.h> 14c37d4a00SZhao Qiang #include <linux/sched.h> 15c37d4a00SZhao Qiang #include <linux/kthread.h> 16c37d4a00SZhao Qiang #include <linux/spi/spi.h> 17c37d4a00SZhao Qiang #include <linux/wait.h> 18c37d4a00SZhao Qiang #include <linux/param.h> 19c37d4a00SZhao Qiang #include <linux/delay.h> 20c37d4a00SZhao Qiang #include <linux/of.h> 21c37d4a00SZhao Qiang #include <linux/of_address.h> 22c37d4a00SZhao Qiang #include <linux/io.h> 23c37d4a00SZhao Qiang #include "slic_ds26522.h" 24c37d4a00SZhao Qiang 25c37d4a00SZhao Qiang #define DRV_NAME "ds26522" 26c37d4a00SZhao Qiang 27c37d4a00SZhao Qiang #define SLIC_TRANS_LEN 1 28c37d4a00SZhao Qiang #define SLIC_TWO_LEN 2 29c37d4a00SZhao Qiang #define SLIC_THREE_LEN 3 30c37d4a00SZhao Qiang 31c37d4a00SZhao Qiang static struct spi_device *g_spi; 32c37d4a00SZhao Qiang 33c37d4a00SZhao Qiang MODULE_LICENSE("GPL"); 34c37d4a00SZhao Qiang MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>"); 35c37d4a00SZhao Qiang 36c37d4a00SZhao Qiang /* the read/write format of address is 37c37d4a00SZhao Qiang * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x 38c37d4a00SZhao Qiang */ 39c37d4a00SZhao Qiang static void slic_write(struct spi_device *spi, u16 addr, 40c37d4a00SZhao Qiang u8 data) 41c37d4a00SZhao Qiang { 42c37d4a00SZhao Qiang u8 temp[3]; 43c37d4a00SZhao Qiang 44c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 45c37d4a00SZhao Qiang data = bitrev8(data); 46c37d4a00SZhao Qiang temp[0] = (u8)((addr >> 8) & 0x7f); 47c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 48c37d4a00SZhao Qiang temp[2] = data; 49c37d4a00SZhao Qiang 50c37d4a00SZhao Qiang /* write spi addr and value */ 51c37d4a00SZhao Qiang spi_write(spi, &temp[0], SLIC_THREE_LEN); 52c37d4a00SZhao Qiang } 53c37d4a00SZhao Qiang 54c37d4a00SZhao Qiang static u8 slic_read(struct spi_device *spi, u16 addr) 55c37d4a00SZhao Qiang { 56c37d4a00SZhao Qiang u8 temp[2]; 57c37d4a00SZhao Qiang u8 data; 58c37d4a00SZhao Qiang 59c37d4a00SZhao Qiang addr = bitrev16(addr) >> 1; 60c37d4a00SZhao Qiang temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80); 61c37d4a00SZhao Qiang temp[1] = (u8)(addr & 0xfe); 62c37d4a00SZhao Qiang 63c37d4a00SZhao Qiang spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data, 64c37d4a00SZhao Qiang SLIC_TRANS_LEN); 65c37d4a00SZhao Qiang 66c37d4a00SZhao Qiang data = bitrev8(data); 67c37d4a00SZhao Qiang return data; 68c37d4a00SZhao Qiang } 69c37d4a00SZhao Qiang 70c37d4a00SZhao Qiang static bool get_slic_product_code(struct spi_device *spi) 71c37d4a00SZhao Qiang { 72c37d4a00SZhao Qiang u8 device_id; 73c37d4a00SZhao Qiang 74c37d4a00SZhao Qiang device_id = slic_read(spi, DS26522_IDR_ADDR); 75c37d4a00SZhao Qiang if ((device_id & 0xf8) == 0x68) 76c37d4a00SZhao Qiang return true; 77c37d4a00SZhao Qiang else 78c37d4a00SZhao Qiang return false; 79c37d4a00SZhao Qiang } 80c37d4a00SZhao Qiang 81c37d4a00SZhao Qiang static void ds26522_e1_spec_config(struct spi_device *spi) 82c37d4a00SZhao Qiang { 83c37d4a00SZhao Qiang /* Receive E1 Mode, Framer Disabled */ 84c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1); 85c37d4a00SZhao Qiang 86c37d4a00SZhao Qiang /* Transmit E1 Mode, Framer Disable */ 87c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1); 88c37d4a00SZhao Qiang 89c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable */ 90c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, 91c37d4a00SZhao Qiang slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN); 92c37d4a00SZhao Qiang 93c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable */ 94c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, 95c37d4a00SZhao Qiang slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN); 96c37d4a00SZhao Qiang 97c37d4a00SZhao Qiang /* RCR1, receive E1 B8zs & ESF */ 98c37d4a00SZhao Qiang slic_write(spi, DS26522_RCR1_ADDR, 99c37d4a00SZhao Qiang DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS); 100c37d4a00SZhao Qiang 101c37d4a00SZhao Qiang /* RSYSCLK=2.048MHz, RSYNC-Output */ 102c37d4a00SZhao Qiang slic_write(spi, DS26522_RIOCR_ADDR, 103c37d4a00SZhao Qiang DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT); 104c37d4a00SZhao Qiang 105c37d4a00SZhao Qiang /* TCR1 Transmit E1 b8zs */ 106c37d4a00SZhao Qiang slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS); 107c37d4a00SZhao Qiang 108c37d4a00SZhao Qiang /* TSYSCLK=2.048MHz, TSYNC-Output */ 109c37d4a00SZhao Qiang slic_write(spi, DS26522_TIOCR_ADDR, 110c37d4a00SZhao Qiang DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT); 111c37d4a00SZhao Qiang 112c37d4a00SZhao Qiang /* Set E1TAF */ 113c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT); 114c37d4a00SZhao Qiang 115c37d4a00SZhao Qiang /* Set E1TNAF register */ 116c37d4a00SZhao Qiang slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT); 117c37d4a00SZhao Qiang 118c37d4a00SZhao Qiang /* Receive E1 Mode Framer Enable & init Done */ 119c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) | 120c37d4a00SZhao Qiang DS26522_RMMR_INIT_DONE); 121c37d4a00SZhao Qiang 122c37d4a00SZhao Qiang /* Transmit E1 Mode Framer Enable & init Done */ 123c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) | 124c37d4a00SZhao Qiang DS26522_TMMR_INIT_DONE); 125c37d4a00SZhao Qiang 126c37d4a00SZhao Qiang /* Configure LIU E1 mode */ 127c37d4a00SZhao Qiang slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1); 128c37d4a00SZhao Qiang 129c37d4a00SZhao Qiang /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */ 130c37d4a00SZhao Qiang slic_write(spi, DS26522_LTITSR_ADDR, 131c37d4a00SZhao Qiang DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM); 132c37d4a00SZhao Qiang 133c37d4a00SZhao Qiang /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */ 134c37d4a00SZhao Qiang slic_write(spi, DS26522_LRISMR_ADDR, 135c37d4a00SZhao Qiang DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX); 136c37d4a00SZhao Qiang 137c37d4a00SZhao Qiang /* Enable Transmit output */ 138c37d4a00SZhao Qiang slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE); 139c37d4a00SZhao Qiang } 140c37d4a00SZhao Qiang 141c37d4a00SZhao Qiang static int slic_ds26522_init_configure(struct spi_device *spi) 142c37d4a00SZhao Qiang { 143c37d4a00SZhao Qiang u16 addr; 144c37d4a00SZhao Qiang 145c37d4a00SZhao Qiang /* set clock */ 146c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN | 147c37d4a00SZhao Qiang DS26522_GTCCR_BFREQSEL_2048KHZ | 148c37d4a00SZhao Qiang DS26522_GTCCR_FREQSEL_2048KHZ); 149c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT); 150c37d4a00SZhao Qiang slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ); 151c37d4a00SZhao Qiang 152c37d4a00SZhao Qiang /* set gtcr */ 153c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1); 154c37d4a00SZhao Qiang 155c37d4a00SZhao Qiang /* Global LIU Software Reset Register */ 156c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET); 157c37d4a00SZhao Qiang 158c37d4a00SZhao Qiang /* Global Framer and BERT Software Reset Register */ 159c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET); 160c37d4a00SZhao Qiang 161c37d4a00SZhao Qiang usleep_range(100, 120); 162c37d4a00SZhao Qiang 163c37d4a00SZhao Qiang slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL); 164c37d4a00SZhao Qiang slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL); 165c37d4a00SZhao Qiang 166c37d4a00SZhao Qiang /* Perform RX/TX SRESET,Reset receiver */ 167c37d4a00SZhao Qiang slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST); 168c37d4a00SZhao Qiang 169c37d4a00SZhao Qiang /* Reset tranceiver */ 170c37d4a00SZhao Qiang slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST); 171c37d4a00SZhao Qiang 172c37d4a00SZhao Qiang usleep_range(100, 120); 173c37d4a00SZhao Qiang 174c37d4a00SZhao Qiang /* Zero all Framer Registers */ 175c37d4a00SZhao Qiang for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END; 176c37d4a00SZhao Qiang addr++) 177c37d4a00SZhao Qiang slic_write(spi, addr, 0); 178c37d4a00SZhao Qiang 179c37d4a00SZhao Qiang for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END; 180c37d4a00SZhao Qiang addr++) 181c37d4a00SZhao Qiang slic_write(spi, addr, 0); 182c37d4a00SZhao Qiang 183c37d4a00SZhao Qiang for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END; 184c37d4a00SZhao Qiang addr++) 185c37d4a00SZhao Qiang slic_write(spi, addr, 0); 186c37d4a00SZhao Qiang 187c37d4a00SZhao Qiang for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END; 188c37d4a00SZhao Qiang addr++) 189c37d4a00SZhao Qiang slic_write(spi, addr, 0); 190c37d4a00SZhao Qiang 191c37d4a00SZhao Qiang /* setup ds26522 for E1 specification */ 192c37d4a00SZhao Qiang ds26522_e1_spec_config(spi); 193c37d4a00SZhao Qiang 194c37d4a00SZhao Qiang slic_write(spi, DS26522_GTCR1_ADDR, 0x00); 195c37d4a00SZhao Qiang 196c37d4a00SZhao Qiang return 0; 197c37d4a00SZhao Qiang } 198c37d4a00SZhao Qiang 199c37d4a00SZhao Qiang static int slic_ds26522_remove(struct spi_device *spi) 200c37d4a00SZhao Qiang { 201c37d4a00SZhao Qiang pr_info("DS26522 module uninstalled\n"); 202c37d4a00SZhao Qiang return 0; 203c37d4a00SZhao Qiang } 204c37d4a00SZhao Qiang 205c37d4a00SZhao Qiang static int slic_ds26522_probe(struct spi_device *spi) 206c37d4a00SZhao Qiang { 207c37d4a00SZhao Qiang int ret = 0; 208c37d4a00SZhao Qiang 209c37d4a00SZhao Qiang g_spi = spi; 210c37d4a00SZhao Qiang spi->bits_per_word = 8; 211c37d4a00SZhao Qiang 212c37d4a00SZhao Qiang if (!get_slic_product_code(spi)) 213c37d4a00SZhao Qiang return ret; 214c37d4a00SZhao Qiang 215c37d4a00SZhao Qiang ret = slic_ds26522_init_configure(spi); 216c37d4a00SZhao Qiang if (ret == 0) 21760133867SColin Ian King pr_info("DS26522 cs%d configured\n", spi->chip_select); 218c37d4a00SZhao Qiang 219c37d4a00SZhao Qiang return ret; 220c37d4a00SZhao Qiang } 221c37d4a00SZhao Qiang 222558c5eb5SJavier Martinez Canillas static const struct spi_device_id slic_ds26522_id[] = { 223558c5eb5SJavier Martinez Canillas { .name = "ds26522" }, 224558c5eb5SJavier Martinez Canillas { /* sentinel */ }, 225558c5eb5SJavier Martinez Canillas }; 226558c5eb5SJavier Martinez Canillas MODULE_DEVICE_TABLE(spi, slic_ds26522_id); 227558c5eb5SJavier Martinez Canillas 228c37d4a00SZhao Qiang static const struct of_device_id slic_ds26522_match[] = { 229c37d4a00SZhao Qiang { 230c37d4a00SZhao Qiang .compatible = "maxim,ds26522", 231c37d4a00SZhao Qiang }, 232c37d4a00SZhao Qiang {}, 233c37d4a00SZhao Qiang }; 234485c9d43SJavier Martinez Canillas MODULE_DEVICE_TABLE(of, slic_ds26522_match); 235c37d4a00SZhao Qiang 236c37d4a00SZhao Qiang static struct spi_driver slic_ds26522_driver = { 237c37d4a00SZhao Qiang .driver = { 238c37d4a00SZhao Qiang .name = "ds26522", 239c37d4a00SZhao Qiang .bus = &spi_bus_type, 240c37d4a00SZhao Qiang .of_match_table = slic_ds26522_match, 241c37d4a00SZhao Qiang }, 242c37d4a00SZhao Qiang .probe = slic_ds26522_probe, 243c37d4a00SZhao Qiang .remove = slic_ds26522_remove, 244558c5eb5SJavier Martinez Canillas .id_table = slic_ds26522_id, 245c37d4a00SZhao Qiang }; 246c37d4a00SZhao Qiang 247c3afa995SWei Yongjun module_spi_driver(slic_ds26522_driver); 248