1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cyclades PC300 synchronous serial card driver for Linux 4 * 5 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>. 8 * 9 * Sources of information: 10 * Hitachi HD64572 SCA-II User's Manual 11 * Original Cyclades PC300 Linux driver 12 * 13 * This driver currently supports only PC300/RSV (V.24/V.35) and 14 * PC300/X21 cards. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/types.h> 24 #include <linux/fcntl.h> 25 #include <linux/in.h> 26 #include <linux/string.h> 27 #include <linux/errno.h> 28 #include <linux/init.h> 29 #include <linux/ioport.h> 30 #include <linux/moduleparam.h> 31 #include <linux/netdevice.h> 32 #include <linux/hdlc.h> 33 #include <linux/pci.h> 34 #include <linux/delay.h> 35 #include <asm/io.h> 36 37 #include "hd64572.h" 38 39 #undef DEBUG_PKT 40 #define DEBUG_RINGS 41 42 #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */ 43 #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */ 44 #define MAX_TX_BUFFERS 10 45 46 static int pci_clock_freq = 33000000; 47 static int use_crystal_clock; 48 static unsigned int CLOCK_BASE; 49 50 /* Masks to access the init_ctrl PLX register */ 51 #define PC300_CLKSEL_MASK (0x00000004UL) 52 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3)) 53 #define PC300_CTYPE_MASK (0x00000800UL) 54 55 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */ 56 57 /* 58 * PLX PCI9050-1 local configuration and shared runtime registers. 59 * This structure can be used to access 9050 registers (memory mapped). 60 */ 61 typedef struct { 62 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 63 u32 loc_rom_range; /* 10h : Local ROM Range */ 64 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 65 u32 loc_rom_base; /* 24h : Local ROM Base */ 66 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 67 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ 68 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 69 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 70 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 71 }plx9050; 72 73 typedef struct port_s { 74 struct napi_struct napi; 75 struct net_device *netdev; 76 struct card_s *card; 77 spinlock_t lock; /* TX lock */ 78 sync_serial_settings settings; 79 int rxpart; /* partial frame received, next frame invalid*/ 80 unsigned short encoding; 81 unsigned short parity; 82 unsigned int iface; 83 u16 rxin; /* rx ring buffer 'in' pointer */ 84 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 85 u16 txlast; 86 u8 rxs, txs, tmc; /* SCA registers */ 87 u8 chan; /* physical port # - 0 or 1 */ 88 }port_t; 89 90 typedef struct card_s { 91 int type; /* RSV, X21, etc. */ 92 int n_ports; /* 1 or 2 ports */ 93 u8 __iomem *rambase; /* buffer memory base (virtual) */ 94 u8 __iomem *scabase; /* SCA memory base (virtual) */ 95 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */ 96 u32 init_ctrl_value; /* Saved value - 9050 bug workaround */ 97 u16 rx_ring_buffers; /* number of buffers in a ring */ 98 u16 tx_ring_buffers; 99 u16 buff_offset; /* offset of first buffer of first channel */ 100 u8 irq; /* interrupt request level */ 101 102 port_t ports[2]; 103 }card_t; 104 105 #define get_port(card, port) ((port) < (card)->n_ports ? \ 106 (&(card)->ports[port]) : (NULL)) 107 108 #include "hd64572.c" 109 110 static void pc300_set_iface(port_t *port) 111 { 112 card_t *card = port->card; 113 u32 __iomem *init_ctrl = &card->plxbase->init_ctrl; 114 u16 msci = get_msci(port); 115 u8 rxs = port->rxs & CLK_BRG_MASK; 116 u8 txs = port->txs & CLK_BRG_MASK; 117 118 sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, 119 port->card); 120 switch(port->settings.clock_type) { 121 case CLOCK_INT: 122 rxs |= CLK_BRG; /* BRG output */ 123 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 124 break; 125 126 case CLOCK_TXINT: 127 rxs |= CLK_LINE; /* RXC input */ 128 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ 129 break; 130 131 case CLOCK_TXFROMRX: 132 rxs |= CLK_LINE; /* RXC input */ 133 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 134 break; 135 136 default: /* EXTernal clock */ 137 rxs |= CLK_LINE; /* RXC input */ 138 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ 139 break; 140 } 141 142 port->rxs = rxs; 143 port->txs = txs; 144 sca_out(rxs, msci + RXS, card); 145 sca_out(txs, msci + TXS, card); 146 sca_set_port(port); 147 148 if (port->card->type == PC300_RSV) { 149 if (port->iface == IF_IFACE_V35) 150 writel(card->init_ctrl_value | 151 PC300_CHMEDIA_MASK(port->chan), init_ctrl); 152 else 153 writel(card->init_ctrl_value & 154 ~PC300_CHMEDIA_MASK(port->chan), init_ctrl); 155 } 156 } 157 158 static int pc300_open(struct net_device *dev) 159 { 160 port_t *port = dev_to_port(dev); 161 int result = hdlc_open(dev); 162 163 if (result) 164 return result; 165 166 sca_open(dev); 167 pc300_set_iface(port); 168 return 0; 169 } 170 171 static int pc300_close(struct net_device *dev) 172 { 173 sca_close(dev); 174 hdlc_close(dev); 175 return 0; 176 } 177 178 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 179 { 180 const size_t size = sizeof(sync_serial_settings); 181 sync_serial_settings new_line; 182 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 183 int new_type; 184 port_t *port = dev_to_port(dev); 185 186 #ifdef DEBUG_RINGS 187 if (cmd == SIOCDEVPRIVATE) { 188 sca_dump_rings(dev); 189 return 0; 190 } 191 #endif 192 if (cmd != SIOCWANDEV) 193 return hdlc_ioctl(dev, ifr, cmd); 194 195 if (ifr->ifr_settings.type == IF_GET_IFACE) { 196 ifr->ifr_settings.type = port->iface; 197 if (ifr->ifr_settings.size < size) { 198 ifr->ifr_settings.size = size; /* data size wanted */ 199 return -ENOBUFS; 200 } 201 if (copy_to_user(line, &port->settings, size)) 202 return -EFAULT; 203 return 0; 204 } 205 206 if (port->card->type == PC300_X21 && 207 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || 208 ifr->ifr_settings.type == IF_IFACE_X21)) 209 new_type = IF_IFACE_X21; 210 211 else if (port->card->type == PC300_RSV && 212 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || 213 ifr->ifr_settings.type == IF_IFACE_V35)) 214 new_type = IF_IFACE_V35; 215 216 else if (port->card->type == PC300_RSV && 217 ifr->ifr_settings.type == IF_IFACE_V24) 218 new_type = IF_IFACE_V24; 219 220 else 221 return hdlc_ioctl(dev, ifr, cmd); 222 223 if (!capable(CAP_NET_ADMIN)) 224 return -EPERM; 225 226 if (copy_from_user(&new_line, line, size)) 227 return -EFAULT; 228 229 if (new_line.clock_type != CLOCK_EXT && 230 new_line.clock_type != CLOCK_TXFROMRX && 231 new_line.clock_type != CLOCK_INT && 232 new_line.clock_type != CLOCK_TXINT) 233 return -EINVAL; /* No such clock setting */ 234 235 if (new_line.loopback != 0 && new_line.loopback != 1) 236 return -EINVAL; 237 238 memcpy(&port->settings, &new_line, size); /* Update settings */ 239 port->iface = new_type; 240 pc300_set_iface(port); 241 return 0; 242 } 243 244 static void pc300_pci_remove_one(struct pci_dev *pdev) 245 { 246 int i; 247 card_t *card = pci_get_drvdata(pdev); 248 249 for (i = 0; i < 2; i++) 250 if (card->ports[i].card) 251 unregister_hdlc_device(card->ports[i].netdev); 252 253 if (card->irq) 254 free_irq(card->irq, card); 255 256 if (card->rambase) 257 iounmap(card->rambase); 258 if (card->scabase) 259 iounmap(card->scabase); 260 if (card->plxbase) 261 iounmap(card->plxbase); 262 263 pci_release_regions(pdev); 264 pci_disable_device(pdev); 265 if (card->ports[0].netdev) 266 free_netdev(card->ports[0].netdev); 267 if (card->ports[1].netdev) 268 free_netdev(card->ports[1].netdev); 269 kfree(card); 270 } 271 272 static const struct net_device_ops pc300_ops = { 273 .ndo_open = pc300_open, 274 .ndo_stop = pc300_close, 275 .ndo_start_xmit = hdlc_start_xmit, 276 .ndo_do_ioctl = pc300_ioctl, 277 }; 278 279 static int pc300_pci_init_one(struct pci_dev *pdev, 280 const struct pci_device_id *ent) 281 { 282 card_t *card; 283 u32 __iomem *p; 284 int i; 285 u32 ramsize; 286 u32 ramphys; /* buffer memory base */ 287 u32 scaphys; /* SCA memory base */ 288 u32 plxphys; /* PLX registers memory base */ 289 290 i = pci_enable_device(pdev); 291 if (i) 292 return i; 293 294 i = pci_request_regions(pdev, "PC300"); 295 if (i) { 296 pci_disable_device(pdev); 297 return i; 298 } 299 300 card = kzalloc(sizeof(card_t), GFP_KERNEL); 301 if (card == NULL) { 302 pci_release_regions(pdev); 303 pci_disable_device(pdev); 304 return -ENOBUFS; 305 } 306 pci_set_drvdata(pdev, card); 307 308 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE || 309 pci_resource_len(pdev, 2) != PC300_SCA_SIZE || 310 pci_resource_len(pdev, 3) < 16384) { 311 pr_err("invalid card EEPROM parameters\n"); 312 pc300_pci_remove_one(pdev); 313 return -EFAULT; 314 } 315 316 plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK; 317 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE); 318 319 scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK; 320 card->scabase = ioremap(scaphys, PC300_SCA_SIZE); 321 322 ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK; 323 card->rambase = pci_ioremap_bar(pdev, 3); 324 325 if (card->plxbase == NULL || 326 card->scabase == NULL || 327 card->rambase == NULL) { 328 pr_err("ioremap() failed\n"); 329 pc300_pci_remove_one(pdev); 330 return -ENOMEM; 331 } 332 333 /* PLX PCI 9050 workaround for local configuration register read bug */ 334 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys); 335 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl); 336 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys); 337 338 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 || 339 pdev->device == PCI_DEVICE_ID_PC300_TE_2) 340 card->type = PC300_TE; /* not fully supported */ 341 else if (card->init_ctrl_value & PC300_CTYPE_MASK) 342 card->type = PC300_X21; 343 else 344 card->type = PC300_RSV; 345 346 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 || 347 pdev->device == PCI_DEVICE_ID_PC300_TE_1) 348 card->n_ports = 1; 349 else 350 card->n_ports = 2; 351 352 for (i = 0; i < card->n_ports; i++) { 353 card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]); 354 if (!card->ports[i].netdev) { 355 pr_err("unable to allocate memory\n"); 356 pc300_pci_remove_one(pdev); 357 return -ENOMEM; 358 } 359 } 360 361 /* Reset PLX */ 362 p = &card->plxbase->init_ctrl; 363 writel(card->init_ctrl_value | 0x40000000, p); 364 readl(p); /* Flush the write - do not use sca_flush */ 365 udelay(1); 366 367 writel(card->init_ctrl_value, p); 368 readl(p); /* Flush the write - do not use sca_flush */ 369 udelay(1); 370 371 /* Reload Config. Registers from EEPROM */ 372 writel(card->init_ctrl_value | 0x20000000, p); 373 readl(p); /* Flush the write - do not use sca_flush */ 374 udelay(1); 375 376 writel(card->init_ctrl_value, p); 377 readl(p); /* Flush the write - do not use sca_flush */ 378 udelay(1); 379 380 ramsize = sca_detect_ram(card, card->rambase, 381 pci_resource_len(pdev, 3)); 382 383 if (use_crystal_clock) 384 card->init_ctrl_value &= ~PC300_CLKSEL_MASK; 385 else 386 card->init_ctrl_value |= PC300_CLKSEL_MASK; 387 388 writel(card->init_ctrl_value, &card->plxbase->init_ctrl); 389 /* number of TX + RX buffers for one port */ 390 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU)); 391 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); 392 card->rx_ring_buffers = i - card->tx_ring_buffers; 393 394 card->buff_offset = card->n_ports * sizeof(pkt_desc) * 395 (card->tx_ring_buffers + card->rx_ring_buffers); 396 397 pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n", 398 card->type == PC300_X21 ? "X21" : 399 card->type == PC300_TE ? "TE" : "RSV", 400 ramsize / 1024, ramphys, pdev->irq, 401 card->tx_ring_buffers, card->rx_ring_buffers); 402 403 if (card->tx_ring_buffers < 1) { 404 pr_err("RAM test failed\n"); 405 pc300_pci_remove_one(pdev); 406 return -EFAULT; 407 } 408 409 /* Enable interrupts on the PCI bridge, LINTi1 active low */ 410 writew(0x0041, &card->plxbase->intr_ctrl_stat); 411 412 /* Allocate IRQ */ 413 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) { 414 pr_warn("could not allocate IRQ%d\n", pdev->irq); 415 pc300_pci_remove_one(pdev); 416 return -EBUSY; 417 } 418 card->irq = pdev->irq; 419 420 sca_init(card, 0); 421 422 // COTE not set - allows better TX DMA settings 423 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card); 424 425 sca_out(0x10, BTCR, card); 426 427 for (i = 0; i < card->n_ports; i++) { 428 port_t *port = &card->ports[i]; 429 struct net_device *dev = port->netdev; 430 hdlc_device *hdlc = dev_to_hdlc(dev); 431 432 port->chan = i; 433 434 spin_lock_init(&port->lock); 435 dev->irq = card->irq; 436 dev->mem_start = ramphys; 437 dev->mem_end = ramphys + ramsize - 1; 438 dev->tx_queue_len = 50; 439 dev->netdev_ops = &pc300_ops; 440 hdlc->attach = sca_attach; 441 hdlc->xmit = sca_xmit; 442 port->settings.clock_type = CLOCK_EXT; 443 port->card = card; 444 if (card->type == PC300_X21) 445 port->iface = IF_IFACE_X21; 446 else 447 port->iface = IF_IFACE_V35; 448 449 sca_init_port(port); 450 if (register_hdlc_device(dev)) { 451 pr_err("unable to register hdlc device\n"); 452 port->card = NULL; 453 pc300_pci_remove_one(pdev); 454 return -ENOBUFS; 455 } 456 457 netdev_info(dev, "PC300 channel %d\n", port->chan); 458 } 459 return 0; 460 } 461 462 static const struct pci_device_id pc300_pci_tbl[] = { 463 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID, 464 PCI_ANY_ID, 0, 0, 0 }, 465 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID, 466 PCI_ANY_ID, 0, 0, 0 }, 467 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID, 468 PCI_ANY_ID, 0, 0, 0 }, 469 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID, 470 PCI_ANY_ID, 0, 0, 0 }, 471 { 0, } 472 }; 473 474 static struct pci_driver pc300_pci_driver = { 475 .name = "PC300", 476 .id_table = pc300_pci_tbl, 477 .probe = pc300_pci_init_one, 478 .remove = pc300_pci_remove_one, 479 }; 480 481 static int __init pc300_init_module(void) 482 { 483 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { 484 pr_err("Invalid PCI clock frequency\n"); 485 return -EINVAL; 486 } 487 if (use_crystal_clock != 0 && use_crystal_clock != 1) { 488 pr_err("Invalid 'use_crystal_clock' value\n"); 489 return -EINVAL; 490 } 491 492 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq; 493 494 return pci_register_driver(&pc300_pci_driver); 495 } 496 497 static void __exit pc300_cleanup_module(void) 498 { 499 pci_unregister_driver(&pc300_pci_driver); 500 } 501 502 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 503 MODULE_DESCRIPTION("Cyclades PC300 serial port driver"); 504 MODULE_LICENSE("GPL v2"); 505 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl); 506 module_param(pci_clock_freq, int, 0444); 507 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); 508 module_param(use_crystal_clock, int, 0444); 509 MODULE_PARM_DESC(use_crystal_clock, 510 "Use 24.576 MHz clock instead of PCI clock"); 511 module_init(pc300_init_module); 512 module_exit(pc300_cleanup_module); 513