1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Freescale QUICC Engine HDLC Device Driver 3 * 4 * Copyright 2016 Freescale Semiconductor Inc. 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/hdlc.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/sched.h> 22 #include <linux/skbuff.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/stddef.h> 26 #include <soc/fsl/qe/qe_tdm.h> 27 #include <uapi/linux/if_arp.h> 28 29 #include "fsl_ucc_hdlc.h" 30 31 #define DRV_DESC "Freescale QE UCC HDLC Driver" 32 #define DRV_NAME "ucc_hdlc" 33 34 #define TDM_PPPOHT_SLIC_MAXIN 35 #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S) 36 37 static int uhdlc_close(struct net_device *dev); 38 39 static struct ucc_tdm_info utdm_primary_info = { 40 .uf_info = { 41 .tsa = 0, 42 .cdp = 0, 43 .cds = 1, 44 .ctsp = 1, 45 .ctss = 1, 46 .revd = 0, 47 .urfs = 256, 48 .utfs = 256, 49 .urfet = 128, 50 .urfset = 192, 51 .utfet = 128, 52 .utftt = 0x40, 53 .ufpt = 256, 54 .mode = UCC_FAST_PROTOCOL_MODE_HDLC, 55 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 56 .tenc = UCC_FAST_TX_ENCODING_NRZ, 57 .renc = UCC_FAST_RX_ENCODING_NRZ, 58 .tcrc = UCC_FAST_16_BIT_CRC, 59 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 60 }, 61 62 .si_info = { 63 #ifdef TDM_PPPOHT_SLIC_MAXIN 64 .simr_rfsd = 1, 65 .simr_tfsd = 2, 66 #else 67 .simr_rfsd = 0, 68 .simr_tfsd = 0, 69 #endif 70 .simr_crt = 0, 71 .simr_sl = 0, 72 .simr_ce = 1, 73 .simr_fe = 1, 74 .simr_gm = 0, 75 }, 76 }; 77 78 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM]; 79 80 static int uhdlc_init(struct ucc_hdlc_private *priv) 81 { 82 struct ucc_tdm_info *ut_info; 83 struct ucc_fast_info *uf_info; 84 u32 cecr_subblock; 85 u16 bd_status; 86 int ret, i; 87 void *bd_buffer; 88 dma_addr_t bd_dma_addr; 89 s32 riptr; 90 s32 tiptr; 91 u32 gumr; 92 93 ut_info = priv->ut_info; 94 uf_info = &ut_info->uf_info; 95 96 if (priv->tsa) { 97 uf_info->tsa = 1; 98 uf_info->ctsp = 1; 99 uf_info->cds = 1; 100 uf_info->ctss = 1; 101 } else { 102 uf_info->cds = 0; 103 uf_info->ctsp = 0; 104 uf_info->ctss = 0; 105 } 106 107 /* This sets HPM register in CMXUCR register which configures a 108 * open drain connected HDLC bus 109 */ 110 if (priv->hdlc_bus) 111 uf_info->brkpt_support = 1; 112 113 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF | 114 UCC_HDLC_UCCE_TXB) << 16); 115 116 ret = ucc_fast_init(uf_info, &priv->uccf); 117 if (ret) { 118 dev_err(priv->dev, "Failed to init uccf."); 119 return ret; 120 } 121 122 priv->uf_regs = priv->uccf->uf_regs; 123 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 124 125 /* Loopback mode */ 126 if (priv->loopback) { 127 dev_info(priv->dev, "Loopback Mode\n"); 128 /* use the same clock when work in loopback */ 129 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1); 130 131 gumr = ioread32be(&priv->uf_regs->gumr); 132 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS | 133 UCC_FAST_GUMR_TCI); 134 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN); 135 iowrite32be(gumr, &priv->uf_regs->gumr); 136 } 137 138 /* Initialize SI */ 139 if (priv->tsa) 140 ucc_tdm_init(priv->utdm, priv->ut_info); 141 142 /* Write to QE CECR, UCCx channel to Stop Transmission */ 143 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 144 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock, 145 QE_CR_PROTOCOL_UNSPECIFIED, 0); 146 147 /* Set UPSMR normal mode (need fixed)*/ 148 iowrite32be(0, &priv->uf_regs->upsmr); 149 150 /* hdlc_bus mode */ 151 if (priv->hdlc_bus) { 152 u32 upsmr; 153 154 dev_info(priv->dev, "HDLC bus Mode\n"); 155 upsmr = ioread32be(&priv->uf_regs->upsmr); 156 157 /* bus mode and retransmit enable, with collision window 158 * set to 8 bytes 159 */ 160 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS | 161 UCC_HDLC_UPSMR_CW8; 162 iowrite32be(upsmr, &priv->uf_regs->upsmr); 163 164 /* explicitly disable CDS & CTSP */ 165 gumr = ioread32be(&priv->uf_regs->gumr); 166 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP); 167 /* set automatic sync to explicitly ignore CD signal */ 168 gumr |= UCC_FAST_GUMR_SYNL_AUTO; 169 iowrite32be(gumr, &priv->uf_regs->gumr); 170 } 171 172 priv->rx_ring_size = RX_BD_RING_LEN; 173 priv->tx_ring_size = TX_BD_RING_LEN; 174 /* Alloc Rx BD */ 175 priv->rx_bd_base = dma_alloc_coherent(priv->dev, 176 RX_BD_RING_LEN * sizeof(struct qe_bd), 177 &priv->dma_rx_bd, GFP_KERNEL); 178 179 if (!priv->rx_bd_base) { 180 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n"); 181 ret = -ENOMEM; 182 goto free_uccf; 183 } 184 185 /* Alloc Tx BD */ 186 priv->tx_bd_base = dma_alloc_coherent(priv->dev, 187 TX_BD_RING_LEN * sizeof(struct qe_bd), 188 &priv->dma_tx_bd, GFP_KERNEL); 189 190 if (!priv->tx_bd_base) { 191 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n"); 192 ret = -ENOMEM; 193 goto free_rx_bd; 194 } 195 196 /* Alloc parameter ram for ucc hdlc */ 197 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param), 198 ALIGNMENT_OF_UCC_HDLC_PRAM); 199 200 if (priv->ucc_pram_offset < 0) { 201 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n"); 202 ret = -ENOMEM; 203 goto free_tx_bd; 204 } 205 206 priv->rx_skbuff = kzalloc_objs(*priv->rx_skbuff, priv->rx_ring_size); 207 if (!priv->rx_skbuff) { 208 ret = -ENOMEM; 209 goto free_ucc_pram; 210 } 211 212 priv->tx_skbuff = kzalloc_objs(*priv->tx_skbuff, priv->tx_ring_size); 213 if (!priv->tx_skbuff) { 214 ret = -ENOMEM; 215 goto free_rx_skbuff; 216 } 217 218 priv->skb_curtx = 0; 219 priv->skb_dirtytx = 0; 220 priv->curtx_bd = priv->tx_bd_base; 221 priv->dirty_tx = priv->tx_bd_base; 222 priv->currx_bd = priv->rx_bd_base; 223 priv->currx_bdnum = 0; 224 225 /* init parameter base */ 226 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 227 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, 228 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); 229 230 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) 231 qe_muram_addr(priv->ucc_pram_offset); 232 233 /* Zero out parameter ram */ 234 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param)); 235 236 /* Alloc riptr, tiptr */ 237 riptr = qe_muram_alloc(32, 32); 238 if (riptr < 0) { 239 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n"); 240 ret = -ENOMEM; 241 goto free_tx_skbuff; 242 } 243 244 tiptr = qe_muram_alloc(32, 32); 245 if (tiptr < 0) { 246 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n"); 247 ret = -ENOMEM; 248 goto free_riptr; 249 } 250 if (riptr != (u16)riptr || tiptr != (u16)tiptr) { 251 dev_err(priv->dev, "MURAM allocation out of addressable range\n"); 252 ret = -ENOMEM; 253 goto free_tiptr; 254 } 255 256 /* Set RIPTR, TIPTR */ 257 iowrite16be(riptr, &priv->ucc_pram->riptr); 258 iowrite16be(tiptr, &priv->ucc_pram->tiptr); 259 260 /* Set MRBLR */ 261 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr); 262 263 /* Set RBASE, TBASE */ 264 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase); 265 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase); 266 267 /* Set RSTATE, TSTATE */ 268 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate); 269 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate); 270 271 /* Set C_MASK, C_PRES for 16bit CRC */ 272 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask); 273 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres); 274 275 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr); 276 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr); 277 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt); 278 iowrite16be(priv->hmask, &priv->ucc_pram->hmask); 279 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1); 280 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2); 281 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3); 282 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4); 283 284 /* Get BD buffer */ 285 bd_buffer = dma_alloc_coherent(priv->dev, 286 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH, 287 &bd_dma_addr, GFP_KERNEL); 288 289 if (!bd_buffer) { 290 dev_err(priv->dev, "Could not allocate buffer descriptors\n"); 291 ret = -ENOMEM; 292 goto free_tiptr; 293 } 294 295 priv->rx_buffer = bd_buffer; 296 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; 297 298 priv->dma_rx_addr = bd_dma_addr; 299 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; 300 301 for (i = 0; i < RX_BD_RING_LEN; i++) { 302 if (i < (RX_BD_RING_LEN - 1)) 303 bd_status = R_E_S | R_I_S; 304 else 305 bd_status = R_E_S | R_I_S | R_W_S; 306 307 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); 308 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); 309 } 310 311 for (i = 0; i < TX_BD_RING_LEN; i++) { 312 if (i < (TX_BD_RING_LEN - 1)) 313 bd_status = T_I_S | T_TC_S; 314 else 315 bd_status = T_I_S | T_TC_S | T_W_S; 316 317 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); 318 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); 319 } 320 dma_wmb(); 321 322 return 0; 323 324 free_tiptr: 325 qe_muram_free(tiptr); 326 free_riptr: 327 qe_muram_free(riptr); 328 free_tx_skbuff: 329 kfree(priv->tx_skbuff); 330 free_rx_skbuff: 331 kfree(priv->rx_skbuff); 332 free_ucc_pram: 333 qe_muram_free(priv->ucc_pram_offset); 334 free_tx_bd: 335 dma_free_coherent(priv->dev, 336 TX_BD_RING_LEN * sizeof(struct qe_bd), 337 priv->tx_bd_base, priv->dma_tx_bd); 338 free_rx_bd: 339 dma_free_coherent(priv->dev, 340 RX_BD_RING_LEN * sizeof(struct qe_bd), 341 priv->rx_bd_base, priv->dma_rx_bd); 342 free_uccf: 343 ucc_fast_free(priv->uccf); 344 345 return ret; 346 } 347 348 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev) 349 { 350 hdlc_device *hdlc = dev_to_hdlc(dev); 351 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv; 352 struct qe_bd *bd; 353 u16 bd_status; 354 unsigned long flags; 355 __be16 *proto_head; 356 357 switch (dev->type) { 358 case ARPHRD_RAWHDLC: 359 if (skb_headroom(skb) < HDLC_HEAD_LEN) { 360 dev->stats.tx_dropped++; 361 dev_kfree_skb(skb); 362 netdev_err(dev, "No enough space for hdlc head\n"); 363 return -ENOMEM; 364 } 365 366 skb_push(skb, HDLC_HEAD_LEN); 367 368 proto_head = (__be16 *)skb->data; 369 *proto_head = htons(DEFAULT_HDLC_HEAD); 370 371 dev->stats.tx_bytes += skb->len; 372 break; 373 374 case ARPHRD_PPP: 375 proto_head = (__be16 *)skb->data; 376 if (*proto_head != htons(DEFAULT_PPP_HEAD)) { 377 dev->stats.tx_dropped++; 378 dev_kfree_skb(skb); 379 netdev_err(dev, "Wrong ppp header\n"); 380 return -ENOMEM; 381 } 382 383 dev->stats.tx_bytes += skb->len; 384 break; 385 386 case ARPHRD_ETHER: 387 dev->stats.tx_bytes += skb->len; 388 break; 389 390 default: 391 dev->stats.tx_dropped++; 392 dev_kfree_skb(skb); 393 return -ENOMEM; 394 } 395 netdev_sent_queue(dev, skb->len); 396 spin_lock_irqsave(&priv->lock, flags); 397 398 dma_rmb(); 399 /* Start from the next BD that should be filled */ 400 bd = priv->curtx_bd; 401 bd_status = be16_to_cpu(bd->status); 402 /* Save the skb pointer so we can free it later */ 403 priv->tx_skbuff[priv->skb_curtx] = skb; 404 405 /* Update the current skb pointer (wrapping if this was the last) */ 406 priv->skb_curtx = 407 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); 408 409 /* copy skb data to tx buffer for sdma processing */ 410 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr), 411 skb->data, skb->len); 412 413 /* set bd status and length */ 414 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S; 415 416 bd->length = cpu_to_be16(skb->len); 417 bd->status = cpu_to_be16(bd_status); 418 419 /* Move to next BD in the ring */ 420 if (!(bd_status & T_W_S)) 421 bd += 1; 422 else 423 bd = priv->tx_bd_base; 424 425 if (bd == priv->dirty_tx) { 426 if (!netif_queue_stopped(dev)) 427 netif_stop_queue(dev); 428 } 429 430 priv->curtx_bd = bd; 431 432 spin_unlock_irqrestore(&priv->lock, flags); 433 434 return NETDEV_TX_OK; 435 } 436 437 static int hdlc_tx_restart(struct ucc_hdlc_private *priv) 438 { 439 u32 cecr_subblock; 440 441 cecr_subblock = 442 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num); 443 444 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, 445 QE_CR_PROTOCOL_UNSPECIFIED, 0); 446 return 0; 447 } 448 449 static int hdlc_tx_done(struct ucc_hdlc_private *priv) 450 { 451 /* Start from the next BD that should be filled */ 452 struct net_device *dev = priv->ndev; 453 unsigned int bytes_sent = 0; 454 int howmany = 0; 455 struct qe_bd *bd; /* BD pointer */ 456 u16 bd_status; 457 int tx_restart = 0; 458 459 dma_rmb(); 460 bd = priv->dirty_tx; 461 bd_status = be16_to_cpu(bd->status); 462 463 /* Normal processing. */ 464 while ((bd_status & T_R_S) == 0) { 465 struct sk_buff *skb; 466 467 if (bd_status & T_UN_S) { /* Underrun */ 468 dev->stats.tx_fifo_errors++; 469 tx_restart = 1; 470 } 471 if (bd_status & T_CT_S) { /* Carrier lost */ 472 dev->stats.tx_carrier_errors++; 473 tx_restart = 1; 474 } 475 476 /* BD contains already transmitted buffer. */ 477 /* Handle the transmitted buffer and release */ 478 /* the BD to be used with the current frame */ 479 480 skb = priv->tx_skbuff[priv->skb_dirtytx]; 481 if (!skb) 482 break; 483 howmany++; 484 bytes_sent += skb->len; 485 dev->stats.tx_packets++; 486 memset(priv->tx_buffer + 487 (be32_to_cpu(bd->buf) - priv->dma_tx_addr), 488 0, skb->len); 489 dev_consume_skb_irq(skb); 490 491 priv->tx_skbuff[priv->skb_dirtytx] = NULL; 492 priv->skb_dirtytx = 493 (priv->skb_dirtytx + 494 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); 495 496 /* We freed a buffer, so now we can restart transmission */ 497 if (netif_queue_stopped(dev)) 498 netif_wake_queue(dev); 499 500 /* Advance the confirmation BD pointer */ 501 if (!(bd_status & T_W_S)) 502 bd += 1; 503 else 504 bd = priv->tx_bd_base; 505 bd_status = be16_to_cpu(bd->status); 506 } 507 priv->dirty_tx = bd; 508 509 if (tx_restart) 510 hdlc_tx_restart(priv); 511 512 netdev_completed_queue(dev, howmany, bytes_sent); 513 return 0; 514 } 515 516 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit) 517 { 518 struct net_device *dev = priv->ndev; 519 struct sk_buff *skb = NULL; 520 hdlc_device *hdlc = dev_to_hdlc(dev); 521 struct qe_bd *bd; 522 u16 bd_status; 523 u16 length, howmany = 0; 524 u8 *bdbuffer; 525 526 dma_rmb(); 527 bd = priv->currx_bd; 528 bd_status = be16_to_cpu(bd->status); 529 530 /* while there are received buffers and BD is full (~R_E) */ 531 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) { 532 if (bd_status & (RX_BD_ERRORS)) { 533 dev->stats.rx_errors++; 534 535 if (bd_status & R_CD_S) 536 dev->stats.collisions++; 537 if (bd_status & R_OV_S) 538 dev->stats.rx_fifo_errors++; 539 if (bd_status & R_CR_S) 540 dev->stats.rx_crc_errors++; 541 if (bd_status & R_AB_S) 542 dev->stats.rx_over_errors++; 543 if (bd_status & R_NO_S) 544 dev->stats.rx_frame_errors++; 545 if (bd_status & R_LG_S) 546 dev->stats.rx_length_errors++; 547 548 goto recycle; 549 } 550 bdbuffer = priv->rx_buffer + 551 (priv->currx_bdnum * MAX_RX_BUF_LENGTH); 552 length = be16_to_cpu(bd->length); 553 554 switch (dev->type) { 555 case ARPHRD_RAWHDLC: 556 bdbuffer += HDLC_HEAD_LEN; 557 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE); 558 559 skb = dev_alloc_skb(length); 560 if (!skb) { 561 dev->stats.rx_dropped++; 562 return -ENOMEM; 563 } 564 565 skb_put(skb, length); 566 skb->len = length; 567 skb->dev = dev; 568 memcpy(skb->data, bdbuffer, length); 569 break; 570 571 case ARPHRD_PPP: 572 case ARPHRD_ETHER: 573 length -= HDLC_CRC_SIZE; 574 575 skb = dev_alloc_skb(length); 576 if (!skb) { 577 dev->stats.rx_dropped++; 578 return -ENOMEM; 579 } 580 581 skb_put(skb, length); 582 skb->len = length; 583 skb->dev = dev; 584 memcpy(skb->data, bdbuffer, length); 585 break; 586 } 587 588 dev->stats.rx_packets++; 589 dev->stats.rx_bytes += skb->len; 590 howmany++; 591 if (hdlc->proto) 592 skb->protocol = hdlc_type_trans(skb, dev); 593 netif_receive_skb(skb); 594 595 recycle: 596 bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S); 597 598 /* update to point at the next bd */ 599 if (bd_status & R_W_S) { 600 priv->currx_bdnum = 0; 601 bd = priv->rx_bd_base; 602 } else { 603 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1)) 604 priv->currx_bdnum += 1; 605 else 606 priv->currx_bdnum = RX_BD_RING_LEN - 1; 607 608 bd += 1; 609 } 610 611 bd_status = be16_to_cpu(bd->status); 612 } 613 dma_rmb(); 614 615 priv->currx_bd = bd; 616 return howmany; 617 } 618 619 static int ucc_hdlc_poll(struct napi_struct *napi, int budget) 620 { 621 struct ucc_hdlc_private *priv = container_of(napi, 622 struct ucc_hdlc_private, 623 napi); 624 int howmany; 625 626 /* Tx event processing */ 627 spin_lock(&priv->lock); 628 hdlc_tx_done(priv); 629 spin_unlock(&priv->lock); 630 631 howmany = 0; 632 howmany += hdlc_rx_done(priv, budget - howmany); 633 634 if (howmany < budget) { 635 napi_complete_done(napi, howmany); 636 qe_setbits_be32(priv->uccf->p_uccm, 637 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16); 638 } 639 640 return howmany; 641 } 642 643 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id) 644 { 645 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id; 646 struct net_device *dev = priv->ndev; 647 struct ucc_fast_private *uccf; 648 u32 ucce; 649 u32 uccm; 650 651 uccf = priv->uccf; 652 653 ucce = ioread32be(uccf->p_ucce); 654 uccm = ioread32be(uccf->p_uccm); 655 ucce &= uccm; 656 iowrite32be(ucce, uccf->p_ucce); 657 if (!ucce) 658 return IRQ_NONE; 659 660 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) { 661 if (napi_schedule_prep(&priv->napi)) { 662 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) 663 << 16); 664 iowrite32be(uccm, uccf->p_uccm); 665 __napi_schedule(&priv->napi); 666 } 667 } 668 669 /* Errors and other events */ 670 if (ucce >> 16 & UCC_HDLC_UCCE_BSY) 671 dev->stats.rx_missed_errors++; 672 if (ucce >> 16 & UCC_HDLC_UCCE_TXE) 673 dev->stats.tx_errors++; 674 675 return IRQ_HANDLED; 676 } 677 678 static int uhdlc_ioctl(struct net_device *dev, struct if_settings *ifs) 679 { 680 const size_t size = sizeof(te1_settings); 681 te1_settings line; 682 struct ucc_hdlc_private *priv = netdev_priv(dev); 683 684 switch (ifs->type) { 685 case IF_GET_IFACE: 686 ifs->type = IF_IFACE_E1; 687 if (ifs->size < size) { 688 ifs->size = size; /* data size wanted */ 689 return -ENOBUFS; 690 } 691 memset(&line, 0, sizeof(line)); 692 line.clock_type = priv->clocking; 693 694 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size)) 695 return -EFAULT; 696 return 0; 697 698 default: 699 return hdlc_ioctl(dev, ifs); 700 } 701 } 702 703 static int uhdlc_open(struct net_device *dev) 704 { 705 u32 cecr_subblock; 706 hdlc_device *hdlc = dev_to_hdlc(dev); 707 struct ucc_hdlc_private *priv = hdlc->priv; 708 struct ucc_tdm *utdm = priv->utdm; 709 int rc = 0; 710 711 if (priv->hdlc_busy != 1) { 712 if (request_irq(priv->ut_info->uf_info.irq, 713 ucc_hdlc_irq_handler, 0, "hdlc", priv)) 714 return -ENODEV; 715 716 cecr_subblock = ucc_fast_get_qe_cr_subblock( 717 priv->ut_info->uf_info.ucc_num); 718 719 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 720 QE_CR_PROTOCOL_UNSPECIFIED, 0); 721 722 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 723 724 /* Enable the TDM port */ 725 if (priv->tsa) 726 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 727 728 priv->hdlc_busy = 1; 729 netif_device_attach(priv->ndev); 730 napi_enable(&priv->napi); 731 netdev_reset_queue(dev); 732 netif_start_queue(dev); 733 734 rc = hdlc_open(dev); 735 if (rc) 736 uhdlc_close(dev); 737 } 738 739 return rc; 740 } 741 742 static void uhdlc_memclean(struct ucc_hdlc_private *priv) 743 { 744 qe_muram_free(ioread16be(&priv->ucc_pram->riptr)); 745 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr)); 746 747 if (priv->rx_bd_base) { 748 dma_free_coherent(priv->dev, 749 RX_BD_RING_LEN * sizeof(struct qe_bd), 750 priv->rx_bd_base, priv->dma_rx_bd); 751 752 priv->rx_bd_base = NULL; 753 priv->dma_rx_bd = 0; 754 } 755 756 if (priv->tx_bd_base) { 757 dma_free_coherent(priv->dev, 758 TX_BD_RING_LEN * sizeof(struct qe_bd), 759 priv->tx_bd_base, priv->dma_tx_bd); 760 761 priv->tx_bd_base = NULL; 762 priv->dma_tx_bd = 0; 763 } 764 765 if (priv->ucc_pram) { 766 qe_muram_free(priv->ucc_pram_offset); 767 priv->ucc_pram = NULL; 768 priv->ucc_pram_offset = 0; 769 } 770 771 kfree(priv->rx_skbuff); 772 priv->rx_skbuff = NULL; 773 774 kfree(priv->tx_skbuff); 775 priv->tx_skbuff = NULL; 776 777 if (priv->uf_regs) { 778 iounmap(priv->uf_regs); 779 priv->uf_regs = NULL; 780 } 781 782 if (priv->uccf) { 783 ucc_fast_free(priv->uccf); 784 priv->uccf = NULL; 785 } 786 787 if (priv->rx_buffer) { 788 dma_free_coherent(priv->dev, 789 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH, 790 priv->rx_buffer, priv->dma_rx_addr); 791 priv->rx_buffer = NULL; 792 priv->dma_rx_addr = 0; 793 794 priv->tx_buffer = NULL; 795 priv->dma_tx_addr = 0; 796 797 } 798 } 799 800 static int uhdlc_close(struct net_device *dev) 801 { 802 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; 803 struct ucc_tdm *utdm = priv->utdm; 804 u32 cecr_subblock; 805 806 napi_disable(&priv->napi); 807 cecr_subblock = ucc_fast_get_qe_cr_subblock( 808 priv->ut_info->uf_info.ucc_num); 809 810 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 811 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 812 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock, 813 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 814 815 if (priv->tsa) 816 qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 817 818 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 819 820 free_irq(priv->ut_info->uf_info.irq, priv); 821 netif_stop_queue(dev); 822 netdev_reset_queue(dev); 823 priv->hdlc_busy = 0; 824 825 hdlc_close(dev); 826 827 return 0; 828 } 829 830 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding, 831 unsigned short parity) 832 { 833 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; 834 835 if (encoding != ENCODING_NRZ && 836 encoding != ENCODING_NRZI) 837 return -EINVAL; 838 839 if (parity != PARITY_NONE && 840 parity != PARITY_CRC32_PR1_CCITT && 841 parity != PARITY_CRC16_PR0_CCITT && 842 parity != PARITY_CRC16_PR1_CCITT) 843 return -EINVAL; 844 845 priv->encoding = encoding; 846 priv->parity = parity; 847 848 return 0; 849 } 850 851 #ifdef CONFIG_PM 852 static void store_clk_config(struct ucc_hdlc_private *priv) 853 { 854 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; 855 856 /* store si clk */ 857 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h); 858 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l); 859 860 /* store si sync */ 861 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr); 862 863 /* store ucc clk */ 864 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32)); 865 } 866 867 static void resume_clk_config(struct ucc_hdlc_private *priv) 868 { 869 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; 870 871 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32)); 872 873 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h); 874 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l); 875 876 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr); 877 } 878 879 static int uhdlc_suspend(struct device *dev) 880 { 881 struct ucc_hdlc_private *priv = dev_get_drvdata(dev); 882 struct ucc_fast __iomem *uf_regs; 883 884 if (!priv) 885 return -EINVAL; 886 887 if (!netif_running(priv->ndev)) 888 return 0; 889 890 netif_device_detach(priv->ndev); 891 napi_disable(&priv->napi); 892 893 uf_regs = priv->uf_regs; 894 895 /* backup gumr guemr*/ 896 priv->gumr = ioread32be(&uf_regs->gumr); 897 priv->guemr = ioread8(&uf_regs->guemr); 898 899 priv->ucc_pram_bak = kmalloc_obj(*priv->ucc_pram_bak); 900 if (!priv->ucc_pram_bak) 901 return -ENOMEM; 902 903 /* backup HDLC parameter */ 904 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram, 905 sizeof(struct ucc_hdlc_param)); 906 907 /* store the clk configuration */ 908 store_clk_config(priv); 909 910 /* save power */ 911 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 912 913 return 0; 914 } 915 916 static int uhdlc_resume(struct device *dev) 917 { 918 struct ucc_hdlc_private *priv = dev_get_drvdata(dev); 919 struct ucc_tdm *utdm; 920 struct ucc_tdm_info *ut_info; 921 struct ucc_fast __iomem *uf_regs; 922 struct ucc_fast_private *uccf; 923 struct ucc_fast_info *uf_info; 924 int i; 925 u32 cecr_subblock; 926 u16 bd_status; 927 928 if (!priv) 929 return -EINVAL; 930 931 if (!netif_running(priv->ndev)) 932 return 0; 933 934 utdm = priv->utdm; 935 ut_info = priv->ut_info; 936 uf_info = &ut_info->uf_info; 937 uf_regs = priv->uf_regs; 938 uccf = priv->uccf; 939 940 /* restore gumr guemr */ 941 iowrite8(priv->guemr, &uf_regs->guemr); 942 iowrite32be(priv->gumr, &uf_regs->gumr); 943 944 /* Set Virtual Fifo registers */ 945 iowrite16be(uf_info->urfs, &uf_regs->urfs); 946 iowrite16be(uf_info->urfet, &uf_regs->urfet); 947 iowrite16be(uf_info->urfset, &uf_regs->urfset); 948 iowrite16be(uf_info->utfs, &uf_regs->utfs); 949 iowrite16be(uf_info->utfet, &uf_regs->utfet); 950 iowrite16be(uf_info->utftt, &uf_regs->utftt); 951 /* utfb, urfb are offsets from MURAM base */ 952 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb); 953 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb); 954 955 /* Rx Tx and sync clock routing */ 956 resume_clk_config(priv); 957 958 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm); 959 iowrite32be(0xffffffff, &uf_regs->ucce); 960 961 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 962 963 /* rebuild SIRAM */ 964 if (priv->tsa) 965 ucc_tdm_init(priv->utdm, priv->ut_info); 966 967 /* Write to QE CECR, UCCx channel to Stop Transmission */ 968 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 969 qe_issue_cmd(QE_STOP_TX, cecr_subblock, 970 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 971 972 /* Set UPSMR normal mode */ 973 iowrite32be(0, &uf_regs->upsmr); 974 975 /* init parameter base */ 976 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 977 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, 978 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); 979 980 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) 981 qe_muram_addr(priv->ucc_pram_offset); 982 983 /* restore ucc parameter */ 984 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak, 985 sizeof(struct ucc_hdlc_param)); 986 kfree(priv->ucc_pram_bak); 987 988 /* rebuild BD entry */ 989 for (i = 0; i < RX_BD_RING_LEN; i++) { 990 if (i < (RX_BD_RING_LEN - 1)) 991 bd_status = R_E_S | R_I_S; 992 else 993 bd_status = R_E_S | R_I_S | R_W_S; 994 995 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); 996 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); 997 } 998 999 for (i = 0; i < TX_BD_RING_LEN; i++) { 1000 if (i < (TX_BD_RING_LEN - 1)) 1001 bd_status = T_I_S | T_TC_S; 1002 else 1003 bd_status = T_I_S | T_TC_S | T_W_S; 1004 1005 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); 1006 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); 1007 } 1008 dma_wmb(); 1009 1010 /* if hdlc is busy enable TX and RX */ 1011 if (priv->hdlc_busy == 1) { 1012 cecr_subblock = ucc_fast_get_qe_cr_subblock( 1013 priv->ut_info->uf_info.ucc_num); 1014 1015 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 1016 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 1017 1018 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 1019 1020 /* Enable the TDM port */ 1021 if (priv->tsa) 1022 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 1023 } 1024 1025 napi_enable(&priv->napi); 1026 netif_device_attach(priv->ndev); 1027 1028 return 0; 1029 } 1030 1031 static const struct dev_pm_ops uhdlc_pm_ops = { 1032 .suspend = uhdlc_suspend, 1033 .resume = uhdlc_resume, 1034 .freeze = uhdlc_suspend, 1035 .thaw = uhdlc_resume, 1036 }; 1037 1038 #define HDLC_PM_OPS (&uhdlc_pm_ops) 1039 1040 #else 1041 1042 #define HDLC_PM_OPS NULL 1043 1044 #endif 1045 static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1046 { 1047 netdev_err(ndev, "%s\n", __func__); 1048 } 1049 1050 static const struct net_device_ops uhdlc_ops = { 1051 .ndo_open = uhdlc_open, 1052 .ndo_stop = uhdlc_close, 1053 .ndo_start_xmit = hdlc_start_xmit, 1054 .ndo_siocwandev = uhdlc_ioctl, 1055 .ndo_tx_timeout = uhdlc_tx_timeout, 1056 }; 1057 1058 static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr) 1059 { 1060 struct device_node *np; 1061 struct platform_device *pdev; 1062 struct resource *res; 1063 static int siram_init_flag; 1064 int ret = 0; 1065 1066 np = of_find_compatible_node(NULL, NULL, name); 1067 if (!np) 1068 return -EINVAL; 1069 1070 pdev = of_find_device_by_node(np); 1071 if (!pdev) { 1072 pr_err("%pOFn: failed to lookup pdev\n", np); 1073 of_node_put(np); 1074 return -EINVAL; 1075 } 1076 1077 of_node_put(np); 1078 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1079 if (!res) { 1080 ret = -EINVAL; 1081 goto error_put_device; 1082 } 1083 *ptr = ioremap(res->start, resource_size(res)); 1084 if (!*ptr) { 1085 ret = -ENOMEM; 1086 goto error_put_device; 1087 } 1088 1089 /* We've remapped the addresses, and we don't need the device any 1090 * more, so we should release it. 1091 */ 1092 put_device(&pdev->dev); 1093 1094 if (init_flag && siram_init_flag == 0) { 1095 memset_io(*ptr, 0, resource_size(res)); 1096 siram_init_flag = 1; 1097 } 1098 return 0; 1099 1100 error_put_device: 1101 put_device(&pdev->dev); 1102 1103 return ret; 1104 } 1105 1106 static int ucc_hdlc_probe(struct platform_device *pdev) 1107 { 1108 struct device_node *np = pdev->dev.of_node; 1109 struct ucc_hdlc_private *uhdlc_priv = NULL; 1110 struct ucc_tdm_info *ut_info; 1111 struct ucc_tdm *utdm = NULL; 1112 struct resource res; 1113 struct net_device *dev; 1114 hdlc_device *hdlc; 1115 int ucc_num; 1116 const char *sprop; 1117 int ret; 1118 u32 val; 1119 1120 ret = of_property_read_u32_index(np, "cell-index", 0, &val); 1121 if (ret) { 1122 dev_err(&pdev->dev, "Invalid ucc property\n"); 1123 return -ENODEV; 1124 } 1125 1126 ucc_num = val - 1; 1127 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) { 1128 dev_err(&pdev->dev, ": Invalid UCC num\n"); 1129 return -EINVAL; 1130 } 1131 1132 memcpy(&utdm_info[ucc_num], &utdm_primary_info, 1133 sizeof(utdm_primary_info)); 1134 1135 ut_info = &utdm_info[ucc_num]; 1136 ut_info->uf_info.ucc_num = ucc_num; 1137 1138 sprop = of_get_property(np, "rx-clock-name", NULL); 1139 if (sprop) { 1140 ut_info->uf_info.rx_clock = qe_clock_source(sprop); 1141 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) || 1142 (ut_info->uf_info.rx_clock > QE_CLK24)) { 1143 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); 1144 return -EINVAL; 1145 } 1146 } else { 1147 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); 1148 return -EINVAL; 1149 } 1150 1151 sprop = of_get_property(np, "tx-clock-name", NULL); 1152 if (sprop) { 1153 ut_info->uf_info.tx_clock = qe_clock_source(sprop); 1154 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) || 1155 (ut_info->uf_info.tx_clock > QE_CLK24)) { 1156 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); 1157 return -EINVAL; 1158 } 1159 } else { 1160 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); 1161 return -EINVAL; 1162 } 1163 1164 ret = of_address_to_resource(np, 0, &res); 1165 if (ret) 1166 return -EINVAL; 1167 1168 ut_info->uf_info.regs = res.start; 1169 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0); 1170 1171 uhdlc_priv = kzalloc_obj(*uhdlc_priv); 1172 if (!uhdlc_priv) 1173 return -ENOMEM; 1174 1175 dev_set_drvdata(&pdev->dev, uhdlc_priv); 1176 uhdlc_priv->dev = &pdev->dev; 1177 uhdlc_priv->ut_info = ut_info; 1178 1179 uhdlc_priv->tsa = of_property_read_bool(np, "fsl,tdm-interface"); 1180 uhdlc_priv->loopback = of_property_read_bool(np, "fsl,ucc-internal-loopback"); 1181 uhdlc_priv->hdlc_bus = of_property_read_bool(np, "fsl,hdlc-bus"); 1182 1183 if (uhdlc_priv->tsa == 1) { 1184 utdm = kzalloc_obj(*utdm); 1185 if (!utdm) { 1186 ret = -ENOMEM; 1187 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n"); 1188 goto free_uhdlc_priv; 1189 } 1190 uhdlc_priv->utdm = utdm; 1191 ret = ucc_of_parse_tdm(np, utdm, ut_info); 1192 if (ret) 1193 goto free_utdm; 1194 1195 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0, 1196 (void __iomem **)&utdm->si_regs); 1197 if (ret) 1198 goto free_utdm; 1199 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1, 1200 (void __iomem **)&utdm->siram); 1201 if (ret) 1202 goto unmap_si_regs; 1203 } 1204 1205 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask)) 1206 uhdlc_priv->hmask = DEFAULT_ADDR_MASK; 1207 1208 ret = uhdlc_init(uhdlc_priv); 1209 if (ret) { 1210 dev_err(&pdev->dev, "Failed to init uhdlc\n"); 1211 goto undo_uhdlc_init; 1212 } 1213 1214 dev = alloc_hdlcdev(uhdlc_priv); 1215 if (!dev) { 1216 ret = -ENOMEM; 1217 pr_err("ucc_hdlc: unable to allocate memory\n"); 1218 goto undo_uhdlc_init; 1219 } 1220 1221 uhdlc_priv->ndev = dev; 1222 hdlc = dev_to_hdlc(dev); 1223 dev->tx_queue_len = 16; 1224 dev->netdev_ops = &uhdlc_ops; 1225 dev->watchdog_timeo = 2 * HZ; 1226 hdlc->attach = ucc_hdlc_attach; 1227 hdlc->xmit = ucc_hdlc_tx; 1228 netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32); 1229 if (register_hdlc_device(dev)) { 1230 ret = -ENOBUFS; 1231 pr_err("ucc_hdlc: unable to register hdlc device\n"); 1232 goto free_dev; 1233 } 1234 1235 return 0; 1236 1237 free_dev: 1238 free_netdev(dev); 1239 undo_uhdlc_init: 1240 if (utdm) 1241 iounmap(utdm->siram); 1242 unmap_si_regs: 1243 if (utdm) 1244 iounmap(utdm->si_regs); 1245 free_utdm: 1246 if (uhdlc_priv->tsa) 1247 kfree(utdm); 1248 free_uhdlc_priv: 1249 kfree(uhdlc_priv); 1250 return ret; 1251 } 1252 1253 static void ucc_hdlc_remove(struct platform_device *pdev) 1254 { 1255 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev); 1256 1257 uhdlc_memclean(priv); 1258 1259 if (priv->utdm->si_regs) { 1260 iounmap(priv->utdm->si_regs); 1261 priv->utdm->si_regs = NULL; 1262 } 1263 1264 if (priv->utdm->siram) { 1265 iounmap(priv->utdm->siram); 1266 priv->utdm->siram = NULL; 1267 } 1268 kfree(priv); 1269 1270 dev_info(&pdev->dev, "UCC based hdlc module removed\n"); 1271 } 1272 1273 static const struct of_device_id fsl_ucc_hdlc_of_match[] = { 1274 { 1275 .compatible = "fsl,ucc-hdlc", 1276 }, 1277 {}, 1278 }; 1279 1280 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match); 1281 1282 static struct platform_driver ucc_hdlc_driver = { 1283 .probe = ucc_hdlc_probe, 1284 .remove = ucc_hdlc_remove, 1285 .driver = { 1286 .name = DRV_NAME, 1287 .pm = HDLC_PM_OPS, 1288 .of_match_table = fsl_ucc_hdlc_of_match, 1289 }, 1290 }; 1291 1292 module_platform_driver(ucc_hdlc_driver); 1293 MODULE_LICENSE("GPL"); 1294 MODULE_DESCRIPTION(DRV_DESC); 1295