1 /* 2 * FarSync WAN driver for Linux (2.6.x kernel version) 3 * 4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards 5 * 6 * Copyright (C) 2001-2004 FarSite Communications Ltd. 7 * www.farsite.co.uk 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> 15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/version.h> 21 #include <linux/pci.h> 22 #include <linux/sched.h> 23 #include <linux/slab.h> 24 #include <linux/ioport.h> 25 #include <linux/init.h> 26 #include <linux/if.h> 27 #include <linux/hdlc.h> 28 #include <asm/io.h> 29 #include <asm/uaccess.h> 30 31 #include "farsync.h" 32 33 /* 34 * Module info 35 */ 36 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); 37 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); 38 MODULE_LICENSE("GPL"); 39 40 /* Driver configuration and global parameters 41 * ========================================== 42 */ 43 44 /* Number of ports (per card) and cards supported 45 */ 46 #define FST_MAX_PORTS 4 47 #define FST_MAX_CARDS 32 48 49 /* Default parameters for the link 50 */ 51 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is 52 * useful */ 53 #define FST_TXQ_DEPTH 16 /* This one is for the buffering 54 * of frames on the way down to the card 55 * so that we can keep the card busy 56 * and maximise throughput 57 */ 58 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control 59 * network layer */ 60 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow 61 * control from network layer */ 62 #define FST_MAX_MTU 8000 /* Huge but possible */ 63 #define FST_DEF_MTU 1500 /* Common sane value */ 64 65 #define FST_TX_TIMEOUT (2*HZ) 66 67 #ifdef ARPHRD_RAWHDLC 68 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ 69 #else 70 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ 71 #endif 72 73 /* 74 * Modules parameters and associated variables 75 */ 76 static int fst_txq_low = FST_LOW_WATER_MARK; 77 static int fst_txq_high = FST_HIGH_WATER_MARK; 78 static int fst_max_reads = 7; 79 static int fst_excluded_cards = 0; 80 static int fst_excluded_list[FST_MAX_CARDS]; 81 82 module_param(fst_txq_low, int, 0); 83 module_param(fst_txq_high, int, 0); 84 module_param(fst_max_reads, int, 0); 85 module_param(fst_excluded_cards, int, 0); 86 module_param_array(fst_excluded_list, int, NULL, 0); 87 88 /* Card shared memory layout 89 * ========================= 90 */ 91 #pragma pack(1) 92 93 /* This information is derived in part from the FarSite FarSync Smc.h 94 * file. Unfortunately various name clashes and the non-portability of the 95 * bit field declarations in that file have meant that I have chosen to 96 * recreate the information here. 97 * 98 * The SMC (Shared Memory Configuration) has a version number that is 99 * incremented every time there is a significant change. This number can 100 * be used to check that we have not got out of step with the firmware 101 * contained in the .CDE files. 102 */ 103 #define SMC_VERSION 24 104 105 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ 106 107 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main 108 * configuration structure */ 109 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA 110 * buffers */ 111 112 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */ 113 #define LEN_RX_BUFFER 8192 114 115 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ 116 #define LEN_SMALL_RX_BUFFER 256 117 118 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ 119 #define NUM_RX_BUFFER 8 120 121 /* Interrupt retry time in milliseconds */ 122 #define INT_RETRY_TIME 2 123 124 /* The Am186CH/CC processors support a SmartDMA mode using circular pools 125 * of buffer descriptors. The structure is almost identical to that used 126 * in the LANCE Ethernet controllers. Details available as PDF from the 127 * AMD web site: http://www.amd.com/products/epd/processors/\ 128 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf 129 */ 130 struct txdesc { /* Transmit descriptor */ 131 volatile u16 ladr; /* Low order address of packet. This is a 132 * linear address in the Am186 memory space 133 */ 134 volatile u8 hadr; /* High order address. Low 4 bits only, high 4 135 * bits must be zero 136 */ 137 volatile u8 bits; /* Status and config */ 138 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. 139 * Transmit terminal count interrupt enable in 140 * top bit. 141 */ 142 u16 unused; /* Not used in Tx */ 143 }; 144 145 struct rxdesc { /* Receive descriptor */ 146 volatile u16 ladr; /* Low order address of packet */ 147 volatile u8 hadr; /* High order address */ 148 volatile u8 bits; /* Status and config */ 149 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. 150 * Receive terminal count interrupt enable in 151 * top bit. 152 */ 153 volatile u16 mcnt; /* Message byte count (15 bits) */ 154 }; 155 156 /* Convert a length into the 15 bit 2's complement */ 157 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ 158 /* Since we need to set the high bit to enable the completion interrupt this 159 * can be made a lot simpler 160 */ 161 #define cnv_bcnt(len) (-(len)) 162 163 /* Status and config bits for the above */ 164 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ 165 #define TX_STP 0x02 /* Tx: start of packet */ 166 #define TX_ENP 0x01 /* Tx: end of packet */ 167 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ 168 #define RX_FRAM 0x20 /* Rx: framing error */ 169 #define RX_OFLO 0x10 /* Rx: overflow error */ 170 #define RX_CRC 0x08 /* Rx: CRC error */ 171 #define RX_HBUF 0x04 /* Rx: buffer error */ 172 #define RX_STP 0x02 /* Rx: start of packet */ 173 #define RX_ENP 0x01 /* Rx: end of packet */ 174 175 /* Interrupts from the card are caused by various events which are presented 176 * in a circular buffer as several events may be processed on one physical int 177 */ 178 #define MAX_CIRBUFF 32 179 180 struct cirbuff { 181 u8 rdindex; /* read, then increment and wrap */ 182 u8 wrindex; /* write, then increment and wrap */ 183 u8 evntbuff[MAX_CIRBUFF]; 184 }; 185 186 /* Interrupt event codes. 187 * Where appropriate the two low order bits indicate the port number 188 */ 189 #define CTLA_CHG 0x18 /* Control signal changed */ 190 #define CTLB_CHG 0x19 191 #define CTLC_CHG 0x1A 192 #define CTLD_CHG 0x1B 193 194 #define INIT_CPLT 0x20 /* Initialisation complete */ 195 #define INIT_FAIL 0x21 /* Initialisation failed */ 196 197 #define ABTA_SENT 0x24 /* Abort sent */ 198 #define ABTB_SENT 0x25 199 #define ABTC_SENT 0x26 200 #define ABTD_SENT 0x27 201 202 #define TXA_UNDF 0x28 /* Transmission underflow */ 203 #define TXB_UNDF 0x29 204 #define TXC_UNDF 0x2A 205 #define TXD_UNDF 0x2B 206 207 #define F56_INT 0x2C 208 #define M32_INT 0x2D 209 210 #define TE1_ALMA 0x30 211 212 /* Port physical configuration. See farsync.h for field values */ 213 struct port_cfg { 214 u16 lineInterface; /* Physical interface type */ 215 u8 x25op; /* Unused at present */ 216 u8 internalClock; /* 1 => internal clock, 0 => external */ 217 u8 transparentMode; /* 1 => on, 0 => off */ 218 u8 invertClock; /* 0 => normal, 1 => inverted */ 219 u8 padBytes[6]; /* Padding */ 220 u32 lineSpeed; /* Speed in bps */ 221 }; 222 223 /* TE1 port physical configuration */ 224 struct su_config { 225 u32 dataRate; 226 u8 clocking; 227 u8 framing; 228 u8 structure; 229 u8 interface; 230 u8 coding; 231 u8 lineBuildOut; 232 u8 equalizer; 233 u8 transparentMode; 234 u8 loopMode; 235 u8 range; 236 u8 txBufferMode; 237 u8 rxBufferMode; 238 u8 startingSlot; 239 u8 losThreshold; 240 u8 enableIdleCode; 241 u8 idleCode; 242 u8 spare[44]; 243 }; 244 245 /* TE1 Status */ 246 struct su_status { 247 u32 receiveBufferDelay; 248 u32 framingErrorCount; 249 u32 codeViolationCount; 250 u32 crcErrorCount; 251 u32 lineAttenuation; 252 u8 portStarted; 253 u8 lossOfSignal; 254 u8 receiveRemoteAlarm; 255 u8 alarmIndicationSignal; 256 u8 spare[40]; 257 }; 258 259 /* Finally sling all the above together into the shared memory structure. 260 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been 261 * evolving under NT for some time so I guess we're stuck with it. 262 * The structure starts at offset SMC_BASE. 263 * See farsync.h for some field values. 264 */ 265 struct fst_shared { 266 /* DMA descriptor rings */ 267 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; 268 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; 269 270 /* Obsolete small buffers */ 271 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; 272 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; 273 274 u8 taskStatus; /* 0x00 => initialising, 0x01 => running, 275 * 0xFF => halted 276 */ 277 278 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, 279 * set to 0xEE by host to acknowledge interrupt 280 */ 281 282 u16 smcVersion; /* Must match SMC_VERSION */ 283 284 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major 285 * version, RR = revision and BB = build 286 */ 287 288 u16 txa_done; /* Obsolete completion flags */ 289 u16 rxa_done; 290 u16 txb_done; 291 u16 rxb_done; 292 u16 txc_done; 293 u16 rxc_done; 294 u16 txd_done; 295 u16 rxd_done; 296 297 u16 mailbox[4]; /* Diagnostics mailbox. Not used */ 298 299 struct cirbuff interruptEvent; /* interrupt causes */ 300 301 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ 302 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ 303 304 struct port_cfg portConfig[FST_MAX_PORTS]; 305 306 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ 307 308 u16 cableStatus; /* lsb: 0=> present, 1=> absent */ 309 310 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ 311 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ 312 313 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ 314 u16 cardMailbox[4]; /* Not used */ 315 316 /* Number of times the card thinks the host has 317 * missed an interrupt by not acknowledging 318 * within 2mS (I guess NT has problems) 319 */ 320 u32 interruptRetryCount; 321 322 /* Driver private data used as an ID. We'll not 323 * use this as I'd rather keep such things 324 * in main memory rather than on the PCI bus 325 */ 326 u32 portHandle[FST_MAX_PORTS]; 327 328 /* Count of Tx underflows for stats */ 329 u32 transmitBufferUnderflow[FST_MAX_PORTS]; 330 331 /* Debounced V.24 control input status */ 332 u32 v24DebouncedSts[FST_MAX_PORTS]; 333 334 /* Adapter debounce timers. Don't touch */ 335 u32 ctsTimer[FST_MAX_PORTS]; 336 u32 ctsTimerRun[FST_MAX_PORTS]; 337 u32 dcdTimer[FST_MAX_PORTS]; 338 u32 dcdTimerRun[FST_MAX_PORTS]; 339 340 u32 numberOfPorts; /* Number of ports detected at startup */ 341 342 u16 _reserved[64]; 343 344 u16 cardMode; /* Bit-mask to enable features: 345 * Bit 0: 1 enables LED identify mode 346 */ 347 348 u16 portScheduleOffset; 349 350 struct su_config suConfig; /* TE1 Bits */ 351 struct su_status suStatus; 352 353 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of 354 * the structure and marks the end of shared 355 * memory. Adapter code initializes it as 356 * END_SIG. 357 */ 358 }; 359 360 /* endOfSmcSignature value */ 361 #define END_SIG 0x12345678 362 363 /* Mailbox values. (portMailbox) */ 364 #define NOP 0 /* No operation */ 365 #define ACK 1 /* Positive acknowledgement to PC driver */ 366 #define NAK 2 /* Negative acknowledgement to PC driver */ 367 #define STARTPORT 3 /* Start an HDLC port */ 368 #define STOPPORT 4 /* Stop an HDLC port */ 369 #define ABORTTX 5 /* Abort the transmitter for a port */ 370 #define SETV24O 6 /* Set V24 outputs */ 371 372 /* PLX Chip Register Offsets */ 373 #define CNTRL_9052 0x50 /* Control Register */ 374 #define CNTRL_9054 0x6c /* Control Register */ 375 376 #define INTCSR_9052 0x4c /* Interrupt control/status register */ 377 #define INTCSR_9054 0x68 /* Interrupt control/status register */ 378 379 /* 9054 DMA Registers */ 380 /* 381 * Note that we will be using DMA Channel 0 for copying rx data 382 * and Channel 1 for copying tx data 383 */ 384 #define DMAMODE0 0x80 385 #define DMAPADR0 0x84 386 #define DMALADR0 0x88 387 #define DMASIZ0 0x8c 388 #define DMADPR0 0x90 389 #define DMAMODE1 0x94 390 #define DMAPADR1 0x98 391 #define DMALADR1 0x9c 392 #define DMASIZ1 0xa0 393 #define DMADPR1 0xa4 394 #define DMACSR0 0xa8 395 #define DMACSR1 0xa9 396 #define DMAARB 0xac 397 #define DMATHR 0xb0 398 #define DMADAC0 0xb4 399 #define DMADAC1 0xb8 400 #define DMAMARBR 0xac 401 402 #define FST_MIN_DMA_LEN 64 403 #define FST_RX_DMA_INT 0x01 404 #define FST_TX_DMA_INT 0x02 405 #define FST_CARD_INT 0x04 406 407 /* Larger buffers are positioned in memory at offset BFM_BASE */ 408 struct buf_window { 409 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; 410 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; 411 }; 412 413 /* Calculate offset of a buffer object within the shared memory window */ 414 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) 415 416 #pragma pack() 417 418 /* Device driver private information 419 * ================================= 420 */ 421 /* Per port (line or channel) information 422 */ 423 struct fst_port_info { 424 struct net_device *dev; /* Device struct - must be first */ 425 struct fst_card_info *card; /* Card we're associated with */ 426 int index; /* Port index on the card */ 427 int hwif; /* Line hardware (lineInterface copy) */ 428 int run; /* Port is running */ 429 int mode; /* Normal or FarSync raw */ 430 int rxpos; /* Next Rx buffer to use */ 431 int txpos; /* Next Tx buffer to use */ 432 int txipos; /* Next Tx buffer to check for free */ 433 int start; /* Indication of start/stop to network */ 434 /* 435 * A sixteen entry transmit queue 436 */ 437 int txqs; /* index to get next buffer to tx */ 438 int txqe; /* index to queue next packet */ 439 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ 440 int rxqdepth; 441 }; 442 443 /* Per card information 444 */ 445 struct fst_card_info { 446 char __iomem *mem; /* Card memory mapped to kernel space */ 447 char __iomem *ctlmem; /* Control memory for PCI cards */ 448 unsigned int phys_mem; /* Physical memory window address */ 449 unsigned int phys_ctlmem; /* Physical control memory address */ 450 unsigned int irq; /* Interrupt request line number */ 451 unsigned int nports; /* Number of serial ports */ 452 unsigned int type; /* Type index of card */ 453 unsigned int state; /* State of card */ 454 spinlock_t card_lock; /* Lock for SMP access */ 455 unsigned short pci_conf; /* PCI card config in I/O space */ 456 /* Per port info */ 457 struct fst_port_info ports[FST_MAX_PORTS]; 458 struct pci_dev *device; /* Information about the pci device */ 459 int card_no; /* Inst of the card on the system */ 460 int family; /* TxP or TxU */ 461 int dmarx_in_progress; 462 int dmatx_in_progress; 463 unsigned long int_count; 464 unsigned long int_time_ave; 465 void *rx_dma_handle_host; 466 dma_addr_t rx_dma_handle_card; 467 void *tx_dma_handle_host; 468 dma_addr_t tx_dma_handle_card; 469 struct sk_buff *dma_skb_rx; 470 struct fst_port_info *dma_port_rx; 471 struct fst_port_info *dma_port_tx; 472 int dma_len_rx; 473 int dma_len_tx; 474 int dma_txpos; 475 int dma_rxpos; 476 }; 477 478 /* Convert an HDLC device pointer into a port info pointer and similar */ 479 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 480 #define port_to_dev(P) ((P)->dev) 481 482 483 /* 484 * Shared memory window access macros 485 * 486 * We have a nice memory based structure above, which could be directly 487 * mapped on i386 but might not work on other architectures unless we use 488 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take 489 * physical offsets so we have to convert. The only saving grace is that 490 * this should all collapse back to a simple indirection eventually. 491 */ 492 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) 493 494 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) 495 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) 496 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) 497 498 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) 499 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) 500 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) 501 502 /* 503 * Debug support 504 */ 505 #if FST_DEBUG 506 507 static int fst_debug_mask = { FST_DEBUG }; 508 509 /* Most common debug activity is to print something if the corresponding bit 510 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to 511 * support variable numbers of macro parameters. The inverted if prevents us 512 * eating someone else's else clause. 513 */ 514 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \ 515 ; \ 516 else \ 517 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A ) 518 519 #else 520 #define dbg(X...) /* NOP */ 521 #endif 522 523 /* Printing short cuts 524 */ 525 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A ) 526 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A ) 527 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A ) 528 529 /* 530 * PCI ID lookup table 531 */ 532 static DEFINE_PCI_DEVICE_TABLE(fst_pci_dev_id) = { 533 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, 534 PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, 535 536 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, 537 PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, 538 539 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, 540 PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, 541 542 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, 543 PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, 544 545 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, 546 PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, 547 548 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, 549 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 550 551 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, 552 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 553 {0,} /* End */ 554 }; 555 556 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); 557 558 /* 559 * Device Driver Work Queues 560 * 561 * So that we don't spend too much time processing events in the 562 * Interrupt Service routine, we will declare a work queue per Card 563 * and make the ISR schedule a task in the queue for later execution. 564 * In the 2.4 Kernel we used to use the immediate queue for BH's 565 * Now that they are gone, tasklets seem to be much better than work 566 * queues. 567 */ 568 569 static void do_bottom_half_tx(struct fst_card_info *card); 570 static void do_bottom_half_rx(struct fst_card_info *card); 571 static void fst_process_tx_work_q(unsigned long work_q); 572 static void fst_process_int_work_q(unsigned long work_q); 573 574 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0); 575 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0); 576 577 static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; 578 static spinlock_t fst_work_q_lock; 579 static u64 fst_work_txq; 580 static u64 fst_work_intq; 581 582 static void 583 fst_q_work_item(u64 * queue, int card_index) 584 { 585 unsigned long flags; 586 u64 mask; 587 588 /* 589 * Grab the queue exclusively 590 */ 591 spin_lock_irqsave(&fst_work_q_lock, flags); 592 593 /* 594 * Making an entry in the queue is simply a matter of setting 595 * a bit for the card indicating that there is work to do in the 596 * bottom half for the card. Note the limitation of 64 cards. 597 * That ought to be enough 598 */ 599 mask = 1 << card_index; 600 *queue |= mask; 601 spin_unlock_irqrestore(&fst_work_q_lock, flags); 602 } 603 604 static void 605 fst_process_tx_work_q(unsigned long /*void **/work_q) 606 { 607 unsigned long flags; 608 u64 work_txq; 609 int i; 610 611 /* 612 * Grab the queue exclusively 613 */ 614 dbg(DBG_TX, "fst_process_tx_work_q\n"); 615 spin_lock_irqsave(&fst_work_q_lock, flags); 616 work_txq = fst_work_txq; 617 fst_work_txq = 0; 618 spin_unlock_irqrestore(&fst_work_q_lock, flags); 619 620 /* 621 * Call the bottom half for each card with work waiting 622 */ 623 for (i = 0; i < FST_MAX_CARDS; i++) { 624 if (work_txq & 0x01) { 625 if (fst_card_array[i] != NULL) { 626 dbg(DBG_TX, "Calling tx bh for card %d\n", i); 627 do_bottom_half_tx(fst_card_array[i]); 628 } 629 } 630 work_txq = work_txq >> 1; 631 } 632 } 633 634 static void 635 fst_process_int_work_q(unsigned long /*void **/work_q) 636 { 637 unsigned long flags; 638 u64 work_intq; 639 int i; 640 641 /* 642 * Grab the queue exclusively 643 */ 644 dbg(DBG_INTR, "fst_process_int_work_q\n"); 645 spin_lock_irqsave(&fst_work_q_lock, flags); 646 work_intq = fst_work_intq; 647 fst_work_intq = 0; 648 spin_unlock_irqrestore(&fst_work_q_lock, flags); 649 650 /* 651 * Call the bottom half for each card with work waiting 652 */ 653 for (i = 0; i < FST_MAX_CARDS; i++) { 654 if (work_intq & 0x01) { 655 if (fst_card_array[i] != NULL) { 656 dbg(DBG_INTR, 657 "Calling rx & tx bh for card %d\n", i); 658 do_bottom_half_rx(fst_card_array[i]); 659 do_bottom_half_tx(fst_card_array[i]); 660 } 661 } 662 work_intq = work_intq >> 1; 663 } 664 } 665 666 /* Card control functions 667 * ====================== 668 */ 669 /* Place the processor in reset state 670 * 671 * Used to be a simple write to card control space but a glitch in the latest 672 * AMD Am186CH processor means that we now have to do it by asserting and de- 673 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register 674 * at offset 9052_CNTRL. Note the updates for the TXU. 675 */ 676 static inline void 677 fst_cpureset(struct fst_card_info *card) 678 { 679 unsigned char interrupt_line_register; 680 unsigned long j = jiffies + 1; 681 unsigned int regval; 682 683 if (card->family == FST_FAMILY_TXU) { 684 if (pci_read_config_byte 685 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { 686 dbg(DBG_ASS, 687 "Error in reading interrupt line register\n"); 688 } 689 /* 690 * Assert PLX software reset and Am186 hardware reset 691 * and then deassert the PLX software reset but 186 still in reset 692 */ 693 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); 694 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 695 /* 696 * We are delaying here to allow the 9054 to reset itself 697 */ 698 j = jiffies + 1; 699 while (jiffies < j) 700 /* Do nothing */ ; 701 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); 702 /* 703 * We are delaying here to allow the 9054 to reload its eeprom 704 */ 705 j = jiffies + 1; 706 while (jiffies < j) 707 /* Do nothing */ ; 708 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 709 710 if (pci_write_config_byte 711 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { 712 dbg(DBG_ASS, 713 "Error in writing interrupt line register\n"); 714 } 715 716 } else { 717 regval = inl(card->pci_conf + CNTRL_9052); 718 719 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); 720 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); 721 } 722 } 723 724 /* Release the processor from reset 725 */ 726 static inline void 727 fst_cpurelease(struct fst_card_info *card) 728 { 729 if (card->family == FST_FAMILY_TXU) { 730 /* 731 * Force posted writes to complete 732 */ 733 (void) readb(card->mem); 734 735 /* 736 * Release LRESET DO = 1 737 * Then release Local Hold, DO = 1 738 */ 739 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); 740 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 741 } else { 742 (void) readb(card->ctlmem); 743 } 744 } 745 746 /* Clear the cards interrupt flag 747 */ 748 static inline void 749 fst_clear_intr(struct fst_card_info *card) 750 { 751 if (card->family == FST_FAMILY_TXU) { 752 (void) readb(card->ctlmem); 753 } else { 754 /* Poke the appropriate PLX chip register (same as enabling interrupts) 755 */ 756 outw(0x0543, card->pci_conf + INTCSR_9052); 757 } 758 } 759 760 /* Enable card interrupts 761 */ 762 static inline void 763 fst_enable_intr(struct fst_card_info *card) 764 { 765 if (card->family == FST_FAMILY_TXU) { 766 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); 767 } else { 768 outw(0x0543, card->pci_conf + INTCSR_9052); 769 } 770 } 771 772 /* Disable card interrupts 773 */ 774 static inline void 775 fst_disable_intr(struct fst_card_info *card) 776 { 777 if (card->family == FST_FAMILY_TXU) { 778 outl(0x00000000, card->pci_conf + INTCSR_9054); 779 } else { 780 outw(0x0000, card->pci_conf + INTCSR_9052); 781 } 782 } 783 784 /* Process the result of trying to pass a received frame up the stack 785 */ 786 static void 787 fst_process_rx_status(int rx_status, char *name) 788 { 789 switch (rx_status) { 790 case NET_RX_SUCCESS: 791 { 792 /* 793 * Nothing to do here 794 */ 795 break; 796 } 797 case NET_RX_DROP: 798 { 799 dbg(DBG_ASS, "%s: Received packet dropped\n", name); 800 break; 801 } 802 } 803 } 804 805 /* Initilaise DMA for PLX 9054 806 */ 807 static inline void 808 fst_init_dma(struct fst_card_info *card) 809 { 810 /* 811 * This is only required for the PLX 9054 812 */ 813 if (card->family == FST_FAMILY_TXU) { 814 pci_set_master(card->device); 815 outl(0x00020441, card->pci_conf + DMAMODE0); 816 outl(0x00020441, card->pci_conf + DMAMODE1); 817 outl(0x0, card->pci_conf + DMATHR); 818 } 819 } 820 821 /* Tx dma complete interrupt 822 */ 823 static void 824 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 825 int len, int txpos) 826 { 827 struct net_device *dev = port_to_dev(port); 828 829 /* 830 * Everything is now set, just tell the card to go 831 */ 832 dbg(DBG_TX, "fst_tx_dma_complete\n"); 833 FST_WRB(card, txDescrRing[port->index][txpos].bits, 834 DMA_OWN | TX_STP | TX_ENP); 835 dev->stats.tx_packets++; 836 dev->stats.tx_bytes += len; 837 dev->trans_start = jiffies; 838 } 839 840 /* 841 * Mark it for our own raw sockets interface 842 */ 843 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) 844 { 845 skb->dev = dev; 846 skb_reset_mac_header(skb); 847 skb->pkt_type = PACKET_HOST; 848 return htons(ETH_P_CUST); 849 } 850 851 /* Rx dma complete interrupt 852 */ 853 static void 854 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 855 int len, struct sk_buff *skb, int rxp) 856 { 857 struct net_device *dev = port_to_dev(port); 858 int pi; 859 int rx_status; 860 861 dbg(DBG_TX, "fst_rx_dma_complete\n"); 862 pi = port->index; 863 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len); 864 865 /* Reset buffer descriptor */ 866 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 867 868 /* Update stats */ 869 dev->stats.rx_packets++; 870 dev->stats.rx_bytes += len; 871 872 /* Push upstream */ 873 dbg(DBG_RX, "Pushing the frame up the stack\n"); 874 if (port->mode == FST_RAW) 875 skb->protocol = farsync_type_trans(skb, dev); 876 else 877 skb->protocol = hdlc_type_trans(skb, dev); 878 rx_status = netif_rx(skb); 879 fst_process_rx_status(rx_status, port_to_dev(port)->name); 880 if (rx_status == NET_RX_DROP) 881 dev->stats.rx_dropped++; 882 } 883 884 /* 885 * Receive a frame through the DMA 886 */ 887 static inline void 888 fst_rx_dma(struct fst_card_info *card, unsigned char *skb, 889 unsigned char *mem, int len) 890 { 891 /* 892 * This routine will setup the DMA and start it 893 */ 894 895 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len); 896 if (card->dmarx_in_progress) { 897 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); 898 } 899 900 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */ 901 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */ 902 outl(len, card->pci_conf + DMASIZ0); /* for this length */ 903 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ 904 905 /* 906 * We use the dmarx_in_progress flag to flag the channel as busy 907 */ 908 card->dmarx_in_progress = 1; 909 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ 910 } 911 912 /* 913 * Send a frame through the DMA 914 */ 915 static inline void 916 fst_tx_dma(struct fst_card_info *card, unsigned char *skb, 917 unsigned char *mem, int len) 918 { 919 /* 920 * This routine will setup the DMA and start it. 921 */ 922 923 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len); 924 if (card->dmatx_in_progress) { 925 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); 926 } 927 928 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */ 929 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */ 930 outl(len, card->pci_conf + DMASIZ1); /* for this length */ 931 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ 932 933 /* 934 * We use the dmatx_in_progress to flag the channel as busy 935 */ 936 card->dmatx_in_progress = 1; 937 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ 938 } 939 940 /* Issue a Mailbox command for a port. 941 * Note we issue them on a fire and forget basis, not expecting to see an 942 * error and not waiting for completion. 943 */ 944 static void 945 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) 946 { 947 struct fst_card_info *card; 948 unsigned short mbval; 949 unsigned long flags; 950 int safety; 951 952 card = port->card; 953 spin_lock_irqsave(&card->card_lock, flags); 954 mbval = FST_RDW(card, portMailbox[port->index][0]); 955 956 safety = 0; 957 /* Wait for any previous command to complete */ 958 while (mbval > NAK) { 959 spin_unlock_irqrestore(&card->card_lock, flags); 960 schedule_timeout_uninterruptible(1); 961 spin_lock_irqsave(&card->card_lock, flags); 962 963 if (++safety > 2000) { 964 printk_err("Mailbox safety timeout\n"); 965 break; 966 } 967 968 mbval = FST_RDW(card, portMailbox[port->index][0]); 969 } 970 if (safety > 0) { 971 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); 972 } 973 if (mbval == NAK) { 974 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); 975 } 976 977 FST_WRW(card, portMailbox[port->index][0], cmd); 978 979 if (cmd == ABORTTX || cmd == STARTPORT) { 980 port->txpos = 0; 981 port->txipos = 0; 982 port->start = 0; 983 } 984 985 spin_unlock_irqrestore(&card->card_lock, flags); 986 } 987 988 /* Port output signals control 989 */ 990 static inline void 991 fst_op_raise(struct fst_port_info *port, unsigned int outputs) 992 { 993 outputs |= FST_RDL(port->card, v24OpSts[port->index]); 994 FST_WRL(port->card, v24OpSts[port->index], outputs); 995 996 if (port->run) 997 fst_issue_cmd(port, SETV24O); 998 } 999 1000 static inline void 1001 fst_op_lower(struct fst_port_info *port, unsigned int outputs) 1002 { 1003 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); 1004 FST_WRL(port->card, v24OpSts[port->index], outputs); 1005 1006 if (port->run) 1007 fst_issue_cmd(port, SETV24O); 1008 } 1009 1010 /* 1011 * Setup port Rx buffers 1012 */ 1013 static void 1014 fst_rx_config(struct fst_port_info *port) 1015 { 1016 int i; 1017 int pi; 1018 unsigned int offset; 1019 unsigned long flags; 1020 struct fst_card_info *card; 1021 1022 pi = port->index; 1023 card = port->card; 1024 spin_lock_irqsave(&card->card_lock, flags); 1025 for (i = 0; i < NUM_RX_BUFFER; i++) { 1026 offset = BUF_OFFSET(rxBuffer[pi][i][0]); 1027 1028 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); 1029 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1030 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); 1031 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); 1032 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); 1033 } 1034 port->rxpos = 0; 1035 spin_unlock_irqrestore(&card->card_lock, flags); 1036 } 1037 1038 /* 1039 * Setup port Tx buffers 1040 */ 1041 static void 1042 fst_tx_config(struct fst_port_info *port) 1043 { 1044 int i; 1045 int pi; 1046 unsigned int offset; 1047 unsigned long flags; 1048 struct fst_card_info *card; 1049 1050 pi = port->index; 1051 card = port->card; 1052 spin_lock_irqsave(&card->card_lock, flags); 1053 for (i = 0; i < NUM_TX_BUFFER; i++) { 1054 offset = BUF_OFFSET(txBuffer[pi][i][0]); 1055 1056 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); 1057 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1058 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); 1059 FST_WRB(card, txDescrRing[pi][i].bits, 0); 1060 } 1061 port->txpos = 0; 1062 port->txipos = 0; 1063 port->start = 0; 1064 spin_unlock_irqrestore(&card->card_lock, flags); 1065 } 1066 1067 /* TE1 Alarm change interrupt event 1068 */ 1069 static void 1070 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) 1071 { 1072 u8 los; 1073 u8 rra; 1074 u8 ais; 1075 1076 los = FST_RDB(card, suStatus.lossOfSignal); 1077 rra = FST_RDB(card, suStatus.receiveRemoteAlarm); 1078 ais = FST_RDB(card, suStatus.alarmIndicationSignal); 1079 1080 if (los) { 1081 /* 1082 * Lost the link 1083 */ 1084 if (netif_carrier_ok(port_to_dev(port))) { 1085 dbg(DBG_INTR, "Net carrier off\n"); 1086 netif_carrier_off(port_to_dev(port)); 1087 } 1088 } else { 1089 /* 1090 * Link available 1091 */ 1092 if (!netif_carrier_ok(port_to_dev(port))) { 1093 dbg(DBG_INTR, "Net carrier on\n"); 1094 netif_carrier_on(port_to_dev(port)); 1095 } 1096 } 1097 1098 if (los) 1099 dbg(DBG_INTR, "Assert LOS Alarm\n"); 1100 else 1101 dbg(DBG_INTR, "De-assert LOS Alarm\n"); 1102 if (rra) 1103 dbg(DBG_INTR, "Assert RRA Alarm\n"); 1104 else 1105 dbg(DBG_INTR, "De-assert RRA Alarm\n"); 1106 1107 if (ais) 1108 dbg(DBG_INTR, "Assert AIS Alarm\n"); 1109 else 1110 dbg(DBG_INTR, "De-assert AIS Alarm\n"); 1111 } 1112 1113 /* Control signal change interrupt event 1114 */ 1115 static void 1116 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) 1117 { 1118 int signals; 1119 1120 signals = FST_RDL(card, v24DebouncedSts[port->index]); 1121 1122 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 1123 ? IPSTS_INDICATE : IPSTS_DCD)) { 1124 if (!netif_carrier_ok(port_to_dev(port))) { 1125 dbg(DBG_INTR, "DCD active\n"); 1126 netif_carrier_on(port_to_dev(port)); 1127 } 1128 } else { 1129 if (netif_carrier_ok(port_to_dev(port))) { 1130 dbg(DBG_INTR, "DCD lost\n"); 1131 netif_carrier_off(port_to_dev(port)); 1132 } 1133 } 1134 } 1135 1136 /* Log Rx Errors 1137 */ 1138 static void 1139 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1140 unsigned char dmabits, int rxp, unsigned short len) 1141 { 1142 struct net_device *dev = port_to_dev(port); 1143 1144 /* 1145 * Increment the appropriate error counter 1146 */ 1147 dev->stats.rx_errors++; 1148 if (dmabits & RX_OFLO) { 1149 dev->stats.rx_fifo_errors++; 1150 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1151 card->card_no, port->index, rxp); 1152 } 1153 if (dmabits & RX_CRC) { 1154 dev->stats.rx_crc_errors++; 1155 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1156 card->card_no, port->index); 1157 } 1158 if (dmabits & RX_FRAM) { 1159 dev->stats.rx_frame_errors++; 1160 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1161 card->card_no, port->index); 1162 } 1163 if (dmabits == (RX_STP | RX_ENP)) { 1164 dev->stats.rx_length_errors++; 1165 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1166 len, card->card_no, port->index); 1167 } 1168 } 1169 1170 /* Rx Error Recovery 1171 */ 1172 static void 1173 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1174 unsigned char dmabits, int rxp, unsigned short len) 1175 { 1176 int i; 1177 int pi; 1178 1179 pi = port->index; 1180 /* 1181 * Discard buffer descriptors until we see the start of the 1182 * next frame. Note that for long frames this could be in 1183 * a subsequent interrupt. 1184 */ 1185 i = 0; 1186 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { 1187 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1188 rxp = (rxp+1) % NUM_RX_BUFFER; 1189 if (++i > NUM_RX_BUFFER) { 1190 dbg(DBG_ASS, "intr_rx: Discarding more bufs" 1191 " than we have\n"); 1192 break; 1193 } 1194 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1195 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); 1196 } 1197 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); 1198 1199 /* Discard the terminal buffer */ 1200 if (!(dmabits & DMA_OWN)) { 1201 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1202 rxp = (rxp+1) % NUM_RX_BUFFER; 1203 } 1204 port->rxpos = rxp; 1205 return; 1206 1207 } 1208 1209 /* Rx complete interrupt 1210 */ 1211 static void 1212 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) 1213 { 1214 unsigned char dmabits; 1215 int pi; 1216 int rxp; 1217 int rx_status; 1218 unsigned short len; 1219 struct sk_buff *skb; 1220 struct net_device *dev = port_to_dev(port); 1221 1222 /* Check we have a buffer to process */ 1223 pi = port->index; 1224 rxp = port->rxpos; 1225 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1226 if (dmabits & DMA_OWN) { 1227 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", 1228 pi, rxp); 1229 return; 1230 } 1231 if (card->dmarx_in_progress) { 1232 return; 1233 } 1234 1235 /* Get buffer length */ 1236 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); 1237 /* Discard the CRC */ 1238 len -= 2; 1239 if (len == 0) { 1240 /* 1241 * This seems to happen on the TE1 interface sometimes 1242 * so throw the frame away and log the event. 1243 */ 1244 printk_err("Frame received with 0 length. Card %d Port %d\n", 1245 card->card_no, port->index); 1246 /* Return descriptor to card */ 1247 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1248 1249 rxp = (rxp+1) % NUM_RX_BUFFER; 1250 port->rxpos = rxp; 1251 return; 1252 } 1253 1254 /* Check buffer length and for other errors. We insist on one packet 1255 * in one buffer. This simplifies things greatly and since we've 1256 * allocated 8K it shouldn't be a real world limitation 1257 */ 1258 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); 1259 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { 1260 fst_log_rx_error(card, port, dmabits, rxp, len); 1261 fst_recover_rx_error(card, port, dmabits, rxp, len); 1262 return; 1263 } 1264 1265 /* Allocate SKB */ 1266 if ((skb = dev_alloc_skb(len)) == NULL) { 1267 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1268 1269 dev->stats.rx_dropped++; 1270 1271 /* Return descriptor to card */ 1272 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1273 1274 rxp = (rxp+1) % NUM_RX_BUFFER; 1275 port->rxpos = rxp; 1276 return; 1277 } 1278 1279 /* 1280 * We know the length we need to receive, len. 1281 * It's not worth using the DMA for reads of less than 1282 * FST_MIN_DMA_LEN 1283 */ 1284 1285 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { 1286 memcpy_fromio(skb_put(skb, len), 1287 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), 1288 len); 1289 1290 /* Reset buffer descriptor */ 1291 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1292 1293 /* Update stats */ 1294 dev->stats.rx_packets++; 1295 dev->stats.rx_bytes += len; 1296 1297 /* Push upstream */ 1298 dbg(DBG_RX, "Pushing frame up the stack\n"); 1299 if (port->mode == FST_RAW) 1300 skb->protocol = farsync_type_trans(skb, dev); 1301 else 1302 skb->protocol = hdlc_type_trans(skb, dev); 1303 rx_status = netif_rx(skb); 1304 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1305 if (rx_status == NET_RX_DROP) 1306 dev->stats.rx_dropped++; 1307 } else { 1308 card->dma_skb_rx = skb; 1309 card->dma_port_rx = port; 1310 card->dma_len_rx = len; 1311 card->dma_rxpos = rxp; 1312 fst_rx_dma(card, (char *) card->rx_dma_handle_card, 1313 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len); 1314 } 1315 if (rxp != port->rxpos) { 1316 dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); 1317 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); 1318 } 1319 rxp = (rxp+1) % NUM_RX_BUFFER; 1320 port->rxpos = rxp; 1321 } 1322 1323 /* 1324 * The bottom halfs to the ISR 1325 * 1326 */ 1327 1328 static void 1329 do_bottom_half_tx(struct fst_card_info *card) 1330 { 1331 struct fst_port_info *port; 1332 int pi; 1333 int txq_length; 1334 struct sk_buff *skb; 1335 unsigned long flags; 1336 struct net_device *dev; 1337 1338 /* 1339 * Find a free buffer for the transmit 1340 * Step through each port on this card 1341 */ 1342 1343 dbg(DBG_TX, "do_bottom_half_tx\n"); 1344 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1345 if (!port->run) 1346 continue; 1347 1348 dev = port_to_dev(port); 1349 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1350 DMA_OWN) && 1351 !(card->dmatx_in_progress)) { 1352 /* 1353 * There doesn't seem to be a txdone event per-se 1354 * We seem to have to deduce it, by checking the DMA_OWN 1355 * bit on the next buffer we think we can use 1356 */ 1357 spin_lock_irqsave(&card->card_lock, flags); 1358 if ((txq_length = port->txqe - port->txqs) < 0) { 1359 /* 1360 * This is the case where one has wrapped and the 1361 * maths gives us a negative number 1362 */ 1363 txq_length = txq_length + FST_TXQ_DEPTH; 1364 } 1365 spin_unlock_irqrestore(&card->card_lock, flags); 1366 if (txq_length > 0) { 1367 /* 1368 * There is something to send 1369 */ 1370 spin_lock_irqsave(&card->card_lock, flags); 1371 skb = port->txq[port->txqs]; 1372 port->txqs++; 1373 if (port->txqs == FST_TXQ_DEPTH) { 1374 port->txqs = 0; 1375 } 1376 spin_unlock_irqrestore(&card->card_lock, flags); 1377 /* 1378 * copy the data and set the required indicators on the 1379 * card. 1380 */ 1381 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, 1382 cnv_bcnt(skb->len)); 1383 if ((skb->len < FST_MIN_DMA_LEN) || 1384 (card->family == FST_FAMILY_TXP)) { 1385 /* Enqueue the packet with normal io */ 1386 memcpy_toio(card->mem + 1387 BUF_OFFSET(txBuffer[pi] 1388 [port-> 1389 txpos][0]), 1390 skb->data, skb->len); 1391 FST_WRB(card, 1392 txDescrRing[pi][port->txpos]. 1393 bits, 1394 DMA_OWN | TX_STP | TX_ENP); 1395 dev->stats.tx_packets++; 1396 dev->stats.tx_bytes += skb->len; 1397 dev->trans_start = jiffies; 1398 } else { 1399 /* Or do it through dma */ 1400 memcpy(card->tx_dma_handle_host, 1401 skb->data, skb->len); 1402 card->dma_port_tx = port; 1403 card->dma_len_tx = skb->len; 1404 card->dma_txpos = port->txpos; 1405 fst_tx_dma(card, 1406 (char *) card-> 1407 tx_dma_handle_card, 1408 (char *) 1409 BUF_OFFSET(txBuffer[pi] 1410 [port->txpos][0]), 1411 skb->len); 1412 } 1413 if (++port->txpos >= NUM_TX_BUFFER) 1414 port->txpos = 0; 1415 /* 1416 * If we have flow control on, can we now release it? 1417 */ 1418 if (port->start) { 1419 if (txq_length < fst_txq_low) { 1420 netif_wake_queue(port_to_dev 1421 (port)); 1422 port->start = 0; 1423 } 1424 } 1425 dev_kfree_skb(skb); 1426 } else { 1427 /* 1428 * Nothing to send so break out of the while loop 1429 */ 1430 break; 1431 } 1432 } 1433 } 1434 } 1435 1436 static void 1437 do_bottom_half_rx(struct fst_card_info *card) 1438 { 1439 struct fst_port_info *port; 1440 int pi; 1441 int rx_count = 0; 1442 1443 /* Check for rx completions on all ports on this card */ 1444 dbg(DBG_RX, "do_bottom_half_rx\n"); 1445 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1446 if (!port->run) 1447 continue; 1448 1449 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) 1450 & DMA_OWN) && !(card->dmarx_in_progress)) { 1451 if (rx_count > fst_max_reads) { 1452 /* 1453 * Don't spend forever in receive processing 1454 * Schedule another event 1455 */ 1456 fst_q_work_item(&fst_work_intq, card->card_no); 1457 tasklet_schedule(&fst_int_task); 1458 break; /* Leave the loop */ 1459 } 1460 fst_intr_rx(card, port); 1461 rx_count++; 1462 } 1463 } 1464 } 1465 1466 /* 1467 * The interrupt service routine 1468 * Dev_id is our fst_card_info pointer 1469 */ 1470 static irqreturn_t 1471 fst_intr(int dummy, void *dev_id) 1472 { 1473 struct fst_card_info *card = dev_id; 1474 struct fst_port_info *port; 1475 int rdidx; /* Event buffer indices */ 1476 int wridx; 1477 int event; /* Actual event for processing */ 1478 unsigned int dma_intcsr = 0; 1479 unsigned int do_card_interrupt; 1480 unsigned int int_retry_count; 1481 1482 /* 1483 * Check to see if the interrupt was for this card 1484 * return if not 1485 * Note that the call to clear the interrupt is important 1486 */ 1487 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); 1488 if (card->state != FST_RUNNING) { 1489 printk_err 1490 ("Interrupt received for card %d in a non running state (%d)\n", 1491 card->card_no, card->state); 1492 1493 /* 1494 * It is possible to really be running, i.e. we have re-loaded 1495 * a running card 1496 * Clear and reprime the interrupt source 1497 */ 1498 fst_clear_intr(card); 1499 return IRQ_HANDLED; 1500 } 1501 1502 /* Clear and reprime the interrupt source */ 1503 fst_clear_intr(card); 1504 1505 /* 1506 * Is the interrupt for this card (handshake == 1) 1507 */ 1508 do_card_interrupt = 0; 1509 if (FST_RDB(card, interruptHandshake) == 1) { 1510 do_card_interrupt += FST_CARD_INT; 1511 /* Set the software acknowledge */ 1512 FST_WRB(card, interruptHandshake, 0xEE); 1513 } 1514 if (card->family == FST_FAMILY_TXU) { 1515 /* 1516 * Is it a DMA Interrupt 1517 */ 1518 dma_intcsr = inl(card->pci_conf + INTCSR_9054); 1519 if (dma_intcsr & 0x00200000) { 1520 /* 1521 * DMA Channel 0 (Rx transfer complete) 1522 */ 1523 dbg(DBG_RX, "DMA Rx xfer complete\n"); 1524 outb(0x8, card->pci_conf + DMACSR0); 1525 fst_rx_dma_complete(card, card->dma_port_rx, 1526 card->dma_len_rx, card->dma_skb_rx, 1527 card->dma_rxpos); 1528 card->dmarx_in_progress = 0; 1529 do_card_interrupt += FST_RX_DMA_INT; 1530 } 1531 if (dma_intcsr & 0x00400000) { 1532 /* 1533 * DMA Channel 1 (Tx transfer complete) 1534 */ 1535 dbg(DBG_TX, "DMA Tx xfer complete\n"); 1536 outb(0x8, card->pci_conf + DMACSR1); 1537 fst_tx_dma_complete(card, card->dma_port_tx, 1538 card->dma_len_tx, card->dma_txpos); 1539 card->dmatx_in_progress = 0; 1540 do_card_interrupt += FST_TX_DMA_INT; 1541 } 1542 } 1543 1544 /* 1545 * Have we been missing Interrupts 1546 */ 1547 int_retry_count = FST_RDL(card, interruptRetryCount); 1548 if (int_retry_count) { 1549 dbg(DBG_ASS, "Card %d int_retry_count is %d\n", 1550 card->card_no, int_retry_count); 1551 FST_WRL(card, interruptRetryCount, 0); 1552 } 1553 1554 if (!do_card_interrupt) { 1555 return IRQ_HANDLED; 1556 } 1557 1558 /* Scehdule the bottom half of the ISR */ 1559 fst_q_work_item(&fst_work_intq, card->card_no); 1560 tasklet_schedule(&fst_int_task); 1561 1562 /* Drain the event queue */ 1563 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; 1564 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; 1565 while (rdidx != wridx) { 1566 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); 1567 port = &card->ports[event & 0x03]; 1568 1569 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); 1570 1571 switch (event) { 1572 case TE1_ALMA: 1573 dbg(DBG_INTR, "TE1 Alarm intr\n"); 1574 if (port->run) 1575 fst_intr_te1_alarm(card, port); 1576 break; 1577 1578 case CTLA_CHG: 1579 case CTLB_CHG: 1580 case CTLC_CHG: 1581 case CTLD_CHG: 1582 if (port->run) 1583 fst_intr_ctlchg(card, port); 1584 break; 1585 1586 case ABTA_SENT: 1587 case ABTB_SENT: 1588 case ABTC_SENT: 1589 case ABTD_SENT: 1590 dbg(DBG_TX, "Abort complete port %d\n", port->index); 1591 break; 1592 1593 case TXA_UNDF: 1594 case TXB_UNDF: 1595 case TXC_UNDF: 1596 case TXD_UNDF: 1597 /* Difficult to see how we'd get this given that we 1598 * always load up the entire packet for DMA. 1599 */ 1600 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1601 port_to_dev(port)->stats.tx_errors++; 1602 port_to_dev(port)->stats.tx_fifo_errors++; 1603 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1604 card->card_no, port->index); 1605 break; 1606 1607 case INIT_CPLT: 1608 dbg(DBG_INIT, "Card init OK intr\n"); 1609 break; 1610 1611 case INIT_FAIL: 1612 dbg(DBG_INIT, "Card init FAILED intr\n"); 1613 card->state = FST_IFAILED; 1614 break; 1615 1616 default: 1617 printk_err("intr: unknown card event %d. ignored\n", 1618 event); 1619 break; 1620 } 1621 1622 /* Bump and wrap the index */ 1623 if (++rdidx >= MAX_CIRBUFF) 1624 rdidx = 0; 1625 } 1626 FST_WRB(card, interruptEvent.rdindex, rdidx); 1627 return IRQ_HANDLED; 1628 } 1629 1630 /* Check that the shared memory configuration is one that we can handle 1631 * and that some basic parameters are correct 1632 */ 1633 static void 1634 check_started_ok(struct fst_card_info *card) 1635 { 1636 int i; 1637 1638 /* Check structure version and end marker */ 1639 if (FST_RDW(card, smcVersion) != SMC_VERSION) { 1640 printk_err("Bad shared memory version %d expected %d\n", 1641 FST_RDW(card, smcVersion), SMC_VERSION); 1642 card->state = FST_BADVERSION; 1643 return; 1644 } 1645 if (FST_RDL(card, endOfSmcSignature) != END_SIG) { 1646 printk_err("Missing shared memory signature\n"); 1647 card->state = FST_BADVERSION; 1648 return; 1649 } 1650 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ 1651 if ((i = FST_RDB(card, taskStatus)) == 0x01) { 1652 card->state = FST_RUNNING; 1653 } else if (i == 0xFF) { 1654 printk_err("Firmware initialisation failed. Card halted\n"); 1655 card->state = FST_HALTED; 1656 return; 1657 } else if (i != 0x00) { 1658 printk_err("Unknown firmware status 0x%x\n", i); 1659 card->state = FST_HALTED; 1660 return; 1661 } 1662 1663 /* Finally check the number of ports reported by firmware against the 1664 * number we assumed at card detection. Should never happen with 1665 * existing firmware etc so we just report it for the moment. 1666 */ 1667 if (FST_RDL(card, numberOfPorts) != card->nports) { 1668 printk_warn("Port count mismatch on card %d." 1669 " Firmware thinks %d we say %d\n", card->card_no, 1670 FST_RDL(card, numberOfPorts), card->nports); 1671 } 1672 } 1673 1674 static int 1675 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, 1676 struct fstioc_info *info) 1677 { 1678 int err; 1679 unsigned char my_framing; 1680 1681 /* Set things according to the user set valid flags 1682 * Several of the old options have been invalidated/replaced by the 1683 * generic hdlc package. 1684 */ 1685 err = 0; 1686 if (info->valid & FSTVAL_PROTO) { 1687 if (info->proto == FST_RAW) 1688 port->mode = FST_RAW; 1689 else 1690 port->mode = FST_GEN_HDLC; 1691 } 1692 1693 if (info->valid & FSTVAL_CABLE) 1694 err = -EINVAL; 1695 1696 if (info->valid & FSTVAL_SPEED) 1697 err = -EINVAL; 1698 1699 if (info->valid & FSTVAL_PHASE) 1700 FST_WRB(card, portConfig[port->index].invertClock, 1701 info->invertClock); 1702 if (info->valid & FSTVAL_MODE) 1703 FST_WRW(card, cardMode, info->cardMode); 1704 if (info->valid & FSTVAL_TE1) { 1705 FST_WRL(card, suConfig.dataRate, info->lineSpeed); 1706 FST_WRB(card, suConfig.clocking, info->clockSource); 1707 my_framing = FRAMING_E1; 1708 if (info->framing == E1) 1709 my_framing = FRAMING_E1; 1710 if (info->framing == T1) 1711 my_framing = FRAMING_T1; 1712 if (info->framing == J1) 1713 my_framing = FRAMING_J1; 1714 FST_WRB(card, suConfig.framing, my_framing); 1715 FST_WRB(card, suConfig.structure, info->structure); 1716 FST_WRB(card, suConfig.interface, info->interface); 1717 FST_WRB(card, suConfig.coding, info->coding); 1718 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); 1719 FST_WRB(card, suConfig.equalizer, info->equalizer); 1720 FST_WRB(card, suConfig.transparentMode, info->transparentMode); 1721 FST_WRB(card, suConfig.loopMode, info->loopMode); 1722 FST_WRB(card, suConfig.range, info->range); 1723 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); 1724 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); 1725 FST_WRB(card, suConfig.startingSlot, info->startingSlot); 1726 FST_WRB(card, suConfig.losThreshold, info->losThreshold); 1727 if (info->idleCode) 1728 FST_WRB(card, suConfig.enableIdleCode, 1); 1729 else 1730 FST_WRB(card, suConfig.enableIdleCode, 0); 1731 FST_WRB(card, suConfig.idleCode, info->idleCode); 1732 #if FST_DEBUG 1733 if (info->valid & FSTVAL_TE1) { 1734 printk("Setting TE1 data\n"); 1735 printk("Line Speed = %d\n", info->lineSpeed); 1736 printk("Start slot = %d\n", info->startingSlot); 1737 printk("Clock source = %d\n", info->clockSource); 1738 printk("Framing = %d\n", my_framing); 1739 printk("Structure = %d\n", info->structure); 1740 printk("interface = %d\n", info->interface); 1741 printk("Coding = %d\n", info->coding); 1742 printk("Line build out = %d\n", info->lineBuildOut); 1743 printk("Equaliser = %d\n", info->equalizer); 1744 printk("Transparent mode = %d\n", 1745 info->transparentMode); 1746 printk("Loop mode = %d\n", info->loopMode); 1747 printk("Range = %d\n", info->range); 1748 printk("Tx Buffer mode = %d\n", info->txBufferMode); 1749 printk("Rx Buffer mode = %d\n", info->rxBufferMode); 1750 printk("LOS Threshold = %d\n", info->losThreshold); 1751 printk("Idle Code = %d\n", info->idleCode); 1752 } 1753 #endif 1754 } 1755 #if FST_DEBUG 1756 if (info->valid & FSTVAL_DEBUG) { 1757 fst_debug_mask = info->debug; 1758 } 1759 #endif 1760 1761 return err; 1762 } 1763 1764 static void 1765 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, 1766 struct fstioc_info *info) 1767 { 1768 int i; 1769 1770 memset(info, 0, sizeof (struct fstioc_info)); 1771 1772 i = port->index; 1773 info->kernelVersion = LINUX_VERSION_CODE; 1774 info->nports = card->nports; 1775 info->type = card->type; 1776 info->state = card->state; 1777 info->proto = FST_GEN_HDLC; 1778 info->index = i; 1779 #if FST_DEBUG 1780 info->debug = fst_debug_mask; 1781 #endif 1782 1783 /* Only mark information as valid if card is running. 1784 * Copy the data anyway in case it is useful for diagnostics 1785 */ 1786 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) 1787 #if FST_DEBUG 1788 | FSTVAL_DEBUG 1789 #endif 1790 ; 1791 1792 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); 1793 info->internalClock = FST_RDB(card, portConfig[i].internalClock); 1794 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); 1795 info->invertClock = FST_RDB(card, portConfig[i].invertClock); 1796 info->v24IpSts = FST_RDL(card, v24IpSts[i]); 1797 info->v24OpSts = FST_RDL(card, v24OpSts[i]); 1798 info->clockStatus = FST_RDW(card, clockStatus[i]); 1799 info->cableStatus = FST_RDW(card, cableStatus); 1800 info->cardMode = FST_RDW(card, cardMode); 1801 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); 1802 1803 /* 1804 * The T2U can report cable presence for both A or B 1805 * in bits 0 and 1 of cableStatus. See which port we are and 1806 * do the mapping. 1807 */ 1808 if (card->family == FST_FAMILY_TXU) { 1809 if (port->index == 0) { 1810 /* 1811 * Port A 1812 */ 1813 info->cableStatus = info->cableStatus & 1; 1814 } else { 1815 /* 1816 * Port B 1817 */ 1818 info->cableStatus = info->cableStatus >> 1; 1819 info->cableStatus = info->cableStatus & 1; 1820 } 1821 } 1822 /* 1823 * Some additional bits if we are TE1 1824 */ 1825 if (card->type == FST_TYPE_TE1) { 1826 info->lineSpeed = FST_RDL(card, suConfig.dataRate); 1827 info->clockSource = FST_RDB(card, suConfig.clocking); 1828 info->framing = FST_RDB(card, suConfig.framing); 1829 info->structure = FST_RDB(card, suConfig.structure); 1830 info->interface = FST_RDB(card, suConfig.interface); 1831 info->coding = FST_RDB(card, suConfig.coding); 1832 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); 1833 info->equalizer = FST_RDB(card, suConfig.equalizer); 1834 info->loopMode = FST_RDB(card, suConfig.loopMode); 1835 info->range = FST_RDB(card, suConfig.range); 1836 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); 1837 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); 1838 info->startingSlot = FST_RDB(card, suConfig.startingSlot); 1839 info->losThreshold = FST_RDB(card, suConfig.losThreshold); 1840 if (FST_RDB(card, suConfig.enableIdleCode)) 1841 info->idleCode = FST_RDB(card, suConfig.idleCode); 1842 else 1843 info->idleCode = 0; 1844 info->receiveBufferDelay = 1845 FST_RDL(card, suStatus.receiveBufferDelay); 1846 info->framingErrorCount = 1847 FST_RDL(card, suStatus.framingErrorCount); 1848 info->codeViolationCount = 1849 FST_RDL(card, suStatus.codeViolationCount); 1850 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); 1851 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); 1852 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); 1853 info->receiveRemoteAlarm = 1854 FST_RDB(card, suStatus.receiveRemoteAlarm); 1855 info->alarmIndicationSignal = 1856 FST_RDB(card, suStatus.alarmIndicationSignal); 1857 } 1858 } 1859 1860 static int 1861 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, 1862 struct ifreq *ifr) 1863 { 1864 sync_serial_settings sync; 1865 int i; 1866 1867 if (ifr->ifr_settings.size != sizeof (sync)) { 1868 return -ENOMEM; 1869 } 1870 1871 if (copy_from_user 1872 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { 1873 return -EFAULT; 1874 } 1875 1876 if (sync.loopback) 1877 return -EINVAL; 1878 1879 i = port->index; 1880 1881 switch (ifr->ifr_settings.type) { 1882 case IF_IFACE_V35: 1883 FST_WRW(card, portConfig[i].lineInterface, V35); 1884 port->hwif = V35; 1885 break; 1886 1887 case IF_IFACE_V24: 1888 FST_WRW(card, portConfig[i].lineInterface, V24); 1889 port->hwif = V24; 1890 break; 1891 1892 case IF_IFACE_X21: 1893 FST_WRW(card, portConfig[i].lineInterface, X21); 1894 port->hwif = X21; 1895 break; 1896 1897 case IF_IFACE_X21D: 1898 FST_WRW(card, portConfig[i].lineInterface, X21D); 1899 port->hwif = X21D; 1900 break; 1901 1902 case IF_IFACE_T1: 1903 FST_WRW(card, portConfig[i].lineInterface, T1); 1904 port->hwif = T1; 1905 break; 1906 1907 case IF_IFACE_E1: 1908 FST_WRW(card, portConfig[i].lineInterface, E1); 1909 port->hwif = E1; 1910 break; 1911 1912 case IF_IFACE_SYNC_SERIAL: 1913 break; 1914 1915 default: 1916 return -EINVAL; 1917 } 1918 1919 switch (sync.clock_type) { 1920 case CLOCK_EXT: 1921 FST_WRB(card, portConfig[i].internalClock, EXTCLK); 1922 break; 1923 1924 case CLOCK_INT: 1925 FST_WRB(card, portConfig[i].internalClock, INTCLK); 1926 break; 1927 1928 default: 1929 return -EINVAL; 1930 } 1931 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); 1932 return 0; 1933 } 1934 1935 static int 1936 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, 1937 struct ifreq *ifr) 1938 { 1939 sync_serial_settings sync; 1940 int i; 1941 1942 /* First check what line type is set, we'll default to reporting X.21 1943 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be 1944 * changed 1945 */ 1946 switch (port->hwif) { 1947 case E1: 1948 ifr->ifr_settings.type = IF_IFACE_E1; 1949 break; 1950 case T1: 1951 ifr->ifr_settings.type = IF_IFACE_T1; 1952 break; 1953 case V35: 1954 ifr->ifr_settings.type = IF_IFACE_V35; 1955 break; 1956 case V24: 1957 ifr->ifr_settings.type = IF_IFACE_V24; 1958 break; 1959 case X21D: 1960 ifr->ifr_settings.type = IF_IFACE_X21D; 1961 break; 1962 case X21: 1963 default: 1964 ifr->ifr_settings.type = IF_IFACE_X21; 1965 break; 1966 } 1967 if (ifr->ifr_settings.size == 0) { 1968 return 0; /* only type requested */ 1969 } 1970 if (ifr->ifr_settings.size < sizeof (sync)) { 1971 return -ENOMEM; 1972 } 1973 1974 i = port->index; 1975 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); 1976 /* Lucky card and linux use same encoding here */ 1977 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == 1978 INTCLK ? CLOCK_INT : CLOCK_EXT; 1979 sync.loopback = 0; 1980 1981 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { 1982 return -EFAULT; 1983 } 1984 1985 ifr->ifr_settings.size = sizeof (sync); 1986 return 0; 1987 } 1988 1989 static int 1990 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1991 { 1992 struct fst_card_info *card; 1993 struct fst_port_info *port; 1994 struct fstioc_write wrthdr; 1995 struct fstioc_info info; 1996 unsigned long flags; 1997 void *buf; 1998 1999 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); 2000 2001 port = dev_to_port(dev); 2002 card = port->card; 2003 2004 if (!capable(CAP_NET_ADMIN)) 2005 return -EPERM; 2006 2007 switch (cmd) { 2008 case FSTCPURESET: 2009 fst_cpureset(card); 2010 card->state = FST_RESET; 2011 return 0; 2012 2013 case FSTCPURELEASE: 2014 fst_cpurelease(card); 2015 card->state = FST_STARTING; 2016 return 0; 2017 2018 case FSTWRITE: /* Code write (download) */ 2019 2020 /* First copy in the header with the length and offset of data 2021 * to write 2022 */ 2023 if (ifr->ifr_data == NULL) { 2024 return -EINVAL; 2025 } 2026 if (copy_from_user(&wrthdr, ifr->ifr_data, 2027 sizeof (struct fstioc_write))) { 2028 return -EFAULT; 2029 } 2030 2031 /* Sanity check the parameters. We don't support partial writes 2032 * when going over the top 2033 */ 2034 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE || 2035 wrthdr.size + wrthdr.offset > FST_MEMSIZE) { 2036 return -ENXIO; 2037 } 2038 2039 /* Now copy the data to the card. */ 2040 2041 buf = kmalloc(wrthdr.size, GFP_KERNEL); 2042 if (!buf) 2043 return -ENOMEM; 2044 2045 if (copy_from_user(buf, 2046 ifr->ifr_data + sizeof (struct fstioc_write), 2047 wrthdr.size)) { 2048 kfree(buf); 2049 return -EFAULT; 2050 } 2051 2052 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); 2053 kfree(buf); 2054 2055 /* Writes to the memory of a card in the reset state constitute 2056 * a download 2057 */ 2058 if (card->state == FST_RESET) { 2059 card->state = FST_DOWNLOAD; 2060 } 2061 return 0; 2062 2063 case FSTGETCONF: 2064 2065 /* If card has just been started check the shared memory config 2066 * version and marker 2067 */ 2068 if (card->state == FST_STARTING) { 2069 check_started_ok(card); 2070 2071 /* If everything checked out enable card interrupts */ 2072 if (card->state == FST_RUNNING) { 2073 spin_lock_irqsave(&card->card_lock, flags); 2074 fst_enable_intr(card); 2075 FST_WRB(card, interruptHandshake, 0xEE); 2076 spin_unlock_irqrestore(&card->card_lock, flags); 2077 } 2078 } 2079 2080 if (ifr->ifr_data == NULL) { 2081 return -EINVAL; 2082 } 2083 2084 gather_conf_info(card, port, &info); 2085 2086 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { 2087 return -EFAULT; 2088 } 2089 return 0; 2090 2091 case FSTSETCONF: 2092 2093 /* 2094 * Most of the settings have been moved to the generic ioctls 2095 * this just covers debug and board ident now 2096 */ 2097 2098 if (card->state != FST_RUNNING) { 2099 printk_err 2100 ("Attempt to configure card %d in non-running state (%d)\n", 2101 card->card_no, card->state); 2102 return -EIO; 2103 } 2104 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { 2105 return -EFAULT; 2106 } 2107 2108 return set_conf_from_info(card, port, &info); 2109 2110 case SIOCWANDEV: 2111 switch (ifr->ifr_settings.type) { 2112 case IF_GET_IFACE: 2113 return fst_get_iface(card, port, ifr); 2114 2115 case IF_IFACE_SYNC_SERIAL: 2116 case IF_IFACE_V35: 2117 case IF_IFACE_V24: 2118 case IF_IFACE_X21: 2119 case IF_IFACE_X21D: 2120 case IF_IFACE_T1: 2121 case IF_IFACE_E1: 2122 return fst_set_iface(card, port, ifr); 2123 2124 case IF_PROTO_RAW: 2125 port->mode = FST_RAW; 2126 return 0; 2127 2128 case IF_GET_PROTO: 2129 if (port->mode == FST_RAW) { 2130 ifr->ifr_settings.type = IF_PROTO_RAW; 2131 return 0; 2132 } 2133 return hdlc_ioctl(dev, ifr, cmd); 2134 2135 default: 2136 port->mode = FST_GEN_HDLC; 2137 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", 2138 ifr->ifr_settings.type); 2139 return hdlc_ioctl(dev, ifr, cmd); 2140 } 2141 2142 default: 2143 /* Not one of ours. Pass through to HDLC package */ 2144 return hdlc_ioctl(dev, ifr, cmd); 2145 } 2146 } 2147 2148 static void 2149 fst_openport(struct fst_port_info *port) 2150 { 2151 int signals; 2152 int txq_length; 2153 2154 /* Only init things if card is actually running. This allows open to 2155 * succeed for downloads etc. 2156 */ 2157 if (port->card->state == FST_RUNNING) { 2158 if (port->run) { 2159 dbg(DBG_OPEN, "open: found port already running\n"); 2160 2161 fst_issue_cmd(port, STOPPORT); 2162 port->run = 0; 2163 } 2164 2165 fst_rx_config(port); 2166 fst_tx_config(port); 2167 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); 2168 2169 fst_issue_cmd(port, STARTPORT); 2170 port->run = 1; 2171 2172 signals = FST_RDL(port->card, v24DebouncedSts[port->index]); 2173 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 2174 ? IPSTS_INDICATE : IPSTS_DCD)) 2175 netif_carrier_on(port_to_dev(port)); 2176 else 2177 netif_carrier_off(port_to_dev(port)); 2178 2179 txq_length = port->txqe - port->txqs; 2180 port->txqe = 0; 2181 port->txqs = 0; 2182 } 2183 2184 } 2185 2186 static void 2187 fst_closeport(struct fst_port_info *port) 2188 { 2189 if (port->card->state == FST_RUNNING) { 2190 if (port->run) { 2191 port->run = 0; 2192 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); 2193 2194 fst_issue_cmd(port, STOPPORT); 2195 } else { 2196 dbg(DBG_OPEN, "close: port not running\n"); 2197 } 2198 } 2199 } 2200 2201 static int 2202 fst_open(struct net_device *dev) 2203 { 2204 int err; 2205 struct fst_port_info *port; 2206 2207 port = dev_to_port(dev); 2208 if (!try_module_get(THIS_MODULE)) 2209 return -EBUSY; 2210 2211 if (port->mode != FST_RAW) { 2212 err = hdlc_open(dev); 2213 if (err) 2214 return err; 2215 } 2216 2217 fst_openport(port); 2218 netif_wake_queue(dev); 2219 return 0; 2220 } 2221 2222 static int 2223 fst_close(struct net_device *dev) 2224 { 2225 struct fst_port_info *port; 2226 struct fst_card_info *card; 2227 unsigned char tx_dma_done; 2228 unsigned char rx_dma_done; 2229 2230 port = dev_to_port(dev); 2231 card = port->card; 2232 2233 tx_dma_done = inb(card->pci_conf + DMACSR1); 2234 rx_dma_done = inb(card->pci_conf + DMACSR0); 2235 dbg(DBG_OPEN, 2236 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", 2237 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, 2238 rx_dma_done); 2239 2240 netif_stop_queue(dev); 2241 fst_closeport(dev_to_port(dev)); 2242 if (port->mode != FST_RAW) { 2243 hdlc_close(dev); 2244 } 2245 module_put(THIS_MODULE); 2246 return 0; 2247 } 2248 2249 static int 2250 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) 2251 { 2252 /* 2253 * Setting currently fixed in FarSync card so we check and forget 2254 */ 2255 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) 2256 return -EINVAL; 2257 return 0; 2258 } 2259 2260 static void 2261 fst_tx_timeout(struct net_device *dev) 2262 { 2263 struct fst_port_info *port; 2264 struct fst_card_info *card; 2265 2266 port = dev_to_port(dev); 2267 card = port->card; 2268 dev->stats.tx_errors++; 2269 dev->stats.tx_aborted_errors++; 2270 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2271 card->card_no, port->index); 2272 fst_issue_cmd(port, ABORTTX); 2273 2274 dev->trans_start = jiffies; 2275 netif_wake_queue(dev); 2276 port->start = 0; 2277 } 2278 2279 static netdev_tx_t 2280 fst_start_xmit(struct sk_buff *skb, struct net_device *dev) 2281 { 2282 struct fst_card_info *card; 2283 struct fst_port_info *port; 2284 unsigned long flags; 2285 int txq_length; 2286 2287 port = dev_to_port(dev); 2288 card = port->card; 2289 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); 2290 2291 /* Drop packet with error if we don't have carrier */ 2292 if (!netif_carrier_ok(dev)) { 2293 dev_kfree_skb(skb); 2294 dev->stats.tx_errors++; 2295 dev->stats.tx_carrier_errors++; 2296 dbg(DBG_ASS, 2297 "Tried to transmit but no carrier on card %d port %d\n", 2298 card->card_no, port->index); 2299 return NETDEV_TX_OK; 2300 } 2301 2302 /* Drop it if it's too big! MTU failure ? */ 2303 if (skb->len > LEN_TX_BUFFER) { 2304 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2305 LEN_TX_BUFFER); 2306 dev_kfree_skb(skb); 2307 dev->stats.tx_errors++; 2308 return NETDEV_TX_OK; 2309 } 2310 2311 /* 2312 * We are always going to queue the packet 2313 * so that the bottom half is the only place we tx from 2314 * Check there is room in the port txq 2315 */ 2316 spin_lock_irqsave(&card->card_lock, flags); 2317 if ((txq_length = port->txqe - port->txqs) < 0) { 2318 /* 2319 * This is the case where the next free has wrapped but the 2320 * last used hasn't 2321 */ 2322 txq_length = txq_length + FST_TXQ_DEPTH; 2323 } 2324 spin_unlock_irqrestore(&card->card_lock, flags); 2325 if (txq_length > fst_txq_high) { 2326 /* 2327 * We have got enough buffers in the pipeline. Ask the network 2328 * layer to stop sending frames down 2329 */ 2330 netif_stop_queue(dev); 2331 port->start = 1; /* I'm using this to signal stop sent up */ 2332 } 2333 2334 if (txq_length == FST_TXQ_DEPTH - 1) { 2335 /* 2336 * This shouldn't have happened but such is life 2337 */ 2338 dev_kfree_skb(skb); 2339 dev->stats.tx_errors++; 2340 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2341 card->card_no, port->index); 2342 return NETDEV_TX_OK; 2343 } 2344 2345 /* 2346 * queue the buffer 2347 */ 2348 spin_lock_irqsave(&card->card_lock, flags); 2349 port->txq[port->txqe] = skb; 2350 port->txqe++; 2351 if (port->txqe == FST_TXQ_DEPTH) 2352 port->txqe = 0; 2353 spin_unlock_irqrestore(&card->card_lock, flags); 2354 2355 /* Scehdule the bottom half which now does transmit processing */ 2356 fst_q_work_item(&fst_work_txq, card->card_no); 2357 tasklet_schedule(&fst_tx_task); 2358 2359 return NETDEV_TX_OK; 2360 } 2361 2362 /* 2363 * Card setup having checked hardware resources. 2364 * Should be pretty bizarre if we get an error here (kernel memory 2365 * exhaustion is one possibility). If we do see a problem we report it 2366 * via a printk and leave the corresponding interface and all that follow 2367 * disabled. 2368 */ 2369 static char *type_strings[] __devinitdata = { 2370 "no hardware", /* Should never be seen */ 2371 "FarSync T2P", 2372 "FarSync T4P", 2373 "FarSync T1U", 2374 "FarSync T2U", 2375 "FarSync T4U", 2376 "FarSync TE1" 2377 }; 2378 2379 static void __devinit 2380 fst_init_card(struct fst_card_info *card) 2381 { 2382 int i; 2383 int err; 2384 2385 /* We're working on a number of ports based on the card ID. If the 2386 * firmware detects something different later (should never happen) 2387 * we'll have to revise it in some way then. 2388 */ 2389 for (i = 0; i < card->nports; i++) { 2390 err = register_hdlc_device(card->ports[i].dev); 2391 if (err < 0) { 2392 int j; 2393 printk_err ("Cannot register HDLC device for port %d" 2394 " (errno %d)\n", i, -err ); 2395 for (j = i; j < card->nports; j++) { 2396 free_netdev(card->ports[j].dev); 2397 card->ports[j].dev = NULL; 2398 } 2399 card->nports = i; 2400 break; 2401 } 2402 } 2403 2404 printk_info("%s-%s: %s IRQ%d, %d ports\n", 2405 port_to_dev(&card->ports[0])->name, 2406 port_to_dev(&card->ports[card->nports - 1])->name, 2407 type_strings[card->type], card->irq, card->nports); 2408 } 2409 2410 static const struct net_device_ops fst_ops = { 2411 .ndo_open = fst_open, 2412 .ndo_stop = fst_close, 2413 .ndo_change_mtu = hdlc_change_mtu, 2414 .ndo_start_xmit = hdlc_start_xmit, 2415 .ndo_do_ioctl = fst_ioctl, 2416 .ndo_tx_timeout = fst_tx_timeout, 2417 }; 2418 2419 /* 2420 * Initialise card when detected. 2421 * Returns 0 to indicate success, or errno otherwise. 2422 */ 2423 static int __devinit 2424 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2425 { 2426 static int firsttime_done = 0; 2427 static int no_of_cards_added = 0; 2428 struct fst_card_info *card; 2429 int err = 0; 2430 int i; 2431 2432 if (!firsttime_done) { 2433 printk_info("FarSync WAN driver " FST_USER_VERSION 2434 " (c) 2001-2004 FarSite Communications Ltd.\n"); 2435 firsttime_done = 1; 2436 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); 2437 } 2438 2439 /* 2440 * We are going to be clever and allow certain cards not to be 2441 * configured. An exclude list can be provided in /etc/modules.conf 2442 */ 2443 if (fst_excluded_cards != 0) { 2444 /* 2445 * There are cards to exclude 2446 * 2447 */ 2448 for (i = 0; i < fst_excluded_cards; i++) { 2449 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { 2450 printk_info("FarSync PCI device %d not assigned\n", 2451 (pdev->devfn) >> 3); 2452 return -EBUSY; 2453 } 2454 } 2455 } 2456 2457 /* Allocate driver private data */ 2458 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL); 2459 if (card == NULL) { 2460 printk_err("FarSync card found but insufficient memory for" 2461 " driver storage\n"); 2462 return -ENOMEM; 2463 } 2464 2465 /* Try to enable the device */ 2466 if ((err = pci_enable_device(pdev)) != 0) { 2467 printk_err("Failed to enable card. Err %d\n", -err); 2468 kfree(card); 2469 return err; 2470 } 2471 2472 if ((err = pci_request_regions(pdev, "FarSync")) !=0) { 2473 printk_err("Failed to allocate regions. Err %d\n", -err); 2474 pci_disable_device(pdev); 2475 kfree(card); 2476 return err; 2477 } 2478 2479 /* Get virtual addresses of memory regions */ 2480 card->pci_conf = pci_resource_start(pdev, 1); 2481 card->phys_mem = pci_resource_start(pdev, 2); 2482 card->phys_ctlmem = pci_resource_start(pdev, 3); 2483 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { 2484 printk_err("Physical memory remap failed\n"); 2485 pci_release_regions(pdev); 2486 pci_disable_device(pdev); 2487 kfree(card); 2488 return -ENODEV; 2489 } 2490 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { 2491 printk_err("Control memory remap failed\n"); 2492 pci_release_regions(pdev); 2493 pci_disable_device(pdev); 2494 kfree(card); 2495 return -ENODEV; 2496 } 2497 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); 2498 2499 /* Register the interrupt handler */ 2500 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { 2501 printk_err("Unable to register interrupt %d\n", card->irq); 2502 pci_release_regions(pdev); 2503 pci_disable_device(pdev); 2504 iounmap(card->ctlmem); 2505 iounmap(card->mem); 2506 kfree(card); 2507 return -ENODEV; 2508 } 2509 2510 /* Record info we need */ 2511 card->irq = pdev->irq; 2512 card->type = ent->driver_data; 2513 card->family = ((ent->driver_data == FST_TYPE_T2P) || 2514 (ent->driver_data == FST_TYPE_T4P)) 2515 ? FST_FAMILY_TXP : FST_FAMILY_TXU; 2516 if ((ent->driver_data == FST_TYPE_T1U) || 2517 (ent->driver_data == FST_TYPE_TE1)) 2518 card->nports = 1; 2519 else 2520 card->nports = ((ent->driver_data == FST_TYPE_T2P) || 2521 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; 2522 2523 card->state = FST_UNINIT; 2524 spin_lock_init ( &card->card_lock ); 2525 2526 for ( i = 0 ; i < card->nports ; i++ ) { 2527 struct net_device *dev = alloc_hdlcdev(&card->ports[i]); 2528 hdlc_device *hdlc; 2529 if (!dev) { 2530 while (i--) 2531 free_netdev(card->ports[i].dev); 2532 printk_err ("FarSync: out of memory\n"); 2533 free_irq(card->irq, card); 2534 pci_release_regions(pdev); 2535 pci_disable_device(pdev); 2536 iounmap(card->ctlmem); 2537 iounmap(card->mem); 2538 kfree(card); 2539 return -ENODEV; 2540 } 2541 card->ports[i].dev = dev; 2542 card->ports[i].card = card; 2543 card->ports[i].index = i; 2544 card->ports[i].run = 0; 2545 2546 hdlc = dev_to_hdlc(dev); 2547 2548 /* Fill in the net device info */ 2549 /* Since this is a PCI setup this is purely 2550 * informational. Give them the buffer addresses 2551 * and basic card I/O. 2552 */ 2553 dev->mem_start = card->phys_mem 2554 + BUF_OFFSET ( txBuffer[i][0][0]); 2555 dev->mem_end = card->phys_mem 2556 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]); 2557 dev->base_addr = card->pci_conf; 2558 dev->irq = card->irq; 2559 2560 dev->netdev_ops = &fst_ops; 2561 dev->tx_queue_len = FST_TX_QUEUE_LEN; 2562 dev->watchdog_timeo = FST_TX_TIMEOUT; 2563 hdlc->attach = fst_attach; 2564 hdlc->xmit = fst_start_xmit; 2565 } 2566 2567 card->device = pdev; 2568 2569 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, 2570 card->nports, card->irq); 2571 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", 2572 card->pci_conf, card->phys_mem, card->phys_ctlmem); 2573 2574 /* Reset the card's processor */ 2575 fst_cpureset(card); 2576 card->state = FST_RESET; 2577 2578 /* Initialise DMA (if required) */ 2579 fst_init_dma(card); 2580 2581 /* Record driver data for later use */ 2582 pci_set_drvdata(pdev, card); 2583 2584 /* Remainder of card setup */ 2585 fst_card_array[no_of_cards_added] = card; 2586 card->card_no = no_of_cards_added++; /* Record instance and bump it */ 2587 fst_init_card(card); 2588 if (card->family == FST_FAMILY_TXU) { 2589 /* 2590 * Allocate a dma buffer for transmit and receives 2591 */ 2592 card->rx_dma_handle_host = 2593 pci_alloc_consistent(card->device, FST_MAX_MTU, 2594 &card->rx_dma_handle_card); 2595 if (card->rx_dma_handle_host == NULL) { 2596 printk_err("Could not allocate rx dma buffer\n"); 2597 fst_disable_intr(card); 2598 pci_release_regions(pdev); 2599 pci_disable_device(pdev); 2600 iounmap(card->ctlmem); 2601 iounmap(card->mem); 2602 kfree(card); 2603 return -ENOMEM; 2604 } 2605 card->tx_dma_handle_host = 2606 pci_alloc_consistent(card->device, FST_MAX_MTU, 2607 &card->tx_dma_handle_card); 2608 if (card->tx_dma_handle_host == NULL) { 2609 printk_err("Could not allocate tx dma buffer\n"); 2610 fst_disable_intr(card); 2611 pci_release_regions(pdev); 2612 pci_disable_device(pdev); 2613 iounmap(card->ctlmem); 2614 iounmap(card->mem); 2615 kfree(card); 2616 return -ENOMEM; 2617 } 2618 } 2619 return 0; /* Success */ 2620 } 2621 2622 /* 2623 * Cleanup and close down a card 2624 */ 2625 static void __devexit 2626 fst_remove_one(struct pci_dev *pdev) 2627 { 2628 struct fst_card_info *card; 2629 int i; 2630 2631 card = pci_get_drvdata(pdev); 2632 2633 for (i = 0; i < card->nports; i++) { 2634 struct net_device *dev = port_to_dev(&card->ports[i]); 2635 unregister_hdlc_device(dev); 2636 } 2637 2638 fst_disable_intr(card); 2639 free_irq(card->irq, card); 2640 2641 iounmap(card->ctlmem); 2642 iounmap(card->mem); 2643 pci_release_regions(pdev); 2644 if (card->family == FST_FAMILY_TXU) { 2645 /* 2646 * Free dma buffers 2647 */ 2648 pci_free_consistent(card->device, FST_MAX_MTU, 2649 card->rx_dma_handle_host, 2650 card->rx_dma_handle_card); 2651 pci_free_consistent(card->device, FST_MAX_MTU, 2652 card->tx_dma_handle_host, 2653 card->tx_dma_handle_card); 2654 } 2655 fst_card_array[card->card_no] = NULL; 2656 } 2657 2658 static struct pci_driver fst_driver = { 2659 .name = FST_NAME, 2660 .id_table = fst_pci_dev_id, 2661 .probe = fst_add_one, 2662 .remove = __devexit_p(fst_remove_one), 2663 .suspend = NULL, 2664 .resume = NULL, 2665 }; 2666 2667 static int __init 2668 fst_init(void) 2669 { 2670 int i; 2671 2672 for (i = 0; i < FST_MAX_CARDS; i++) 2673 fst_card_array[i] = NULL; 2674 spin_lock_init(&fst_work_q_lock); 2675 return pci_register_driver(&fst_driver); 2676 } 2677 2678 static void __exit 2679 fst_cleanup_module(void) 2680 { 2681 printk_info("FarSync WAN driver unloading\n"); 2682 pci_unregister_driver(&fst_driver); 2683 } 2684 2685 module_init(fst_init); 2686 module_exit(fst_cleanup_module); 2687