1 /* 2 * FarSync WAN driver for Linux (2.6.x kernel version) 3 * 4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards 5 * 6 * Copyright (C) 2001-2004 FarSite Communications Ltd. 7 * www.farsite.co.uk 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> 15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/version.h> 21 #include <linux/pci.h> 22 #include <linux/ioport.h> 23 #include <linux/init.h> 24 #include <linux/if.h> 25 #include <linux/hdlc.h> 26 #include <asm/io.h> 27 #include <asm/uaccess.h> 28 29 #include "farsync.h" 30 31 /* 32 * Module info 33 */ 34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); 35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); 36 MODULE_LICENSE("GPL"); 37 38 /* Driver configuration and global parameters 39 * ========================================== 40 */ 41 42 /* Number of ports (per card) and cards supported 43 */ 44 #define FST_MAX_PORTS 4 45 #define FST_MAX_CARDS 32 46 47 /* Default parameters for the link 48 */ 49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is 50 * useful, the syncppp module forces 51 * this down assuming a slower line I 52 * guess. 53 */ 54 #define FST_TXQ_DEPTH 16 /* This one is for the buffering 55 * of frames on the way down to the card 56 * so that we can keep the card busy 57 * and maximise throughput 58 */ 59 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control 60 * network layer */ 61 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow 62 * control from network layer */ 63 #define FST_MAX_MTU 8000 /* Huge but possible */ 64 #define FST_DEF_MTU 1500 /* Common sane value */ 65 66 #define FST_TX_TIMEOUT (2*HZ) 67 68 #ifdef ARPHRD_RAWHDLC 69 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ 70 #else 71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ 72 #endif 73 74 /* 75 * Modules parameters and associated varaibles 76 */ 77 static int fst_txq_low = FST_LOW_WATER_MARK; 78 static int fst_txq_high = FST_HIGH_WATER_MARK; 79 static int fst_max_reads = 7; 80 static int fst_excluded_cards = 0; 81 static int fst_excluded_list[FST_MAX_CARDS]; 82 83 module_param(fst_txq_low, int, 0); 84 module_param(fst_txq_high, int, 0); 85 module_param(fst_max_reads, int, 0); 86 module_param(fst_excluded_cards, int, 0); 87 module_param_array(fst_excluded_list, int, NULL, 0); 88 89 /* Card shared memory layout 90 * ========================= 91 */ 92 #pragma pack(1) 93 94 /* This information is derived in part from the FarSite FarSync Smc.h 95 * file. Unfortunately various name clashes and the non-portability of the 96 * bit field declarations in that file have meant that I have chosen to 97 * recreate the information here. 98 * 99 * The SMC (Shared Memory Configuration) has a version number that is 100 * incremented every time there is a significant change. This number can 101 * be used to check that we have not got out of step with the firmware 102 * contained in the .CDE files. 103 */ 104 #define SMC_VERSION 24 105 106 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ 107 108 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main 109 * configuration structure */ 110 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA 111 * buffers */ 112 113 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */ 114 #define LEN_RX_BUFFER 8192 115 116 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ 117 #define LEN_SMALL_RX_BUFFER 256 118 119 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ 120 #define NUM_RX_BUFFER 8 121 122 /* Interrupt retry time in milliseconds */ 123 #define INT_RETRY_TIME 2 124 125 /* The Am186CH/CC processors support a SmartDMA mode using circular pools 126 * of buffer descriptors. The structure is almost identical to that used 127 * in the LANCE Ethernet controllers. Details available as PDF from the 128 * AMD web site: http://www.amd.com/products/epd/processors/\ 129 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf 130 */ 131 struct txdesc { /* Transmit descriptor */ 132 volatile u16 ladr; /* Low order address of packet. This is a 133 * linear address in the Am186 memory space 134 */ 135 volatile u8 hadr; /* High order address. Low 4 bits only, high 4 136 * bits must be zero 137 */ 138 volatile u8 bits; /* Status and config */ 139 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. 140 * Transmit terminal count interrupt enable in 141 * top bit. 142 */ 143 u16 unused; /* Not used in Tx */ 144 }; 145 146 struct rxdesc { /* Receive descriptor */ 147 volatile u16 ladr; /* Low order address of packet */ 148 volatile u8 hadr; /* High order address */ 149 volatile u8 bits; /* Status and config */ 150 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. 151 * Receive terminal count interrupt enable in 152 * top bit. 153 */ 154 volatile u16 mcnt; /* Message byte count (15 bits) */ 155 }; 156 157 /* Convert a length into the 15 bit 2's complement */ 158 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ 159 /* Since we need to set the high bit to enable the completion interrupt this 160 * can be made a lot simpler 161 */ 162 #define cnv_bcnt(len) (-(len)) 163 164 /* Status and config bits for the above */ 165 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ 166 #define TX_STP 0x02 /* Tx: start of packet */ 167 #define TX_ENP 0x01 /* Tx: end of packet */ 168 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ 169 #define RX_FRAM 0x20 /* Rx: framing error */ 170 #define RX_OFLO 0x10 /* Rx: overflow error */ 171 #define RX_CRC 0x08 /* Rx: CRC error */ 172 #define RX_HBUF 0x04 /* Rx: buffer error */ 173 #define RX_STP 0x02 /* Rx: start of packet */ 174 #define RX_ENP 0x01 /* Rx: end of packet */ 175 176 /* Interrupts from the card are caused by various events which are presented 177 * in a circular buffer as several events may be processed on one physical int 178 */ 179 #define MAX_CIRBUFF 32 180 181 struct cirbuff { 182 u8 rdindex; /* read, then increment and wrap */ 183 u8 wrindex; /* write, then increment and wrap */ 184 u8 evntbuff[MAX_CIRBUFF]; 185 }; 186 187 /* Interrupt event codes. 188 * Where appropriate the two low order bits indicate the port number 189 */ 190 #define CTLA_CHG 0x18 /* Control signal changed */ 191 #define CTLB_CHG 0x19 192 #define CTLC_CHG 0x1A 193 #define CTLD_CHG 0x1B 194 195 #define INIT_CPLT 0x20 /* Initialisation complete */ 196 #define INIT_FAIL 0x21 /* Initialisation failed */ 197 198 #define ABTA_SENT 0x24 /* Abort sent */ 199 #define ABTB_SENT 0x25 200 #define ABTC_SENT 0x26 201 #define ABTD_SENT 0x27 202 203 #define TXA_UNDF 0x28 /* Transmission underflow */ 204 #define TXB_UNDF 0x29 205 #define TXC_UNDF 0x2A 206 #define TXD_UNDF 0x2B 207 208 #define F56_INT 0x2C 209 #define M32_INT 0x2D 210 211 #define TE1_ALMA 0x30 212 213 /* Port physical configuration. See farsync.h for field values */ 214 struct port_cfg { 215 u16 lineInterface; /* Physical interface type */ 216 u8 x25op; /* Unused at present */ 217 u8 internalClock; /* 1 => internal clock, 0 => external */ 218 u8 transparentMode; /* 1 => on, 0 => off */ 219 u8 invertClock; /* 0 => normal, 1 => inverted */ 220 u8 padBytes[6]; /* Padding */ 221 u32 lineSpeed; /* Speed in bps */ 222 }; 223 224 /* TE1 port physical configuration */ 225 struct su_config { 226 u32 dataRate; 227 u8 clocking; 228 u8 framing; 229 u8 structure; 230 u8 interface; 231 u8 coding; 232 u8 lineBuildOut; 233 u8 equalizer; 234 u8 transparentMode; 235 u8 loopMode; 236 u8 range; 237 u8 txBufferMode; 238 u8 rxBufferMode; 239 u8 startingSlot; 240 u8 losThreshold; 241 u8 enableIdleCode; 242 u8 idleCode; 243 u8 spare[44]; 244 }; 245 246 /* TE1 Status */ 247 struct su_status { 248 u32 receiveBufferDelay; 249 u32 framingErrorCount; 250 u32 codeViolationCount; 251 u32 crcErrorCount; 252 u32 lineAttenuation; 253 u8 portStarted; 254 u8 lossOfSignal; 255 u8 receiveRemoteAlarm; 256 u8 alarmIndicationSignal; 257 u8 spare[40]; 258 }; 259 260 /* Finally sling all the above together into the shared memory structure. 261 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been 262 * evolving under NT for some time so I guess we're stuck with it. 263 * The structure starts at offset SMC_BASE. 264 * See farsync.h for some field values. 265 */ 266 struct fst_shared { 267 /* DMA descriptor rings */ 268 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; 269 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; 270 271 /* Obsolete small buffers */ 272 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; 273 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; 274 275 u8 taskStatus; /* 0x00 => initialising, 0x01 => running, 276 * 0xFF => halted 277 */ 278 279 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, 280 * set to 0xEE by host to acknowledge interrupt 281 */ 282 283 u16 smcVersion; /* Must match SMC_VERSION */ 284 285 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major 286 * version, RR = revision and BB = build 287 */ 288 289 u16 txa_done; /* Obsolete completion flags */ 290 u16 rxa_done; 291 u16 txb_done; 292 u16 rxb_done; 293 u16 txc_done; 294 u16 rxc_done; 295 u16 txd_done; 296 u16 rxd_done; 297 298 u16 mailbox[4]; /* Diagnostics mailbox. Not used */ 299 300 struct cirbuff interruptEvent; /* interrupt causes */ 301 302 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ 303 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ 304 305 struct port_cfg portConfig[FST_MAX_PORTS]; 306 307 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ 308 309 u16 cableStatus; /* lsb: 0=> present, 1=> absent */ 310 311 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ 312 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ 313 314 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ 315 u16 cardMailbox[4]; /* Not used */ 316 317 /* Number of times the card thinks the host has 318 * missed an interrupt by not acknowledging 319 * within 2mS (I guess NT has problems) 320 */ 321 u32 interruptRetryCount; 322 323 /* Driver private data used as an ID. We'll not 324 * use this as I'd rather keep such things 325 * in main memory rather than on the PCI bus 326 */ 327 u32 portHandle[FST_MAX_PORTS]; 328 329 /* Count of Tx underflows for stats */ 330 u32 transmitBufferUnderflow[FST_MAX_PORTS]; 331 332 /* Debounced V.24 control input status */ 333 u32 v24DebouncedSts[FST_MAX_PORTS]; 334 335 /* Adapter debounce timers. Don't touch */ 336 u32 ctsTimer[FST_MAX_PORTS]; 337 u32 ctsTimerRun[FST_MAX_PORTS]; 338 u32 dcdTimer[FST_MAX_PORTS]; 339 u32 dcdTimerRun[FST_MAX_PORTS]; 340 341 u32 numberOfPorts; /* Number of ports detected at startup */ 342 343 u16 _reserved[64]; 344 345 u16 cardMode; /* Bit-mask to enable features: 346 * Bit 0: 1 enables LED identify mode 347 */ 348 349 u16 portScheduleOffset; 350 351 struct su_config suConfig; /* TE1 Bits */ 352 struct su_status suStatus; 353 354 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of 355 * the structure and marks the end of shared 356 * memory. Adapter code initializes it as 357 * END_SIG. 358 */ 359 }; 360 361 /* endOfSmcSignature value */ 362 #define END_SIG 0x12345678 363 364 /* Mailbox values. (portMailbox) */ 365 #define NOP 0 /* No operation */ 366 #define ACK 1 /* Positive acknowledgement to PC driver */ 367 #define NAK 2 /* Negative acknowledgement to PC driver */ 368 #define STARTPORT 3 /* Start an HDLC port */ 369 #define STOPPORT 4 /* Stop an HDLC port */ 370 #define ABORTTX 5 /* Abort the transmitter for a port */ 371 #define SETV24O 6 /* Set V24 outputs */ 372 373 /* PLX Chip Register Offsets */ 374 #define CNTRL_9052 0x50 /* Control Register */ 375 #define CNTRL_9054 0x6c /* Control Register */ 376 377 #define INTCSR_9052 0x4c /* Interrupt control/status register */ 378 #define INTCSR_9054 0x68 /* Interrupt control/status register */ 379 380 /* 9054 DMA Registers */ 381 /* 382 * Note that we will be using DMA Channel 0 for copying rx data 383 * and Channel 1 for copying tx data 384 */ 385 #define DMAMODE0 0x80 386 #define DMAPADR0 0x84 387 #define DMALADR0 0x88 388 #define DMASIZ0 0x8c 389 #define DMADPR0 0x90 390 #define DMAMODE1 0x94 391 #define DMAPADR1 0x98 392 #define DMALADR1 0x9c 393 #define DMASIZ1 0xa0 394 #define DMADPR1 0xa4 395 #define DMACSR0 0xa8 396 #define DMACSR1 0xa9 397 #define DMAARB 0xac 398 #define DMATHR 0xb0 399 #define DMADAC0 0xb4 400 #define DMADAC1 0xb8 401 #define DMAMARBR 0xac 402 403 #define FST_MIN_DMA_LEN 64 404 #define FST_RX_DMA_INT 0x01 405 #define FST_TX_DMA_INT 0x02 406 #define FST_CARD_INT 0x04 407 408 /* Larger buffers are positioned in memory at offset BFM_BASE */ 409 struct buf_window { 410 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; 411 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; 412 }; 413 414 /* Calculate offset of a buffer object within the shared memory window */ 415 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) 416 417 #pragma pack() 418 419 /* Device driver private information 420 * ================================= 421 */ 422 /* Per port (line or channel) information 423 */ 424 struct fst_port_info { 425 struct net_device *dev; /* Device struct - must be first */ 426 struct fst_card_info *card; /* Card we're associated with */ 427 int index; /* Port index on the card */ 428 int hwif; /* Line hardware (lineInterface copy) */ 429 int run; /* Port is running */ 430 int mode; /* Normal or FarSync raw */ 431 int rxpos; /* Next Rx buffer to use */ 432 int txpos; /* Next Tx buffer to use */ 433 int txipos; /* Next Tx buffer to check for free */ 434 int start; /* Indication of start/stop to network */ 435 /* 436 * A sixteen entry transmit queue 437 */ 438 int txqs; /* index to get next buffer to tx */ 439 int txqe; /* index to queue next packet */ 440 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ 441 int rxqdepth; 442 }; 443 444 /* Per card information 445 */ 446 struct fst_card_info { 447 char __iomem *mem; /* Card memory mapped to kernel space */ 448 char __iomem *ctlmem; /* Control memory for PCI cards */ 449 unsigned int phys_mem; /* Physical memory window address */ 450 unsigned int phys_ctlmem; /* Physical control memory address */ 451 unsigned int irq; /* Interrupt request line number */ 452 unsigned int nports; /* Number of serial ports */ 453 unsigned int type; /* Type index of card */ 454 unsigned int state; /* State of card */ 455 spinlock_t card_lock; /* Lock for SMP access */ 456 unsigned short pci_conf; /* PCI card config in I/O space */ 457 /* Per port info */ 458 struct fst_port_info ports[FST_MAX_PORTS]; 459 struct pci_dev *device; /* Information about the pci device */ 460 int card_no; /* Inst of the card on the system */ 461 int family; /* TxP or TxU */ 462 int dmarx_in_progress; 463 int dmatx_in_progress; 464 unsigned long int_count; 465 unsigned long int_time_ave; 466 void *rx_dma_handle_host; 467 dma_addr_t rx_dma_handle_card; 468 void *tx_dma_handle_host; 469 dma_addr_t tx_dma_handle_card; 470 struct sk_buff *dma_skb_rx; 471 struct fst_port_info *dma_port_rx; 472 struct fst_port_info *dma_port_tx; 473 int dma_len_rx; 474 int dma_len_tx; 475 int dma_txpos; 476 int dma_rxpos; 477 }; 478 479 /* Convert an HDLC device pointer into a port info pointer and similar */ 480 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 481 #define port_to_dev(P) ((P)->dev) 482 483 484 /* 485 * Shared memory window access macros 486 * 487 * We have a nice memory based structure above, which could be directly 488 * mapped on i386 but might not work on other architectures unless we use 489 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take 490 * physical offsets so we have to convert. The only saving grace is that 491 * this should all collapse back to a simple indirection eventually. 492 */ 493 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) 494 495 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) 496 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) 497 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) 498 499 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) 500 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) 501 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) 502 503 /* 504 * Debug support 505 */ 506 #if FST_DEBUG 507 508 static int fst_debug_mask = { FST_DEBUG }; 509 510 /* Most common debug activity is to print something if the corresponding bit 511 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to 512 * support variable numbers of macro parameters. The inverted if prevents us 513 * eating someone else's else clause. 514 */ 515 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \ 516 ; \ 517 else \ 518 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A ) 519 520 #else 521 #define dbg(X...) /* NOP */ 522 #endif 523 524 /* Printing short cuts 525 */ 526 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A ) 527 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A ) 528 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A ) 529 530 /* 531 * PCI ID lookup table 532 */ 533 static struct pci_device_id fst_pci_dev_id[] __devinitdata = { 534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, 535 PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, 536 537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, 538 PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, 539 540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, 541 PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, 542 543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, 544 PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, 545 546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, 547 PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, 548 549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, 550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 551 552 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, 553 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 554 {0,} /* End */ 555 }; 556 557 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); 558 559 /* 560 * Device Driver Work Queues 561 * 562 * So that we don't spend too much time processing events in the 563 * Interrupt Service routine, we will declare a work queue per Card 564 * and make the ISR schedule a task in the queue for later execution. 565 * In the 2.4 Kernel we used to use the immediate queue for BH's 566 * Now that they are gone, tasklets seem to be much better than work 567 * queues. 568 */ 569 570 static void do_bottom_half_tx(struct fst_card_info *card); 571 static void do_bottom_half_rx(struct fst_card_info *card); 572 static void fst_process_tx_work_q(unsigned long work_q); 573 static void fst_process_int_work_q(unsigned long work_q); 574 575 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0); 576 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0); 577 578 static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; 579 static spinlock_t fst_work_q_lock; 580 static u64 fst_work_txq; 581 static u64 fst_work_intq; 582 583 static void 584 fst_q_work_item(u64 * queue, int card_index) 585 { 586 unsigned long flags; 587 u64 mask; 588 589 /* 590 * Grab the queue exclusively 591 */ 592 spin_lock_irqsave(&fst_work_q_lock, flags); 593 594 /* 595 * Making an entry in the queue is simply a matter of setting 596 * a bit for the card indicating that there is work to do in the 597 * bottom half for the card. Note the limitation of 64 cards. 598 * That ought to be enough 599 */ 600 mask = 1 << card_index; 601 *queue |= mask; 602 spin_unlock_irqrestore(&fst_work_q_lock, flags); 603 } 604 605 static void 606 fst_process_tx_work_q(unsigned long /*void **/work_q) 607 { 608 unsigned long flags; 609 u64 work_txq; 610 int i; 611 612 /* 613 * Grab the queue exclusively 614 */ 615 dbg(DBG_TX, "fst_process_tx_work_q\n"); 616 spin_lock_irqsave(&fst_work_q_lock, flags); 617 work_txq = fst_work_txq; 618 fst_work_txq = 0; 619 spin_unlock_irqrestore(&fst_work_q_lock, flags); 620 621 /* 622 * Call the bottom half for each card with work waiting 623 */ 624 for (i = 0; i < FST_MAX_CARDS; i++) { 625 if (work_txq & 0x01) { 626 if (fst_card_array[i] != NULL) { 627 dbg(DBG_TX, "Calling tx bh for card %d\n", i); 628 do_bottom_half_tx(fst_card_array[i]); 629 } 630 } 631 work_txq = work_txq >> 1; 632 } 633 } 634 635 static void 636 fst_process_int_work_q(unsigned long /*void **/work_q) 637 { 638 unsigned long flags; 639 u64 work_intq; 640 int i; 641 642 /* 643 * Grab the queue exclusively 644 */ 645 dbg(DBG_INTR, "fst_process_int_work_q\n"); 646 spin_lock_irqsave(&fst_work_q_lock, flags); 647 work_intq = fst_work_intq; 648 fst_work_intq = 0; 649 spin_unlock_irqrestore(&fst_work_q_lock, flags); 650 651 /* 652 * Call the bottom half for each card with work waiting 653 */ 654 for (i = 0; i < FST_MAX_CARDS; i++) { 655 if (work_intq & 0x01) { 656 if (fst_card_array[i] != NULL) { 657 dbg(DBG_INTR, 658 "Calling rx & tx bh for card %d\n", i); 659 do_bottom_half_rx(fst_card_array[i]); 660 do_bottom_half_tx(fst_card_array[i]); 661 } 662 } 663 work_intq = work_intq >> 1; 664 } 665 } 666 667 /* Card control functions 668 * ====================== 669 */ 670 /* Place the processor in reset state 671 * 672 * Used to be a simple write to card control space but a glitch in the latest 673 * AMD Am186CH processor means that we now have to do it by asserting and de- 674 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register 675 * at offset 9052_CNTRL. Note the updates for the TXU. 676 */ 677 static inline void 678 fst_cpureset(struct fst_card_info *card) 679 { 680 unsigned char interrupt_line_register; 681 unsigned long j = jiffies + 1; 682 unsigned int regval; 683 684 if (card->family == FST_FAMILY_TXU) { 685 if (pci_read_config_byte 686 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { 687 dbg(DBG_ASS, 688 "Error in reading interrupt line register\n"); 689 } 690 /* 691 * Assert PLX software reset and Am186 hardware reset 692 * and then deassert the PLX software reset but 186 still in reset 693 */ 694 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); 695 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 696 /* 697 * We are delaying here to allow the 9054 to reset itself 698 */ 699 j = jiffies + 1; 700 while (jiffies < j) 701 /* Do nothing */ ; 702 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); 703 /* 704 * We are delaying here to allow the 9054 to reload its eeprom 705 */ 706 j = jiffies + 1; 707 while (jiffies < j) 708 /* Do nothing */ ; 709 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 710 711 if (pci_write_config_byte 712 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { 713 dbg(DBG_ASS, 714 "Error in writing interrupt line register\n"); 715 } 716 717 } else { 718 regval = inl(card->pci_conf + CNTRL_9052); 719 720 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); 721 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); 722 } 723 } 724 725 /* Release the processor from reset 726 */ 727 static inline void 728 fst_cpurelease(struct fst_card_info *card) 729 { 730 if (card->family == FST_FAMILY_TXU) { 731 /* 732 * Force posted writes to complete 733 */ 734 (void) readb(card->mem); 735 736 /* 737 * Release LRESET DO = 1 738 * Then release Local Hold, DO = 1 739 */ 740 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); 741 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 742 } else { 743 (void) readb(card->ctlmem); 744 } 745 } 746 747 /* Clear the cards interrupt flag 748 */ 749 static inline void 750 fst_clear_intr(struct fst_card_info *card) 751 { 752 if (card->family == FST_FAMILY_TXU) { 753 (void) readb(card->ctlmem); 754 } else { 755 /* Poke the appropriate PLX chip register (same as enabling interrupts) 756 */ 757 outw(0x0543, card->pci_conf + INTCSR_9052); 758 } 759 } 760 761 /* Enable card interrupts 762 */ 763 static inline void 764 fst_enable_intr(struct fst_card_info *card) 765 { 766 if (card->family == FST_FAMILY_TXU) { 767 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); 768 } else { 769 outw(0x0543, card->pci_conf + INTCSR_9052); 770 } 771 } 772 773 /* Disable card interrupts 774 */ 775 static inline void 776 fst_disable_intr(struct fst_card_info *card) 777 { 778 if (card->family == FST_FAMILY_TXU) { 779 outl(0x00000000, card->pci_conf + INTCSR_9054); 780 } else { 781 outw(0x0000, card->pci_conf + INTCSR_9052); 782 } 783 } 784 785 /* Process the result of trying to pass a received frame up the stack 786 */ 787 static void 788 fst_process_rx_status(int rx_status, char *name) 789 { 790 switch (rx_status) { 791 case NET_RX_SUCCESS: 792 { 793 /* 794 * Nothing to do here 795 */ 796 break; 797 } 798 799 case NET_RX_CN_LOW: 800 { 801 dbg(DBG_ASS, "%s: Receive Low Congestion\n", name); 802 break; 803 } 804 805 case NET_RX_CN_MOD: 806 { 807 dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name); 808 break; 809 } 810 811 case NET_RX_CN_HIGH: 812 { 813 dbg(DBG_ASS, "%s: Receive High Congestion\n", name); 814 break; 815 } 816 817 case NET_RX_DROP: 818 { 819 dbg(DBG_ASS, "%s: Received packet dropped\n", name); 820 break; 821 } 822 } 823 } 824 825 /* Initilaise DMA for PLX 9054 826 */ 827 static inline void 828 fst_init_dma(struct fst_card_info *card) 829 { 830 /* 831 * This is only required for the PLX 9054 832 */ 833 if (card->family == FST_FAMILY_TXU) { 834 pci_set_master(card->device); 835 outl(0x00020441, card->pci_conf + DMAMODE0); 836 outl(0x00020441, card->pci_conf + DMAMODE1); 837 outl(0x0, card->pci_conf + DMATHR); 838 } 839 } 840 841 /* Tx dma complete interrupt 842 */ 843 static void 844 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 845 int len, int txpos) 846 { 847 struct net_device *dev = port_to_dev(port); 848 849 /* 850 * Everything is now set, just tell the card to go 851 */ 852 dbg(DBG_TX, "fst_tx_dma_complete\n"); 853 FST_WRB(card, txDescrRing[port->index][txpos].bits, 854 DMA_OWN | TX_STP | TX_ENP); 855 dev->stats.tx_packets++; 856 dev->stats.tx_bytes += len; 857 dev->trans_start = jiffies; 858 } 859 860 /* 861 * Mark it for our own raw sockets interface 862 */ 863 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) 864 { 865 skb->dev = dev; 866 skb_reset_mac_header(skb); 867 skb->pkt_type = PACKET_HOST; 868 return htons(ETH_P_CUST); 869 } 870 871 /* Rx dma complete interrupt 872 */ 873 static void 874 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 875 int len, struct sk_buff *skb, int rxp) 876 { 877 struct net_device *dev = port_to_dev(port); 878 int pi; 879 int rx_status; 880 881 dbg(DBG_TX, "fst_rx_dma_complete\n"); 882 pi = port->index; 883 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len); 884 885 /* Reset buffer descriptor */ 886 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 887 888 /* Update stats */ 889 dev->stats.rx_packets++; 890 dev->stats.rx_bytes += len; 891 892 /* Push upstream */ 893 dbg(DBG_RX, "Pushing the frame up the stack\n"); 894 if (port->mode == FST_RAW) 895 skb->protocol = farsync_type_trans(skb, dev); 896 else 897 skb->protocol = hdlc_type_trans(skb, dev); 898 rx_status = netif_rx(skb); 899 fst_process_rx_status(rx_status, port_to_dev(port)->name); 900 if (rx_status == NET_RX_DROP) 901 dev->stats.rx_dropped++; 902 dev->last_rx = jiffies; 903 } 904 905 /* 906 * Receive a frame through the DMA 907 */ 908 static inline void 909 fst_rx_dma(struct fst_card_info *card, unsigned char *skb, 910 unsigned char *mem, int len) 911 { 912 /* 913 * This routine will setup the DMA and start it 914 */ 915 916 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len); 917 if (card->dmarx_in_progress) { 918 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); 919 } 920 921 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */ 922 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */ 923 outl(len, card->pci_conf + DMASIZ0); /* for this length */ 924 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ 925 926 /* 927 * We use the dmarx_in_progress flag to flag the channel as busy 928 */ 929 card->dmarx_in_progress = 1; 930 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ 931 } 932 933 /* 934 * Send a frame through the DMA 935 */ 936 static inline void 937 fst_tx_dma(struct fst_card_info *card, unsigned char *skb, 938 unsigned char *mem, int len) 939 { 940 /* 941 * This routine will setup the DMA and start it. 942 */ 943 944 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len); 945 if (card->dmatx_in_progress) { 946 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); 947 } 948 949 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */ 950 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */ 951 outl(len, card->pci_conf + DMASIZ1); /* for this length */ 952 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ 953 954 /* 955 * We use the dmatx_in_progress to flag the channel as busy 956 */ 957 card->dmatx_in_progress = 1; 958 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ 959 } 960 961 /* Issue a Mailbox command for a port. 962 * Note we issue them on a fire and forget basis, not expecting to see an 963 * error and not waiting for completion. 964 */ 965 static void 966 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) 967 { 968 struct fst_card_info *card; 969 unsigned short mbval; 970 unsigned long flags; 971 int safety; 972 973 card = port->card; 974 spin_lock_irqsave(&card->card_lock, flags); 975 mbval = FST_RDW(card, portMailbox[port->index][0]); 976 977 safety = 0; 978 /* Wait for any previous command to complete */ 979 while (mbval > NAK) { 980 spin_unlock_irqrestore(&card->card_lock, flags); 981 schedule_timeout_uninterruptible(1); 982 spin_lock_irqsave(&card->card_lock, flags); 983 984 if (++safety > 2000) { 985 printk_err("Mailbox safety timeout\n"); 986 break; 987 } 988 989 mbval = FST_RDW(card, portMailbox[port->index][0]); 990 } 991 if (safety > 0) { 992 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); 993 } 994 if (mbval == NAK) { 995 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); 996 } 997 998 FST_WRW(card, portMailbox[port->index][0], cmd); 999 1000 if (cmd == ABORTTX || cmd == STARTPORT) { 1001 port->txpos = 0; 1002 port->txipos = 0; 1003 port->start = 0; 1004 } 1005 1006 spin_unlock_irqrestore(&card->card_lock, flags); 1007 } 1008 1009 /* Port output signals control 1010 */ 1011 static inline void 1012 fst_op_raise(struct fst_port_info *port, unsigned int outputs) 1013 { 1014 outputs |= FST_RDL(port->card, v24OpSts[port->index]); 1015 FST_WRL(port->card, v24OpSts[port->index], outputs); 1016 1017 if (port->run) 1018 fst_issue_cmd(port, SETV24O); 1019 } 1020 1021 static inline void 1022 fst_op_lower(struct fst_port_info *port, unsigned int outputs) 1023 { 1024 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); 1025 FST_WRL(port->card, v24OpSts[port->index], outputs); 1026 1027 if (port->run) 1028 fst_issue_cmd(port, SETV24O); 1029 } 1030 1031 /* 1032 * Setup port Rx buffers 1033 */ 1034 static void 1035 fst_rx_config(struct fst_port_info *port) 1036 { 1037 int i; 1038 int pi; 1039 unsigned int offset; 1040 unsigned long flags; 1041 struct fst_card_info *card; 1042 1043 pi = port->index; 1044 card = port->card; 1045 spin_lock_irqsave(&card->card_lock, flags); 1046 for (i = 0; i < NUM_RX_BUFFER; i++) { 1047 offset = BUF_OFFSET(rxBuffer[pi][i][0]); 1048 1049 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); 1050 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1051 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); 1052 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); 1053 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); 1054 } 1055 port->rxpos = 0; 1056 spin_unlock_irqrestore(&card->card_lock, flags); 1057 } 1058 1059 /* 1060 * Setup port Tx buffers 1061 */ 1062 static void 1063 fst_tx_config(struct fst_port_info *port) 1064 { 1065 int i; 1066 int pi; 1067 unsigned int offset; 1068 unsigned long flags; 1069 struct fst_card_info *card; 1070 1071 pi = port->index; 1072 card = port->card; 1073 spin_lock_irqsave(&card->card_lock, flags); 1074 for (i = 0; i < NUM_TX_BUFFER; i++) { 1075 offset = BUF_OFFSET(txBuffer[pi][i][0]); 1076 1077 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); 1078 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1079 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); 1080 FST_WRB(card, txDescrRing[pi][i].bits, 0); 1081 } 1082 port->txpos = 0; 1083 port->txipos = 0; 1084 port->start = 0; 1085 spin_unlock_irqrestore(&card->card_lock, flags); 1086 } 1087 1088 /* TE1 Alarm change interrupt event 1089 */ 1090 static void 1091 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) 1092 { 1093 u8 los; 1094 u8 rra; 1095 u8 ais; 1096 1097 los = FST_RDB(card, suStatus.lossOfSignal); 1098 rra = FST_RDB(card, suStatus.receiveRemoteAlarm); 1099 ais = FST_RDB(card, suStatus.alarmIndicationSignal); 1100 1101 if (los) { 1102 /* 1103 * Lost the link 1104 */ 1105 if (netif_carrier_ok(port_to_dev(port))) { 1106 dbg(DBG_INTR, "Net carrier off\n"); 1107 netif_carrier_off(port_to_dev(port)); 1108 } 1109 } else { 1110 /* 1111 * Link available 1112 */ 1113 if (!netif_carrier_ok(port_to_dev(port))) { 1114 dbg(DBG_INTR, "Net carrier on\n"); 1115 netif_carrier_on(port_to_dev(port)); 1116 } 1117 } 1118 1119 if (los) 1120 dbg(DBG_INTR, "Assert LOS Alarm\n"); 1121 else 1122 dbg(DBG_INTR, "De-assert LOS Alarm\n"); 1123 if (rra) 1124 dbg(DBG_INTR, "Assert RRA Alarm\n"); 1125 else 1126 dbg(DBG_INTR, "De-assert RRA Alarm\n"); 1127 1128 if (ais) 1129 dbg(DBG_INTR, "Assert AIS Alarm\n"); 1130 else 1131 dbg(DBG_INTR, "De-assert AIS Alarm\n"); 1132 } 1133 1134 /* Control signal change interrupt event 1135 */ 1136 static void 1137 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) 1138 { 1139 int signals; 1140 1141 signals = FST_RDL(card, v24DebouncedSts[port->index]); 1142 1143 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 1144 ? IPSTS_INDICATE : IPSTS_DCD)) { 1145 if (!netif_carrier_ok(port_to_dev(port))) { 1146 dbg(DBG_INTR, "DCD active\n"); 1147 netif_carrier_on(port_to_dev(port)); 1148 } 1149 } else { 1150 if (netif_carrier_ok(port_to_dev(port))) { 1151 dbg(DBG_INTR, "DCD lost\n"); 1152 netif_carrier_off(port_to_dev(port)); 1153 } 1154 } 1155 } 1156 1157 /* Log Rx Errors 1158 */ 1159 static void 1160 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1161 unsigned char dmabits, int rxp, unsigned short len) 1162 { 1163 struct net_device *dev = port_to_dev(port); 1164 1165 /* 1166 * Increment the appropriate error counter 1167 */ 1168 dev->stats.rx_errors++; 1169 if (dmabits & RX_OFLO) { 1170 dev->stats.rx_fifo_errors++; 1171 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1172 card->card_no, port->index, rxp); 1173 } 1174 if (dmabits & RX_CRC) { 1175 dev->stats.rx_crc_errors++; 1176 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1177 card->card_no, port->index); 1178 } 1179 if (dmabits & RX_FRAM) { 1180 dev->stats.rx_frame_errors++; 1181 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1182 card->card_no, port->index); 1183 } 1184 if (dmabits == (RX_STP | RX_ENP)) { 1185 dev->stats.rx_length_errors++; 1186 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1187 len, card->card_no, port->index); 1188 } 1189 } 1190 1191 /* Rx Error Recovery 1192 */ 1193 static void 1194 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1195 unsigned char dmabits, int rxp, unsigned short len) 1196 { 1197 int i; 1198 int pi; 1199 1200 pi = port->index; 1201 /* 1202 * Discard buffer descriptors until we see the start of the 1203 * next frame. Note that for long frames this could be in 1204 * a subsequent interrupt. 1205 */ 1206 i = 0; 1207 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { 1208 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1209 rxp = (rxp+1) % NUM_RX_BUFFER; 1210 if (++i > NUM_RX_BUFFER) { 1211 dbg(DBG_ASS, "intr_rx: Discarding more bufs" 1212 " than we have\n"); 1213 break; 1214 } 1215 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1216 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); 1217 } 1218 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); 1219 1220 /* Discard the terminal buffer */ 1221 if (!(dmabits & DMA_OWN)) { 1222 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1223 rxp = (rxp+1) % NUM_RX_BUFFER; 1224 } 1225 port->rxpos = rxp; 1226 return; 1227 1228 } 1229 1230 /* Rx complete interrupt 1231 */ 1232 static void 1233 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) 1234 { 1235 unsigned char dmabits; 1236 int pi; 1237 int rxp; 1238 int rx_status; 1239 unsigned short len; 1240 struct sk_buff *skb; 1241 struct net_device *dev = port_to_dev(port); 1242 1243 /* Check we have a buffer to process */ 1244 pi = port->index; 1245 rxp = port->rxpos; 1246 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1247 if (dmabits & DMA_OWN) { 1248 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", 1249 pi, rxp); 1250 return; 1251 } 1252 if (card->dmarx_in_progress) { 1253 return; 1254 } 1255 1256 /* Get buffer length */ 1257 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); 1258 /* Discard the CRC */ 1259 len -= 2; 1260 if (len == 0) { 1261 /* 1262 * This seems to happen on the TE1 interface sometimes 1263 * so throw the frame away and log the event. 1264 */ 1265 printk_err("Frame received with 0 length. Card %d Port %d\n", 1266 card->card_no, port->index); 1267 /* Return descriptor to card */ 1268 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1269 1270 rxp = (rxp+1) % NUM_RX_BUFFER; 1271 port->rxpos = rxp; 1272 return; 1273 } 1274 1275 /* Check buffer length and for other errors. We insist on one packet 1276 * in one buffer. This simplifies things greatly and since we've 1277 * allocated 8K it shouldn't be a real world limitation 1278 */ 1279 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); 1280 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { 1281 fst_log_rx_error(card, port, dmabits, rxp, len); 1282 fst_recover_rx_error(card, port, dmabits, rxp, len); 1283 return; 1284 } 1285 1286 /* Allocate SKB */ 1287 if ((skb = dev_alloc_skb(len)) == NULL) { 1288 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1289 1290 dev->stats.rx_dropped++; 1291 1292 /* Return descriptor to card */ 1293 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1294 1295 rxp = (rxp+1) % NUM_RX_BUFFER; 1296 port->rxpos = rxp; 1297 return; 1298 } 1299 1300 /* 1301 * We know the length we need to receive, len. 1302 * It's not worth using the DMA for reads of less than 1303 * FST_MIN_DMA_LEN 1304 */ 1305 1306 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { 1307 memcpy_fromio(skb_put(skb, len), 1308 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), 1309 len); 1310 1311 /* Reset buffer descriptor */ 1312 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1313 1314 /* Update stats */ 1315 dev->stats.rx_packets++; 1316 dev->stats.rx_bytes += len; 1317 1318 /* Push upstream */ 1319 dbg(DBG_RX, "Pushing frame up the stack\n"); 1320 if (port->mode == FST_RAW) 1321 skb->protocol = farsync_type_trans(skb, dev); 1322 else 1323 skb->protocol = hdlc_type_trans(skb, dev); 1324 rx_status = netif_rx(skb); 1325 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1326 if (rx_status == NET_RX_DROP) 1327 dev->stats.rx_dropped++; 1328 dev->last_rx = jiffies; 1329 } else { 1330 card->dma_skb_rx = skb; 1331 card->dma_port_rx = port; 1332 card->dma_len_rx = len; 1333 card->dma_rxpos = rxp; 1334 fst_rx_dma(card, (char *) card->rx_dma_handle_card, 1335 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len); 1336 } 1337 if (rxp != port->rxpos) { 1338 dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); 1339 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); 1340 } 1341 rxp = (rxp+1) % NUM_RX_BUFFER; 1342 port->rxpos = rxp; 1343 } 1344 1345 /* 1346 * The bottom halfs to the ISR 1347 * 1348 */ 1349 1350 static void 1351 do_bottom_half_tx(struct fst_card_info *card) 1352 { 1353 struct fst_port_info *port; 1354 int pi; 1355 int txq_length; 1356 struct sk_buff *skb; 1357 unsigned long flags; 1358 struct net_device *dev; 1359 1360 /* 1361 * Find a free buffer for the transmit 1362 * Step through each port on this card 1363 */ 1364 1365 dbg(DBG_TX, "do_bottom_half_tx\n"); 1366 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1367 if (!port->run) 1368 continue; 1369 1370 dev = port_to_dev(port); 1371 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1372 DMA_OWN) 1373 && !(card->dmatx_in_progress)) { 1374 /* 1375 * There doesn't seem to be a txdone event per-se 1376 * We seem to have to deduce it, by checking the DMA_OWN 1377 * bit on the next buffer we think we can use 1378 */ 1379 spin_lock_irqsave(&card->card_lock, flags); 1380 if ((txq_length = port->txqe - port->txqs) < 0) { 1381 /* 1382 * This is the case where one has wrapped and the 1383 * maths gives us a negative number 1384 */ 1385 txq_length = txq_length + FST_TXQ_DEPTH; 1386 } 1387 spin_unlock_irqrestore(&card->card_lock, flags); 1388 if (txq_length > 0) { 1389 /* 1390 * There is something to send 1391 */ 1392 spin_lock_irqsave(&card->card_lock, flags); 1393 skb = port->txq[port->txqs]; 1394 port->txqs++; 1395 if (port->txqs == FST_TXQ_DEPTH) { 1396 port->txqs = 0; 1397 } 1398 spin_unlock_irqrestore(&card->card_lock, flags); 1399 /* 1400 * copy the data and set the required indicators on the 1401 * card. 1402 */ 1403 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, 1404 cnv_bcnt(skb->len)); 1405 if ((skb->len < FST_MIN_DMA_LEN) 1406 || (card->family == FST_FAMILY_TXP)) { 1407 /* Enqueue the packet with normal io */ 1408 memcpy_toio(card->mem + 1409 BUF_OFFSET(txBuffer[pi] 1410 [port-> 1411 txpos][0]), 1412 skb->data, skb->len); 1413 FST_WRB(card, 1414 txDescrRing[pi][port->txpos]. 1415 bits, 1416 DMA_OWN | TX_STP | TX_ENP); 1417 dev->stats.tx_packets++; 1418 dev->stats.tx_bytes += skb->len; 1419 dev->trans_start = jiffies; 1420 } else { 1421 /* Or do it through dma */ 1422 memcpy(card->tx_dma_handle_host, 1423 skb->data, skb->len); 1424 card->dma_port_tx = port; 1425 card->dma_len_tx = skb->len; 1426 card->dma_txpos = port->txpos; 1427 fst_tx_dma(card, 1428 (char *) card-> 1429 tx_dma_handle_card, 1430 (char *) 1431 BUF_OFFSET(txBuffer[pi] 1432 [port->txpos][0]), 1433 skb->len); 1434 } 1435 if (++port->txpos >= NUM_TX_BUFFER) 1436 port->txpos = 0; 1437 /* 1438 * If we have flow control on, can we now release it? 1439 */ 1440 if (port->start) { 1441 if (txq_length < fst_txq_low) { 1442 netif_wake_queue(port_to_dev 1443 (port)); 1444 port->start = 0; 1445 } 1446 } 1447 dev_kfree_skb(skb); 1448 } else { 1449 /* 1450 * Nothing to send so break out of the while loop 1451 */ 1452 break; 1453 } 1454 } 1455 } 1456 } 1457 1458 static void 1459 do_bottom_half_rx(struct fst_card_info *card) 1460 { 1461 struct fst_port_info *port; 1462 int pi; 1463 int rx_count = 0; 1464 1465 /* Check for rx completions on all ports on this card */ 1466 dbg(DBG_RX, "do_bottom_half_rx\n"); 1467 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1468 if (!port->run) 1469 continue; 1470 1471 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) 1472 & DMA_OWN) && !(card->dmarx_in_progress)) { 1473 if (rx_count > fst_max_reads) { 1474 /* 1475 * Don't spend forever in receive processing 1476 * Schedule another event 1477 */ 1478 fst_q_work_item(&fst_work_intq, card->card_no); 1479 tasklet_schedule(&fst_int_task); 1480 break; /* Leave the loop */ 1481 } 1482 fst_intr_rx(card, port); 1483 rx_count++; 1484 } 1485 } 1486 } 1487 1488 /* 1489 * The interrupt service routine 1490 * Dev_id is our fst_card_info pointer 1491 */ 1492 static irqreturn_t 1493 fst_intr(int dummy, void *dev_id) 1494 { 1495 struct fst_card_info *card = dev_id; 1496 struct fst_port_info *port; 1497 int rdidx; /* Event buffer indices */ 1498 int wridx; 1499 int event; /* Actual event for processing */ 1500 unsigned int dma_intcsr = 0; 1501 unsigned int do_card_interrupt; 1502 unsigned int int_retry_count; 1503 1504 /* 1505 * Check to see if the interrupt was for this card 1506 * return if not 1507 * Note that the call to clear the interrupt is important 1508 */ 1509 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); 1510 if (card->state != FST_RUNNING) { 1511 printk_err 1512 ("Interrupt received for card %d in a non running state (%d)\n", 1513 card->card_no, card->state); 1514 1515 /* 1516 * It is possible to really be running, i.e. we have re-loaded 1517 * a running card 1518 * Clear and reprime the interrupt source 1519 */ 1520 fst_clear_intr(card); 1521 return IRQ_HANDLED; 1522 } 1523 1524 /* Clear and reprime the interrupt source */ 1525 fst_clear_intr(card); 1526 1527 /* 1528 * Is the interrupt for this card (handshake == 1) 1529 */ 1530 do_card_interrupt = 0; 1531 if (FST_RDB(card, interruptHandshake) == 1) { 1532 do_card_interrupt += FST_CARD_INT; 1533 /* Set the software acknowledge */ 1534 FST_WRB(card, interruptHandshake, 0xEE); 1535 } 1536 if (card->family == FST_FAMILY_TXU) { 1537 /* 1538 * Is it a DMA Interrupt 1539 */ 1540 dma_intcsr = inl(card->pci_conf + INTCSR_9054); 1541 if (dma_intcsr & 0x00200000) { 1542 /* 1543 * DMA Channel 0 (Rx transfer complete) 1544 */ 1545 dbg(DBG_RX, "DMA Rx xfer complete\n"); 1546 outb(0x8, card->pci_conf + DMACSR0); 1547 fst_rx_dma_complete(card, card->dma_port_rx, 1548 card->dma_len_rx, card->dma_skb_rx, 1549 card->dma_rxpos); 1550 card->dmarx_in_progress = 0; 1551 do_card_interrupt += FST_RX_DMA_INT; 1552 } 1553 if (dma_intcsr & 0x00400000) { 1554 /* 1555 * DMA Channel 1 (Tx transfer complete) 1556 */ 1557 dbg(DBG_TX, "DMA Tx xfer complete\n"); 1558 outb(0x8, card->pci_conf + DMACSR1); 1559 fst_tx_dma_complete(card, card->dma_port_tx, 1560 card->dma_len_tx, card->dma_txpos); 1561 card->dmatx_in_progress = 0; 1562 do_card_interrupt += FST_TX_DMA_INT; 1563 } 1564 } 1565 1566 /* 1567 * Have we been missing Interrupts 1568 */ 1569 int_retry_count = FST_RDL(card, interruptRetryCount); 1570 if (int_retry_count) { 1571 dbg(DBG_ASS, "Card %d int_retry_count is %d\n", 1572 card->card_no, int_retry_count); 1573 FST_WRL(card, interruptRetryCount, 0); 1574 } 1575 1576 if (!do_card_interrupt) { 1577 return IRQ_HANDLED; 1578 } 1579 1580 /* Scehdule the bottom half of the ISR */ 1581 fst_q_work_item(&fst_work_intq, card->card_no); 1582 tasklet_schedule(&fst_int_task); 1583 1584 /* Drain the event queue */ 1585 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; 1586 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; 1587 while (rdidx != wridx) { 1588 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); 1589 port = &card->ports[event & 0x03]; 1590 1591 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); 1592 1593 switch (event) { 1594 case TE1_ALMA: 1595 dbg(DBG_INTR, "TE1 Alarm intr\n"); 1596 if (port->run) 1597 fst_intr_te1_alarm(card, port); 1598 break; 1599 1600 case CTLA_CHG: 1601 case CTLB_CHG: 1602 case CTLC_CHG: 1603 case CTLD_CHG: 1604 if (port->run) 1605 fst_intr_ctlchg(card, port); 1606 break; 1607 1608 case ABTA_SENT: 1609 case ABTB_SENT: 1610 case ABTC_SENT: 1611 case ABTD_SENT: 1612 dbg(DBG_TX, "Abort complete port %d\n", port->index); 1613 break; 1614 1615 case TXA_UNDF: 1616 case TXB_UNDF: 1617 case TXC_UNDF: 1618 case TXD_UNDF: 1619 /* Difficult to see how we'd get this given that we 1620 * always load up the entire packet for DMA. 1621 */ 1622 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1623 port_to_dev(port)->stats.tx_errors++; 1624 port_to_dev(port)->stats.tx_fifo_errors++; 1625 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1626 card->card_no, port->index); 1627 break; 1628 1629 case INIT_CPLT: 1630 dbg(DBG_INIT, "Card init OK intr\n"); 1631 break; 1632 1633 case INIT_FAIL: 1634 dbg(DBG_INIT, "Card init FAILED intr\n"); 1635 card->state = FST_IFAILED; 1636 break; 1637 1638 default: 1639 printk_err("intr: unknown card event %d. ignored\n", 1640 event); 1641 break; 1642 } 1643 1644 /* Bump and wrap the index */ 1645 if (++rdidx >= MAX_CIRBUFF) 1646 rdidx = 0; 1647 } 1648 FST_WRB(card, interruptEvent.rdindex, rdidx); 1649 return IRQ_HANDLED; 1650 } 1651 1652 /* Check that the shared memory configuration is one that we can handle 1653 * and that some basic parameters are correct 1654 */ 1655 static void 1656 check_started_ok(struct fst_card_info *card) 1657 { 1658 int i; 1659 1660 /* Check structure version and end marker */ 1661 if (FST_RDW(card, smcVersion) != SMC_VERSION) { 1662 printk_err("Bad shared memory version %d expected %d\n", 1663 FST_RDW(card, smcVersion), SMC_VERSION); 1664 card->state = FST_BADVERSION; 1665 return; 1666 } 1667 if (FST_RDL(card, endOfSmcSignature) != END_SIG) { 1668 printk_err("Missing shared memory signature\n"); 1669 card->state = FST_BADVERSION; 1670 return; 1671 } 1672 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ 1673 if ((i = FST_RDB(card, taskStatus)) == 0x01) { 1674 card->state = FST_RUNNING; 1675 } else if (i == 0xFF) { 1676 printk_err("Firmware initialisation failed. Card halted\n"); 1677 card->state = FST_HALTED; 1678 return; 1679 } else if (i != 0x00) { 1680 printk_err("Unknown firmware status 0x%x\n", i); 1681 card->state = FST_HALTED; 1682 return; 1683 } 1684 1685 /* Finally check the number of ports reported by firmware against the 1686 * number we assumed at card detection. Should never happen with 1687 * existing firmware etc so we just report it for the moment. 1688 */ 1689 if (FST_RDL(card, numberOfPorts) != card->nports) { 1690 printk_warn("Port count mismatch on card %d." 1691 " Firmware thinks %d we say %d\n", card->card_no, 1692 FST_RDL(card, numberOfPorts), card->nports); 1693 } 1694 } 1695 1696 static int 1697 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, 1698 struct fstioc_info *info) 1699 { 1700 int err; 1701 unsigned char my_framing; 1702 1703 /* Set things according to the user set valid flags 1704 * Several of the old options have been invalidated/replaced by the 1705 * generic hdlc package. 1706 */ 1707 err = 0; 1708 if (info->valid & FSTVAL_PROTO) { 1709 if (info->proto == FST_RAW) 1710 port->mode = FST_RAW; 1711 else 1712 port->mode = FST_GEN_HDLC; 1713 } 1714 1715 if (info->valid & FSTVAL_CABLE) 1716 err = -EINVAL; 1717 1718 if (info->valid & FSTVAL_SPEED) 1719 err = -EINVAL; 1720 1721 if (info->valid & FSTVAL_PHASE) 1722 FST_WRB(card, portConfig[port->index].invertClock, 1723 info->invertClock); 1724 if (info->valid & FSTVAL_MODE) 1725 FST_WRW(card, cardMode, info->cardMode); 1726 if (info->valid & FSTVAL_TE1) { 1727 FST_WRL(card, suConfig.dataRate, info->lineSpeed); 1728 FST_WRB(card, suConfig.clocking, info->clockSource); 1729 my_framing = FRAMING_E1; 1730 if (info->framing == E1) 1731 my_framing = FRAMING_E1; 1732 if (info->framing == T1) 1733 my_framing = FRAMING_T1; 1734 if (info->framing == J1) 1735 my_framing = FRAMING_J1; 1736 FST_WRB(card, suConfig.framing, my_framing); 1737 FST_WRB(card, suConfig.structure, info->structure); 1738 FST_WRB(card, suConfig.interface, info->interface); 1739 FST_WRB(card, suConfig.coding, info->coding); 1740 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); 1741 FST_WRB(card, suConfig.equalizer, info->equalizer); 1742 FST_WRB(card, suConfig.transparentMode, info->transparentMode); 1743 FST_WRB(card, suConfig.loopMode, info->loopMode); 1744 FST_WRB(card, suConfig.range, info->range); 1745 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); 1746 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); 1747 FST_WRB(card, suConfig.startingSlot, info->startingSlot); 1748 FST_WRB(card, suConfig.losThreshold, info->losThreshold); 1749 if (info->idleCode) 1750 FST_WRB(card, suConfig.enableIdleCode, 1); 1751 else 1752 FST_WRB(card, suConfig.enableIdleCode, 0); 1753 FST_WRB(card, suConfig.idleCode, info->idleCode); 1754 #if FST_DEBUG 1755 if (info->valid & FSTVAL_TE1) { 1756 printk("Setting TE1 data\n"); 1757 printk("Line Speed = %d\n", info->lineSpeed); 1758 printk("Start slot = %d\n", info->startingSlot); 1759 printk("Clock source = %d\n", info->clockSource); 1760 printk("Framing = %d\n", my_framing); 1761 printk("Structure = %d\n", info->structure); 1762 printk("interface = %d\n", info->interface); 1763 printk("Coding = %d\n", info->coding); 1764 printk("Line build out = %d\n", info->lineBuildOut); 1765 printk("Equaliser = %d\n", info->equalizer); 1766 printk("Transparent mode = %d\n", 1767 info->transparentMode); 1768 printk("Loop mode = %d\n", info->loopMode); 1769 printk("Range = %d\n", info->range); 1770 printk("Tx Buffer mode = %d\n", info->txBufferMode); 1771 printk("Rx Buffer mode = %d\n", info->rxBufferMode); 1772 printk("LOS Threshold = %d\n", info->losThreshold); 1773 printk("Idle Code = %d\n", info->idleCode); 1774 } 1775 #endif 1776 } 1777 #if FST_DEBUG 1778 if (info->valid & FSTVAL_DEBUG) { 1779 fst_debug_mask = info->debug; 1780 } 1781 #endif 1782 1783 return err; 1784 } 1785 1786 static void 1787 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, 1788 struct fstioc_info *info) 1789 { 1790 int i; 1791 1792 memset(info, 0, sizeof (struct fstioc_info)); 1793 1794 i = port->index; 1795 info->kernelVersion = LINUX_VERSION_CODE; 1796 info->nports = card->nports; 1797 info->type = card->type; 1798 info->state = card->state; 1799 info->proto = FST_GEN_HDLC; 1800 info->index = i; 1801 #if FST_DEBUG 1802 info->debug = fst_debug_mask; 1803 #endif 1804 1805 /* Only mark information as valid if card is running. 1806 * Copy the data anyway in case it is useful for diagnostics 1807 */ 1808 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) 1809 #if FST_DEBUG 1810 | FSTVAL_DEBUG 1811 #endif 1812 ; 1813 1814 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); 1815 info->internalClock = FST_RDB(card, portConfig[i].internalClock); 1816 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); 1817 info->invertClock = FST_RDB(card, portConfig[i].invertClock); 1818 info->v24IpSts = FST_RDL(card, v24IpSts[i]); 1819 info->v24OpSts = FST_RDL(card, v24OpSts[i]); 1820 info->clockStatus = FST_RDW(card, clockStatus[i]); 1821 info->cableStatus = FST_RDW(card, cableStatus); 1822 info->cardMode = FST_RDW(card, cardMode); 1823 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); 1824 1825 /* 1826 * The T2U can report cable presence for both A or B 1827 * in bits 0 and 1 of cableStatus. See which port we are and 1828 * do the mapping. 1829 */ 1830 if (card->family == FST_FAMILY_TXU) { 1831 if (port->index == 0) { 1832 /* 1833 * Port A 1834 */ 1835 info->cableStatus = info->cableStatus & 1; 1836 } else { 1837 /* 1838 * Port B 1839 */ 1840 info->cableStatus = info->cableStatus >> 1; 1841 info->cableStatus = info->cableStatus & 1; 1842 } 1843 } 1844 /* 1845 * Some additional bits if we are TE1 1846 */ 1847 if (card->type == FST_TYPE_TE1) { 1848 info->lineSpeed = FST_RDL(card, suConfig.dataRate); 1849 info->clockSource = FST_RDB(card, suConfig.clocking); 1850 info->framing = FST_RDB(card, suConfig.framing); 1851 info->structure = FST_RDB(card, suConfig.structure); 1852 info->interface = FST_RDB(card, suConfig.interface); 1853 info->coding = FST_RDB(card, suConfig.coding); 1854 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); 1855 info->equalizer = FST_RDB(card, suConfig.equalizer); 1856 info->loopMode = FST_RDB(card, suConfig.loopMode); 1857 info->range = FST_RDB(card, suConfig.range); 1858 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); 1859 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); 1860 info->startingSlot = FST_RDB(card, suConfig.startingSlot); 1861 info->losThreshold = FST_RDB(card, suConfig.losThreshold); 1862 if (FST_RDB(card, suConfig.enableIdleCode)) 1863 info->idleCode = FST_RDB(card, suConfig.idleCode); 1864 else 1865 info->idleCode = 0; 1866 info->receiveBufferDelay = 1867 FST_RDL(card, suStatus.receiveBufferDelay); 1868 info->framingErrorCount = 1869 FST_RDL(card, suStatus.framingErrorCount); 1870 info->codeViolationCount = 1871 FST_RDL(card, suStatus.codeViolationCount); 1872 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); 1873 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); 1874 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); 1875 info->receiveRemoteAlarm = 1876 FST_RDB(card, suStatus.receiveRemoteAlarm); 1877 info->alarmIndicationSignal = 1878 FST_RDB(card, suStatus.alarmIndicationSignal); 1879 } 1880 } 1881 1882 static int 1883 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, 1884 struct ifreq *ifr) 1885 { 1886 sync_serial_settings sync; 1887 int i; 1888 1889 if (ifr->ifr_settings.size != sizeof (sync)) { 1890 return -ENOMEM; 1891 } 1892 1893 if (copy_from_user 1894 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { 1895 return -EFAULT; 1896 } 1897 1898 if (sync.loopback) 1899 return -EINVAL; 1900 1901 i = port->index; 1902 1903 switch (ifr->ifr_settings.type) { 1904 case IF_IFACE_V35: 1905 FST_WRW(card, portConfig[i].lineInterface, V35); 1906 port->hwif = V35; 1907 break; 1908 1909 case IF_IFACE_V24: 1910 FST_WRW(card, portConfig[i].lineInterface, V24); 1911 port->hwif = V24; 1912 break; 1913 1914 case IF_IFACE_X21: 1915 FST_WRW(card, portConfig[i].lineInterface, X21); 1916 port->hwif = X21; 1917 break; 1918 1919 case IF_IFACE_X21D: 1920 FST_WRW(card, portConfig[i].lineInterface, X21D); 1921 port->hwif = X21D; 1922 break; 1923 1924 case IF_IFACE_T1: 1925 FST_WRW(card, portConfig[i].lineInterface, T1); 1926 port->hwif = T1; 1927 break; 1928 1929 case IF_IFACE_E1: 1930 FST_WRW(card, portConfig[i].lineInterface, E1); 1931 port->hwif = E1; 1932 break; 1933 1934 case IF_IFACE_SYNC_SERIAL: 1935 break; 1936 1937 default: 1938 return -EINVAL; 1939 } 1940 1941 switch (sync.clock_type) { 1942 case CLOCK_EXT: 1943 FST_WRB(card, portConfig[i].internalClock, EXTCLK); 1944 break; 1945 1946 case CLOCK_INT: 1947 FST_WRB(card, portConfig[i].internalClock, INTCLK); 1948 break; 1949 1950 default: 1951 return -EINVAL; 1952 } 1953 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); 1954 return 0; 1955 } 1956 1957 static int 1958 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, 1959 struct ifreq *ifr) 1960 { 1961 sync_serial_settings sync; 1962 int i; 1963 1964 /* First check what line type is set, we'll default to reporting X.21 1965 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be 1966 * changed 1967 */ 1968 switch (port->hwif) { 1969 case E1: 1970 ifr->ifr_settings.type = IF_IFACE_E1; 1971 break; 1972 case T1: 1973 ifr->ifr_settings.type = IF_IFACE_T1; 1974 break; 1975 case V35: 1976 ifr->ifr_settings.type = IF_IFACE_V35; 1977 break; 1978 case V24: 1979 ifr->ifr_settings.type = IF_IFACE_V24; 1980 break; 1981 case X21D: 1982 ifr->ifr_settings.type = IF_IFACE_X21D; 1983 break; 1984 case X21: 1985 default: 1986 ifr->ifr_settings.type = IF_IFACE_X21; 1987 break; 1988 } 1989 if (ifr->ifr_settings.size == 0) { 1990 return 0; /* only type requested */ 1991 } 1992 if (ifr->ifr_settings.size < sizeof (sync)) { 1993 return -ENOMEM; 1994 } 1995 1996 i = port->index; 1997 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); 1998 /* Lucky card and linux use same encoding here */ 1999 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == 2000 INTCLK ? CLOCK_INT : CLOCK_EXT; 2001 sync.loopback = 0; 2002 2003 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { 2004 return -EFAULT; 2005 } 2006 2007 ifr->ifr_settings.size = sizeof (sync); 2008 return 0; 2009 } 2010 2011 static int 2012 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2013 { 2014 struct fst_card_info *card; 2015 struct fst_port_info *port; 2016 struct fstioc_write wrthdr; 2017 struct fstioc_info info; 2018 unsigned long flags; 2019 void *buf; 2020 2021 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); 2022 2023 port = dev_to_port(dev); 2024 card = port->card; 2025 2026 if (!capable(CAP_NET_ADMIN)) 2027 return -EPERM; 2028 2029 switch (cmd) { 2030 case FSTCPURESET: 2031 fst_cpureset(card); 2032 card->state = FST_RESET; 2033 return 0; 2034 2035 case FSTCPURELEASE: 2036 fst_cpurelease(card); 2037 card->state = FST_STARTING; 2038 return 0; 2039 2040 case FSTWRITE: /* Code write (download) */ 2041 2042 /* First copy in the header with the length and offset of data 2043 * to write 2044 */ 2045 if (ifr->ifr_data == NULL) { 2046 return -EINVAL; 2047 } 2048 if (copy_from_user(&wrthdr, ifr->ifr_data, 2049 sizeof (struct fstioc_write))) { 2050 return -EFAULT; 2051 } 2052 2053 /* Sanity check the parameters. We don't support partial writes 2054 * when going over the top 2055 */ 2056 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE 2057 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) { 2058 return -ENXIO; 2059 } 2060 2061 /* Now copy the data to the card. */ 2062 2063 buf = kmalloc(wrthdr.size, GFP_KERNEL); 2064 if (!buf) 2065 return -ENOMEM; 2066 2067 if (copy_from_user(buf, 2068 ifr->ifr_data + sizeof (struct fstioc_write), 2069 wrthdr.size)) { 2070 kfree(buf); 2071 return -EFAULT; 2072 } 2073 2074 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); 2075 kfree(buf); 2076 2077 /* Writes to the memory of a card in the reset state constitute 2078 * a download 2079 */ 2080 if (card->state == FST_RESET) { 2081 card->state = FST_DOWNLOAD; 2082 } 2083 return 0; 2084 2085 case FSTGETCONF: 2086 2087 /* If card has just been started check the shared memory config 2088 * version and marker 2089 */ 2090 if (card->state == FST_STARTING) { 2091 check_started_ok(card); 2092 2093 /* If everything checked out enable card interrupts */ 2094 if (card->state == FST_RUNNING) { 2095 spin_lock_irqsave(&card->card_lock, flags); 2096 fst_enable_intr(card); 2097 FST_WRB(card, interruptHandshake, 0xEE); 2098 spin_unlock_irqrestore(&card->card_lock, flags); 2099 } 2100 } 2101 2102 if (ifr->ifr_data == NULL) { 2103 return -EINVAL; 2104 } 2105 2106 gather_conf_info(card, port, &info); 2107 2108 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { 2109 return -EFAULT; 2110 } 2111 return 0; 2112 2113 case FSTSETCONF: 2114 2115 /* 2116 * Most of the settings have been moved to the generic ioctls 2117 * this just covers debug and board ident now 2118 */ 2119 2120 if (card->state != FST_RUNNING) { 2121 printk_err 2122 ("Attempt to configure card %d in non-running state (%d)\n", 2123 card->card_no, card->state); 2124 return -EIO; 2125 } 2126 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { 2127 return -EFAULT; 2128 } 2129 2130 return set_conf_from_info(card, port, &info); 2131 2132 case SIOCWANDEV: 2133 switch (ifr->ifr_settings.type) { 2134 case IF_GET_IFACE: 2135 return fst_get_iface(card, port, ifr); 2136 2137 case IF_IFACE_SYNC_SERIAL: 2138 case IF_IFACE_V35: 2139 case IF_IFACE_V24: 2140 case IF_IFACE_X21: 2141 case IF_IFACE_X21D: 2142 case IF_IFACE_T1: 2143 case IF_IFACE_E1: 2144 return fst_set_iface(card, port, ifr); 2145 2146 case IF_PROTO_RAW: 2147 port->mode = FST_RAW; 2148 return 0; 2149 2150 case IF_GET_PROTO: 2151 if (port->mode == FST_RAW) { 2152 ifr->ifr_settings.type = IF_PROTO_RAW; 2153 return 0; 2154 } 2155 return hdlc_ioctl(dev, ifr, cmd); 2156 2157 default: 2158 port->mode = FST_GEN_HDLC; 2159 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", 2160 ifr->ifr_settings.type); 2161 return hdlc_ioctl(dev, ifr, cmd); 2162 } 2163 2164 default: 2165 /* Not one of ours. Pass through to HDLC package */ 2166 return hdlc_ioctl(dev, ifr, cmd); 2167 } 2168 } 2169 2170 static void 2171 fst_openport(struct fst_port_info *port) 2172 { 2173 int signals; 2174 int txq_length; 2175 2176 /* Only init things if card is actually running. This allows open to 2177 * succeed for downloads etc. 2178 */ 2179 if (port->card->state == FST_RUNNING) { 2180 if (port->run) { 2181 dbg(DBG_OPEN, "open: found port already running\n"); 2182 2183 fst_issue_cmd(port, STOPPORT); 2184 port->run = 0; 2185 } 2186 2187 fst_rx_config(port); 2188 fst_tx_config(port); 2189 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); 2190 2191 fst_issue_cmd(port, STARTPORT); 2192 port->run = 1; 2193 2194 signals = FST_RDL(port->card, v24DebouncedSts[port->index]); 2195 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 2196 ? IPSTS_INDICATE : IPSTS_DCD)) 2197 netif_carrier_on(port_to_dev(port)); 2198 else 2199 netif_carrier_off(port_to_dev(port)); 2200 2201 txq_length = port->txqe - port->txqs; 2202 port->txqe = 0; 2203 port->txqs = 0; 2204 } 2205 2206 } 2207 2208 static void 2209 fst_closeport(struct fst_port_info *port) 2210 { 2211 if (port->card->state == FST_RUNNING) { 2212 if (port->run) { 2213 port->run = 0; 2214 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); 2215 2216 fst_issue_cmd(port, STOPPORT); 2217 } else { 2218 dbg(DBG_OPEN, "close: port not running\n"); 2219 } 2220 } 2221 } 2222 2223 static int 2224 fst_open(struct net_device *dev) 2225 { 2226 int err; 2227 struct fst_port_info *port; 2228 2229 port = dev_to_port(dev); 2230 if (!try_module_get(THIS_MODULE)) 2231 return -EBUSY; 2232 2233 if (port->mode != FST_RAW) { 2234 err = hdlc_open(dev); 2235 if (err) 2236 return err; 2237 } 2238 2239 fst_openport(port); 2240 netif_wake_queue(dev); 2241 return 0; 2242 } 2243 2244 static int 2245 fst_close(struct net_device *dev) 2246 { 2247 struct fst_port_info *port; 2248 struct fst_card_info *card; 2249 unsigned char tx_dma_done; 2250 unsigned char rx_dma_done; 2251 2252 port = dev_to_port(dev); 2253 card = port->card; 2254 2255 tx_dma_done = inb(card->pci_conf + DMACSR1); 2256 rx_dma_done = inb(card->pci_conf + DMACSR0); 2257 dbg(DBG_OPEN, 2258 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", 2259 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, 2260 rx_dma_done); 2261 2262 netif_stop_queue(dev); 2263 fst_closeport(dev_to_port(dev)); 2264 if (port->mode != FST_RAW) { 2265 hdlc_close(dev); 2266 } 2267 module_put(THIS_MODULE); 2268 return 0; 2269 } 2270 2271 static int 2272 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) 2273 { 2274 /* 2275 * Setting currently fixed in FarSync card so we check and forget 2276 */ 2277 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) 2278 return -EINVAL; 2279 return 0; 2280 } 2281 2282 static void 2283 fst_tx_timeout(struct net_device *dev) 2284 { 2285 struct fst_port_info *port; 2286 struct fst_card_info *card; 2287 2288 port = dev_to_port(dev); 2289 card = port->card; 2290 dev->stats.tx_errors++; 2291 dev->stats.tx_aborted_errors++; 2292 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2293 card->card_no, port->index); 2294 fst_issue_cmd(port, ABORTTX); 2295 2296 dev->trans_start = jiffies; 2297 netif_wake_queue(dev); 2298 port->start = 0; 2299 } 2300 2301 static int 2302 fst_start_xmit(struct sk_buff *skb, struct net_device *dev) 2303 { 2304 struct fst_card_info *card; 2305 struct fst_port_info *port; 2306 unsigned long flags; 2307 int txq_length; 2308 2309 port = dev_to_port(dev); 2310 card = port->card; 2311 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); 2312 2313 /* Drop packet with error if we don't have carrier */ 2314 if (!netif_carrier_ok(dev)) { 2315 dev_kfree_skb(skb); 2316 dev->stats.tx_errors++; 2317 dev->stats.tx_carrier_errors++; 2318 dbg(DBG_ASS, 2319 "Tried to transmit but no carrier on card %d port %d\n", 2320 card->card_no, port->index); 2321 return 0; 2322 } 2323 2324 /* Drop it if it's too big! MTU failure ? */ 2325 if (skb->len > LEN_TX_BUFFER) { 2326 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2327 LEN_TX_BUFFER); 2328 dev_kfree_skb(skb); 2329 dev->stats.tx_errors++; 2330 return 0; 2331 } 2332 2333 /* 2334 * We are always going to queue the packet 2335 * so that the bottom half is the only place we tx from 2336 * Check there is room in the port txq 2337 */ 2338 spin_lock_irqsave(&card->card_lock, flags); 2339 if ((txq_length = port->txqe - port->txqs) < 0) { 2340 /* 2341 * This is the case where the next free has wrapped but the 2342 * last used hasn't 2343 */ 2344 txq_length = txq_length + FST_TXQ_DEPTH; 2345 } 2346 spin_unlock_irqrestore(&card->card_lock, flags); 2347 if (txq_length > fst_txq_high) { 2348 /* 2349 * We have got enough buffers in the pipeline. Ask the network 2350 * layer to stop sending frames down 2351 */ 2352 netif_stop_queue(dev); 2353 port->start = 1; /* I'm using this to signal stop sent up */ 2354 } 2355 2356 if (txq_length == FST_TXQ_DEPTH - 1) { 2357 /* 2358 * This shouldn't have happened but such is life 2359 */ 2360 dev_kfree_skb(skb); 2361 dev->stats.tx_errors++; 2362 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2363 card->card_no, port->index); 2364 return 0; 2365 } 2366 2367 /* 2368 * queue the buffer 2369 */ 2370 spin_lock_irqsave(&card->card_lock, flags); 2371 port->txq[port->txqe] = skb; 2372 port->txqe++; 2373 if (port->txqe == FST_TXQ_DEPTH) 2374 port->txqe = 0; 2375 spin_unlock_irqrestore(&card->card_lock, flags); 2376 2377 /* Scehdule the bottom half which now does transmit processing */ 2378 fst_q_work_item(&fst_work_txq, card->card_no); 2379 tasklet_schedule(&fst_tx_task); 2380 2381 return 0; 2382 } 2383 2384 /* 2385 * Card setup having checked hardware resources. 2386 * Should be pretty bizarre if we get an error here (kernel memory 2387 * exhaustion is one possibility). If we do see a problem we report it 2388 * via a printk and leave the corresponding interface and all that follow 2389 * disabled. 2390 */ 2391 static char *type_strings[] __devinitdata = { 2392 "no hardware", /* Should never be seen */ 2393 "FarSync T2P", 2394 "FarSync T4P", 2395 "FarSync T1U", 2396 "FarSync T2U", 2397 "FarSync T4U", 2398 "FarSync TE1" 2399 }; 2400 2401 static void __devinit 2402 fst_init_card(struct fst_card_info *card) 2403 { 2404 int i; 2405 int err; 2406 2407 /* We're working on a number of ports based on the card ID. If the 2408 * firmware detects something different later (should never happen) 2409 * we'll have to revise it in some way then. 2410 */ 2411 for (i = 0; i < card->nports; i++) { 2412 err = register_hdlc_device(card->ports[i].dev); 2413 if (err < 0) { 2414 int j; 2415 printk_err ("Cannot register HDLC device for port %d" 2416 " (errno %d)\n", i, -err ); 2417 for (j = i; j < card->nports; j++) { 2418 free_netdev(card->ports[j].dev); 2419 card->ports[j].dev = NULL; 2420 } 2421 card->nports = i; 2422 break; 2423 } 2424 } 2425 2426 printk_info("%s-%s: %s IRQ%d, %d ports\n", 2427 port_to_dev(&card->ports[0])->name, 2428 port_to_dev(&card->ports[card->nports - 1])->name, 2429 type_strings[card->type], card->irq, card->nports); 2430 } 2431 2432 /* 2433 * Initialise card when detected. 2434 * Returns 0 to indicate success, or errno otherwise. 2435 */ 2436 static int __devinit 2437 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2438 { 2439 static int firsttime_done = 0; 2440 static int no_of_cards_added = 0; 2441 struct fst_card_info *card; 2442 int err = 0; 2443 int i; 2444 2445 if (!firsttime_done) { 2446 printk_info("FarSync WAN driver " FST_USER_VERSION 2447 " (c) 2001-2004 FarSite Communications Ltd.\n"); 2448 firsttime_done = 1; 2449 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); 2450 } 2451 2452 /* 2453 * We are going to be clever and allow certain cards not to be 2454 * configured. An exclude list can be provided in /etc/modules.conf 2455 */ 2456 if (fst_excluded_cards != 0) { 2457 /* 2458 * There are cards to exclude 2459 * 2460 */ 2461 for (i = 0; i < fst_excluded_cards; i++) { 2462 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { 2463 printk_info("FarSync PCI device %d not assigned\n", 2464 (pdev->devfn) >> 3); 2465 return -EBUSY; 2466 } 2467 } 2468 } 2469 2470 /* Allocate driver private data */ 2471 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL); 2472 if (card == NULL) { 2473 printk_err("FarSync card found but insufficient memory for" 2474 " driver storage\n"); 2475 return -ENOMEM; 2476 } 2477 2478 /* Try to enable the device */ 2479 if ((err = pci_enable_device(pdev)) != 0) { 2480 printk_err("Failed to enable card. Err %d\n", -err); 2481 kfree(card); 2482 return err; 2483 } 2484 2485 if ((err = pci_request_regions(pdev, "FarSync")) !=0) { 2486 printk_err("Failed to allocate regions. Err %d\n", -err); 2487 pci_disable_device(pdev); 2488 kfree(card); 2489 return err; 2490 } 2491 2492 /* Get virtual addresses of memory regions */ 2493 card->pci_conf = pci_resource_start(pdev, 1); 2494 card->phys_mem = pci_resource_start(pdev, 2); 2495 card->phys_ctlmem = pci_resource_start(pdev, 3); 2496 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { 2497 printk_err("Physical memory remap failed\n"); 2498 pci_release_regions(pdev); 2499 pci_disable_device(pdev); 2500 kfree(card); 2501 return -ENODEV; 2502 } 2503 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { 2504 printk_err("Control memory remap failed\n"); 2505 pci_release_regions(pdev); 2506 pci_disable_device(pdev); 2507 kfree(card); 2508 return -ENODEV; 2509 } 2510 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); 2511 2512 /* Register the interrupt handler */ 2513 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { 2514 printk_err("Unable to register interrupt %d\n", card->irq); 2515 pci_release_regions(pdev); 2516 pci_disable_device(pdev); 2517 iounmap(card->ctlmem); 2518 iounmap(card->mem); 2519 kfree(card); 2520 return -ENODEV; 2521 } 2522 2523 /* Record info we need */ 2524 card->irq = pdev->irq; 2525 card->type = ent->driver_data; 2526 card->family = ((ent->driver_data == FST_TYPE_T2P) || 2527 (ent->driver_data == FST_TYPE_T4P)) 2528 ? FST_FAMILY_TXP : FST_FAMILY_TXU; 2529 if ((ent->driver_data == FST_TYPE_T1U) || 2530 (ent->driver_data == FST_TYPE_TE1)) 2531 card->nports = 1; 2532 else 2533 card->nports = ((ent->driver_data == FST_TYPE_T2P) || 2534 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; 2535 2536 card->state = FST_UNINIT; 2537 spin_lock_init ( &card->card_lock ); 2538 2539 for ( i = 0 ; i < card->nports ; i++ ) { 2540 struct net_device *dev = alloc_hdlcdev(&card->ports[i]); 2541 hdlc_device *hdlc; 2542 if (!dev) { 2543 while (i--) 2544 free_netdev(card->ports[i].dev); 2545 printk_err ("FarSync: out of memory\n"); 2546 free_irq(card->irq, card); 2547 pci_release_regions(pdev); 2548 pci_disable_device(pdev); 2549 iounmap(card->ctlmem); 2550 iounmap(card->mem); 2551 kfree(card); 2552 return -ENODEV; 2553 } 2554 card->ports[i].dev = dev; 2555 card->ports[i].card = card; 2556 card->ports[i].index = i; 2557 card->ports[i].run = 0; 2558 2559 hdlc = dev_to_hdlc(dev); 2560 2561 /* Fill in the net device info */ 2562 /* Since this is a PCI setup this is purely 2563 * informational. Give them the buffer addresses 2564 * and basic card I/O. 2565 */ 2566 dev->mem_start = card->phys_mem 2567 + BUF_OFFSET ( txBuffer[i][0][0]); 2568 dev->mem_end = card->phys_mem 2569 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]); 2570 dev->base_addr = card->pci_conf; 2571 dev->irq = card->irq; 2572 2573 dev->tx_queue_len = FST_TX_QUEUE_LEN; 2574 dev->open = fst_open; 2575 dev->stop = fst_close; 2576 dev->do_ioctl = fst_ioctl; 2577 dev->watchdog_timeo = FST_TX_TIMEOUT; 2578 dev->tx_timeout = fst_tx_timeout; 2579 hdlc->attach = fst_attach; 2580 hdlc->xmit = fst_start_xmit; 2581 } 2582 2583 card->device = pdev; 2584 2585 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, 2586 card->nports, card->irq); 2587 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", 2588 card->pci_conf, card->phys_mem, card->phys_ctlmem); 2589 2590 /* Reset the card's processor */ 2591 fst_cpureset(card); 2592 card->state = FST_RESET; 2593 2594 /* Initialise DMA (if required) */ 2595 fst_init_dma(card); 2596 2597 /* Record driver data for later use */ 2598 pci_set_drvdata(pdev, card); 2599 2600 /* Remainder of card setup */ 2601 fst_card_array[no_of_cards_added] = card; 2602 card->card_no = no_of_cards_added++; /* Record instance and bump it */ 2603 fst_init_card(card); 2604 if (card->family == FST_FAMILY_TXU) { 2605 /* 2606 * Allocate a dma buffer for transmit and receives 2607 */ 2608 card->rx_dma_handle_host = 2609 pci_alloc_consistent(card->device, FST_MAX_MTU, 2610 &card->rx_dma_handle_card); 2611 if (card->rx_dma_handle_host == NULL) { 2612 printk_err("Could not allocate rx dma buffer\n"); 2613 fst_disable_intr(card); 2614 pci_release_regions(pdev); 2615 pci_disable_device(pdev); 2616 iounmap(card->ctlmem); 2617 iounmap(card->mem); 2618 kfree(card); 2619 return -ENOMEM; 2620 } 2621 card->tx_dma_handle_host = 2622 pci_alloc_consistent(card->device, FST_MAX_MTU, 2623 &card->tx_dma_handle_card); 2624 if (card->tx_dma_handle_host == NULL) { 2625 printk_err("Could not allocate tx dma buffer\n"); 2626 fst_disable_intr(card); 2627 pci_release_regions(pdev); 2628 pci_disable_device(pdev); 2629 iounmap(card->ctlmem); 2630 iounmap(card->mem); 2631 kfree(card); 2632 return -ENOMEM; 2633 } 2634 } 2635 return 0; /* Success */ 2636 } 2637 2638 /* 2639 * Cleanup and close down a card 2640 */ 2641 static void __devexit 2642 fst_remove_one(struct pci_dev *pdev) 2643 { 2644 struct fst_card_info *card; 2645 int i; 2646 2647 card = pci_get_drvdata(pdev); 2648 2649 for (i = 0; i < card->nports; i++) { 2650 struct net_device *dev = port_to_dev(&card->ports[i]); 2651 unregister_hdlc_device(dev); 2652 } 2653 2654 fst_disable_intr(card); 2655 free_irq(card->irq, card); 2656 2657 iounmap(card->ctlmem); 2658 iounmap(card->mem); 2659 pci_release_regions(pdev); 2660 if (card->family == FST_FAMILY_TXU) { 2661 /* 2662 * Free dma buffers 2663 */ 2664 pci_free_consistent(card->device, FST_MAX_MTU, 2665 card->rx_dma_handle_host, 2666 card->rx_dma_handle_card); 2667 pci_free_consistent(card->device, FST_MAX_MTU, 2668 card->tx_dma_handle_host, 2669 card->tx_dma_handle_card); 2670 } 2671 fst_card_array[card->card_no] = NULL; 2672 } 2673 2674 static struct pci_driver fst_driver = { 2675 .name = FST_NAME, 2676 .id_table = fst_pci_dev_id, 2677 .probe = fst_add_one, 2678 .remove = __devexit_p(fst_remove_one), 2679 .suspend = NULL, 2680 .resume = NULL, 2681 }; 2682 2683 static int __init 2684 fst_init(void) 2685 { 2686 int i; 2687 2688 for (i = 0; i < FST_MAX_CARDS; i++) 2689 fst_card_array[i] = NULL; 2690 spin_lock_init(&fst_work_q_lock); 2691 return pci_register_driver(&fst_driver); 2692 } 2693 2694 static void __exit 2695 fst_cleanup_module(void) 2696 { 2697 printk_info("FarSync WAN driver unloading\n"); 2698 pci_unregister_driver(&fst_driver); 2699 } 2700 2701 module_init(fst_init); 2702 module_exit(fst_cleanup_module); 2703