1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "09" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_TEREDO_WAKE_BASE 0xc0c4 55 #define PLA_MAR 0xcd00 56 #define PLA_BACKUP 0xd000 57 #define PAL_BDC_CR 0xd1a0 58 #define PLA_TEREDO_TIMER 0xd2cc 59 #define PLA_REALWOW_TIMER 0xd2e8 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_AFE_CTRL2 0xd824 133 #define USB_UPS_CFG 0xd842 134 #define USB_UPS_FLAGS 0xd848 135 #define USB_WDT11_CTRL 0xe43c 136 #define USB_BP_BA 0xfc26 137 #define USB_BP_0 0xfc28 138 #define USB_BP_1 0xfc2a 139 #define USB_BP_2 0xfc2c 140 #define USB_BP_3 0xfc2e 141 #define USB_BP_4 0xfc30 142 #define USB_BP_5 0xfc32 143 #define USB_BP_6 0xfc34 144 #define USB_BP_7 0xfc36 145 #define USB_BP_EN 0xfc38 146 #define USB_BP_8 0xfc38 147 #define USB_BP_9 0xfc3a 148 #define USB_BP_10 0xfc3c 149 #define USB_BP_11 0xfc3e 150 #define USB_BP_12 0xfc40 151 #define USB_BP_13 0xfc42 152 #define USB_BP_14 0xfc44 153 #define USB_BP_15 0xfc46 154 #define USB_BP2_EN 0xfc48 155 156 /* OCP Registers */ 157 #define OCP_ALDPS_CONFIG 0x2010 158 #define OCP_EEE_CONFIG1 0x2080 159 #define OCP_EEE_CONFIG2 0x2092 160 #define OCP_EEE_CONFIG3 0x2094 161 #define OCP_BASE_MII 0xa400 162 #define OCP_EEE_AR 0xa41a 163 #define OCP_EEE_DATA 0xa41c 164 #define OCP_PHY_STATUS 0xa420 165 #define OCP_NCTL_CFG 0xa42c 166 #define OCP_POWER_CFG 0xa430 167 #define OCP_EEE_CFG 0xa432 168 #define OCP_SRAM_ADDR 0xa436 169 #define OCP_SRAM_DATA 0xa438 170 #define OCP_DOWN_SPEED 0xa442 171 #define OCP_EEE_ABLE 0xa5c4 172 #define OCP_EEE_ADV 0xa5d0 173 #define OCP_EEE_LPABLE 0xa5d2 174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 175 #define OCP_PHY_PATCH_STAT 0xb800 176 #define OCP_PHY_PATCH_CMD 0xb820 177 #define OCP_ADC_IOFFSET 0xbcfc 178 #define OCP_ADC_CFG 0xbc06 179 #define OCP_SYSCLK_CFG 0xc416 180 181 /* SRAM Register */ 182 #define SRAM_GREEN_CFG 0x8011 183 #define SRAM_LPF_CFG 0x8012 184 #define SRAM_10M_AMP1 0x8080 185 #define SRAM_10M_AMP2 0x8082 186 #define SRAM_IMPEDANCE 0x8084 187 188 /* PLA_RCR */ 189 #define RCR_AAP 0x00000001 190 #define RCR_APM 0x00000002 191 #define RCR_AM 0x00000004 192 #define RCR_AB 0x00000008 193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 194 195 /* PLA_RXFIFO_CTRL0 */ 196 #define RXFIFO_THR1_NORMAL 0x00080002 197 #define RXFIFO_THR1_OOB 0x01800003 198 199 /* PLA_RXFIFO_CTRL1 */ 200 #define RXFIFO_THR2_FULL 0x00000060 201 #define RXFIFO_THR2_HIGH 0x00000038 202 #define RXFIFO_THR2_OOB 0x0000004a 203 #define RXFIFO_THR2_NORMAL 0x00a0 204 205 /* PLA_RXFIFO_CTRL2 */ 206 #define RXFIFO_THR3_FULL 0x00000078 207 #define RXFIFO_THR3_HIGH 0x00000048 208 #define RXFIFO_THR3_OOB 0x0000005a 209 #define RXFIFO_THR3_NORMAL 0x0110 210 211 /* PLA_TXFIFO_CTRL */ 212 #define TXFIFO_THR_NORMAL 0x00400008 213 #define TXFIFO_THR_NORMAL2 0x01000008 214 215 /* PLA_DMY_REG0 */ 216 #define ECM_ALDPS 0x0002 217 218 /* PLA_FMC */ 219 #define FMC_FCR_MCU_EN 0x0001 220 221 /* PLA_EEEP_CR */ 222 #define EEEP_CR_EEEP_TX 0x0002 223 224 /* PLA_WDT6_CTRL */ 225 #define WDT6_SET_MODE 0x0010 226 227 /* PLA_TCR0 */ 228 #define TCR0_TX_EMPTY 0x0800 229 #define TCR0_AUTO_FIFO 0x0080 230 231 /* PLA_TCR1 */ 232 #define VERSION_MASK 0x7cf0 233 234 /* PLA_MTPS */ 235 #define MTPS_JUMBO (12 * 1024 / 64) 236 #define MTPS_DEFAULT (6 * 1024 / 64) 237 238 /* PLA_RSTTALLY */ 239 #define TALLY_RESET 0x0001 240 241 /* PLA_CR */ 242 #define CR_RST 0x10 243 #define CR_RE 0x08 244 #define CR_TE 0x04 245 246 /* PLA_CRWECR */ 247 #define CRWECR_NORAML 0x00 248 #define CRWECR_CONFIG 0xc0 249 250 /* PLA_OOB_CTRL */ 251 #define NOW_IS_OOB 0x80 252 #define TXFIFO_EMPTY 0x20 253 #define RXFIFO_EMPTY 0x10 254 #define LINK_LIST_READY 0x02 255 #define DIS_MCU_CLROOB 0x01 256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 257 258 /* PLA_MISC_1 */ 259 #define RXDY_GATED_EN 0x0008 260 261 /* PLA_SFF_STS_7 */ 262 #define RE_INIT_LL 0x8000 263 #define MCU_BORW_EN 0x4000 264 265 /* PLA_CPCR */ 266 #define CPCR_RX_VLAN 0x0040 267 268 /* PLA_CFG_WOL */ 269 #define MAGIC_EN 0x0001 270 271 /* PLA_TEREDO_CFG */ 272 #define TEREDO_SEL 0x8000 273 #define TEREDO_WAKE_MASK 0x7f00 274 #define TEREDO_RS_EVENT_MASK 0x00fe 275 #define OOB_TEREDO_EN 0x0001 276 277 /* PAL_BDC_CR */ 278 #define ALDPS_PROXY_MODE 0x0001 279 280 /* PLA_EFUSE_CMD */ 281 #define EFUSE_READ_CMD BIT(15) 282 #define EFUSE_DATA_BIT16 BIT(7) 283 284 /* PLA_CONFIG34 */ 285 #define LINK_ON_WAKE_EN 0x0010 286 #define LINK_OFF_WAKE_EN 0x0008 287 288 /* PLA_CONFIG5 */ 289 #define BWF_EN 0x0040 290 #define MWF_EN 0x0020 291 #define UWF_EN 0x0010 292 #define LAN_WAKE_EN 0x0002 293 294 /* PLA_LED_FEATURE */ 295 #define LED_MODE_MASK 0x0700 296 297 /* PLA_PHY_PWR */ 298 #define TX_10M_IDLE_EN 0x0080 299 #define PFM_PWM_SWITCH 0x0040 300 301 /* PLA_MAC_PWR_CTRL */ 302 #define D3_CLK_GATED_EN 0x00004000 303 #define MCU_CLK_RATIO 0x07010f07 304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 305 #define ALDPS_SPDWN_RATIO 0x0f87 306 307 /* PLA_MAC_PWR_CTRL2 */ 308 #define EEE_SPDWN_RATIO 0x8007 309 #define MAC_CLK_SPDWN_EN BIT(15) 310 311 /* PLA_MAC_PWR_CTRL3 */ 312 #define PKT_AVAIL_SPDWN_EN 0x0100 313 #define SUSPEND_SPDWN_EN 0x0004 314 #define U1U2_SPDWN_EN 0x0002 315 #define L1_SPDWN_EN 0x0001 316 317 /* PLA_MAC_PWR_CTRL4 */ 318 #define PWRSAVE_SPDWN_EN 0x1000 319 #define RXDV_SPDWN_EN 0x0800 320 #define TX10MIDLE_EN 0x0100 321 #define TP100_SPDWN_EN 0x0020 322 #define TP500_SPDWN_EN 0x0010 323 #define TP1000_SPDWN_EN 0x0008 324 #define EEE_SPDWN_EN 0x0001 325 326 /* PLA_GPHY_INTR_IMR */ 327 #define GPHY_STS_MSK 0x0001 328 #define SPEED_DOWN_MSK 0x0002 329 #define SPDWN_RXDV_MSK 0x0004 330 #define SPDWN_LINKCHG_MSK 0x0008 331 332 /* PLA_PHYAR */ 333 #define PHYAR_FLAG 0x80000000 334 335 /* PLA_EEE_CR */ 336 #define EEE_RX_EN 0x0001 337 #define EEE_TX_EN 0x0002 338 339 /* PLA_BOOT_CTRL */ 340 #define AUTOLOAD_DONE 0x0002 341 342 /* USB_USB2PHY */ 343 #define USB2PHY_SUSPEND 0x0001 344 #define USB2PHY_L1 0x0002 345 346 /* USB_SSPHYLINK2 */ 347 #define pwd_dn_scale_mask 0x3ffe 348 #define pwd_dn_scale(x) ((x) << 1) 349 350 /* USB_CSR_DUMMY1 */ 351 #define DYNAMIC_BURST 0x0001 352 353 /* USB_CSR_DUMMY2 */ 354 #define EP4_FULL_FC 0x0001 355 356 /* USB_DEV_STAT */ 357 #define STAT_SPEED_MASK 0x0006 358 #define STAT_SPEED_HIGH 0x0000 359 #define STAT_SPEED_FULL 0x0002 360 361 /* USB_LPM_CONFIG */ 362 #define LPM_U1U2_EN BIT(0) 363 364 /* USB_TX_AGG */ 365 #define TX_AGG_MAX_THRESHOLD 0x03 366 367 /* USB_RX_BUF_TH */ 368 #define RX_THR_SUPPER 0x0c350180 369 #define RX_THR_HIGH 0x7a120180 370 #define RX_THR_SLOW 0xffff0180 371 #define RX_THR_B 0x00010001 372 373 /* USB_TX_DMA */ 374 #define TEST_MODE_DISABLE 0x00000001 375 #define TX_SIZE_ADJUST1 0x00000100 376 377 /* USB_BMU_RESET */ 378 #define BMU_RESET_EP_IN 0x01 379 #define BMU_RESET_EP_OUT 0x02 380 381 /* USB_UPT_RXDMA_OWN */ 382 #define OWN_UPDATE BIT(0) 383 #define OWN_CLEAR BIT(1) 384 385 /* USB_UPS_CTRL */ 386 #define POWER_CUT 0x0100 387 388 /* USB_PM_CTRL_STATUS */ 389 #define RESUME_INDICATE 0x0001 390 391 /* USB_USB_CTRL */ 392 #define RX_AGG_DISABLE 0x0010 393 #define RX_ZERO_EN 0x0080 394 395 /* USB_U2P3_CTRL */ 396 #define U2P3_ENABLE 0x0001 397 398 /* USB_POWER_CUT */ 399 #define PWR_EN 0x0001 400 #define PHASE2_EN 0x0008 401 #define UPS_EN BIT(4) 402 #define USP_PREWAKE BIT(5) 403 404 /* USB_MISC_0 */ 405 #define PCUT_STATUS 0x0001 406 407 /* USB_RX_EARLY_TIMEOUT */ 408 #define COALESCE_SUPER 85000U 409 #define COALESCE_HIGH 250000U 410 #define COALESCE_SLOW 524280U 411 412 /* USB_WDT11_CTRL */ 413 #define TIMER11_EN 0x0001 414 415 /* USB_LPM_CTRL */ 416 /* bit 4 ~ 5: fifo empty boundary */ 417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 418 /* bit 2 ~ 3: LMP timer */ 419 #define LPM_TIMER_MASK 0x0c 420 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 421 #define LPM_TIMER_500US 0x0c /* 500 us */ 422 #define ROK_EXIT_LPM 0x02 423 424 /* USB_AFE_CTRL2 */ 425 #define SEN_VAL_MASK 0xf800 426 #define SEN_VAL_NORMAL 0xa000 427 #define SEL_RXIDLE 0x0100 428 429 /* USB_UPS_CFG */ 430 #define SAW_CNT_1MS_MASK 0x0fff 431 432 /* USB_UPS_FLAGS */ 433 #define UPS_FLAGS_R_TUNE BIT(0) 434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 435 #define UPS_FLAGS_250M_CKDIV BIT(2) 436 #define UPS_FLAGS_EN_ALDPS BIT(3) 437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 438 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 439 #define ups_flags_speed(x) ((x) << 16) 440 #define UPS_FLAGS_EN_EEE BIT(20) 441 #define UPS_FLAGS_EN_500M_EEE BIT(21) 442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 445 #define UPS_FLAGS_EN_GREEN BIT(26) 446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 447 448 enum spd_duplex { 449 NWAY_10M_HALF = 1, 450 NWAY_10M_FULL, 451 NWAY_100M_HALF, 452 NWAY_100M_FULL, 453 NWAY_1000M_FULL, 454 FORCE_10M_HALF, 455 FORCE_10M_FULL, 456 FORCE_100M_HALF, 457 FORCE_100M_FULL, 458 }; 459 460 /* OCP_ALDPS_CONFIG */ 461 #define ENPWRSAVE 0x8000 462 #define ENPDNPS 0x0200 463 #define LINKENA 0x0100 464 #define DIS_SDSAVE 0x0010 465 466 /* OCP_PHY_STATUS */ 467 #define PHY_STAT_MASK 0x0007 468 #define PHY_STAT_EXT_INIT 2 469 #define PHY_STAT_LAN_ON 3 470 #define PHY_STAT_PWRDN 5 471 472 /* OCP_NCTL_CFG */ 473 #define PGA_RETURN_EN BIT(1) 474 475 /* OCP_POWER_CFG */ 476 #define EEE_CLKDIV_EN 0x8000 477 #define EN_ALDPS 0x0004 478 #define EN_10M_PLLOFF 0x0001 479 480 /* OCP_EEE_CONFIG1 */ 481 #define RG_TXLPI_MSK_HFDUP 0x8000 482 #define RG_MATCLR_EN 0x4000 483 #define EEE_10_CAP 0x2000 484 #define EEE_NWAY_EN 0x1000 485 #define TX_QUIET_EN 0x0200 486 #define RX_QUIET_EN 0x0100 487 #define sd_rise_time_mask 0x0070 488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 489 #define RG_RXLPI_MSK_HFDUP 0x0008 490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 491 492 /* OCP_EEE_CONFIG2 */ 493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 494 #define RG_DACQUIET_EN 0x0400 495 #define RG_LDVQUIET_EN 0x0200 496 #define RG_CKRSEL 0x0020 497 #define RG_EEEPRG_EN 0x0010 498 499 /* OCP_EEE_CONFIG3 */ 500 #define fast_snr_mask 0xff80 501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 504 505 /* OCP_EEE_AR */ 506 /* bit[15:14] function */ 507 #define FUN_ADDR 0x0000 508 #define FUN_DATA 0x4000 509 /* bit[4:0] device addr */ 510 511 /* OCP_EEE_CFG */ 512 #define CTAP_SHORT_EN 0x0040 513 #define EEE10_EN 0x0010 514 515 /* OCP_DOWN_SPEED */ 516 #define EN_EEE_CMODE BIT(14) 517 #define EN_EEE_1000 BIT(13) 518 #define EN_EEE_100 BIT(12) 519 #define EN_10M_CLKDIV BIT(11) 520 #define EN_10M_BGOFF 0x0080 521 522 /* OCP_PHY_STATE */ 523 #define TXDIS_STATE 0x01 524 #define ABD_STATE 0x02 525 526 /* OCP_PHY_PATCH_STAT */ 527 #define PATCH_READY BIT(6) 528 529 /* OCP_PHY_PATCH_CMD */ 530 #define PATCH_REQUEST BIT(4) 531 532 /* OCP_ADC_CFG */ 533 #define CKADSEL_L 0x0100 534 #define ADC_EN 0x0080 535 #define EN_EMI_L 0x0040 536 537 /* OCP_SYSCLK_CFG */ 538 #define clk_div_expo(x) (min(x, 5) << 8) 539 540 /* SRAM_GREEN_CFG */ 541 #define GREEN_ETH_EN BIT(15) 542 #define R_TUNE_EN BIT(11) 543 544 /* SRAM_LPF_CFG */ 545 #define LPF_AUTO_TUNE 0x8000 546 547 /* SRAM_10M_AMP1 */ 548 #define GDAC_IB_UPALL 0x0008 549 550 /* SRAM_10M_AMP2 */ 551 #define AMP_DN 0x0200 552 553 /* SRAM_IMPEDANCE */ 554 #define RX_DRIVING_MASK 0x6000 555 556 /* MAC PASSTHRU */ 557 #define AD_MASK 0xfee0 558 #define EFUSE 0xcfdb 559 #define PASS_THRU_MASK 0x1 560 561 enum rtl_register_content { 562 _1000bps = 0x10, 563 _100bps = 0x08, 564 _10bps = 0x04, 565 LINK_STATUS = 0x02, 566 FULL_DUP = 0x01, 567 }; 568 569 #define RTL8152_MAX_TX 4 570 #define RTL8152_MAX_RX 10 571 #define INTBUFSIZE 2 572 #define TX_ALIGN 4 573 #define RX_ALIGN 8 574 575 #define INTR_LINK 0x0004 576 577 #define RTL8152_REQT_READ 0xc0 578 #define RTL8152_REQT_WRITE 0x40 579 #define RTL8152_REQ_GET_REGS 0x05 580 #define RTL8152_REQ_SET_REGS 0x05 581 582 #define BYTE_EN_DWORD 0xff 583 #define BYTE_EN_WORD 0x33 584 #define BYTE_EN_BYTE 0x11 585 #define BYTE_EN_SIX_BYTES 0x3f 586 #define BYTE_EN_START_MASK 0x0f 587 #define BYTE_EN_END_MASK 0xf0 588 589 #define RTL8153_MAX_PACKET 9216 /* 9K */ 590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 591 ETH_FCS_LEN) 592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 593 #define RTL8153_RMS RTL8153_MAX_PACKET 594 #define RTL8152_TX_TIMEOUT (5 * HZ) 595 #define RTL8152_NAPI_WEIGHT 64 596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 597 sizeof(struct rx_desc) + RX_ALIGN) 598 599 /* rtl8152 flags */ 600 enum rtl8152_flags { 601 RTL8152_UNPLUG = 0, 602 RTL8152_SET_RX_MODE, 603 WORK_ENABLE, 604 RTL8152_LINK_CHG, 605 SELECTIVE_SUSPEND, 606 PHY_RESET, 607 SCHEDULE_NAPI, 608 GREEN_ETHERNET, 609 DELL_TB_RX_AGG_BUG, 610 }; 611 612 /* Define these values to match your device */ 613 #define VENDOR_ID_REALTEK 0x0bda 614 #define VENDOR_ID_MICROSOFT 0x045e 615 #define VENDOR_ID_SAMSUNG 0x04e8 616 #define VENDOR_ID_LENOVO 0x17ef 617 #define VENDOR_ID_LINKSYS 0x13b1 618 #define VENDOR_ID_NVIDIA 0x0955 619 #define VENDOR_ID_TPLINK 0x2357 620 621 #define MCU_TYPE_PLA 0x0100 622 #define MCU_TYPE_USB 0x0000 623 624 struct tally_counter { 625 __le64 tx_packets; 626 __le64 rx_packets; 627 __le64 tx_errors; 628 __le32 rx_errors; 629 __le16 rx_missed; 630 __le16 align_errors; 631 __le32 tx_one_collision; 632 __le32 tx_multi_collision; 633 __le64 rx_unicast; 634 __le64 rx_broadcast; 635 __le32 rx_multicast; 636 __le16 tx_aborted; 637 __le16 tx_underrun; 638 }; 639 640 struct rx_desc { 641 __le32 opts1; 642 #define RX_LEN_MASK 0x7fff 643 644 __le32 opts2; 645 #define RD_UDP_CS BIT(23) 646 #define RD_TCP_CS BIT(22) 647 #define RD_IPV6_CS BIT(20) 648 #define RD_IPV4_CS BIT(19) 649 650 __le32 opts3; 651 #define IPF BIT(23) /* IP checksum fail */ 652 #define UDPF BIT(22) /* UDP checksum fail */ 653 #define TCPF BIT(21) /* TCP checksum fail */ 654 #define RX_VLAN_TAG BIT(16) 655 656 __le32 opts4; 657 __le32 opts5; 658 __le32 opts6; 659 }; 660 661 struct tx_desc { 662 __le32 opts1; 663 #define TX_FS BIT(31) /* First segment of a packet */ 664 #define TX_LS BIT(30) /* Final segment of a packet */ 665 #define GTSENDV4 BIT(28) 666 #define GTSENDV6 BIT(27) 667 #define GTTCPHO_SHIFT 18 668 #define GTTCPHO_MAX 0x7fU 669 #define TX_LEN_MAX 0x3ffffU 670 671 __le32 opts2; 672 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 673 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 674 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 675 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 676 #define MSS_SHIFT 17 677 #define MSS_MAX 0x7ffU 678 #define TCPHO_SHIFT 17 679 #define TCPHO_MAX 0x7ffU 680 #define TX_VLAN_TAG BIT(16) 681 }; 682 683 struct r8152; 684 685 struct rx_agg { 686 struct list_head list; 687 struct urb *urb; 688 struct r8152 *context; 689 void *buffer; 690 void *head; 691 }; 692 693 struct tx_agg { 694 struct list_head list; 695 struct urb *urb; 696 struct r8152 *context; 697 void *buffer; 698 void *head; 699 u32 skb_num; 700 u32 skb_len; 701 }; 702 703 struct r8152 { 704 unsigned long flags; 705 struct usb_device *udev; 706 struct napi_struct napi; 707 struct usb_interface *intf; 708 struct net_device *netdev; 709 struct urb *intr_urb; 710 struct tx_agg tx_info[RTL8152_MAX_TX]; 711 struct rx_agg rx_info[RTL8152_MAX_RX]; 712 struct list_head rx_done, tx_free; 713 struct sk_buff_head tx_queue, rx_queue; 714 spinlock_t rx_lock, tx_lock; 715 struct delayed_work schedule, hw_phy_work; 716 struct mii_if_info mii; 717 struct mutex control; /* use for hw setting */ 718 #ifdef CONFIG_PM_SLEEP 719 struct notifier_block pm_notifier; 720 #endif 721 722 struct rtl_ops { 723 void (*init)(struct r8152 *); 724 int (*enable)(struct r8152 *); 725 void (*disable)(struct r8152 *); 726 void (*up)(struct r8152 *); 727 void (*down)(struct r8152 *); 728 void (*unload)(struct r8152 *); 729 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 730 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 731 bool (*in_nway)(struct r8152 *); 732 void (*hw_phy_cfg)(struct r8152 *); 733 void (*autosuspend_en)(struct r8152 *tp, bool enable); 734 } rtl_ops; 735 736 int intr_interval; 737 u32 saved_wolopts; 738 u32 msg_enable; 739 u32 tx_qlen; 740 u32 coalesce; 741 u16 ocp_base; 742 u16 speed; 743 u8 *intr_buff; 744 u8 version; 745 u8 duplex; 746 u8 autoneg; 747 }; 748 749 enum rtl_version { 750 RTL_VER_UNKNOWN = 0, 751 RTL_VER_01, 752 RTL_VER_02, 753 RTL_VER_03, 754 RTL_VER_04, 755 RTL_VER_05, 756 RTL_VER_06, 757 RTL_VER_07, 758 RTL_VER_08, 759 RTL_VER_09, 760 RTL_VER_MAX 761 }; 762 763 enum tx_csum_stat { 764 TX_CSUM_SUCCESS = 0, 765 TX_CSUM_TSO, 766 TX_CSUM_NONE 767 }; 768 769 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 770 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 771 */ 772 static const int multicast_filter_limit = 32; 773 static unsigned int agg_buf_sz = 16384; 774 775 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 776 VLAN_ETH_HLEN - ETH_FCS_LEN) 777 778 static 779 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 780 { 781 int ret; 782 void *tmp; 783 784 tmp = kmalloc(size, GFP_KERNEL); 785 if (!tmp) 786 return -ENOMEM; 787 788 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 789 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 790 value, index, tmp, size, 500); 791 792 memcpy(data, tmp, size); 793 kfree(tmp); 794 795 return ret; 796 } 797 798 static 799 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 800 { 801 int ret; 802 void *tmp; 803 804 tmp = kmemdup(data, size, GFP_KERNEL); 805 if (!tmp) 806 return -ENOMEM; 807 808 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 809 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 810 value, index, tmp, size, 500); 811 812 kfree(tmp); 813 814 return ret; 815 } 816 817 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 818 void *data, u16 type) 819 { 820 u16 limit = 64; 821 int ret = 0; 822 823 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 824 return -ENODEV; 825 826 /* both size and indix must be 4 bytes align */ 827 if ((size & 3) || !size || (index & 3) || !data) 828 return -EPERM; 829 830 if ((u32)index + (u32)size > 0xffff) 831 return -EPERM; 832 833 while (size) { 834 if (size > limit) { 835 ret = get_registers(tp, index, type, limit, data); 836 if (ret < 0) 837 break; 838 839 index += limit; 840 data += limit; 841 size -= limit; 842 } else { 843 ret = get_registers(tp, index, type, size, data); 844 if (ret < 0) 845 break; 846 847 index += size; 848 data += size; 849 size = 0; 850 break; 851 } 852 } 853 854 if (ret == -ENODEV) 855 set_bit(RTL8152_UNPLUG, &tp->flags); 856 857 return ret; 858 } 859 860 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 861 u16 size, void *data, u16 type) 862 { 863 int ret; 864 u16 byteen_start, byteen_end, byen; 865 u16 limit = 512; 866 867 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 868 return -ENODEV; 869 870 /* both size and indix must be 4 bytes align */ 871 if ((size & 3) || !size || (index & 3) || !data) 872 return -EPERM; 873 874 if ((u32)index + (u32)size > 0xffff) 875 return -EPERM; 876 877 byteen_start = byteen & BYTE_EN_START_MASK; 878 byteen_end = byteen & BYTE_EN_END_MASK; 879 880 byen = byteen_start | (byteen_start << 4); 881 ret = set_registers(tp, index, type | byen, 4, data); 882 if (ret < 0) 883 goto error1; 884 885 index += 4; 886 data += 4; 887 size -= 4; 888 889 if (size) { 890 size -= 4; 891 892 while (size) { 893 if (size > limit) { 894 ret = set_registers(tp, index, 895 type | BYTE_EN_DWORD, 896 limit, data); 897 if (ret < 0) 898 goto error1; 899 900 index += limit; 901 data += limit; 902 size -= limit; 903 } else { 904 ret = set_registers(tp, index, 905 type | BYTE_EN_DWORD, 906 size, data); 907 if (ret < 0) 908 goto error1; 909 910 index += size; 911 data += size; 912 size = 0; 913 break; 914 } 915 } 916 917 byen = byteen_end | (byteen_end >> 4); 918 ret = set_registers(tp, index, type | byen, 4, data); 919 if (ret < 0) 920 goto error1; 921 } 922 923 error1: 924 if (ret == -ENODEV) 925 set_bit(RTL8152_UNPLUG, &tp->flags); 926 927 return ret; 928 } 929 930 static inline 931 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 932 { 933 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 934 } 935 936 static inline 937 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 938 { 939 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 940 } 941 942 static inline 943 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 944 { 945 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 946 } 947 948 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 949 { 950 __le32 data; 951 952 generic_ocp_read(tp, index, sizeof(data), &data, type); 953 954 return __le32_to_cpu(data); 955 } 956 957 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 958 { 959 __le32 tmp = __cpu_to_le32(data); 960 961 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 962 } 963 964 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 965 { 966 u32 data; 967 __le32 tmp; 968 u16 byen = BYTE_EN_WORD; 969 u8 shift = index & 2; 970 971 index &= ~3; 972 byen <<= shift; 973 974 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 975 976 data = __le32_to_cpu(tmp); 977 data >>= (shift * 8); 978 data &= 0xffff; 979 980 return (u16)data; 981 } 982 983 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 984 { 985 u32 mask = 0xffff; 986 __le32 tmp; 987 u16 byen = BYTE_EN_WORD; 988 u8 shift = index & 2; 989 990 data &= mask; 991 992 if (index & 2) { 993 byen <<= shift; 994 mask <<= (shift * 8); 995 data <<= (shift * 8); 996 index &= ~3; 997 } 998 999 tmp = __cpu_to_le32(data); 1000 1001 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1002 } 1003 1004 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1005 { 1006 u32 data; 1007 __le32 tmp; 1008 u8 shift = index & 3; 1009 1010 index &= ~3; 1011 1012 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1013 1014 data = __le32_to_cpu(tmp); 1015 data >>= (shift * 8); 1016 data &= 0xff; 1017 1018 return (u8)data; 1019 } 1020 1021 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1022 { 1023 u32 mask = 0xff; 1024 __le32 tmp; 1025 u16 byen = BYTE_EN_BYTE; 1026 u8 shift = index & 3; 1027 1028 data &= mask; 1029 1030 if (index & 3) { 1031 byen <<= shift; 1032 mask <<= (shift * 8); 1033 data <<= (shift * 8); 1034 index &= ~3; 1035 } 1036 1037 tmp = __cpu_to_le32(data); 1038 1039 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1040 } 1041 1042 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1043 { 1044 u16 ocp_base, ocp_index; 1045 1046 ocp_base = addr & 0xf000; 1047 if (ocp_base != tp->ocp_base) { 1048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1049 tp->ocp_base = ocp_base; 1050 } 1051 1052 ocp_index = (addr & 0x0fff) | 0xb000; 1053 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1054 } 1055 1056 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1057 { 1058 u16 ocp_base, ocp_index; 1059 1060 ocp_base = addr & 0xf000; 1061 if (ocp_base != tp->ocp_base) { 1062 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1063 tp->ocp_base = ocp_base; 1064 } 1065 1066 ocp_index = (addr & 0x0fff) | 0xb000; 1067 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1068 } 1069 1070 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1071 { 1072 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1073 } 1074 1075 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1076 { 1077 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1078 } 1079 1080 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1081 { 1082 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1083 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1084 } 1085 1086 static u16 sram_read(struct r8152 *tp, u16 addr) 1087 { 1088 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1089 return ocp_reg_read(tp, OCP_SRAM_DATA); 1090 } 1091 1092 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1093 { 1094 struct r8152 *tp = netdev_priv(netdev); 1095 int ret; 1096 1097 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1098 return -ENODEV; 1099 1100 if (phy_id != R8152_PHY_ID) 1101 return -EINVAL; 1102 1103 ret = r8152_mdio_read(tp, reg); 1104 1105 return ret; 1106 } 1107 1108 static 1109 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1110 { 1111 struct r8152 *tp = netdev_priv(netdev); 1112 1113 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1114 return; 1115 1116 if (phy_id != R8152_PHY_ID) 1117 return; 1118 1119 r8152_mdio_write(tp, reg, val); 1120 } 1121 1122 static int 1123 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1124 1125 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1126 { 1127 struct r8152 *tp = netdev_priv(netdev); 1128 struct sockaddr *addr = p; 1129 int ret = -EADDRNOTAVAIL; 1130 1131 if (!is_valid_ether_addr(addr->sa_data)) 1132 goto out1; 1133 1134 ret = usb_autopm_get_interface(tp->intf); 1135 if (ret < 0) 1136 goto out1; 1137 1138 mutex_lock(&tp->control); 1139 1140 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1141 1142 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1143 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1144 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1145 1146 mutex_unlock(&tp->control); 1147 1148 usb_autopm_put_interface(tp->intf); 1149 out1: 1150 return ret; 1151 } 1152 1153 /* Devices containing RTL8153-AD can support a persistent 1154 * host system provided MAC address. 1155 * Examples of this are Dell TB15 and Dell WD15 docks 1156 */ 1157 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1158 { 1159 acpi_status status; 1160 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1161 union acpi_object *obj; 1162 int ret = -EINVAL; 1163 u32 ocp_data; 1164 unsigned char buf[6]; 1165 1166 /* test for -AD variant of RTL8153 */ 1167 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1168 if ((ocp_data & AD_MASK) != 0x1000) 1169 return -ENODEV; 1170 1171 /* test for MAC address pass-through bit */ 1172 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1173 if ((ocp_data & PASS_THRU_MASK) != 1) 1174 return -ENODEV; 1175 1176 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1177 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1178 obj = (union acpi_object *)buffer.pointer; 1179 if (!ACPI_SUCCESS(status)) 1180 return -ENODEV; 1181 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1182 netif_warn(tp, probe, tp->netdev, 1183 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1184 obj->type, obj->string.length); 1185 goto amacout; 1186 } 1187 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1188 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1189 netif_warn(tp, probe, tp->netdev, 1190 "Invalid header when reading pass-thru MAC addr\n"); 1191 goto amacout; 1192 } 1193 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1194 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1195 netif_warn(tp, probe, tp->netdev, 1196 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1197 ret, buf); 1198 ret = -EINVAL; 1199 goto amacout; 1200 } 1201 memcpy(sa->sa_data, buf, 6); 1202 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1203 netif_info(tp, probe, tp->netdev, 1204 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1205 1206 amacout: 1207 kfree(obj); 1208 return ret; 1209 } 1210 1211 static int set_ethernet_addr(struct r8152 *tp) 1212 { 1213 struct net_device *dev = tp->netdev; 1214 struct sockaddr sa; 1215 int ret; 1216 1217 if (tp->version == RTL_VER_01) { 1218 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1219 } else { 1220 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1221 * or system doesn't provide valid _SB.AMAC this will be 1222 * be expected to non-zero 1223 */ 1224 ret = vendor_mac_passthru_addr_read(tp, &sa); 1225 if (ret < 0) 1226 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1227 } 1228 1229 if (ret < 0) { 1230 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1231 } else if (!is_valid_ether_addr(sa.sa_data)) { 1232 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1233 sa.sa_data); 1234 eth_hw_addr_random(dev); 1235 ether_addr_copy(sa.sa_data, dev->dev_addr); 1236 ret = rtl8152_set_mac_address(dev, &sa); 1237 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1238 sa.sa_data); 1239 } else { 1240 if (tp->version == RTL_VER_01) 1241 ether_addr_copy(dev->dev_addr, sa.sa_data); 1242 else 1243 ret = rtl8152_set_mac_address(dev, &sa); 1244 } 1245 1246 return ret; 1247 } 1248 1249 static void read_bulk_callback(struct urb *urb) 1250 { 1251 struct net_device *netdev; 1252 int status = urb->status; 1253 struct rx_agg *agg; 1254 struct r8152 *tp; 1255 unsigned long flags; 1256 1257 agg = urb->context; 1258 if (!agg) 1259 return; 1260 1261 tp = agg->context; 1262 if (!tp) 1263 return; 1264 1265 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1266 return; 1267 1268 if (!test_bit(WORK_ENABLE, &tp->flags)) 1269 return; 1270 1271 netdev = tp->netdev; 1272 1273 /* When link down, the driver would cancel all bulks. */ 1274 /* This avoid the re-submitting bulk */ 1275 if (!netif_carrier_ok(netdev)) 1276 return; 1277 1278 usb_mark_last_busy(tp->udev); 1279 1280 switch (status) { 1281 case 0: 1282 if (urb->actual_length < ETH_ZLEN) 1283 break; 1284 1285 spin_lock_irqsave(&tp->rx_lock, flags); 1286 list_add_tail(&agg->list, &tp->rx_done); 1287 spin_unlock_irqrestore(&tp->rx_lock, flags); 1288 napi_schedule(&tp->napi); 1289 return; 1290 case -ESHUTDOWN: 1291 set_bit(RTL8152_UNPLUG, &tp->flags); 1292 netif_device_detach(tp->netdev); 1293 return; 1294 case -ENOENT: 1295 return; /* the urb is in unlink state */ 1296 case -ETIME: 1297 if (net_ratelimit()) 1298 netdev_warn(netdev, "maybe reset is needed?\n"); 1299 break; 1300 default: 1301 if (net_ratelimit()) 1302 netdev_warn(netdev, "Rx status %d\n", status); 1303 break; 1304 } 1305 1306 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1307 } 1308 1309 static void write_bulk_callback(struct urb *urb) 1310 { 1311 struct net_device_stats *stats; 1312 struct net_device *netdev; 1313 struct tx_agg *agg; 1314 struct r8152 *tp; 1315 unsigned long flags; 1316 int status = urb->status; 1317 1318 agg = urb->context; 1319 if (!agg) 1320 return; 1321 1322 tp = agg->context; 1323 if (!tp) 1324 return; 1325 1326 netdev = tp->netdev; 1327 stats = &netdev->stats; 1328 if (status) { 1329 if (net_ratelimit()) 1330 netdev_warn(netdev, "Tx status %d\n", status); 1331 stats->tx_errors += agg->skb_num; 1332 } else { 1333 stats->tx_packets += agg->skb_num; 1334 stats->tx_bytes += agg->skb_len; 1335 } 1336 1337 spin_lock_irqsave(&tp->tx_lock, flags); 1338 list_add_tail(&agg->list, &tp->tx_free); 1339 spin_unlock_irqrestore(&tp->tx_lock, flags); 1340 1341 usb_autopm_put_interface_async(tp->intf); 1342 1343 if (!netif_carrier_ok(netdev)) 1344 return; 1345 1346 if (!test_bit(WORK_ENABLE, &tp->flags)) 1347 return; 1348 1349 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1350 return; 1351 1352 if (!skb_queue_empty(&tp->tx_queue)) 1353 napi_schedule(&tp->napi); 1354 } 1355 1356 static void intr_callback(struct urb *urb) 1357 { 1358 struct r8152 *tp; 1359 __le16 *d; 1360 int status = urb->status; 1361 int res; 1362 1363 tp = urb->context; 1364 if (!tp) 1365 return; 1366 1367 if (!test_bit(WORK_ENABLE, &tp->flags)) 1368 return; 1369 1370 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1371 return; 1372 1373 switch (status) { 1374 case 0: /* success */ 1375 break; 1376 case -ECONNRESET: /* unlink */ 1377 case -ESHUTDOWN: 1378 netif_device_detach(tp->netdev); 1379 case -ENOENT: 1380 case -EPROTO: 1381 netif_info(tp, intr, tp->netdev, 1382 "Stop submitting intr, status %d\n", status); 1383 return; 1384 case -EOVERFLOW: 1385 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1386 goto resubmit; 1387 /* -EPIPE: should clear the halt */ 1388 default: 1389 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1390 goto resubmit; 1391 } 1392 1393 d = urb->transfer_buffer; 1394 if (INTR_LINK & __le16_to_cpu(d[0])) { 1395 if (!netif_carrier_ok(tp->netdev)) { 1396 set_bit(RTL8152_LINK_CHG, &tp->flags); 1397 schedule_delayed_work(&tp->schedule, 0); 1398 } 1399 } else { 1400 if (netif_carrier_ok(tp->netdev)) { 1401 netif_stop_queue(tp->netdev); 1402 set_bit(RTL8152_LINK_CHG, &tp->flags); 1403 schedule_delayed_work(&tp->schedule, 0); 1404 } 1405 } 1406 1407 resubmit: 1408 res = usb_submit_urb(urb, GFP_ATOMIC); 1409 if (res == -ENODEV) { 1410 set_bit(RTL8152_UNPLUG, &tp->flags); 1411 netif_device_detach(tp->netdev); 1412 } else if (res) { 1413 netif_err(tp, intr, tp->netdev, 1414 "can't resubmit intr, status %d\n", res); 1415 } 1416 } 1417 1418 static inline void *rx_agg_align(void *data) 1419 { 1420 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1421 } 1422 1423 static inline void *tx_agg_align(void *data) 1424 { 1425 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1426 } 1427 1428 static void free_all_mem(struct r8152 *tp) 1429 { 1430 int i; 1431 1432 for (i = 0; i < RTL8152_MAX_RX; i++) { 1433 usb_free_urb(tp->rx_info[i].urb); 1434 tp->rx_info[i].urb = NULL; 1435 1436 kfree(tp->rx_info[i].buffer); 1437 tp->rx_info[i].buffer = NULL; 1438 tp->rx_info[i].head = NULL; 1439 } 1440 1441 for (i = 0; i < RTL8152_MAX_TX; i++) { 1442 usb_free_urb(tp->tx_info[i].urb); 1443 tp->tx_info[i].urb = NULL; 1444 1445 kfree(tp->tx_info[i].buffer); 1446 tp->tx_info[i].buffer = NULL; 1447 tp->tx_info[i].head = NULL; 1448 } 1449 1450 usb_free_urb(tp->intr_urb); 1451 tp->intr_urb = NULL; 1452 1453 kfree(tp->intr_buff); 1454 tp->intr_buff = NULL; 1455 } 1456 1457 static int alloc_all_mem(struct r8152 *tp) 1458 { 1459 struct net_device *netdev = tp->netdev; 1460 struct usb_interface *intf = tp->intf; 1461 struct usb_host_interface *alt = intf->cur_altsetting; 1462 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1463 struct urb *urb; 1464 int node, i; 1465 u8 *buf; 1466 1467 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1468 1469 spin_lock_init(&tp->rx_lock); 1470 spin_lock_init(&tp->tx_lock); 1471 INIT_LIST_HEAD(&tp->tx_free); 1472 INIT_LIST_HEAD(&tp->rx_done); 1473 skb_queue_head_init(&tp->tx_queue); 1474 skb_queue_head_init(&tp->rx_queue); 1475 1476 for (i = 0; i < RTL8152_MAX_RX; i++) { 1477 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1478 if (!buf) 1479 goto err1; 1480 1481 if (buf != rx_agg_align(buf)) { 1482 kfree(buf); 1483 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1484 node); 1485 if (!buf) 1486 goto err1; 1487 } 1488 1489 urb = usb_alloc_urb(0, GFP_KERNEL); 1490 if (!urb) { 1491 kfree(buf); 1492 goto err1; 1493 } 1494 1495 INIT_LIST_HEAD(&tp->rx_info[i].list); 1496 tp->rx_info[i].context = tp; 1497 tp->rx_info[i].urb = urb; 1498 tp->rx_info[i].buffer = buf; 1499 tp->rx_info[i].head = rx_agg_align(buf); 1500 } 1501 1502 for (i = 0; i < RTL8152_MAX_TX; i++) { 1503 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1504 if (!buf) 1505 goto err1; 1506 1507 if (buf != tx_agg_align(buf)) { 1508 kfree(buf); 1509 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1510 node); 1511 if (!buf) 1512 goto err1; 1513 } 1514 1515 urb = usb_alloc_urb(0, GFP_KERNEL); 1516 if (!urb) { 1517 kfree(buf); 1518 goto err1; 1519 } 1520 1521 INIT_LIST_HEAD(&tp->tx_info[i].list); 1522 tp->tx_info[i].context = tp; 1523 tp->tx_info[i].urb = urb; 1524 tp->tx_info[i].buffer = buf; 1525 tp->tx_info[i].head = tx_agg_align(buf); 1526 1527 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1528 } 1529 1530 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1531 if (!tp->intr_urb) 1532 goto err1; 1533 1534 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1535 if (!tp->intr_buff) 1536 goto err1; 1537 1538 tp->intr_interval = (int)ep_intr->desc.bInterval; 1539 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1540 tp->intr_buff, INTBUFSIZE, intr_callback, 1541 tp, tp->intr_interval); 1542 1543 return 0; 1544 1545 err1: 1546 free_all_mem(tp); 1547 return -ENOMEM; 1548 } 1549 1550 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1551 { 1552 struct tx_agg *agg = NULL; 1553 unsigned long flags; 1554 1555 if (list_empty(&tp->tx_free)) 1556 return NULL; 1557 1558 spin_lock_irqsave(&tp->tx_lock, flags); 1559 if (!list_empty(&tp->tx_free)) { 1560 struct list_head *cursor; 1561 1562 cursor = tp->tx_free.next; 1563 list_del_init(cursor); 1564 agg = list_entry(cursor, struct tx_agg, list); 1565 } 1566 spin_unlock_irqrestore(&tp->tx_lock, flags); 1567 1568 return agg; 1569 } 1570 1571 /* r8152_csum_workaround() 1572 * The hw limites the value the transport offset. When the offset is out of the 1573 * range, calculate the checksum by sw. 1574 */ 1575 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1576 struct sk_buff_head *list) 1577 { 1578 if (skb_shinfo(skb)->gso_size) { 1579 netdev_features_t features = tp->netdev->features; 1580 struct sk_buff_head seg_list; 1581 struct sk_buff *segs, *nskb; 1582 1583 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1584 segs = skb_gso_segment(skb, features); 1585 if (IS_ERR(segs) || !segs) 1586 goto drop; 1587 1588 __skb_queue_head_init(&seg_list); 1589 1590 do { 1591 nskb = segs; 1592 segs = segs->next; 1593 nskb->next = NULL; 1594 __skb_queue_tail(&seg_list, nskb); 1595 } while (segs); 1596 1597 skb_queue_splice(&seg_list, list); 1598 dev_kfree_skb(skb); 1599 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1600 if (skb_checksum_help(skb) < 0) 1601 goto drop; 1602 1603 __skb_queue_head(list, skb); 1604 } else { 1605 struct net_device_stats *stats; 1606 1607 drop: 1608 stats = &tp->netdev->stats; 1609 stats->tx_dropped++; 1610 dev_kfree_skb(skb); 1611 } 1612 } 1613 1614 /* msdn_giant_send_check() 1615 * According to the document of microsoft, the TCP Pseudo Header excludes the 1616 * packet length for IPv6 TCP large packets. 1617 */ 1618 static int msdn_giant_send_check(struct sk_buff *skb) 1619 { 1620 const struct ipv6hdr *ipv6h; 1621 struct tcphdr *th; 1622 int ret; 1623 1624 ret = skb_cow_head(skb, 0); 1625 if (ret) 1626 return ret; 1627 1628 ipv6h = ipv6_hdr(skb); 1629 th = tcp_hdr(skb); 1630 1631 th->check = 0; 1632 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1633 1634 return ret; 1635 } 1636 1637 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1638 { 1639 if (skb_vlan_tag_present(skb)) { 1640 u32 opts2; 1641 1642 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1643 desc->opts2 |= cpu_to_le32(opts2); 1644 } 1645 } 1646 1647 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1648 { 1649 u32 opts2 = le32_to_cpu(desc->opts2); 1650 1651 if (opts2 & RX_VLAN_TAG) 1652 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1653 swab16(opts2 & 0xffff)); 1654 } 1655 1656 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1657 struct sk_buff *skb, u32 len, u32 transport_offset) 1658 { 1659 u32 mss = skb_shinfo(skb)->gso_size; 1660 u32 opts1, opts2 = 0; 1661 int ret = TX_CSUM_SUCCESS; 1662 1663 WARN_ON_ONCE(len > TX_LEN_MAX); 1664 1665 opts1 = len | TX_FS | TX_LS; 1666 1667 if (mss) { 1668 if (transport_offset > GTTCPHO_MAX) { 1669 netif_warn(tp, tx_err, tp->netdev, 1670 "Invalid transport offset 0x%x for TSO\n", 1671 transport_offset); 1672 ret = TX_CSUM_TSO; 1673 goto unavailable; 1674 } 1675 1676 switch (vlan_get_protocol(skb)) { 1677 case htons(ETH_P_IP): 1678 opts1 |= GTSENDV4; 1679 break; 1680 1681 case htons(ETH_P_IPV6): 1682 if (msdn_giant_send_check(skb)) { 1683 ret = TX_CSUM_TSO; 1684 goto unavailable; 1685 } 1686 opts1 |= GTSENDV6; 1687 break; 1688 1689 default: 1690 WARN_ON_ONCE(1); 1691 break; 1692 } 1693 1694 opts1 |= transport_offset << GTTCPHO_SHIFT; 1695 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1696 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1697 u8 ip_protocol; 1698 1699 if (transport_offset > TCPHO_MAX) { 1700 netif_warn(tp, tx_err, tp->netdev, 1701 "Invalid transport offset 0x%x\n", 1702 transport_offset); 1703 ret = TX_CSUM_NONE; 1704 goto unavailable; 1705 } 1706 1707 switch (vlan_get_protocol(skb)) { 1708 case htons(ETH_P_IP): 1709 opts2 |= IPV4_CS; 1710 ip_protocol = ip_hdr(skb)->protocol; 1711 break; 1712 1713 case htons(ETH_P_IPV6): 1714 opts2 |= IPV6_CS; 1715 ip_protocol = ipv6_hdr(skb)->nexthdr; 1716 break; 1717 1718 default: 1719 ip_protocol = IPPROTO_RAW; 1720 break; 1721 } 1722 1723 if (ip_protocol == IPPROTO_TCP) 1724 opts2 |= TCP_CS; 1725 else if (ip_protocol == IPPROTO_UDP) 1726 opts2 |= UDP_CS; 1727 else 1728 WARN_ON_ONCE(1); 1729 1730 opts2 |= transport_offset << TCPHO_SHIFT; 1731 } 1732 1733 desc->opts2 = cpu_to_le32(opts2); 1734 desc->opts1 = cpu_to_le32(opts1); 1735 1736 unavailable: 1737 return ret; 1738 } 1739 1740 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1741 { 1742 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1743 int remain, ret; 1744 u8 *tx_data; 1745 1746 __skb_queue_head_init(&skb_head); 1747 spin_lock(&tx_queue->lock); 1748 skb_queue_splice_init(tx_queue, &skb_head); 1749 spin_unlock(&tx_queue->lock); 1750 1751 tx_data = agg->head; 1752 agg->skb_num = 0; 1753 agg->skb_len = 0; 1754 remain = agg_buf_sz; 1755 1756 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1757 struct tx_desc *tx_desc; 1758 struct sk_buff *skb; 1759 unsigned int len; 1760 u32 offset; 1761 1762 skb = __skb_dequeue(&skb_head); 1763 if (!skb) 1764 break; 1765 1766 len = skb->len + sizeof(*tx_desc); 1767 1768 if (len > remain) { 1769 __skb_queue_head(&skb_head, skb); 1770 break; 1771 } 1772 1773 tx_data = tx_agg_align(tx_data); 1774 tx_desc = (struct tx_desc *)tx_data; 1775 1776 offset = (u32)skb_transport_offset(skb); 1777 1778 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1779 r8152_csum_workaround(tp, skb, &skb_head); 1780 continue; 1781 } 1782 1783 rtl_tx_vlan_tag(tx_desc, skb); 1784 1785 tx_data += sizeof(*tx_desc); 1786 1787 len = skb->len; 1788 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1789 struct net_device_stats *stats = &tp->netdev->stats; 1790 1791 stats->tx_dropped++; 1792 dev_kfree_skb_any(skb); 1793 tx_data -= sizeof(*tx_desc); 1794 continue; 1795 } 1796 1797 tx_data += len; 1798 agg->skb_len += len; 1799 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1800 1801 dev_kfree_skb_any(skb); 1802 1803 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1804 1805 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1806 break; 1807 } 1808 1809 if (!skb_queue_empty(&skb_head)) { 1810 spin_lock(&tx_queue->lock); 1811 skb_queue_splice(&skb_head, tx_queue); 1812 spin_unlock(&tx_queue->lock); 1813 } 1814 1815 netif_tx_lock(tp->netdev); 1816 1817 if (netif_queue_stopped(tp->netdev) && 1818 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1819 netif_wake_queue(tp->netdev); 1820 1821 netif_tx_unlock(tp->netdev); 1822 1823 ret = usb_autopm_get_interface_async(tp->intf); 1824 if (ret < 0) 1825 goto out_tx_fill; 1826 1827 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1828 agg->head, (int)(tx_data - (u8 *)agg->head), 1829 (usb_complete_t)write_bulk_callback, agg); 1830 1831 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1832 if (ret < 0) 1833 usb_autopm_put_interface_async(tp->intf); 1834 1835 out_tx_fill: 1836 return ret; 1837 } 1838 1839 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1840 { 1841 u8 checksum = CHECKSUM_NONE; 1842 u32 opts2, opts3; 1843 1844 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1845 goto return_result; 1846 1847 opts2 = le32_to_cpu(rx_desc->opts2); 1848 opts3 = le32_to_cpu(rx_desc->opts3); 1849 1850 if (opts2 & RD_IPV4_CS) { 1851 if (opts3 & IPF) 1852 checksum = CHECKSUM_NONE; 1853 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1854 checksum = CHECKSUM_UNNECESSARY; 1855 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1856 checksum = CHECKSUM_UNNECESSARY; 1857 } else if (opts2 & RD_IPV6_CS) { 1858 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1859 checksum = CHECKSUM_UNNECESSARY; 1860 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1861 checksum = CHECKSUM_UNNECESSARY; 1862 } 1863 1864 return_result: 1865 return checksum; 1866 } 1867 1868 static int rx_bottom(struct r8152 *tp, int budget) 1869 { 1870 unsigned long flags; 1871 struct list_head *cursor, *next, rx_queue; 1872 int ret = 0, work_done = 0; 1873 struct napi_struct *napi = &tp->napi; 1874 1875 if (!skb_queue_empty(&tp->rx_queue)) { 1876 while (work_done < budget) { 1877 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1878 struct net_device *netdev = tp->netdev; 1879 struct net_device_stats *stats = &netdev->stats; 1880 unsigned int pkt_len; 1881 1882 if (!skb) 1883 break; 1884 1885 pkt_len = skb->len; 1886 napi_gro_receive(napi, skb); 1887 work_done++; 1888 stats->rx_packets++; 1889 stats->rx_bytes += pkt_len; 1890 } 1891 } 1892 1893 if (list_empty(&tp->rx_done)) 1894 goto out1; 1895 1896 INIT_LIST_HEAD(&rx_queue); 1897 spin_lock_irqsave(&tp->rx_lock, flags); 1898 list_splice_init(&tp->rx_done, &rx_queue); 1899 spin_unlock_irqrestore(&tp->rx_lock, flags); 1900 1901 list_for_each_safe(cursor, next, &rx_queue) { 1902 struct rx_desc *rx_desc; 1903 struct rx_agg *agg; 1904 int len_used = 0; 1905 struct urb *urb; 1906 u8 *rx_data; 1907 1908 list_del_init(cursor); 1909 1910 agg = list_entry(cursor, struct rx_agg, list); 1911 urb = agg->urb; 1912 if (urb->actual_length < ETH_ZLEN) 1913 goto submit; 1914 1915 rx_desc = agg->head; 1916 rx_data = agg->head; 1917 len_used += sizeof(struct rx_desc); 1918 1919 while (urb->actual_length > len_used) { 1920 struct net_device *netdev = tp->netdev; 1921 struct net_device_stats *stats = &netdev->stats; 1922 unsigned int pkt_len; 1923 struct sk_buff *skb; 1924 1925 /* limite the skb numbers for rx_queue */ 1926 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1927 break; 1928 1929 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1930 if (pkt_len < ETH_ZLEN) 1931 break; 1932 1933 len_used += pkt_len; 1934 if (urb->actual_length < len_used) 1935 break; 1936 1937 pkt_len -= ETH_FCS_LEN; 1938 rx_data += sizeof(struct rx_desc); 1939 1940 skb = napi_alloc_skb(napi, pkt_len); 1941 if (!skb) { 1942 stats->rx_dropped++; 1943 goto find_next_rx; 1944 } 1945 1946 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1947 memcpy(skb->data, rx_data, pkt_len); 1948 skb_put(skb, pkt_len); 1949 skb->protocol = eth_type_trans(skb, netdev); 1950 rtl_rx_vlan_tag(rx_desc, skb); 1951 if (work_done < budget) { 1952 napi_gro_receive(napi, skb); 1953 work_done++; 1954 stats->rx_packets++; 1955 stats->rx_bytes += pkt_len; 1956 } else { 1957 __skb_queue_tail(&tp->rx_queue, skb); 1958 } 1959 1960 find_next_rx: 1961 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1962 rx_desc = (struct rx_desc *)rx_data; 1963 len_used = (int)(rx_data - (u8 *)agg->head); 1964 len_used += sizeof(struct rx_desc); 1965 } 1966 1967 submit: 1968 if (!ret) { 1969 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1970 } else { 1971 urb->actual_length = 0; 1972 list_add_tail(&agg->list, next); 1973 } 1974 } 1975 1976 if (!list_empty(&rx_queue)) { 1977 spin_lock_irqsave(&tp->rx_lock, flags); 1978 list_splice_tail(&rx_queue, &tp->rx_done); 1979 spin_unlock_irqrestore(&tp->rx_lock, flags); 1980 } 1981 1982 out1: 1983 return work_done; 1984 } 1985 1986 static void tx_bottom(struct r8152 *tp) 1987 { 1988 int res; 1989 1990 do { 1991 struct tx_agg *agg; 1992 1993 if (skb_queue_empty(&tp->tx_queue)) 1994 break; 1995 1996 agg = r8152_get_tx_agg(tp); 1997 if (!agg) 1998 break; 1999 2000 res = r8152_tx_agg_fill(tp, agg); 2001 if (res) { 2002 struct net_device *netdev = tp->netdev; 2003 2004 if (res == -ENODEV) { 2005 set_bit(RTL8152_UNPLUG, &tp->flags); 2006 netif_device_detach(netdev); 2007 } else { 2008 struct net_device_stats *stats = &netdev->stats; 2009 unsigned long flags; 2010 2011 netif_warn(tp, tx_err, netdev, 2012 "failed tx_urb %d\n", res); 2013 stats->tx_dropped += agg->skb_num; 2014 2015 spin_lock_irqsave(&tp->tx_lock, flags); 2016 list_add_tail(&agg->list, &tp->tx_free); 2017 spin_unlock_irqrestore(&tp->tx_lock, flags); 2018 } 2019 } 2020 } while (res == 0); 2021 } 2022 2023 static void bottom_half(struct r8152 *tp) 2024 { 2025 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2026 return; 2027 2028 if (!test_bit(WORK_ENABLE, &tp->flags)) 2029 return; 2030 2031 /* When link down, the driver would cancel all bulks. */ 2032 /* This avoid the re-submitting bulk */ 2033 if (!netif_carrier_ok(tp->netdev)) 2034 return; 2035 2036 clear_bit(SCHEDULE_NAPI, &tp->flags); 2037 2038 tx_bottom(tp); 2039 } 2040 2041 static int r8152_poll(struct napi_struct *napi, int budget) 2042 { 2043 struct r8152 *tp = container_of(napi, struct r8152, napi); 2044 int work_done; 2045 2046 work_done = rx_bottom(tp, budget); 2047 bottom_half(tp); 2048 2049 if (work_done < budget) { 2050 if (!napi_complete_done(napi, work_done)) 2051 goto out; 2052 if (!list_empty(&tp->rx_done)) 2053 napi_schedule(napi); 2054 else if (!skb_queue_empty(&tp->tx_queue) && 2055 !list_empty(&tp->tx_free)) 2056 napi_schedule(napi); 2057 } 2058 2059 out: 2060 return work_done; 2061 } 2062 2063 static 2064 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2065 { 2066 int ret; 2067 2068 /* The rx would be stopped, so skip submitting */ 2069 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2070 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2071 return 0; 2072 2073 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2074 agg->head, agg_buf_sz, 2075 (usb_complete_t)read_bulk_callback, agg); 2076 2077 ret = usb_submit_urb(agg->urb, mem_flags); 2078 if (ret == -ENODEV) { 2079 set_bit(RTL8152_UNPLUG, &tp->flags); 2080 netif_device_detach(tp->netdev); 2081 } else if (ret) { 2082 struct urb *urb = agg->urb; 2083 unsigned long flags; 2084 2085 urb->actual_length = 0; 2086 spin_lock_irqsave(&tp->rx_lock, flags); 2087 list_add_tail(&agg->list, &tp->rx_done); 2088 spin_unlock_irqrestore(&tp->rx_lock, flags); 2089 2090 netif_err(tp, rx_err, tp->netdev, 2091 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2092 2093 napi_schedule(&tp->napi); 2094 } 2095 2096 return ret; 2097 } 2098 2099 static void rtl_drop_queued_tx(struct r8152 *tp) 2100 { 2101 struct net_device_stats *stats = &tp->netdev->stats; 2102 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2103 struct sk_buff *skb; 2104 2105 if (skb_queue_empty(tx_queue)) 2106 return; 2107 2108 __skb_queue_head_init(&skb_head); 2109 spin_lock_bh(&tx_queue->lock); 2110 skb_queue_splice_init(tx_queue, &skb_head); 2111 spin_unlock_bh(&tx_queue->lock); 2112 2113 while ((skb = __skb_dequeue(&skb_head))) { 2114 dev_kfree_skb(skb); 2115 stats->tx_dropped++; 2116 } 2117 } 2118 2119 static void rtl8152_tx_timeout(struct net_device *netdev) 2120 { 2121 struct r8152 *tp = netdev_priv(netdev); 2122 2123 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2124 2125 usb_queue_reset_device(tp->intf); 2126 } 2127 2128 static void rtl8152_set_rx_mode(struct net_device *netdev) 2129 { 2130 struct r8152 *tp = netdev_priv(netdev); 2131 2132 if (netif_carrier_ok(netdev)) { 2133 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2134 schedule_delayed_work(&tp->schedule, 0); 2135 } 2136 } 2137 2138 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2139 { 2140 struct r8152 *tp = netdev_priv(netdev); 2141 u32 mc_filter[2]; /* Multicast hash filter */ 2142 __le32 tmp[2]; 2143 u32 ocp_data; 2144 2145 netif_stop_queue(netdev); 2146 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2147 ocp_data &= ~RCR_ACPT_ALL; 2148 ocp_data |= RCR_AB | RCR_APM; 2149 2150 if (netdev->flags & IFF_PROMISC) { 2151 /* Unconditionally log net taps. */ 2152 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2153 ocp_data |= RCR_AM | RCR_AAP; 2154 mc_filter[1] = 0xffffffff; 2155 mc_filter[0] = 0xffffffff; 2156 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2157 (netdev->flags & IFF_ALLMULTI)) { 2158 /* Too many to filter perfectly -- accept all multicasts. */ 2159 ocp_data |= RCR_AM; 2160 mc_filter[1] = 0xffffffff; 2161 mc_filter[0] = 0xffffffff; 2162 } else { 2163 struct netdev_hw_addr *ha; 2164 2165 mc_filter[1] = 0; 2166 mc_filter[0] = 0; 2167 netdev_for_each_mc_addr(ha, netdev) { 2168 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2169 2170 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2171 ocp_data |= RCR_AM; 2172 } 2173 } 2174 2175 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2176 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2177 2178 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2179 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2180 netif_wake_queue(netdev); 2181 } 2182 2183 static netdev_features_t 2184 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2185 netdev_features_t features) 2186 { 2187 u32 mss = skb_shinfo(skb)->gso_size; 2188 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2189 int offset = skb_transport_offset(skb); 2190 2191 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2192 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2193 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2194 features &= ~NETIF_F_GSO_MASK; 2195 2196 return features; 2197 } 2198 2199 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2200 struct net_device *netdev) 2201 { 2202 struct r8152 *tp = netdev_priv(netdev); 2203 2204 skb_tx_timestamp(skb); 2205 2206 skb_queue_tail(&tp->tx_queue, skb); 2207 2208 if (!list_empty(&tp->tx_free)) { 2209 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2210 set_bit(SCHEDULE_NAPI, &tp->flags); 2211 schedule_delayed_work(&tp->schedule, 0); 2212 } else { 2213 usb_mark_last_busy(tp->udev); 2214 napi_schedule(&tp->napi); 2215 } 2216 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2217 netif_stop_queue(netdev); 2218 } 2219 2220 return NETDEV_TX_OK; 2221 } 2222 2223 static void r8152b_reset_packet_filter(struct r8152 *tp) 2224 { 2225 u32 ocp_data; 2226 2227 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2228 ocp_data &= ~FMC_FCR_MCU_EN; 2229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2230 ocp_data |= FMC_FCR_MCU_EN; 2231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2232 } 2233 2234 static void rtl8152_nic_reset(struct r8152 *tp) 2235 { 2236 int i; 2237 2238 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2239 2240 for (i = 0; i < 1000; i++) { 2241 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2242 break; 2243 usleep_range(100, 400); 2244 } 2245 } 2246 2247 static void set_tx_qlen(struct r8152 *tp) 2248 { 2249 struct net_device *netdev = tp->netdev; 2250 2251 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2252 sizeof(struct tx_desc)); 2253 } 2254 2255 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2256 { 2257 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2258 } 2259 2260 static void rtl_set_eee_plus(struct r8152 *tp) 2261 { 2262 u32 ocp_data; 2263 u8 speed; 2264 2265 speed = rtl8152_get_speed(tp); 2266 if (speed & _10bps) { 2267 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2268 ocp_data |= EEEP_CR_EEEP_TX; 2269 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2270 } else { 2271 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2272 ocp_data &= ~EEEP_CR_EEEP_TX; 2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2274 } 2275 } 2276 2277 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2278 { 2279 u32 ocp_data; 2280 2281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2282 if (enable) 2283 ocp_data |= RXDY_GATED_EN; 2284 else 2285 ocp_data &= ~RXDY_GATED_EN; 2286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2287 } 2288 2289 static int rtl_start_rx(struct r8152 *tp) 2290 { 2291 int i, ret = 0; 2292 2293 INIT_LIST_HEAD(&tp->rx_done); 2294 for (i = 0; i < RTL8152_MAX_RX; i++) { 2295 INIT_LIST_HEAD(&tp->rx_info[i].list); 2296 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2297 if (ret) 2298 break; 2299 } 2300 2301 if (ret && ++i < RTL8152_MAX_RX) { 2302 struct list_head rx_queue; 2303 unsigned long flags; 2304 2305 INIT_LIST_HEAD(&rx_queue); 2306 2307 do { 2308 struct rx_agg *agg = &tp->rx_info[i++]; 2309 struct urb *urb = agg->urb; 2310 2311 urb->actual_length = 0; 2312 list_add_tail(&agg->list, &rx_queue); 2313 } while (i < RTL8152_MAX_RX); 2314 2315 spin_lock_irqsave(&tp->rx_lock, flags); 2316 list_splice_tail(&rx_queue, &tp->rx_done); 2317 spin_unlock_irqrestore(&tp->rx_lock, flags); 2318 } 2319 2320 return ret; 2321 } 2322 2323 static int rtl_stop_rx(struct r8152 *tp) 2324 { 2325 int i; 2326 2327 for (i = 0; i < RTL8152_MAX_RX; i++) 2328 usb_kill_urb(tp->rx_info[i].urb); 2329 2330 while (!skb_queue_empty(&tp->rx_queue)) 2331 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2332 2333 return 0; 2334 } 2335 2336 static int rtl_enable(struct r8152 *tp) 2337 { 2338 u32 ocp_data; 2339 2340 r8152b_reset_packet_filter(tp); 2341 2342 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2343 ocp_data |= CR_RE | CR_TE; 2344 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2345 2346 rxdy_gated_en(tp, false); 2347 2348 return 0; 2349 } 2350 2351 static int rtl8152_enable(struct r8152 *tp) 2352 { 2353 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2354 return -ENODEV; 2355 2356 set_tx_qlen(tp); 2357 rtl_set_eee_plus(tp); 2358 2359 return rtl_enable(tp); 2360 } 2361 2362 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2363 { 2364 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2365 OWN_UPDATE | OWN_CLEAR); 2366 } 2367 2368 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2369 { 2370 u32 ocp_data = tp->coalesce / 8; 2371 2372 switch (tp->version) { 2373 case RTL_VER_03: 2374 case RTL_VER_04: 2375 case RTL_VER_05: 2376 case RTL_VER_06: 2377 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2378 ocp_data); 2379 break; 2380 2381 case RTL_VER_08: 2382 case RTL_VER_09: 2383 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2384 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2385 */ 2386 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2387 128 / 8); 2388 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2389 ocp_data); 2390 r8153b_rx_agg_chg_indicate(tp); 2391 break; 2392 2393 default: 2394 break; 2395 } 2396 } 2397 2398 static void r8153_set_rx_early_size(struct r8152 *tp) 2399 { 2400 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2401 2402 switch (tp->version) { 2403 case RTL_VER_03: 2404 case RTL_VER_04: 2405 case RTL_VER_05: 2406 case RTL_VER_06: 2407 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2408 ocp_data / 4); 2409 break; 2410 case RTL_VER_08: 2411 case RTL_VER_09: 2412 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2413 ocp_data / 8); 2414 r8153b_rx_agg_chg_indicate(tp); 2415 break; 2416 default: 2417 WARN_ON_ONCE(1); 2418 break; 2419 } 2420 } 2421 2422 static int rtl8153_enable(struct r8152 *tp) 2423 { 2424 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2425 return -ENODEV; 2426 2427 set_tx_qlen(tp); 2428 rtl_set_eee_plus(tp); 2429 r8153_set_rx_early_timeout(tp); 2430 r8153_set_rx_early_size(tp); 2431 2432 return rtl_enable(tp); 2433 } 2434 2435 static void rtl_disable(struct r8152 *tp) 2436 { 2437 u32 ocp_data; 2438 int i; 2439 2440 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2441 rtl_drop_queued_tx(tp); 2442 return; 2443 } 2444 2445 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2446 ocp_data &= ~RCR_ACPT_ALL; 2447 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2448 2449 rtl_drop_queued_tx(tp); 2450 2451 for (i = 0; i < RTL8152_MAX_TX; i++) 2452 usb_kill_urb(tp->tx_info[i].urb); 2453 2454 rxdy_gated_en(tp, true); 2455 2456 for (i = 0; i < 1000; i++) { 2457 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2458 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2459 break; 2460 usleep_range(1000, 2000); 2461 } 2462 2463 for (i = 0; i < 1000; i++) { 2464 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2465 break; 2466 usleep_range(1000, 2000); 2467 } 2468 2469 rtl_stop_rx(tp); 2470 2471 rtl8152_nic_reset(tp); 2472 } 2473 2474 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2475 { 2476 u32 ocp_data; 2477 2478 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2479 if (enable) 2480 ocp_data |= POWER_CUT; 2481 else 2482 ocp_data &= ~POWER_CUT; 2483 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2484 2485 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2486 ocp_data &= ~RESUME_INDICATE; 2487 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2488 } 2489 2490 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2491 { 2492 u32 ocp_data; 2493 2494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2495 if (enable) 2496 ocp_data |= CPCR_RX_VLAN; 2497 else 2498 ocp_data &= ~CPCR_RX_VLAN; 2499 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2500 } 2501 2502 static int rtl8152_set_features(struct net_device *dev, 2503 netdev_features_t features) 2504 { 2505 netdev_features_t changed = features ^ dev->features; 2506 struct r8152 *tp = netdev_priv(dev); 2507 int ret; 2508 2509 ret = usb_autopm_get_interface(tp->intf); 2510 if (ret < 0) 2511 goto out; 2512 2513 mutex_lock(&tp->control); 2514 2515 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2516 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2517 rtl_rx_vlan_en(tp, true); 2518 else 2519 rtl_rx_vlan_en(tp, false); 2520 } 2521 2522 mutex_unlock(&tp->control); 2523 2524 usb_autopm_put_interface(tp->intf); 2525 2526 out: 2527 return ret; 2528 } 2529 2530 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2531 2532 static u32 __rtl_get_wol(struct r8152 *tp) 2533 { 2534 u32 ocp_data; 2535 u32 wolopts = 0; 2536 2537 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2538 if (ocp_data & LINK_ON_WAKE_EN) 2539 wolopts |= WAKE_PHY; 2540 2541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2542 if (ocp_data & UWF_EN) 2543 wolopts |= WAKE_UCAST; 2544 if (ocp_data & BWF_EN) 2545 wolopts |= WAKE_BCAST; 2546 if (ocp_data & MWF_EN) 2547 wolopts |= WAKE_MCAST; 2548 2549 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2550 if (ocp_data & MAGIC_EN) 2551 wolopts |= WAKE_MAGIC; 2552 2553 return wolopts; 2554 } 2555 2556 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2557 { 2558 u32 ocp_data; 2559 2560 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2561 2562 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2563 ocp_data &= ~LINK_ON_WAKE_EN; 2564 if (wolopts & WAKE_PHY) 2565 ocp_data |= LINK_ON_WAKE_EN; 2566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2567 2568 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2569 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2570 if (wolopts & WAKE_UCAST) 2571 ocp_data |= UWF_EN; 2572 if (wolopts & WAKE_BCAST) 2573 ocp_data |= BWF_EN; 2574 if (wolopts & WAKE_MCAST) 2575 ocp_data |= MWF_EN; 2576 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2577 2578 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2579 2580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2581 ocp_data &= ~MAGIC_EN; 2582 if (wolopts & WAKE_MAGIC) 2583 ocp_data |= MAGIC_EN; 2584 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2585 2586 if (wolopts & WAKE_ANY) 2587 device_set_wakeup_enable(&tp->udev->dev, true); 2588 else 2589 device_set_wakeup_enable(&tp->udev->dev, false); 2590 } 2591 2592 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2593 { 2594 /* MAC clock speed down */ 2595 if (enable) { 2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2597 ALDPS_SPDWN_RATIO); 2598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2599 EEE_SPDWN_RATIO); 2600 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2601 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2602 U1U2_SPDWN_EN | L1_SPDWN_EN); 2603 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2604 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2605 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2606 TP1000_SPDWN_EN); 2607 } else { 2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2612 } 2613 } 2614 2615 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2616 { 2617 u8 u1u2[8]; 2618 2619 if (enable) 2620 memset(u1u2, 0xff, sizeof(u1u2)); 2621 else 2622 memset(u1u2, 0x00, sizeof(u1u2)); 2623 2624 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2625 } 2626 2627 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2628 { 2629 u32 ocp_data; 2630 2631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2632 if (enable) 2633 ocp_data |= LPM_U1U2_EN; 2634 else 2635 ocp_data &= ~LPM_U1U2_EN; 2636 2637 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2638 } 2639 2640 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2641 { 2642 u32 ocp_data; 2643 2644 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2645 if (enable) 2646 ocp_data |= U2P3_ENABLE; 2647 else 2648 ocp_data &= ~U2P3_ENABLE; 2649 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2650 } 2651 2652 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2653 { 2654 u32 ocp_data; 2655 2656 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2657 ocp_data &= ~clear; 2658 ocp_data |= set; 2659 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2660 } 2661 2662 static void r8153b_green_en(struct r8152 *tp, bool enable) 2663 { 2664 u16 data; 2665 2666 if (enable) { 2667 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2668 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2669 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2670 } else { 2671 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2672 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2673 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2674 } 2675 2676 data = sram_read(tp, SRAM_GREEN_CFG); 2677 data |= GREEN_ETH_EN; 2678 sram_write(tp, SRAM_GREEN_CFG, data); 2679 2680 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2681 } 2682 2683 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2684 { 2685 u16 data; 2686 int i; 2687 2688 for (i = 0; i < 500; i++) { 2689 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2690 data &= PHY_STAT_MASK; 2691 if (desired) { 2692 if (data == desired) 2693 break; 2694 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2695 data == PHY_STAT_EXT_INIT) { 2696 break; 2697 } 2698 2699 msleep(20); 2700 } 2701 2702 return data; 2703 } 2704 2705 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2706 { 2707 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2708 2709 if (enable) { 2710 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2711 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2712 2713 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2714 ocp_data |= BIT(0); 2715 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2716 } else { 2717 u16 data; 2718 2719 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2720 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2721 2722 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2723 ocp_data &= ~BIT(0); 2724 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2725 2726 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2727 ocp_data &= ~PCUT_STATUS; 2728 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2729 2730 data = r8153_phy_status(tp, 0); 2731 2732 switch (data) { 2733 case PHY_STAT_PWRDN: 2734 case PHY_STAT_EXT_INIT: 2735 r8153b_green_en(tp, 2736 test_bit(GREEN_ETHERNET, &tp->flags)); 2737 2738 data = r8152_mdio_read(tp, MII_BMCR); 2739 data &= ~BMCR_PDOWN; 2740 data |= BMCR_RESET; 2741 r8152_mdio_write(tp, MII_BMCR, data); 2742 2743 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2744 2745 default: 2746 if (data != PHY_STAT_LAN_ON) 2747 netif_warn(tp, link, tp->netdev, 2748 "PHY not ready"); 2749 break; 2750 } 2751 } 2752 } 2753 2754 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2755 { 2756 u32 ocp_data; 2757 2758 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2759 if (enable) 2760 ocp_data |= PWR_EN | PHASE2_EN; 2761 else 2762 ocp_data &= ~(PWR_EN | PHASE2_EN); 2763 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2764 2765 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2766 ocp_data &= ~PCUT_STATUS; 2767 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2768 } 2769 2770 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2771 { 2772 u32 ocp_data; 2773 2774 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2775 if (enable) 2776 ocp_data |= PWR_EN | PHASE2_EN; 2777 else 2778 ocp_data &= ~PWR_EN; 2779 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2780 2781 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2782 ocp_data &= ~PCUT_STATUS; 2783 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2784 } 2785 2786 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2787 { 2788 u32 ocp_data; 2789 2790 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2791 if (enable) 2792 ocp_data |= BIT(0); 2793 else 2794 ocp_data &= ~BIT(0); 2795 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2796 2797 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2798 ocp_data &= ~BIT(0); 2799 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2800 } 2801 2802 static bool rtl_can_wakeup(struct r8152 *tp) 2803 { 2804 struct usb_device *udev = tp->udev; 2805 2806 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2807 } 2808 2809 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2810 { 2811 if (enable) { 2812 u32 ocp_data; 2813 2814 __rtl_set_wol(tp, WAKE_ANY); 2815 2816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2817 2818 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2819 ocp_data |= LINK_OFF_WAKE_EN; 2820 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2821 2822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2823 } else { 2824 u32 ocp_data; 2825 2826 __rtl_set_wol(tp, tp->saved_wolopts); 2827 2828 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2829 2830 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2831 ocp_data &= ~LINK_OFF_WAKE_EN; 2832 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2833 2834 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2835 } 2836 } 2837 2838 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2839 { 2840 if (enable) { 2841 r8153_u1u2en(tp, false); 2842 r8153_u2p3en(tp, false); 2843 r8153_mac_clk_spd(tp, true); 2844 rtl_runtime_suspend_enable(tp, true); 2845 } else { 2846 rtl_runtime_suspend_enable(tp, false); 2847 r8153_mac_clk_spd(tp, false); 2848 2849 switch (tp->version) { 2850 case RTL_VER_03: 2851 case RTL_VER_04: 2852 break; 2853 case RTL_VER_05: 2854 case RTL_VER_06: 2855 default: 2856 r8153_u2p3en(tp, true); 2857 break; 2858 } 2859 2860 r8153_u1u2en(tp, true); 2861 } 2862 } 2863 2864 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2865 { 2866 if (enable) { 2867 r8153b_queue_wake(tp, true); 2868 r8153b_u1u2en(tp, false); 2869 r8153_u2p3en(tp, false); 2870 rtl_runtime_suspend_enable(tp, true); 2871 r8153b_ups_en(tp, true); 2872 } else { 2873 r8153b_ups_en(tp, false); 2874 r8153b_queue_wake(tp, false); 2875 rtl_runtime_suspend_enable(tp, false); 2876 r8153_u2p3en(tp, true); 2877 r8153b_u1u2en(tp, true); 2878 } 2879 } 2880 2881 static void r8153_teredo_off(struct r8152 *tp) 2882 { 2883 u32 ocp_data; 2884 2885 switch (tp->version) { 2886 case RTL_VER_01: 2887 case RTL_VER_02: 2888 case RTL_VER_03: 2889 case RTL_VER_04: 2890 case RTL_VER_05: 2891 case RTL_VER_06: 2892 case RTL_VER_07: 2893 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2894 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2895 OOB_TEREDO_EN); 2896 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2897 break; 2898 2899 case RTL_VER_08: 2900 case RTL_VER_09: 2901 /* The bit 0 ~ 7 are relative with teredo settings. They are 2902 * W1C (write 1 to clear), so set all 1 to disable it. 2903 */ 2904 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2905 break; 2906 2907 default: 2908 break; 2909 } 2910 2911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2912 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2913 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2914 } 2915 2916 static void rtl_reset_bmu(struct r8152 *tp) 2917 { 2918 u32 ocp_data; 2919 2920 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2921 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2922 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2923 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2924 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2925 } 2926 2927 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2928 { 2929 if (enable) { 2930 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2931 LINKENA | DIS_SDSAVE); 2932 } else { 2933 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2934 DIS_SDSAVE); 2935 msleep(20); 2936 } 2937 } 2938 2939 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2940 { 2941 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2942 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2943 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2944 } 2945 2946 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2947 { 2948 u16 data; 2949 2950 r8152_mmd_indirect(tp, dev, reg); 2951 data = ocp_reg_read(tp, OCP_EEE_DATA); 2952 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2953 2954 return data; 2955 } 2956 2957 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2958 { 2959 r8152_mmd_indirect(tp, dev, reg); 2960 ocp_reg_write(tp, OCP_EEE_DATA, data); 2961 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2962 } 2963 2964 static void r8152_eee_en(struct r8152 *tp, bool enable) 2965 { 2966 u16 config1, config2, config3; 2967 u32 ocp_data; 2968 2969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2970 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2971 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2972 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2973 2974 if (enable) { 2975 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2976 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 2977 config1 |= sd_rise_time(1); 2978 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 2979 config3 |= fast_snr(42); 2980 } else { 2981 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2982 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 2983 RX_QUIET_EN); 2984 config1 |= sd_rise_time(7); 2985 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 2986 config3 |= fast_snr(511); 2987 } 2988 2989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2990 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 2991 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 2992 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 2993 } 2994 2995 static void r8152b_enable_eee(struct r8152 *tp) 2996 { 2997 r8152_eee_en(tp, true); 2998 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 2999 } 3000 3001 static void r8152b_enable_fc(struct r8152 *tp) 3002 { 3003 u16 anar; 3004 3005 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3006 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3007 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3008 } 3009 3010 static void rtl8152_disable(struct r8152 *tp) 3011 { 3012 r8152_aldps_en(tp, false); 3013 rtl_disable(tp); 3014 r8152_aldps_en(tp, true); 3015 } 3016 3017 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3018 { 3019 r8152b_enable_eee(tp); 3020 r8152_aldps_en(tp, true); 3021 r8152b_enable_fc(tp); 3022 3023 set_bit(PHY_RESET, &tp->flags); 3024 } 3025 3026 static void r8152b_exit_oob(struct r8152 *tp) 3027 { 3028 u32 ocp_data; 3029 int i; 3030 3031 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3032 ocp_data &= ~RCR_ACPT_ALL; 3033 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3034 3035 rxdy_gated_en(tp, true); 3036 r8153_teredo_off(tp); 3037 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3038 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3039 3040 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3041 ocp_data &= ~NOW_IS_OOB; 3042 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3043 3044 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3045 ocp_data &= ~MCU_BORW_EN; 3046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3047 3048 for (i = 0; i < 1000; i++) { 3049 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3050 if (ocp_data & LINK_LIST_READY) 3051 break; 3052 usleep_range(1000, 2000); 3053 } 3054 3055 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3056 ocp_data |= RE_INIT_LL; 3057 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3058 3059 for (i = 0; i < 1000; i++) { 3060 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3061 if (ocp_data & LINK_LIST_READY) 3062 break; 3063 usleep_range(1000, 2000); 3064 } 3065 3066 rtl8152_nic_reset(tp); 3067 3068 /* rx share fifo credit full threshold */ 3069 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3070 3071 if (tp->udev->speed == USB_SPEED_FULL || 3072 tp->udev->speed == USB_SPEED_LOW) { 3073 /* rx share fifo credit near full threshold */ 3074 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3075 RXFIFO_THR2_FULL); 3076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3077 RXFIFO_THR3_FULL); 3078 } else { 3079 /* rx share fifo credit near full threshold */ 3080 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3081 RXFIFO_THR2_HIGH); 3082 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3083 RXFIFO_THR3_HIGH); 3084 } 3085 3086 /* TX share fifo free credit full threshold */ 3087 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3088 3089 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3090 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3091 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3092 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3093 3094 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3095 3096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3097 3098 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3099 ocp_data |= TCR0_AUTO_FIFO; 3100 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3101 } 3102 3103 static void r8152b_enter_oob(struct r8152 *tp) 3104 { 3105 u32 ocp_data; 3106 int i; 3107 3108 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3109 ocp_data &= ~NOW_IS_OOB; 3110 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3111 3112 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3113 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3114 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3115 3116 rtl_disable(tp); 3117 3118 for (i = 0; i < 1000; i++) { 3119 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3120 if (ocp_data & LINK_LIST_READY) 3121 break; 3122 usleep_range(1000, 2000); 3123 } 3124 3125 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3126 ocp_data |= RE_INIT_LL; 3127 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3128 3129 for (i = 0; i < 1000; i++) { 3130 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3131 if (ocp_data & LINK_LIST_READY) 3132 break; 3133 usleep_range(1000, 2000); 3134 } 3135 3136 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3137 3138 rtl_rx_vlan_en(tp, true); 3139 3140 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3141 ocp_data |= ALDPS_PROXY_MODE; 3142 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3143 3144 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3145 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3146 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3147 3148 rxdy_gated_en(tp, false); 3149 3150 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3151 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3152 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3153 } 3154 3155 static int r8153_patch_request(struct r8152 *tp, bool request) 3156 { 3157 u16 data; 3158 int i; 3159 3160 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3161 if (request) 3162 data |= PATCH_REQUEST; 3163 else 3164 data &= ~PATCH_REQUEST; 3165 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3166 3167 for (i = 0; request && i < 5000; i++) { 3168 usleep_range(1000, 2000); 3169 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3170 break; 3171 } 3172 3173 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3174 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3175 r8153_patch_request(tp, false); 3176 return -ETIME; 3177 } else { 3178 return 0; 3179 } 3180 } 3181 3182 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3183 { 3184 u16 data; 3185 3186 data = ocp_reg_read(tp, OCP_POWER_CFG); 3187 if (enable) { 3188 data |= EN_ALDPS; 3189 ocp_reg_write(tp, OCP_POWER_CFG, data); 3190 } else { 3191 int i; 3192 3193 data &= ~EN_ALDPS; 3194 ocp_reg_write(tp, OCP_POWER_CFG, data); 3195 for (i = 0; i < 20; i++) { 3196 usleep_range(1000, 2000); 3197 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3198 break; 3199 } 3200 } 3201 } 3202 3203 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3204 { 3205 r8153_aldps_en(tp, enable); 3206 3207 if (enable) 3208 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3209 else 3210 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3211 } 3212 3213 static void r8153_eee_en(struct r8152 *tp, bool enable) 3214 { 3215 u32 ocp_data; 3216 u16 config; 3217 3218 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3219 config = ocp_reg_read(tp, OCP_EEE_CFG); 3220 3221 if (enable) { 3222 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3223 config |= EEE10_EN; 3224 } else { 3225 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3226 config &= ~EEE10_EN; 3227 } 3228 3229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3230 ocp_reg_write(tp, OCP_EEE_CFG, config); 3231 } 3232 3233 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3234 { 3235 r8153_eee_en(tp, enable); 3236 3237 if (enable) 3238 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3239 else 3240 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3241 } 3242 3243 static void r8153b_enable_fc(struct r8152 *tp) 3244 { 3245 r8152b_enable_fc(tp); 3246 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3247 } 3248 3249 static void r8153_hw_phy_cfg(struct r8152 *tp) 3250 { 3251 u32 ocp_data; 3252 u16 data; 3253 3254 /* disable ALDPS before updating the PHY parameters */ 3255 r8153_aldps_en(tp, false); 3256 3257 /* disable EEE before updating the PHY parameters */ 3258 r8153_eee_en(tp, false); 3259 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3260 3261 if (tp->version == RTL_VER_03) { 3262 data = ocp_reg_read(tp, OCP_EEE_CFG); 3263 data &= ~CTAP_SHORT_EN; 3264 ocp_reg_write(tp, OCP_EEE_CFG, data); 3265 } 3266 3267 data = ocp_reg_read(tp, OCP_POWER_CFG); 3268 data |= EEE_CLKDIV_EN; 3269 ocp_reg_write(tp, OCP_POWER_CFG, data); 3270 3271 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3272 data |= EN_10M_BGOFF; 3273 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3274 data = ocp_reg_read(tp, OCP_POWER_CFG); 3275 data |= EN_10M_PLLOFF; 3276 ocp_reg_write(tp, OCP_POWER_CFG, data); 3277 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3278 3279 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3280 ocp_data |= PFM_PWM_SWITCH; 3281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3282 3283 /* Enable LPF corner auto tune */ 3284 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3285 3286 /* Adjust 10M Amplitude */ 3287 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3288 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3289 3290 r8153_eee_en(tp, true); 3291 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3292 3293 r8153_aldps_en(tp, true); 3294 r8152b_enable_fc(tp); 3295 3296 switch (tp->version) { 3297 case RTL_VER_03: 3298 case RTL_VER_04: 3299 break; 3300 case RTL_VER_05: 3301 case RTL_VER_06: 3302 default: 3303 r8153_u2p3en(tp, true); 3304 break; 3305 } 3306 3307 set_bit(PHY_RESET, &tp->flags); 3308 } 3309 3310 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3311 { 3312 u32 ocp_data; 3313 3314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3315 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3316 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3317 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3318 3319 return ocp_data; 3320 } 3321 3322 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3323 { 3324 u32 ocp_data, ups_flags = 0; 3325 u16 data; 3326 3327 /* disable ALDPS before updating the PHY parameters */ 3328 r8153b_aldps_en(tp, false); 3329 3330 /* disable EEE before updating the PHY parameters */ 3331 r8153b_eee_en(tp, false); 3332 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3333 3334 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3335 3336 data = sram_read(tp, SRAM_GREEN_CFG); 3337 data |= R_TUNE_EN; 3338 sram_write(tp, SRAM_GREEN_CFG, data); 3339 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3340 data |= PGA_RETURN_EN; 3341 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3342 3343 /* ADC Bias Calibration: 3344 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3345 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3346 * ADC ioffset. 3347 */ 3348 ocp_data = r8152_efuse_read(tp, 0x7d); 3349 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3350 if (data != 0xffff) 3351 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3352 3353 /* ups mode tx-link-pulse timing adjustment: 3354 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3355 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3356 */ 3357 ocp_data = ocp_reg_read(tp, 0xc426); 3358 ocp_data &= 0x3fff; 3359 if (ocp_data) { 3360 u32 swr_cnt_1ms_ini; 3361 3362 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3363 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3364 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3365 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3366 } 3367 3368 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3369 ocp_data |= PFM_PWM_SWITCH; 3370 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3371 3372 /* Advnace EEE */ 3373 if (!r8153_patch_request(tp, true)) { 3374 data = ocp_reg_read(tp, OCP_POWER_CFG); 3375 data |= EEE_CLKDIV_EN; 3376 ocp_reg_write(tp, OCP_POWER_CFG, data); 3377 3378 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3379 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3380 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3381 3382 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3383 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3384 3385 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3386 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3387 UPS_FLAGS_EEE_PLLOFF_GIGA; 3388 3389 r8153_patch_request(tp, false); 3390 } 3391 3392 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3393 3394 r8153b_eee_en(tp, true); 3395 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3396 3397 r8153b_aldps_en(tp, true); 3398 r8153b_enable_fc(tp); 3399 r8153_u2p3en(tp, true); 3400 3401 set_bit(PHY_RESET, &tp->flags); 3402 } 3403 3404 static void r8153_first_init(struct r8152 *tp) 3405 { 3406 u32 ocp_data; 3407 int i; 3408 3409 r8153_mac_clk_spd(tp, false); 3410 rxdy_gated_en(tp, true); 3411 r8153_teredo_off(tp); 3412 3413 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3414 ocp_data &= ~RCR_ACPT_ALL; 3415 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3416 3417 rtl8152_nic_reset(tp); 3418 rtl_reset_bmu(tp); 3419 3420 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3421 ocp_data &= ~NOW_IS_OOB; 3422 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3423 3424 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3425 ocp_data &= ~MCU_BORW_EN; 3426 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3427 3428 for (i = 0; i < 1000; i++) { 3429 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3430 if (ocp_data & LINK_LIST_READY) 3431 break; 3432 usleep_range(1000, 2000); 3433 } 3434 3435 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3436 ocp_data |= RE_INIT_LL; 3437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3438 3439 for (i = 0; i < 1000; i++) { 3440 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3441 if (ocp_data & LINK_LIST_READY) 3442 break; 3443 usleep_range(1000, 2000); 3444 } 3445 3446 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3447 3448 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3449 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3450 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3451 3452 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3453 ocp_data |= TCR0_AUTO_FIFO; 3454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3455 3456 rtl8152_nic_reset(tp); 3457 3458 /* rx share fifo credit full threshold */ 3459 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3461 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3462 /* TX share fifo free credit full threshold */ 3463 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3464 } 3465 3466 static void r8153_enter_oob(struct r8152 *tp) 3467 { 3468 u32 ocp_data; 3469 int i; 3470 3471 r8153_mac_clk_spd(tp, true); 3472 3473 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3474 ocp_data &= ~NOW_IS_OOB; 3475 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3476 3477 rtl_disable(tp); 3478 rtl_reset_bmu(tp); 3479 3480 for (i = 0; i < 1000; i++) { 3481 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3482 if (ocp_data & LINK_LIST_READY) 3483 break; 3484 usleep_range(1000, 2000); 3485 } 3486 3487 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3488 ocp_data |= RE_INIT_LL; 3489 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3490 3491 for (i = 0; i < 1000; i++) { 3492 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3493 if (ocp_data & LINK_LIST_READY) 3494 break; 3495 usleep_range(1000, 2000); 3496 } 3497 3498 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3499 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3500 3501 switch (tp->version) { 3502 case RTL_VER_03: 3503 case RTL_VER_04: 3504 case RTL_VER_05: 3505 case RTL_VER_06: 3506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3507 ocp_data &= ~TEREDO_WAKE_MASK; 3508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3509 break; 3510 3511 case RTL_VER_08: 3512 case RTL_VER_09: 3513 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3514 * type. Set it to zero. bits[7:0] are the W1C bits about 3515 * the events. Set them to all 1 to clear them. 3516 */ 3517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3518 break; 3519 3520 default: 3521 break; 3522 } 3523 3524 rtl_rx_vlan_en(tp, true); 3525 3526 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3527 ocp_data |= ALDPS_PROXY_MODE; 3528 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3529 3530 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3531 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3533 3534 rxdy_gated_en(tp, false); 3535 3536 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3537 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3538 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3539 } 3540 3541 static void rtl8153_disable(struct r8152 *tp) 3542 { 3543 r8153_aldps_en(tp, false); 3544 rtl_disable(tp); 3545 rtl_reset_bmu(tp); 3546 r8153_aldps_en(tp, true); 3547 } 3548 3549 static void rtl8153b_disable(struct r8152 *tp) 3550 { 3551 r8153b_aldps_en(tp, false); 3552 rtl_disable(tp); 3553 rtl_reset_bmu(tp); 3554 r8153b_aldps_en(tp, true); 3555 } 3556 3557 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3558 { 3559 u16 bmcr, anar, gbcr; 3560 enum spd_duplex speed_duplex; 3561 int ret = 0; 3562 3563 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3564 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3565 ADVERTISE_100HALF | ADVERTISE_100FULL); 3566 if (tp->mii.supports_gmii) { 3567 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3568 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3569 } else { 3570 gbcr = 0; 3571 } 3572 3573 if (autoneg == AUTONEG_DISABLE) { 3574 if (speed == SPEED_10) { 3575 bmcr = 0; 3576 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3577 speed_duplex = FORCE_10M_HALF; 3578 } else if (speed == SPEED_100) { 3579 bmcr = BMCR_SPEED100; 3580 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3581 speed_duplex = FORCE_100M_HALF; 3582 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3583 bmcr = BMCR_SPEED1000; 3584 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3585 speed_duplex = NWAY_1000M_FULL; 3586 } else { 3587 ret = -EINVAL; 3588 goto out; 3589 } 3590 3591 if (duplex == DUPLEX_FULL) { 3592 bmcr |= BMCR_FULLDPLX; 3593 if (speed != SPEED_1000) 3594 speed_duplex++; 3595 } 3596 } else { 3597 if (speed == SPEED_10) { 3598 if (duplex == DUPLEX_FULL) { 3599 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3600 speed_duplex = NWAY_10M_FULL; 3601 } else { 3602 anar |= ADVERTISE_10HALF; 3603 speed_duplex = NWAY_10M_HALF; 3604 } 3605 } else if (speed == SPEED_100) { 3606 if (duplex == DUPLEX_FULL) { 3607 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3608 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3609 speed_duplex = NWAY_100M_FULL; 3610 } else { 3611 anar |= ADVERTISE_10HALF; 3612 anar |= ADVERTISE_100HALF; 3613 speed_duplex = NWAY_100M_HALF; 3614 } 3615 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3616 if (duplex == DUPLEX_FULL) { 3617 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3618 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3619 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3620 } else { 3621 anar |= ADVERTISE_10HALF; 3622 anar |= ADVERTISE_100HALF; 3623 gbcr |= ADVERTISE_1000HALF; 3624 } 3625 speed_duplex = NWAY_1000M_FULL; 3626 } else { 3627 ret = -EINVAL; 3628 goto out; 3629 } 3630 3631 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3632 } 3633 3634 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3635 bmcr |= BMCR_RESET; 3636 3637 if (tp->mii.supports_gmii) 3638 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3639 3640 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3641 r8152_mdio_write(tp, MII_BMCR, bmcr); 3642 3643 switch (tp->version) { 3644 case RTL_VER_08: 3645 case RTL_VER_09: 3646 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3647 UPS_FLAGS_SPEED_MASK); 3648 break; 3649 3650 default: 3651 break; 3652 } 3653 3654 if (bmcr & BMCR_RESET) { 3655 int i; 3656 3657 for (i = 0; i < 50; i++) { 3658 msleep(20); 3659 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3660 break; 3661 } 3662 } 3663 3664 out: 3665 return ret; 3666 } 3667 3668 static void rtl8152_up(struct r8152 *tp) 3669 { 3670 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3671 return; 3672 3673 r8152_aldps_en(tp, false); 3674 r8152b_exit_oob(tp); 3675 r8152_aldps_en(tp, true); 3676 } 3677 3678 static void rtl8152_down(struct r8152 *tp) 3679 { 3680 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3681 rtl_drop_queued_tx(tp); 3682 return; 3683 } 3684 3685 r8152_power_cut_en(tp, false); 3686 r8152_aldps_en(tp, false); 3687 r8152b_enter_oob(tp); 3688 r8152_aldps_en(tp, true); 3689 } 3690 3691 static void rtl8153_up(struct r8152 *tp) 3692 { 3693 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3694 return; 3695 3696 r8153_u1u2en(tp, false); 3697 r8153_u2p3en(tp, false); 3698 r8153_aldps_en(tp, false); 3699 r8153_first_init(tp); 3700 r8153_aldps_en(tp, true); 3701 3702 switch (tp->version) { 3703 case RTL_VER_03: 3704 case RTL_VER_04: 3705 break; 3706 case RTL_VER_05: 3707 case RTL_VER_06: 3708 default: 3709 r8153_u2p3en(tp, true); 3710 break; 3711 } 3712 3713 r8153_u1u2en(tp, true); 3714 } 3715 3716 static void rtl8153_down(struct r8152 *tp) 3717 { 3718 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3719 rtl_drop_queued_tx(tp); 3720 return; 3721 } 3722 3723 r8153_u1u2en(tp, false); 3724 r8153_u2p3en(tp, false); 3725 r8153_power_cut_en(tp, false); 3726 r8153_aldps_en(tp, false); 3727 r8153_enter_oob(tp); 3728 r8153_aldps_en(tp, true); 3729 } 3730 3731 static void rtl8153b_up(struct r8152 *tp) 3732 { 3733 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3734 return; 3735 3736 r8153b_u1u2en(tp, false); 3737 r8153_u2p3en(tp, false); 3738 r8153b_aldps_en(tp, false); 3739 3740 r8153_first_init(tp); 3741 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3742 3743 r8153b_aldps_en(tp, true); 3744 r8153_u2p3en(tp, true); 3745 r8153b_u1u2en(tp, true); 3746 } 3747 3748 static void rtl8153b_down(struct r8152 *tp) 3749 { 3750 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3751 rtl_drop_queued_tx(tp); 3752 return; 3753 } 3754 3755 r8153b_u1u2en(tp, false); 3756 r8153_u2p3en(tp, false); 3757 r8153b_power_cut_en(tp, false); 3758 r8153b_aldps_en(tp, false); 3759 r8153_enter_oob(tp); 3760 r8153b_aldps_en(tp, true); 3761 } 3762 3763 static bool rtl8152_in_nway(struct r8152 *tp) 3764 { 3765 u16 nway_state; 3766 3767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3768 tp->ocp_base = 0x2000; 3769 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3770 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3771 3772 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3773 if (nway_state & 0xc000) 3774 return false; 3775 else 3776 return true; 3777 } 3778 3779 static bool rtl8153_in_nway(struct r8152 *tp) 3780 { 3781 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3782 3783 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3784 return false; 3785 else 3786 return true; 3787 } 3788 3789 static void set_carrier(struct r8152 *tp) 3790 { 3791 struct net_device *netdev = tp->netdev; 3792 struct napi_struct *napi = &tp->napi; 3793 u8 speed; 3794 3795 speed = rtl8152_get_speed(tp); 3796 3797 if (speed & LINK_STATUS) { 3798 if (!netif_carrier_ok(netdev)) { 3799 tp->rtl_ops.enable(tp); 3800 netif_stop_queue(netdev); 3801 napi_disable(napi); 3802 netif_carrier_on(netdev); 3803 rtl_start_rx(tp); 3804 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 3805 _rtl8152_set_rx_mode(netdev); 3806 napi_enable(&tp->napi); 3807 netif_wake_queue(netdev); 3808 netif_info(tp, link, netdev, "carrier on\n"); 3809 } else if (netif_queue_stopped(netdev) && 3810 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3811 netif_wake_queue(netdev); 3812 } 3813 } else { 3814 if (netif_carrier_ok(netdev)) { 3815 netif_carrier_off(netdev); 3816 napi_disable(napi); 3817 tp->rtl_ops.disable(tp); 3818 napi_enable(napi); 3819 netif_info(tp, link, netdev, "carrier off\n"); 3820 } 3821 } 3822 } 3823 3824 static void rtl_work_func_t(struct work_struct *work) 3825 { 3826 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3827 3828 /* If the device is unplugged or !netif_running(), the workqueue 3829 * doesn't need to wake the device, and could return directly. 3830 */ 3831 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3832 return; 3833 3834 if (usb_autopm_get_interface(tp->intf) < 0) 3835 return; 3836 3837 if (!test_bit(WORK_ENABLE, &tp->flags)) 3838 goto out1; 3839 3840 if (!mutex_trylock(&tp->control)) { 3841 schedule_delayed_work(&tp->schedule, 0); 3842 goto out1; 3843 } 3844 3845 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3846 set_carrier(tp); 3847 3848 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3849 _rtl8152_set_rx_mode(tp->netdev); 3850 3851 /* don't schedule napi before linking */ 3852 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3853 netif_carrier_ok(tp->netdev)) 3854 napi_schedule(&tp->napi); 3855 3856 mutex_unlock(&tp->control); 3857 3858 out1: 3859 usb_autopm_put_interface(tp->intf); 3860 } 3861 3862 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3863 { 3864 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3865 3866 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3867 return; 3868 3869 if (usb_autopm_get_interface(tp->intf) < 0) 3870 return; 3871 3872 mutex_lock(&tp->control); 3873 3874 tp->rtl_ops.hw_phy_cfg(tp); 3875 3876 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3877 3878 mutex_unlock(&tp->control); 3879 3880 usb_autopm_put_interface(tp->intf); 3881 } 3882 3883 #ifdef CONFIG_PM_SLEEP 3884 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3885 void *data) 3886 { 3887 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3888 3889 switch (action) { 3890 case PM_HIBERNATION_PREPARE: 3891 case PM_SUSPEND_PREPARE: 3892 usb_autopm_get_interface(tp->intf); 3893 break; 3894 3895 case PM_POST_HIBERNATION: 3896 case PM_POST_SUSPEND: 3897 usb_autopm_put_interface(tp->intf); 3898 break; 3899 3900 case PM_POST_RESTORE: 3901 case PM_RESTORE_PREPARE: 3902 default: 3903 break; 3904 } 3905 3906 return NOTIFY_DONE; 3907 } 3908 #endif 3909 3910 static int rtl8152_open(struct net_device *netdev) 3911 { 3912 struct r8152 *tp = netdev_priv(netdev); 3913 int res = 0; 3914 3915 res = alloc_all_mem(tp); 3916 if (res) 3917 goto out; 3918 3919 res = usb_autopm_get_interface(tp->intf); 3920 if (res < 0) 3921 goto out_free; 3922 3923 mutex_lock(&tp->control); 3924 3925 tp->rtl_ops.up(tp); 3926 3927 netif_carrier_off(netdev); 3928 netif_start_queue(netdev); 3929 set_bit(WORK_ENABLE, &tp->flags); 3930 3931 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3932 if (res) { 3933 if (res == -ENODEV) 3934 netif_device_detach(tp->netdev); 3935 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3936 res); 3937 goto out_unlock; 3938 } 3939 napi_enable(&tp->napi); 3940 3941 mutex_unlock(&tp->control); 3942 3943 usb_autopm_put_interface(tp->intf); 3944 #ifdef CONFIG_PM_SLEEP 3945 tp->pm_notifier.notifier_call = rtl_notifier; 3946 register_pm_notifier(&tp->pm_notifier); 3947 #endif 3948 return 0; 3949 3950 out_unlock: 3951 mutex_unlock(&tp->control); 3952 usb_autopm_put_interface(tp->intf); 3953 out_free: 3954 free_all_mem(tp); 3955 out: 3956 return res; 3957 } 3958 3959 static int rtl8152_close(struct net_device *netdev) 3960 { 3961 struct r8152 *tp = netdev_priv(netdev); 3962 int res = 0; 3963 3964 #ifdef CONFIG_PM_SLEEP 3965 unregister_pm_notifier(&tp->pm_notifier); 3966 #endif 3967 napi_disable(&tp->napi); 3968 clear_bit(WORK_ENABLE, &tp->flags); 3969 usb_kill_urb(tp->intr_urb); 3970 cancel_delayed_work_sync(&tp->schedule); 3971 netif_stop_queue(netdev); 3972 3973 res = usb_autopm_get_interface(tp->intf); 3974 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3975 rtl_drop_queued_tx(tp); 3976 rtl_stop_rx(tp); 3977 } else { 3978 mutex_lock(&tp->control); 3979 3980 tp->rtl_ops.down(tp); 3981 3982 mutex_unlock(&tp->control); 3983 3984 usb_autopm_put_interface(tp->intf); 3985 } 3986 3987 free_all_mem(tp); 3988 3989 return res; 3990 } 3991 3992 static void rtl_tally_reset(struct r8152 *tp) 3993 { 3994 u32 ocp_data; 3995 3996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3997 ocp_data |= TALLY_RESET; 3998 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3999 } 4000 4001 static void r8152b_init(struct r8152 *tp) 4002 { 4003 u32 ocp_data; 4004 u16 data; 4005 4006 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4007 return; 4008 4009 data = r8152_mdio_read(tp, MII_BMCR); 4010 if (data & BMCR_PDOWN) { 4011 data &= ~BMCR_PDOWN; 4012 r8152_mdio_write(tp, MII_BMCR, data); 4013 } 4014 4015 r8152_aldps_en(tp, false); 4016 4017 if (tp->version == RTL_VER_01) { 4018 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4019 ocp_data &= ~LED_MODE_MASK; 4020 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4021 } 4022 4023 r8152_power_cut_en(tp, false); 4024 4025 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4026 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4028 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4029 ocp_data &= ~MCU_CLK_RATIO_MASK; 4030 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4031 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4032 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4033 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4035 4036 rtl_tally_reset(tp); 4037 4038 /* enable rx aggregation */ 4039 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4040 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4041 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4042 } 4043 4044 static void r8153_init(struct r8152 *tp) 4045 { 4046 u32 ocp_data; 4047 u16 data; 4048 int i; 4049 4050 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4051 return; 4052 4053 r8153_u1u2en(tp, false); 4054 4055 for (i = 0; i < 500; i++) { 4056 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4057 AUTOLOAD_DONE) 4058 break; 4059 msleep(20); 4060 } 4061 4062 data = r8153_phy_status(tp, 0); 4063 4064 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4065 tp->version == RTL_VER_05) 4066 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4067 4068 data = r8152_mdio_read(tp, MII_BMCR); 4069 if (data & BMCR_PDOWN) { 4070 data &= ~BMCR_PDOWN; 4071 r8152_mdio_write(tp, MII_BMCR, data); 4072 } 4073 4074 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4075 4076 r8153_u2p3en(tp, false); 4077 4078 if (tp->version == RTL_VER_04) { 4079 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4080 ocp_data &= ~pwd_dn_scale_mask; 4081 ocp_data |= pwd_dn_scale(96); 4082 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4083 4084 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4085 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4086 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4087 } else if (tp->version == RTL_VER_05) { 4088 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4089 ocp_data &= ~ECM_ALDPS; 4090 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4091 4092 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4093 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4094 ocp_data &= ~DYNAMIC_BURST; 4095 else 4096 ocp_data |= DYNAMIC_BURST; 4097 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4098 } else if (tp->version == RTL_VER_06) { 4099 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4100 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4101 ocp_data &= ~DYNAMIC_BURST; 4102 else 4103 ocp_data |= DYNAMIC_BURST; 4104 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4105 } 4106 4107 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4108 ocp_data |= EP4_FULL_FC; 4109 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4110 4111 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4112 ocp_data &= ~TIMER11_EN; 4113 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4114 4115 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4116 ocp_data &= ~LED_MODE_MASK; 4117 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4118 4119 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4120 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4121 ocp_data |= LPM_TIMER_500MS; 4122 else 4123 ocp_data |= LPM_TIMER_500US; 4124 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4125 4126 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4127 ocp_data &= ~SEN_VAL_MASK; 4128 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4129 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4130 4131 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4132 4133 r8153_power_cut_en(tp, false); 4134 r8153_u1u2en(tp, true); 4135 r8153_mac_clk_spd(tp, false); 4136 usb_enable_lpm(tp->udev); 4137 4138 /* rx aggregation */ 4139 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4140 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4141 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4142 ocp_data |= RX_AGG_DISABLE; 4143 4144 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4145 4146 rtl_tally_reset(tp); 4147 4148 switch (tp->udev->speed) { 4149 case USB_SPEED_SUPER: 4150 case USB_SPEED_SUPER_PLUS: 4151 tp->coalesce = COALESCE_SUPER; 4152 break; 4153 case USB_SPEED_HIGH: 4154 tp->coalesce = COALESCE_HIGH; 4155 break; 4156 default: 4157 tp->coalesce = COALESCE_SLOW; 4158 break; 4159 } 4160 } 4161 4162 static void r8153b_init(struct r8152 *tp) 4163 { 4164 u32 ocp_data; 4165 u16 data; 4166 int i; 4167 4168 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4169 return; 4170 4171 r8153b_u1u2en(tp, false); 4172 4173 for (i = 0; i < 500; i++) { 4174 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4175 AUTOLOAD_DONE) 4176 break; 4177 msleep(20); 4178 } 4179 4180 data = r8153_phy_status(tp, 0); 4181 4182 data = r8152_mdio_read(tp, MII_BMCR); 4183 if (data & BMCR_PDOWN) { 4184 data &= ~BMCR_PDOWN; 4185 r8152_mdio_write(tp, MII_BMCR, data); 4186 } 4187 4188 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4189 4190 r8153_u2p3en(tp, false); 4191 4192 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4193 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4194 4195 /* U1/U2/L1 idle timer. 500 us */ 4196 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4197 4198 r8153b_power_cut_en(tp, false); 4199 r8153b_ups_en(tp, false); 4200 r8153b_queue_wake(tp, false); 4201 rtl_runtime_suspend_enable(tp, false); 4202 r8153b_u1u2en(tp, true); 4203 usb_enable_lpm(tp->udev); 4204 4205 /* MAC clock speed down */ 4206 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4207 ocp_data |= MAC_CLK_SPDWN_EN; 4208 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4209 4210 set_bit(GREEN_ETHERNET, &tp->flags); 4211 4212 /* rx aggregation */ 4213 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4214 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4215 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4216 4217 rtl_tally_reset(tp); 4218 4219 tp->coalesce = 15000; /* 15 us */ 4220 } 4221 4222 static int rtl8152_pre_reset(struct usb_interface *intf) 4223 { 4224 struct r8152 *tp = usb_get_intfdata(intf); 4225 struct net_device *netdev; 4226 4227 if (!tp) 4228 return 0; 4229 4230 netdev = tp->netdev; 4231 if (!netif_running(netdev)) 4232 return 0; 4233 4234 netif_stop_queue(netdev); 4235 napi_disable(&tp->napi); 4236 clear_bit(WORK_ENABLE, &tp->flags); 4237 usb_kill_urb(tp->intr_urb); 4238 cancel_delayed_work_sync(&tp->schedule); 4239 if (netif_carrier_ok(netdev)) { 4240 mutex_lock(&tp->control); 4241 tp->rtl_ops.disable(tp); 4242 mutex_unlock(&tp->control); 4243 } 4244 4245 return 0; 4246 } 4247 4248 static int rtl8152_post_reset(struct usb_interface *intf) 4249 { 4250 struct r8152 *tp = usb_get_intfdata(intf); 4251 struct net_device *netdev; 4252 4253 if (!tp) 4254 return 0; 4255 4256 netdev = tp->netdev; 4257 if (!netif_running(netdev)) 4258 return 0; 4259 4260 set_bit(WORK_ENABLE, &tp->flags); 4261 if (netif_carrier_ok(netdev)) { 4262 mutex_lock(&tp->control); 4263 tp->rtl_ops.enable(tp); 4264 rtl_start_rx(tp); 4265 _rtl8152_set_rx_mode(netdev); 4266 mutex_unlock(&tp->control); 4267 } 4268 4269 napi_enable(&tp->napi); 4270 netif_wake_queue(netdev); 4271 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4272 4273 if (!list_empty(&tp->rx_done)) 4274 napi_schedule(&tp->napi); 4275 4276 return 0; 4277 } 4278 4279 static bool delay_autosuspend(struct r8152 *tp) 4280 { 4281 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4282 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4283 4284 /* This means a linking change occurs and the driver doesn't detect it, 4285 * yet. If the driver has disabled tx/rx and hw is linking on, the 4286 * device wouldn't wake up by receiving any packet. 4287 */ 4288 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4289 return true; 4290 4291 /* If the linking down is occurred by nway, the device may miss the 4292 * linking change event. And it wouldn't wake when linking on. 4293 */ 4294 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4295 return true; 4296 else if (!skb_queue_empty(&tp->tx_queue)) 4297 return true; 4298 else 4299 return false; 4300 } 4301 4302 static int rtl8152_runtime_resume(struct r8152 *tp) 4303 { 4304 struct net_device *netdev = tp->netdev; 4305 4306 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4307 struct napi_struct *napi = &tp->napi; 4308 4309 tp->rtl_ops.autosuspend_en(tp, false); 4310 napi_disable(napi); 4311 set_bit(WORK_ENABLE, &tp->flags); 4312 4313 if (netif_carrier_ok(netdev)) { 4314 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4315 rtl_start_rx(tp); 4316 } else { 4317 netif_carrier_off(netdev); 4318 tp->rtl_ops.disable(tp); 4319 netif_info(tp, link, netdev, "linking down\n"); 4320 } 4321 } 4322 4323 napi_enable(napi); 4324 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4325 smp_mb__after_atomic(); 4326 4327 if (!list_empty(&tp->rx_done)) 4328 napi_schedule(&tp->napi); 4329 4330 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4331 } else { 4332 if (netdev->flags & IFF_UP) 4333 tp->rtl_ops.autosuspend_en(tp, false); 4334 4335 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4336 } 4337 4338 return 0; 4339 } 4340 4341 static int rtl8152_system_resume(struct r8152 *tp) 4342 { 4343 struct net_device *netdev = tp->netdev; 4344 4345 netif_device_attach(netdev); 4346 4347 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4348 tp->rtl_ops.up(tp); 4349 netif_carrier_off(netdev); 4350 set_bit(WORK_ENABLE, &tp->flags); 4351 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4352 } 4353 4354 return 0; 4355 } 4356 4357 static int rtl8152_runtime_suspend(struct r8152 *tp) 4358 { 4359 struct net_device *netdev = tp->netdev; 4360 int ret = 0; 4361 4362 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4363 smp_mb__after_atomic(); 4364 4365 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4366 u32 rcr = 0; 4367 4368 if (netif_carrier_ok(netdev)) { 4369 u32 ocp_data; 4370 4371 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4372 ocp_data = rcr & ~RCR_ACPT_ALL; 4373 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4374 rxdy_gated_en(tp, true); 4375 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4376 PLA_OOB_CTRL); 4377 if (!(ocp_data & RXFIFO_EMPTY)) { 4378 rxdy_gated_en(tp, false); 4379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4380 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4381 smp_mb__after_atomic(); 4382 ret = -EBUSY; 4383 goto out1; 4384 } 4385 } 4386 4387 clear_bit(WORK_ENABLE, &tp->flags); 4388 usb_kill_urb(tp->intr_urb); 4389 4390 tp->rtl_ops.autosuspend_en(tp, true); 4391 4392 if (netif_carrier_ok(netdev)) { 4393 struct napi_struct *napi = &tp->napi; 4394 4395 napi_disable(napi); 4396 rtl_stop_rx(tp); 4397 rxdy_gated_en(tp, false); 4398 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4399 napi_enable(napi); 4400 } 4401 4402 if (delay_autosuspend(tp)) { 4403 rtl8152_runtime_resume(tp); 4404 ret = -EBUSY; 4405 } 4406 } 4407 4408 out1: 4409 return ret; 4410 } 4411 4412 static int rtl8152_system_suspend(struct r8152 *tp) 4413 { 4414 struct net_device *netdev = tp->netdev; 4415 int ret = 0; 4416 4417 netif_device_detach(netdev); 4418 4419 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4420 struct napi_struct *napi = &tp->napi; 4421 4422 clear_bit(WORK_ENABLE, &tp->flags); 4423 usb_kill_urb(tp->intr_urb); 4424 napi_disable(napi); 4425 cancel_delayed_work_sync(&tp->schedule); 4426 tp->rtl_ops.down(tp); 4427 napi_enable(napi); 4428 } 4429 4430 return ret; 4431 } 4432 4433 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4434 { 4435 struct r8152 *tp = usb_get_intfdata(intf); 4436 int ret; 4437 4438 mutex_lock(&tp->control); 4439 4440 if (PMSG_IS_AUTO(message)) 4441 ret = rtl8152_runtime_suspend(tp); 4442 else 4443 ret = rtl8152_system_suspend(tp); 4444 4445 mutex_unlock(&tp->control); 4446 4447 return ret; 4448 } 4449 4450 static int rtl8152_resume(struct usb_interface *intf) 4451 { 4452 struct r8152 *tp = usb_get_intfdata(intf); 4453 int ret; 4454 4455 mutex_lock(&tp->control); 4456 4457 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4458 ret = rtl8152_runtime_resume(tp); 4459 else 4460 ret = rtl8152_system_resume(tp); 4461 4462 mutex_unlock(&tp->control); 4463 4464 return ret; 4465 } 4466 4467 static int rtl8152_reset_resume(struct usb_interface *intf) 4468 { 4469 struct r8152 *tp = usb_get_intfdata(intf); 4470 4471 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4472 mutex_lock(&tp->control); 4473 tp->rtl_ops.init(tp); 4474 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4475 mutex_unlock(&tp->control); 4476 return rtl8152_resume(intf); 4477 } 4478 4479 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4480 { 4481 struct r8152 *tp = netdev_priv(dev); 4482 4483 if (usb_autopm_get_interface(tp->intf) < 0) 4484 return; 4485 4486 if (!rtl_can_wakeup(tp)) { 4487 wol->supported = 0; 4488 wol->wolopts = 0; 4489 } else { 4490 mutex_lock(&tp->control); 4491 wol->supported = WAKE_ANY; 4492 wol->wolopts = __rtl_get_wol(tp); 4493 mutex_unlock(&tp->control); 4494 } 4495 4496 usb_autopm_put_interface(tp->intf); 4497 } 4498 4499 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4500 { 4501 struct r8152 *tp = netdev_priv(dev); 4502 int ret; 4503 4504 if (!rtl_can_wakeup(tp)) 4505 return -EOPNOTSUPP; 4506 4507 ret = usb_autopm_get_interface(tp->intf); 4508 if (ret < 0) 4509 goto out_set_wol; 4510 4511 mutex_lock(&tp->control); 4512 4513 __rtl_set_wol(tp, wol->wolopts); 4514 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4515 4516 mutex_unlock(&tp->control); 4517 4518 usb_autopm_put_interface(tp->intf); 4519 4520 out_set_wol: 4521 return ret; 4522 } 4523 4524 static u32 rtl8152_get_msglevel(struct net_device *dev) 4525 { 4526 struct r8152 *tp = netdev_priv(dev); 4527 4528 return tp->msg_enable; 4529 } 4530 4531 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4532 { 4533 struct r8152 *tp = netdev_priv(dev); 4534 4535 tp->msg_enable = value; 4536 } 4537 4538 static void rtl8152_get_drvinfo(struct net_device *netdev, 4539 struct ethtool_drvinfo *info) 4540 { 4541 struct r8152 *tp = netdev_priv(netdev); 4542 4543 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4544 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4545 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4546 } 4547 4548 static 4549 int rtl8152_get_link_ksettings(struct net_device *netdev, 4550 struct ethtool_link_ksettings *cmd) 4551 { 4552 struct r8152 *tp = netdev_priv(netdev); 4553 int ret; 4554 4555 if (!tp->mii.mdio_read) 4556 return -EOPNOTSUPP; 4557 4558 ret = usb_autopm_get_interface(tp->intf); 4559 if (ret < 0) 4560 goto out; 4561 4562 mutex_lock(&tp->control); 4563 4564 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4565 4566 mutex_unlock(&tp->control); 4567 4568 usb_autopm_put_interface(tp->intf); 4569 4570 out: 4571 return ret; 4572 } 4573 4574 static int rtl8152_set_link_ksettings(struct net_device *dev, 4575 const struct ethtool_link_ksettings *cmd) 4576 { 4577 struct r8152 *tp = netdev_priv(dev); 4578 int ret; 4579 4580 ret = usb_autopm_get_interface(tp->intf); 4581 if (ret < 0) 4582 goto out; 4583 4584 mutex_lock(&tp->control); 4585 4586 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4587 cmd->base.duplex); 4588 if (!ret) { 4589 tp->autoneg = cmd->base.autoneg; 4590 tp->speed = cmd->base.speed; 4591 tp->duplex = cmd->base.duplex; 4592 } 4593 4594 mutex_unlock(&tp->control); 4595 4596 usb_autopm_put_interface(tp->intf); 4597 4598 out: 4599 return ret; 4600 } 4601 4602 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4603 "tx_packets", 4604 "rx_packets", 4605 "tx_errors", 4606 "rx_errors", 4607 "rx_missed", 4608 "align_errors", 4609 "tx_single_collisions", 4610 "tx_multi_collisions", 4611 "rx_unicast", 4612 "rx_broadcast", 4613 "rx_multicast", 4614 "tx_aborted", 4615 "tx_underrun", 4616 }; 4617 4618 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4619 { 4620 switch (sset) { 4621 case ETH_SS_STATS: 4622 return ARRAY_SIZE(rtl8152_gstrings); 4623 default: 4624 return -EOPNOTSUPP; 4625 } 4626 } 4627 4628 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4629 struct ethtool_stats *stats, u64 *data) 4630 { 4631 struct r8152 *tp = netdev_priv(dev); 4632 struct tally_counter tally; 4633 4634 if (usb_autopm_get_interface(tp->intf) < 0) 4635 return; 4636 4637 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4638 4639 usb_autopm_put_interface(tp->intf); 4640 4641 data[0] = le64_to_cpu(tally.tx_packets); 4642 data[1] = le64_to_cpu(tally.rx_packets); 4643 data[2] = le64_to_cpu(tally.tx_errors); 4644 data[3] = le32_to_cpu(tally.rx_errors); 4645 data[4] = le16_to_cpu(tally.rx_missed); 4646 data[5] = le16_to_cpu(tally.align_errors); 4647 data[6] = le32_to_cpu(tally.tx_one_collision); 4648 data[7] = le32_to_cpu(tally.tx_multi_collision); 4649 data[8] = le64_to_cpu(tally.rx_unicast); 4650 data[9] = le64_to_cpu(tally.rx_broadcast); 4651 data[10] = le32_to_cpu(tally.rx_multicast); 4652 data[11] = le16_to_cpu(tally.tx_aborted); 4653 data[12] = le16_to_cpu(tally.tx_underrun); 4654 } 4655 4656 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4657 { 4658 switch (stringset) { 4659 case ETH_SS_STATS: 4660 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4661 break; 4662 } 4663 } 4664 4665 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4666 { 4667 u32 ocp_data, lp, adv, supported = 0; 4668 u16 val; 4669 4670 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4671 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4672 4673 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4674 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4675 4676 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4677 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4678 4679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4680 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4681 4682 eee->eee_enabled = !!ocp_data; 4683 eee->eee_active = !!(supported & adv & lp); 4684 eee->supported = supported; 4685 eee->advertised = adv; 4686 eee->lp_advertised = lp; 4687 4688 return 0; 4689 } 4690 4691 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4692 { 4693 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4694 4695 r8152_eee_en(tp, eee->eee_enabled); 4696 4697 if (!eee->eee_enabled) 4698 val = 0; 4699 4700 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4701 4702 return 0; 4703 } 4704 4705 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4706 { 4707 u32 ocp_data, lp, adv, supported = 0; 4708 u16 val; 4709 4710 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4711 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4712 4713 val = ocp_reg_read(tp, OCP_EEE_ADV); 4714 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4715 4716 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4717 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4718 4719 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4720 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4721 4722 eee->eee_enabled = !!ocp_data; 4723 eee->eee_active = !!(supported & adv & lp); 4724 eee->supported = supported; 4725 eee->advertised = adv; 4726 eee->lp_advertised = lp; 4727 4728 return 0; 4729 } 4730 4731 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4732 { 4733 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4734 4735 r8153_eee_en(tp, eee->eee_enabled); 4736 4737 if (!eee->eee_enabled) 4738 val = 0; 4739 4740 ocp_reg_write(tp, OCP_EEE_ADV, val); 4741 4742 return 0; 4743 } 4744 4745 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4746 { 4747 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4748 4749 r8153b_eee_en(tp, eee->eee_enabled); 4750 4751 if (!eee->eee_enabled) 4752 val = 0; 4753 4754 ocp_reg_write(tp, OCP_EEE_ADV, val); 4755 4756 return 0; 4757 } 4758 4759 static int 4760 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4761 { 4762 struct r8152 *tp = netdev_priv(net); 4763 int ret; 4764 4765 ret = usb_autopm_get_interface(tp->intf); 4766 if (ret < 0) 4767 goto out; 4768 4769 mutex_lock(&tp->control); 4770 4771 ret = tp->rtl_ops.eee_get(tp, edata); 4772 4773 mutex_unlock(&tp->control); 4774 4775 usb_autopm_put_interface(tp->intf); 4776 4777 out: 4778 return ret; 4779 } 4780 4781 static int 4782 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4783 { 4784 struct r8152 *tp = netdev_priv(net); 4785 int ret; 4786 4787 ret = usb_autopm_get_interface(tp->intf); 4788 if (ret < 0) 4789 goto out; 4790 4791 mutex_lock(&tp->control); 4792 4793 ret = tp->rtl_ops.eee_set(tp, edata); 4794 if (!ret) 4795 ret = mii_nway_restart(&tp->mii); 4796 4797 mutex_unlock(&tp->control); 4798 4799 usb_autopm_put_interface(tp->intf); 4800 4801 out: 4802 return ret; 4803 } 4804 4805 static int rtl8152_nway_reset(struct net_device *dev) 4806 { 4807 struct r8152 *tp = netdev_priv(dev); 4808 int ret; 4809 4810 ret = usb_autopm_get_interface(tp->intf); 4811 if (ret < 0) 4812 goto out; 4813 4814 mutex_lock(&tp->control); 4815 4816 ret = mii_nway_restart(&tp->mii); 4817 4818 mutex_unlock(&tp->control); 4819 4820 usb_autopm_put_interface(tp->intf); 4821 4822 out: 4823 return ret; 4824 } 4825 4826 static int rtl8152_get_coalesce(struct net_device *netdev, 4827 struct ethtool_coalesce *coalesce) 4828 { 4829 struct r8152 *tp = netdev_priv(netdev); 4830 4831 switch (tp->version) { 4832 case RTL_VER_01: 4833 case RTL_VER_02: 4834 case RTL_VER_07: 4835 return -EOPNOTSUPP; 4836 default: 4837 break; 4838 } 4839 4840 coalesce->rx_coalesce_usecs = tp->coalesce; 4841 4842 return 0; 4843 } 4844 4845 static int rtl8152_set_coalesce(struct net_device *netdev, 4846 struct ethtool_coalesce *coalesce) 4847 { 4848 struct r8152 *tp = netdev_priv(netdev); 4849 int ret; 4850 4851 switch (tp->version) { 4852 case RTL_VER_01: 4853 case RTL_VER_02: 4854 case RTL_VER_07: 4855 return -EOPNOTSUPP; 4856 default: 4857 break; 4858 } 4859 4860 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4861 return -EINVAL; 4862 4863 ret = usb_autopm_get_interface(tp->intf); 4864 if (ret < 0) 4865 return ret; 4866 4867 mutex_lock(&tp->control); 4868 4869 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4870 tp->coalesce = coalesce->rx_coalesce_usecs; 4871 4872 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4873 r8153_set_rx_early_timeout(tp); 4874 } 4875 4876 mutex_unlock(&tp->control); 4877 4878 usb_autopm_put_interface(tp->intf); 4879 4880 return ret; 4881 } 4882 4883 static const struct ethtool_ops ops = { 4884 .get_drvinfo = rtl8152_get_drvinfo, 4885 .get_link = ethtool_op_get_link, 4886 .nway_reset = rtl8152_nway_reset, 4887 .get_msglevel = rtl8152_get_msglevel, 4888 .set_msglevel = rtl8152_set_msglevel, 4889 .get_wol = rtl8152_get_wol, 4890 .set_wol = rtl8152_set_wol, 4891 .get_strings = rtl8152_get_strings, 4892 .get_sset_count = rtl8152_get_sset_count, 4893 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4894 .get_coalesce = rtl8152_get_coalesce, 4895 .set_coalesce = rtl8152_set_coalesce, 4896 .get_eee = rtl_ethtool_get_eee, 4897 .set_eee = rtl_ethtool_set_eee, 4898 .get_link_ksettings = rtl8152_get_link_ksettings, 4899 .set_link_ksettings = rtl8152_set_link_ksettings, 4900 }; 4901 4902 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4903 { 4904 struct r8152 *tp = netdev_priv(netdev); 4905 struct mii_ioctl_data *data = if_mii(rq); 4906 int res; 4907 4908 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4909 return -ENODEV; 4910 4911 res = usb_autopm_get_interface(tp->intf); 4912 if (res < 0) 4913 goto out; 4914 4915 switch (cmd) { 4916 case SIOCGMIIPHY: 4917 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4918 break; 4919 4920 case SIOCGMIIREG: 4921 mutex_lock(&tp->control); 4922 data->val_out = r8152_mdio_read(tp, data->reg_num); 4923 mutex_unlock(&tp->control); 4924 break; 4925 4926 case SIOCSMIIREG: 4927 if (!capable(CAP_NET_ADMIN)) { 4928 res = -EPERM; 4929 break; 4930 } 4931 mutex_lock(&tp->control); 4932 r8152_mdio_write(tp, data->reg_num, data->val_in); 4933 mutex_unlock(&tp->control); 4934 break; 4935 4936 default: 4937 res = -EOPNOTSUPP; 4938 } 4939 4940 usb_autopm_put_interface(tp->intf); 4941 4942 out: 4943 return res; 4944 } 4945 4946 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4947 { 4948 struct r8152 *tp = netdev_priv(dev); 4949 int ret; 4950 4951 switch (tp->version) { 4952 case RTL_VER_01: 4953 case RTL_VER_02: 4954 case RTL_VER_07: 4955 dev->mtu = new_mtu; 4956 return 0; 4957 default: 4958 break; 4959 } 4960 4961 ret = usb_autopm_get_interface(tp->intf); 4962 if (ret < 0) 4963 return ret; 4964 4965 mutex_lock(&tp->control); 4966 4967 dev->mtu = new_mtu; 4968 4969 if (netif_running(dev)) { 4970 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4971 4972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 4973 4974 if (netif_carrier_ok(dev)) 4975 r8153_set_rx_early_size(tp); 4976 } 4977 4978 mutex_unlock(&tp->control); 4979 4980 usb_autopm_put_interface(tp->intf); 4981 4982 return ret; 4983 } 4984 4985 static const struct net_device_ops rtl8152_netdev_ops = { 4986 .ndo_open = rtl8152_open, 4987 .ndo_stop = rtl8152_close, 4988 .ndo_do_ioctl = rtl8152_ioctl, 4989 .ndo_start_xmit = rtl8152_start_xmit, 4990 .ndo_tx_timeout = rtl8152_tx_timeout, 4991 .ndo_set_features = rtl8152_set_features, 4992 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4993 .ndo_set_mac_address = rtl8152_set_mac_address, 4994 .ndo_change_mtu = rtl8152_change_mtu, 4995 .ndo_validate_addr = eth_validate_addr, 4996 .ndo_features_check = rtl8152_features_check, 4997 }; 4998 4999 static void rtl8152_unload(struct r8152 *tp) 5000 { 5001 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5002 return; 5003 5004 if (tp->version != RTL_VER_01) 5005 r8152_power_cut_en(tp, true); 5006 } 5007 5008 static void rtl8153_unload(struct r8152 *tp) 5009 { 5010 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5011 return; 5012 5013 r8153_power_cut_en(tp, false); 5014 } 5015 5016 static void rtl8153b_unload(struct r8152 *tp) 5017 { 5018 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5019 return; 5020 5021 r8153b_power_cut_en(tp, false); 5022 } 5023 5024 static int rtl_ops_init(struct r8152 *tp) 5025 { 5026 struct rtl_ops *ops = &tp->rtl_ops; 5027 int ret = 0; 5028 5029 switch (tp->version) { 5030 case RTL_VER_01: 5031 case RTL_VER_02: 5032 case RTL_VER_07: 5033 ops->init = r8152b_init; 5034 ops->enable = rtl8152_enable; 5035 ops->disable = rtl8152_disable; 5036 ops->up = rtl8152_up; 5037 ops->down = rtl8152_down; 5038 ops->unload = rtl8152_unload; 5039 ops->eee_get = r8152_get_eee; 5040 ops->eee_set = r8152_set_eee; 5041 ops->in_nway = rtl8152_in_nway; 5042 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5043 ops->autosuspend_en = rtl_runtime_suspend_enable; 5044 break; 5045 5046 case RTL_VER_03: 5047 case RTL_VER_04: 5048 case RTL_VER_05: 5049 case RTL_VER_06: 5050 ops->init = r8153_init; 5051 ops->enable = rtl8153_enable; 5052 ops->disable = rtl8153_disable; 5053 ops->up = rtl8153_up; 5054 ops->down = rtl8153_down; 5055 ops->unload = rtl8153_unload; 5056 ops->eee_get = r8153_get_eee; 5057 ops->eee_set = r8153_set_eee; 5058 ops->in_nway = rtl8153_in_nway; 5059 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5060 ops->autosuspend_en = rtl8153_runtime_enable; 5061 break; 5062 5063 case RTL_VER_08: 5064 case RTL_VER_09: 5065 ops->init = r8153b_init; 5066 ops->enable = rtl8153_enable; 5067 ops->disable = rtl8153b_disable; 5068 ops->up = rtl8153b_up; 5069 ops->down = rtl8153b_down; 5070 ops->unload = rtl8153b_unload; 5071 ops->eee_get = r8153_get_eee; 5072 ops->eee_set = r8153b_set_eee; 5073 ops->in_nway = rtl8153_in_nway; 5074 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5075 ops->autosuspend_en = rtl8153b_runtime_enable; 5076 break; 5077 5078 default: 5079 ret = -ENODEV; 5080 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5081 break; 5082 } 5083 5084 return ret; 5085 } 5086 5087 static u8 rtl_get_version(struct usb_interface *intf) 5088 { 5089 struct usb_device *udev = interface_to_usbdev(intf); 5090 u32 ocp_data = 0; 5091 __le32 *tmp; 5092 u8 version; 5093 int ret; 5094 5095 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5096 if (!tmp) 5097 return 0; 5098 5099 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5100 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5101 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5102 if (ret > 0) 5103 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5104 5105 kfree(tmp); 5106 5107 switch (ocp_data) { 5108 case 0x4c00: 5109 version = RTL_VER_01; 5110 break; 5111 case 0x4c10: 5112 version = RTL_VER_02; 5113 break; 5114 case 0x5c00: 5115 version = RTL_VER_03; 5116 break; 5117 case 0x5c10: 5118 version = RTL_VER_04; 5119 break; 5120 case 0x5c20: 5121 version = RTL_VER_05; 5122 break; 5123 case 0x5c30: 5124 version = RTL_VER_06; 5125 break; 5126 case 0x4800: 5127 version = RTL_VER_07; 5128 break; 5129 case 0x6000: 5130 version = RTL_VER_08; 5131 break; 5132 case 0x6010: 5133 version = RTL_VER_09; 5134 break; 5135 default: 5136 version = RTL_VER_UNKNOWN; 5137 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5138 break; 5139 } 5140 5141 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5142 5143 return version; 5144 } 5145 5146 static int rtl8152_probe(struct usb_interface *intf, 5147 const struct usb_device_id *id) 5148 { 5149 struct usb_device *udev = interface_to_usbdev(intf); 5150 u8 version = rtl_get_version(intf); 5151 struct r8152 *tp; 5152 struct net_device *netdev; 5153 int ret; 5154 5155 if (version == RTL_VER_UNKNOWN) 5156 return -ENODEV; 5157 5158 if (udev->actconfig->desc.bConfigurationValue != 1) { 5159 usb_driver_set_configuration(udev, 1); 5160 return -ENODEV; 5161 } 5162 5163 usb_reset_device(udev); 5164 netdev = alloc_etherdev(sizeof(struct r8152)); 5165 if (!netdev) { 5166 dev_err(&intf->dev, "Out of memory\n"); 5167 return -ENOMEM; 5168 } 5169 5170 SET_NETDEV_DEV(netdev, &intf->dev); 5171 tp = netdev_priv(netdev); 5172 tp->msg_enable = 0x7FFF; 5173 5174 tp->udev = udev; 5175 tp->netdev = netdev; 5176 tp->intf = intf; 5177 tp->version = version; 5178 5179 switch (version) { 5180 case RTL_VER_01: 5181 case RTL_VER_02: 5182 case RTL_VER_07: 5183 tp->mii.supports_gmii = 0; 5184 break; 5185 default: 5186 tp->mii.supports_gmii = 1; 5187 break; 5188 } 5189 5190 ret = rtl_ops_init(tp); 5191 if (ret) 5192 goto out; 5193 5194 mutex_init(&tp->control); 5195 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5196 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5197 5198 netdev->netdev_ops = &rtl8152_netdev_ops; 5199 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5200 5201 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5202 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5203 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5204 NETIF_F_HW_VLAN_CTAG_TX; 5205 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5206 NETIF_F_TSO | NETIF_F_FRAGLIST | 5207 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5208 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5209 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5210 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5211 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5212 5213 if (tp->version == RTL_VER_01) { 5214 netdev->features &= ~NETIF_F_RXCSUM; 5215 netdev->hw_features &= ~NETIF_F_RXCSUM; 5216 } 5217 5218 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && 5219 udev->serial && !strcmp(udev->serial, "000001000000")) { 5220 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5221 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5222 } 5223 5224 netdev->ethtool_ops = &ops; 5225 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5226 5227 /* MTU range: 68 - 1500 or 9194 */ 5228 netdev->min_mtu = ETH_MIN_MTU; 5229 switch (tp->version) { 5230 case RTL_VER_01: 5231 case RTL_VER_02: 5232 netdev->max_mtu = ETH_DATA_LEN; 5233 break; 5234 default: 5235 netdev->max_mtu = RTL8153_MAX_MTU; 5236 break; 5237 } 5238 5239 tp->mii.dev = netdev; 5240 tp->mii.mdio_read = read_mii_word; 5241 tp->mii.mdio_write = write_mii_word; 5242 tp->mii.phy_id_mask = 0x3f; 5243 tp->mii.reg_num_mask = 0x1f; 5244 tp->mii.phy_id = R8152_PHY_ID; 5245 5246 tp->autoneg = AUTONEG_ENABLE; 5247 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5248 tp->duplex = DUPLEX_FULL; 5249 5250 intf->needs_remote_wakeup = 1; 5251 5252 tp->rtl_ops.init(tp); 5253 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5254 set_ethernet_addr(tp); 5255 5256 usb_set_intfdata(intf, tp); 5257 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5258 5259 ret = register_netdev(netdev); 5260 if (ret != 0) { 5261 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5262 goto out1; 5263 } 5264 5265 if (!rtl_can_wakeup(tp)) 5266 __rtl_set_wol(tp, 0); 5267 5268 tp->saved_wolopts = __rtl_get_wol(tp); 5269 if (tp->saved_wolopts) 5270 device_set_wakeup_enable(&udev->dev, true); 5271 else 5272 device_set_wakeup_enable(&udev->dev, false); 5273 5274 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5275 5276 return 0; 5277 5278 out1: 5279 netif_napi_del(&tp->napi); 5280 usb_set_intfdata(intf, NULL); 5281 out: 5282 free_netdev(netdev); 5283 return ret; 5284 } 5285 5286 static void rtl8152_disconnect(struct usb_interface *intf) 5287 { 5288 struct r8152 *tp = usb_get_intfdata(intf); 5289 5290 usb_set_intfdata(intf, NULL); 5291 if (tp) { 5292 struct usb_device *udev = tp->udev; 5293 5294 if (udev->state == USB_STATE_NOTATTACHED) 5295 set_bit(RTL8152_UNPLUG, &tp->flags); 5296 5297 netif_napi_del(&tp->napi); 5298 unregister_netdev(tp->netdev); 5299 cancel_delayed_work_sync(&tp->hw_phy_work); 5300 tp->rtl_ops.unload(tp); 5301 free_netdev(tp->netdev); 5302 } 5303 } 5304 5305 #define REALTEK_USB_DEVICE(vend, prod) \ 5306 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5307 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5308 .idVendor = (vend), \ 5309 .idProduct = (prod), \ 5310 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5311 }, \ 5312 { \ 5313 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5314 USB_DEVICE_ID_MATCH_DEVICE, \ 5315 .idVendor = (vend), \ 5316 .idProduct = (prod), \ 5317 .bInterfaceClass = USB_CLASS_COMM, \ 5318 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5319 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5320 5321 /* table of devices that work with this driver */ 5322 static const struct usb_device_id rtl8152_table[] = { 5323 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5324 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5325 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5326 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5327 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5328 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5329 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5330 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5331 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5332 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5333 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5334 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5335 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5336 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5337 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5338 {} 5339 }; 5340 5341 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5342 5343 static struct usb_driver rtl8152_driver = { 5344 .name = MODULENAME, 5345 .id_table = rtl8152_table, 5346 .probe = rtl8152_probe, 5347 .disconnect = rtl8152_disconnect, 5348 .suspend = rtl8152_suspend, 5349 .resume = rtl8152_resume, 5350 .reset_resume = rtl8152_reset_resume, 5351 .pre_reset = rtl8152_pre_reset, 5352 .post_reset = rtl8152_post_reset, 5353 .supports_autosuspend = 1, 5354 .disable_hub_initiated_lpm = 1, 5355 }; 5356 5357 module_usb_driver(rtl8152_driver); 5358 5359 MODULE_AUTHOR(DRIVER_AUTHOR); 5360 MODULE_DESCRIPTION(DRIVER_DESC); 5361 MODULE_LICENSE("GPL"); 5362 MODULE_VERSION(DRIVER_VERSION); 5363