1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 29 /* Version Information */ 30 #define DRIVER_VERSION "v1.07.0 (2014/10/09)" 31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 33 #define MODULENAME "r8152" 34 35 #define R8152_PHY_ID 32 36 37 #define PLA_IDR 0xc000 38 #define PLA_RCR 0xc010 39 #define PLA_RMS 0xc016 40 #define PLA_RXFIFO_CTRL0 0xc0a0 41 #define PLA_RXFIFO_CTRL1 0xc0a4 42 #define PLA_RXFIFO_CTRL2 0xc0a8 43 #define PLA_FMC 0xc0b4 44 #define PLA_CFG_WOL 0xc0b6 45 #define PLA_TEREDO_CFG 0xc0bc 46 #define PLA_MAR 0xcd00 47 #define PLA_BACKUP 0xd000 48 #define PAL_BDC_CR 0xd1a0 49 #define PLA_TEREDO_TIMER 0xd2cc 50 #define PLA_REALWOW_TIMER 0xd2e8 51 #define PLA_LEDSEL 0xdd90 52 #define PLA_LED_FEATURE 0xdd92 53 #define PLA_PHYAR 0xde00 54 #define PLA_BOOT_CTRL 0xe004 55 #define PLA_GPHY_INTR_IMR 0xe022 56 #define PLA_EEE_CR 0xe040 57 #define PLA_EEEP_CR 0xe080 58 #define PLA_MAC_PWR_CTRL 0xe0c0 59 #define PLA_MAC_PWR_CTRL2 0xe0ca 60 #define PLA_MAC_PWR_CTRL3 0xe0cc 61 #define PLA_MAC_PWR_CTRL4 0xe0ce 62 #define PLA_WDT6_CTRL 0xe428 63 #define PLA_TCR0 0xe610 64 #define PLA_TCR1 0xe612 65 #define PLA_MTPS 0xe615 66 #define PLA_TXFIFO_CTRL 0xe618 67 #define PLA_RSTTALLY 0xe800 68 #define PLA_CR 0xe813 69 #define PLA_CRWECR 0xe81c 70 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 71 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 72 #define PLA_CONFIG5 0xe822 73 #define PLA_PHY_PWR 0xe84c 74 #define PLA_OOB_CTRL 0xe84f 75 #define PLA_CPCR 0xe854 76 #define PLA_MISC_0 0xe858 77 #define PLA_MISC_1 0xe85a 78 #define PLA_OCP_GPHY_BASE 0xe86c 79 #define PLA_TALLYCNT 0xe890 80 #define PLA_SFF_STS_7 0xe8de 81 #define PLA_PHYSTATUS 0xe908 82 #define PLA_BP_BA 0xfc26 83 #define PLA_BP_0 0xfc28 84 #define PLA_BP_1 0xfc2a 85 #define PLA_BP_2 0xfc2c 86 #define PLA_BP_3 0xfc2e 87 #define PLA_BP_4 0xfc30 88 #define PLA_BP_5 0xfc32 89 #define PLA_BP_6 0xfc34 90 #define PLA_BP_7 0xfc36 91 #define PLA_BP_EN 0xfc38 92 93 #define USB_U2P3_CTRL 0xb460 94 #define USB_DEV_STAT 0xb808 95 #define USB_USB_CTRL 0xd406 96 #define USB_PHY_CTRL 0xd408 97 #define USB_TX_AGG 0xd40a 98 #define USB_RX_BUF_TH 0xd40c 99 #define USB_USB_TIMER 0xd428 100 #define USB_RX_EARLY_AGG 0xd42c 101 #define USB_PM_CTRL_STATUS 0xd432 102 #define USB_TX_DMA 0xd434 103 #define USB_TOLERANCE 0xd490 104 #define USB_LPM_CTRL 0xd41a 105 #define USB_UPS_CTRL 0xd800 106 #define USB_MISC_0 0xd81a 107 #define USB_POWER_CUT 0xd80a 108 #define USB_AFE_CTRL2 0xd824 109 #define USB_WDT11_CTRL 0xe43c 110 #define USB_BP_BA 0xfc26 111 #define USB_BP_0 0xfc28 112 #define USB_BP_1 0xfc2a 113 #define USB_BP_2 0xfc2c 114 #define USB_BP_3 0xfc2e 115 #define USB_BP_4 0xfc30 116 #define USB_BP_5 0xfc32 117 #define USB_BP_6 0xfc34 118 #define USB_BP_7 0xfc36 119 #define USB_BP_EN 0xfc38 120 121 /* OCP Registers */ 122 #define OCP_ALDPS_CONFIG 0x2010 123 #define OCP_EEE_CONFIG1 0x2080 124 #define OCP_EEE_CONFIG2 0x2092 125 #define OCP_EEE_CONFIG3 0x2094 126 #define OCP_BASE_MII 0xa400 127 #define OCP_EEE_AR 0xa41a 128 #define OCP_EEE_DATA 0xa41c 129 #define OCP_PHY_STATUS 0xa420 130 #define OCP_POWER_CFG 0xa430 131 #define OCP_EEE_CFG 0xa432 132 #define OCP_SRAM_ADDR 0xa436 133 #define OCP_SRAM_DATA 0xa438 134 #define OCP_DOWN_SPEED 0xa442 135 #define OCP_EEE_ABLE 0xa5c4 136 #define OCP_EEE_ADV 0xa5d0 137 #define OCP_EEE_LPABLE 0xa5d2 138 #define OCP_ADC_CFG 0xbc06 139 140 /* SRAM Register */ 141 #define SRAM_LPF_CFG 0x8012 142 #define SRAM_10M_AMP1 0x8080 143 #define SRAM_10M_AMP2 0x8082 144 #define SRAM_IMPEDANCE 0x8084 145 146 /* PLA_RCR */ 147 #define RCR_AAP 0x00000001 148 #define RCR_APM 0x00000002 149 #define RCR_AM 0x00000004 150 #define RCR_AB 0x00000008 151 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 152 153 /* PLA_RXFIFO_CTRL0 */ 154 #define RXFIFO_THR1_NORMAL 0x00080002 155 #define RXFIFO_THR1_OOB 0x01800003 156 157 /* PLA_RXFIFO_CTRL1 */ 158 #define RXFIFO_THR2_FULL 0x00000060 159 #define RXFIFO_THR2_HIGH 0x00000038 160 #define RXFIFO_THR2_OOB 0x0000004a 161 #define RXFIFO_THR2_NORMAL 0x00a0 162 163 /* PLA_RXFIFO_CTRL2 */ 164 #define RXFIFO_THR3_FULL 0x00000078 165 #define RXFIFO_THR3_HIGH 0x00000048 166 #define RXFIFO_THR3_OOB 0x0000005a 167 #define RXFIFO_THR3_NORMAL 0x0110 168 169 /* PLA_TXFIFO_CTRL */ 170 #define TXFIFO_THR_NORMAL 0x00400008 171 #define TXFIFO_THR_NORMAL2 0x01000008 172 173 /* PLA_FMC */ 174 #define FMC_FCR_MCU_EN 0x0001 175 176 /* PLA_EEEP_CR */ 177 #define EEEP_CR_EEEP_TX 0x0002 178 179 /* PLA_WDT6_CTRL */ 180 #define WDT6_SET_MODE 0x0010 181 182 /* PLA_TCR0 */ 183 #define TCR0_TX_EMPTY 0x0800 184 #define TCR0_AUTO_FIFO 0x0080 185 186 /* PLA_TCR1 */ 187 #define VERSION_MASK 0x7cf0 188 189 /* PLA_MTPS */ 190 #define MTPS_JUMBO (12 * 1024 / 64) 191 #define MTPS_DEFAULT (6 * 1024 / 64) 192 193 /* PLA_RSTTALLY */ 194 #define TALLY_RESET 0x0001 195 196 /* PLA_CR */ 197 #define CR_RST 0x10 198 #define CR_RE 0x08 199 #define CR_TE 0x04 200 201 /* PLA_CRWECR */ 202 #define CRWECR_NORAML 0x00 203 #define CRWECR_CONFIG 0xc0 204 205 /* PLA_OOB_CTRL */ 206 #define NOW_IS_OOB 0x80 207 #define TXFIFO_EMPTY 0x20 208 #define RXFIFO_EMPTY 0x10 209 #define LINK_LIST_READY 0x02 210 #define DIS_MCU_CLROOB 0x01 211 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 212 213 /* PLA_MISC_1 */ 214 #define RXDY_GATED_EN 0x0008 215 216 /* PLA_SFF_STS_7 */ 217 #define RE_INIT_LL 0x8000 218 #define MCU_BORW_EN 0x4000 219 220 /* PLA_CPCR */ 221 #define CPCR_RX_VLAN 0x0040 222 223 /* PLA_CFG_WOL */ 224 #define MAGIC_EN 0x0001 225 226 /* PLA_TEREDO_CFG */ 227 #define TEREDO_SEL 0x8000 228 #define TEREDO_WAKE_MASK 0x7f00 229 #define TEREDO_RS_EVENT_MASK 0x00fe 230 #define OOB_TEREDO_EN 0x0001 231 232 /* PAL_BDC_CR */ 233 #define ALDPS_PROXY_MODE 0x0001 234 235 /* PLA_CONFIG34 */ 236 #define LINK_ON_WAKE_EN 0x0010 237 #define LINK_OFF_WAKE_EN 0x0008 238 239 /* PLA_CONFIG5 */ 240 #define BWF_EN 0x0040 241 #define MWF_EN 0x0020 242 #define UWF_EN 0x0010 243 #define LAN_WAKE_EN 0x0002 244 245 /* PLA_LED_FEATURE */ 246 #define LED_MODE_MASK 0x0700 247 248 /* PLA_PHY_PWR */ 249 #define TX_10M_IDLE_EN 0x0080 250 #define PFM_PWM_SWITCH 0x0040 251 252 /* PLA_MAC_PWR_CTRL */ 253 #define D3_CLK_GATED_EN 0x00004000 254 #define MCU_CLK_RATIO 0x07010f07 255 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 256 #define ALDPS_SPDWN_RATIO 0x0f87 257 258 /* PLA_MAC_PWR_CTRL2 */ 259 #define EEE_SPDWN_RATIO 0x8007 260 261 /* PLA_MAC_PWR_CTRL3 */ 262 #define PKT_AVAIL_SPDWN_EN 0x0100 263 #define SUSPEND_SPDWN_EN 0x0004 264 #define U1U2_SPDWN_EN 0x0002 265 #define L1_SPDWN_EN 0x0001 266 267 /* PLA_MAC_PWR_CTRL4 */ 268 #define PWRSAVE_SPDWN_EN 0x1000 269 #define RXDV_SPDWN_EN 0x0800 270 #define TX10MIDLE_EN 0x0100 271 #define TP100_SPDWN_EN 0x0020 272 #define TP500_SPDWN_EN 0x0010 273 #define TP1000_SPDWN_EN 0x0008 274 #define EEE_SPDWN_EN 0x0001 275 276 /* PLA_GPHY_INTR_IMR */ 277 #define GPHY_STS_MSK 0x0001 278 #define SPEED_DOWN_MSK 0x0002 279 #define SPDWN_RXDV_MSK 0x0004 280 #define SPDWN_LINKCHG_MSK 0x0008 281 282 /* PLA_PHYAR */ 283 #define PHYAR_FLAG 0x80000000 284 285 /* PLA_EEE_CR */ 286 #define EEE_RX_EN 0x0001 287 #define EEE_TX_EN 0x0002 288 289 /* PLA_BOOT_CTRL */ 290 #define AUTOLOAD_DONE 0x0002 291 292 /* USB_DEV_STAT */ 293 #define STAT_SPEED_MASK 0x0006 294 #define STAT_SPEED_HIGH 0x0000 295 #define STAT_SPEED_FULL 0x0002 296 297 /* USB_TX_AGG */ 298 #define TX_AGG_MAX_THRESHOLD 0x03 299 300 /* USB_RX_BUF_TH */ 301 #define RX_THR_SUPPER 0x0c350180 302 #define RX_THR_HIGH 0x7a120180 303 #define RX_THR_SLOW 0xffff0180 304 305 /* USB_TX_DMA */ 306 #define TEST_MODE_DISABLE 0x00000001 307 #define TX_SIZE_ADJUST1 0x00000100 308 309 /* USB_UPS_CTRL */ 310 #define POWER_CUT 0x0100 311 312 /* USB_PM_CTRL_STATUS */ 313 #define RESUME_INDICATE 0x0001 314 315 /* USB_USB_CTRL */ 316 #define RX_AGG_DISABLE 0x0010 317 318 /* USB_U2P3_CTRL */ 319 #define U2P3_ENABLE 0x0001 320 321 /* USB_POWER_CUT */ 322 #define PWR_EN 0x0001 323 #define PHASE2_EN 0x0008 324 325 /* USB_MISC_0 */ 326 #define PCUT_STATUS 0x0001 327 328 /* USB_RX_EARLY_AGG */ 329 #define EARLY_AGG_SUPPER 0x0e832981 330 #define EARLY_AGG_HIGH 0x0e837a12 331 #define EARLY_AGG_SLOW 0x0e83ffff 332 333 /* USB_WDT11_CTRL */ 334 #define TIMER11_EN 0x0001 335 336 /* USB_LPM_CTRL */ 337 #define LPM_TIMER_MASK 0x0c 338 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 339 #define LPM_TIMER_500US 0x0c /* 500 us */ 340 341 /* USB_AFE_CTRL2 */ 342 #define SEN_VAL_MASK 0xf800 343 #define SEN_VAL_NORMAL 0xa000 344 #define SEL_RXIDLE 0x0100 345 346 /* OCP_ALDPS_CONFIG */ 347 #define ENPWRSAVE 0x8000 348 #define ENPDNPS 0x0200 349 #define LINKENA 0x0100 350 #define DIS_SDSAVE 0x0010 351 352 /* OCP_PHY_STATUS */ 353 #define PHY_STAT_MASK 0x0007 354 #define PHY_STAT_LAN_ON 3 355 #define PHY_STAT_PWRDN 5 356 357 /* OCP_POWER_CFG */ 358 #define EEE_CLKDIV_EN 0x8000 359 #define EN_ALDPS 0x0004 360 #define EN_10M_PLLOFF 0x0001 361 362 /* OCP_EEE_CONFIG1 */ 363 #define RG_TXLPI_MSK_HFDUP 0x8000 364 #define RG_MATCLR_EN 0x4000 365 #define EEE_10_CAP 0x2000 366 #define EEE_NWAY_EN 0x1000 367 #define TX_QUIET_EN 0x0200 368 #define RX_QUIET_EN 0x0100 369 #define sd_rise_time_mask 0x0070 370 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 371 #define RG_RXLPI_MSK_HFDUP 0x0008 372 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 373 374 /* OCP_EEE_CONFIG2 */ 375 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 376 #define RG_DACQUIET_EN 0x0400 377 #define RG_LDVQUIET_EN 0x0200 378 #define RG_CKRSEL 0x0020 379 #define RG_EEEPRG_EN 0x0010 380 381 /* OCP_EEE_CONFIG3 */ 382 #define fast_snr_mask 0xff80 383 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 384 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 385 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 386 387 /* OCP_EEE_AR */ 388 /* bit[15:14] function */ 389 #define FUN_ADDR 0x0000 390 #define FUN_DATA 0x4000 391 /* bit[4:0] device addr */ 392 393 /* OCP_EEE_CFG */ 394 #define CTAP_SHORT_EN 0x0040 395 #define EEE10_EN 0x0010 396 397 /* OCP_DOWN_SPEED */ 398 #define EN_10M_BGOFF 0x0080 399 400 /* OCP_ADC_CFG */ 401 #define CKADSEL_L 0x0100 402 #define ADC_EN 0x0080 403 #define EN_EMI_L 0x0040 404 405 /* SRAM_LPF_CFG */ 406 #define LPF_AUTO_TUNE 0x8000 407 408 /* SRAM_10M_AMP1 */ 409 #define GDAC_IB_UPALL 0x0008 410 411 /* SRAM_10M_AMP2 */ 412 #define AMP_DN 0x0200 413 414 /* SRAM_IMPEDANCE */ 415 #define RX_DRIVING_MASK 0x6000 416 417 enum rtl_register_content { 418 _1000bps = 0x10, 419 _100bps = 0x08, 420 _10bps = 0x04, 421 LINK_STATUS = 0x02, 422 FULL_DUP = 0x01, 423 }; 424 425 #define RTL8152_MAX_TX 4 426 #define RTL8152_MAX_RX 10 427 #define INTBUFSIZE 2 428 #define CRC_SIZE 4 429 #define TX_ALIGN 4 430 #define RX_ALIGN 8 431 432 #define INTR_LINK 0x0004 433 434 #define RTL8152_REQT_READ 0xc0 435 #define RTL8152_REQT_WRITE 0x40 436 #define RTL8152_REQ_GET_REGS 0x05 437 #define RTL8152_REQ_SET_REGS 0x05 438 439 #define BYTE_EN_DWORD 0xff 440 #define BYTE_EN_WORD 0x33 441 #define BYTE_EN_BYTE 0x11 442 #define BYTE_EN_SIX_BYTES 0x3f 443 #define BYTE_EN_START_MASK 0x0f 444 #define BYTE_EN_END_MASK 0xf0 445 446 #define RTL8153_MAX_PACKET 9216 /* 9K */ 447 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 448 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 449 #define RTL8153_RMS RTL8153_MAX_PACKET 450 #define RTL8152_TX_TIMEOUT (5 * HZ) 451 452 /* rtl8152 flags */ 453 enum rtl8152_flags { 454 RTL8152_UNPLUG = 0, 455 RTL8152_SET_RX_MODE, 456 WORK_ENABLE, 457 RTL8152_LINK_CHG, 458 SELECTIVE_SUSPEND, 459 PHY_RESET, 460 SCHEDULE_TASKLET, 461 }; 462 463 /* Define these values to match your device */ 464 #define VENDOR_ID_REALTEK 0x0bda 465 #define VENDOR_ID_SAMSUNG 0x04e8 466 467 #define MCU_TYPE_PLA 0x0100 468 #define MCU_TYPE_USB 0x0000 469 470 struct tally_counter { 471 __le64 tx_packets; 472 __le64 rx_packets; 473 __le64 tx_errors; 474 __le32 rx_errors; 475 __le16 rx_missed; 476 __le16 align_errors; 477 __le32 tx_one_collision; 478 __le32 tx_multi_collision; 479 __le64 rx_unicast; 480 __le64 rx_broadcast; 481 __le32 rx_multicast; 482 __le16 tx_aborted; 483 __le16 tx_underrun; 484 }; 485 486 struct rx_desc { 487 __le32 opts1; 488 #define RX_LEN_MASK 0x7fff 489 490 __le32 opts2; 491 #define RD_UDP_CS (1 << 23) 492 #define RD_TCP_CS (1 << 22) 493 #define RD_IPV6_CS (1 << 20) 494 #define RD_IPV4_CS (1 << 19) 495 496 __le32 opts3; 497 #define IPF (1 << 23) /* IP checksum fail */ 498 #define UDPF (1 << 22) /* UDP checksum fail */ 499 #define TCPF (1 << 21) /* TCP checksum fail */ 500 #define RX_VLAN_TAG (1 << 16) 501 502 __le32 opts4; 503 __le32 opts5; 504 __le32 opts6; 505 }; 506 507 struct tx_desc { 508 __le32 opts1; 509 #define TX_FS (1 << 31) /* First segment of a packet */ 510 #define TX_LS (1 << 30) /* Final segment of a packet */ 511 #define GTSENDV4 (1 << 28) 512 #define GTSENDV6 (1 << 27) 513 #define GTTCPHO_SHIFT 18 514 #define GTTCPHO_MAX 0x7fU 515 #define TX_LEN_MAX 0x3ffffU 516 517 __le32 opts2; 518 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 519 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 520 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 521 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 522 #define MSS_SHIFT 17 523 #define MSS_MAX 0x7ffU 524 #define TCPHO_SHIFT 17 525 #define TCPHO_MAX 0x7ffU 526 #define TX_VLAN_TAG (1 << 16) 527 }; 528 529 struct r8152; 530 531 struct rx_agg { 532 struct list_head list; 533 struct urb *urb; 534 struct r8152 *context; 535 void *buffer; 536 void *head; 537 }; 538 539 struct tx_agg { 540 struct list_head list; 541 struct urb *urb; 542 struct r8152 *context; 543 void *buffer; 544 void *head; 545 u32 skb_num; 546 u32 skb_len; 547 }; 548 549 struct r8152 { 550 unsigned long flags; 551 struct usb_device *udev; 552 struct tasklet_struct tl; 553 struct usb_interface *intf; 554 struct net_device *netdev; 555 struct urb *intr_urb; 556 struct tx_agg tx_info[RTL8152_MAX_TX]; 557 struct rx_agg rx_info[RTL8152_MAX_RX]; 558 struct list_head rx_done, tx_free; 559 struct sk_buff_head tx_queue; 560 spinlock_t rx_lock, tx_lock; 561 struct delayed_work schedule; 562 struct mii_if_info mii; 563 struct mutex control; /* use for hw setting */ 564 565 struct rtl_ops { 566 void (*init)(struct r8152 *); 567 int (*enable)(struct r8152 *); 568 void (*disable)(struct r8152 *); 569 void (*up)(struct r8152 *); 570 void (*down)(struct r8152 *); 571 void (*unload)(struct r8152 *); 572 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 573 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 574 } rtl_ops; 575 576 int intr_interval; 577 u32 saved_wolopts; 578 u32 msg_enable; 579 u32 tx_qlen; 580 u16 ocp_base; 581 u8 *intr_buff; 582 u8 version; 583 u8 speed; 584 }; 585 586 enum rtl_version { 587 RTL_VER_UNKNOWN = 0, 588 RTL_VER_01, 589 RTL_VER_02, 590 RTL_VER_03, 591 RTL_VER_04, 592 RTL_VER_05, 593 RTL_VER_MAX 594 }; 595 596 enum tx_csum_stat { 597 TX_CSUM_SUCCESS = 0, 598 TX_CSUM_TSO, 599 TX_CSUM_NONE 600 }; 601 602 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 603 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 604 */ 605 static const int multicast_filter_limit = 32; 606 static unsigned int agg_buf_sz = 16384; 607 608 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 609 VLAN_ETH_HLEN - VLAN_HLEN) 610 611 static 612 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 613 { 614 int ret; 615 void *tmp; 616 617 tmp = kmalloc(size, GFP_KERNEL); 618 if (!tmp) 619 return -ENOMEM; 620 621 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 622 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 623 value, index, tmp, size, 500); 624 625 memcpy(data, tmp, size); 626 kfree(tmp); 627 628 return ret; 629 } 630 631 static 632 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 633 { 634 int ret; 635 void *tmp; 636 637 tmp = kmemdup(data, size, GFP_KERNEL); 638 if (!tmp) 639 return -ENOMEM; 640 641 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 642 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 643 value, index, tmp, size, 500); 644 645 kfree(tmp); 646 647 return ret; 648 } 649 650 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 651 void *data, u16 type) 652 { 653 u16 limit = 64; 654 int ret = 0; 655 656 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 657 return -ENODEV; 658 659 /* both size and indix must be 4 bytes align */ 660 if ((size & 3) || !size || (index & 3) || !data) 661 return -EPERM; 662 663 if ((u32)index + (u32)size > 0xffff) 664 return -EPERM; 665 666 while (size) { 667 if (size > limit) { 668 ret = get_registers(tp, index, type, limit, data); 669 if (ret < 0) 670 break; 671 672 index += limit; 673 data += limit; 674 size -= limit; 675 } else { 676 ret = get_registers(tp, index, type, size, data); 677 if (ret < 0) 678 break; 679 680 index += size; 681 data += size; 682 size = 0; 683 break; 684 } 685 } 686 687 if (ret == -ENODEV) 688 set_bit(RTL8152_UNPLUG, &tp->flags); 689 690 return ret; 691 } 692 693 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 694 u16 size, void *data, u16 type) 695 { 696 int ret; 697 u16 byteen_start, byteen_end, byen; 698 u16 limit = 512; 699 700 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 701 return -ENODEV; 702 703 /* both size and indix must be 4 bytes align */ 704 if ((size & 3) || !size || (index & 3) || !data) 705 return -EPERM; 706 707 if ((u32)index + (u32)size > 0xffff) 708 return -EPERM; 709 710 byteen_start = byteen & BYTE_EN_START_MASK; 711 byteen_end = byteen & BYTE_EN_END_MASK; 712 713 byen = byteen_start | (byteen_start << 4); 714 ret = set_registers(tp, index, type | byen, 4, data); 715 if (ret < 0) 716 goto error1; 717 718 index += 4; 719 data += 4; 720 size -= 4; 721 722 if (size) { 723 size -= 4; 724 725 while (size) { 726 if (size > limit) { 727 ret = set_registers(tp, index, 728 type | BYTE_EN_DWORD, 729 limit, data); 730 if (ret < 0) 731 goto error1; 732 733 index += limit; 734 data += limit; 735 size -= limit; 736 } else { 737 ret = set_registers(tp, index, 738 type | BYTE_EN_DWORD, 739 size, data); 740 if (ret < 0) 741 goto error1; 742 743 index += size; 744 data += size; 745 size = 0; 746 break; 747 } 748 } 749 750 byen = byteen_end | (byteen_end >> 4); 751 ret = set_registers(tp, index, type | byen, 4, data); 752 if (ret < 0) 753 goto error1; 754 } 755 756 error1: 757 if (ret == -ENODEV) 758 set_bit(RTL8152_UNPLUG, &tp->flags); 759 760 return ret; 761 } 762 763 static inline 764 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 765 { 766 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 767 } 768 769 static inline 770 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 771 { 772 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 773 } 774 775 static inline 776 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 777 { 778 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 779 } 780 781 static inline 782 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 783 { 784 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 785 } 786 787 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 788 { 789 __le32 data; 790 791 generic_ocp_read(tp, index, sizeof(data), &data, type); 792 793 return __le32_to_cpu(data); 794 } 795 796 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 797 { 798 __le32 tmp = __cpu_to_le32(data); 799 800 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 801 } 802 803 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 804 { 805 u32 data; 806 __le32 tmp; 807 u8 shift = index & 2; 808 809 index &= ~3; 810 811 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 812 813 data = __le32_to_cpu(tmp); 814 data >>= (shift * 8); 815 data &= 0xffff; 816 817 return (u16)data; 818 } 819 820 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 821 { 822 u32 mask = 0xffff; 823 __le32 tmp; 824 u16 byen = BYTE_EN_WORD; 825 u8 shift = index & 2; 826 827 data &= mask; 828 829 if (index & 2) { 830 byen <<= shift; 831 mask <<= (shift * 8); 832 data <<= (shift * 8); 833 index &= ~3; 834 } 835 836 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 837 838 data |= __le32_to_cpu(tmp) & ~mask; 839 tmp = __cpu_to_le32(data); 840 841 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 842 } 843 844 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 845 { 846 u32 data; 847 __le32 tmp; 848 u8 shift = index & 3; 849 850 index &= ~3; 851 852 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 853 854 data = __le32_to_cpu(tmp); 855 data >>= (shift * 8); 856 data &= 0xff; 857 858 return (u8)data; 859 } 860 861 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 862 { 863 u32 mask = 0xff; 864 __le32 tmp; 865 u16 byen = BYTE_EN_BYTE; 866 u8 shift = index & 3; 867 868 data &= mask; 869 870 if (index & 3) { 871 byen <<= shift; 872 mask <<= (shift * 8); 873 data <<= (shift * 8); 874 index &= ~3; 875 } 876 877 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 878 879 data |= __le32_to_cpu(tmp) & ~mask; 880 tmp = __cpu_to_le32(data); 881 882 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 883 } 884 885 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 886 { 887 u16 ocp_base, ocp_index; 888 889 ocp_base = addr & 0xf000; 890 if (ocp_base != tp->ocp_base) { 891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 892 tp->ocp_base = ocp_base; 893 } 894 895 ocp_index = (addr & 0x0fff) | 0xb000; 896 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 897 } 898 899 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 900 { 901 u16 ocp_base, ocp_index; 902 903 ocp_base = addr & 0xf000; 904 if (ocp_base != tp->ocp_base) { 905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 906 tp->ocp_base = ocp_base; 907 } 908 909 ocp_index = (addr & 0x0fff) | 0xb000; 910 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 911 } 912 913 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 914 { 915 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 916 } 917 918 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 919 { 920 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 921 } 922 923 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 924 { 925 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 926 ocp_reg_write(tp, OCP_SRAM_DATA, data); 927 } 928 929 static u16 sram_read(struct r8152 *tp, u16 addr) 930 { 931 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 932 return ocp_reg_read(tp, OCP_SRAM_DATA); 933 } 934 935 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 936 { 937 struct r8152 *tp = netdev_priv(netdev); 938 int ret; 939 940 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 941 return -ENODEV; 942 943 if (phy_id != R8152_PHY_ID) 944 return -EINVAL; 945 946 ret = r8152_mdio_read(tp, reg); 947 948 return ret; 949 } 950 951 static 952 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 953 { 954 struct r8152 *tp = netdev_priv(netdev); 955 956 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 957 return; 958 959 if (phy_id != R8152_PHY_ID) 960 return; 961 962 r8152_mdio_write(tp, reg, val); 963 } 964 965 static int 966 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 967 968 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 969 { 970 struct r8152 *tp = netdev_priv(netdev); 971 struct sockaddr *addr = p; 972 int ret = -EADDRNOTAVAIL; 973 974 if (!is_valid_ether_addr(addr->sa_data)) 975 goto out1; 976 977 ret = usb_autopm_get_interface(tp->intf); 978 if (ret < 0) 979 goto out1; 980 981 mutex_lock(&tp->control); 982 983 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 984 985 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 986 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 988 989 mutex_unlock(&tp->control); 990 991 usb_autopm_put_interface(tp->intf); 992 out1: 993 return ret; 994 } 995 996 static int set_ethernet_addr(struct r8152 *tp) 997 { 998 struct net_device *dev = tp->netdev; 999 struct sockaddr sa; 1000 int ret; 1001 1002 if (tp->version == RTL_VER_01) 1003 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1004 else 1005 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1006 1007 if (ret < 0) { 1008 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1009 } else if (!is_valid_ether_addr(sa.sa_data)) { 1010 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1011 sa.sa_data); 1012 eth_hw_addr_random(dev); 1013 ether_addr_copy(sa.sa_data, dev->dev_addr); 1014 ret = rtl8152_set_mac_address(dev, &sa); 1015 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1016 sa.sa_data); 1017 } else { 1018 if (tp->version == RTL_VER_01) 1019 ether_addr_copy(dev->dev_addr, sa.sa_data); 1020 else 1021 ret = rtl8152_set_mac_address(dev, &sa); 1022 } 1023 1024 return ret; 1025 } 1026 1027 static void read_bulk_callback(struct urb *urb) 1028 { 1029 struct net_device *netdev; 1030 int status = urb->status; 1031 struct rx_agg *agg; 1032 struct r8152 *tp; 1033 1034 agg = urb->context; 1035 if (!agg) 1036 return; 1037 1038 tp = agg->context; 1039 if (!tp) 1040 return; 1041 1042 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1043 return; 1044 1045 if (!test_bit(WORK_ENABLE, &tp->flags)) 1046 return; 1047 1048 netdev = tp->netdev; 1049 1050 /* When link down, the driver would cancel all bulks. */ 1051 /* This avoid the re-submitting bulk */ 1052 if (!netif_carrier_ok(netdev)) 1053 return; 1054 1055 usb_mark_last_busy(tp->udev); 1056 1057 switch (status) { 1058 case 0: 1059 if (urb->actual_length < ETH_ZLEN) 1060 break; 1061 1062 spin_lock(&tp->rx_lock); 1063 list_add_tail(&agg->list, &tp->rx_done); 1064 spin_unlock(&tp->rx_lock); 1065 tasklet_schedule(&tp->tl); 1066 return; 1067 case -ESHUTDOWN: 1068 set_bit(RTL8152_UNPLUG, &tp->flags); 1069 netif_device_detach(tp->netdev); 1070 return; 1071 case -ENOENT: 1072 return; /* the urb is in unlink state */ 1073 case -ETIME: 1074 if (net_ratelimit()) 1075 netdev_warn(netdev, "maybe reset is needed?\n"); 1076 break; 1077 default: 1078 if (net_ratelimit()) 1079 netdev_warn(netdev, "Rx status %d\n", status); 1080 break; 1081 } 1082 1083 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1084 } 1085 1086 static void write_bulk_callback(struct urb *urb) 1087 { 1088 struct net_device_stats *stats; 1089 struct net_device *netdev; 1090 struct tx_agg *agg; 1091 struct r8152 *tp; 1092 int status = urb->status; 1093 1094 agg = urb->context; 1095 if (!agg) 1096 return; 1097 1098 tp = agg->context; 1099 if (!tp) 1100 return; 1101 1102 netdev = tp->netdev; 1103 stats = &netdev->stats; 1104 if (status) { 1105 if (net_ratelimit()) 1106 netdev_warn(netdev, "Tx status %d\n", status); 1107 stats->tx_errors += agg->skb_num; 1108 } else { 1109 stats->tx_packets += agg->skb_num; 1110 stats->tx_bytes += agg->skb_len; 1111 } 1112 1113 spin_lock(&tp->tx_lock); 1114 list_add_tail(&agg->list, &tp->tx_free); 1115 spin_unlock(&tp->tx_lock); 1116 1117 usb_autopm_put_interface_async(tp->intf); 1118 1119 if (!netif_carrier_ok(netdev)) 1120 return; 1121 1122 if (!test_bit(WORK_ENABLE, &tp->flags)) 1123 return; 1124 1125 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1126 return; 1127 1128 if (!skb_queue_empty(&tp->tx_queue)) 1129 tasklet_schedule(&tp->tl); 1130 } 1131 1132 static void intr_callback(struct urb *urb) 1133 { 1134 struct r8152 *tp; 1135 __le16 *d; 1136 int status = urb->status; 1137 int res; 1138 1139 tp = urb->context; 1140 if (!tp) 1141 return; 1142 1143 if (!test_bit(WORK_ENABLE, &tp->flags)) 1144 return; 1145 1146 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1147 return; 1148 1149 switch (status) { 1150 case 0: /* success */ 1151 break; 1152 case -ECONNRESET: /* unlink */ 1153 case -ESHUTDOWN: 1154 netif_device_detach(tp->netdev); 1155 case -ENOENT: 1156 case -EPROTO: 1157 netif_info(tp, intr, tp->netdev, 1158 "Stop submitting intr, status %d\n", status); 1159 return; 1160 case -EOVERFLOW: 1161 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1162 goto resubmit; 1163 /* -EPIPE: should clear the halt */ 1164 default: 1165 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1166 goto resubmit; 1167 } 1168 1169 d = urb->transfer_buffer; 1170 if (INTR_LINK & __le16_to_cpu(d[0])) { 1171 if (!(tp->speed & LINK_STATUS)) { 1172 set_bit(RTL8152_LINK_CHG, &tp->flags); 1173 schedule_delayed_work(&tp->schedule, 0); 1174 } 1175 } else { 1176 if (tp->speed & LINK_STATUS) { 1177 set_bit(RTL8152_LINK_CHG, &tp->flags); 1178 schedule_delayed_work(&tp->schedule, 0); 1179 } 1180 } 1181 1182 resubmit: 1183 res = usb_submit_urb(urb, GFP_ATOMIC); 1184 if (res == -ENODEV) { 1185 set_bit(RTL8152_UNPLUG, &tp->flags); 1186 netif_device_detach(tp->netdev); 1187 } else if (res) { 1188 netif_err(tp, intr, tp->netdev, 1189 "can't resubmit intr, status %d\n", res); 1190 } 1191 } 1192 1193 static inline void *rx_agg_align(void *data) 1194 { 1195 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1196 } 1197 1198 static inline void *tx_agg_align(void *data) 1199 { 1200 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1201 } 1202 1203 static void free_all_mem(struct r8152 *tp) 1204 { 1205 int i; 1206 1207 for (i = 0; i < RTL8152_MAX_RX; i++) { 1208 usb_free_urb(tp->rx_info[i].urb); 1209 tp->rx_info[i].urb = NULL; 1210 1211 kfree(tp->rx_info[i].buffer); 1212 tp->rx_info[i].buffer = NULL; 1213 tp->rx_info[i].head = NULL; 1214 } 1215 1216 for (i = 0; i < RTL8152_MAX_TX; i++) { 1217 usb_free_urb(tp->tx_info[i].urb); 1218 tp->tx_info[i].urb = NULL; 1219 1220 kfree(tp->tx_info[i].buffer); 1221 tp->tx_info[i].buffer = NULL; 1222 tp->tx_info[i].head = NULL; 1223 } 1224 1225 usb_free_urb(tp->intr_urb); 1226 tp->intr_urb = NULL; 1227 1228 kfree(tp->intr_buff); 1229 tp->intr_buff = NULL; 1230 } 1231 1232 static int alloc_all_mem(struct r8152 *tp) 1233 { 1234 struct net_device *netdev = tp->netdev; 1235 struct usb_interface *intf = tp->intf; 1236 struct usb_host_interface *alt = intf->cur_altsetting; 1237 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1238 struct urb *urb; 1239 int node, i; 1240 u8 *buf; 1241 1242 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1243 1244 spin_lock_init(&tp->rx_lock); 1245 spin_lock_init(&tp->tx_lock); 1246 INIT_LIST_HEAD(&tp->tx_free); 1247 skb_queue_head_init(&tp->tx_queue); 1248 1249 for (i = 0; i < RTL8152_MAX_RX; i++) { 1250 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1251 if (!buf) 1252 goto err1; 1253 1254 if (buf != rx_agg_align(buf)) { 1255 kfree(buf); 1256 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1257 node); 1258 if (!buf) 1259 goto err1; 1260 } 1261 1262 urb = usb_alloc_urb(0, GFP_KERNEL); 1263 if (!urb) { 1264 kfree(buf); 1265 goto err1; 1266 } 1267 1268 INIT_LIST_HEAD(&tp->rx_info[i].list); 1269 tp->rx_info[i].context = tp; 1270 tp->rx_info[i].urb = urb; 1271 tp->rx_info[i].buffer = buf; 1272 tp->rx_info[i].head = rx_agg_align(buf); 1273 } 1274 1275 for (i = 0; i < RTL8152_MAX_TX; i++) { 1276 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1277 if (!buf) 1278 goto err1; 1279 1280 if (buf != tx_agg_align(buf)) { 1281 kfree(buf); 1282 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1283 node); 1284 if (!buf) 1285 goto err1; 1286 } 1287 1288 urb = usb_alloc_urb(0, GFP_KERNEL); 1289 if (!urb) { 1290 kfree(buf); 1291 goto err1; 1292 } 1293 1294 INIT_LIST_HEAD(&tp->tx_info[i].list); 1295 tp->tx_info[i].context = tp; 1296 tp->tx_info[i].urb = urb; 1297 tp->tx_info[i].buffer = buf; 1298 tp->tx_info[i].head = tx_agg_align(buf); 1299 1300 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1301 } 1302 1303 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1304 if (!tp->intr_urb) 1305 goto err1; 1306 1307 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1308 if (!tp->intr_buff) 1309 goto err1; 1310 1311 tp->intr_interval = (int)ep_intr->desc.bInterval; 1312 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1313 tp->intr_buff, INTBUFSIZE, intr_callback, 1314 tp, tp->intr_interval); 1315 1316 return 0; 1317 1318 err1: 1319 free_all_mem(tp); 1320 return -ENOMEM; 1321 } 1322 1323 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1324 { 1325 struct tx_agg *agg = NULL; 1326 unsigned long flags; 1327 1328 if (list_empty(&tp->tx_free)) 1329 return NULL; 1330 1331 spin_lock_irqsave(&tp->tx_lock, flags); 1332 if (!list_empty(&tp->tx_free)) { 1333 struct list_head *cursor; 1334 1335 cursor = tp->tx_free.next; 1336 list_del_init(cursor); 1337 agg = list_entry(cursor, struct tx_agg, list); 1338 } 1339 spin_unlock_irqrestore(&tp->tx_lock, flags); 1340 1341 return agg; 1342 } 1343 1344 static inline __be16 get_protocol(struct sk_buff *skb) 1345 { 1346 __be16 protocol; 1347 1348 if (skb->protocol == htons(ETH_P_8021Q)) 1349 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1350 else 1351 protocol = skb->protocol; 1352 1353 return protocol; 1354 } 1355 1356 /* r8152_csum_workaround() 1357 * The hw limites the value the transport offset. When the offset is out of the 1358 * range, calculate the checksum by sw. 1359 */ 1360 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1361 struct sk_buff_head *list) 1362 { 1363 if (skb_shinfo(skb)->gso_size) { 1364 netdev_features_t features = tp->netdev->features; 1365 struct sk_buff_head seg_list; 1366 struct sk_buff *segs, *nskb; 1367 1368 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1369 segs = skb_gso_segment(skb, features); 1370 if (IS_ERR(segs) || !segs) 1371 goto drop; 1372 1373 __skb_queue_head_init(&seg_list); 1374 1375 do { 1376 nskb = segs; 1377 segs = segs->next; 1378 nskb->next = NULL; 1379 __skb_queue_tail(&seg_list, nskb); 1380 } while (segs); 1381 1382 skb_queue_splice(&seg_list, list); 1383 dev_kfree_skb(skb); 1384 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1385 if (skb_checksum_help(skb) < 0) 1386 goto drop; 1387 1388 __skb_queue_head(list, skb); 1389 } else { 1390 struct net_device_stats *stats; 1391 1392 drop: 1393 stats = &tp->netdev->stats; 1394 stats->tx_dropped++; 1395 dev_kfree_skb(skb); 1396 } 1397 } 1398 1399 /* msdn_giant_send_check() 1400 * According to the document of microsoft, the TCP Pseudo Header excludes the 1401 * packet length for IPv6 TCP large packets. 1402 */ 1403 static int msdn_giant_send_check(struct sk_buff *skb) 1404 { 1405 const struct ipv6hdr *ipv6h; 1406 struct tcphdr *th; 1407 int ret; 1408 1409 ret = skb_cow_head(skb, 0); 1410 if (ret) 1411 return ret; 1412 1413 ipv6h = ipv6_hdr(skb); 1414 th = tcp_hdr(skb); 1415 1416 th->check = 0; 1417 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1418 1419 return ret; 1420 } 1421 1422 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1423 { 1424 if (vlan_tx_tag_present(skb)) { 1425 u32 opts2; 1426 1427 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb)); 1428 desc->opts2 |= cpu_to_le32(opts2); 1429 } 1430 } 1431 1432 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1433 { 1434 u32 opts2 = le32_to_cpu(desc->opts2); 1435 1436 if (opts2 & RX_VLAN_TAG) 1437 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1438 swab16(opts2 & 0xffff)); 1439 } 1440 1441 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1442 struct sk_buff *skb, u32 len, u32 transport_offset) 1443 { 1444 u32 mss = skb_shinfo(skb)->gso_size; 1445 u32 opts1, opts2 = 0; 1446 int ret = TX_CSUM_SUCCESS; 1447 1448 WARN_ON_ONCE(len > TX_LEN_MAX); 1449 1450 opts1 = len | TX_FS | TX_LS; 1451 1452 if (mss) { 1453 if (transport_offset > GTTCPHO_MAX) { 1454 netif_warn(tp, tx_err, tp->netdev, 1455 "Invalid transport offset 0x%x for TSO\n", 1456 transport_offset); 1457 ret = TX_CSUM_TSO; 1458 goto unavailable; 1459 } 1460 1461 switch (get_protocol(skb)) { 1462 case htons(ETH_P_IP): 1463 opts1 |= GTSENDV4; 1464 break; 1465 1466 case htons(ETH_P_IPV6): 1467 if (msdn_giant_send_check(skb)) { 1468 ret = TX_CSUM_TSO; 1469 goto unavailable; 1470 } 1471 opts1 |= GTSENDV6; 1472 break; 1473 1474 default: 1475 WARN_ON_ONCE(1); 1476 break; 1477 } 1478 1479 opts1 |= transport_offset << GTTCPHO_SHIFT; 1480 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1481 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1482 u8 ip_protocol; 1483 1484 if (transport_offset > TCPHO_MAX) { 1485 netif_warn(tp, tx_err, tp->netdev, 1486 "Invalid transport offset 0x%x\n", 1487 transport_offset); 1488 ret = TX_CSUM_NONE; 1489 goto unavailable; 1490 } 1491 1492 switch (get_protocol(skb)) { 1493 case htons(ETH_P_IP): 1494 opts2 |= IPV4_CS; 1495 ip_protocol = ip_hdr(skb)->protocol; 1496 break; 1497 1498 case htons(ETH_P_IPV6): 1499 opts2 |= IPV6_CS; 1500 ip_protocol = ipv6_hdr(skb)->nexthdr; 1501 break; 1502 1503 default: 1504 ip_protocol = IPPROTO_RAW; 1505 break; 1506 } 1507 1508 if (ip_protocol == IPPROTO_TCP) 1509 opts2 |= TCP_CS; 1510 else if (ip_protocol == IPPROTO_UDP) 1511 opts2 |= UDP_CS; 1512 else 1513 WARN_ON_ONCE(1); 1514 1515 opts2 |= transport_offset << TCPHO_SHIFT; 1516 } 1517 1518 desc->opts2 = cpu_to_le32(opts2); 1519 desc->opts1 = cpu_to_le32(opts1); 1520 1521 unavailable: 1522 return ret; 1523 } 1524 1525 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1526 { 1527 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1528 int remain, ret; 1529 u8 *tx_data; 1530 1531 __skb_queue_head_init(&skb_head); 1532 spin_lock(&tx_queue->lock); 1533 skb_queue_splice_init(tx_queue, &skb_head); 1534 spin_unlock(&tx_queue->lock); 1535 1536 tx_data = agg->head; 1537 agg->skb_num = 0; 1538 agg->skb_len = 0; 1539 remain = agg_buf_sz; 1540 1541 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1542 struct tx_desc *tx_desc; 1543 struct sk_buff *skb; 1544 unsigned int len; 1545 u32 offset; 1546 1547 skb = __skb_dequeue(&skb_head); 1548 if (!skb) 1549 break; 1550 1551 len = skb->len + sizeof(*tx_desc); 1552 1553 if (len > remain) { 1554 __skb_queue_head(&skb_head, skb); 1555 break; 1556 } 1557 1558 tx_data = tx_agg_align(tx_data); 1559 tx_desc = (struct tx_desc *)tx_data; 1560 1561 offset = (u32)skb_transport_offset(skb); 1562 1563 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1564 r8152_csum_workaround(tp, skb, &skb_head); 1565 continue; 1566 } 1567 1568 rtl_tx_vlan_tag(tx_desc, skb); 1569 1570 tx_data += sizeof(*tx_desc); 1571 1572 len = skb->len; 1573 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1574 struct net_device_stats *stats = &tp->netdev->stats; 1575 1576 stats->tx_dropped++; 1577 dev_kfree_skb_any(skb); 1578 tx_data -= sizeof(*tx_desc); 1579 continue; 1580 } 1581 1582 tx_data += len; 1583 agg->skb_len += len; 1584 agg->skb_num++; 1585 1586 dev_kfree_skb_any(skb); 1587 1588 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1589 } 1590 1591 if (!skb_queue_empty(&skb_head)) { 1592 spin_lock(&tx_queue->lock); 1593 skb_queue_splice(&skb_head, tx_queue); 1594 spin_unlock(&tx_queue->lock); 1595 } 1596 1597 netif_tx_lock(tp->netdev); 1598 1599 if (netif_queue_stopped(tp->netdev) && 1600 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1601 netif_wake_queue(tp->netdev); 1602 1603 netif_tx_unlock(tp->netdev); 1604 1605 ret = usb_autopm_get_interface_async(tp->intf); 1606 if (ret < 0) 1607 goto out_tx_fill; 1608 1609 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1610 agg->head, (int)(tx_data - (u8 *)agg->head), 1611 (usb_complete_t)write_bulk_callback, agg); 1612 1613 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1614 if (ret < 0) 1615 usb_autopm_put_interface_async(tp->intf); 1616 1617 out_tx_fill: 1618 return ret; 1619 } 1620 1621 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1622 { 1623 u8 checksum = CHECKSUM_NONE; 1624 u32 opts2, opts3; 1625 1626 if (tp->version == RTL_VER_01) 1627 goto return_result; 1628 1629 opts2 = le32_to_cpu(rx_desc->opts2); 1630 opts3 = le32_to_cpu(rx_desc->opts3); 1631 1632 if (opts2 & RD_IPV4_CS) { 1633 if (opts3 & IPF) 1634 checksum = CHECKSUM_NONE; 1635 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1636 checksum = CHECKSUM_NONE; 1637 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1638 checksum = CHECKSUM_NONE; 1639 else 1640 checksum = CHECKSUM_UNNECESSARY; 1641 } else if (RD_IPV6_CS) { 1642 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1643 checksum = CHECKSUM_UNNECESSARY; 1644 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1645 checksum = CHECKSUM_UNNECESSARY; 1646 } 1647 1648 return_result: 1649 return checksum; 1650 } 1651 1652 static void rx_bottom(struct r8152 *tp) 1653 { 1654 unsigned long flags; 1655 struct list_head *cursor, *next, rx_queue; 1656 1657 if (list_empty(&tp->rx_done)) 1658 return; 1659 1660 INIT_LIST_HEAD(&rx_queue); 1661 spin_lock_irqsave(&tp->rx_lock, flags); 1662 list_splice_init(&tp->rx_done, &rx_queue); 1663 spin_unlock_irqrestore(&tp->rx_lock, flags); 1664 1665 list_for_each_safe(cursor, next, &rx_queue) { 1666 struct rx_desc *rx_desc; 1667 struct rx_agg *agg; 1668 int len_used = 0; 1669 struct urb *urb; 1670 u8 *rx_data; 1671 1672 list_del_init(cursor); 1673 1674 agg = list_entry(cursor, struct rx_agg, list); 1675 urb = agg->urb; 1676 if (urb->actual_length < ETH_ZLEN) 1677 goto submit; 1678 1679 rx_desc = agg->head; 1680 rx_data = agg->head; 1681 len_used += sizeof(struct rx_desc); 1682 1683 while (urb->actual_length > len_used) { 1684 struct net_device *netdev = tp->netdev; 1685 struct net_device_stats *stats = &netdev->stats; 1686 unsigned int pkt_len; 1687 struct sk_buff *skb; 1688 1689 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1690 if (pkt_len < ETH_ZLEN) 1691 break; 1692 1693 len_used += pkt_len; 1694 if (urb->actual_length < len_used) 1695 break; 1696 1697 pkt_len -= CRC_SIZE; 1698 rx_data += sizeof(struct rx_desc); 1699 1700 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1701 if (!skb) { 1702 stats->rx_dropped++; 1703 goto find_next_rx; 1704 } 1705 1706 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1707 memcpy(skb->data, rx_data, pkt_len); 1708 skb_put(skb, pkt_len); 1709 skb->protocol = eth_type_trans(skb, netdev); 1710 rtl_rx_vlan_tag(rx_desc, skb); 1711 netif_receive_skb(skb); 1712 stats->rx_packets++; 1713 stats->rx_bytes += pkt_len; 1714 1715 find_next_rx: 1716 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1717 rx_desc = (struct rx_desc *)rx_data; 1718 len_used = (int)(rx_data - (u8 *)agg->head); 1719 len_used += sizeof(struct rx_desc); 1720 } 1721 1722 submit: 1723 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1724 } 1725 } 1726 1727 static void tx_bottom(struct r8152 *tp) 1728 { 1729 int res; 1730 1731 do { 1732 struct tx_agg *agg; 1733 1734 if (skb_queue_empty(&tp->tx_queue)) 1735 break; 1736 1737 agg = r8152_get_tx_agg(tp); 1738 if (!agg) 1739 break; 1740 1741 res = r8152_tx_agg_fill(tp, agg); 1742 if (res) { 1743 struct net_device *netdev = tp->netdev; 1744 1745 if (res == -ENODEV) { 1746 set_bit(RTL8152_UNPLUG, &tp->flags); 1747 netif_device_detach(netdev); 1748 } else { 1749 struct net_device_stats *stats = &netdev->stats; 1750 unsigned long flags; 1751 1752 netif_warn(tp, tx_err, netdev, 1753 "failed tx_urb %d\n", res); 1754 stats->tx_dropped += agg->skb_num; 1755 1756 spin_lock_irqsave(&tp->tx_lock, flags); 1757 list_add_tail(&agg->list, &tp->tx_free); 1758 spin_unlock_irqrestore(&tp->tx_lock, flags); 1759 } 1760 } 1761 } while (res == 0); 1762 } 1763 1764 static void bottom_half(unsigned long data) 1765 { 1766 struct r8152 *tp; 1767 1768 tp = (struct r8152 *)data; 1769 1770 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1771 return; 1772 1773 if (!test_bit(WORK_ENABLE, &tp->flags)) 1774 return; 1775 1776 /* When link down, the driver would cancel all bulks. */ 1777 /* This avoid the re-submitting bulk */ 1778 if (!netif_carrier_ok(tp->netdev)) 1779 return; 1780 1781 clear_bit(SCHEDULE_TASKLET, &tp->flags); 1782 1783 rx_bottom(tp); 1784 tx_bottom(tp); 1785 } 1786 1787 static 1788 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1789 { 1790 int ret; 1791 1792 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1793 agg->head, agg_buf_sz, 1794 (usb_complete_t)read_bulk_callback, agg); 1795 1796 ret = usb_submit_urb(agg->urb, mem_flags); 1797 if (ret == -ENODEV) { 1798 set_bit(RTL8152_UNPLUG, &tp->flags); 1799 netif_device_detach(tp->netdev); 1800 } else if (ret) { 1801 struct urb *urb = agg->urb; 1802 unsigned long flags; 1803 1804 urb->actual_length = 0; 1805 spin_lock_irqsave(&tp->rx_lock, flags); 1806 list_add_tail(&agg->list, &tp->rx_done); 1807 spin_unlock_irqrestore(&tp->rx_lock, flags); 1808 tasklet_schedule(&tp->tl); 1809 } 1810 1811 return ret; 1812 } 1813 1814 static void rtl_drop_queued_tx(struct r8152 *tp) 1815 { 1816 struct net_device_stats *stats = &tp->netdev->stats; 1817 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1818 struct sk_buff *skb; 1819 1820 if (skb_queue_empty(tx_queue)) 1821 return; 1822 1823 __skb_queue_head_init(&skb_head); 1824 spin_lock_bh(&tx_queue->lock); 1825 skb_queue_splice_init(tx_queue, &skb_head); 1826 spin_unlock_bh(&tx_queue->lock); 1827 1828 while ((skb = __skb_dequeue(&skb_head))) { 1829 dev_kfree_skb(skb); 1830 stats->tx_dropped++; 1831 } 1832 } 1833 1834 static void rtl8152_tx_timeout(struct net_device *netdev) 1835 { 1836 struct r8152 *tp = netdev_priv(netdev); 1837 int i; 1838 1839 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1840 for (i = 0; i < RTL8152_MAX_TX; i++) 1841 usb_unlink_urb(tp->tx_info[i].urb); 1842 } 1843 1844 static void rtl8152_set_rx_mode(struct net_device *netdev) 1845 { 1846 struct r8152 *tp = netdev_priv(netdev); 1847 1848 if (tp->speed & LINK_STATUS) { 1849 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1850 schedule_delayed_work(&tp->schedule, 0); 1851 } 1852 } 1853 1854 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1855 { 1856 struct r8152 *tp = netdev_priv(netdev); 1857 u32 mc_filter[2]; /* Multicast hash filter */ 1858 __le32 tmp[2]; 1859 u32 ocp_data; 1860 1861 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1862 netif_stop_queue(netdev); 1863 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1864 ocp_data &= ~RCR_ACPT_ALL; 1865 ocp_data |= RCR_AB | RCR_APM; 1866 1867 if (netdev->flags & IFF_PROMISC) { 1868 /* Unconditionally log net taps. */ 1869 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1870 ocp_data |= RCR_AM | RCR_AAP; 1871 mc_filter[1] = 0xffffffff; 1872 mc_filter[0] = 0xffffffff; 1873 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1874 (netdev->flags & IFF_ALLMULTI)) { 1875 /* Too many to filter perfectly -- accept all multicasts. */ 1876 ocp_data |= RCR_AM; 1877 mc_filter[1] = 0xffffffff; 1878 mc_filter[0] = 0xffffffff; 1879 } else { 1880 struct netdev_hw_addr *ha; 1881 1882 mc_filter[1] = 0; 1883 mc_filter[0] = 0; 1884 netdev_for_each_mc_addr(ha, netdev) { 1885 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1886 1887 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1888 ocp_data |= RCR_AM; 1889 } 1890 } 1891 1892 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1893 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1894 1895 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1896 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1897 netif_wake_queue(netdev); 1898 } 1899 1900 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1901 struct net_device *netdev) 1902 { 1903 struct r8152 *tp = netdev_priv(netdev); 1904 1905 skb_tx_timestamp(skb); 1906 1907 skb_queue_tail(&tp->tx_queue, skb); 1908 1909 if (!list_empty(&tp->tx_free)) { 1910 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 1911 set_bit(SCHEDULE_TASKLET, &tp->flags); 1912 schedule_delayed_work(&tp->schedule, 0); 1913 } else { 1914 usb_mark_last_busy(tp->udev); 1915 tasklet_schedule(&tp->tl); 1916 } 1917 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 1918 netif_stop_queue(netdev); 1919 } 1920 1921 return NETDEV_TX_OK; 1922 } 1923 1924 static void r8152b_reset_packet_filter(struct r8152 *tp) 1925 { 1926 u32 ocp_data; 1927 1928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1929 ocp_data &= ~FMC_FCR_MCU_EN; 1930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1931 ocp_data |= FMC_FCR_MCU_EN; 1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1933 } 1934 1935 static void rtl8152_nic_reset(struct r8152 *tp) 1936 { 1937 int i; 1938 1939 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1940 1941 for (i = 0; i < 1000; i++) { 1942 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1943 break; 1944 usleep_range(100, 400); 1945 } 1946 } 1947 1948 static void set_tx_qlen(struct r8152 *tp) 1949 { 1950 struct net_device *netdev = tp->netdev; 1951 1952 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 1953 sizeof(struct tx_desc)); 1954 } 1955 1956 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1957 { 1958 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1959 } 1960 1961 static void rtl_set_eee_plus(struct r8152 *tp) 1962 { 1963 u32 ocp_data; 1964 u8 speed; 1965 1966 speed = rtl8152_get_speed(tp); 1967 if (speed & _10bps) { 1968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1969 ocp_data |= EEEP_CR_EEEP_TX; 1970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1971 } else { 1972 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1973 ocp_data &= ~EEEP_CR_EEEP_TX; 1974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1975 } 1976 } 1977 1978 static void rxdy_gated_en(struct r8152 *tp, bool enable) 1979 { 1980 u32 ocp_data; 1981 1982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1983 if (enable) 1984 ocp_data |= RXDY_GATED_EN; 1985 else 1986 ocp_data &= ~RXDY_GATED_EN; 1987 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1988 } 1989 1990 static int rtl_start_rx(struct r8152 *tp) 1991 { 1992 int i, ret = 0; 1993 1994 INIT_LIST_HEAD(&tp->rx_done); 1995 for (i = 0; i < RTL8152_MAX_RX; i++) { 1996 INIT_LIST_HEAD(&tp->rx_info[i].list); 1997 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1998 if (ret) 1999 break; 2000 } 2001 2002 if (ret && ++i < RTL8152_MAX_RX) { 2003 struct list_head rx_queue; 2004 unsigned long flags; 2005 2006 INIT_LIST_HEAD(&rx_queue); 2007 2008 do { 2009 struct rx_agg *agg = &tp->rx_info[i++]; 2010 struct urb *urb = agg->urb; 2011 2012 urb->actual_length = 0; 2013 list_add_tail(&agg->list, &rx_queue); 2014 } while (i < RTL8152_MAX_RX); 2015 2016 spin_lock_irqsave(&tp->rx_lock, flags); 2017 list_splice_tail(&rx_queue, &tp->rx_done); 2018 spin_unlock_irqrestore(&tp->rx_lock, flags); 2019 } 2020 2021 return ret; 2022 } 2023 2024 static int rtl_stop_rx(struct r8152 *tp) 2025 { 2026 int i; 2027 2028 for (i = 0; i < RTL8152_MAX_RX; i++) 2029 usb_kill_urb(tp->rx_info[i].urb); 2030 2031 return 0; 2032 } 2033 2034 static int rtl_enable(struct r8152 *tp) 2035 { 2036 u32 ocp_data; 2037 2038 r8152b_reset_packet_filter(tp); 2039 2040 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2041 ocp_data |= CR_RE | CR_TE; 2042 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2043 2044 rxdy_gated_en(tp, false); 2045 2046 return rtl_start_rx(tp); 2047 } 2048 2049 static int rtl8152_enable(struct r8152 *tp) 2050 { 2051 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2052 return -ENODEV; 2053 2054 set_tx_qlen(tp); 2055 rtl_set_eee_plus(tp); 2056 2057 return rtl_enable(tp); 2058 } 2059 2060 static void r8153_set_rx_agg(struct r8152 *tp) 2061 { 2062 u8 speed; 2063 2064 speed = rtl8152_get_speed(tp); 2065 if (speed & _1000bps) { 2066 if (tp->udev->speed == USB_SPEED_SUPER) { 2067 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 2068 RX_THR_SUPPER); 2069 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2070 EARLY_AGG_SUPPER); 2071 } else { 2072 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 2073 RX_THR_HIGH); 2074 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2075 EARLY_AGG_HIGH); 2076 } 2077 } else { 2078 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); 2079 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2080 EARLY_AGG_SLOW); 2081 } 2082 } 2083 2084 static int rtl8153_enable(struct r8152 *tp) 2085 { 2086 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2087 return -ENODEV; 2088 2089 set_tx_qlen(tp); 2090 rtl_set_eee_plus(tp); 2091 r8153_set_rx_agg(tp); 2092 2093 return rtl_enable(tp); 2094 } 2095 2096 static void rtl_disable(struct r8152 *tp) 2097 { 2098 u32 ocp_data; 2099 int i; 2100 2101 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2102 rtl_drop_queued_tx(tp); 2103 return; 2104 } 2105 2106 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2107 ocp_data &= ~RCR_ACPT_ALL; 2108 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2109 2110 rtl_drop_queued_tx(tp); 2111 2112 for (i = 0; i < RTL8152_MAX_TX; i++) 2113 usb_kill_urb(tp->tx_info[i].urb); 2114 2115 rxdy_gated_en(tp, true); 2116 2117 for (i = 0; i < 1000; i++) { 2118 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2119 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2120 break; 2121 usleep_range(1000, 2000); 2122 } 2123 2124 for (i = 0; i < 1000; i++) { 2125 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2126 break; 2127 usleep_range(1000, 2000); 2128 } 2129 2130 rtl_stop_rx(tp); 2131 2132 rtl8152_nic_reset(tp); 2133 } 2134 2135 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2136 { 2137 u32 ocp_data; 2138 2139 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2140 if (enable) 2141 ocp_data |= POWER_CUT; 2142 else 2143 ocp_data &= ~POWER_CUT; 2144 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2145 2146 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2147 ocp_data &= ~RESUME_INDICATE; 2148 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2149 } 2150 2151 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2152 { 2153 u32 ocp_data; 2154 2155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2156 if (enable) 2157 ocp_data |= CPCR_RX_VLAN; 2158 else 2159 ocp_data &= ~CPCR_RX_VLAN; 2160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2161 } 2162 2163 static int rtl8152_set_features(struct net_device *dev, 2164 netdev_features_t features) 2165 { 2166 netdev_features_t changed = features ^ dev->features; 2167 struct r8152 *tp = netdev_priv(dev); 2168 int ret; 2169 2170 ret = usb_autopm_get_interface(tp->intf); 2171 if (ret < 0) 2172 goto out; 2173 2174 mutex_lock(&tp->control); 2175 2176 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2177 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2178 rtl_rx_vlan_en(tp, true); 2179 else 2180 rtl_rx_vlan_en(tp, false); 2181 } 2182 2183 mutex_unlock(&tp->control); 2184 2185 usb_autopm_put_interface(tp->intf); 2186 2187 out: 2188 return ret; 2189 } 2190 2191 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2192 2193 static u32 __rtl_get_wol(struct r8152 *tp) 2194 { 2195 u32 ocp_data; 2196 u32 wolopts = 0; 2197 2198 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2199 if (!(ocp_data & LAN_WAKE_EN)) 2200 return 0; 2201 2202 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2203 if (ocp_data & LINK_ON_WAKE_EN) 2204 wolopts |= WAKE_PHY; 2205 2206 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2207 if (ocp_data & UWF_EN) 2208 wolopts |= WAKE_UCAST; 2209 if (ocp_data & BWF_EN) 2210 wolopts |= WAKE_BCAST; 2211 if (ocp_data & MWF_EN) 2212 wolopts |= WAKE_MCAST; 2213 2214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2215 if (ocp_data & MAGIC_EN) 2216 wolopts |= WAKE_MAGIC; 2217 2218 return wolopts; 2219 } 2220 2221 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2222 { 2223 u32 ocp_data; 2224 2225 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2226 2227 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2228 ocp_data &= ~LINK_ON_WAKE_EN; 2229 if (wolopts & WAKE_PHY) 2230 ocp_data |= LINK_ON_WAKE_EN; 2231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2232 2233 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2234 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2235 if (wolopts & WAKE_UCAST) 2236 ocp_data |= UWF_EN; 2237 if (wolopts & WAKE_BCAST) 2238 ocp_data |= BWF_EN; 2239 if (wolopts & WAKE_MCAST) 2240 ocp_data |= MWF_EN; 2241 if (wolopts & WAKE_ANY) 2242 ocp_data |= LAN_WAKE_EN; 2243 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2244 2245 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2246 2247 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2248 ocp_data &= ~MAGIC_EN; 2249 if (wolopts & WAKE_MAGIC) 2250 ocp_data |= MAGIC_EN; 2251 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2252 2253 if (wolopts & WAKE_ANY) 2254 device_set_wakeup_enable(&tp->udev->dev, true); 2255 else 2256 device_set_wakeup_enable(&tp->udev->dev, false); 2257 } 2258 2259 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2260 { 2261 if (enable) { 2262 u32 ocp_data; 2263 2264 __rtl_set_wol(tp, WAKE_ANY); 2265 2266 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2267 2268 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2269 ocp_data |= LINK_OFF_WAKE_EN; 2270 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2271 2272 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2273 } else { 2274 __rtl_set_wol(tp, tp->saved_wolopts); 2275 } 2276 } 2277 2278 static void rtl_phy_reset(struct r8152 *tp) 2279 { 2280 u16 data; 2281 int i; 2282 2283 clear_bit(PHY_RESET, &tp->flags); 2284 2285 data = r8152_mdio_read(tp, MII_BMCR); 2286 2287 /* don't reset again before the previous one complete */ 2288 if (data & BMCR_RESET) 2289 return; 2290 2291 data |= BMCR_RESET; 2292 r8152_mdio_write(tp, MII_BMCR, data); 2293 2294 for (i = 0; i < 50; i++) { 2295 msleep(20); 2296 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2297 break; 2298 } 2299 } 2300 2301 static void r8153_teredo_off(struct r8152 *tp) 2302 { 2303 u32 ocp_data; 2304 2305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2306 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2308 2309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2310 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2311 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2312 } 2313 2314 static void r8152b_disable_aldps(struct r8152 *tp) 2315 { 2316 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2317 msleep(20); 2318 } 2319 2320 static inline void r8152b_enable_aldps(struct r8152 *tp) 2321 { 2322 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2323 LINKENA | DIS_SDSAVE); 2324 } 2325 2326 static void rtl8152_disable(struct r8152 *tp) 2327 { 2328 r8152b_disable_aldps(tp); 2329 rtl_disable(tp); 2330 r8152b_enable_aldps(tp); 2331 } 2332 2333 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2334 { 2335 u16 data; 2336 2337 data = r8152_mdio_read(tp, MII_BMCR); 2338 if (data & BMCR_PDOWN) { 2339 data &= ~BMCR_PDOWN; 2340 r8152_mdio_write(tp, MII_BMCR, data); 2341 } 2342 2343 set_bit(PHY_RESET, &tp->flags); 2344 } 2345 2346 static void r8152b_exit_oob(struct r8152 *tp) 2347 { 2348 u32 ocp_data; 2349 int i; 2350 2351 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2352 ocp_data &= ~RCR_ACPT_ALL; 2353 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2354 2355 rxdy_gated_en(tp, true); 2356 r8153_teredo_off(tp); 2357 r8152b_hw_phy_cfg(tp); 2358 2359 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2360 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2361 2362 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2363 ocp_data &= ~NOW_IS_OOB; 2364 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2365 2366 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2367 ocp_data &= ~MCU_BORW_EN; 2368 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2369 2370 for (i = 0; i < 1000; i++) { 2371 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2372 if (ocp_data & LINK_LIST_READY) 2373 break; 2374 usleep_range(1000, 2000); 2375 } 2376 2377 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2378 ocp_data |= RE_INIT_LL; 2379 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2380 2381 for (i = 0; i < 1000; i++) { 2382 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2383 if (ocp_data & LINK_LIST_READY) 2384 break; 2385 usleep_range(1000, 2000); 2386 } 2387 2388 rtl8152_nic_reset(tp); 2389 2390 /* rx share fifo credit full threshold */ 2391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2392 2393 if (tp->udev->speed == USB_SPEED_FULL || 2394 tp->udev->speed == USB_SPEED_LOW) { 2395 /* rx share fifo credit near full threshold */ 2396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2397 RXFIFO_THR2_FULL); 2398 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2399 RXFIFO_THR3_FULL); 2400 } else { 2401 /* rx share fifo credit near full threshold */ 2402 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2403 RXFIFO_THR2_HIGH); 2404 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2405 RXFIFO_THR3_HIGH); 2406 } 2407 2408 /* TX share fifo free credit full threshold */ 2409 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2410 2411 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2412 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2413 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2414 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2415 2416 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2417 2418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2419 2420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2421 ocp_data |= TCR0_AUTO_FIFO; 2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2423 } 2424 2425 static void r8152b_enter_oob(struct r8152 *tp) 2426 { 2427 u32 ocp_data; 2428 int i; 2429 2430 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2431 ocp_data &= ~NOW_IS_OOB; 2432 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2433 2434 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2435 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2436 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2437 2438 rtl_disable(tp); 2439 2440 for (i = 0; i < 1000; i++) { 2441 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2442 if (ocp_data & LINK_LIST_READY) 2443 break; 2444 usleep_range(1000, 2000); 2445 } 2446 2447 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2448 ocp_data |= RE_INIT_LL; 2449 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2450 2451 for (i = 0; i < 1000; i++) { 2452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2453 if (ocp_data & LINK_LIST_READY) 2454 break; 2455 usleep_range(1000, 2000); 2456 } 2457 2458 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2459 2460 rtl_rx_vlan_en(tp, true); 2461 2462 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2463 ocp_data |= ALDPS_PROXY_MODE; 2464 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2465 2466 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2467 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2468 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2469 2470 rxdy_gated_en(tp, false); 2471 2472 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2473 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2474 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2475 } 2476 2477 static void r8153_hw_phy_cfg(struct r8152 *tp) 2478 { 2479 u32 ocp_data; 2480 u16 data; 2481 2482 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2483 data = r8152_mdio_read(tp, MII_BMCR); 2484 if (data & BMCR_PDOWN) { 2485 data &= ~BMCR_PDOWN; 2486 r8152_mdio_write(tp, MII_BMCR, data); 2487 } 2488 2489 if (tp->version == RTL_VER_03) { 2490 data = ocp_reg_read(tp, OCP_EEE_CFG); 2491 data &= ~CTAP_SHORT_EN; 2492 ocp_reg_write(tp, OCP_EEE_CFG, data); 2493 } 2494 2495 data = ocp_reg_read(tp, OCP_POWER_CFG); 2496 data |= EEE_CLKDIV_EN; 2497 ocp_reg_write(tp, OCP_POWER_CFG, data); 2498 2499 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2500 data |= EN_10M_BGOFF; 2501 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2502 data = ocp_reg_read(tp, OCP_POWER_CFG); 2503 data |= EN_10M_PLLOFF; 2504 ocp_reg_write(tp, OCP_POWER_CFG, data); 2505 data = sram_read(tp, SRAM_IMPEDANCE); 2506 data &= ~RX_DRIVING_MASK; 2507 sram_write(tp, SRAM_IMPEDANCE, data); 2508 2509 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2510 ocp_data |= PFM_PWM_SWITCH; 2511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2512 2513 data = sram_read(tp, SRAM_LPF_CFG); 2514 data |= LPF_AUTO_TUNE; 2515 sram_write(tp, SRAM_LPF_CFG, data); 2516 2517 data = sram_read(tp, SRAM_10M_AMP1); 2518 data |= GDAC_IB_UPALL; 2519 sram_write(tp, SRAM_10M_AMP1, data); 2520 data = sram_read(tp, SRAM_10M_AMP2); 2521 data |= AMP_DN; 2522 sram_write(tp, SRAM_10M_AMP2, data); 2523 2524 set_bit(PHY_RESET, &tp->flags); 2525 } 2526 2527 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2528 { 2529 u8 u1u2[8]; 2530 2531 if (enable) 2532 memset(u1u2, 0xff, sizeof(u1u2)); 2533 else 2534 memset(u1u2, 0x00, sizeof(u1u2)); 2535 2536 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2537 } 2538 2539 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2540 { 2541 u32 ocp_data; 2542 2543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2544 if (enable) 2545 ocp_data |= U2P3_ENABLE; 2546 else 2547 ocp_data &= ~U2P3_ENABLE; 2548 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2549 } 2550 2551 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2552 { 2553 u32 ocp_data; 2554 2555 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2556 if (enable) 2557 ocp_data |= PWR_EN | PHASE2_EN; 2558 else 2559 ocp_data &= ~(PWR_EN | PHASE2_EN); 2560 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2561 2562 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2563 ocp_data &= ~PCUT_STATUS; 2564 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2565 } 2566 2567 static void r8153_first_init(struct r8152 *tp) 2568 { 2569 u32 ocp_data; 2570 int i; 2571 2572 rxdy_gated_en(tp, true); 2573 r8153_teredo_off(tp); 2574 2575 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2576 ocp_data &= ~RCR_ACPT_ALL; 2577 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2578 2579 r8153_hw_phy_cfg(tp); 2580 2581 rtl8152_nic_reset(tp); 2582 2583 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2584 ocp_data &= ~NOW_IS_OOB; 2585 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2586 2587 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2588 ocp_data &= ~MCU_BORW_EN; 2589 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2590 2591 for (i = 0; i < 1000; i++) { 2592 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2593 if (ocp_data & LINK_LIST_READY) 2594 break; 2595 usleep_range(1000, 2000); 2596 } 2597 2598 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2599 ocp_data |= RE_INIT_LL; 2600 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2601 2602 for (i = 0; i < 1000; i++) { 2603 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2604 if (ocp_data & LINK_LIST_READY) 2605 break; 2606 usleep_range(1000, 2000); 2607 } 2608 2609 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2610 2611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2612 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2613 2614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2615 ocp_data |= TCR0_AUTO_FIFO; 2616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2617 2618 rtl8152_nic_reset(tp); 2619 2620 /* rx share fifo credit full threshold */ 2621 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2624 /* TX share fifo free credit full threshold */ 2625 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2626 2627 /* rx aggregation */ 2628 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2629 ocp_data &= ~RX_AGG_DISABLE; 2630 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2631 } 2632 2633 static void r8153_enter_oob(struct r8152 *tp) 2634 { 2635 u32 ocp_data; 2636 int i; 2637 2638 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2639 ocp_data &= ~NOW_IS_OOB; 2640 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2641 2642 rtl_disable(tp); 2643 2644 for (i = 0; i < 1000; i++) { 2645 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2646 if (ocp_data & LINK_LIST_READY) 2647 break; 2648 usleep_range(1000, 2000); 2649 } 2650 2651 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2652 ocp_data |= RE_INIT_LL; 2653 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2654 2655 for (i = 0; i < 1000; i++) { 2656 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2657 if (ocp_data & LINK_LIST_READY) 2658 break; 2659 usleep_range(1000, 2000); 2660 } 2661 2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2663 2664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2665 ocp_data &= ~TEREDO_WAKE_MASK; 2666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2667 2668 rtl_rx_vlan_en(tp, true); 2669 2670 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2671 ocp_data |= ALDPS_PROXY_MODE; 2672 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2673 2674 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2675 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2676 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2677 2678 rxdy_gated_en(tp, false); 2679 2680 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2681 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2682 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2683 } 2684 2685 static void r8153_disable_aldps(struct r8152 *tp) 2686 { 2687 u16 data; 2688 2689 data = ocp_reg_read(tp, OCP_POWER_CFG); 2690 data &= ~EN_ALDPS; 2691 ocp_reg_write(tp, OCP_POWER_CFG, data); 2692 msleep(20); 2693 } 2694 2695 static void r8153_enable_aldps(struct r8152 *tp) 2696 { 2697 u16 data; 2698 2699 data = ocp_reg_read(tp, OCP_POWER_CFG); 2700 data |= EN_ALDPS; 2701 ocp_reg_write(tp, OCP_POWER_CFG, data); 2702 } 2703 2704 static void rtl8153_disable(struct r8152 *tp) 2705 { 2706 r8153_disable_aldps(tp); 2707 rtl_disable(tp); 2708 r8153_enable_aldps(tp); 2709 } 2710 2711 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2712 { 2713 u16 bmcr, anar, gbcr; 2714 int ret = 0; 2715 2716 cancel_delayed_work_sync(&tp->schedule); 2717 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2718 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2719 ADVERTISE_100HALF | ADVERTISE_100FULL); 2720 if (tp->mii.supports_gmii) { 2721 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2722 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2723 } else { 2724 gbcr = 0; 2725 } 2726 2727 if (autoneg == AUTONEG_DISABLE) { 2728 if (speed == SPEED_10) { 2729 bmcr = 0; 2730 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2731 } else if (speed == SPEED_100) { 2732 bmcr = BMCR_SPEED100; 2733 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2734 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2735 bmcr = BMCR_SPEED1000; 2736 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2737 } else { 2738 ret = -EINVAL; 2739 goto out; 2740 } 2741 2742 if (duplex == DUPLEX_FULL) 2743 bmcr |= BMCR_FULLDPLX; 2744 } else { 2745 if (speed == SPEED_10) { 2746 if (duplex == DUPLEX_FULL) 2747 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2748 else 2749 anar |= ADVERTISE_10HALF; 2750 } else if (speed == SPEED_100) { 2751 if (duplex == DUPLEX_FULL) { 2752 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2753 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2754 } else { 2755 anar |= ADVERTISE_10HALF; 2756 anar |= ADVERTISE_100HALF; 2757 } 2758 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2759 if (duplex == DUPLEX_FULL) { 2760 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2761 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2762 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2763 } else { 2764 anar |= ADVERTISE_10HALF; 2765 anar |= ADVERTISE_100HALF; 2766 gbcr |= ADVERTISE_1000HALF; 2767 } 2768 } else { 2769 ret = -EINVAL; 2770 goto out; 2771 } 2772 2773 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2774 } 2775 2776 if (test_bit(PHY_RESET, &tp->flags)) 2777 bmcr |= BMCR_RESET; 2778 2779 if (tp->mii.supports_gmii) 2780 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2781 2782 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2783 r8152_mdio_write(tp, MII_BMCR, bmcr); 2784 2785 if (test_bit(PHY_RESET, &tp->flags)) { 2786 int i; 2787 2788 clear_bit(PHY_RESET, &tp->flags); 2789 for (i = 0; i < 50; i++) { 2790 msleep(20); 2791 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2792 break; 2793 } 2794 } 2795 2796 out: 2797 2798 return ret; 2799 } 2800 2801 static void rtl8152_up(struct r8152 *tp) 2802 { 2803 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2804 return; 2805 2806 r8152b_disable_aldps(tp); 2807 r8152b_exit_oob(tp); 2808 r8152b_enable_aldps(tp); 2809 } 2810 2811 static void rtl8152_down(struct r8152 *tp) 2812 { 2813 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2814 rtl_drop_queued_tx(tp); 2815 return; 2816 } 2817 2818 r8152_power_cut_en(tp, false); 2819 r8152b_disable_aldps(tp); 2820 r8152b_enter_oob(tp); 2821 r8152b_enable_aldps(tp); 2822 } 2823 2824 static void rtl8153_up(struct r8152 *tp) 2825 { 2826 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2827 return; 2828 2829 r8153_disable_aldps(tp); 2830 r8153_first_init(tp); 2831 r8153_enable_aldps(tp); 2832 } 2833 2834 static void rtl8153_down(struct r8152 *tp) 2835 { 2836 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2837 rtl_drop_queued_tx(tp); 2838 return; 2839 } 2840 2841 r8153_u1u2en(tp, false); 2842 r8153_power_cut_en(tp, false); 2843 r8153_disable_aldps(tp); 2844 r8153_enter_oob(tp); 2845 r8153_enable_aldps(tp); 2846 } 2847 2848 static void set_carrier(struct r8152 *tp) 2849 { 2850 struct net_device *netdev = tp->netdev; 2851 u8 speed; 2852 2853 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2854 speed = rtl8152_get_speed(tp); 2855 2856 if (speed & LINK_STATUS) { 2857 if (!(tp->speed & LINK_STATUS)) { 2858 tp->rtl_ops.enable(tp); 2859 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2860 netif_carrier_on(netdev); 2861 } 2862 } else { 2863 if (tp->speed & LINK_STATUS) { 2864 netif_carrier_off(netdev); 2865 tasklet_disable(&tp->tl); 2866 tp->rtl_ops.disable(tp); 2867 tasklet_enable(&tp->tl); 2868 } 2869 } 2870 tp->speed = speed; 2871 } 2872 2873 static void rtl_work_func_t(struct work_struct *work) 2874 { 2875 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 2876 2877 /* If the device is unplugged or !netif_running(), the workqueue 2878 * doesn't need to wake the device, and could return directly. 2879 */ 2880 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 2881 return; 2882 2883 if (usb_autopm_get_interface(tp->intf) < 0) 2884 return; 2885 2886 if (!test_bit(WORK_ENABLE, &tp->flags)) 2887 goto out1; 2888 2889 if (!mutex_trylock(&tp->control)) { 2890 schedule_delayed_work(&tp->schedule, 0); 2891 goto out1; 2892 } 2893 2894 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 2895 set_carrier(tp); 2896 2897 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 2898 _rtl8152_set_rx_mode(tp->netdev); 2899 2900 if (test_bit(SCHEDULE_TASKLET, &tp->flags) && 2901 (tp->speed & LINK_STATUS)) { 2902 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2903 tasklet_schedule(&tp->tl); 2904 } 2905 2906 if (test_bit(PHY_RESET, &tp->flags)) 2907 rtl_phy_reset(tp); 2908 2909 mutex_unlock(&tp->control); 2910 2911 out1: 2912 usb_autopm_put_interface(tp->intf); 2913 } 2914 2915 static int rtl8152_open(struct net_device *netdev) 2916 { 2917 struct r8152 *tp = netdev_priv(netdev); 2918 int res = 0; 2919 2920 res = alloc_all_mem(tp); 2921 if (res) 2922 goto out; 2923 2924 /* set speed to 0 to avoid autoresume try to submit rx */ 2925 tp->speed = 0; 2926 2927 res = usb_autopm_get_interface(tp->intf); 2928 if (res < 0) { 2929 free_all_mem(tp); 2930 goto out; 2931 } 2932 2933 mutex_lock(&tp->control); 2934 2935 /* The WORK_ENABLE may be set when autoresume occurs */ 2936 if (test_bit(WORK_ENABLE, &tp->flags)) { 2937 clear_bit(WORK_ENABLE, &tp->flags); 2938 usb_kill_urb(tp->intr_urb); 2939 cancel_delayed_work_sync(&tp->schedule); 2940 2941 /* disable the tx/rx, if the workqueue has enabled them. */ 2942 if (tp->speed & LINK_STATUS) 2943 tp->rtl_ops.disable(tp); 2944 } 2945 2946 tp->rtl_ops.up(tp); 2947 2948 rtl8152_set_speed(tp, AUTONEG_ENABLE, 2949 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 2950 DUPLEX_FULL); 2951 tp->speed = 0; 2952 netif_carrier_off(netdev); 2953 netif_start_queue(netdev); 2954 set_bit(WORK_ENABLE, &tp->flags); 2955 2956 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 2957 if (res) { 2958 if (res == -ENODEV) 2959 netif_device_detach(tp->netdev); 2960 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 2961 res); 2962 free_all_mem(tp); 2963 } else { 2964 tasklet_enable(&tp->tl); 2965 } 2966 2967 mutex_unlock(&tp->control); 2968 2969 usb_autopm_put_interface(tp->intf); 2970 2971 out: 2972 return res; 2973 } 2974 2975 static int rtl8152_close(struct net_device *netdev) 2976 { 2977 struct r8152 *tp = netdev_priv(netdev); 2978 int res = 0; 2979 2980 tasklet_disable(&tp->tl); 2981 clear_bit(WORK_ENABLE, &tp->flags); 2982 usb_kill_urb(tp->intr_urb); 2983 cancel_delayed_work_sync(&tp->schedule); 2984 netif_stop_queue(netdev); 2985 2986 res = usb_autopm_get_interface(tp->intf); 2987 if (res < 0) { 2988 rtl_drop_queued_tx(tp); 2989 } else { 2990 mutex_lock(&tp->control); 2991 2992 /* The autosuspend may have been enabled and wouldn't 2993 * be disable when autoresume occurs, because the 2994 * netif_running() would be false. 2995 */ 2996 rtl_runtime_suspend_enable(tp, false); 2997 2998 tp->rtl_ops.down(tp); 2999 3000 mutex_unlock(&tp->control); 3001 3002 usb_autopm_put_interface(tp->intf); 3003 } 3004 3005 free_all_mem(tp); 3006 3007 return res; 3008 } 3009 3010 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3011 { 3012 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3013 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3014 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3015 } 3016 3017 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3018 { 3019 u16 data; 3020 3021 r8152_mmd_indirect(tp, dev, reg); 3022 data = ocp_reg_read(tp, OCP_EEE_DATA); 3023 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3024 3025 return data; 3026 } 3027 3028 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3029 { 3030 r8152_mmd_indirect(tp, dev, reg); 3031 ocp_reg_write(tp, OCP_EEE_DATA, data); 3032 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3033 } 3034 3035 static void r8152_eee_en(struct r8152 *tp, bool enable) 3036 { 3037 u16 config1, config2, config3; 3038 u32 ocp_data; 3039 3040 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3041 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3042 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3043 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3044 3045 if (enable) { 3046 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3047 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3048 config1 |= sd_rise_time(1); 3049 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3050 config3 |= fast_snr(42); 3051 } else { 3052 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3053 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3054 RX_QUIET_EN); 3055 config1 |= sd_rise_time(7); 3056 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3057 config3 |= fast_snr(511); 3058 } 3059 3060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3061 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3062 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3063 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3064 } 3065 3066 static void r8152b_enable_eee(struct r8152 *tp) 3067 { 3068 r8152_eee_en(tp, true); 3069 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3070 } 3071 3072 static void r8153_eee_en(struct r8152 *tp, bool enable) 3073 { 3074 u32 ocp_data; 3075 u16 config; 3076 3077 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3078 config = ocp_reg_read(tp, OCP_EEE_CFG); 3079 3080 if (enable) { 3081 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3082 config |= EEE10_EN; 3083 } else { 3084 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3085 config &= ~EEE10_EN; 3086 } 3087 3088 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3089 ocp_reg_write(tp, OCP_EEE_CFG, config); 3090 } 3091 3092 static void r8153_enable_eee(struct r8152 *tp) 3093 { 3094 r8153_eee_en(tp, true); 3095 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3096 } 3097 3098 static void r8152b_enable_fc(struct r8152 *tp) 3099 { 3100 u16 anar; 3101 3102 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3103 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3104 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3105 } 3106 3107 static void rtl_tally_reset(struct r8152 *tp) 3108 { 3109 u32 ocp_data; 3110 3111 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3112 ocp_data |= TALLY_RESET; 3113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3114 } 3115 3116 static void r8152b_init(struct r8152 *tp) 3117 { 3118 u32 ocp_data; 3119 3120 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3121 return; 3122 3123 r8152b_disable_aldps(tp); 3124 3125 if (tp->version == RTL_VER_01) { 3126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3127 ocp_data &= ~LED_MODE_MASK; 3128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3129 } 3130 3131 r8152_power_cut_en(tp, false); 3132 3133 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3134 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3135 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3136 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3137 ocp_data &= ~MCU_CLK_RATIO_MASK; 3138 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3139 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3140 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3141 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3142 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3143 3144 r8152b_enable_eee(tp); 3145 r8152b_enable_aldps(tp); 3146 r8152b_enable_fc(tp); 3147 rtl_tally_reset(tp); 3148 3149 /* enable rx aggregation */ 3150 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3151 ocp_data &= ~RX_AGG_DISABLE; 3152 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3153 } 3154 3155 static void r8153_init(struct r8152 *tp) 3156 { 3157 u32 ocp_data; 3158 int i; 3159 3160 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3161 return; 3162 3163 r8153_disable_aldps(tp); 3164 r8153_u1u2en(tp, false); 3165 3166 for (i = 0; i < 500; i++) { 3167 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3168 AUTOLOAD_DONE) 3169 break; 3170 msleep(20); 3171 } 3172 3173 for (i = 0; i < 500; i++) { 3174 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3175 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3176 break; 3177 msleep(20); 3178 } 3179 3180 r8153_u2p3en(tp, false); 3181 3182 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3183 ocp_data &= ~TIMER11_EN; 3184 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3185 3186 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3187 ocp_data &= ~LED_MODE_MASK; 3188 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3189 3190 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); 3191 ocp_data &= ~LPM_TIMER_MASK; 3192 if (tp->udev->speed == USB_SPEED_SUPER) 3193 ocp_data |= LPM_TIMER_500US; 3194 else 3195 ocp_data |= LPM_TIMER_500MS; 3196 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3197 3198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3199 ocp_data &= ~SEN_VAL_MASK; 3200 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3201 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3202 3203 r8153_power_cut_en(tp, false); 3204 r8153_u1u2en(tp, true); 3205 3206 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3207 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3208 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3209 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3210 U1U2_SPDWN_EN | L1_SPDWN_EN); 3211 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3212 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3213 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3214 EEE_SPDWN_EN); 3215 3216 r8153_enable_eee(tp); 3217 r8153_enable_aldps(tp); 3218 r8152b_enable_fc(tp); 3219 rtl_tally_reset(tp); 3220 } 3221 3222 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3223 { 3224 struct r8152 *tp = usb_get_intfdata(intf); 3225 struct net_device *netdev = tp->netdev; 3226 int ret = 0; 3227 3228 mutex_lock(&tp->control); 3229 3230 if (PMSG_IS_AUTO(message)) { 3231 if (netif_running(netdev) && work_busy(&tp->schedule.work)) { 3232 ret = -EBUSY; 3233 goto out1; 3234 } 3235 3236 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3237 } else { 3238 netif_device_detach(netdev); 3239 } 3240 3241 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3242 clear_bit(WORK_ENABLE, &tp->flags); 3243 usb_kill_urb(tp->intr_urb); 3244 tasklet_disable(&tp->tl); 3245 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3246 rtl_stop_rx(tp); 3247 rtl_runtime_suspend_enable(tp, true); 3248 } else { 3249 cancel_delayed_work_sync(&tp->schedule); 3250 tp->rtl_ops.down(tp); 3251 } 3252 tasklet_enable(&tp->tl); 3253 } 3254 out1: 3255 mutex_unlock(&tp->control); 3256 3257 return ret; 3258 } 3259 3260 static int rtl8152_resume(struct usb_interface *intf) 3261 { 3262 struct r8152 *tp = usb_get_intfdata(intf); 3263 3264 mutex_lock(&tp->control); 3265 3266 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3267 tp->rtl_ops.init(tp); 3268 netif_device_attach(tp->netdev); 3269 } 3270 3271 if (netif_running(tp->netdev)) { 3272 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3273 rtl_runtime_suspend_enable(tp, false); 3274 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3275 set_bit(WORK_ENABLE, &tp->flags); 3276 if (tp->speed & LINK_STATUS) 3277 rtl_start_rx(tp); 3278 } else { 3279 tp->rtl_ops.up(tp); 3280 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3281 tp->mii.supports_gmii ? 3282 SPEED_1000 : SPEED_100, 3283 DUPLEX_FULL); 3284 tp->speed = 0; 3285 netif_carrier_off(tp->netdev); 3286 set_bit(WORK_ENABLE, &tp->flags); 3287 } 3288 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3289 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3290 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3291 } 3292 3293 mutex_unlock(&tp->control); 3294 3295 return 0; 3296 } 3297 3298 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3299 { 3300 struct r8152 *tp = netdev_priv(dev); 3301 3302 if (usb_autopm_get_interface(tp->intf) < 0) 3303 return; 3304 3305 mutex_lock(&tp->control); 3306 3307 wol->supported = WAKE_ANY; 3308 wol->wolopts = __rtl_get_wol(tp); 3309 3310 mutex_unlock(&tp->control); 3311 3312 usb_autopm_put_interface(tp->intf); 3313 } 3314 3315 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3316 { 3317 struct r8152 *tp = netdev_priv(dev); 3318 int ret; 3319 3320 ret = usb_autopm_get_interface(tp->intf); 3321 if (ret < 0) 3322 goto out_set_wol; 3323 3324 mutex_lock(&tp->control); 3325 3326 __rtl_set_wol(tp, wol->wolopts); 3327 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3328 3329 mutex_unlock(&tp->control); 3330 3331 usb_autopm_put_interface(tp->intf); 3332 3333 out_set_wol: 3334 return ret; 3335 } 3336 3337 static u32 rtl8152_get_msglevel(struct net_device *dev) 3338 { 3339 struct r8152 *tp = netdev_priv(dev); 3340 3341 return tp->msg_enable; 3342 } 3343 3344 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3345 { 3346 struct r8152 *tp = netdev_priv(dev); 3347 3348 tp->msg_enable = value; 3349 } 3350 3351 static void rtl8152_get_drvinfo(struct net_device *netdev, 3352 struct ethtool_drvinfo *info) 3353 { 3354 struct r8152 *tp = netdev_priv(netdev); 3355 3356 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3357 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3358 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3359 } 3360 3361 static 3362 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3363 { 3364 struct r8152 *tp = netdev_priv(netdev); 3365 int ret; 3366 3367 if (!tp->mii.mdio_read) 3368 return -EOPNOTSUPP; 3369 3370 ret = usb_autopm_get_interface(tp->intf); 3371 if (ret < 0) 3372 goto out; 3373 3374 mutex_lock(&tp->control); 3375 3376 ret = mii_ethtool_gset(&tp->mii, cmd); 3377 3378 mutex_unlock(&tp->control); 3379 3380 usb_autopm_put_interface(tp->intf); 3381 3382 out: 3383 return ret; 3384 } 3385 3386 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3387 { 3388 struct r8152 *tp = netdev_priv(dev); 3389 int ret; 3390 3391 ret = usb_autopm_get_interface(tp->intf); 3392 if (ret < 0) 3393 goto out; 3394 3395 mutex_lock(&tp->control); 3396 3397 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3398 3399 mutex_unlock(&tp->control); 3400 3401 usb_autopm_put_interface(tp->intf); 3402 3403 out: 3404 return ret; 3405 } 3406 3407 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3408 "tx_packets", 3409 "rx_packets", 3410 "tx_errors", 3411 "rx_errors", 3412 "rx_missed", 3413 "align_errors", 3414 "tx_single_collisions", 3415 "tx_multi_collisions", 3416 "rx_unicast", 3417 "rx_broadcast", 3418 "rx_multicast", 3419 "tx_aborted", 3420 "tx_underrun", 3421 }; 3422 3423 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3424 { 3425 switch (sset) { 3426 case ETH_SS_STATS: 3427 return ARRAY_SIZE(rtl8152_gstrings); 3428 default: 3429 return -EOPNOTSUPP; 3430 } 3431 } 3432 3433 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3434 struct ethtool_stats *stats, u64 *data) 3435 { 3436 struct r8152 *tp = netdev_priv(dev); 3437 struct tally_counter tally; 3438 3439 if (usb_autopm_get_interface(tp->intf) < 0) 3440 return; 3441 3442 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3443 3444 usb_autopm_put_interface(tp->intf); 3445 3446 data[0] = le64_to_cpu(tally.tx_packets); 3447 data[1] = le64_to_cpu(tally.rx_packets); 3448 data[2] = le64_to_cpu(tally.tx_errors); 3449 data[3] = le32_to_cpu(tally.rx_errors); 3450 data[4] = le16_to_cpu(tally.rx_missed); 3451 data[5] = le16_to_cpu(tally.align_errors); 3452 data[6] = le32_to_cpu(tally.tx_one_collision); 3453 data[7] = le32_to_cpu(tally.tx_multi_collision); 3454 data[8] = le64_to_cpu(tally.rx_unicast); 3455 data[9] = le64_to_cpu(tally.rx_broadcast); 3456 data[10] = le32_to_cpu(tally.rx_multicast); 3457 data[11] = le16_to_cpu(tally.tx_aborted); 3458 data[12] = le16_to_cpu(tally.tx_underrun); 3459 } 3460 3461 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3462 { 3463 switch (stringset) { 3464 case ETH_SS_STATS: 3465 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3466 break; 3467 } 3468 } 3469 3470 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3471 { 3472 u32 ocp_data, lp, adv, supported = 0; 3473 u16 val; 3474 3475 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3476 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3477 3478 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3479 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3480 3481 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3482 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3483 3484 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3485 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3486 3487 eee->eee_enabled = !!ocp_data; 3488 eee->eee_active = !!(supported & adv & lp); 3489 eee->supported = supported; 3490 eee->advertised = adv; 3491 eee->lp_advertised = lp; 3492 3493 return 0; 3494 } 3495 3496 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3497 { 3498 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3499 3500 r8152_eee_en(tp, eee->eee_enabled); 3501 3502 if (!eee->eee_enabled) 3503 val = 0; 3504 3505 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3506 3507 return 0; 3508 } 3509 3510 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3511 { 3512 u32 ocp_data, lp, adv, supported = 0; 3513 u16 val; 3514 3515 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3516 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3517 3518 val = ocp_reg_read(tp, OCP_EEE_ADV); 3519 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3520 3521 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3522 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3523 3524 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3525 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3526 3527 eee->eee_enabled = !!ocp_data; 3528 eee->eee_active = !!(supported & adv & lp); 3529 eee->supported = supported; 3530 eee->advertised = adv; 3531 eee->lp_advertised = lp; 3532 3533 return 0; 3534 } 3535 3536 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3537 { 3538 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3539 3540 r8153_eee_en(tp, eee->eee_enabled); 3541 3542 if (!eee->eee_enabled) 3543 val = 0; 3544 3545 ocp_reg_write(tp, OCP_EEE_ADV, val); 3546 3547 return 0; 3548 } 3549 3550 static int 3551 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3552 { 3553 struct r8152 *tp = netdev_priv(net); 3554 int ret; 3555 3556 ret = usb_autopm_get_interface(tp->intf); 3557 if (ret < 0) 3558 goto out; 3559 3560 mutex_lock(&tp->control); 3561 3562 ret = tp->rtl_ops.eee_get(tp, edata); 3563 3564 mutex_unlock(&tp->control); 3565 3566 usb_autopm_put_interface(tp->intf); 3567 3568 out: 3569 return ret; 3570 } 3571 3572 static int 3573 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3574 { 3575 struct r8152 *tp = netdev_priv(net); 3576 int ret; 3577 3578 ret = usb_autopm_get_interface(tp->intf); 3579 if (ret < 0) 3580 goto out; 3581 3582 mutex_lock(&tp->control); 3583 3584 ret = tp->rtl_ops.eee_set(tp, edata); 3585 if (!ret) 3586 ret = mii_nway_restart(&tp->mii); 3587 3588 mutex_unlock(&tp->control); 3589 3590 usb_autopm_put_interface(tp->intf); 3591 3592 out: 3593 return ret; 3594 } 3595 3596 static int rtl8152_nway_reset(struct net_device *dev) 3597 { 3598 struct r8152 *tp = netdev_priv(dev); 3599 int ret; 3600 3601 ret = usb_autopm_get_interface(tp->intf); 3602 if (ret < 0) 3603 goto out; 3604 3605 mutex_lock(&tp->control); 3606 3607 ret = mii_nway_restart(&tp->mii); 3608 3609 mutex_unlock(&tp->control); 3610 3611 usb_autopm_put_interface(tp->intf); 3612 3613 out: 3614 return ret; 3615 } 3616 3617 static struct ethtool_ops ops = { 3618 .get_drvinfo = rtl8152_get_drvinfo, 3619 .get_settings = rtl8152_get_settings, 3620 .set_settings = rtl8152_set_settings, 3621 .get_link = ethtool_op_get_link, 3622 .nway_reset = rtl8152_nway_reset, 3623 .get_msglevel = rtl8152_get_msglevel, 3624 .set_msglevel = rtl8152_set_msglevel, 3625 .get_wol = rtl8152_get_wol, 3626 .set_wol = rtl8152_set_wol, 3627 .get_strings = rtl8152_get_strings, 3628 .get_sset_count = rtl8152_get_sset_count, 3629 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3630 .get_eee = rtl_ethtool_get_eee, 3631 .set_eee = rtl_ethtool_set_eee, 3632 }; 3633 3634 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3635 { 3636 struct r8152 *tp = netdev_priv(netdev); 3637 struct mii_ioctl_data *data = if_mii(rq); 3638 int res; 3639 3640 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3641 return -ENODEV; 3642 3643 res = usb_autopm_get_interface(tp->intf); 3644 if (res < 0) 3645 goto out; 3646 3647 switch (cmd) { 3648 case SIOCGMIIPHY: 3649 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3650 break; 3651 3652 case SIOCGMIIREG: 3653 mutex_lock(&tp->control); 3654 data->val_out = r8152_mdio_read(tp, data->reg_num); 3655 mutex_unlock(&tp->control); 3656 break; 3657 3658 case SIOCSMIIREG: 3659 if (!capable(CAP_NET_ADMIN)) { 3660 res = -EPERM; 3661 break; 3662 } 3663 mutex_lock(&tp->control); 3664 r8152_mdio_write(tp, data->reg_num, data->val_in); 3665 mutex_unlock(&tp->control); 3666 break; 3667 3668 default: 3669 res = -EOPNOTSUPP; 3670 } 3671 3672 usb_autopm_put_interface(tp->intf); 3673 3674 out: 3675 return res; 3676 } 3677 3678 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 3679 { 3680 struct r8152 *tp = netdev_priv(dev); 3681 3682 switch (tp->version) { 3683 case RTL_VER_01: 3684 case RTL_VER_02: 3685 return eth_change_mtu(dev, new_mtu); 3686 default: 3687 break; 3688 } 3689 3690 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 3691 return -EINVAL; 3692 3693 dev->mtu = new_mtu; 3694 3695 return 0; 3696 } 3697 3698 static const struct net_device_ops rtl8152_netdev_ops = { 3699 .ndo_open = rtl8152_open, 3700 .ndo_stop = rtl8152_close, 3701 .ndo_do_ioctl = rtl8152_ioctl, 3702 .ndo_start_xmit = rtl8152_start_xmit, 3703 .ndo_tx_timeout = rtl8152_tx_timeout, 3704 .ndo_set_features = rtl8152_set_features, 3705 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3706 .ndo_set_mac_address = rtl8152_set_mac_address, 3707 .ndo_change_mtu = rtl8152_change_mtu, 3708 .ndo_validate_addr = eth_validate_addr, 3709 }; 3710 3711 static void r8152b_get_version(struct r8152 *tp) 3712 { 3713 u32 ocp_data; 3714 u16 version; 3715 3716 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3717 version = (u16)(ocp_data & VERSION_MASK); 3718 3719 switch (version) { 3720 case 0x4c00: 3721 tp->version = RTL_VER_01; 3722 break; 3723 case 0x4c10: 3724 tp->version = RTL_VER_02; 3725 break; 3726 case 0x5c00: 3727 tp->version = RTL_VER_03; 3728 tp->mii.supports_gmii = 1; 3729 break; 3730 case 0x5c10: 3731 tp->version = RTL_VER_04; 3732 tp->mii.supports_gmii = 1; 3733 break; 3734 case 0x5c20: 3735 tp->version = RTL_VER_05; 3736 tp->mii.supports_gmii = 1; 3737 break; 3738 default: 3739 netif_info(tp, probe, tp->netdev, 3740 "Unknown version 0x%04x\n", version); 3741 break; 3742 } 3743 } 3744 3745 static void rtl8152_unload(struct r8152 *tp) 3746 { 3747 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3748 return; 3749 3750 if (tp->version != RTL_VER_01) 3751 r8152_power_cut_en(tp, true); 3752 } 3753 3754 static void rtl8153_unload(struct r8152 *tp) 3755 { 3756 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3757 return; 3758 3759 r8153_power_cut_en(tp, false); 3760 } 3761 3762 static int rtl_ops_init(struct r8152 *tp) 3763 { 3764 struct rtl_ops *ops = &tp->rtl_ops; 3765 int ret = 0; 3766 3767 switch (tp->version) { 3768 case RTL_VER_01: 3769 case RTL_VER_02: 3770 ops->init = r8152b_init; 3771 ops->enable = rtl8152_enable; 3772 ops->disable = rtl8152_disable; 3773 ops->up = rtl8152_up; 3774 ops->down = rtl8152_down; 3775 ops->unload = rtl8152_unload; 3776 ops->eee_get = r8152_get_eee; 3777 ops->eee_set = r8152_set_eee; 3778 break; 3779 3780 case RTL_VER_03: 3781 case RTL_VER_04: 3782 case RTL_VER_05: 3783 ops->init = r8153_init; 3784 ops->enable = rtl8153_enable; 3785 ops->disable = rtl8153_disable; 3786 ops->up = rtl8153_up; 3787 ops->down = rtl8153_down; 3788 ops->unload = rtl8153_unload; 3789 ops->eee_get = r8153_get_eee; 3790 ops->eee_set = r8153_set_eee; 3791 break; 3792 3793 default: 3794 ret = -ENODEV; 3795 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 3796 break; 3797 } 3798 3799 return ret; 3800 } 3801 3802 static int rtl8152_probe(struct usb_interface *intf, 3803 const struct usb_device_id *id) 3804 { 3805 struct usb_device *udev = interface_to_usbdev(intf); 3806 struct r8152 *tp; 3807 struct net_device *netdev; 3808 int ret; 3809 3810 if (udev->actconfig->desc.bConfigurationValue != 1) { 3811 usb_driver_set_configuration(udev, 1); 3812 return -ENODEV; 3813 } 3814 3815 usb_reset_device(udev); 3816 netdev = alloc_etherdev(sizeof(struct r8152)); 3817 if (!netdev) { 3818 dev_err(&intf->dev, "Out of memory\n"); 3819 return -ENOMEM; 3820 } 3821 3822 SET_NETDEV_DEV(netdev, &intf->dev); 3823 tp = netdev_priv(netdev); 3824 tp->msg_enable = 0x7FFF; 3825 3826 tp->udev = udev; 3827 tp->netdev = netdev; 3828 tp->intf = intf; 3829 3830 r8152b_get_version(tp); 3831 ret = rtl_ops_init(tp); 3832 if (ret) 3833 goto out; 3834 3835 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 3836 mutex_init(&tp->control); 3837 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 3838 3839 netdev->netdev_ops = &rtl8152_netdev_ops; 3840 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 3841 3842 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3843 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 3844 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 3845 NETIF_F_HW_VLAN_CTAG_TX; 3846 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3847 NETIF_F_TSO | NETIF_F_FRAGLIST | 3848 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 3849 NETIF_F_HW_VLAN_CTAG_RX | 3850 NETIF_F_HW_VLAN_CTAG_TX; 3851 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 3852 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 3853 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 3854 3855 netdev->ethtool_ops = &ops; 3856 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 3857 3858 tp->mii.dev = netdev; 3859 tp->mii.mdio_read = read_mii_word; 3860 tp->mii.mdio_write = write_mii_word; 3861 tp->mii.phy_id_mask = 0x3f; 3862 tp->mii.reg_num_mask = 0x1f; 3863 tp->mii.phy_id = R8152_PHY_ID; 3864 3865 intf->needs_remote_wakeup = 1; 3866 3867 tp->rtl_ops.init(tp); 3868 set_ethernet_addr(tp); 3869 3870 usb_set_intfdata(intf, tp); 3871 3872 ret = register_netdev(netdev); 3873 if (ret != 0) { 3874 netif_err(tp, probe, netdev, "couldn't register the device\n"); 3875 goto out1; 3876 } 3877 3878 tp->saved_wolopts = __rtl_get_wol(tp); 3879 if (tp->saved_wolopts) 3880 device_set_wakeup_enable(&udev->dev, true); 3881 else 3882 device_set_wakeup_enable(&udev->dev, false); 3883 3884 tasklet_disable(&tp->tl); 3885 3886 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 3887 3888 return 0; 3889 3890 out1: 3891 usb_set_intfdata(intf, NULL); 3892 tasklet_kill(&tp->tl); 3893 out: 3894 free_netdev(netdev); 3895 return ret; 3896 } 3897 3898 static void rtl8152_disconnect(struct usb_interface *intf) 3899 { 3900 struct r8152 *tp = usb_get_intfdata(intf); 3901 3902 usb_set_intfdata(intf, NULL); 3903 if (tp) { 3904 struct usb_device *udev = tp->udev; 3905 3906 if (udev->state == USB_STATE_NOTATTACHED) 3907 set_bit(RTL8152_UNPLUG, &tp->flags); 3908 3909 tasklet_kill(&tp->tl); 3910 unregister_netdev(tp->netdev); 3911 tp->rtl_ops.unload(tp); 3912 free_netdev(tp->netdev); 3913 } 3914 } 3915 3916 #define REALTEK_USB_DEVICE(vend, prod) \ 3917 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 3918 USB_DEVICE_ID_MATCH_INT_CLASS, \ 3919 .idVendor = (vend), \ 3920 .idProduct = (prod), \ 3921 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 3922 }, \ 3923 { \ 3924 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 3925 USB_DEVICE_ID_MATCH_DEVICE, \ 3926 .idVendor = (vend), \ 3927 .idProduct = (prod), \ 3928 .bInterfaceClass = USB_CLASS_COMM, \ 3929 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 3930 .bInterfaceProtocol = USB_CDC_PROTO_NONE 3931 3932 /* table of devices that work with this driver */ 3933 static struct usb_device_id rtl8152_table[] = { 3934 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 3935 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 3936 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 3937 {} 3938 }; 3939 3940 MODULE_DEVICE_TABLE(usb, rtl8152_table); 3941 3942 static struct usb_driver rtl8152_driver = { 3943 .name = MODULENAME, 3944 .id_table = rtl8152_table, 3945 .probe = rtl8152_probe, 3946 .disconnect = rtl8152_disconnect, 3947 .suspend = rtl8152_suspend, 3948 .resume = rtl8152_resume, 3949 .reset_resume = rtl8152_resume, 3950 .supports_autosuspend = 1, 3951 .disable_hub_initiated_lpm = 1, 3952 }; 3953 3954 module_usb_driver(rtl8152_driver); 3955 3956 MODULE_AUTHOR(DRIVER_AUTHOR); 3957 MODULE_DESCRIPTION(DRIVER_DESC); 3958 MODULE_LICENSE("GPL"); 3959