1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 29 /* Version Information */ 30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)" 31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 33 #define MODULENAME "r8152" 34 35 #define R8152_PHY_ID 32 36 37 #define PLA_IDR 0xc000 38 #define PLA_RCR 0xc010 39 #define PLA_RMS 0xc016 40 #define PLA_RXFIFO_CTRL0 0xc0a0 41 #define PLA_RXFIFO_CTRL1 0xc0a4 42 #define PLA_RXFIFO_CTRL2 0xc0a8 43 #define PLA_DMY_REG0 0xc0b0 44 #define PLA_FMC 0xc0b4 45 #define PLA_CFG_WOL 0xc0b6 46 #define PLA_TEREDO_CFG 0xc0bc 47 #define PLA_MAR 0xcd00 48 #define PLA_BACKUP 0xd000 49 #define PAL_BDC_CR 0xd1a0 50 #define PLA_TEREDO_TIMER 0xd2cc 51 #define PLA_REALWOW_TIMER 0xd2e8 52 #define PLA_LEDSEL 0xdd90 53 #define PLA_LED_FEATURE 0xdd92 54 #define PLA_PHYAR 0xde00 55 #define PLA_BOOT_CTRL 0xe004 56 #define PLA_GPHY_INTR_IMR 0xe022 57 #define PLA_EEE_CR 0xe040 58 #define PLA_EEEP_CR 0xe080 59 #define PLA_MAC_PWR_CTRL 0xe0c0 60 #define PLA_MAC_PWR_CTRL2 0xe0ca 61 #define PLA_MAC_PWR_CTRL3 0xe0cc 62 #define PLA_MAC_PWR_CTRL4 0xe0ce 63 #define PLA_WDT6_CTRL 0xe428 64 #define PLA_TCR0 0xe610 65 #define PLA_TCR1 0xe612 66 #define PLA_MTPS 0xe615 67 #define PLA_TXFIFO_CTRL 0xe618 68 #define PLA_RSTTALLY 0xe800 69 #define PLA_CR 0xe813 70 #define PLA_CRWECR 0xe81c 71 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 72 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 73 #define PLA_CONFIG5 0xe822 74 #define PLA_PHY_PWR 0xe84c 75 #define PLA_OOB_CTRL 0xe84f 76 #define PLA_CPCR 0xe854 77 #define PLA_MISC_0 0xe858 78 #define PLA_MISC_1 0xe85a 79 #define PLA_OCP_GPHY_BASE 0xe86c 80 #define PLA_TALLYCNT 0xe890 81 #define PLA_SFF_STS_7 0xe8de 82 #define PLA_PHYSTATUS 0xe908 83 #define PLA_BP_BA 0xfc26 84 #define PLA_BP_0 0xfc28 85 #define PLA_BP_1 0xfc2a 86 #define PLA_BP_2 0xfc2c 87 #define PLA_BP_3 0xfc2e 88 #define PLA_BP_4 0xfc30 89 #define PLA_BP_5 0xfc32 90 #define PLA_BP_6 0xfc34 91 #define PLA_BP_7 0xfc36 92 #define PLA_BP_EN 0xfc38 93 94 #define USB_USB2PHY 0xb41e 95 #define USB_SSPHYLINK2 0xb428 96 #define USB_U2P3_CTRL 0xb460 97 #define USB_CSR_DUMMY1 0xb464 98 #define USB_CSR_DUMMY2 0xb466 99 #define USB_DEV_STAT 0xb808 100 #define USB_CONNECT_TIMER 0xcbf8 101 #define USB_BURST_SIZE 0xcfc0 102 #define USB_USB_CTRL 0xd406 103 #define USB_PHY_CTRL 0xd408 104 #define USB_TX_AGG 0xd40a 105 #define USB_RX_BUF_TH 0xd40c 106 #define USB_USB_TIMER 0xd428 107 #define USB_RX_EARLY_AGG 0xd42c 108 #define USB_PM_CTRL_STATUS 0xd432 109 #define USB_TX_DMA 0xd434 110 #define USB_TOLERANCE 0xd490 111 #define USB_LPM_CTRL 0xd41a 112 #define USB_UPS_CTRL 0xd800 113 #define USB_MISC_0 0xd81a 114 #define USB_POWER_CUT 0xd80a 115 #define USB_AFE_CTRL2 0xd824 116 #define USB_WDT11_CTRL 0xe43c 117 #define USB_BP_BA 0xfc26 118 #define USB_BP_0 0xfc28 119 #define USB_BP_1 0xfc2a 120 #define USB_BP_2 0xfc2c 121 #define USB_BP_3 0xfc2e 122 #define USB_BP_4 0xfc30 123 #define USB_BP_5 0xfc32 124 #define USB_BP_6 0xfc34 125 #define USB_BP_7 0xfc36 126 #define USB_BP_EN 0xfc38 127 128 /* OCP Registers */ 129 #define OCP_ALDPS_CONFIG 0x2010 130 #define OCP_EEE_CONFIG1 0x2080 131 #define OCP_EEE_CONFIG2 0x2092 132 #define OCP_EEE_CONFIG3 0x2094 133 #define OCP_BASE_MII 0xa400 134 #define OCP_EEE_AR 0xa41a 135 #define OCP_EEE_DATA 0xa41c 136 #define OCP_PHY_STATUS 0xa420 137 #define OCP_POWER_CFG 0xa430 138 #define OCP_EEE_CFG 0xa432 139 #define OCP_SRAM_ADDR 0xa436 140 #define OCP_SRAM_DATA 0xa438 141 #define OCP_DOWN_SPEED 0xa442 142 #define OCP_EEE_ABLE 0xa5c4 143 #define OCP_EEE_ADV 0xa5d0 144 #define OCP_EEE_LPABLE 0xa5d2 145 #define OCP_ADC_CFG 0xbc06 146 147 /* SRAM Register */ 148 #define SRAM_LPF_CFG 0x8012 149 #define SRAM_10M_AMP1 0x8080 150 #define SRAM_10M_AMP2 0x8082 151 #define SRAM_IMPEDANCE 0x8084 152 153 /* PLA_RCR */ 154 #define RCR_AAP 0x00000001 155 #define RCR_APM 0x00000002 156 #define RCR_AM 0x00000004 157 #define RCR_AB 0x00000008 158 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 159 160 /* PLA_RXFIFO_CTRL0 */ 161 #define RXFIFO_THR1_NORMAL 0x00080002 162 #define RXFIFO_THR1_OOB 0x01800003 163 164 /* PLA_RXFIFO_CTRL1 */ 165 #define RXFIFO_THR2_FULL 0x00000060 166 #define RXFIFO_THR2_HIGH 0x00000038 167 #define RXFIFO_THR2_OOB 0x0000004a 168 #define RXFIFO_THR2_NORMAL 0x00a0 169 170 /* PLA_RXFIFO_CTRL2 */ 171 #define RXFIFO_THR3_FULL 0x00000078 172 #define RXFIFO_THR3_HIGH 0x00000048 173 #define RXFIFO_THR3_OOB 0x0000005a 174 #define RXFIFO_THR3_NORMAL 0x0110 175 176 /* PLA_TXFIFO_CTRL */ 177 #define TXFIFO_THR_NORMAL 0x00400008 178 #define TXFIFO_THR_NORMAL2 0x01000008 179 180 /* PLA_DMY_REG0 */ 181 #define ECM_ALDPS 0x0002 182 183 /* PLA_FMC */ 184 #define FMC_FCR_MCU_EN 0x0001 185 186 /* PLA_EEEP_CR */ 187 #define EEEP_CR_EEEP_TX 0x0002 188 189 /* PLA_WDT6_CTRL */ 190 #define WDT6_SET_MODE 0x0010 191 192 /* PLA_TCR0 */ 193 #define TCR0_TX_EMPTY 0x0800 194 #define TCR0_AUTO_FIFO 0x0080 195 196 /* PLA_TCR1 */ 197 #define VERSION_MASK 0x7cf0 198 199 /* PLA_MTPS */ 200 #define MTPS_JUMBO (12 * 1024 / 64) 201 #define MTPS_DEFAULT (6 * 1024 / 64) 202 203 /* PLA_RSTTALLY */ 204 #define TALLY_RESET 0x0001 205 206 /* PLA_CR */ 207 #define CR_RST 0x10 208 #define CR_RE 0x08 209 #define CR_TE 0x04 210 211 /* PLA_CRWECR */ 212 #define CRWECR_NORAML 0x00 213 #define CRWECR_CONFIG 0xc0 214 215 /* PLA_OOB_CTRL */ 216 #define NOW_IS_OOB 0x80 217 #define TXFIFO_EMPTY 0x20 218 #define RXFIFO_EMPTY 0x10 219 #define LINK_LIST_READY 0x02 220 #define DIS_MCU_CLROOB 0x01 221 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 222 223 /* PLA_MISC_1 */ 224 #define RXDY_GATED_EN 0x0008 225 226 /* PLA_SFF_STS_7 */ 227 #define RE_INIT_LL 0x8000 228 #define MCU_BORW_EN 0x4000 229 230 /* PLA_CPCR */ 231 #define CPCR_RX_VLAN 0x0040 232 233 /* PLA_CFG_WOL */ 234 #define MAGIC_EN 0x0001 235 236 /* PLA_TEREDO_CFG */ 237 #define TEREDO_SEL 0x8000 238 #define TEREDO_WAKE_MASK 0x7f00 239 #define TEREDO_RS_EVENT_MASK 0x00fe 240 #define OOB_TEREDO_EN 0x0001 241 242 /* PAL_BDC_CR */ 243 #define ALDPS_PROXY_MODE 0x0001 244 245 /* PLA_CONFIG34 */ 246 #define LINK_ON_WAKE_EN 0x0010 247 #define LINK_OFF_WAKE_EN 0x0008 248 249 /* PLA_CONFIG5 */ 250 #define BWF_EN 0x0040 251 #define MWF_EN 0x0020 252 #define UWF_EN 0x0010 253 #define LAN_WAKE_EN 0x0002 254 255 /* PLA_LED_FEATURE */ 256 #define LED_MODE_MASK 0x0700 257 258 /* PLA_PHY_PWR */ 259 #define TX_10M_IDLE_EN 0x0080 260 #define PFM_PWM_SWITCH 0x0040 261 262 /* PLA_MAC_PWR_CTRL */ 263 #define D3_CLK_GATED_EN 0x00004000 264 #define MCU_CLK_RATIO 0x07010f07 265 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 266 #define ALDPS_SPDWN_RATIO 0x0f87 267 268 /* PLA_MAC_PWR_CTRL2 */ 269 #define EEE_SPDWN_RATIO 0x8007 270 271 /* PLA_MAC_PWR_CTRL3 */ 272 #define PKT_AVAIL_SPDWN_EN 0x0100 273 #define SUSPEND_SPDWN_EN 0x0004 274 #define U1U2_SPDWN_EN 0x0002 275 #define L1_SPDWN_EN 0x0001 276 277 /* PLA_MAC_PWR_CTRL4 */ 278 #define PWRSAVE_SPDWN_EN 0x1000 279 #define RXDV_SPDWN_EN 0x0800 280 #define TX10MIDLE_EN 0x0100 281 #define TP100_SPDWN_EN 0x0020 282 #define TP500_SPDWN_EN 0x0010 283 #define TP1000_SPDWN_EN 0x0008 284 #define EEE_SPDWN_EN 0x0001 285 286 /* PLA_GPHY_INTR_IMR */ 287 #define GPHY_STS_MSK 0x0001 288 #define SPEED_DOWN_MSK 0x0002 289 #define SPDWN_RXDV_MSK 0x0004 290 #define SPDWN_LINKCHG_MSK 0x0008 291 292 /* PLA_PHYAR */ 293 #define PHYAR_FLAG 0x80000000 294 295 /* PLA_EEE_CR */ 296 #define EEE_RX_EN 0x0001 297 #define EEE_TX_EN 0x0002 298 299 /* PLA_BOOT_CTRL */ 300 #define AUTOLOAD_DONE 0x0002 301 302 /* USB_USB2PHY */ 303 #define USB2PHY_SUSPEND 0x0001 304 #define USB2PHY_L1 0x0002 305 306 /* USB_SSPHYLINK2 */ 307 #define pwd_dn_scale_mask 0x3ffe 308 #define pwd_dn_scale(x) ((x) << 1) 309 310 /* USB_CSR_DUMMY1 */ 311 #define DYNAMIC_BURST 0x0001 312 313 /* USB_CSR_DUMMY2 */ 314 #define EP4_FULL_FC 0x0001 315 316 /* USB_DEV_STAT */ 317 #define STAT_SPEED_MASK 0x0006 318 #define STAT_SPEED_HIGH 0x0000 319 #define STAT_SPEED_FULL 0x0002 320 321 /* USB_TX_AGG */ 322 #define TX_AGG_MAX_THRESHOLD 0x03 323 324 /* USB_RX_BUF_TH */ 325 #define RX_THR_SUPPER 0x0c350180 326 #define RX_THR_HIGH 0x7a120180 327 #define RX_THR_SLOW 0xffff0180 328 329 /* USB_TX_DMA */ 330 #define TEST_MODE_DISABLE 0x00000001 331 #define TX_SIZE_ADJUST1 0x00000100 332 333 /* USB_UPS_CTRL */ 334 #define POWER_CUT 0x0100 335 336 /* USB_PM_CTRL_STATUS */ 337 #define RESUME_INDICATE 0x0001 338 339 /* USB_USB_CTRL */ 340 #define RX_AGG_DISABLE 0x0010 341 342 /* USB_U2P3_CTRL */ 343 #define U2P3_ENABLE 0x0001 344 345 /* USB_POWER_CUT */ 346 #define PWR_EN 0x0001 347 #define PHASE2_EN 0x0008 348 349 /* USB_MISC_0 */ 350 #define PCUT_STATUS 0x0001 351 352 /* USB_RX_EARLY_AGG */ 353 #define EARLY_AGG_SUPPER 0x0e832981 354 #define EARLY_AGG_HIGH 0x0e837a12 355 #define EARLY_AGG_SLOW 0x0e83ffff 356 357 /* USB_WDT11_CTRL */ 358 #define TIMER11_EN 0x0001 359 360 /* USB_LPM_CTRL */ 361 /* bit 4 ~ 5: fifo empty boundary */ 362 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 363 /* bit 2 ~ 3: LMP timer */ 364 #define LPM_TIMER_MASK 0x0c 365 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 366 #define LPM_TIMER_500US 0x0c /* 500 us */ 367 #define ROK_EXIT_LPM 0x02 368 369 /* USB_AFE_CTRL2 */ 370 #define SEN_VAL_MASK 0xf800 371 #define SEN_VAL_NORMAL 0xa000 372 #define SEL_RXIDLE 0x0100 373 374 /* OCP_ALDPS_CONFIG */ 375 #define ENPWRSAVE 0x8000 376 #define ENPDNPS 0x0200 377 #define LINKENA 0x0100 378 #define DIS_SDSAVE 0x0010 379 380 /* OCP_PHY_STATUS */ 381 #define PHY_STAT_MASK 0x0007 382 #define PHY_STAT_LAN_ON 3 383 #define PHY_STAT_PWRDN 5 384 385 /* OCP_POWER_CFG */ 386 #define EEE_CLKDIV_EN 0x8000 387 #define EN_ALDPS 0x0004 388 #define EN_10M_PLLOFF 0x0001 389 390 /* OCP_EEE_CONFIG1 */ 391 #define RG_TXLPI_MSK_HFDUP 0x8000 392 #define RG_MATCLR_EN 0x4000 393 #define EEE_10_CAP 0x2000 394 #define EEE_NWAY_EN 0x1000 395 #define TX_QUIET_EN 0x0200 396 #define RX_QUIET_EN 0x0100 397 #define sd_rise_time_mask 0x0070 398 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 399 #define RG_RXLPI_MSK_HFDUP 0x0008 400 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 401 402 /* OCP_EEE_CONFIG2 */ 403 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 404 #define RG_DACQUIET_EN 0x0400 405 #define RG_LDVQUIET_EN 0x0200 406 #define RG_CKRSEL 0x0020 407 #define RG_EEEPRG_EN 0x0010 408 409 /* OCP_EEE_CONFIG3 */ 410 #define fast_snr_mask 0xff80 411 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 412 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 413 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 414 415 /* OCP_EEE_AR */ 416 /* bit[15:14] function */ 417 #define FUN_ADDR 0x0000 418 #define FUN_DATA 0x4000 419 /* bit[4:0] device addr */ 420 421 /* OCP_EEE_CFG */ 422 #define CTAP_SHORT_EN 0x0040 423 #define EEE10_EN 0x0010 424 425 /* OCP_DOWN_SPEED */ 426 #define EN_10M_BGOFF 0x0080 427 428 /* OCP_ADC_CFG */ 429 #define CKADSEL_L 0x0100 430 #define ADC_EN 0x0080 431 #define EN_EMI_L 0x0040 432 433 /* SRAM_LPF_CFG */ 434 #define LPF_AUTO_TUNE 0x8000 435 436 /* SRAM_10M_AMP1 */ 437 #define GDAC_IB_UPALL 0x0008 438 439 /* SRAM_10M_AMP2 */ 440 #define AMP_DN 0x0200 441 442 /* SRAM_IMPEDANCE */ 443 #define RX_DRIVING_MASK 0x6000 444 445 enum rtl_register_content { 446 _1000bps = 0x10, 447 _100bps = 0x08, 448 _10bps = 0x04, 449 LINK_STATUS = 0x02, 450 FULL_DUP = 0x01, 451 }; 452 453 #define RTL8152_MAX_TX 4 454 #define RTL8152_MAX_RX 10 455 #define INTBUFSIZE 2 456 #define CRC_SIZE 4 457 #define TX_ALIGN 4 458 #define RX_ALIGN 8 459 460 #define INTR_LINK 0x0004 461 462 #define RTL8152_REQT_READ 0xc0 463 #define RTL8152_REQT_WRITE 0x40 464 #define RTL8152_REQ_GET_REGS 0x05 465 #define RTL8152_REQ_SET_REGS 0x05 466 467 #define BYTE_EN_DWORD 0xff 468 #define BYTE_EN_WORD 0x33 469 #define BYTE_EN_BYTE 0x11 470 #define BYTE_EN_SIX_BYTES 0x3f 471 #define BYTE_EN_START_MASK 0x0f 472 #define BYTE_EN_END_MASK 0xf0 473 474 #define RTL8153_MAX_PACKET 9216 /* 9K */ 475 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 476 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 477 #define RTL8153_RMS RTL8153_MAX_PACKET 478 #define RTL8152_TX_TIMEOUT (5 * HZ) 479 #define RTL8152_NAPI_WEIGHT 64 480 481 /* rtl8152 flags */ 482 enum rtl8152_flags { 483 RTL8152_UNPLUG = 0, 484 RTL8152_SET_RX_MODE, 485 WORK_ENABLE, 486 RTL8152_LINK_CHG, 487 SELECTIVE_SUSPEND, 488 PHY_RESET, 489 SCHEDULE_NAPI, 490 }; 491 492 /* Define these values to match your device */ 493 #define VENDOR_ID_REALTEK 0x0bda 494 #define VENDOR_ID_SAMSUNG 0x04e8 495 #define VENDOR_ID_LENOVO 0x17ef 496 497 #define MCU_TYPE_PLA 0x0100 498 #define MCU_TYPE_USB 0x0000 499 500 struct tally_counter { 501 __le64 tx_packets; 502 __le64 rx_packets; 503 __le64 tx_errors; 504 __le32 rx_errors; 505 __le16 rx_missed; 506 __le16 align_errors; 507 __le32 tx_one_collision; 508 __le32 tx_multi_collision; 509 __le64 rx_unicast; 510 __le64 rx_broadcast; 511 __le32 rx_multicast; 512 __le16 tx_aborted; 513 __le16 tx_underrun; 514 }; 515 516 struct rx_desc { 517 __le32 opts1; 518 #define RX_LEN_MASK 0x7fff 519 520 __le32 opts2; 521 #define RD_UDP_CS BIT(23) 522 #define RD_TCP_CS BIT(22) 523 #define RD_IPV6_CS BIT(20) 524 #define RD_IPV4_CS BIT(19) 525 526 __le32 opts3; 527 #define IPF BIT(23) /* IP checksum fail */ 528 #define UDPF BIT(22) /* UDP checksum fail */ 529 #define TCPF BIT(21) /* TCP checksum fail */ 530 #define RX_VLAN_TAG BIT(16) 531 532 __le32 opts4; 533 __le32 opts5; 534 __le32 opts6; 535 }; 536 537 struct tx_desc { 538 __le32 opts1; 539 #define TX_FS BIT(31) /* First segment of a packet */ 540 #define TX_LS BIT(30) /* Final segment of a packet */ 541 #define GTSENDV4 BIT(28) 542 #define GTSENDV6 BIT(27) 543 #define GTTCPHO_SHIFT 18 544 #define GTTCPHO_MAX 0x7fU 545 #define TX_LEN_MAX 0x3ffffU 546 547 __le32 opts2; 548 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 549 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 550 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 551 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 552 #define MSS_SHIFT 17 553 #define MSS_MAX 0x7ffU 554 #define TCPHO_SHIFT 17 555 #define TCPHO_MAX 0x7ffU 556 #define TX_VLAN_TAG BIT(16) 557 }; 558 559 struct r8152; 560 561 struct rx_agg { 562 struct list_head list; 563 struct urb *urb; 564 struct r8152 *context; 565 void *buffer; 566 void *head; 567 }; 568 569 struct tx_agg { 570 struct list_head list; 571 struct urb *urb; 572 struct r8152 *context; 573 void *buffer; 574 void *head; 575 u32 skb_num; 576 u32 skb_len; 577 }; 578 579 struct r8152 { 580 unsigned long flags; 581 struct usb_device *udev; 582 struct napi_struct napi; 583 struct usb_interface *intf; 584 struct net_device *netdev; 585 struct urb *intr_urb; 586 struct tx_agg tx_info[RTL8152_MAX_TX]; 587 struct rx_agg rx_info[RTL8152_MAX_RX]; 588 struct list_head rx_done, tx_free; 589 struct sk_buff_head tx_queue, rx_queue; 590 spinlock_t rx_lock, tx_lock; 591 struct delayed_work schedule; 592 struct mii_if_info mii; 593 struct mutex control; /* use for hw setting */ 594 595 struct rtl_ops { 596 void (*init)(struct r8152 *); 597 int (*enable)(struct r8152 *); 598 void (*disable)(struct r8152 *); 599 void (*up)(struct r8152 *); 600 void (*down)(struct r8152 *); 601 void (*unload)(struct r8152 *); 602 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 603 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 604 } rtl_ops; 605 606 int intr_interval; 607 u32 saved_wolopts; 608 u32 msg_enable; 609 u32 tx_qlen; 610 u16 ocp_base; 611 u8 *intr_buff; 612 u8 version; 613 }; 614 615 enum rtl_version { 616 RTL_VER_UNKNOWN = 0, 617 RTL_VER_01, 618 RTL_VER_02, 619 RTL_VER_03, 620 RTL_VER_04, 621 RTL_VER_05, 622 RTL_VER_MAX 623 }; 624 625 enum tx_csum_stat { 626 TX_CSUM_SUCCESS = 0, 627 TX_CSUM_TSO, 628 TX_CSUM_NONE 629 }; 630 631 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 632 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 633 */ 634 static const int multicast_filter_limit = 32; 635 static unsigned int agg_buf_sz = 16384; 636 637 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 638 VLAN_ETH_HLEN - VLAN_HLEN) 639 640 static 641 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 642 { 643 int ret; 644 void *tmp; 645 646 tmp = kmalloc(size, GFP_KERNEL); 647 if (!tmp) 648 return -ENOMEM; 649 650 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 651 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 652 value, index, tmp, size, 500); 653 654 memcpy(data, tmp, size); 655 kfree(tmp); 656 657 return ret; 658 } 659 660 static 661 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 662 { 663 int ret; 664 void *tmp; 665 666 tmp = kmemdup(data, size, GFP_KERNEL); 667 if (!tmp) 668 return -ENOMEM; 669 670 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 671 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 672 value, index, tmp, size, 500); 673 674 kfree(tmp); 675 676 return ret; 677 } 678 679 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 680 void *data, u16 type) 681 { 682 u16 limit = 64; 683 int ret = 0; 684 685 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 686 return -ENODEV; 687 688 /* both size and indix must be 4 bytes align */ 689 if ((size & 3) || !size || (index & 3) || !data) 690 return -EPERM; 691 692 if ((u32)index + (u32)size > 0xffff) 693 return -EPERM; 694 695 while (size) { 696 if (size > limit) { 697 ret = get_registers(tp, index, type, limit, data); 698 if (ret < 0) 699 break; 700 701 index += limit; 702 data += limit; 703 size -= limit; 704 } else { 705 ret = get_registers(tp, index, type, size, data); 706 if (ret < 0) 707 break; 708 709 index += size; 710 data += size; 711 size = 0; 712 break; 713 } 714 } 715 716 if (ret == -ENODEV) 717 set_bit(RTL8152_UNPLUG, &tp->flags); 718 719 return ret; 720 } 721 722 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 723 u16 size, void *data, u16 type) 724 { 725 int ret; 726 u16 byteen_start, byteen_end, byen; 727 u16 limit = 512; 728 729 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 730 return -ENODEV; 731 732 /* both size and indix must be 4 bytes align */ 733 if ((size & 3) || !size || (index & 3) || !data) 734 return -EPERM; 735 736 if ((u32)index + (u32)size > 0xffff) 737 return -EPERM; 738 739 byteen_start = byteen & BYTE_EN_START_MASK; 740 byteen_end = byteen & BYTE_EN_END_MASK; 741 742 byen = byteen_start | (byteen_start << 4); 743 ret = set_registers(tp, index, type | byen, 4, data); 744 if (ret < 0) 745 goto error1; 746 747 index += 4; 748 data += 4; 749 size -= 4; 750 751 if (size) { 752 size -= 4; 753 754 while (size) { 755 if (size > limit) { 756 ret = set_registers(tp, index, 757 type | BYTE_EN_DWORD, 758 limit, data); 759 if (ret < 0) 760 goto error1; 761 762 index += limit; 763 data += limit; 764 size -= limit; 765 } else { 766 ret = set_registers(tp, index, 767 type | BYTE_EN_DWORD, 768 size, data); 769 if (ret < 0) 770 goto error1; 771 772 index += size; 773 data += size; 774 size = 0; 775 break; 776 } 777 } 778 779 byen = byteen_end | (byteen_end >> 4); 780 ret = set_registers(tp, index, type | byen, 4, data); 781 if (ret < 0) 782 goto error1; 783 } 784 785 error1: 786 if (ret == -ENODEV) 787 set_bit(RTL8152_UNPLUG, &tp->flags); 788 789 return ret; 790 } 791 792 static inline 793 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 794 { 795 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 796 } 797 798 static inline 799 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 800 { 801 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 802 } 803 804 static inline 805 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 806 { 807 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 808 } 809 810 static inline 811 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 812 { 813 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 814 } 815 816 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 817 { 818 __le32 data; 819 820 generic_ocp_read(tp, index, sizeof(data), &data, type); 821 822 return __le32_to_cpu(data); 823 } 824 825 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 826 { 827 __le32 tmp = __cpu_to_le32(data); 828 829 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 830 } 831 832 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 833 { 834 u32 data; 835 __le32 tmp; 836 u8 shift = index & 2; 837 838 index &= ~3; 839 840 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 841 842 data = __le32_to_cpu(tmp); 843 data >>= (shift * 8); 844 data &= 0xffff; 845 846 return (u16)data; 847 } 848 849 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 850 { 851 u32 mask = 0xffff; 852 __le32 tmp; 853 u16 byen = BYTE_EN_WORD; 854 u8 shift = index & 2; 855 856 data &= mask; 857 858 if (index & 2) { 859 byen <<= shift; 860 mask <<= (shift * 8); 861 data <<= (shift * 8); 862 index &= ~3; 863 } 864 865 tmp = __cpu_to_le32(data); 866 867 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 868 } 869 870 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 871 { 872 u32 data; 873 __le32 tmp; 874 u8 shift = index & 3; 875 876 index &= ~3; 877 878 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 879 880 data = __le32_to_cpu(tmp); 881 data >>= (shift * 8); 882 data &= 0xff; 883 884 return (u8)data; 885 } 886 887 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 888 { 889 u32 mask = 0xff; 890 __le32 tmp; 891 u16 byen = BYTE_EN_BYTE; 892 u8 shift = index & 3; 893 894 data &= mask; 895 896 if (index & 3) { 897 byen <<= shift; 898 mask <<= (shift * 8); 899 data <<= (shift * 8); 900 index &= ~3; 901 } 902 903 tmp = __cpu_to_le32(data); 904 905 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 906 } 907 908 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 909 { 910 u16 ocp_base, ocp_index; 911 912 ocp_base = addr & 0xf000; 913 if (ocp_base != tp->ocp_base) { 914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 915 tp->ocp_base = ocp_base; 916 } 917 918 ocp_index = (addr & 0x0fff) | 0xb000; 919 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 920 } 921 922 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 923 { 924 u16 ocp_base, ocp_index; 925 926 ocp_base = addr & 0xf000; 927 if (ocp_base != tp->ocp_base) { 928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 929 tp->ocp_base = ocp_base; 930 } 931 932 ocp_index = (addr & 0x0fff) | 0xb000; 933 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 934 } 935 936 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 937 { 938 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 939 } 940 941 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 942 { 943 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 944 } 945 946 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 947 { 948 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 949 ocp_reg_write(tp, OCP_SRAM_DATA, data); 950 } 951 952 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 953 { 954 struct r8152 *tp = netdev_priv(netdev); 955 int ret; 956 957 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 958 return -ENODEV; 959 960 if (phy_id != R8152_PHY_ID) 961 return -EINVAL; 962 963 ret = r8152_mdio_read(tp, reg); 964 965 return ret; 966 } 967 968 static 969 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 970 { 971 struct r8152 *tp = netdev_priv(netdev); 972 973 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 974 return; 975 976 if (phy_id != R8152_PHY_ID) 977 return; 978 979 r8152_mdio_write(tp, reg, val); 980 } 981 982 static int 983 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 984 985 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 986 { 987 struct r8152 *tp = netdev_priv(netdev); 988 struct sockaddr *addr = p; 989 int ret = -EADDRNOTAVAIL; 990 991 if (!is_valid_ether_addr(addr->sa_data)) 992 goto out1; 993 994 ret = usb_autopm_get_interface(tp->intf); 995 if (ret < 0) 996 goto out1; 997 998 mutex_lock(&tp->control); 999 1000 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1001 1002 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1003 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1004 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1005 1006 mutex_unlock(&tp->control); 1007 1008 usb_autopm_put_interface(tp->intf); 1009 out1: 1010 return ret; 1011 } 1012 1013 static int set_ethernet_addr(struct r8152 *tp) 1014 { 1015 struct net_device *dev = tp->netdev; 1016 struct sockaddr sa; 1017 int ret; 1018 1019 if (tp->version == RTL_VER_01) 1020 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1021 else 1022 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1023 1024 if (ret < 0) { 1025 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1026 } else if (!is_valid_ether_addr(sa.sa_data)) { 1027 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1028 sa.sa_data); 1029 eth_hw_addr_random(dev); 1030 ether_addr_copy(sa.sa_data, dev->dev_addr); 1031 ret = rtl8152_set_mac_address(dev, &sa); 1032 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1033 sa.sa_data); 1034 } else { 1035 if (tp->version == RTL_VER_01) 1036 ether_addr_copy(dev->dev_addr, sa.sa_data); 1037 else 1038 ret = rtl8152_set_mac_address(dev, &sa); 1039 } 1040 1041 return ret; 1042 } 1043 1044 static void read_bulk_callback(struct urb *urb) 1045 { 1046 struct net_device *netdev; 1047 int status = urb->status; 1048 struct rx_agg *agg; 1049 struct r8152 *tp; 1050 1051 agg = urb->context; 1052 if (!agg) 1053 return; 1054 1055 tp = agg->context; 1056 if (!tp) 1057 return; 1058 1059 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1060 return; 1061 1062 if (!test_bit(WORK_ENABLE, &tp->flags)) 1063 return; 1064 1065 netdev = tp->netdev; 1066 1067 /* When link down, the driver would cancel all bulks. */ 1068 /* This avoid the re-submitting bulk */ 1069 if (!netif_carrier_ok(netdev)) 1070 return; 1071 1072 usb_mark_last_busy(tp->udev); 1073 1074 switch (status) { 1075 case 0: 1076 if (urb->actual_length < ETH_ZLEN) 1077 break; 1078 1079 spin_lock(&tp->rx_lock); 1080 list_add_tail(&agg->list, &tp->rx_done); 1081 spin_unlock(&tp->rx_lock); 1082 napi_schedule(&tp->napi); 1083 return; 1084 case -ESHUTDOWN: 1085 set_bit(RTL8152_UNPLUG, &tp->flags); 1086 netif_device_detach(tp->netdev); 1087 return; 1088 case -ENOENT: 1089 return; /* the urb is in unlink state */ 1090 case -ETIME: 1091 if (net_ratelimit()) 1092 netdev_warn(netdev, "maybe reset is needed?\n"); 1093 break; 1094 default: 1095 if (net_ratelimit()) 1096 netdev_warn(netdev, "Rx status %d\n", status); 1097 break; 1098 } 1099 1100 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1101 } 1102 1103 static void write_bulk_callback(struct urb *urb) 1104 { 1105 struct net_device_stats *stats; 1106 struct net_device *netdev; 1107 struct tx_agg *agg; 1108 struct r8152 *tp; 1109 int status = urb->status; 1110 1111 agg = urb->context; 1112 if (!agg) 1113 return; 1114 1115 tp = agg->context; 1116 if (!tp) 1117 return; 1118 1119 netdev = tp->netdev; 1120 stats = &netdev->stats; 1121 if (status) { 1122 if (net_ratelimit()) 1123 netdev_warn(netdev, "Tx status %d\n", status); 1124 stats->tx_errors += agg->skb_num; 1125 } else { 1126 stats->tx_packets += agg->skb_num; 1127 stats->tx_bytes += agg->skb_len; 1128 } 1129 1130 spin_lock(&tp->tx_lock); 1131 list_add_tail(&agg->list, &tp->tx_free); 1132 spin_unlock(&tp->tx_lock); 1133 1134 usb_autopm_put_interface_async(tp->intf); 1135 1136 if (!netif_carrier_ok(netdev)) 1137 return; 1138 1139 if (!test_bit(WORK_ENABLE, &tp->flags)) 1140 return; 1141 1142 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1143 return; 1144 1145 if (!skb_queue_empty(&tp->tx_queue)) 1146 napi_schedule(&tp->napi); 1147 } 1148 1149 static void intr_callback(struct urb *urb) 1150 { 1151 struct r8152 *tp; 1152 __le16 *d; 1153 int status = urb->status; 1154 int res; 1155 1156 tp = urb->context; 1157 if (!tp) 1158 return; 1159 1160 if (!test_bit(WORK_ENABLE, &tp->flags)) 1161 return; 1162 1163 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1164 return; 1165 1166 switch (status) { 1167 case 0: /* success */ 1168 break; 1169 case -ECONNRESET: /* unlink */ 1170 case -ESHUTDOWN: 1171 netif_device_detach(tp->netdev); 1172 case -ENOENT: 1173 case -EPROTO: 1174 netif_info(tp, intr, tp->netdev, 1175 "Stop submitting intr, status %d\n", status); 1176 return; 1177 case -EOVERFLOW: 1178 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1179 goto resubmit; 1180 /* -EPIPE: should clear the halt */ 1181 default: 1182 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1183 goto resubmit; 1184 } 1185 1186 d = urb->transfer_buffer; 1187 if (INTR_LINK & __le16_to_cpu(d[0])) { 1188 if (!netif_carrier_ok(tp->netdev)) { 1189 set_bit(RTL8152_LINK_CHG, &tp->flags); 1190 schedule_delayed_work(&tp->schedule, 0); 1191 } 1192 } else { 1193 if (netif_carrier_ok(tp->netdev)) { 1194 set_bit(RTL8152_LINK_CHG, &tp->flags); 1195 schedule_delayed_work(&tp->schedule, 0); 1196 } 1197 } 1198 1199 resubmit: 1200 res = usb_submit_urb(urb, GFP_ATOMIC); 1201 if (res == -ENODEV) { 1202 set_bit(RTL8152_UNPLUG, &tp->flags); 1203 netif_device_detach(tp->netdev); 1204 } else if (res) { 1205 netif_err(tp, intr, tp->netdev, 1206 "can't resubmit intr, status %d\n", res); 1207 } 1208 } 1209 1210 static inline void *rx_agg_align(void *data) 1211 { 1212 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1213 } 1214 1215 static inline void *tx_agg_align(void *data) 1216 { 1217 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1218 } 1219 1220 static void free_all_mem(struct r8152 *tp) 1221 { 1222 int i; 1223 1224 for (i = 0; i < RTL8152_MAX_RX; i++) { 1225 usb_free_urb(tp->rx_info[i].urb); 1226 tp->rx_info[i].urb = NULL; 1227 1228 kfree(tp->rx_info[i].buffer); 1229 tp->rx_info[i].buffer = NULL; 1230 tp->rx_info[i].head = NULL; 1231 } 1232 1233 for (i = 0; i < RTL8152_MAX_TX; i++) { 1234 usb_free_urb(tp->tx_info[i].urb); 1235 tp->tx_info[i].urb = NULL; 1236 1237 kfree(tp->tx_info[i].buffer); 1238 tp->tx_info[i].buffer = NULL; 1239 tp->tx_info[i].head = NULL; 1240 } 1241 1242 usb_free_urb(tp->intr_urb); 1243 tp->intr_urb = NULL; 1244 1245 kfree(tp->intr_buff); 1246 tp->intr_buff = NULL; 1247 } 1248 1249 static int alloc_all_mem(struct r8152 *tp) 1250 { 1251 struct net_device *netdev = tp->netdev; 1252 struct usb_interface *intf = tp->intf; 1253 struct usb_host_interface *alt = intf->cur_altsetting; 1254 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1255 struct urb *urb; 1256 int node, i; 1257 u8 *buf; 1258 1259 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1260 1261 spin_lock_init(&tp->rx_lock); 1262 spin_lock_init(&tp->tx_lock); 1263 INIT_LIST_HEAD(&tp->tx_free); 1264 skb_queue_head_init(&tp->tx_queue); 1265 skb_queue_head_init(&tp->rx_queue); 1266 1267 for (i = 0; i < RTL8152_MAX_RX; i++) { 1268 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1269 if (!buf) 1270 goto err1; 1271 1272 if (buf != rx_agg_align(buf)) { 1273 kfree(buf); 1274 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1275 node); 1276 if (!buf) 1277 goto err1; 1278 } 1279 1280 urb = usb_alloc_urb(0, GFP_KERNEL); 1281 if (!urb) { 1282 kfree(buf); 1283 goto err1; 1284 } 1285 1286 INIT_LIST_HEAD(&tp->rx_info[i].list); 1287 tp->rx_info[i].context = tp; 1288 tp->rx_info[i].urb = urb; 1289 tp->rx_info[i].buffer = buf; 1290 tp->rx_info[i].head = rx_agg_align(buf); 1291 } 1292 1293 for (i = 0; i < RTL8152_MAX_TX; i++) { 1294 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1295 if (!buf) 1296 goto err1; 1297 1298 if (buf != tx_agg_align(buf)) { 1299 kfree(buf); 1300 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1301 node); 1302 if (!buf) 1303 goto err1; 1304 } 1305 1306 urb = usb_alloc_urb(0, GFP_KERNEL); 1307 if (!urb) { 1308 kfree(buf); 1309 goto err1; 1310 } 1311 1312 INIT_LIST_HEAD(&tp->tx_info[i].list); 1313 tp->tx_info[i].context = tp; 1314 tp->tx_info[i].urb = urb; 1315 tp->tx_info[i].buffer = buf; 1316 tp->tx_info[i].head = tx_agg_align(buf); 1317 1318 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1319 } 1320 1321 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1322 if (!tp->intr_urb) 1323 goto err1; 1324 1325 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1326 if (!tp->intr_buff) 1327 goto err1; 1328 1329 tp->intr_interval = (int)ep_intr->desc.bInterval; 1330 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1331 tp->intr_buff, INTBUFSIZE, intr_callback, 1332 tp, tp->intr_interval); 1333 1334 return 0; 1335 1336 err1: 1337 free_all_mem(tp); 1338 return -ENOMEM; 1339 } 1340 1341 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1342 { 1343 struct tx_agg *agg = NULL; 1344 unsigned long flags; 1345 1346 if (list_empty(&tp->tx_free)) 1347 return NULL; 1348 1349 spin_lock_irqsave(&tp->tx_lock, flags); 1350 if (!list_empty(&tp->tx_free)) { 1351 struct list_head *cursor; 1352 1353 cursor = tp->tx_free.next; 1354 list_del_init(cursor); 1355 agg = list_entry(cursor, struct tx_agg, list); 1356 } 1357 spin_unlock_irqrestore(&tp->tx_lock, flags); 1358 1359 return agg; 1360 } 1361 1362 /* r8152_csum_workaround() 1363 * The hw limites the value the transport offset. When the offset is out of the 1364 * range, calculate the checksum by sw. 1365 */ 1366 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1367 struct sk_buff_head *list) 1368 { 1369 if (skb_shinfo(skb)->gso_size) { 1370 netdev_features_t features = tp->netdev->features; 1371 struct sk_buff_head seg_list; 1372 struct sk_buff *segs, *nskb; 1373 1374 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1375 segs = skb_gso_segment(skb, features); 1376 if (IS_ERR(segs) || !segs) 1377 goto drop; 1378 1379 __skb_queue_head_init(&seg_list); 1380 1381 do { 1382 nskb = segs; 1383 segs = segs->next; 1384 nskb->next = NULL; 1385 __skb_queue_tail(&seg_list, nskb); 1386 } while (segs); 1387 1388 skb_queue_splice(&seg_list, list); 1389 dev_kfree_skb(skb); 1390 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1391 if (skb_checksum_help(skb) < 0) 1392 goto drop; 1393 1394 __skb_queue_head(list, skb); 1395 } else { 1396 struct net_device_stats *stats; 1397 1398 drop: 1399 stats = &tp->netdev->stats; 1400 stats->tx_dropped++; 1401 dev_kfree_skb(skb); 1402 } 1403 } 1404 1405 /* msdn_giant_send_check() 1406 * According to the document of microsoft, the TCP Pseudo Header excludes the 1407 * packet length for IPv6 TCP large packets. 1408 */ 1409 static int msdn_giant_send_check(struct sk_buff *skb) 1410 { 1411 const struct ipv6hdr *ipv6h; 1412 struct tcphdr *th; 1413 int ret; 1414 1415 ret = skb_cow_head(skb, 0); 1416 if (ret) 1417 return ret; 1418 1419 ipv6h = ipv6_hdr(skb); 1420 th = tcp_hdr(skb); 1421 1422 th->check = 0; 1423 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1424 1425 return ret; 1426 } 1427 1428 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1429 { 1430 if (skb_vlan_tag_present(skb)) { 1431 u32 opts2; 1432 1433 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1434 desc->opts2 |= cpu_to_le32(opts2); 1435 } 1436 } 1437 1438 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1439 { 1440 u32 opts2 = le32_to_cpu(desc->opts2); 1441 1442 if (opts2 & RX_VLAN_TAG) 1443 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1444 swab16(opts2 & 0xffff)); 1445 } 1446 1447 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1448 struct sk_buff *skb, u32 len, u32 transport_offset) 1449 { 1450 u32 mss = skb_shinfo(skb)->gso_size; 1451 u32 opts1, opts2 = 0; 1452 int ret = TX_CSUM_SUCCESS; 1453 1454 WARN_ON_ONCE(len > TX_LEN_MAX); 1455 1456 opts1 = len | TX_FS | TX_LS; 1457 1458 if (mss) { 1459 if (transport_offset > GTTCPHO_MAX) { 1460 netif_warn(tp, tx_err, tp->netdev, 1461 "Invalid transport offset 0x%x for TSO\n", 1462 transport_offset); 1463 ret = TX_CSUM_TSO; 1464 goto unavailable; 1465 } 1466 1467 switch (vlan_get_protocol(skb)) { 1468 case htons(ETH_P_IP): 1469 opts1 |= GTSENDV4; 1470 break; 1471 1472 case htons(ETH_P_IPV6): 1473 if (msdn_giant_send_check(skb)) { 1474 ret = TX_CSUM_TSO; 1475 goto unavailable; 1476 } 1477 opts1 |= GTSENDV6; 1478 break; 1479 1480 default: 1481 WARN_ON_ONCE(1); 1482 break; 1483 } 1484 1485 opts1 |= transport_offset << GTTCPHO_SHIFT; 1486 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1487 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1488 u8 ip_protocol; 1489 1490 if (transport_offset > TCPHO_MAX) { 1491 netif_warn(tp, tx_err, tp->netdev, 1492 "Invalid transport offset 0x%x\n", 1493 transport_offset); 1494 ret = TX_CSUM_NONE; 1495 goto unavailable; 1496 } 1497 1498 switch (vlan_get_protocol(skb)) { 1499 case htons(ETH_P_IP): 1500 opts2 |= IPV4_CS; 1501 ip_protocol = ip_hdr(skb)->protocol; 1502 break; 1503 1504 case htons(ETH_P_IPV6): 1505 opts2 |= IPV6_CS; 1506 ip_protocol = ipv6_hdr(skb)->nexthdr; 1507 break; 1508 1509 default: 1510 ip_protocol = IPPROTO_RAW; 1511 break; 1512 } 1513 1514 if (ip_protocol == IPPROTO_TCP) 1515 opts2 |= TCP_CS; 1516 else if (ip_protocol == IPPROTO_UDP) 1517 opts2 |= UDP_CS; 1518 else 1519 WARN_ON_ONCE(1); 1520 1521 opts2 |= transport_offset << TCPHO_SHIFT; 1522 } 1523 1524 desc->opts2 = cpu_to_le32(opts2); 1525 desc->opts1 = cpu_to_le32(opts1); 1526 1527 unavailable: 1528 return ret; 1529 } 1530 1531 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1532 { 1533 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1534 int remain, ret; 1535 u8 *tx_data; 1536 1537 __skb_queue_head_init(&skb_head); 1538 spin_lock(&tx_queue->lock); 1539 skb_queue_splice_init(tx_queue, &skb_head); 1540 spin_unlock(&tx_queue->lock); 1541 1542 tx_data = agg->head; 1543 agg->skb_num = 0; 1544 agg->skb_len = 0; 1545 remain = agg_buf_sz; 1546 1547 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1548 struct tx_desc *tx_desc; 1549 struct sk_buff *skb; 1550 unsigned int len; 1551 u32 offset; 1552 1553 skb = __skb_dequeue(&skb_head); 1554 if (!skb) 1555 break; 1556 1557 len = skb->len + sizeof(*tx_desc); 1558 1559 if (len > remain) { 1560 __skb_queue_head(&skb_head, skb); 1561 break; 1562 } 1563 1564 tx_data = tx_agg_align(tx_data); 1565 tx_desc = (struct tx_desc *)tx_data; 1566 1567 offset = (u32)skb_transport_offset(skb); 1568 1569 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1570 r8152_csum_workaround(tp, skb, &skb_head); 1571 continue; 1572 } 1573 1574 rtl_tx_vlan_tag(tx_desc, skb); 1575 1576 tx_data += sizeof(*tx_desc); 1577 1578 len = skb->len; 1579 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1580 struct net_device_stats *stats = &tp->netdev->stats; 1581 1582 stats->tx_dropped++; 1583 dev_kfree_skb_any(skb); 1584 tx_data -= sizeof(*tx_desc); 1585 continue; 1586 } 1587 1588 tx_data += len; 1589 agg->skb_len += len; 1590 agg->skb_num++; 1591 1592 dev_kfree_skb_any(skb); 1593 1594 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1595 } 1596 1597 if (!skb_queue_empty(&skb_head)) { 1598 spin_lock(&tx_queue->lock); 1599 skb_queue_splice(&skb_head, tx_queue); 1600 spin_unlock(&tx_queue->lock); 1601 } 1602 1603 netif_tx_lock(tp->netdev); 1604 1605 if (netif_queue_stopped(tp->netdev) && 1606 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1607 netif_wake_queue(tp->netdev); 1608 1609 netif_tx_unlock(tp->netdev); 1610 1611 ret = usb_autopm_get_interface_async(tp->intf); 1612 if (ret < 0) 1613 goto out_tx_fill; 1614 1615 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1616 agg->head, (int)(tx_data - (u8 *)agg->head), 1617 (usb_complete_t)write_bulk_callback, agg); 1618 1619 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1620 if (ret < 0) 1621 usb_autopm_put_interface_async(tp->intf); 1622 1623 out_tx_fill: 1624 return ret; 1625 } 1626 1627 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1628 { 1629 u8 checksum = CHECKSUM_NONE; 1630 u32 opts2, opts3; 1631 1632 if (tp->version == RTL_VER_01) 1633 goto return_result; 1634 1635 opts2 = le32_to_cpu(rx_desc->opts2); 1636 opts3 = le32_to_cpu(rx_desc->opts3); 1637 1638 if (opts2 & RD_IPV4_CS) { 1639 if (opts3 & IPF) 1640 checksum = CHECKSUM_NONE; 1641 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1642 checksum = CHECKSUM_NONE; 1643 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1644 checksum = CHECKSUM_NONE; 1645 else 1646 checksum = CHECKSUM_UNNECESSARY; 1647 } else if (RD_IPV6_CS) { 1648 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1649 checksum = CHECKSUM_UNNECESSARY; 1650 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1651 checksum = CHECKSUM_UNNECESSARY; 1652 } 1653 1654 return_result: 1655 return checksum; 1656 } 1657 1658 static int rx_bottom(struct r8152 *tp, int budget) 1659 { 1660 unsigned long flags; 1661 struct list_head *cursor, *next, rx_queue; 1662 int ret = 0, work_done = 0; 1663 1664 if (!skb_queue_empty(&tp->rx_queue)) { 1665 while (work_done < budget) { 1666 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1667 struct net_device *netdev = tp->netdev; 1668 struct net_device_stats *stats = &netdev->stats; 1669 unsigned int pkt_len; 1670 1671 if (!skb) 1672 break; 1673 1674 pkt_len = skb->len; 1675 napi_gro_receive(&tp->napi, skb); 1676 work_done++; 1677 stats->rx_packets++; 1678 stats->rx_bytes += pkt_len; 1679 } 1680 } 1681 1682 if (list_empty(&tp->rx_done)) 1683 goto out1; 1684 1685 INIT_LIST_HEAD(&rx_queue); 1686 spin_lock_irqsave(&tp->rx_lock, flags); 1687 list_splice_init(&tp->rx_done, &rx_queue); 1688 spin_unlock_irqrestore(&tp->rx_lock, flags); 1689 1690 list_for_each_safe(cursor, next, &rx_queue) { 1691 struct rx_desc *rx_desc; 1692 struct rx_agg *agg; 1693 int len_used = 0; 1694 struct urb *urb; 1695 u8 *rx_data; 1696 1697 list_del_init(cursor); 1698 1699 agg = list_entry(cursor, struct rx_agg, list); 1700 urb = agg->urb; 1701 if (urb->actual_length < ETH_ZLEN) 1702 goto submit; 1703 1704 rx_desc = agg->head; 1705 rx_data = agg->head; 1706 len_used += sizeof(struct rx_desc); 1707 1708 while (urb->actual_length > len_used) { 1709 struct net_device *netdev = tp->netdev; 1710 struct net_device_stats *stats = &netdev->stats; 1711 unsigned int pkt_len; 1712 struct sk_buff *skb; 1713 1714 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1715 if (pkt_len < ETH_ZLEN) 1716 break; 1717 1718 len_used += pkt_len; 1719 if (urb->actual_length < len_used) 1720 break; 1721 1722 pkt_len -= CRC_SIZE; 1723 rx_data += sizeof(struct rx_desc); 1724 1725 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1726 if (!skb) { 1727 stats->rx_dropped++; 1728 goto find_next_rx; 1729 } 1730 1731 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1732 memcpy(skb->data, rx_data, pkt_len); 1733 skb_put(skb, pkt_len); 1734 skb->protocol = eth_type_trans(skb, netdev); 1735 rtl_rx_vlan_tag(rx_desc, skb); 1736 if (work_done < budget) { 1737 napi_gro_receive(&tp->napi, skb); 1738 work_done++; 1739 stats->rx_packets++; 1740 stats->rx_bytes += pkt_len; 1741 } else { 1742 __skb_queue_tail(&tp->rx_queue, skb); 1743 } 1744 1745 find_next_rx: 1746 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1747 rx_desc = (struct rx_desc *)rx_data; 1748 len_used = (int)(rx_data - (u8 *)agg->head); 1749 len_used += sizeof(struct rx_desc); 1750 } 1751 1752 submit: 1753 if (!ret) { 1754 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1755 } else { 1756 urb->actual_length = 0; 1757 list_add_tail(&agg->list, next); 1758 } 1759 } 1760 1761 if (!list_empty(&rx_queue)) { 1762 spin_lock_irqsave(&tp->rx_lock, flags); 1763 list_splice_tail(&rx_queue, &tp->rx_done); 1764 spin_unlock_irqrestore(&tp->rx_lock, flags); 1765 } 1766 1767 out1: 1768 return work_done; 1769 } 1770 1771 static void tx_bottom(struct r8152 *tp) 1772 { 1773 int res; 1774 1775 do { 1776 struct tx_agg *agg; 1777 1778 if (skb_queue_empty(&tp->tx_queue)) 1779 break; 1780 1781 agg = r8152_get_tx_agg(tp); 1782 if (!agg) 1783 break; 1784 1785 res = r8152_tx_agg_fill(tp, agg); 1786 if (res) { 1787 struct net_device *netdev = tp->netdev; 1788 1789 if (res == -ENODEV) { 1790 set_bit(RTL8152_UNPLUG, &tp->flags); 1791 netif_device_detach(netdev); 1792 } else { 1793 struct net_device_stats *stats = &netdev->stats; 1794 unsigned long flags; 1795 1796 netif_warn(tp, tx_err, netdev, 1797 "failed tx_urb %d\n", res); 1798 stats->tx_dropped += agg->skb_num; 1799 1800 spin_lock_irqsave(&tp->tx_lock, flags); 1801 list_add_tail(&agg->list, &tp->tx_free); 1802 spin_unlock_irqrestore(&tp->tx_lock, flags); 1803 } 1804 } 1805 } while (res == 0); 1806 } 1807 1808 static void bottom_half(struct r8152 *tp) 1809 { 1810 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1811 return; 1812 1813 if (!test_bit(WORK_ENABLE, &tp->flags)) 1814 return; 1815 1816 /* When link down, the driver would cancel all bulks. */ 1817 /* This avoid the re-submitting bulk */ 1818 if (!netif_carrier_ok(tp->netdev)) 1819 return; 1820 1821 clear_bit(SCHEDULE_NAPI, &tp->flags); 1822 1823 tx_bottom(tp); 1824 } 1825 1826 static int r8152_poll(struct napi_struct *napi, int budget) 1827 { 1828 struct r8152 *tp = container_of(napi, struct r8152, napi); 1829 int work_done; 1830 1831 work_done = rx_bottom(tp, budget); 1832 bottom_half(tp); 1833 1834 if (work_done < budget) { 1835 napi_complete(napi); 1836 if (!list_empty(&tp->rx_done)) 1837 napi_schedule(napi); 1838 } 1839 1840 return work_done; 1841 } 1842 1843 static 1844 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1845 { 1846 int ret; 1847 1848 /* The rx would be stopped, so skip submitting */ 1849 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1850 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1851 return 0; 1852 1853 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1854 agg->head, agg_buf_sz, 1855 (usb_complete_t)read_bulk_callback, agg); 1856 1857 ret = usb_submit_urb(agg->urb, mem_flags); 1858 if (ret == -ENODEV) { 1859 set_bit(RTL8152_UNPLUG, &tp->flags); 1860 netif_device_detach(tp->netdev); 1861 } else if (ret) { 1862 struct urb *urb = agg->urb; 1863 unsigned long flags; 1864 1865 urb->actual_length = 0; 1866 spin_lock_irqsave(&tp->rx_lock, flags); 1867 list_add_tail(&agg->list, &tp->rx_done); 1868 spin_unlock_irqrestore(&tp->rx_lock, flags); 1869 1870 netif_err(tp, rx_err, tp->netdev, 1871 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1872 1873 napi_schedule(&tp->napi); 1874 } 1875 1876 return ret; 1877 } 1878 1879 static void rtl_drop_queued_tx(struct r8152 *tp) 1880 { 1881 struct net_device_stats *stats = &tp->netdev->stats; 1882 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1883 struct sk_buff *skb; 1884 1885 if (skb_queue_empty(tx_queue)) 1886 return; 1887 1888 __skb_queue_head_init(&skb_head); 1889 spin_lock_bh(&tx_queue->lock); 1890 skb_queue_splice_init(tx_queue, &skb_head); 1891 spin_unlock_bh(&tx_queue->lock); 1892 1893 while ((skb = __skb_dequeue(&skb_head))) { 1894 dev_kfree_skb(skb); 1895 stats->tx_dropped++; 1896 } 1897 } 1898 1899 static void rtl8152_tx_timeout(struct net_device *netdev) 1900 { 1901 struct r8152 *tp = netdev_priv(netdev); 1902 int i; 1903 1904 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1905 for (i = 0; i < RTL8152_MAX_TX; i++) 1906 usb_unlink_urb(tp->tx_info[i].urb); 1907 } 1908 1909 static void rtl8152_set_rx_mode(struct net_device *netdev) 1910 { 1911 struct r8152 *tp = netdev_priv(netdev); 1912 1913 if (netif_carrier_ok(netdev)) { 1914 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1915 schedule_delayed_work(&tp->schedule, 0); 1916 } 1917 } 1918 1919 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1920 { 1921 struct r8152 *tp = netdev_priv(netdev); 1922 u32 mc_filter[2]; /* Multicast hash filter */ 1923 __le32 tmp[2]; 1924 u32 ocp_data; 1925 1926 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1927 netif_stop_queue(netdev); 1928 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1929 ocp_data &= ~RCR_ACPT_ALL; 1930 ocp_data |= RCR_AB | RCR_APM; 1931 1932 if (netdev->flags & IFF_PROMISC) { 1933 /* Unconditionally log net taps. */ 1934 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1935 ocp_data |= RCR_AM | RCR_AAP; 1936 mc_filter[1] = 0xffffffff; 1937 mc_filter[0] = 0xffffffff; 1938 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1939 (netdev->flags & IFF_ALLMULTI)) { 1940 /* Too many to filter perfectly -- accept all multicasts. */ 1941 ocp_data |= RCR_AM; 1942 mc_filter[1] = 0xffffffff; 1943 mc_filter[0] = 0xffffffff; 1944 } else { 1945 struct netdev_hw_addr *ha; 1946 1947 mc_filter[1] = 0; 1948 mc_filter[0] = 0; 1949 netdev_for_each_mc_addr(ha, netdev) { 1950 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1951 1952 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1953 ocp_data |= RCR_AM; 1954 } 1955 } 1956 1957 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1958 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1959 1960 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1961 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1962 netif_wake_queue(netdev); 1963 } 1964 1965 static netdev_features_t 1966 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 1967 netdev_features_t features) 1968 { 1969 u32 mss = skb_shinfo(skb)->gso_size; 1970 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 1971 int offset = skb_transport_offset(skb); 1972 1973 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 1974 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); 1975 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 1976 features &= ~NETIF_F_GSO_MASK; 1977 1978 return features; 1979 } 1980 1981 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1982 struct net_device *netdev) 1983 { 1984 struct r8152 *tp = netdev_priv(netdev); 1985 1986 skb_tx_timestamp(skb); 1987 1988 skb_queue_tail(&tp->tx_queue, skb); 1989 1990 if (!list_empty(&tp->tx_free)) { 1991 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 1992 set_bit(SCHEDULE_NAPI, &tp->flags); 1993 schedule_delayed_work(&tp->schedule, 0); 1994 } else { 1995 usb_mark_last_busy(tp->udev); 1996 napi_schedule(&tp->napi); 1997 } 1998 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 1999 netif_stop_queue(netdev); 2000 } 2001 2002 return NETDEV_TX_OK; 2003 } 2004 2005 static void r8152b_reset_packet_filter(struct r8152 *tp) 2006 { 2007 u32 ocp_data; 2008 2009 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2010 ocp_data &= ~FMC_FCR_MCU_EN; 2011 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2012 ocp_data |= FMC_FCR_MCU_EN; 2013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2014 } 2015 2016 static void rtl8152_nic_reset(struct r8152 *tp) 2017 { 2018 int i; 2019 2020 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2021 2022 for (i = 0; i < 1000; i++) { 2023 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2024 break; 2025 usleep_range(100, 400); 2026 } 2027 } 2028 2029 static void set_tx_qlen(struct r8152 *tp) 2030 { 2031 struct net_device *netdev = tp->netdev; 2032 2033 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2034 sizeof(struct tx_desc)); 2035 } 2036 2037 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2038 { 2039 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2040 } 2041 2042 static void rtl_set_eee_plus(struct r8152 *tp) 2043 { 2044 u32 ocp_data; 2045 u8 speed; 2046 2047 speed = rtl8152_get_speed(tp); 2048 if (speed & _10bps) { 2049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2050 ocp_data |= EEEP_CR_EEEP_TX; 2051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2052 } else { 2053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2054 ocp_data &= ~EEEP_CR_EEEP_TX; 2055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2056 } 2057 } 2058 2059 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2060 { 2061 u32 ocp_data; 2062 2063 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2064 if (enable) 2065 ocp_data |= RXDY_GATED_EN; 2066 else 2067 ocp_data &= ~RXDY_GATED_EN; 2068 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2069 } 2070 2071 static int rtl_start_rx(struct r8152 *tp) 2072 { 2073 int i, ret = 0; 2074 2075 napi_disable(&tp->napi); 2076 INIT_LIST_HEAD(&tp->rx_done); 2077 for (i = 0; i < RTL8152_MAX_RX; i++) { 2078 INIT_LIST_HEAD(&tp->rx_info[i].list); 2079 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2080 if (ret) 2081 break; 2082 } 2083 napi_enable(&tp->napi); 2084 2085 if (ret && ++i < RTL8152_MAX_RX) { 2086 struct list_head rx_queue; 2087 unsigned long flags; 2088 2089 INIT_LIST_HEAD(&rx_queue); 2090 2091 do { 2092 struct rx_agg *agg = &tp->rx_info[i++]; 2093 struct urb *urb = agg->urb; 2094 2095 urb->actual_length = 0; 2096 list_add_tail(&agg->list, &rx_queue); 2097 } while (i < RTL8152_MAX_RX); 2098 2099 spin_lock_irqsave(&tp->rx_lock, flags); 2100 list_splice_tail(&rx_queue, &tp->rx_done); 2101 spin_unlock_irqrestore(&tp->rx_lock, flags); 2102 } 2103 2104 return ret; 2105 } 2106 2107 static int rtl_stop_rx(struct r8152 *tp) 2108 { 2109 int i; 2110 2111 for (i = 0; i < RTL8152_MAX_RX; i++) 2112 usb_kill_urb(tp->rx_info[i].urb); 2113 2114 while (!skb_queue_empty(&tp->rx_queue)) 2115 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2116 2117 return 0; 2118 } 2119 2120 static int rtl_enable(struct r8152 *tp) 2121 { 2122 u32 ocp_data; 2123 2124 r8152b_reset_packet_filter(tp); 2125 2126 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2127 ocp_data |= CR_RE | CR_TE; 2128 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2129 2130 rxdy_gated_en(tp, false); 2131 2132 return 0; 2133 } 2134 2135 static int rtl8152_enable(struct r8152 *tp) 2136 { 2137 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2138 return -ENODEV; 2139 2140 set_tx_qlen(tp); 2141 rtl_set_eee_plus(tp); 2142 2143 return rtl_enable(tp); 2144 } 2145 2146 static void r8153_set_rx_agg(struct r8152 *tp) 2147 { 2148 u8 speed; 2149 2150 speed = rtl8152_get_speed(tp); 2151 if (speed & _1000bps) { 2152 if (tp->udev->speed == USB_SPEED_SUPER) { 2153 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 2154 RX_THR_SUPPER); 2155 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2156 EARLY_AGG_SUPPER); 2157 } else { 2158 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 2159 RX_THR_HIGH); 2160 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2161 EARLY_AGG_HIGH); 2162 } 2163 } else { 2164 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); 2165 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2166 EARLY_AGG_SLOW); 2167 } 2168 } 2169 2170 static int rtl8153_enable(struct r8152 *tp) 2171 { 2172 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2173 return -ENODEV; 2174 2175 set_tx_qlen(tp); 2176 rtl_set_eee_plus(tp); 2177 r8153_set_rx_agg(tp); 2178 2179 return rtl_enable(tp); 2180 } 2181 2182 static void rtl_disable(struct r8152 *tp) 2183 { 2184 u32 ocp_data; 2185 int i; 2186 2187 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2188 rtl_drop_queued_tx(tp); 2189 return; 2190 } 2191 2192 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2193 ocp_data &= ~RCR_ACPT_ALL; 2194 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2195 2196 rtl_drop_queued_tx(tp); 2197 2198 for (i = 0; i < RTL8152_MAX_TX; i++) 2199 usb_kill_urb(tp->tx_info[i].urb); 2200 2201 rxdy_gated_en(tp, true); 2202 2203 for (i = 0; i < 1000; i++) { 2204 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2205 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2206 break; 2207 usleep_range(1000, 2000); 2208 } 2209 2210 for (i = 0; i < 1000; i++) { 2211 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2212 break; 2213 usleep_range(1000, 2000); 2214 } 2215 2216 rtl_stop_rx(tp); 2217 2218 rtl8152_nic_reset(tp); 2219 } 2220 2221 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2222 { 2223 u32 ocp_data; 2224 2225 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2226 if (enable) 2227 ocp_data |= POWER_CUT; 2228 else 2229 ocp_data &= ~POWER_CUT; 2230 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2231 2232 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2233 ocp_data &= ~RESUME_INDICATE; 2234 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2235 } 2236 2237 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2238 { 2239 u32 ocp_data; 2240 2241 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2242 if (enable) 2243 ocp_data |= CPCR_RX_VLAN; 2244 else 2245 ocp_data &= ~CPCR_RX_VLAN; 2246 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2247 } 2248 2249 static int rtl8152_set_features(struct net_device *dev, 2250 netdev_features_t features) 2251 { 2252 netdev_features_t changed = features ^ dev->features; 2253 struct r8152 *tp = netdev_priv(dev); 2254 int ret; 2255 2256 ret = usb_autopm_get_interface(tp->intf); 2257 if (ret < 0) 2258 goto out; 2259 2260 mutex_lock(&tp->control); 2261 2262 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2263 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2264 rtl_rx_vlan_en(tp, true); 2265 else 2266 rtl_rx_vlan_en(tp, false); 2267 } 2268 2269 mutex_unlock(&tp->control); 2270 2271 usb_autopm_put_interface(tp->intf); 2272 2273 out: 2274 return ret; 2275 } 2276 2277 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2278 2279 static u32 __rtl_get_wol(struct r8152 *tp) 2280 { 2281 u32 ocp_data; 2282 u32 wolopts = 0; 2283 2284 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2285 if (!(ocp_data & LAN_WAKE_EN)) 2286 return 0; 2287 2288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2289 if (ocp_data & LINK_ON_WAKE_EN) 2290 wolopts |= WAKE_PHY; 2291 2292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2293 if (ocp_data & UWF_EN) 2294 wolopts |= WAKE_UCAST; 2295 if (ocp_data & BWF_EN) 2296 wolopts |= WAKE_BCAST; 2297 if (ocp_data & MWF_EN) 2298 wolopts |= WAKE_MCAST; 2299 2300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2301 if (ocp_data & MAGIC_EN) 2302 wolopts |= WAKE_MAGIC; 2303 2304 return wolopts; 2305 } 2306 2307 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2308 { 2309 u32 ocp_data; 2310 2311 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2312 2313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2314 ocp_data &= ~LINK_ON_WAKE_EN; 2315 if (wolopts & WAKE_PHY) 2316 ocp_data |= LINK_ON_WAKE_EN; 2317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2318 2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2320 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2321 if (wolopts & WAKE_UCAST) 2322 ocp_data |= UWF_EN; 2323 if (wolopts & WAKE_BCAST) 2324 ocp_data |= BWF_EN; 2325 if (wolopts & WAKE_MCAST) 2326 ocp_data |= MWF_EN; 2327 if (wolopts & WAKE_ANY) 2328 ocp_data |= LAN_WAKE_EN; 2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2330 2331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2332 2333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2334 ocp_data &= ~MAGIC_EN; 2335 if (wolopts & WAKE_MAGIC) 2336 ocp_data |= MAGIC_EN; 2337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2338 2339 if (wolopts & WAKE_ANY) 2340 device_set_wakeup_enable(&tp->udev->dev, true); 2341 else 2342 device_set_wakeup_enable(&tp->udev->dev, false); 2343 } 2344 2345 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2346 { 2347 if (enable) { 2348 u32 ocp_data; 2349 2350 __rtl_set_wol(tp, WAKE_ANY); 2351 2352 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2353 2354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2355 ocp_data |= LINK_OFF_WAKE_EN; 2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2357 2358 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2359 } else { 2360 __rtl_set_wol(tp, tp->saved_wolopts); 2361 } 2362 } 2363 2364 static void rtl_phy_reset(struct r8152 *tp) 2365 { 2366 u16 data; 2367 int i; 2368 2369 clear_bit(PHY_RESET, &tp->flags); 2370 2371 data = r8152_mdio_read(tp, MII_BMCR); 2372 2373 /* don't reset again before the previous one complete */ 2374 if (data & BMCR_RESET) 2375 return; 2376 2377 data |= BMCR_RESET; 2378 r8152_mdio_write(tp, MII_BMCR, data); 2379 2380 for (i = 0; i < 50; i++) { 2381 msleep(20); 2382 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2383 break; 2384 } 2385 } 2386 2387 static void r8153_teredo_off(struct r8152 *tp) 2388 { 2389 u32 ocp_data; 2390 2391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2392 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2394 2395 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2397 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2398 } 2399 2400 static void r8152b_disable_aldps(struct r8152 *tp) 2401 { 2402 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2403 msleep(20); 2404 } 2405 2406 static inline void r8152b_enable_aldps(struct r8152 *tp) 2407 { 2408 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2409 LINKENA | DIS_SDSAVE); 2410 } 2411 2412 static void rtl8152_disable(struct r8152 *tp) 2413 { 2414 r8152b_disable_aldps(tp); 2415 rtl_disable(tp); 2416 r8152b_enable_aldps(tp); 2417 } 2418 2419 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2420 { 2421 u16 data; 2422 2423 data = r8152_mdio_read(tp, MII_BMCR); 2424 if (data & BMCR_PDOWN) { 2425 data &= ~BMCR_PDOWN; 2426 r8152_mdio_write(tp, MII_BMCR, data); 2427 } 2428 2429 set_bit(PHY_RESET, &tp->flags); 2430 } 2431 2432 static void r8152b_exit_oob(struct r8152 *tp) 2433 { 2434 u32 ocp_data; 2435 int i; 2436 2437 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2438 ocp_data &= ~RCR_ACPT_ALL; 2439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2440 2441 rxdy_gated_en(tp, true); 2442 r8153_teredo_off(tp); 2443 r8152b_hw_phy_cfg(tp); 2444 2445 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2446 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2447 2448 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2449 ocp_data &= ~NOW_IS_OOB; 2450 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2451 2452 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2453 ocp_data &= ~MCU_BORW_EN; 2454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2455 2456 for (i = 0; i < 1000; i++) { 2457 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2458 if (ocp_data & LINK_LIST_READY) 2459 break; 2460 usleep_range(1000, 2000); 2461 } 2462 2463 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2464 ocp_data |= RE_INIT_LL; 2465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2466 2467 for (i = 0; i < 1000; i++) { 2468 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2469 if (ocp_data & LINK_LIST_READY) 2470 break; 2471 usleep_range(1000, 2000); 2472 } 2473 2474 rtl8152_nic_reset(tp); 2475 2476 /* rx share fifo credit full threshold */ 2477 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2478 2479 if (tp->udev->speed == USB_SPEED_FULL || 2480 tp->udev->speed == USB_SPEED_LOW) { 2481 /* rx share fifo credit near full threshold */ 2482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2483 RXFIFO_THR2_FULL); 2484 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2485 RXFIFO_THR3_FULL); 2486 } else { 2487 /* rx share fifo credit near full threshold */ 2488 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2489 RXFIFO_THR2_HIGH); 2490 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2491 RXFIFO_THR3_HIGH); 2492 } 2493 2494 /* TX share fifo free credit full threshold */ 2495 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2496 2497 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2498 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2499 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2500 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2501 2502 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2503 2504 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2505 2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2507 ocp_data |= TCR0_AUTO_FIFO; 2508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2509 } 2510 2511 static void r8152b_enter_oob(struct r8152 *tp) 2512 { 2513 u32 ocp_data; 2514 int i; 2515 2516 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2517 ocp_data &= ~NOW_IS_OOB; 2518 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2519 2520 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2521 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2522 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2523 2524 rtl_disable(tp); 2525 2526 for (i = 0; i < 1000; i++) { 2527 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2528 if (ocp_data & LINK_LIST_READY) 2529 break; 2530 usleep_range(1000, 2000); 2531 } 2532 2533 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2534 ocp_data |= RE_INIT_LL; 2535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2536 2537 for (i = 0; i < 1000; i++) { 2538 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2539 if (ocp_data & LINK_LIST_READY) 2540 break; 2541 usleep_range(1000, 2000); 2542 } 2543 2544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2545 2546 rtl_rx_vlan_en(tp, true); 2547 2548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2549 ocp_data |= ALDPS_PROXY_MODE; 2550 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2551 2552 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2553 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2555 2556 rxdy_gated_en(tp, false); 2557 2558 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2559 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2561 } 2562 2563 static void r8153_hw_phy_cfg(struct r8152 *tp) 2564 { 2565 u32 ocp_data; 2566 u16 data; 2567 2568 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2569 data = r8152_mdio_read(tp, MII_BMCR); 2570 if (data & BMCR_PDOWN) { 2571 data &= ~BMCR_PDOWN; 2572 r8152_mdio_write(tp, MII_BMCR, data); 2573 } 2574 2575 if (tp->version == RTL_VER_03) { 2576 data = ocp_reg_read(tp, OCP_EEE_CFG); 2577 data &= ~CTAP_SHORT_EN; 2578 ocp_reg_write(tp, OCP_EEE_CFG, data); 2579 } 2580 2581 data = ocp_reg_read(tp, OCP_POWER_CFG); 2582 data |= EEE_CLKDIV_EN; 2583 ocp_reg_write(tp, OCP_POWER_CFG, data); 2584 2585 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2586 data |= EN_10M_BGOFF; 2587 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2588 data = ocp_reg_read(tp, OCP_POWER_CFG); 2589 data |= EN_10M_PLLOFF; 2590 ocp_reg_write(tp, OCP_POWER_CFG, data); 2591 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2592 2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2594 ocp_data |= PFM_PWM_SWITCH; 2595 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2596 2597 /* Enable LPF corner auto tune */ 2598 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2599 2600 /* Adjust 10M Amplitude */ 2601 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2602 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2603 2604 set_bit(PHY_RESET, &tp->flags); 2605 } 2606 2607 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2608 { 2609 u8 u1u2[8]; 2610 2611 if (enable) 2612 memset(u1u2, 0xff, sizeof(u1u2)); 2613 else 2614 memset(u1u2, 0x00, sizeof(u1u2)); 2615 2616 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2617 } 2618 2619 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2620 { 2621 u32 ocp_data; 2622 2623 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2624 if (enable) 2625 ocp_data |= U2P3_ENABLE; 2626 else 2627 ocp_data &= ~U2P3_ENABLE; 2628 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2629 } 2630 2631 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2632 { 2633 u32 ocp_data; 2634 2635 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2636 if (enable) 2637 ocp_data |= PWR_EN | PHASE2_EN; 2638 else 2639 ocp_data &= ~(PWR_EN | PHASE2_EN); 2640 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2641 2642 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2643 ocp_data &= ~PCUT_STATUS; 2644 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2645 } 2646 2647 static void r8153_first_init(struct r8152 *tp) 2648 { 2649 u32 ocp_data; 2650 int i; 2651 2652 rxdy_gated_en(tp, true); 2653 r8153_teredo_off(tp); 2654 2655 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2656 ocp_data &= ~RCR_ACPT_ALL; 2657 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2658 2659 r8153_hw_phy_cfg(tp); 2660 2661 rtl8152_nic_reset(tp); 2662 2663 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2664 ocp_data &= ~NOW_IS_OOB; 2665 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2666 2667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2668 ocp_data &= ~MCU_BORW_EN; 2669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2670 2671 for (i = 0; i < 1000; i++) { 2672 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2673 if (ocp_data & LINK_LIST_READY) 2674 break; 2675 usleep_range(1000, 2000); 2676 } 2677 2678 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2679 ocp_data |= RE_INIT_LL; 2680 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2681 2682 for (i = 0; i < 1000; i++) { 2683 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2684 if (ocp_data & LINK_LIST_READY) 2685 break; 2686 usleep_range(1000, 2000); 2687 } 2688 2689 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2690 2691 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2692 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2693 2694 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2695 ocp_data |= TCR0_AUTO_FIFO; 2696 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2697 2698 rtl8152_nic_reset(tp); 2699 2700 /* rx share fifo credit full threshold */ 2701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2702 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2703 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2704 /* TX share fifo free credit full threshold */ 2705 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2706 2707 /* rx aggregation */ 2708 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2709 ocp_data &= ~RX_AGG_DISABLE; 2710 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2711 } 2712 2713 static void r8153_enter_oob(struct r8152 *tp) 2714 { 2715 u32 ocp_data; 2716 int i; 2717 2718 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2719 ocp_data &= ~NOW_IS_OOB; 2720 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2721 2722 rtl_disable(tp); 2723 2724 for (i = 0; i < 1000; i++) { 2725 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2726 if (ocp_data & LINK_LIST_READY) 2727 break; 2728 usleep_range(1000, 2000); 2729 } 2730 2731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2732 ocp_data |= RE_INIT_LL; 2733 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2734 2735 for (i = 0; i < 1000; i++) { 2736 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2737 if (ocp_data & LINK_LIST_READY) 2738 break; 2739 usleep_range(1000, 2000); 2740 } 2741 2742 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2743 2744 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2745 ocp_data &= ~TEREDO_WAKE_MASK; 2746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2747 2748 rtl_rx_vlan_en(tp, true); 2749 2750 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2751 ocp_data |= ALDPS_PROXY_MODE; 2752 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2753 2754 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2755 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2756 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2757 2758 rxdy_gated_en(tp, false); 2759 2760 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2761 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2762 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2763 } 2764 2765 static void r8153_disable_aldps(struct r8152 *tp) 2766 { 2767 u16 data; 2768 2769 data = ocp_reg_read(tp, OCP_POWER_CFG); 2770 data &= ~EN_ALDPS; 2771 ocp_reg_write(tp, OCP_POWER_CFG, data); 2772 msleep(20); 2773 } 2774 2775 static void r8153_enable_aldps(struct r8152 *tp) 2776 { 2777 u16 data; 2778 2779 data = ocp_reg_read(tp, OCP_POWER_CFG); 2780 data |= EN_ALDPS; 2781 ocp_reg_write(tp, OCP_POWER_CFG, data); 2782 } 2783 2784 static void rtl8153_disable(struct r8152 *tp) 2785 { 2786 r8153_disable_aldps(tp); 2787 rtl_disable(tp); 2788 r8153_enable_aldps(tp); 2789 } 2790 2791 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2792 { 2793 u16 bmcr, anar, gbcr; 2794 int ret = 0; 2795 2796 cancel_delayed_work_sync(&tp->schedule); 2797 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2798 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2799 ADVERTISE_100HALF | ADVERTISE_100FULL); 2800 if (tp->mii.supports_gmii) { 2801 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2802 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2803 } else { 2804 gbcr = 0; 2805 } 2806 2807 if (autoneg == AUTONEG_DISABLE) { 2808 if (speed == SPEED_10) { 2809 bmcr = 0; 2810 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2811 } else if (speed == SPEED_100) { 2812 bmcr = BMCR_SPEED100; 2813 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2814 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2815 bmcr = BMCR_SPEED1000; 2816 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2817 } else { 2818 ret = -EINVAL; 2819 goto out; 2820 } 2821 2822 if (duplex == DUPLEX_FULL) 2823 bmcr |= BMCR_FULLDPLX; 2824 } else { 2825 if (speed == SPEED_10) { 2826 if (duplex == DUPLEX_FULL) 2827 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2828 else 2829 anar |= ADVERTISE_10HALF; 2830 } else if (speed == SPEED_100) { 2831 if (duplex == DUPLEX_FULL) { 2832 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2833 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2834 } else { 2835 anar |= ADVERTISE_10HALF; 2836 anar |= ADVERTISE_100HALF; 2837 } 2838 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2839 if (duplex == DUPLEX_FULL) { 2840 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2841 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2842 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2843 } else { 2844 anar |= ADVERTISE_10HALF; 2845 anar |= ADVERTISE_100HALF; 2846 gbcr |= ADVERTISE_1000HALF; 2847 } 2848 } else { 2849 ret = -EINVAL; 2850 goto out; 2851 } 2852 2853 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2854 } 2855 2856 if (test_bit(PHY_RESET, &tp->flags)) 2857 bmcr |= BMCR_RESET; 2858 2859 if (tp->mii.supports_gmii) 2860 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2861 2862 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2863 r8152_mdio_write(tp, MII_BMCR, bmcr); 2864 2865 if (test_bit(PHY_RESET, &tp->flags)) { 2866 int i; 2867 2868 clear_bit(PHY_RESET, &tp->flags); 2869 for (i = 0; i < 50; i++) { 2870 msleep(20); 2871 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2872 break; 2873 } 2874 } 2875 2876 out: 2877 2878 return ret; 2879 } 2880 2881 static void rtl8152_up(struct r8152 *tp) 2882 { 2883 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2884 return; 2885 2886 r8152b_disable_aldps(tp); 2887 r8152b_exit_oob(tp); 2888 r8152b_enable_aldps(tp); 2889 } 2890 2891 static void rtl8152_down(struct r8152 *tp) 2892 { 2893 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2894 rtl_drop_queued_tx(tp); 2895 return; 2896 } 2897 2898 r8152_power_cut_en(tp, false); 2899 r8152b_disable_aldps(tp); 2900 r8152b_enter_oob(tp); 2901 r8152b_enable_aldps(tp); 2902 } 2903 2904 static void rtl8153_up(struct r8152 *tp) 2905 { 2906 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2907 return; 2908 2909 r8153_disable_aldps(tp); 2910 r8153_first_init(tp); 2911 r8153_enable_aldps(tp); 2912 } 2913 2914 static void rtl8153_down(struct r8152 *tp) 2915 { 2916 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2917 rtl_drop_queued_tx(tp); 2918 return; 2919 } 2920 2921 r8153_u1u2en(tp, false); 2922 r8153_power_cut_en(tp, false); 2923 r8153_disable_aldps(tp); 2924 r8153_enter_oob(tp); 2925 r8153_enable_aldps(tp); 2926 } 2927 2928 static void set_carrier(struct r8152 *tp) 2929 { 2930 struct net_device *netdev = tp->netdev; 2931 u8 speed; 2932 2933 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2934 speed = rtl8152_get_speed(tp); 2935 2936 if (speed & LINK_STATUS) { 2937 if (!netif_carrier_ok(netdev)) { 2938 tp->rtl_ops.enable(tp); 2939 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2940 netif_carrier_on(netdev); 2941 rtl_start_rx(tp); 2942 } 2943 } else { 2944 if (netif_carrier_ok(netdev)) { 2945 netif_carrier_off(netdev); 2946 napi_disable(&tp->napi); 2947 tp->rtl_ops.disable(tp); 2948 napi_enable(&tp->napi); 2949 } 2950 } 2951 } 2952 2953 static void rtl_work_func_t(struct work_struct *work) 2954 { 2955 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 2956 2957 /* If the device is unplugged or !netif_running(), the workqueue 2958 * doesn't need to wake the device, and could return directly. 2959 */ 2960 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 2961 return; 2962 2963 if (usb_autopm_get_interface(tp->intf) < 0) 2964 return; 2965 2966 if (!test_bit(WORK_ENABLE, &tp->flags)) 2967 goto out1; 2968 2969 if (!mutex_trylock(&tp->control)) { 2970 schedule_delayed_work(&tp->schedule, 0); 2971 goto out1; 2972 } 2973 2974 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 2975 set_carrier(tp); 2976 2977 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 2978 _rtl8152_set_rx_mode(tp->netdev); 2979 2980 /* don't schedule napi before linking */ 2981 if (test_bit(SCHEDULE_NAPI, &tp->flags) && 2982 netif_carrier_ok(tp->netdev)) { 2983 clear_bit(SCHEDULE_NAPI, &tp->flags); 2984 napi_schedule(&tp->napi); 2985 } 2986 2987 if (test_bit(PHY_RESET, &tp->flags)) 2988 rtl_phy_reset(tp); 2989 2990 mutex_unlock(&tp->control); 2991 2992 out1: 2993 usb_autopm_put_interface(tp->intf); 2994 } 2995 2996 static int rtl8152_open(struct net_device *netdev) 2997 { 2998 struct r8152 *tp = netdev_priv(netdev); 2999 int res = 0; 3000 3001 res = alloc_all_mem(tp); 3002 if (res) 3003 goto out; 3004 3005 netif_carrier_off(netdev); 3006 3007 res = usb_autopm_get_interface(tp->intf); 3008 if (res < 0) { 3009 free_all_mem(tp); 3010 goto out; 3011 } 3012 3013 mutex_lock(&tp->control); 3014 3015 /* The WORK_ENABLE may be set when autoresume occurs */ 3016 if (test_bit(WORK_ENABLE, &tp->flags)) { 3017 clear_bit(WORK_ENABLE, &tp->flags); 3018 usb_kill_urb(tp->intr_urb); 3019 cancel_delayed_work_sync(&tp->schedule); 3020 3021 /* disable the tx/rx, if the workqueue has enabled them. */ 3022 if (netif_carrier_ok(netdev)) 3023 tp->rtl_ops.disable(tp); 3024 } 3025 3026 tp->rtl_ops.up(tp); 3027 3028 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3029 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3030 DUPLEX_FULL); 3031 netif_carrier_off(netdev); 3032 netif_start_queue(netdev); 3033 set_bit(WORK_ENABLE, &tp->flags); 3034 3035 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3036 if (res) { 3037 if (res == -ENODEV) 3038 netif_device_detach(tp->netdev); 3039 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3040 res); 3041 free_all_mem(tp); 3042 } else { 3043 napi_enable(&tp->napi); 3044 } 3045 3046 mutex_unlock(&tp->control); 3047 3048 usb_autopm_put_interface(tp->intf); 3049 3050 out: 3051 return res; 3052 } 3053 3054 static int rtl8152_close(struct net_device *netdev) 3055 { 3056 struct r8152 *tp = netdev_priv(netdev); 3057 int res = 0; 3058 3059 napi_disable(&tp->napi); 3060 clear_bit(WORK_ENABLE, &tp->flags); 3061 usb_kill_urb(tp->intr_urb); 3062 cancel_delayed_work_sync(&tp->schedule); 3063 netif_stop_queue(netdev); 3064 3065 res = usb_autopm_get_interface(tp->intf); 3066 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3067 rtl_drop_queued_tx(tp); 3068 rtl_stop_rx(tp); 3069 } else { 3070 mutex_lock(&tp->control); 3071 3072 /* The autosuspend may have been enabled and wouldn't 3073 * be disable when autoresume occurs, because the 3074 * netif_running() would be false. 3075 */ 3076 rtl_runtime_suspend_enable(tp, false); 3077 3078 tp->rtl_ops.down(tp); 3079 3080 mutex_unlock(&tp->control); 3081 3082 usb_autopm_put_interface(tp->intf); 3083 } 3084 3085 free_all_mem(tp); 3086 3087 return res; 3088 } 3089 3090 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3091 { 3092 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3093 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3094 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3095 } 3096 3097 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3098 { 3099 u16 data; 3100 3101 r8152_mmd_indirect(tp, dev, reg); 3102 data = ocp_reg_read(tp, OCP_EEE_DATA); 3103 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3104 3105 return data; 3106 } 3107 3108 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3109 { 3110 r8152_mmd_indirect(tp, dev, reg); 3111 ocp_reg_write(tp, OCP_EEE_DATA, data); 3112 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3113 } 3114 3115 static void r8152_eee_en(struct r8152 *tp, bool enable) 3116 { 3117 u16 config1, config2, config3; 3118 u32 ocp_data; 3119 3120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3121 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3122 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3123 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3124 3125 if (enable) { 3126 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3127 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3128 config1 |= sd_rise_time(1); 3129 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3130 config3 |= fast_snr(42); 3131 } else { 3132 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3133 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3134 RX_QUIET_EN); 3135 config1 |= sd_rise_time(7); 3136 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3137 config3 |= fast_snr(511); 3138 } 3139 3140 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3141 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3142 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3143 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3144 } 3145 3146 static void r8152b_enable_eee(struct r8152 *tp) 3147 { 3148 r8152_eee_en(tp, true); 3149 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3150 } 3151 3152 static void r8153_eee_en(struct r8152 *tp, bool enable) 3153 { 3154 u32 ocp_data; 3155 u16 config; 3156 3157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3158 config = ocp_reg_read(tp, OCP_EEE_CFG); 3159 3160 if (enable) { 3161 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3162 config |= EEE10_EN; 3163 } else { 3164 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3165 config &= ~EEE10_EN; 3166 } 3167 3168 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3169 ocp_reg_write(tp, OCP_EEE_CFG, config); 3170 } 3171 3172 static void r8153_enable_eee(struct r8152 *tp) 3173 { 3174 r8153_eee_en(tp, true); 3175 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3176 } 3177 3178 static void r8152b_enable_fc(struct r8152 *tp) 3179 { 3180 u16 anar; 3181 3182 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3183 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3184 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3185 } 3186 3187 static void rtl_tally_reset(struct r8152 *tp) 3188 { 3189 u32 ocp_data; 3190 3191 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3192 ocp_data |= TALLY_RESET; 3193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3194 } 3195 3196 static void r8152b_init(struct r8152 *tp) 3197 { 3198 u32 ocp_data; 3199 3200 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3201 return; 3202 3203 r8152b_disable_aldps(tp); 3204 3205 if (tp->version == RTL_VER_01) { 3206 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3207 ocp_data &= ~LED_MODE_MASK; 3208 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3209 } 3210 3211 r8152_power_cut_en(tp, false); 3212 3213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3214 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3215 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3216 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3217 ocp_data &= ~MCU_CLK_RATIO_MASK; 3218 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3219 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3220 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3221 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3223 3224 r8152b_enable_eee(tp); 3225 r8152b_enable_aldps(tp); 3226 r8152b_enable_fc(tp); 3227 rtl_tally_reset(tp); 3228 3229 /* enable rx aggregation */ 3230 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3231 ocp_data &= ~RX_AGG_DISABLE; 3232 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3233 } 3234 3235 static void r8153_init(struct r8152 *tp) 3236 { 3237 u32 ocp_data; 3238 int i; 3239 3240 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3241 return; 3242 3243 r8153_disable_aldps(tp); 3244 r8153_u1u2en(tp, false); 3245 3246 for (i = 0; i < 500; i++) { 3247 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3248 AUTOLOAD_DONE) 3249 break; 3250 msleep(20); 3251 } 3252 3253 for (i = 0; i < 500; i++) { 3254 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3255 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3256 break; 3257 msleep(20); 3258 } 3259 3260 r8153_u2p3en(tp, false); 3261 3262 if (tp->version == RTL_VER_04) { 3263 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3264 ocp_data &= ~pwd_dn_scale_mask; 3265 ocp_data |= pwd_dn_scale(96); 3266 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3267 3268 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3269 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3270 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3271 } else if (tp->version == RTL_VER_05) { 3272 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3273 ocp_data &= ~ECM_ALDPS; 3274 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3275 3276 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3277 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3278 ocp_data &= ~DYNAMIC_BURST; 3279 else 3280 ocp_data |= DYNAMIC_BURST; 3281 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3282 } 3283 3284 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3285 ocp_data |= EP4_FULL_FC; 3286 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3287 3288 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3289 ocp_data &= ~TIMER11_EN; 3290 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3291 3292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3293 ocp_data &= ~LED_MODE_MASK; 3294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3295 3296 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3297 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) 3298 ocp_data |= LPM_TIMER_500MS; 3299 else 3300 ocp_data |= LPM_TIMER_500US; 3301 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3302 3303 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3304 ocp_data &= ~SEN_VAL_MASK; 3305 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3306 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3307 3308 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3309 3310 r8153_power_cut_en(tp, false); 3311 r8153_u1u2en(tp, true); 3312 3313 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3316 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3317 U1U2_SPDWN_EN | L1_SPDWN_EN); 3318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3319 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3320 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3321 EEE_SPDWN_EN); 3322 3323 r8153_enable_eee(tp); 3324 r8153_enable_aldps(tp); 3325 r8152b_enable_fc(tp); 3326 rtl_tally_reset(tp); 3327 } 3328 3329 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3330 { 3331 struct r8152 *tp = usb_get_intfdata(intf); 3332 struct net_device *netdev = tp->netdev; 3333 int ret = 0; 3334 3335 mutex_lock(&tp->control); 3336 3337 if (PMSG_IS_AUTO(message)) { 3338 if (netif_running(netdev) && work_busy(&tp->schedule.work)) { 3339 ret = -EBUSY; 3340 goto out1; 3341 } 3342 3343 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3344 } else { 3345 netif_device_detach(netdev); 3346 } 3347 3348 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3349 clear_bit(WORK_ENABLE, &tp->flags); 3350 usb_kill_urb(tp->intr_urb); 3351 napi_disable(&tp->napi); 3352 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3353 rtl_stop_rx(tp); 3354 rtl_runtime_suspend_enable(tp, true); 3355 } else { 3356 cancel_delayed_work_sync(&tp->schedule); 3357 tp->rtl_ops.down(tp); 3358 } 3359 napi_enable(&tp->napi); 3360 } 3361 out1: 3362 mutex_unlock(&tp->control); 3363 3364 return ret; 3365 } 3366 3367 static int rtl8152_resume(struct usb_interface *intf) 3368 { 3369 struct r8152 *tp = usb_get_intfdata(intf); 3370 3371 mutex_lock(&tp->control); 3372 3373 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3374 tp->rtl_ops.init(tp); 3375 netif_device_attach(tp->netdev); 3376 } 3377 3378 if (netif_running(tp->netdev)) { 3379 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3380 rtl_runtime_suspend_enable(tp, false); 3381 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3382 set_bit(WORK_ENABLE, &tp->flags); 3383 if (netif_carrier_ok(tp->netdev)) 3384 rtl_start_rx(tp); 3385 } else { 3386 tp->rtl_ops.up(tp); 3387 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3388 tp->mii.supports_gmii ? 3389 SPEED_1000 : SPEED_100, 3390 DUPLEX_FULL); 3391 netif_carrier_off(tp->netdev); 3392 set_bit(WORK_ENABLE, &tp->flags); 3393 } 3394 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3395 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3396 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3397 } 3398 3399 mutex_unlock(&tp->control); 3400 3401 return 0; 3402 } 3403 3404 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3405 { 3406 struct r8152 *tp = netdev_priv(dev); 3407 3408 if (usb_autopm_get_interface(tp->intf) < 0) 3409 return; 3410 3411 mutex_lock(&tp->control); 3412 3413 wol->supported = WAKE_ANY; 3414 wol->wolopts = __rtl_get_wol(tp); 3415 3416 mutex_unlock(&tp->control); 3417 3418 usb_autopm_put_interface(tp->intf); 3419 } 3420 3421 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3422 { 3423 struct r8152 *tp = netdev_priv(dev); 3424 int ret; 3425 3426 ret = usb_autopm_get_interface(tp->intf); 3427 if (ret < 0) 3428 goto out_set_wol; 3429 3430 mutex_lock(&tp->control); 3431 3432 __rtl_set_wol(tp, wol->wolopts); 3433 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3434 3435 mutex_unlock(&tp->control); 3436 3437 usb_autopm_put_interface(tp->intf); 3438 3439 out_set_wol: 3440 return ret; 3441 } 3442 3443 static u32 rtl8152_get_msglevel(struct net_device *dev) 3444 { 3445 struct r8152 *tp = netdev_priv(dev); 3446 3447 return tp->msg_enable; 3448 } 3449 3450 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3451 { 3452 struct r8152 *tp = netdev_priv(dev); 3453 3454 tp->msg_enable = value; 3455 } 3456 3457 static void rtl8152_get_drvinfo(struct net_device *netdev, 3458 struct ethtool_drvinfo *info) 3459 { 3460 struct r8152 *tp = netdev_priv(netdev); 3461 3462 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3463 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3464 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3465 } 3466 3467 static 3468 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3469 { 3470 struct r8152 *tp = netdev_priv(netdev); 3471 int ret; 3472 3473 if (!tp->mii.mdio_read) 3474 return -EOPNOTSUPP; 3475 3476 ret = usb_autopm_get_interface(tp->intf); 3477 if (ret < 0) 3478 goto out; 3479 3480 mutex_lock(&tp->control); 3481 3482 ret = mii_ethtool_gset(&tp->mii, cmd); 3483 3484 mutex_unlock(&tp->control); 3485 3486 usb_autopm_put_interface(tp->intf); 3487 3488 out: 3489 return ret; 3490 } 3491 3492 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3493 { 3494 struct r8152 *tp = netdev_priv(dev); 3495 int ret; 3496 3497 ret = usb_autopm_get_interface(tp->intf); 3498 if (ret < 0) 3499 goto out; 3500 3501 mutex_lock(&tp->control); 3502 3503 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3504 3505 mutex_unlock(&tp->control); 3506 3507 usb_autopm_put_interface(tp->intf); 3508 3509 out: 3510 return ret; 3511 } 3512 3513 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3514 "tx_packets", 3515 "rx_packets", 3516 "tx_errors", 3517 "rx_errors", 3518 "rx_missed", 3519 "align_errors", 3520 "tx_single_collisions", 3521 "tx_multi_collisions", 3522 "rx_unicast", 3523 "rx_broadcast", 3524 "rx_multicast", 3525 "tx_aborted", 3526 "tx_underrun", 3527 }; 3528 3529 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3530 { 3531 switch (sset) { 3532 case ETH_SS_STATS: 3533 return ARRAY_SIZE(rtl8152_gstrings); 3534 default: 3535 return -EOPNOTSUPP; 3536 } 3537 } 3538 3539 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3540 struct ethtool_stats *stats, u64 *data) 3541 { 3542 struct r8152 *tp = netdev_priv(dev); 3543 struct tally_counter tally; 3544 3545 if (usb_autopm_get_interface(tp->intf) < 0) 3546 return; 3547 3548 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3549 3550 usb_autopm_put_interface(tp->intf); 3551 3552 data[0] = le64_to_cpu(tally.tx_packets); 3553 data[1] = le64_to_cpu(tally.rx_packets); 3554 data[2] = le64_to_cpu(tally.tx_errors); 3555 data[3] = le32_to_cpu(tally.rx_errors); 3556 data[4] = le16_to_cpu(tally.rx_missed); 3557 data[5] = le16_to_cpu(tally.align_errors); 3558 data[6] = le32_to_cpu(tally.tx_one_collision); 3559 data[7] = le32_to_cpu(tally.tx_multi_collision); 3560 data[8] = le64_to_cpu(tally.rx_unicast); 3561 data[9] = le64_to_cpu(tally.rx_broadcast); 3562 data[10] = le32_to_cpu(tally.rx_multicast); 3563 data[11] = le16_to_cpu(tally.tx_aborted); 3564 data[12] = le16_to_cpu(tally.tx_underrun); 3565 } 3566 3567 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3568 { 3569 switch (stringset) { 3570 case ETH_SS_STATS: 3571 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3572 break; 3573 } 3574 } 3575 3576 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3577 { 3578 u32 ocp_data, lp, adv, supported = 0; 3579 u16 val; 3580 3581 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3582 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3583 3584 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3585 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3586 3587 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3588 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3589 3590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3591 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3592 3593 eee->eee_enabled = !!ocp_data; 3594 eee->eee_active = !!(supported & adv & lp); 3595 eee->supported = supported; 3596 eee->advertised = adv; 3597 eee->lp_advertised = lp; 3598 3599 return 0; 3600 } 3601 3602 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3603 { 3604 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3605 3606 r8152_eee_en(tp, eee->eee_enabled); 3607 3608 if (!eee->eee_enabled) 3609 val = 0; 3610 3611 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3612 3613 return 0; 3614 } 3615 3616 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3617 { 3618 u32 ocp_data, lp, adv, supported = 0; 3619 u16 val; 3620 3621 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3622 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3623 3624 val = ocp_reg_read(tp, OCP_EEE_ADV); 3625 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3626 3627 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3628 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3629 3630 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3631 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3632 3633 eee->eee_enabled = !!ocp_data; 3634 eee->eee_active = !!(supported & adv & lp); 3635 eee->supported = supported; 3636 eee->advertised = adv; 3637 eee->lp_advertised = lp; 3638 3639 return 0; 3640 } 3641 3642 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3643 { 3644 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3645 3646 r8153_eee_en(tp, eee->eee_enabled); 3647 3648 if (!eee->eee_enabled) 3649 val = 0; 3650 3651 ocp_reg_write(tp, OCP_EEE_ADV, val); 3652 3653 return 0; 3654 } 3655 3656 static int 3657 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3658 { 3659 struct r8152 *tp = netdev_priv(net); 3660 int ret; 3661 3662 ret = usb_autopm_get_interface(tp->intf); 3663 if (ret < 0) 3664 goto out; 3665 3666 mutex_lock(&tp->control); 3667 3668 ret = tp->rtl_ops.eee_get(tp, edata); 3669 3670 mutex_unlock(&tp->control); 3671 3672 usb_autopm_put_interface(tp->intf); 3673 3674 out: 3675 return ret; 3676 } 3677 3678 static int 3679 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3680 { 3681 struct r8152 *tp = netdev_priv(net); 3682 int ret; 3683 3684 ret = usb_autopm_get_interface(tp->intf); 3685 if (ret < 0) 3686 goto out; 3687 3688 mutex_lock(&tp->control); 3689 3690 ret = tp->rtl_ops.eee_set(tp, edata); 3691 if (!ret) 3692 ret = mii_nway_restart(&tp->mii); 3693 3694 mutex_unlock(&tp->control); 3695 3696 usb_autopm_put_interface(tp->intf); 3697 3698 out: 3699 return ret; 3700 } 3701 3702 static int rtl8152_nway_reset(struct net_device *dev) 3703 { 3704 struct r8152 *tp = netdev_priv(dev); 3705 int ret; 3706 3707 ret = usb_autopm_get_interface(tp->intf); 3708 if (ret < 0) 3709 goto out; 3710 3711 mutex_lock(&tp->control); 3712 3713 ret = mii_nway_restart(&tp->mii); 3714 3715 mutex_unlock(&tp->control); 3716 3717 usb_autopm_put_interface(tp->intf); 3718 3719 out: 3720 return ret; 3721 } 3722 3723 static struct ethtool_ops ops = { 3724 .get_drvinfo = rtl8152_get_drvinfo, 3725 .get_settings = rtl8152_get_settings, 3726 .set_settings = rtl8152_set_settings, 3727 .get_link = ethtool_op_get_link, 3728 .nway_reset = rtl8152_nway_reset, 3729 .get_msglevel = rtl8152_get_msglevel, 3730 .set_msglevel = rtl8152_set_msglevel, 3731 .get_wol = rtl8152_get_wol, 3732 .set_wol = rtl8152_set_wol, 3733 .get_strings = rtl8152_get_strings, 3734 .get_sset_count = rtl8152_get_sset_count, 3735 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3736 .get_eee = rtl_ethtool_get_eee, 3737 .set_eee = rtl_ethtool_set_eee, 3738 }; 3739 3740 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3741 { 3742 struct r8152 *tp = netdev_priv(netdev); 3743 struct mii_ioctl_data *data = if_mii(rq); 3744 int res; 3745 3746 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3747 return -ENODEV; 3748 3749 res = usb_autopm_get_interface(tp->intf); 3750 if (res < 0) 3751 goto out; 3752 3753 switch (cmd) { 3754 case SIOCGMIIPHY: 3755 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3756 break; 3757 3758 case SIOCGMIIREG: 3759 mutex_lock(&tp->control); 3760 data->val_out = r8152_mdio_read(tp, data->reg_num); 3761 mutex_unlock(&tp->control); 3762 break; 3763 3764 case SIOCSMIIREG: 3765 if (!capable(CAP_NET_ADMIN)) { 3766 res = -EPERM; 3767 break; 3768 } 3769 mutex_lock(&tp->control); 3770 r8152_mdio_write(tp, data->reg_num, data->val_in); 3771 mutex_unlock(&tp->control); 3772 break; 3773 3774 default: 3775 res = -EOPNOTSUPP; 3776 } 3777 3778 usb_autopm_put_interface(tp->intf); 3779 3780 out: 3781 return res; 3782 } 3783 3784 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 3785 { 3786 struct r8152 *tp = netdev_priv(dev); 3787 3788 switch (tp->version) { 3789 case RTL_VER_01: 3790 case RTL_VER_02: 3791 return eth_change_mtu(dev, new_mtu); 3792 default: 3793 break; 3794 } 3795 3796 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 3797 return -EINVAL; 3798 3799 dev->mtu = new_mtu; 3800 3801 return 0; 3802 } 3803 3804 static const struct net_device_ops rtl8152_netdev_ops = { 3805 .ndo_open = rtl8152_open, 3806 .ndo_stop = rtl8152_close, 3807 .ndo_do_ioctl = rtl8152_ioctl, 3808 .ndo_start_xmit = rtl8152_start_xmit, 3809 .ndo_tx_timeout = rtl8152_tx_timeout, 3810 .ndo_set_features = rtl8152_set_features, 3811 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3812 .ndo_set_mac_address = rtl8152_set_mac_address, 3813 .ndo_change_mtu = rtl8152_change_mtu, 3814 .ndo_validate_addr = eth_validate_addr, 3815 .ndo_features_check = rtl8152_features_check, 3816 }; 3817 3818 static void r8152b_get_version(struct r8152 *tp) 3819 { 3820 u32 ocp_data; 3821 u16 version; 3822 3823 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3824 version = (u16)(ocp_data & VERSION_MASK); 3825 3826 switch (version) { 3827 case 0x4c00: 3828 tp->version = RTL_VER_01; 3829 break; 3830 case 0x4c10: 3831 tp->version = RTL_VER_02; 3832 break; 3833 case 0x5c00: 3834 tp->version = RTL_VER_03; 3835 tp->mii.supports_gmii = 1; 3836 break; 3837 case 0x5c10: 3838 tp->version = RTL_VER_04; 3839 tp->mii.supports_gmii = 1; 3840 break; 3841 case 0x5c20: 3842 tp->version = RTL_VER_05; 3843 tp->mii.supports_gmii = 1; 3844 break; 3845 default: 3846 netif_info(tp, probe, tp->netdev, 3847 "Unknown version 0x%04x\n", version); 3848 break; 3849 } 3850 } 3851 3852 static void rtl8152_unload(struct r8152 *tp) 3853 { 3854 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3855 return; 3856 3857 if (tp->version != RTL_VER_01) 3858 r8152_power_cut_en(tp, true); 3859 } 3860 3861 static void rtl8153_unload(struct r8152 *tp) 3862 { 3863 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3864 return; 3865 3866 r8153_power_cut_en(tp, false); 3867 } 3868 3869 static int rtl_ops_init(struct r8152 *tp) 3870 { 3871 struct rtl_ops *ops = &tp->rtl_ops; 3872 int ret = 0; 3873 3874 switch (tp->version) { 3875 case RTL_VER_01: 3876 case RTL_VER_02: 3877 ops->init = r8152b_init; 3878 ops->enable = rtl8152_enable; 3879 ops->disable = rtl8152_disable; 3880 ops->up = rtl8152_up; 3881 ops->down = rtl8152_down; 3882 ops->unload = rtl8152_unload; 3883 ops->eee_get = r8152_get_eee; 3884 ops->eee_set = r8152_set_eee; 3885 break; 3886 3887 case RTL_VER_03: 3888 case RTL_VER_04: 3889 case RTL_VER_05: 3890 ops->init = r8153_init; 3891 ops->enable = rtl8153_enable; 3892 ops->disable = rtl8153_disable; 3893 ops->up = rtl8153_up; 3894 ops->down = rtl8153_down; 3895 ops->unload = rtl8153_unload; 3896 ops->eee_get = r8153_get_eee; 3897 ops->eee_set = r8153_set_eee; 3898 break; 3899 3900 default: 3901 ret = -ENODEV; 3902 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 3903 break; 3904 } 3905 3906 return ret; 3907 } 3908 3909 static int rtl8152_probe(struct usb_interface *intf, 3910 const struct usb_device_id *id) 3911 { 3912 struct usb_device *udev = interface_to_usbdev(intf); 3913 struct r8152 *tp; 3914 struct net_device *netdev; 3915 int ret; 3916 3917 if (udev->actconfig->desc.bConfigurationValue != 1) { 3918 usb_driver_set_configuration(udev, 1); 3919 return -ENODEV; 3920 } 3921 3922 usb_reset_device(udev); 3923 netdev = alloc_etherdev(sizeof(struct r8152)); 3924 if (!netdev) { 3925 dev_err(&intf->dev, "Out of memory\n"); 3926 return -ENOMEM; 3927 } 3928 3929 SET_NETDEV_DEV(netdev, &intf->dev); 3930 tp = netdev_priv(netdev); 3931 tp->msg_enable = 0x7FFF; 3932 3933 tp->udev = udev; 3934 tp->netdev = netdev; 3935 tp->intf = intf; 3936 3937 r8152b_get_version(tp); 3938 ret = rtl_ops_init(tp); 3939 if (ret) 3940 goto out; 3941 3942 mutex_init(&tp->control); 3943 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 3944 3945 netdev->netdev_ops = &rtl8152_netdev_ops; 3946 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 3947 3948 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3949 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 3950 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 3951 NETIF_F_HW_VLAN_CTAG_TX; 3952 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3953 NETIF_F_TSO | NETIF_F_FRAGLIST | 3954 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 3955 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 3956 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 3957 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 3958 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 3959 3960 netdev->ethtool_ops = &ops; 3961 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 3962 3963 tp->mii.dev = netdev; 3964 tp->mii.mdio_read = read_mii_word; 3965 tp->mii.mdio_write = write_mii_word; 3966 tp->mii.phy_id_mask = 0x3f; 3967 tp->mii.reg_num_mask = 0x1f; 3968 tp->mii.phy_id = R8152_PHY_ID; 3969 3970 intf->needs_remote_wakeup = 1; 3971 3972 tp->rtl_ops.init(tp); 3973 set_ethernet_addr(tp); 3974 3975 usb_set_intfdata(intf, tp); 3976 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 3977 3978 ret = register_netdev(netdev); 3979 if (ret != 0) { 3980 netif_err(tp, probe, netdev, "couldn't register the device\n"); 3981 goto out1; 3982 } 3983 3984 tp->saved_wolopts = __rtl_get_wol(tp); 3985 if (tp->saved_wolopts) 3986 device_set_wakeup_enable(&udev->dev, true); 3987 else 3988 device_set_wakeup_enable(&udev->dev, false); 3989 3990 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 3991 3992 return 0; 3993 3994 out1: 3995 netif_napi_del(&tp->napi); 3996 usb_set_intfdata(intf, NULL); 3997 out: 3998 free_netdev(netdev); 3999 return ret; 4000 } 4001 4002 static void rtl8152_disconnect(struct usb_interface *intf) 4003 { 4004 struct r8152 *tp = usb_get_intfdata(intf); 4005 4006 usb_set_intfdata(intf, NULL); 4007 if (tp) { 4008 struct usb_device *udev = tp->udev; 4009 4010 if (udev->state == USB_STATE_NOTATTACHED) 4011 set_bit(RTL8152_UNPLUG, &tp->flags); 4012 4013 netif_napi_del(&tp->napi); 4014 unregister_netdev(tp->netdev); 4015 tp->rtl_ops.unload(tp); 4016 free_netdev(tp->netdev); 4017 } 4018 } 4019 4020 #define REALTEK_USB_DEVICE(vend, prod) \ 4021 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4022 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4023 .idVendor = (vend), \ 4024 .idProduct = (prod), \ 4025 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4026 }, \ 4027 { \ 4028 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4029 USB_DEVICE_ID_MATCH_DEVICE, \ 4030 .idVendor = (vend), \ 4031 .idProduct = (prod), \ 4032 .bInterfaceClass = USB_CLASS_COMM, \ 4033 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4034 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4035 4036 /* table of devices that work with this driver */ 4037 static struct usb_device_id rtl8152_table[] = { 4038 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4039 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4040 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4041 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4042 {} 4043 }; 4044 4045 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4046 4047 static struct usb_driver rtl8152_driver = { 4048 .name = MODULENAME, 4049 .id_table = rtl8152_table, 4050 .probe = rtl8152_probe, 4051 .disconnect = rtl8152_disconnect, 4052 .suspend = rtl8152_suspend, 4053 .resume = rtl8152_resume, 4054 .reset_resume = rtl8152_resume, 4055 .supports_autosuspend = 1, 4056 .disable_hub_initiated_lpm = 1, 4057 }; 4058 4059 module_usb_driver(rtl8152_driver); 4060 4061 MODULE_AUTHOR(DRIVER_AUTHOR); 4062 MODULE_DESCRIPTION(DRIVER_DESC); 4063 MODULE_LICENSE("GPL"); 4064