1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/atomic.h> 26 #include <linux/acpi.h> 27 #include <linux/firmware.h> 28 #include <crypto/hash.h> 29 #include <linux/usb/r8152.h> 30 #include <net/gso.h> 31 32 /* Information for net-next */ 33 #define NETNEXT_VERSION "12" 34 35 /* Information for net */ 36 #define NET_VERSION "13" 37 38 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 39 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 40 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 41 #define MODULENAME "r8152" 42 43 #define R8152_PHY_ID 32 44 45 #define PLA_IDR 0xc000 46 #define PLA_RCR 0xc010 47 #define PLA_RCR1 0xc012 48 #define PLA_RMS 0xc016 49 #define PLA_RXFIFO_CTRL0 0xc0a0 50 #define PLA_RXFIFO_FULL 0xc0a2 51 #define PLA_RXFIFO_CTRL1 0xc0a4 52 #define PLA_RX_FIFO_FULL 0xc0a6 53 #define PLA_RXFIFO_CTRL2 0xc0a8 54 #define PLA_RX_FIFO_EMPTY 0xc0aa 55 #define PLA_DMY_REG0 0xc0b0 56 #define PLA_FMC 0xc0b4 57 #define PLA_CFG_WOL 0xc0b6 58 #define PLA_TEREDO_CFG 0xc0bc 59 #define PLA_TEREDO_WAKE_BASE 0xc0c4 60 #define PLA_MAR 0xcd00 61 #define PLA_BACKUP 0xd000 62 #define PLA_BDC_CR 0xd1a0 63 #define PLA_TEREDO_TIMER 0xd2cc 64 #define PLA_REALWOW_TIMER 0xd2e8 65 #define PLA_UPHY_TIMER 0xd388 66 #define PLA_SUSPEND_FLAG 0xd38a 67 #define PLA_INDICATE_FALG 0xd38c 68 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ 69 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ 70 #define PLA_EXTRA_STATUS 0xd398 71 #define PLA_GPHY_CTRL 0xd3ae 72 #define PLA_POL_GPIO_CTRL 0xdc6a 73 #define PLA_EFUSE_DATA 0xdd00 74 #define PLA_EFUSE_CMD 0xdd02 75 #define PLA_LEDSEL 0xdd90 76 #define PLA_LED_FEATURE 0xdd92 77 #define PLA_PHYAR 0xde00 78 #define PLA_BOOT_CTRL 0xe004 79 #define PLA_LWAKE_CTRL_REG 0xe007 80 #define PLA_GPHY_INTR_IMR 0xe022 81 #define PLA_EEE_CR 0xe040 82 #define PLA_EEE_TXTWSYS 0xe04c 83 #define PLA_EEE_TXTWSYS_2P5G 0xe058 84 #define PLA_EEEP_CR 0xe080 85 #define PLA_MAC_PWR_CTRL 0xe0c0 86 #define PLA_MAC_PWR_CTRL2 0xe0ca 87 #define PLA_MAC_PWR_CTRL3 0xe0cc 88 #define PLA_MAC_PWR_CTRL4 0xe0ce 89 #define PLA_WDT6_CTRL 0xe428 90 #define PLA_TCR0 0xe610 91 #define PLA_TCR1 0xe612 92 #define PLA_MTPS 0xe615 93 #define PLA_TXFIFO_CTRL 0xe618 94 #define PLA_TXFIFO_FULL 0xe61a 95 #define PLA_RSTTALLY 0xe800 96 #define PLA_CR 0xe813 97 #define PLA_CRWECR 0xe81c 98 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 99 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 100 #define PLA_CONFIG5 0xe822 101 #define PLA_PHY_PWR 0xe84c 102 #define PLA_OOB_CTRL 0xe84f 103 #define PLA_CPCR 0xe854 104 #define PLA_MISC_0 0xe858 105 #define PLA_MISC_1 0xe85a 106 #define PLA_OCP_GPHY_BASE 0xe86c 107 #define PLA_TALLYCNT 0xe890 108 #define PLA_SFF_STS_7 0xe8de 109 #define PLA_PHYSTATUS 0xe908 110 #define PLA_CONFIG6 0xe90a /* CONFIG6 */ 111 #define PLA_USB_CFG 0xe952 112 #define PLA_BP_BA 0xfc26 113 #define PLA_BP_0 0xfc28 114 #define PLA_BP_1 0xfc2a 115 #define PLA_BP_2 0xfc2c 116 #define PLA_BP_3 0xfc2e 117 #define PLA_BP_4 0xfc30 118 #define PLA_BP_5 0xfc32 119 #define PLA_BP_6 0xfc34 120 #define PLA_BP_7 0xfc36 121 #define PLA_BP_EN 0xfc38 122 123 #define USB_USB2PHY 0xb41e 124 #define USB_SSPHYLINK1 0xb426 125 #define USB_SSPHYLINK2 0xb428 126 #define USB_L1_CTRL 0xb45e 127 #define USB_U2P3_CTRL 0xb460 128 #define USB_CSR_DUMMY1 0xb464 129 #define USB_CSR_DUMMY2 0xb466 130 #define USB_DEV_STAT 0xb808 131 #define USB_CONNECT_TIMER 0xcbf8 132 #define USB_MSC_TIMER 0xcbfc 133 #define USB_BURST_SIZE 0xcfc0 134 #define USB_FW_FIX_EN0 0xcfca 135 #define USB_FW_FIX_EN1 0xcfcc 136 #define USB_LPM_CONFIG 0xcfd8 137 #define USB_ECM_OPTION 0xcfee 138 #define USB_CSTMR 0xcfef /* RTL8153A */ 139 #define USB_MISC_2 0xcfff 140 #define USB_ECM_OP 0xd26b 141 #define USB_GPHY_CTRL 0xd284 142 #define USB_SPEED_OPTION 0xd32a 143 #define USB_FW_CTRL 0xd334 /* RTL8153B */ 144 #define USB_FC_TIMER 0xd340 145 #define USB_USB_CTRL 0xd406 146 #define USB_PHY_CTRL 0xd408 147 #define USB_TX_AGG 0xd40a 148 #define USB_RX_BUF_TH 0xd40c 149 #define USB_USB_TIMER 0xd428 150 #define USB_RX_EARLY_TIMEOUT 0xd42c 151 #define USB_RX_EARLY_SIZE 0xd42e 152 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 153 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 154 #define USB_TX_DMA 0xd434 155 #define USB_UPT_RXDMA_OWN 0xd437 156 #define USB_UPHY3_MDCMDIO 0xd480 157 #define USB_TOLERANCE 0xd490 158 #define USB_LPM_CTRL 0xd41a 159 #define USB_BMU_RESET 0xd4b0 160 #define USB_BMU_CONFIG 0xd4b4 161 #define USB_U1U2_TIMER 0xd4da 162 #define USB_FW_TASK 0xd4e8 /* RTL8153B */ 163 #define USB_RX_AGGR_NUM 0xd4ee 164 #define USB_UPS_CTRL 0xd800 165 #define USB_POWER_CUT 0xd80a 166 #define USB_MISC_0 0xd81a 167 #define USB_MISC_1 0xd81f 168 #define USB_AFE_CTRL2 0xd824 169 #define USB_UPHY_XTAL 0xd826 170 #define USB_UPS_CFG 0xd842 171 #define USB_UPS_FLAGS 0xd848 172 #define USB_WDT1_CTRL 0xe404 173 #define USB_WDT11_CTRL 0xe43c 174 #define USB_BP_BA PLA_BP_BA 175 #define USB_BP_0 PLA_BP_0 176 #define USB_BP_1 PLA_BP_1 177 #define USB_BP_2 PLA_BP_2 178 #define USB_BP_3 PLA_BP_3 179 #define USB_BP_4 PLA_BP_4 180 #define USB_BP_5 PLA_BP_5 181 #define USB_BP_6 PLA_BP_6 182 #define USB_BP_7 PLA_BP_7 183 #define USB_BP_EN PLA_BP_EN /* RTL8153A */ 184 #define USB_BP_8 0xfc38 /* RTL8153B */ 185 #define USB_BP_9 0xfc3a 186 #define USB_BP_10 0xfc3c 187 #define USB_BP_11 0xfc3e 188 #define USB_BP_12 0xfc40 189 #define USB_BP_13 0xfc42 190 #define USB_BP_14 0xfc44 191 #define USB_BP_15 0xfc46 192 #define USB_BP2_EN 0xfc48 193 194 /* OCP Registers */ 195 #define OCP_ALDPS_CONFIG 0x2010 196 #define OCP_EEE_CONFIG1 0x2080 197 #define OCP_EEE_CONFIG2 0x2092 198 #define OCP_EEE_CONFIG3 0x2094 199 #define OCP_BASE_MII 0xa400 200 #define OCP_EEE_AR 0xa41a 201 #define OCP_EEE_DATA 0xa41c 202 #define OCP_PHY_STATUS 0xa420 203 #define OCP_INTR_EN 0xa424 204 #define OCP_NCTL_CFG 0xa42c 205 #define OCP_POWER_CFG 0xa430 206 #define OCP_EEE_CFG 0xa432 207 #define OCP_SRAM_ADDR 0xa436 208 #define OCP_SRAM_DATA 0xa438 209 #define OCP_DOWN_SPEED 0xa442 210 #define OCP_EEE_ABLE 0xa5c4 211 #define OCP_EEE_ADV 0xa5d0 212 #define OCP_EEE_LPABLE 0xa5d2 213 #define OCP_10GBT_CTRL 0xa5d4 214 #define OCP_10GBT_STAT 0xa5d6 215 #define OCP_EEE_ADV2 0xa6d4 216 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 217 #define OCP_PHY_PATCH_STAT 0xb800 218 #define OCP_PHY_PATCH_CMD 0xb820 219 #define OCP_PHY_LOCK 0xb82e 220 #define OCP_ADC_IOFFSET 0xbcfc 221 #define OCP_ADC_CFG 0xbc06 222 #define OCP_SYSCLK_CFG 0xc416 223 224 /* SRAM Register */ 225 #define SRAM_GREEN_CFG 0x8011 226 #define SRAM_LPF_CFG 0x8012 227 #define SRAM_GPHY_FW_VER 0x801e 228 #define SRAM_10M_AMP1 0x8080 229 #define SRAM_10M_AMP2 0x8082 230 #define SRAM_IMPEDANCE 0x8084 231 #define SRAM_PHY_LOCK 0xb82e 232 233 /* PLA_RCR */ 234 #define RCR_AAP 0x00000001 235 #define RCR_APM 0x00000002 236 #define RCR_AM 0x00000004 237 #define RCR_AB 0x00000008 238 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 239 #define SLOT_EN BIT(11) 240 241 /* PLA_RCR1 */ 242 #define OUTER_VLAN BIT(7) 243 #define INNER_VLAN BIT(6) 244 245 /* PLA_RXFIFO_CTRL0 */ 246 #define RXFIFO_THR1_NORMAL 0x00080002 247 #define RXFIFO_THR1_OOB 0x01800003 248 249 /* PLA_RXFIFO_FULL */ 250 #define RXFIFO_FULL_MASK 0xfff 251 252 /* PLA_RXFIFO_CTRL1 */ 253 #define RXFIFO_THR2_FULL 0x00000060 254 #define RXFIFO_THR2_HIGH 0x00000038 255 #define RXFIFO_THR2_OOB 0x0000004a 256 #define RXFIFO_THR2_NORMAL 0x00a0 257 258 /* PLA_RXFIFO_CTRL2 */ 259 #define RXFIFO_THR3_FULL 0x00000078 260 #define RXFIFO_THR3_HIGH 0x00000048 261 #define RXFIFO_THR3_OOB 0x0000005a 262 #define RXFIFO_THR3_NORMAL 0x0110 263 264 /* PLA_TXFIFO_CTRL */ 265 #define TXFIFO_THR_NORMAL 0x00400008 266 #define TXFIFO_THR_NORMAL2 0x01000008 267 268 /* PLA_DMY_REG0 */ 269 #define ECM_ALDPS 0x0002 270 271 /* PLA_FMC */ 272 #define FMC_FCR_MCU_EN 0x0001 273 274 /* PLA_EEEP_CR */ 275 #define EEEP_CR_EEEP_TX 0x0002 276 277 /* PLA_WDT6_CTRL */ 278 #define WDT6_SET_MODE 0x0010 279 280 /* PLA_TCR0 */ 281 #define TCR0_TX_EMPTY 0x0800 282 #define TCR0_AUTO_FIFO 0x0080 283 284 /* PLA_TCR1 */ 285 #define VERSION_MASK 0x7cf0 286 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) 287 #define IFG_144NS BIT(9) 288 #define IFG_96NS (BIT(9) | BIT(8)) 289 290 /* PLA_MTPS */ 291 #define MTPS_JUMBO (12 * 1024 / 64) 292 #define MTPS_DEFAULT (6 * 1024 / 64) 293 294 /* PLA_RSTTALLY */ 295 #define TALLY_RESET 0x0001 296 297 /* PLA_CR */ 298 #define CR_RST 0x10 299 #define CR_RE 0x08 300 #define CR_TE 0x04 301 302 /* PLA_CRWECR */ 303 #define CRWECR_NORAML 0x00 304 #define CRWECR_CONFIG 0xc0 305 306 /* PLA_OOB_CTRL */ 307 #define NOW_IS_OOB 0x80 308 #define TXFIFO_EMPTY 0x20 309 #define RXFIFO_EMPTY 0x10 310 #define LINK_LIST_READY 0x02 311 #define DIS_MCU_CLROOB 0x01 312 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 313 314 /* PLA_MISC_1 */ 315 #define RXDY_GATED_EN 0x0008 316 317 /* PLA_SFF_STS_7 */ 318 #define RE_INIT_LL 0x8000 319 #define MCU_BORW_EN 0x4000 320 321 /* PLA_CPCR */ 322 #define FLOW_CTRL_EN BIT(0) 323 #define CPCR_RX_VLAN 0x0040 324 325 /* PLA_CFG_WOL */ 326 #define MAGIC_EN 0x0001 327 328 /* PLA_TEREDO_CFG */ 329 #define TEREDO_SEL 0x8000 330 #define TEREDO_WAKE_MASK 0x7f00 331 #define TEREDO_RS_EVENT_MASK 0x00fe 332 #define OOB_TEREDO_EN 0x0001 333 334 /* PLA_BDC_CR */ 335 #define ALDPS_PROXY_MODE 0x0001 336 337 /* PLA_EFUSE_CMD */ 338 #define EFUSE_READ_CMD BIT(15) 339 #define EFUSE_DATA_BIT16 BIT(7) 340 341 /* PLA_CONFIG34 */ 342 #define LINK_ON_WAKE_EN 0x0010 343 #define LINK_OFF_WAKE_EN 0x0008 344 345 /* PLA_CONFIG6 */ 346 #define LANWAKE_CLR_EN BIT(0) 347 348 /* PLA_USB_CFG */ 349 #define EN_XG_LIP BIT(1) 350 #define EN_G_LIP BIT(2) 351 352 /* PLA_CONFIG5 */ 353 #define BWF_EN 0x0040 354 #define MWF_EN 0x0020 355 #define UWF_EN 0x0010 356 #define LAN_WAKE_EN 0x0002 357 358 /* PLA_LED_FEATURE */ 359 #define LED_MODE_MASK 0x0700 360 361 /* PLA_PHY_PWR */ 362 #define TX_10M_IDLE_EN 0x0080 363 #define PFM_PWM_SWITCH 0x0040 364 #define TEST_IO_OFF BIT(4) 365 366 /* PLA_MAC_PWR_CTRL */ 367 #define D3_CLK_GATED_EN 0x00004000 368 #define MCU_CLK_RATIO 0x07010f07 369 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 370 #define ALDPS_SPDWN_RATIO 0x0f87 371 372 /* PLA_MAC_PWR_CTRL2 */ 373 #define EEE_SPDWN_RATIO 0x8007 374 #define MAC_CLK_SPDWN_EN BIT(15) 375 #define EEE_SPDWN_RATIO_MASK 0xff 376 377 /* PLA_MAC_PWR_CTRL3 */ 378 #define PLA_MCU_SPDWN_EN BIT(14) 379 #define PKT_AVAIL_SPDWN_EN 0x0100 380 #define SUSPEND_SPDWN_EN 0x0004 381 #define U1U2_SPDWN_EN 0x0002 382 #define L1_SPDWN_EN 0x0001 383 384 /* PLA_MAC_PWR_CTRL4 */ 385 #define PWRSAVE_SPDWN_EN 0x1000 386 #define RXDV_SPDWN_EN 0x0800 387 #define TX10MIDLE_EN 0x0100 388 #define IDLE_SPDWN_EN BIT(6) 389 #define TP100_SPDWN_EN 0x0020 390 #define TP500_SPDWN_EN 0x0010 391 #define TP1000_SPDWN_EN 0x0008 392 #define EEE_SPDWN_EN 0x0001 393 394 /* PLA_GPHY_INTR_IMR */ 395 #define GPHY_STS_MSK 0x0001 396 #define SPEED_DOWN_MSK 0x0002 397 #define SPDWN_RXDV_MSK 0x0004 398 #define SPDWN_LINKCHG_MSK 0x0008 399 400 /* PLA_PHYAR */ 401 #define PHYAR_FLAG 0x80000000 402 403 /* PLA_EEE_CR */ 404 #define EEE_RX_EN 0x0001 405 #define EEE_TX_EN 0x0002 406 407 /* PLA_BOOT_CTRL */ 408 #define AUTOLOAD_DONE 0x0002 409 410 /* PLA_LWAKE_CTRL_REG */ 411 #define LANWAKE_PIN BIT(7) 412 413 /* PLA_SUSPEND_FLAG */ 414 #define LINK_CHG_EVENT BIT(0) 415 416 /* PLA_INDICATE_FALG */ 417 #define UPCOMING_RUNTIME_D3 BIT(0) 418 419 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ 420 #define DEBUG_OE BIT(0) 421 #define DEBUG_LTSSM 0x0082 422 423 /* PLA_EXTRA_STATUS */ 424 #define CUR_LINK_OK BIT(15) 425 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ 426 #define LINK_CHANGE_FLAG BIT(8) 427 #define POLL_LINK_CHG BIT(0) 428 429 /* PLA_GPHY_CTRL */ 430 #define GPHY_FLASH BIT(1) 431 432 /* PLA_POL_GPIO_CTRL */ 433 #define DACK_DET_EN BIT(15) 434 #define POL_GPHY_PATCH BIT(4) 435 436 /* USB_USB2PHY */ 437 #define USB2PHY_SUSPEND 0x0001 438 #define USB2PHY_L1 0x0002 439 440 /* USB_SSPHYLINK1 */ 441 #define DELAY_PHY_PWR_CHG BIT(1) 442 443 /* USB_SSPHYLINK2 */ 444 #define pwd_dn_scale_mask 0x3ffe 445 #define pwd_dn_scale(x) ((x) << 1) 446 447 /* USB_CSR_DUMMY1 */ 448 #define DYNAMIC_BURST 0x0001 449 450 /* USB_CSR_DUMMY2 */ 451 #define EP4_FULL_FC 0x0001 452 453 /* USB_DEV_STAT */ 454 #define STAT_SPEED_MASK 0x0006 455 #define STAT_SPEED_HIGH 0x0000 456 #define STAT_SPEED_FULL 0x0002 457 458 /* USB_FW_FIX_EN0 */ 459 #define FW_FIX_SUSPEND BIT(14) 460 461 /* USB_FW_FIX_EN1 */ 462 #define FW_IP_RESET_EN BIT(9) 463 464 /* USB_LPM_CONFIG */ 465 #define LPM_U1U2_EN BIT(0) 466 467 /* USB_TX_AGG */ 468 #define TX_AGG_MAX_THRESHOLD 0x03 469 470 /* USB_RX_BUF_TH */ 471 #define RX_THR_SUPPER 0x0c350180 472 #define RX_THR_HIGH 0x7a120180 473 #define RX_THR_SLOW 0xffff0180 474 #define RX_THR_B 0x00010001 475 476 /* USB_TX_DMA */ 477 #define TEST_MODE_DISABLE 0x00000001 478 #define TX_SIZE_ADJUST1 0x00000100 479 480 /* USB_BMU_RESET */ 481 #define BMU_RESET_EP_IN 0x01 482 #define BMU_RESET_EP_OUT 0x02 483 484 /* USB_BMU_CONFIG */ 485 #define ACT_ODMA BIT(1) 486 487 /* USB_UPT_RXDMA_OWN */ 488 #define OWN_UPDATE BIT(0) 489 #define OWN_CLEAR BIT(1) 490 491 /* USB_FW_TASK */ 492 #define FC_PATCH_TASK BIT(1) 493 494 /* USB_RX_AGGR_NUM */ 495 #define RX_AGGR_NUM_MASK 0x1ff 496 497 /* USB_UPS_CTRL */ 498 #define POWER_CUT 0x0100 499 500 /* USB_PM_CTRL_STATUS */ 501 #define RESUME_INDICATE 0x0001 502 503 /* USB_ECM_OPTION */ 504 #define BYPASS_MAC_RESET BIT(5) 505 506 /* USB_CSTMR */ 507 #define FORCE_SUPER BIT(0) 508 509 /* USB_MISC_2 */ 510 #define UPS_FORCE_PWR_DOWN BIT(0) 511 512 /* USB_ECM_OP */ 513 #define EN_ALL_SPEED BIT(0) 514 515 /* USB_GPHY_CTRL */ 516 #define GPHY_PATCH_DONE BIT(2) 517 #define BYPASS_FLASH BIT(5) 518 #define BACKUP_RESTRORE BIT(6) 519 520 /* USB_SPEED_OPTION */ 521 #define RG_PWRDN_EN BIT(8) 522 #define ALL_SPEED_OFF BIT(9) 523 524 /* USB_FW_CTRL */ 525 #define FLOW_CTRL_PATCH_OPT BIT(1) 526 #define AUTO_SPEEDUP BIT(3) 527 #define FLOW_CTRL_PATCH_2 BIT(8) 528 529 /* USB_FC_TIMER */ 530 #define CTRL_TIMER_EN BIT(15) 531 532 /* USB_USB_CTRL */ 533 #define CDC_ECM_EN BIT(3) 534 #define RX_AGG_DISABLE 0x0010 535 #define RX_ZERO_EN 0x0080 536 537 /* USB_U2P3_CTRL */ 538 #define U2P3_ENABLE 0x0001 539 #define RX_DETECT8 BIT(3) 540 541 /* USB_POWER_CUT */ 542 #define PWR_EN 0x0001 543 #define PHASE2_EN 0x0008 544 #define UPS_EN BIT(4) 545 #define USP_PREWAKE BIT(5) 546 547 /* USB_MISC_0 */ 548 #define PCUT_STATUS 0x0001 549 550 /* USB_RX_EARLY_TIMEOUT */ 551 #define COALESCE_SUPER 85000U 552 #define COALESCE_HIGH 250000U 553 #define COALESCE_SLOW 524280U 554 555 /* USB_WDT1_CTRL */ 556 #define WTD1_EN BIT(0) 557 558 /* USB_WDT11_CTRL */ 559 #define TIMER11_EN 0x0001 560 561 /* USB_LPM_CTRL */ 562 /* bit 4 ~ 5: fifo empty boundary */ 563 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 564 /* bit 2 ~ 3: LMP timer */ 565 #define LPM_TIMER_MASK 0x0c 566 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 567 #define LPM_TIMER_500US 0x0c /* 500 us */ 568 #define ROK_EXIT_LPM 0x02 569 570 /* USB_AFE_CTRL2 */ 571 #define SEN_VAL_MASK 0xf800 572 #define SEN_VAL_NORMAL 0xa000 573 #define SEL_RXIDLE 0x0100 574 575 /* USB_UPHY_XTAL */ 576 #define OOBS_POLLING BIT(8) 577 578 /* USB_UPS_CFG */ 579 #define SAW_CNT_1MS_MASK 0x0fff 580 #define MID_REVERSE BIT(5) /* RTL8156A */ 581 582 /* USB_UPS_FLAGS */ 583 #define UPS_FLAGS_R_TUNE BIT(0) 584 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 585 #define UPS_FLAGS_250M_CKDIV BIT(2) 586 #define UPS_FLAGS_EN_ALDPS BIT(3) 587 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 588 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 589 #define ups_flags_speed(x) ((x) << 16) 590 #define UPS_FLAGS_EN_EEE BIT(20) 591 #define UPS_FLAGS_EN_500M_EEE BIT(21) 592 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 593 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) 594 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 595 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 596 #define UPS_FLAGS_EN_GREEN BIT(26) 597 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 598 599 enum spd_duplex { 600 NWAY_10M_HALF, 601 NWAY_10M_FULL, 602 NWAY_100M_HALF, 603 NWAY_100M_FULL, 604 NWAY_1000M_FULL, 605 FORCE_10M_HALF, 606 FORCE_10M_FULL, 607 FORCE_100M_HALF, 608 FORCE_100M_FULL, 609 FORCE_1000M_FULL, 610 NWAY_2500M_FULL, 611 }; 612 613 /* OCP_ALDPS_CONFIG */ 614 #define ENPWRSAVE 0x8000 615 #define ENPDNPS 0x0200 616 #define LINKENA 0x0100 617 #define DIS_SDSAVE 0x0010 618 619 /* OCP_PHY_STATUS */ 620 #define PHY_STAT_MASK 0x0007 621 #define PHY_STAT_EXT_INIT 2 622 #define PHY_STAT_LAN_ON 3 623 #define PHY_STAT_PWRDN 5 624 625 /* OCP_INTR_EN */ 626 #define INTR_SPEED_FORCE BIT(3) 627 628 /* OCP_NCTL_CFG */ 629 #define PGA_RETURN_EN BIT(1) 630 631 /* OCP_POWER_CFG */ 632 #define EEE_CLKDIV_EN 0x8000 633 #define EN_ALDPS 0x0004 634 #define EN_10M_PLLOFF 0x0001 635 636 /* OCP_EEE_CONFIG1 */ 637 #define RG_TXLPI_MSK_HFDUP 0x8000 638 #define RG_MATCLR_EN 0x4000 639 #define EEE_10_CAP 0x2000 640 #define EEE_NWAY_EN 0x1000 641 #define TX_QUIET_EN 0x0200 642 #define RX_QUIET_EN 0x0100 643 #define sd_rise_time_mask 0x0070 644 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 645 #define RG_RXLPI_MSK_HFDUP 0x0008 646 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 647 648 /* OCP_EEE_CONFIG2 */ 649 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 650 #define RG_DACQUIET_EN 0x0400 651 #define RG_LDVQUIET_EN 0x0200 652 #define RG_CKRSEL 0x0020 653 #define RG_EEEPRG_EN 0x0010 654 655 /* OCP_EEE_CONFIG3 */ 656 #define fast_snr_mask 0xff80 657 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 658 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 659 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 660 661 /* OCP_EEE_AR */ 662 /* bit[15:14] function */ 663 #define FUN_ADDR 0x0000 664 #define FUN_DATA 0x4000 665 /* bit[4:0] device addr */ 666 667 /* OCP_EEE_CFG */ 668 #define CTAP_SHORT_EN 0x0040 669 #define EEE10_EN 0x0010 670 671 /* OCP_DOWN_SPEED */ 672 #define EN_EEE_CMODE BIT(14) 673 #define EN_EEE_1000 BIT(13) 674 #define EN_EEE_100 BIT(12) 675 #define EN_10M_CLKDIV BIT(11) 676 #define EN_10M_BGOFF 0x0080 677 678 /* OCP_10GBT_CTRL */ 679 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ 680 681 /* OCP_PHY_STATE */ 682 #define TXDIS_STATE 0x01 683 #define ABD_STATE 0x02 684 685 /* OCP_PHY_PATCH_STAT */ 686 #define PATCH_READY BIT(6) 687 688 /* OCP_PHY_PATCH_CMD */ 689 #define PATCH_REQUEST BIT(4) 690 691 /* OCP_PHY_LOCK */ 692 #define PATCH_LOCK BIT(0) 693 694 /* OCP_ADC_CFG */ 695 #define CKADSEL_L 0x0100 696 #define ADC_EN 0x0080 697 #define EN_EMI_L 0x0040 698 699 /* OCP_SYSCLK_CFG */ 700 #define sysclk_div_expo(x) (min(x, 5) << 8) 701 #define clk_div_expo(x) (min(x, 5) << 4) 702 703 /* SRAM_GREEN_CFG */ 704 #define GREEN_ETH_EN BIT(15) 705 #define R_TUNE_EN BIT(11) 706 707 /* SRAM_LPF_CFG */ 708 #define LPF_AUTO_TUNE 0x8000 709 710 /* SRAM_10M_AMP1 */ 711 #define GDAC_IB_UPALL 0x0008 712 713 /* SRAM_10M_AMP2 */ 714 #define AMP_DN 0x0200 715 716 /* SRAM_IMPEDANCE */ 717 #define RX_DRIVING_MASK 0x6000 718 719 /* SRAM_PHY_LOCK */ 720 #define PHY_PATCH_LOCK 0x0001 721 722 /* MAC PASSTHRU */ 723 #define AD_MASK 0xfee0 724 #define BND_MASK 0x0004 725 #define BD_MASK 0x0001 726 #define EFUSE 0xcfdb 727 #define PASS_THRU_MASK 0x1 728 729 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ 730 731 enum rtl_register_content { 732 _2500bps = BIT(10), 733 _1250bps = BIT(9), 734 _500bps = BIT(8), 735 _tx_flow = BIT(6), 736 _rx_flow = BIT(5), 737 _1000bps = 0x10, 738 _100bps = 0x08, 739 _10bps = 0x04, 740 LINK_STATUS = 0x02, 741 FULL_DUP = 0x01, 742 }; 743 744 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) 745 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) 746 747 #define RTL8152_MAX_TX 4 748 #define RTL8152_MAX_RX 10 749 #define INTBUFSIZE 2 750 #define TX_ALIGN 4 751 #define RX_ALIGN 8 752 753 #define RTL8152_RX_MAX_PENDING 4096 754 #define RTL8152_RXFG_HEADSZ 256 755 756 #define INTR_LINK 0x0004 757 758 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 759 #define RTL8153_RMS RTL8153_MAX_PACKET 760 #define RTL8152_TX_TIMEOUT (5 * HZ) 761 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) 762 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) 763 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) 764 765 /* rtl8152 flags */ 766 enum rtl8152_flags { 767 RTL8152_UNPLUG = 0, 768 RTL8152_SET_RX_MODE, 769 WORK_ENABLE, 770 RTL8152_LINK_CHG, 771 SELECTIVE_SUSPEND, 772 PHY_RESET, 773 SCHEDULE_TASKLET, 774 GREEN_ETHERNET, 775 RX_EPROTO, 776 }; 777 778 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e 779 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054 780 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082 781 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c 782 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387 783 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062 784 785 struct tally_counter { 786 __le64 tx_packets; 787 __le64 rx_packets; 788 __le64 tx_errors; 789 __le32 rx_errors; 790 __le16 rx_missed; 791 __le16 align_errors; 792 __le32 tx_one_collision; 793 __le32 tx_multi_collision; 794 __le64 rx_unicast; 795 __le64 rx_broadcast; 796 __le32 rx_multicast; 797 __le16 tx_aborted; 798 __le16 tx_underrun; 799 }; 800 801 struct rx_desc { 802 __le32 opts1; 803 #define RX_LEN_MASK 0x7fff 804 805 __le32 opts2; 806 #define RD_UDP_CS BIT(23) 807 #define RD_TCP_CS BIT(22) 808 #define RD_IPV6_CS BIT(20) 809 #define RD_IPV4_CS BIT(19) 810 811 __le32 opts3; 812 #define IPF BIT(23) /* IP checksum fail */ 813 #define UDPF BIT(22) /* UDP checksum fail */ 814 #define TCPF BIT(21) /* TCP checksum fail */ 815 #define RX_VLAN_TAG BIT(16) 816 817 __le32 opts4; 818 __le32 opts5; 819 __le32 opts6; 820 }; 821 822 struct tx_desc { 823 __le32 opts1; 824 #define TX_FS BIT(31) /* First segment of a packet */ 825 #define TX_LS BIT(30) /* Final segment of a packet */ 826 #define GTSENDV4 BIT(28) 827 #define GTSENDV6 BIT(27) 828 #define GTTCPHO_SHIFT 18 829 #define GTTCPHO_MAX 0x7fU 830 #define TX_LEN_MAX 0x3ffffU 831 832 __le32 opts2; 833 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 834 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 835 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 836 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 837 #define MSS_SHIFT 17 838 #define MSS_MAX 0x7ffU 839 #define TCPHO_SHIFT 17 840 #define TCPHO_MAX 0x7ffU 841 #define TX_VLAN_TAG BIT(16) 842 }; 843 844 struct r8152; 845 846 struct rx_agg { 847 struct list_head list, info_list; 848 struct urb *urb; 849 struct r8152 *context; 850 struct page *page; 851 void *buffer; 852 }; 853 854 struct tx_agg { 855 struct list_head list; 856 struct urb *urb; 857 struct r8152 *context; 858 void *buffer; 859 void *head; 860 u32 skb_num; 861 u32 skb_len; 862 }; 863 864 struct r8152 { 865 unsigned long flags; 866 struct usb_device *udev; 867 struct napi_struct napi; 868 struct usb_interface *intf; 869 struct net_device *netdev; 870 struct urb *intr_urb; 871 struct tx_agg tx_info[RTL8152_MAX_TX]; 872 struct list_head rx_info, rx_used; 873 struct list_head rx_done, tx_free; 874 struct sk_buff_head tx_queue, rx_queue; 875 spinlock_t rx_lock, tx_lock; 876 struct delayed_work schedule, hw_phy_work; 877 struct mii_if_info mii; 878 struct mutex control; /* use for hw setting */ 879 #ifdef CONFIG_PM_SLEEP 880 struct notifier_block pm_notifier; 881 #endif 882 struct tasklet_struct tx_tl; 883 884 struct rtl_ops { 885 void (*init)(struct r8152 *tp); 886 int (*enable)(struct r8152 *tp); 887 void (*disable)(struct r8152 *tp); 888 void (*up)(struct r8152 *tp); 889 void (*down)(struct r8152 *tp); 890 void (*unload)(struct r8152 *tp); 891 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee); 892 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee); 893 bool (*in_nway)(struct r8152 *tp); 894 void (*hw_phy_cfg)(struct r8152 *tp); 895 void (*autosuspend_en)(struct r8152 *tp, bool enable); 896 void (*change_mtu)(struct r8152 *tp); 897 } rtl_ops; 898 899 struct ups_info { 900 u32 r_tune:1; 901 u32 _10m_ckdiv:1; 902 u32 _250m_ckdiv:1; 903 u32 aldps:1; 904 u32 lite_mode:2; 905 u32 speed_duplex:4; 906 u32 eee:1; 907 u32 eee_lite:1; 908 u32 eee_ckdiv:1; 909 u32 eee_plloff_100:1; 910 u32 eee_plloff_giga:1; 911 u32 eee_cmod_lv:1; 912 u32 green:1; 913 u32 flow_control:1; 914 u32 ctap_short_off:1; 915 } ups_info; 916 917 #define RTL_VER_SIZE 32 918 919 struct rtl_fw { 920 const char *fw_name; 921 const struct firmware *fw; 922 923 char version[RTL_VER_SIZE]; 924 int (*pre_fw)(struct r8152 *tp); 925 int (*post_fw)(struct r8152 *tp); 926 927 bool retry; 928 } rtl_fw; 929 930 atomic_t rx_count; 931 932 bool eee_en; 933 int intr_interval; 934 u32 saved_wolopts; 935 u32 msg_enable; 936 u32 tx_qlen; 937 u32 coalesce; 938 u32 advertising; 939 u32 rx_buf_sz; 940 u32 rx_copybreak; 941 u32 rx_pending; 942 u32 fc_pause_on, fc_pause_off; 943 944 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; 945 946 u32 support_2500full:1; 947 u32 lenovo_macpassthru:1; 948 u32 dell_tb_rx_agg_bug:1; 949 u16 ocp_base; 950 u16 speed; 951 u16 eee_adv; 952 u8 *intr_buff; 953 u8 version; 954 u8 duplex; 955 u8 autoneg; 956 }; 957 958 /** 959 * struct fw_block - block type and total length 960 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA, 961 * RTL_FW_USB and so on. 962 * @length: total length of the current block. 963 */ 964 struct fw_block { 965 __le32 type; 966 __le32 length; 967 } __packed; 968 969 /** 970 * struct fw_header - header of the firmware file 971 * @checksum: checksum of sha256 which is calculated from the whole file 972 * except the checksum field of the file. That is, calculate sha256 973 * from the version field to the end of the file. 974 * @version: version of this firmware. 975 * @blocks: the first firmware block of the file 976 */ 977 struct fw_header { 978 u8 checksum[32]; 979 char version[RTL_VER_SIZE]; 980 struct fw_block blocks[]; 981 } __packed; 982 983 enum rtl8152_fw_flags { 984 FW_FLAGS_USB = 0, 985 FW_FLAGS_PLA, 986 FW_FLAGS_START, 987 FW_FLAGS_STOP, 988 FW_FLAGS_NC, 989 FW_FLAGS_NC1, 990 FW_FLAGS_NC2, 991 FW_FLAGS_UC2, 992 FW_FLAGS_UC, 993 FW_FLAGS_SPEED_UP, 994 FW_FLAGS_VER, 995 }; 996 997 enum rtl8152_fw_fixup_cmd { 998 FW_FIXUP_AND = 0, 999 FW_FIXUP_OR, 1000 FW_FIXUP_NOT, 1001 FW_FIXUP_XOR, 1002 }; 1003 1004 struct fw_phy_set { 1005 __le16 addr; 1006 __le16 data; 1007 } __packed; 1008 1009 struct fw_phy_speed_up { 1010 struct fw_block blk_hdr; 1011 __le16 fw_offset; 1012 __le16 version; 1013 __le16 fw_reg; 1014 __le16 reserved; 1015 char info[]; 1016 } __packed; 1017 1018 struct fw_phy_ver { 1019 struct fw_block blk_hdr; 1020 struct fw_phy_set ver; 1021 __le32 reserved; 1022 } __packed; 1023 1024 struct fw_phy_fixup { 1025 struct fw_block blk_hdr; 1026 struct fw_phy_set setting; 1027 __le16 bit_cmd; 1028 __le16 reserved; 1029 } __packed; 1030 1031 struct fw_phy_union { 1032 struct fw_block blk_hdr; 1033 __le16 fw_offset; 1034 __le16 fw_reg; 1035 struct fw_phy_set pre_set[2]; 1036 struct fw_phy_set bp[8]; 1037 struct fw_phy_set bp_en; 1038 u8 pre_num; 1039 u8 bp_num; 1040 char info[]; 1041 } __packed; 1042 1043 /** 1044 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. 1045 * The layout of the firmware block is: 1046 * <struct fw_mac> + <info> + <firmware data>. 1047 * @blk_hdr: firmware descriptor (type, length) 1048 * @fw_offset: offset of the firmware binary data. The start address of 1049 * the data would be the address of struct fw_mac + @fw_offset. 1050 * @fw_reg: the register to load the firmware. Depends on chip. 1051 * @bp_ba_addr: the register to write break point base address. Depends on 1052 * chip. 1053 * @bp_ba_value: break point base address. Depends on chip. 1054 * @bp_en_addr: the register to write break point enabled mask. Depends 1055 * on chip. 1056 * @bp_en_value: break point enabled mask. Depends on the firmware. 1057 * @bp_start: the start register of break points. Depends on chip. 1058 * @bp_num: the break point number which needs to be set for this firmware. 1059 * Depends on the firmware. 1060 * @bp: break points. Depends on firmware. 1061 * @reserved: reserved space (unused) 1062 * @fw_ver_reg: the register to store the fw version. 1063 * @fw_ver_data: the firmware version of the current type. 1064 * @info: additional information for debugging, and is followed by the 1065 * binary data of firmware. 1066 */ 1067 struct fw_mac { 1068 struct fw_block blk_hdr; 1069 __le16 fw_offset; 1070 __le16 fw_reg; 1071 __le16 bp_ba_addr; 1072 __le16 bp_ba_value; 1073 __le16 bp_en_addr; 1074 __le16 bp_en_value; 1075 __le16 bp_start; 1076 __le16 bp_num; 1077 __le16 bp[16]; /* any value determined by firmware */ 1078 __le32 reserved; 1079 __le16 fw_ver_reg; 1080 u8 fw_ver_data; 1081 char info[]; 1082 } __packed; 1083 1084 /** 1085 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. 1086 * This is used to set patch key when loading the firmware of PHY. 1087 * @blk_hdr: firmware descriptor (type, length) 1088 * @key_reg: the register to write the patch key. 1089 * @key_data: patch key. 1090 * @reserved: reserved space (unused) 1091 */ 1092 struct fw_phy_patch_key { 1093 struct fw_block blk_hdr; 1094 __le16 key_reg; 1095 __le16 key_data; 1096 __le32 reserved; 1097 } __packed; 1098 1099 /** 1100 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. 1101 * The layout of the firmware block is: 1102 * <struct fw_phy_nc> + <info> + <firmware data>. 1103 * @blk_hdr: firmware descriptor (type, length) 1104 * @fw_offset: offset of the firmware binary data. The start address of 1105 * the data would be the address of struct fw_phy_nc + @fw_offset. 1106 * @fw_reg: the register to load the firmware. Depends on chip. 1107 * @ba_reg: the register to write the base address. Depends on chip. 1108 * @ba_data: base address. Depends on chip. 1109 * @patch_en_addr: the register of enabling patch mode. Depends on chip. 1110 * @patch_en_value: patch mode enabled mask. Depends on the firmware. 1111 * @mode_reg: the regitster of switching the mode. 1112 * @mode_pre: the mode needing to be set before loading the firmware. 1113 * @mode_post: the mode to be set when finishing to load the firmware. 1114 * @reserved: reserved space (unused) 1115 * @bp_start: the start register of break points. Depends on chip. 1116 * @bp_num: the break point number which needs to be set for this firmware. 1117 * Depends on the firmware. 1118 * @bp: break points. Depends on firmware. 1119 * @info: additional information for debugging, and is followed by the 1120 * binary data of firmware. 1121 */ 1122 struct fw_phy_nc { 1123 struct fw_block blk_hdr; 1124 __le16 fw_offset; 1125 __le16 fw_reg; 1126 __le16 ba_reg; 1127 __le16 ba_data; 1128 __le16 patch_en_addr; 1129 __le16 patch_en_value; 1130 __le16 mode_reg; 1131 __le16 mode_pre; 1132 __le16 mode_post; 1133 __le16 reserved; 1134 __le16 bp_start; 1135 __le16 bp_num; 1136 __le16 bp[4]; 1137 char info[]; 1138 } __packed; 1139 1140 enum rtl_fw_type { 1141 RTL_FW_END = 0, 1142 RTL_FW_PLA, 1143 RTL_FW_USB, 1144 RTL_FW_PHY_START, 1145 RTL_FW_PHY_STOP, 1146 RTL_FW_PHY_NC, 1147 RTL_FW_PHY_FIXUP, 1148 RTL_FW_PHY_UNION_NC, 1149 RTL_FW_PHY_UNION_NC1, 1150 RTL_FW_PHY_UNION_NC2, 1151 RTL_FW_PHY_UNION_UC2, 1152 RTL_FW_PHY_UNION_UC, 1153 RTL_FW_PHY_UNION_MISC, 1154 RTL_FW_PHY_SPEED_UP, 1155 RTL_FW_PHY_VER, 1156 }; 1157 1158 enum rtl_version { 1159 RTL_VER_UNKNOWN = 0, 1160 RTL_VER_01, 1161 RTL_VER_02, 1162 RTL_VER_03, 1163 RTL_VER_04, 1164 RTL_VER_05, 1165 RTL_VER_06, 1166 RTL_VER_07, 1167 RTL_VER_08, 1168 RTL_VER_09, 1169 1170 RTL_TEST_01, 1171 RTL_VER_10, 1172 RTL_VER_11, 1173 RTL_VER_12, 1174 RTL_VER_13, 1175 RTL_VER_14, 1176 RTL_VER_15, 1177 1178 RTL_VER_MAX 1179 }; 1180 1181 enum tx_csum_stat { 1182 TX_CSUM_SUCCESS = 0, 1183 TX_CSUM_TSO, 1184 TX_CSUM_NONE 1185 }; 1186 1187 #define RTL_ADVERTISED_10_HALF BIT(0) 1188 #define RTL_ADVERTISED_10_FULL BIT(1) 1189 #define RTL_ADVERTISED_100_HALF BIT(2) 1190 #define RTL_ADVERTISED_100_FULL BIT(3) 1191 #define RTL_ADVERTISED_1000_HALF BIT(4) 1192 #define RTL_ADVERTISED_1000_FULL BIT(5) 1193 #define RTL_ADVERTISED_2500_FULL BIT(6) 1194 1195 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 1196 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 1197 */ 1198 static const int multicast_filter_limit = 32; 1199 static unsigned int agg_buf_sz = 16384; 1200 1201 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) 1202 1203 static 1204 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 1205 { 1206 int ret; 1207 void *tmp; 1208 1209 tmp = kmalloc(size, GFP_KERNEL); 1210 if (!tmp) 1211 return -ENOMEM; 1212 1213 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in, 1214 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 1215 value, index, tmp, size, 500); 1216 if (ret < 0) 1217 memset(data, 0xff, size); 1218 else 1219 memcpy(data, tmp, size); 1220 1221 kfree(tmp); 1222 1223 return ret; 1224 } 1225 1226 static 1227 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 1228 { 1229 int ret; 1230 void *tmp; 1231 1232 tmp = kmemdup(data, size, GFP_KERNEL); 1233 if (!tmp) 1234 return -ENOMEM; 1235 1236 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out, 1237 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 1238 value, index, tmp, size, 500); 1239 1240 kfree(tmp); 1241 1242 return ret; 1243 } 1244 1245 static void rtl_set_unplug(struct r8152 *tp) 1246 { 1247 if (tp->udev->state == USB_STATE_NOTATTACHED) { 1248 set_bit(RTL8152_UNPLUG, &tp->flags); 1249 smp_mb__after_atomic(); 1250 } 1251 } 1252 1253 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 1254 void *data, u16 type) 1255 { 1256 u16 limit = 64; 1257 int ret = 0; 1258 1259 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1260 return -ENODEV; 1261 1262 /* both size and indix must be 4 bytes align */ 1263 if ((size & 3) || !size || (index & 3) || !data) 1264 return -EPERM; 1265 1266 if ((u32)index + (u32)size > 0xffff) 1267 return -EPERM; 1268 1269 while (size) { 1270 if (size > limit) { 1271 ret = get_registers(tp, index, type, limit, data); 1272 if (ret < 0) 1273 break; 1274 1275 index += limit; 1276 data += limit; 1277 size -= limit; 1278 } else { 1279 ret = get_registers(tp, index, type, size, data); 1280 if (ret < 0) 1281 break; 1282 1283 index += size; 1284 data += size; 1285 size = 0; 1286 break; 1287 } 1288 } 1289 1290 if (ret == -ENODEV) 1291 rtl_set_unplug(tp); 1292 1293 return ret; 1294 } 1295 1296 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 1297 u16 size, void *data, u16 type) 1298 { 1299 int ret; 1300 u16 byteen_start, byteen_end, byen; 1301 u16 limit = 512; 1302 1303 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1304 return -ENODEV; 1305 1306 /* both size and indix must be 4 bytes align */ 1307 if ((size & 3) || !size || (index & 3) || !data) 1308 return -EPERM; 1309 1310 if ((u32)index + (u32)size > 0xffff) 1311 return -EPERM; 1312 1313 byteen_start = byteen & BYTE_EN_START_MASK; 1314 byteen_end = byteen & BYTE_EN_END_MASK; 1315 1316 byen = byteen_start | (byteen_start << 4); 1317 ret = set_registers(tp, index, type | byen, 4, data); 1318 if (ret < 0) 1319 goto error1; 1320 1321 index += 4; 1322 data += 4; 1323 size -= 4; 1324 1325 if (size) { 1326 size -= 4; 1327 1328 while (size) { 1329 if (size > limit) { 1330 ret = set_registers(tp, index, 1331 type | BYTE_EN_DWORD, 1332 limit, data); 1333 if (ret < 0) 1334 goto error1; 1335 1336 index += limit; 1337 data += limit; 1338 size -= limit; 1339 } else { 1340 ret = set_registers(tp, index, 1341 type | BYTE_EN_DWORD, 1342 size, data); 1343 if (ret < 0) 1344 goto error1; 1345 1346 index += size; 1347 data += size; 1348 size = 0; 1349 break; 1350 } 1351 } 1352 1353 byen = byteen_end | (byteen_end >> 4); 1354 ret = set_registers(tp, index, type | byen, 4, data); 1355 if (ret < 0) 1356 goto error1; 1357 } 1358 1359 error1: 1360 if (ret == -ENODEV) 1361 rtl_set_unplug(tp); 1362 1363 return ret; 1364 } 1365 1366 static inline 1367 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 1368 { 1369 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 1370 } 1371 1372 static inline 1373 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 1374 { 1375 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 1376 } 1377 1378 static inline 1379 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 1380 { 1381 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 1382 } 1383 1384 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 1385 { 1386 __le32 data; 1387 1388 generic_ocp_read(tp, index, sizeof(data), &data, type); 1389 1390 return __le32_to_cpu(data); 1391 } 1392 1393 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 1394 { 1395 __le32 tmp = __cpu_to_le32(data); 1396 1397 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 1398 } 1399 1400 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 1401 { 1402 u32 data; 1403 __le32 tmp; 1404 u16 byen = BYTE_EN_WORD; 1405 u8 shift = index & 2; 1406 1407 index &= ~3; 1408 byen <<= shift; 1409 1410 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 1411 1412 data = __le32_to_cpu(tmp); 1413 data >>= (shift * 8); 1414 data &= 0xffff; 1415 1416 return (u16)data; 1417 } 1418 1419 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1420 { 1421 u32 mask = 0xffff; 1422 __le32 tmp; 1423 u16 byen = BYTE_EN_WORD; 1424 u8 shift = index & 2; 1425 1426 data &= mask; 1427 1428 if (index & 2) { 1429 byen <<= shift; 1430 mask <<= (shift * 8); 1431 data <<= (shift * 8); 1432 index &= ~3; 1433 } 1434 1435 tmp = __cpu_to_le32(data); 1436 1437 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1438 } 1439 1440 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1441 { 1442 u32 data; 1443 __le32 tmp; 1444 u8 shift = index & 3; 1445 1446 index &= ~3; 1447 1448 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1449 1450 data = __le32_to_cpu(tmp); 1451 data >>= (shift * 8); 1452 data &= 0xff; 1453 1454 return (u8)data; 1455 } 1456 1457 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1458 { 1459 u32 mask = 0xff; 1460 __le32 tmp; 1461 u16 byen = BYTE_EN_BYTE; 1462 u8 shift = index & 3; 1463 1464 data &= mask; 1465 1466 if (index & 3) { 1467 byen <<= shift; 1468 mask <<= (shift * 8); 1469 data <<= (shift * 8); 1470 index &= ~3; 1471 } 1472 1473 tmp = __cpu_to_le32(data); 1474 1475 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1476 } 1477 1478 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1479 { 1480 u16 ocp_base, ocp_index; 1481 1482 ocp_base = addr & 0xf000; 1483 if (ocp_base != tp->ocp_base) { 1484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1485 tp->ocp_base = ocp_base; 1486 } 1487 1488 ocp_index = (addr & 0x0fff) | 0xb000; 1489 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1490 } 1491 1492 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1493 { 1494 u16 ocp_base, ocp_index; 1495 1496 ocp_base = addr & 0xf000; 1497 if (ocp_base != tp->ocp_base) { 1498 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1499 tp->ocp_base = ocp_base; 1500 } 1501 1502 ocp_index = (addr & 0x0fff) | 0xb000; 1503 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1504 } 1505 1506 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1507 { 1508 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1509 } 1510 1511 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1512 { 1513 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1514 } 1515 1516 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1517 { 1518 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1519 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1520 } 1521 1522 static u16 sram_read(struct r8152 *tp, u16 addr) 1523 { 1524 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1525 return ocp_reg_read(tp, OCP_SRAM_DATA); 1526 } 1527 1528 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1529 { 1530 struct r8152 *tp = netdev_priv(netdev); 1531 int ret; 1532 1533 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1534 return -ENODEV; 1535 1536 if (phy_id != R8152_PHY_ID) 1537 return -EINVAL; 1538 1539 ret = r8152_mdio_read(tp, reg); 1540 1541 return ret; 1542 } 1543 1544 static 1545 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1546 { 1547 struct r8152 *tp = netdev_priv(netdev); 1548 1549 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1550 return; 1551 1552 if (phy_id != R8152_PHY_ID) 1553 return; 1554 1555 r8152_mdio_write(tp, reg, val); 1556 } 1557 1558 static int 1559 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1560 1561 static int 1562 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, 1563 u32 advertising); 1564 1565 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p, 1566 bool in_resume) 1567 { 1568 struct r8152 *tp = netdev_priv(netdev); 1569 struct sockaddr *addr = p; 1570 int ret = -EADDRNOTAVAIL; 1571 1572 if (!is_valid_ether_addr(addr->sa_data)) 1573 goto out1; 1574 1575 if (!in_resume) { 1576 ret = usb_autopm_get_interface(tp->intf); 1577 if (ret < 0) 1578 goto out1; 1579 } 1580 1581 mutex_lock(&tp->control); 1582 1583 eth_hw_addr_set(netdev, addr->sa_data); 1584 1585 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1586 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1587 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1588 1589 mutex_unlock(&tp->control); 1590 1591 if (!in_resume) 1592 usb_autopm_put_interface(tp->intf); 1593 out1: 1594 return ret; 1595 } 1596 1597 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1598 { 1599 return __rtl8152_set_mac_address(netdev, p, false); 1600 } 1601 1602 /* Devices containing proper chips can support a persistent 1603 * host system provided MAC address. 1604 * Examples of this are Dell TB15 and Dell WD15 docks 1605 */ 1606 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1607 { 1608 acpi_status status; 1609 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1610 union acpi_object *obj; 1611 int ret = -EINVAL; 1612 u32 ocp_data; 1613 unsigned char buf[6]; 1614 char *mac_obj_name; 1615 acpi_object_type mac_obj_type; 1616 int mac_strlen; 1617 1618 if (tp->lenovo_macpassthru) { 1619 mac_obj_name = "\\MACA"; 1620 mac_obj_type = ACPI_TYPE_STRING; 1621 mac_strlen = 0x16; 1622 } else { 1623 /* test for -AD variant of RTL8153 */ 1624 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1625 if ((ocp_data & AD_MASK) == 0x1000) { 1626 /* test for MAC address pass-through bit */ 1627 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1628 if ((ocp_data & PASS_THRU_MASK) != 1) { 1629 netif_dbg(tp, probe, tp->netdev, 1630 "No efuse for RTL8153-AD MAC pass through\n"); 1631 return -ENODEV; 1632 } 1633 } else { 1634 /* test for RTL8153-BND and RTL8153-BD */ 1635 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1636 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1637 netif_dbg(tp, probe, tp->netdev, 1638 "Invalid variant for MAC pass through\n"); 1639 return -ENODEV; 1640 } 1641 } 1642 1643 mac_obj_name = "\\_SB.AMAC"; 1644 mac_obj_type = ACPI_TYPE_BUFFER; 1645 mac_strlen = 0x17; 1646 } 1647 1648 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1649 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); 1650 obj = (union acpi_object *)buffer.pointer; 1651 if (!ACPI_SUCCESS(status)) 1652 return -ENODEV; 1653 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { 1654 netif_warn(tp, probe, tp->netdev, 1655 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1656 obj->type, obj->string.length); 1657 goto amacout; 1658 } 1659 1660 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1661 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1662 netif_warn(tp, probe, tp->netdev, 1663 "Invalid header when reading pass-thru MAC addr\n"); 1664 goto amacout; 1665 } 1666 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1667 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1668 netif_warn(tp, probe, tp->netdev, 1669 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1670 ret, buf); 1671 ret = -EINVAL; 1672 goto amacout; 1673 } 1674 memcpy(sa->sa_data, buf, 6); 1675 netif_info(tp, probe, tp->netdev, 1676 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1677 1678 amacout: 1679 kfree(obj); 1680 return ret; 1681 } 1682 1683 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1684 { 1685 struct net_device *dev = tp->netdev; 1686 int ret; 1687 1688 sa->sa_family = dev->type; 1689 1690 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data); 1691 if (ret < 0) { 1692 if (tp->version == RTL_VER_01) { 1693 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1694 } else { 1695 /* if device doesn't support MAC pass through this will 1696 * be expected to be non-zero 1697 */ 1698 ret = vendor_mac_passthru_addr_read(tp, sa); 1699 if (ret < 0) 1700 ret = pla_ocp_read(tp, PLA_BACKUP, 8, 1701 sa->sa_data); 1702 } 1703 } 1704 1705 if (ret < 0) { 1706 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1707 } else if (!is_valid_ether_addr(sa->sa_data)) { 1708 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1709 sa->sa_data); 1710 eth_hw_addr_random(dev); 1711 ether_addr_copy(sa->sa_data, dev->dev_addr); 1712 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1713 sa->sa_data); 1714 return 0; 1715 } 1716 1717 return ret; 1718 } 1719 1720 static int set_ethernet_addr(struct r8152 *tp, bool in_resume) 1721 { 1722 struct net_device *dev = tp->netdev; 1723 struct sockaddr sa; 1724 int ret; 1725 1726 ret = determine_ethernet_addr(tp, &sa); 1727 if (ret < 0) 1728 return ret; 1729 1730 if (tp->version == RTL_VER_01) 1731 eth_hw_addr_set(dev, sa.sa_data); 1732 else 1733 ret = __rtl8152_set_mac_address(dev, &sa, in_resume); 1734 1735 return ret; 1736 } 1737 1738 static void read_bulk_callback(struct urb *urb) 1739 { 1740 struct net_device *netdev; 1741 int status = urb->status; 1742 struct rx_agg *agg; 1743 struct r8152 *tp; 1744 unsigned long flags; 1745 1746 agg = urb->context; 1747 if (!agg) 1748 return; 1749 1750 tp = agg->context; 1751 if (!tp) 1752 return; 1753 1754 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1755 return; 1756 1757 if (!test_bit(WORK_ENABLE, &tp->flags)) 1758 return; 1759 1760 netdev = tp->netdev; 1761 1762 /* When link down, the driver would cancel all bulks. */ 1763 /* This avoid the re-submitting bulk */ 1764 if (!netif_carrier_ok(netdev)) 1765 return; 1766 1767 usb_mark_last_busy(tp->udev); 1768 1769 switch (status) { 1770 case 0: 1771 if (urb->actual_length < ETH_ZLEN) 1772 break; 1773 1774 spin_lock_irqsave(&tp->rx_lock, flags); 1775 list_add_tail(&agg->list, &tp->rx_done); 1776 spin_unlock_irqrestore(&tp->rx_lock, flags); 1777 napi_schedule(&tp->napi); 1778 return; 1779 case -ESHUTDOWN: 1780 rtl_set_unplug(tp); 1781 netif_device_detach(tp->netdev); 1782 return; 1783 case -EPROTO: 1784 urb->actual_length = 0; 1785 spin_lock_irqsave(&tp->rx_lock, flags); 1786 list_add_tail(&agg->list, &tp->rx_done); 1787 spin_unlock_irqrestore(&tp->rx_lock, flags); 1788 set_bit(RX_EPROTO, &tp->flags); 1789 schedule_delayed_work(&tp->schedule, 1); 1790 return; 1791 case -ENOENT: 1792 return; /* the urb is in unlink state */ 1793 case -ETIME: 1794 if (net_ratelimit()) 1795 netdev_warn(netdev, "maybe reset is needed?\n"); 1796 break; 1797 default: 1798 if (net_ratelimit()) 1799 netdev_warn(netdev, "Rx status %d\n", status); 1800 break; 1801 } 1802 1803 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1804 } 1805 1806 static void write_bulk_callback(struct urb *urb) 1807 { 1808 struct net_device_stats *stats; 1809 struct net_device *netdev; 1810 struct tx_agg *agg; 1811 struct r8152 *tp; 1812 unsigned long flags; 1813 int status = urb->status; 1814 1815 agg = urb->context; 1816 if (!agg) 1817 return; 1818 1819 tp = agg->context; 1820 if (!tp) 1821 return; 1822 1823 netdev = tp->netdev; 1824 stats = &netdev->stats; 1825 if (status) { 1826 if (net_ratelimit()) 1827 netdev_warn(netdev, "Tx status %d\n", status); 1828 stats->tx_errors += agg->skb_num; 1829 } else { 1830 stats->tx_packets += agg->skb_num; 1831 stats->tx_bytes += agg->skb_len; 1832 } 1833 1834 spin_lock_irqsave(&tp->tx_lock, flags); 1835 list_add_tail(&agg->list, &tp->tx_free); 1836 spin_unlock_irqrestore(&tp->tx_lock, flags); 1837 1838 usb_autopm_put_interface_async(tp->intf); 1839 1840 if (!netif_carrier_ok(netdev)) 1841 return; 1842 1843 if (!test_bit(WORK_ENABLE, &tp->flags)) 1844 return; 1845 1846 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1847 return; 1848 1849 if (!skb_queue_empty(&tp->tx_queue)) 1850 tasklet_schedule(&tp->tx_tl); 1851 } 1852 1853 static void intr_callback(struct urb *urb) 1854 { 1855 struct r8152 *tp; 1856 __le16 *d; 1857 int status = urb->status; 1858 int res; 1859 1860 tp = urb->context; 1861 if (!tp) 1862 return; 1863 1864 if (!test_bit(WORK_ENABLE, &tp->flags)) 1865 return; 1866 1867 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1868 return; 1869 1870 switch (status) { 1871 case 0: /* success */ 1872 break; 1873 case -ECONNRESET: /* unlink */ 1874 case -ESHUTDOWN: 1875 netif_device_detach(tp->netdev); 1876 fallthrough; 1877 case -ENOENT: 1878 case -EPROTO: 1879 netif_info(tp, intr, tp->netdev, 1880 "Stop submitting intr, status %d\n", status); 1881 return; 1882 case -EOVERFLOW: 1883 if (net_ratelimit()) 1884 netif_info(tp, intr, tp->netdev, 1885 "intr status -EOVERFLOW\n"); 1886 goto resubmit; 1887 /* -EPIPE: should clear the halt */ 1888 default: 1889 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1890 goto resubmit; 1891 } 1892 1893 d = urb->transfer_buffer; 1894 if (INTR_LINK & __le16_to_cpu(d[0])) { 1895 if (!netif_carrier_ok(tp->netdev)) { 1896 set_bit(RTL8152_LINK_CHG, &tp->flags); 1897 schedule_delayed_work(&tp->schedule, 0); 1898 } 1899 } else { 1900 if (netif_carrier_ok(tp->netdev)) { 1901 netif_stop_queue(tp->netdev); 1902 set_bit(RTL8152_LINK_CHG, &tp->flags); 1903 schedule_delayed_work(&tp->schedule, 0); 1904 } 1905 } 1906 1907 resubmit: 1908 res = usb_submit_urb(urb, GFP_ATOMIC); 1909 if (res == -ENODEV) { 1910 rtl_set_unplug(tp); 1911 netif_device_detach(tp->netdev); 1912 } else if (res) { 1913 netif_err(tp, intr, tp->netdev, 1914 "can't resubmit intr, status %d\n", res); 1915 } 1916 } 1917 1918 static inline void *rx_agg_align(void *data) 1919 { 1920 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1921 } 1922 1923 static inline void *tx_agg_align(void *data) 1924 { 1925 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1926 } 1927 1928 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) 1929 { 1930 list_del(&agg->info_list); 1931 1932 usb_free_urb(agg->urb); 1933 put_page(agg->page); 1934 kfree(agg); 1935 1936 atomic_dec(&tp->rx_count); 1937 } 1938 1939 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) 1940 { 1941 struct net_device *netdev = tp->netdev; 1942 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1943 unsigned int order = get_order(tp->rx_buf_sz); 1944 struct rx_agg *rx_agg; 1945 unsigned long flags; 1946 1947 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); 1948 if (!rx_agg) 1949 return NULL; 1950 1951 rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order); 1952 if (!rx_agg->page) 1953 goto free_rx; 1954 1955 rx_agg->buffer = page_address(rx_agg->page); 1956 1957 rx_agg->urb = usb_alloc_urb(0, mflags); 1958 if (!rx_agg->urb) 1959 goto free_buf; 1960 1961 rx_agg->context = tp; 1962 1963 INIT_LIST_HEAD(&rx_agg->list); 1964 INIT_LIST_HEAD(&rx_agg->info_list); 1965 spin_lock_irqsave(&tp->rx_lock, flags); 1966 list_add_tail(&rx_agg->info_list, &tp->rx_info); 1967 spin_unlock_irqrestore(&tp->rx_lock, flags); 1968 1969 atomic_inc(&tp->rx_count); 1970 1971 return rx_agg; 1972 1973 free_buf: 1974 __free_pages(rx_agg->page, order); 1975 free_rx: 1976 kfree(rx_agg); 1977 return NULL; 1978 } 1979 1980 static void free_all_mem(struct r8152 *tp) 1981 { 1982 struct rx_agg *agg, *agg_next; 1983 unsigned long flags; 1984 int i; 1985 1986 spin_lock_irqsave(&tp->rx_lock, flags); 1987 1988 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) 1989 free_rx_agg(tp, agg); 1990 1991 spin_unlock_irqrestore(&tp->rx_lock, flags); 1992 1993 WARN_ON(atomic_read(&tp->rx_count)); 1994 1995 for (i = 0; i < RTL8152_MAX_TX; i++) { 1996 usb_free_urb(tp->tx_info[i].urb); 1997 tp->tx_info[i].urb = NULL; 1998 1999 kfree(tp->tx_info[i].buffer); 2000 tp->tx_info[i].buffer = NULL; 2001 tp->tx_info[i].head = NULL; 2002 } 2003 2004 usb_free_urb(tp->intr_urb); 2005 tp->intr_urb = NULL; 2006 2007 kfree(tp->intr_buff); 2008 tp->intr_buff = NULL; 2009 } 2010 2011 static int alloc_all_mem(struct r8152 *tp) 2012 { 2013 struct net_device *netdev = tp->netdev; 2014 struct usb_interface *intf = tp->intf; 2015 struct usb_host_interface *alt = intf->cur_altsetting; 2016 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 2017 int node, i; 2018 2019 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 2020 2021 spin_lock_init(&tp->rx_lock); 2022 spin_lock_init(&tp->tx_lock); 2023 INIT_LIST_HEAD(&tp->rx_info); 2024 INIT_LIST_HEAD(&tp->tx_free); 2025 INIT_LIST_HEAD(&tp->rx_done); 2026 skb_queue_head_init(&tp->tx_queue); 2027 skb_queue_head_init(&tp->rx_queue); 2028 atomic_set(&tp->rx_count, 0); 2029 2030 for (i = 0; i < RTL8152_MAX_RX; i++) { 2031 if (!alloc_rx_agg(tp, GFP_KERNEL)) 2032 goto err1; 2033 } 2034 2035 for (i = 0; i < RTL8152_MAX_TX; i++) { 2036 struct urb *urb; 2037 u8 *buf; 2038 2039 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 2040 if (!buf) 2041 goto err1; 2042 2043 if (buf != tx_agg_align(buf)) { 2044 kfree(buf); 2045 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 2046 node); 2047 if (!buf) 2048 goto err1; 2049 } 2050 2051 urb = usb_alloc_urb(0, GFP_KERNEL); 2052 if (!urb) { 2053 kfree(buf); 2054 goto err1; 2055 } 2056 2057 INIT_LIST_HEAD(&tp->tx_info[i].list); 2058 tp->tx_info[i].context = tp; 2059 tp->tx_info[i].urb = urb; 2060 tp->tx_info[i].buffer = buf; 2061 tp->tx_info[i].head = tx_agg_align(buf); 2062 2063 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 2064 } 2065 2066 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 2067 if (!tp->intr_urb) 2068 goto err1; 2069 2070 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 2071 if (!tp->intr_buff) 2072 goto err1; 2073 2074 tp->intr_interval = (int)ep_intr->desc.bInterval; 2075 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr, 2076 tp->intr_buff, INTBUFSIZE, intr_callback, 2077 tp, tp->intr_interval); 2078 2079 return 0; 2080 2081 err1: 2082 free_all_mem(tp); 2083 return -ENOMEM; 2084 } 2085 2086 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 2087 { 2088 struct tx_agg *agg = NULL; 2089 unsigned long flags; 2090 2091 if (list_empty(&tp->tx_free)) 2092 return NULL; 2093 2094 spin_lock_irqsave(&tp->tx_lock, flags); 2095 if (!list_empty(&tp->tx_free)) { 2096 struct list_head *cursor; 2097 2098 cursor = tp->tx_free.next; 2099 list_del_init(cursor); 2100 agg = list_entry(cursor, struct tx_agg, list); 2101 } 2102 spin_unlock_irqrestore(&tp->tx_lock, flags); 2103 2104 return agg; 2105 } 2106 2107 /* r8152_csum_workaround() 2108 * The hw limits the value of the transport offset. When the offset is out of 2109 * range, calculate the checksum by sw. 2110 */ 2111 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 2112 struct sk_buff_head *list) 2113 { 2114 if (skb_shinfo(skb)->gso_size) { 2115 netdev_features_t features = tp->netdev->features; 2116 struct sk_buff *segs, *seg, *next; 2117 struct sk_buff_head seg_list; 2118 2119 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 2120 segs = skb_gso_segment(skb, features); 2121 if (IS_ERR(segs) || !segs) 2122 goto drop; 2123 2124 __skb_queue_head_init(&seg_list); 2125 2126 skb_list_walk_safe(segs, seg, next) { 2127 skb_mark_not_on_list(seg); 2128 __skb_queue_tail(&seg_list, seg); 2129 } 2130 2131 skb_queue_splice(&seg_list, list); 2132 dev_kfree_skb(skb); 2133 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 2134 if (skb_checksum_help(skb) < 0) 2135 goto drop; 2136 2137 __skb_queue_head(list, skb); 2138 } else { 2139 struct net_device_stats *stats; 2140 2141 drop: 2142 stats = &tp->netdev->stats; 2143 stats->tx_dropped++; 2144 dev_kfree_skb(skb); 2145 } 2146 } 2147 2148 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 2149 { 2150 if (skb_vlan_tag_present(skb)) { 2151 u32 opts2; 2152 2153 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 2154 desc->opts2 |= cpu_to_le32(opts2); 2155 } 2156 } 2157 2158 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 2159 { 2160 u32 opts2 = le32_to_cpu(desc->opts2); 2161 2162 if (opts2 & RX_VLAN_TAG) 2163 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2164 swab16(opts2 & 0xffff)); 2165 } 2166 2167 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 2168 struct sk_buff *skb, u32 len) 2169 { 2170 u32 mss = skb_shinfo(skb)->gso_size; 2171 u32 opts1, opts2 = 0; 2172 int ret = TX_CSUM_SUCCESS; 2173 2174 WARN_ON_ONCE(len > TX_LEN_MAX); 2175 2176 opts1 = len | TX_FS | TX_LS; 2177 2178 if (mss) { 2179 u32 transport_offset = (u32)skb_transport_offset(skb); 2180 2181 if (transport_offset > GTTCPHO_MAX) { 2182 netif_warn(tp, tx_err, tp->netdev, 2183 "Invalid transport offset 0x%x for TSO\n", 2184 transport_offset); 2185 ret = TX_CSUM_TSO; 2186 goto unavailable; 2187 } 2188 2189 switch (vlan_get_protocol(skb)) { 2190 case htons(ETH_P_IP): 2191 opts1 |= GTSENDV4; 2192 break; 2193 2194 case htons(ETH_P_IPV6): 2195 if (skb_cow_head(skb, 0)) { 2196 ret = TX_CSUM_TSO; 2197 goto unavailable; 2198 } 2199 tcp_v6_gso_csum_prep(skb); 2200 opts1 |= GTSENDV6; 2201 break; 2202 2203 default: 2204 WARN_ON_ONCE(1); 2205 break; 2206 } 2207 2208 opts1 |= transport_offset << GTTCPHO_SHIFT; 2209 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 2210 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 2211 u32 transport_offset = (u32)skb_transport_offset(skb); 2212 u8 ip_protocol; 2213 2214 if (transport_offset > TCPHO_MAX) { 2215 netif_warn(tp, tx_err, tp->netdev, 2216 "Invalid transport offset 0x%x\n", 2217 transport_offset); 2218 ret = TX_CSUM_NONE; 2219 goto unavailable; 2220 } 2221 2222 switch (vlan_get_protocol(skb)) { 2223 case htons(ETH_P_IP): 2224 opts2 |= IPV4_CS; 2225 ip_protocol = ip_hdr(skb)->protocol; 2226 break; 2227 2228 case htons(ETH_P_IPV6): 2229 opts2 |= IPV6_CS; 2230 ip_protocol = ipv6_hdr(skb)->nexthdr; 2231 break; 2232 2233 default: 2234 ip_protocol = IPPROTO_RAW; 2235 break; 2236 } 2237 2238 if (ip_protocol == IPPROTO_TCP) 2239 opts2 |= TCP_CS; 2240 else if (ip_protocol == IPPROTO_UDP) 2241 opts2 |= UDP_CS; 2242 else 2243 WARN_ON_ONCE(1); 2244 2245 opts2 |= transport_offset << TCPHO_SHIFT; 2246 } 2247 2248 desc->opts2 = cpu_to_le32(opts2); 2249 desc->opts1 = cpu_to_le32(opts1); 2250 2251 unavailable: 2252 return ret; 2253 } 2254 2255 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 2256 { 2257 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2258 int remain, ret; 2259 u8 *tx_data; 2260 2261 __skb_queue_head_init(&skb_head); 2262 spin_lock(&tx_queue->lock); 2263 skb_queue_splice_init(tx_queue, &skb_head); 2264 spin_unlock(&tx_queue->lock); 2265 2266 tx_data = agg->head; 2267 agg->skb_num = 0; 2268 agg->skb_len = 0; 2269 remain = agg_buf_sz; 2270 2271 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 2272 struct tx_desc *tx_desc; 2273 struct sk_buff *skb; 2274 unsigned int len; 2275 2276 skb = __skb_dequeue(&skb_head); 2277 if (!skb) 2278 break; 2279 2280 len = skb->len + sizeof(*tx_desc); 2281 2282 if (len > remain) { 2283 __skb_queue_head(&skb_head, skb); 2284 break; 2285 } 2286 2287 tx_data = tx_agg_align(tx_data); 2288 tx_desc = (struct tx_desc *)tx_data; 2289 2290 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { 2291 r8152_csum_workaround(tp, skb, &skb_head); 2292 continue; 2293 } 2294 2295 rtl_tx_vlan_tag(tx_desc, skb); 2296 2297 tx_data += sizeof(*tx_desc); 2298 2299 len = skb->len; 2300 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 2301 struct net_device_stats *stats = &tp->netdev->stats; 2302 2303 stats->tx_dropped++; 2304 dev_kfree_skb_any(skb); 2305 tx_data -= sizeof(*tx_desc); 2306 continue; 2307 } 2308 2309 tx_data += len; 2310 agg->skb_len += len; 2311 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 2312 2313 dev_kfree_skb_any(skb); 2314 2315 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 2316 2317 if (tp->dell_tb_rx_agg_bug) 2318 break; 2319 } 2320 2321 if (!skb_queue_empty(&skb_head)) { 2322 spin_lock(&tx_queue->lock); 2323 skb_queue_splice(&skb_head, tx_queue); 2324 spin_unlock(&tx_queue->lock); 2325 } 2326 2327 netif_tx_lock(tp->netdev); 2328 2329 if (netif_queue_stopped(tp->netdev) && 2330 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 2331 netif_wake_queue(tp->netdev); 2332 2333 netif_tx_unlock(tp->netdev); 2334 2335 ret = usb_autopm_get_interface_async(tp->intf); 2336 if (ret < 0) 2337 goto out_tx_fill; 2338 2339 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out, 2340 agg->head, (int)(tx_data - (u8 *)agg->head), 2341 (usb_complete_t)write_bulk_callback, agg); 2342 2343 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 2344 if (ret < 0) 2345 usb_autopm_put_interface_async(tp->intf); 2346 2347 out_tx_fill: 2348 return ret; 2349 } 2350 2351 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 2352 { 2353 u8 checksum = CHECKSUM_NONE; 2354 u32 opts2, opts3; 2355 2356 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 2357 goto return_result; 2358 2359 opts2 = le32_to_cpu(rx_desc->opts2); 2360 opts3 = le32_to_cpu(rx_desc->opts3); 2361 2362 if (opts2 & RD_IPV4_CS) { 2363 if (opts3 & IPF) 2364 checksum = CHECKSUM_NONE; 2365 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 2366 checksum = CHECKSUM_UNNECESSARY; 2367 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 2368 checksum = CHECKSUM_UNNECESSARY; 2369 } else if (opts2 & RD_IPV6_CS) { 2370 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 2371 checksum = CHECKSUM_UNNECESSARY; 2372 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 2373 checksum = CHECKSUM_UNNECESSARY; 2374 } 2375 2376 return_result: 2377 return checksum; 2378 } 2379 2380 static inline bool rx_count_exceed(struct r8152 *tp) 2381 { 2382 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; 2383 } 2384 2385 static inline int agg_offset(struct rx_agg *agg, void *addr) 2386 { 2387 return (int)(addr - agg->buffer); 2388 } 2389 2390 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) 2391 { 2392 struct rx_agg *agg, *agg_next, *agg_free = NULL; 2393 unsigned long flags; 2394 2395 spin_lock_irqsave(&tp->rx_lock, flags); 2396 2397 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { 2398 if (page_count(agg->page) == 1) { 2399 if (!agg_free) { 2400 list_del_init(&agg->list); 2401 agg_free = agg; 2402 continue; 2403 } 2404 if (rx_count_exceed(tp)) { 2405 list_del_init(&agg->list); 2406 free_rx_agg(tp, agg); 2407 } 2408 break; 2409 } 2410 } 2411 2412 spin_unlock_irqrestore(&tp->rx_lock, flags); 2413 2414 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) 2415 agg_free = alloc_rx_agg(tp, mflags); 2416 2417 return agg_free; 2418 } 2419 2420 static int rx_bottom(struct r8152 *tp, int budget) 2421 { 2422 unsigned long flags; 2423 struct list_head *cursor, *next, rx_queue; 2424 int ret = 0, work_done = 0; 2425 struct napi_struct *napi = &tp->napi; 2426 2427 if (!skb_queue_empty(&tp->rx_queue)) { 2428 while (work_done < budget) { 2429 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 2430 struct net_device *netdev = tp->netdev; 2431 struct net_device_stats *stats = &netdev->stats; 2432 unsigned int pkt_len; 2433 2434 if (!skb) 2435 break; 2436 2437 pkt_len = skb->len; 2438 napi_gro_receive(napi, skb); 2439 work_done++; 2440 stats->rx_packets++; 2441 stats->rx_bytes += pkt_len; 2442 } 2443 } 2444 2445 if (list_empty(&tp->rx_done)) 2446 goto out1; 2447 2448 clear_bit(RX_EPROTO, &tp->flags); 2449 INIT_LIST_HEAD(&rx_queue); 2450 spin_lock_irqsave(&tp->rx_lock, flags); 2451 list_splice_init(&tp->rx_done, &rx_queue); 2452 spin_unlock_irqrestore(&tp->rx_lock, flags); 2453 2454 list_for_each_safe(cursor, next, &rx_queue) { 2455 struct rx_desc *rx_desc; 2456 struct rx_agg *agg, *agg_free; 2457 int len_used = 0; 2458 struct urb *urb; 2459 u8 *rx_data; 2460 2461 list_del_init(cursor); 2462 2463 agg = list_entry(cursor, struct rx_agg, list); 2464 urb = agg->urb; 2465 if (urb->status != 0 || urb->actual_length < ETH_ZLEN) 2466 goto submit; 2467 2468 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); 2469 2470 rx_desc = agg->buffer; 2471 rx_data = agg->buffer; 2472 len_used += sizeof(struct rx_desc); 2473 2474 while (urb->actual_length > len_used) { 2475 struct net_device *netdev = tp->netdev; 2476 struct net_device_stats *stats = &netdev->stats; 2477 unsigned int pkt_len, rx_frag_head_sz; 2478 struct sk_buff *skb; 2479 2480 /* limit the skb numbers for rx_queue */ 2481 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 2482 break; 2483 2484 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2485 if (pkt_len < ETH_ZLEN) 2486 break; 2487 2488 len_used += pkt_len; 2489 if (urb->actual_length < len_used) 2490 break; 2491 2492 pkt_len -= ETH_FCS_LEN; 2493 rx_data += sizeof(struct rx_desc); 2494 2495 if (!agg_free || tp->rx_copybreak > pkt_len) 2496 rx_frag_head_sz = pkt_len; 2497 else 2498 rx_frag_head_sz = tp->rx_copybreak; 2499 2500 skb = napi_alloc_skb(napi, rx_frag_head_sz); 2501 if (!skb) { 2502 stats->rx_dropped++; 2503 goto find_next_rx; 2504 } 2505 2506 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 2507 memcpy(skb->data, rx_data, rx_frag_head_sz); 2508 skb_put(skb, rx_frag_head_sz); 2509 pkt_len -= rx_frag_head_sz; 2510 rx_data += rx_frag_head_sz; 2511 if (pkt_len) { 2512 skb_add_rx_frag(skb, 0, agg->page, 2513 agg_offset(agg, rx_data), 2514 pkt_len, 2515 SKB_DATA_ALIGN(pkt_len)); 2516 get_page(agg->page); 2517 } 2518 2519 skb->protocol = eth_type_trans(skb, netdev); 2520 rtl_rx_vlan_tag(rx_desc, skb); 2521 if (work_done < budget) { 2522 work_done++; 2523 stats->rx_packets++; 2524 stats->rx_bytes += skb->len; 2525 napi_gro_receive(napi, skb); 2526 } else { 2527 __skb_queue_tail(&tp->rx_queue, skb); 2528 } 2529 2530 find_next_rx: 2531 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 2532 rx_desc = (struct rx_desc *)rx_data; 2533 len_used = agg_offset(agg, rx_data); 2534 len_used += sizeof(struct rx_desc); 2535 } 2536 2537 WARN_ON(!agg_free && page_count(agg->page) > 1); 2538 2539 if (agg_free) { 2540 spin_lock_irqsave(&tp->rx_lock, flags); 2541 if (page_count(agg->page) == 1) { 2542 list_add(&agg_free->list, &tp->rx_used); 2543 } else { 2544 list_add_tail(&agg->list, &tp->rx_used); 2545 agg = agg_free; 2546 urb = agg->urb; 2547 } 2548 spin_unlock_irqrestore(&tp->rx_lock, flags); 2549 } 2550 2551 submit: 2552 if (!ret) { 2553 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2554 } else { 2555 urb->actual_length = 0; 2556 list_add_tail(&agg->list, next); 2557 } 2558 } 2559 2560 if (!list_empty(&rx_queue)) { 2561 spin_lock_irqsave(&tp->rx_lock, flags); 2562 list_splice_tail(&rx_queue, &tp->rx_done); 2563 spin_unlock_irqrestore(&tp->rx_lock, flags); 2564 } 2565 2566 out1: 2567 return work_done; 2568 } 2569 2570 static void tx_bottom(struct r8152 *tp) 2571 { 2572 int res; 2573 2574 do { 2575 struct net_device *netdev = tp->netdev; 2576 struct tx_agg *agg; 2577 2578 if (skb_queue_empty(&tp->tx_queue)) 2579 break; 2580 2581 agg = r8152_get_tx_agg(tp); 2582 if (!agg) 2583 break; 2584 2585 res = r8152_tx_agg_fill(tp, agg); 2586 if (!res) 2587 continue; 2588 2589 if (res == -ENODEV) { 2590 rtl_set_unplug(tp); 2591 netif_device_detach(netdev); 2592 } else { 2593 struct net_device_stats *stats = &netdev->stats; 2594 unsigned long flags; 2595 2596 netif_warn(tp, tx_err, netdev, 2597 "failed tx_urb %d\n", res); 2598 stats->tx_dropped += agg->skb_num; 2599 2600 spin_lock_irqsave(&tp->tx_lock, flags); 2601 list_add_tail(&agg->list, &tp->tx_free); 2602 spin_unlock_irqrestore(&tp->tx_lock, flags); 2603 } 2604 } while (res == 0); 2605 } 2606 2607 static void bottom_half(struct tasklet_struct *t) 2608 { 2609 struct r8152 *tp = from_tasklet(tp, t, tx_tl); 2610 2611 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2612 return; 2613 2614 if (!test_bit(WORK_ENABLE, &tp->flags)) 2615 return; 2616 2617 /* When link down, the driver would cancel all bulks. */ 2618 /* This avoid the re-submitting bulk */ 2619 if (!netif_carrier_ok(tp->netdev)) 2620 return; 2621 2622 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2623 2624 tx_bottom(tp); 2625 } 2626 2627 static int r8152_poll(struct napi_struct *napi, int budget) 2628 { 2629 struct r8152 *tp = container_of(napi, struct r8152, napi); 2630 int work_done; 2631 2632 work_done = rx_bottom(tp, budget); 2633 2634 if (work_done < budget) { 2635 if (!napi_complete_done(napi, work_done)) 2636 goto out; 2637 if (!list_empty(&tp->rx_done)) 2638 napi_schedule(napi); 2639 } 2640 2641 out: 2642 return work_done; 2643 } 2644 2645 static 2646 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2647 { 2648 int ret; 2649 2650 /* The rx would be stopped, so skip submitting */ 2651 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2652 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2653 return 0; 2654 2655 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in, 2656 agg->buffer, tp->rx_buf_sz, 2657 (usb_complete_t)read_bulk_callback, agg); 2658 2659 ret = usb_submit_urb(agg->urb, mem_flags); 2660 if (ret == -ENODEV) { 2661 rtl_set_unplug(tp); 2662 netif_device_detach(tp->netdev); 2663 } else if (ret) { 2664 struct urb *urb = agg->urb; 2665 unsigned long flags; 2666 2667 urb->actual_length = 0; 2668 spin_lock_irqsave(&tp->rx_lock, flags); 2669 list_add_tail(&agg->list, &tp->rx_done); 2670 spin_unlock_irqrestore(&tp->rx_lock, flags); 2671 2672 netif_err(tp, rx_err, tp->netdev, 2673 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2674 2675 napi_schedule(&tp->napi); 2676 } 2677 2678 return ret; 2679 } 2680 2681 static void rtl_drop_queued_tx(struct r8152 *tp) 2682 { 2683 struct net_device_stats *stats = &tp->netdev->stats; 2684 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2685 struct sk_buff *skb; 2686 2687 if (skb_queue_empty(tx_queue)) 2688 return; 2689 2690 __skb_queue_head_init(&skb_head); 2691 spin_lock_bh(&tx_queue->lock); 2692 skb_queue_splice_init(tx_queue, &skb_head); 2693 spin_unlock_bh(&tx_queue->lock); 2694 2695 while ((skb = __skb_dequeue(&skb_head))) { 2696 dev_kfree_skb(skb); 2697 stats->tx_dropped++; 2698 } 2699 } 2700 2701 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2702 { 2703 struct r8152 *tp = netdev_priv(netdev); 2704 2705 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2706 2707 usb_queue_reset_device(tp->intf); 2708 } 2709 2710 static void rtl8152_set_rx_mode(struct net_device *netdev) 2711 { 2712 struct r8152 *tp = netdev_priv(netdev); 2713 2714 if (netif_carrier_ok(netdev)) { 2715 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2716 schedule_delayed_work(&tp->schedule, 0); 2717 } 2718 } 2719 2720 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2721 { 2722 struct r8152 *tp = netdev_priv(netdev); 2723 u32 mc_filter[2]; /* Multicast hash filter */ 2724 __le32 tmp[2]; 2725 u32 ocp_data; 2726 2727 netif_stop_queue(netdev); 2728 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2729 ocp_data &= ~RCR_ACPT_ALL; 2730 ocp_data |= RCR_AB | RCR_APM; 2731 2732 if (netdev->flags & IFF_PROMISC) { 2733 /* Unconditionally log net taps. */ 2734 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2735 ocp_data |= RCR_AM | RCR_AAP; 2736 mc_filter[1] = 0xffffffff; 2737 mc_filter[0] = 0xffffffff; 2738 } else if ((netdev->flags & IFF_MULTICAST && 2739 netdev_mc_count(netdev) > multicast_filter_limit) || 2740 (netdev->flags & IFF_ALLMULTI)) { 2741 /* Too many to filter perfectly -- accept all multicasts. */ 2742 ocp_data |= RCR_AM; 2743 mc_filter[1] = 0xffffffff; 2744 mc_filter[0] = 0xffffffff; 2745 } else { 2746 mc_filter[1] = 0; 2747 mc_filter[0] = 0; 2748 2749 if (netdev->flags & IFF_MULTICAST) { 2750 struct netdev_hw_addr *ha; 2751 2752 netdev_for_each_mc_addr(ha, netdev) { 2753 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2754 2755 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2756 ocp_data |= RCR_AM; 2757 } 2758 } 2759 } 2760 2761 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2762 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2763 2764 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2765 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2766 netif_wake_queue(netdev); 2767 } 2768 2769 static netdev_features_t 2770 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2771 netdev_features_t features) 2772 { 2773 u32 mss = skb_shinfo(skb)->gso_size; 2774 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2775 2776 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && 2777 skb_transport_offset(skb) > max_offset) 2778 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2779 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2780 features &= ~NETIF_F_GSO_MASK; 2781 2782 return features; 2783 } 2784 2785 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2786 struct net_device *netdev) 2787 { 2788 struct r8152 *tp = netdev_priv(netdev); 2789 2790 skb_tx_timestamp(skb); 2791 2792 skb_queue_tail(&tp->tx_queue, skb); 2793 2794 if (!list_empty(&tp->tx_free)) { 2795 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2796 set_bit(SCHEDULE_TASKLET, &tp->flags); 2797 schedule_delayed_work(&tp->schedule, 0); 2798 } else { 2799 usb_mark_last_busy(tp->udev); 2800 tasklet_schedule(&tp->tx_tl); 2801 } 2802 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2803 netif_stop_queue(netdev); 2804 } 2805 2806 return NETDEV_TX_OK; 2807 } 2808 2809 static void r8152b_reset_packet_filter(struct r8152 *tp) 2810 { 2811 u32 ocp_data; 2812 2813 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2814 ocp_data &= ~FMC_FCR_MCU_EN; 2815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2816 ocp_data |= FMC_FCR_MCU_EN; 2817 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2818 } 2819 2820 static void rtl8152_nic_reset(struct r8152 *tp) 2821 { 2822 u32 ocp_data; 2823 int i; 2824 2825 switch (tp->version) { 2826 case RTL_TEST_01: 2827 case RTL_VER_10: 2828 case RTL_VER_11: 2829 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2830 ocp_data &= ~CR_TE; 2831 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2832 2833 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); 2834 ocp_data &= ~BMU_RESET_EP_IN; 2835 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2836 2837 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2838 ocp_data |= CDC_ECM_EN; 2839 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2840 2841 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2842 ocp_data &= ~CR_RE; 2843 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2844 2845 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); 2846 ocp_data |= BMU_RESET_EP_IN; 2847 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2848 2849 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2850 ocp_data &= ~CDC_ECM_EN; 2851 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2852 break; 2853 2854 default: 2855 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2856 2857 for (i = 0; i < 1000; i++) { 2858 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2859 break; 2860 usleep_range(100, 400); 2861 } 2862 break; 2863 } 2864 } 2865 2866 static void set_tx_qlen(struct r8152 *tp) 2867 { 2868 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); 2869 } 2870 2871 static inline u16 rtl8152_get_speed(struct r8152 *tp) 2872 { 2873 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2874 } 2875 2876 static void rtl_eee_plus_en(struct r8152 *tp, bool enable) 2877 { 2878 u32 ocp_data; 2879 2880 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2881 if (enable) 2882 ocp_data |= EEEP_CR_EEEP_TX; 2883 else 2884 ocp_data &= ~EEEP_CR_EEEP_TX; 2885 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2886 } 2887 2888 static void rtl_set_eee_plus(struct r8152 *tp) 2889 { 2890 if (rtl8152_get_speed(tp) & _10bps) 2891 rtl_eee_plus_en(tp, true); 2892 else 2893 rtl_eee_plus_en(tp, false); 2894 } 2895 2896 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2897 { 2898 u32 ocp_data; 2899 2900 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2901 if (enable) 2902 ocp_data |= RXDY_GATED_EN; 2903 else 2904 ocp_data &= ~RXDY_GATED_EN; 2905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2906 } 2907 2908 static int rtl_start_rx(struct r8152 *tp) 2909 { 2910 struct rx_agg *agg, *agg_next; 2911 struct list_head tmp_list; 2912 unsigned long flags; 2913 int ret = 0, i = 0; 2914 2915 INIT_LIST_HEAD(&tmp_list); 2916 2917 spin_lock_irqsave(&tp->rx_lock, flags); 2918 2919 INIT_LIST_HEAD(&tp->rx_done); 2920 INIT_LIST_HEAD(&tp->rx_used); 2921 2922 list_splice_init(&tp->rx_info, &tmp_list); 2923 2924 spin_unlock_irqrestore(&tp->rx_lock, flags); 2925 2926 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2927 INIT_LIST_HEAD(&agg->list); 2928 2929 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ 2930 if (++i > RTL8152_MAX_RX) { 2931 spin_lock_irqsave(&tp->rx_lock, flags); 2932 list_add_tail(&agg->list, &tp->rx_used); 2933 spin_unlock_irqrestore(&tp->rx_lock, flags); 2934 } else if (unlikely(ret < 0)) { 2935 spin_lock_irqsave(&tp->rx_lock, flags); 2936 list_add_tail(&agg->list, &tp->rx_done); 2937 spin_unlock_irqrestore(&tp->rx_lock, flags); 2938 } else { 2939 ret = r8152_submit_rx(tp, agg, GFP_KERNEL); 2940 } 2941 } 2942 2943 spin_lock_irqsave(&tp->rx_lock, flags); 2944 WARN_ON(!list_empty(&tp->rx_info)); 2945 list_splice(&tmp_list, &tp->rx_info); 2946 spin_unlock_irqrestore(&tp->rx_lock, flags); 2947 2948 return ret; 2949 } 2950 2951 static int rtl_stop_rx(struct r8152 *tp) 2952 { 2953 struct rx_agg *agg, *agg_next; 2954 struct list_head tmp_list; 2955 unsigned long flags; 2956 2957 INIT_LIST_HEAD(&tmp_list); 2958 2959 /* The usb_kill_urb() couldn't be used in atomic. 2960 * Therefore, move the list of rx_info to a tmp one. 2961 * Then, list_for_each_entry_safe could be used without 2962 * spin lock. 2963 */ 2964 2965 spin_lock_irqsave(&tp->rx_lock, flags); 2966 list_splice_init(&tp->rx_info, &tmp_list); 2967 spin_unlock_irqrestore(&tp->rx_lock, flags); 2968 2969 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2970 /* At least RTL8152_MAX_RX rx_agg have the page_count being 2971 * equal to 1, so the other ones could be freed safely. 2972 */ 2973 if (page_count(agg->page) > 1) 2974 free_rx_agg(tp, agg); 2975 else 2976 usb_kill_urb(agg->urb); 2977 } 2978 2979 /* Move back the list of temp to the rx_info */ 2980 spin_lock_irqsave(&tp->rx_lock, flags); 2981 WARN_ON(!list_empty(&tp->rx_info)); 2982 list_splice(&tmp_list, &tp->rx_info); 2983 spin_unlock_irqrestore(&tp->rx_lock, flags); 2984 2985 while (!skb_queue_empty(&tp->rx_queue)) 2986 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2987 2988 return 0; 2989 } 2990 2991 static void rtl_set_ifg(struct r8152 *tp, u16 speed) 2992 { 2993 u32 ocp_data; 2994 2995 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 2996 ocp_data &= ~IFG_MASK; 2997 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { 2998 ocp_data |= IFG_144NS; 2999 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); 3000 3001 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 3002 ocp_data &= ~TX10MIDLE_EN; 3003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 3004 } else { 3005 ocp_data |= IFG_96NS; 3006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); 3007 3008 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 3009 ocp_data |= TX10MIDLE_EN; 3010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 3011 } 3012 } 3013 3014 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 3015 { 3016 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 3017 OWN_UPDATE | OWN_CLEAR); 3018 } 3019 3020 static int rtl_enable(struct r8152 *tp) 3021 { 3022 u32 ocp_data; 3023 3024 r8152b_reset_packet_filter(tp); 3025 3026 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 3027 ocp_data |= CR_RE | CR_TE; 3028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 3029 3030 switch (tp->version) { 3031 case RTL_VER_01: 3032 case RTL_VER_02: 3033 case RTL_VER_03: 3034 case RTL_VER_04: 3035 case RTL_VER_05: 3036 case RTL_VER_06: 3037 case RTL_VER_07: 3038 break; 3039 default: 3040 r8153b_rx_agg_chg_indicate(tp); 3041 break; 3042 } 3043 3044 rxdy_gated_en(tp, false); 3045 3046 return 0; 3047 } 3048 3049 static int rtl8152_enable(struct r8152 *tp) 3050 { 3051 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3052 return -ENODEV; 3053 3054 set_tx_qlen(tp); 3055 rtl_set_eee_plus(tp); 3056 3057 return rtl_enable(tp); 3058 } 3059 3060 static void r8153_set_rx_early_timeout(struct r8152 *tp) 3061 { 3062 u32 ocp_data = tp->coalesce / 8; 3063 3064 switch (tp->version) { 3065 case RTL_VER_03: 3066 case RTL_VER_04: 3067 case RTL_VER_05: 3068 case RTL_VER_06: 3069 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3070 ocp_data); 3071 break; 3072 3073 case RTL_VER_08: 3074 case RTL_VER_09: 3075 case RTL_VER_14: 3076 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 3077 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 3078 */ 3079 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3080 128 / 8); 3081 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 3082 ocp_data); 3083 break; 3084 3085 case RTL_VER_10: 3086 case RTL_VER_11: 3087 case RTL_VER_12: 3088 case RTL_VER_13: 3089 case RTL_VER_15: 3090 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3091 640 / 8); 3092 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 3093 ocp_data); 3094 break; 3095 3096 default: 3097 break; 3098 } 3099 } 3100 3101 static void r8153_set_rx_early_size(struct r8152 *tp) 3102 { 3103 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 3104 3105 switch (tp->version) { 3106 case RTL_VER_03: 3107 case RTL_VER_04: 3108 case RTL_VER_05: 3109 case RTL_VER_06: 3110 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3111 ocp_data / 4); 3112 break; 3113 case RTL_VER_08: 3114 case RTL_VER_09: 3115 case RTL_VER_14: 3116 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3117 ocp_data / 8); 3118 break; 3119 case RTL_TEST_01: 3120 case RTL_VER_10: 3121 case RTL_VER_11: 3122 case RTL_VER_12: 3123 case RTL_VER_13: 3124 case RTL_VER_15: 3125 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3126 ocp_data / 8); 3127 break; 3128 default: 3129 WARN_ON_ONCE(1); 3130 break; 3131 } 3132 } 3133 3134 static int rtl8153_enable(struct r8152 *tp) 3135 { 3136 u32 ocp_data; 3137 3138 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3139 return -ENODEV; 3140 3141 set_tx_qlen(tp); 3142 rtl_set_eee_plus(tp); 3143 r8153_set_rx_early_timeout(tp); 3144 r8153_set_rx_early_size(tp); 3145 3146 rtl_set_ifg(tp, rtl8152_get_speed(tp)); 3147 3148 switch (tp->version) { 3149 case RTL_VER_09: 3150 case RTL_VER_14: 3151 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 3152 ocp_data &= ~FC_PATCH_TASK; 3153 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 3154 usleep_range(1000, 2000); 3155 ocp_data |= FC_PATCH_TASK; 3156 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 3157 break; 3158 default: 3159 break; 3160 } 3161 3162 return rtl_enable(tp); 3163 } 3164 3165 static void rtl_disable(struct r8152 *tp) 3166 { 3167 u32 ocp_data; 3168 int i; 3169 3170 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3171 rtl_drop_queued_tx(tp); 3172 return; 3173 } 3174 3175 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3176 ocp_data &= ~RCR_ACPT_ALL; 3177 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3178 3179 rtl_drop_queued_tx(tp); 3180 3181 for (i = 0; i < RTL8152_MAX_TX; i++) 3182 usb_kill_urb(tp->tx_info[i].urb); 3183 3184 rxdy_gated_en(tp, true); 3185 3186 for (i = 0; i < 1000; i++) { 3187 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3188 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 3189 break; 3190 usleep_range(1000, 2000); 3191 } 3192 3193 for (i = 0; i < 1000; i++) { 3194 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 3195 break; 3196 usleep_range(1000, 2000); 3197 } 3198 3199 rtl_stop_rx(tp); 3200 3201 rtl8152_nic_reset(tp); 3202 } 3203 3204 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 3205 { 3206 u32 ocp_data; 3207 3208 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 3209 if (enable) 3210 ocp_data |= POWER_CUT; 3211 else 3212 ocp_data &= ~POWER_CUT; 3213 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 3214 3215 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 3216 ocp_data &= ~RESUME_INDICATE; 3217 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 3218 } 3219 3220 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 3221 { 3222 u32 ocp_data; 3223 3224 switch (tp->version) { 3225 case RTL_VER_01: 3226 case RTL_VER_02: 3227 case RTL_VER_03: 3228 case RTL_VER_04: 3229 case RTL_VER_05: 3230 case RTL_VER_06: 3231 case RTL_VER_07: 3232 case RTL_VER_08: 3233 case RTL_VER_09: 3234 case RTL_VER_14: 3235 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 3236 if (enable) 3237 ocp_data |= CPCR_RX_VLAN; 3238 else 3239 ocp_data &= ~CPCR_RX_VLAN; 3240 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 3241 break; 3242 3243 case RTL_TEST_01: 3244 case RTL_VER_10: 3245 case RTL_VER_11: 3246 case RTL_VER_12: 3247 case RTL_VER_13: 3248 case RTL_VER_15: 3249 default: 3250 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); 3251 if (enable) 3252 ocp_data |= OUTER_VLAN | INNER_VLAN; 3253 else 3254 ocp_data &= ~(OUTER_VLAN | INNER_VLAN); 3255 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); 3256 break; 3257 } 3258 } 3259 3260 static int rtl8152_set_features(struct net_device *dev, 3261 netdev_features_t features) 3262 { 3263 netdev_features_t changed = features ^ dev->features; 3264 struct r8152 *tp = netdev_priv(dev); 3265 int ret; 3266 3267 ret = usb_autopm_get_interface(tp->intf); 3268 if (ret < 0) 3269 goto out; 3270 3271 mutex_lock(&tp->control); 3272 3273 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 3274 if (features & NETIF_F_HW_VLAN_CTAG_RX) 3275 rtl_rx_vlan_en(tp, true); 3276 else 3277 rtl_rx_vlan_en(tp, false); 3278 } 3279 3280 mutex_unlock(&tp->control); 3281 3282 usb_autopm_put_interface(tp->intf); 3283 3284 out: 3285 return ret; 3286 } 3287 3288 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 3289 3290 static u32 __rtl_get_wol(struct r8152 *tp) 3291 { 3292 u32 ocp_data; 3293 u32 wolopts = 0; 3294 3295 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3296 if (ocp_data & LINK_ON_WAKE_EN) 3297 wolopts |= WAKE_PHY; 3298 3299 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 3300 if (ocp_data & UWF_EN) 3301 wolopts |= WAKE_UCAST; 3302 if (ocp_data & BWF_EN) 3303 wolopts |= WAKE_BCAST; 3304 if (ocp_data & MWF_EN) 3305 wolopts |= WAKE_MCAST; 3306 3307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 3308 if (ocp_data & MAGIC_EN) 3309 wolopts |= WAKE_MAGIC; 3310 3311 return wolopts; 3312 } 3313 3314 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 3315 { 3316 u32 ocp_data; 3317 3318 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3319 3320 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3321 ocp_data &= ~LINK_ON_WAKE_EN; 3322 if (wolopts & WAKE_PHY) 3323 ocp_data |= LINK_ON_WAKE_EN; 3324 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3325 3326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 3327 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 3328 if (wolopts & WAKE_UCAST) 3329 ocp_data |= UWF_EN; 3330 if (wolopts & WAKE_BCAST) 3331 ocp_data |= BWF_EN; 3332 if (wolopts & WAKE_MCAST) 3333 ocp_data |= MWF_EN; 3334 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 3335 3336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3337 3338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 3339 ocp_data &= ~MAGIC_EN; 3340 if (wolopts & WAKE_MAGIC) 3341 ocp_data |= MAGIC_EN; 3342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 3343 3344 if (wolopts & WAKE_ANY) 3345 device_set_wakeup_enable(&tp->udev->dev, true); 3346 else 3347 device_set_wakeup_enable(&tp->udev->dev, false); 3348 } 3349 3350 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) 3351 { 3352 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3353 3354 /* MAC clock speed down */ 3355 if (enable) 3356 ocp_data |= MAC_CLK_SPDWN_EN; 3357 else 3358 ocp_data &= ~MAC_CLK_SPDWN_EN; 3359 3360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3361 } 3362 3363 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) 3364 { 3365 u32 ocp_data; 3366 3367 /* MAC clock speed down */ 3368 if (enable) { 3369 /* aldps_spdwn_ratio, tp10_spdwn_ratio */ 3370 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 3371 0x0403); 3372 3373 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3374 ocp_data &= ~EEE_SPDWN_RATIO_MASK; 3375 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ 3376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3377 } else { 3378 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3379 ocp_data &= ~MAC_CLK_SPDWN_EN; 3380 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3381 } 3382 } 3383 3384 static void r8153_u1u2en(struct r8152 *tp, bool enable) 3385 { 3386 u8 u1u2[8]; 3387 3388 if (enable) 3389 memset(u1u2, 0xff, sizeof(u1u2)); 3390 else 3391 memset(u1u2, 0x00, sizeof(u1u2)); 3392 3393 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 3394 } 3395 3396 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 3397 { 3398 u32 ocp_data; 3399 3400 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 3401 if (enable) 3402 ocp_data |= LPM_U1U2_EN; 3403 else 3404 ocp_data &= ~LPM_U1U2_EN; 3405 3406 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 3407 } 3408 3409 static void r8153_u2p3en(struct r8152 *tp, bool enable) 3410 { 3411 u32 ocp_data; 3412 3413 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 3414 if (enable) 3415 ocp_data |= U2P3_ENABLE; 3416 else 3417 ocp_data &= ~U2P3_ENABLE; 3418 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 3419 } 3420 3421 static void r8153b_ups_flags(struct r8152 *tp) 3422 { 3423 u32 ups_flags = 0; 3424 3425 if (tp->ups_info.green) 3426 ups_flags |= UPS_FLAGS_EN_GREEN; 3427 3428 if (tp->ups_info.aldps) 3429 ups_flags |= UPS_FLAGS_EN_ALDPS; 3430 3431 if (tp->ups_info.eee) 3432 ups_flags |= UPS_FLAGS_EN_EEE; 3433 3434 if (tp->ups_info.flow_control) 3435 ups_flags |= UPS_FLAGS_EN_FLOW_CTR; 3436 3437 if (tp->ups_info.eee_ckdiv) 3438 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; 3439 3440 if (tp->ups_info.eee_cmod_lv) 3441 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; 3442 3443 if (tp->ups_info.r_tune) 3444 ups_flags |= UPS_FLAGS_R_TUNE; 3445 3446 if (tp->ups_info._10m_ckdiv) 3447 ups_flags |= UPS_FLAGS_EN_10M_CKDIV; 3448 3449 if (tp->ups_info.eee_plloff_100) 3450 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; 3451 3452 if (tp->ups_info.eee_plloff_giga) 3453 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; 3454 3455 if (tp->ups_info._250m_ckdiv) 3456 ups_flags |= UPS_FLAGS_250M_CKDIV; 3457 3458 if (tp->ups_info.ctap_short_off) 3459 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS; 3460 3461 switch (tp->ups_info.speed_duplex) { 3462 case NWAY_10M_HALF: 3463 ups_flags |= ups_flags_speed(1); 3464 break; 3465 case NWAY_10M_FULL: 3466 ups_flags |= ups_flags_speed(2); 3467 break; 3468 case NWAY_100M_HALF: 3469 ups_flags |= ups_flags_speed(3); 3470 break; 3471 case NWAY_100M_FULL: 3472 ups_flags |= ups_flags_speed(4); 3473 break; 3474 case NWAY_1000M_FULL: 3475 ups_flags |= ups_flags_speed(5); 3476 break; 3477 case FORCE_10M_HALF: 3478 ups_flags |= ups_flags_speed(6); 3479 break; 3480 case FORCE_10M_FULL: 3481 ups_flags |= ups_flags_speed(7); 3482 break; 3483 case FORCE_100M_HALF: 3484 ups_flags |= ups_flags_speed(8); 3485 break; 3486 case FORCE_100M_FULL: 3487 ups_flags |= ups_flags_speed(9); 3488 break; 3489 default: 3490 break; 3491 } 3492 3493 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); 3494 } 3495 3496 static void r8156_ups_flags(struct r8152 *tp) 3497 { 3498 u32 ups_flags = 0; 3499 3500 if (tp->ups_info.green) 3501 ups_flags |= UPS_FLAGS_EN_GREEN; 3502 3503 if (tp->ups_info.aldps) 3504 ups_flags |= UPS_FLAGS_EN_ALDPS; 3505 3506 if (tp->ups_info.eee) 3507 ups_flags |= UPS_FLAGS_EN_EEE; 3508 3509 if (tp->ups_info.flow_control) 3510 ups_flags |= UPS_FLAGS_EN_FLOW_CTR; 3511 3512 if (tp->ups_info.eee_ckdiv) 3513 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; 3514 3515 if (tp->ups_info._10m_ckdiv) 3516 ups_flags |= UPS_FLAGS_EN_10M_CKDIV; 3517 3518 if (tp->ups_info.eee_plloff_100) 3519 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; 3520 3521 if (tp->ups_info.eee_plloff_giga) 3522 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; 3523 3524 if (tp->ups_info._250m_ckdiv) 3525 ups_flags |= UPS_FLAGS_250M_CKDIV; 3526 3527 switch (tp->ups_info.speed_duplex) { 3528 case FORCE_10M_HALF: 3529 ups_flags |= ups_flags_speed(0); 3530 break; 3531 case FORCE_10M_FULL: 3532 ups_flags |= ups_flags_speed(1); 3533 break; 3534 case FORCE_100M_HALF: 3535 ups_flags |= ups_flags_speed(2); 3536 break; 3537 case FORCE_100M_FULL: 3538 ups_flags |= ups_flags_speed(3); 3539 break; 3540 case NWAY_10M_HALF: 3541 ups_flags |= ups_flags_speed(4); 3542 break; 3543 case NWAY_10M_FULL: 3544 ups_flags |= ups_flags_speed(5); 3545 break; 3546 case NWAY_100M_HALF: 3547 ups_flags |= ups_flags_speed(6); 3548 break; 3549 case NWAY_100M_FULL: 3550 ups_flags |= ups_flags_speed(7); 3551 break; 3552 case NWAY_1000M_FULL: 3553 ups_flags |= ups_flags_speed(8); 3554 break; 3555 case NWAY_2500M_FULL: 3556 ups_flags |= ups_flags_speed(9); 3557 break; 3558 default: 3559 break; 3560 } 3561 3562 switch (tp->ups_info.lite_mode) { 3563 case 1: 3564 ups_flags |= 0 << 5; 3565 break; 3566 case 2: 3567 ups_flags |= 2 << 5; 3568 break; 3569 case 0: 3570 default: 3571 ups_flags |= 1 << 5; 3572 break; 3573 } 3574 3575 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); 3576 } 3577 3578 static void rtl_green_en(struct r8152 *tp, bool enable) 3579 { 3580 u16 data; 3581 3582 data = sram_read(tp, SRAM_GREEN_CFG); 3583 if (enable) 3584 data |= GREEN_ETH_EN; 3585 else 3586 data &= ~GREEN_ETH_EN; 3587 sram_write(tp, SRAM_GREEN_CFG, data); 3588 3589 tp->ups_info.green = enable; 3590 } 3591 3592 static void r8153b_green_en(struct r8152 *tp, bool enable) 3593 { 3594 if (enable) { 3595 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 3596 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 3597 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 3598 } else { 3599 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 3600 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 3601 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 3602 } 3603 3604 rtl_green_en(tp, true); 3605 } 3606 3607 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 3608 { 3609 u16 data; 3610 int i; 3611 3612 for (i = 0; i < 500; i++) { 3613 data = ocp_reg_read(tp, OCP_PHY_STATUS); 3614 data &= PHY_STAT_MASK; 3615 if (desired) { 3616 if (data == desired) 3617 break; 3618 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 3619 data == PHY_STAT_EXT_INIT) { 3620 break; 3621 } 3622 3623 msleep(20); 3624 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3625 break; 3626 } 3627 3628 return data; 3629 } 3630 3631 static void r8153b_ups_en(struct r8152 *tp, bool enable) 3632 { 3633 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3634 3635 if (enable) { 3636 r8153b_ups_flags(tp); 3637 3638 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3639 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3640 3641 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3642 ocp_data |= UPS_FORCE_PWR_DOWN; 3643 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3644 } else { 3645 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3646 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3647 3648 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3649 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3650 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3651 3652 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3653 int i; 3654 3655 for (i = 0; i < 500; i++) { 3656 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3657 AUTOLOAD_DONE) 3658 break; 3659 msleep(20); 3660 } 3661 3662 tp->rtl_ops.hw_phy_cfg(tp); 3663 3664 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3665 tp->duplex, tp->advertising); 3666 } 3667 } 3668 } 3669 3670 static void r8153c_ups_en(struct r8152 *tp, bool enable) 3671 { 3672 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3673 3674 if (enable) { 3675 r8153b_ups_flags(tp); 3676 3677 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3678 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3679 3680 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3681 ocp_data |= UPS_FORCE_PWR_DOWN; 3682 ocp_data &= ~BIT(7); 3683 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3684 } else { 3685 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3686 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3687 3688 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3689 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3690 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3691 3692 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3693 int i; 3694 3695 for (i = 0; i < 500; i++) { 3696 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3697 AUTOLOAD_DONE) 3698 break; 3699 msleep(20); 3700 } 3701 3702 tp->rtl_ops.hw_phy_cfg(tp); 3703 3704 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3705 tp->duplex, tp->advertising); 3706 } 3707 3708 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3709 3710 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3711 ocp_data |= BIT(8); 3712 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3713 3714 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3715 } 3716 } 3717 3718 static void r8156_ups_en(struct r8152 *tp, bool enable) 3719 { 3720 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3721 3722 if (enable) { 3723 r8156_ups_flags(tp); 3724 3725 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3726 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3727 3728 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3729 ocp_data |= UPS_FORCE_PWR_DOWN; 3730 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3731 3732 switch (tp->version) { 3733 case RTL_VER_13: 3734 case RTL_VER_15: 3735 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); 3736 ocp_data &= ~OOBS_POLLING; 3737 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); 3738 break; 3739 default: 3740 break; 3741 } 3742 } else { 3743 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3744 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3745 3746 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3747 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3748 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3749 3750 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3751 tp->rtl_ops.hw_phy_cfg(tp); 3752 3753 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3754 tp->duplex, tp->advertising); 3755 } 3756 } 3757 } 3758 3759 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 3760 { 3761 u32 ocp_data; 3762 3763 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3764 if (enable) 3765 ocp_data |= PWR_EN | PHASE2_EN; 3766 else 3767 ocp_data &= ~(PWR_EN | PHASE2_EN); 3768 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3769 3770 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3771 ocp_data &= ~PCUT_STATUS; 3772 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3773 } 3774 3775 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 3776 { 3777 u32 ocp_data; 3778 3779 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3780 if (enable) 3781 ocp_data |= PWR_EN | PHASE2_EN; 3782 else 3783 ocp_data &= ~PWR_EN; 3784 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3785 3786 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3787 ocp_data &= ~PCUT_STATUS; 3788 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3789 } 3790 3791 static void r8153_queue_wake(struct r8152 *tp, bool enable) 3792 { 3793 u32 ocp_data; 3794 3795 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 3796 if (enable) 3797 ocp_data |= UPCOMING_RUNTIME_D3; 3798 else 3799 ocp_data &= ~UPCOMING_RUNTIME_D3; 3800 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 3801 3802 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 3803 ocp_data &= ~LINK_CHG_EVENT; 3804 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 3805 3806 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 3807 ocp_data &= ~LINK_CHANGE_FLAG; 3808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 3809 } 3810 3811 static bool rtl_can_wakeup(struct r8152 *tp) 3812 { 3813 struct usb_device *udev = tp->udev; 3814 3815 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 3816 } 3817 3818 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 3819 { 3820 if (enable) { 3821 u32 ocp_data; 3822 3823 __rtl_set_wol(tp, WAKE_ANY); 3824 3825 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3826 3827 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3828 ocp_data |= LINK_OFF_WAKE_EN; 3829 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3830 3831 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3832 } else { 3833 u32 ocp_data; 3834 3835 __rtl_set_wol(tp, tp->saved_wolopts); 3836 3837 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3838 3839 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3840 ocp_data &= ~LINK_OFF_WAKE_EN; 3841 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3842 3843 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3844 } 3845 } 3846 3847 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 3848 { 3849 if (enable) { 3850 r8153_u1u2en(tp, false); 3851 r8153_u2p3en(tp, false); 3852 rtl_runtime_suspend_enable(tp, true); 3853 } else { 3854 rtl_runtime_suspend_enable(tp, false); 3855 3856 switch (tp->version) { 3857 case RTL_VER_03: 3858 case RTL_VER_04: 3859 break; 3860 case RTL_VER_05: 3861 case RTL_VER_06: 3862 default: 3863 r8153_u2p3en(tp, true); 3864 break; 3865 } 3866 3867 r8153_u1u2en(tp, true); 3868 } 3869 } 3870 3871 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 3872 { 3873 if (enable) { 3874 r8153_queue_wake(tp, true); 3875 r8153b_u1u2en(tp, false); 3876 r8153_u2p3en(tp, false); 3877 rtl_runtime_suspend_enable(tp, true); 3878 r8153b_ups_en(tp, true); 3879 } else { 3880 r8153b_ups_en(tp, false); 3881 r8153_queue_wake(tp, false); 3882 rtl_runtime_suspend_enable(tp, false); 3883 if (tp->udev->speed >= USB_SPEED_SUPER) 3884 r8153b_u1u2en(tp, true); 3885 } 3886 } 3887 3888 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) 3889 { 3890 if (enable) { 3891 r8153_queue_wake(tp, true); 3892 r8153b_u1u2en(tp, false); 3893 r8153_u2p3en(tp, false); 3894 rtl_runtime_suspend_enable(tp, true); 3895 r8153c_ups_en(tp, true); 3896 } else { 3897 r8153c_ups_en(tp, false); 3898 r8153_queue_wake(tp, false); 3899 rtl_runtime_suspend_enable(tp, false); 3900 r8153b_u1u2en(tp, true); 3901 } 3902 } 3903 3904 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) 3905 { 3906 if (enable) { 3907 r8153_queue_wake(tp, true); 3908 r8153b_u1u2en(tp, false); 3909 r8153_u2p3en(tp, false); 3910 rtl_runtime_suspend_enable(tp, true); 3911 } else { 3912 r8153_queue_wake(tp, false); 3913 rtl_runtime_suspend_enable(tp, false); 3914 r8153_u2p3en(tp, true); 3915 if (tp->udev->speed >= USB_SPEED_SUPER) 3916 r8153b_u1u2en(tp, true); 3917 } 3918 } 3919 3920 static void r8153_teredo_off(struct r8152 *tp) 3921 { 3922 u32 ocp_data; 3923 3924 switch (tp->version) { 3925 case RTL_VER_01: 3926 case RTL_VER_02: 3927 case RTL_VER_03: 3928 case RTL_VER_04: 3929 case RTL_VER_05: 3930 case RTL_VER_06: 3931 case RTL_VER_07: 3932 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3933 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 3934 OOB_TEREDO_EN); 3935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3936 break; 3937 3938 case RTL_VER_08: 3939 case RTL_VER_09: 3940 case RTL_TEST_01: 3941 case RTL_VER_10: 3942 case RTL_VER_11: 3943 case RTL_VER_12: 3944 case RTL_VER_13: 3945 case RTL_VER_14: 3946 case RTL_VER_15: 3947 default: 3948 /* The bit 0 ~ 7 are relative with teredo settings. They are 3949 * W1C (write 1 to clear), so set all 1 to disable it. 3950 */ 3951 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 3952 break; 3953 } 3954 3955 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 3956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 3957 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 3958 } 3959 3960 static void rtl_reset_bmu(struct r8152 *tp) 3961 { 3962 u32 ocp_data; 3963 3964 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 3965 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 3966 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3967 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 3968 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3969 } 3970 3971 /* Clear the bp to stop the firmware before loading a new one */ 3972 static void rtl_clear_bp(struct r8152 *tp, u16 type) 3973 { 3974 switch (tp->version) { 3975 case RTL_VER_01: 3976 case RTL_VER_02: 3977 case RTL_VER_07: 3978 break; 3979 case RTL_VER_03: 3980 case RTL_VER_04: 3981 case RTL_VER_05: 3982 case RTL_VER_06: 3983 ocp_write_byte(tp, type, PLA_BP_EN, 0); 3984 break; 3985 case RTL_VER_14: 3986 ocp_write_word(tp, type, USB_BP2_EN, 0); 3987 3988 ocp_write_word(tp, type, USB_BP_8, 0); 3989 ocp_write_word(tp, type, USB_BP_9, 0); 3990 ocp_write_word(tp, type, USB_BP_10, 0); 3991 ocp_write_word(tp, type, USB_BP_11, 0); 3992 ocp_write_word(tp, type, USB_BP_12, 0); 3993 ocp_write_word(tp, type, USB_BP_13, 0); 3994 ocp_write_word(tp, type, USB_BP_14, 0); 3995 ocp_write_word(tp, type, USB_BP_15, 0); 3996 break; 3997 case RTL_VER_08: 3998 case RTL_VER_09: 3999 case RTL_VER_10: 4000 case RTL_VER_11: 4001 case RTL_VER_12: 4002 case RTL_VER_13: 4003 case RTL_VER_15: 4004 default: 4005 if (type == MCU_TYPE_USB) { 4006 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); 4007 4008 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0); 4009 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0); 4010 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0); 4011 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0); 4012 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0); 4013 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0); 4014 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0); 4015 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0); 4016 } else { 4017 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); 4018 } 4019 break; 4020 } 4021 4022 ocp_write_word(tp, type, PLA_BP_0, 0); 4023 ocp_write_word(tp, type, PLA_BP_1, 0); 4024 ocp_write_word(tp, type, PLA_BP_2, 0); 4025 ocp_write_word(tp, type, PLA_BP_3, 0); 4026 ocp_write_word(tp, type, PLA_BP_4, 0); 4027 ocp_write_word(tp, type, PLA_BP_5, 0); 4028 ocp_write_word(tp, type, PLA_BP_6, 0); 4029 ocp_write_word(tp, type, PLA_BP_7, 0); 4030 4031 /* wait 3 ms to make sure the firmware is stopped */ 4032 usleep_range(3000, 6000); 4033 ocp_write_word(tp, type, PLA_BP_BA, 0); 4034 } 4035 4036 static inline void rtl_reset_ocp_base(struct r8152 *tp) 4037 { 4038 tp->ocp_base = -1; 4039 } 4040 4041 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) 4042 { 4043 u16 data, check; 4044 int i; 4045 4046 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 4047 if (request) { 4048 data |= PATCH_REQUEST; 4049 check = 0; 4050 } else { 4051 data &= ~PATCH_REQUEST; 4052 check = PATCH_READY; 4053 } 4054 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 4055 4056 for (i = 0; wait && i < 5000; i++) { 4057 u32 ocp_data; 4058 4059 usleep_range(1000, 2000); 4060 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); 4061 if ((ocp_data & PATCH_READY) ^ check) 4062 break; 4063 } 4064 4065 if (request && wait && 4066 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 4067 dev_err(&tp->intf->dev, "PHY patch request fail\n"); 4068 rtl_phy_patch_request(tp, false, false); 4069 return -ETIME; 4070 } else { 4071 return 0; 4072 } 4073 } 4074 4075 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) 4076 { 4077 if (patch_key && key_addr) { 4078 sram_write(tp, key_addr, patch_key); 4079 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); 4080 } else if (key_addr) { 4081 u16 data; 4082 4083 sram_write(tp, 0x0000, 0x0000); 4084 4085 data = ocp_reg_read(tp, OCP_PHY_LOCK); 4086 data &= ~PATCH_LOCK; 4087 ocp_reg_write(tp, OCP_PHY_LOCK, data); 4088 4089 sram_write(tp, key_addr, 0x0000); 4090 } else { 4091 WARN_ON_ONCE(1); 4092 } 4093 } 4094 4095 static int 4096 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) 4097 { 4098 if (rtl_phy_patch_request(tp, true, wait)) 4099 return -ETIME; 4100 4101 rtl_patch_key_set(tp, key_addr, patch_key); 4102 4103 return 0; 4104 } 4105 4106 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) 4107 { 4108 rtl_patch_key_set(tp, key_addr, 0); 4109 4110 rtl_phy_patch_request(tp, false, wait); 4111 4112 return 0; 4113 } 4114 4115 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) 4116 { 4117 u16 fw_offset; 4118 u32 length; 4119 bool rc = false; 4120 4121 switch (tp->version) { 4122 case RTL_VER_01: 4123 case RTL_VER_02: 4124 case RTL_VER_03: 4125 case RTL_VER_04: 4126 case RTL_VER_05: 4127 case RTL_VER_06: 4128 case RTL_VER_07: 4129 case RTL_VER_08: 4130 case RTL_VER_09: 4131 case RTL_VER_10: 4132 case RTL_VER_11: 4133 case RTL_VER_12: 4134 case RTL_VER_14: 4135 goto out; 4136 case RTL_VER_13: 4137 case RTL_VER_15: 4138 default: 4139 break; 4140 } 4141 4142 fw_offset = __le16_to_cpu(phy->fw_offset); 4143 length = __le32_to_cpu(phy->blk_hdr.length); 4144 if (fw_offset < sizeof(*phy) || length <= fw_offset) { 4145 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4146 goto out; 4147 } 4148 4149 length -= fw_offset; 4150 if (length & 3) { 4151 dev_err(&tp->intf->dev, "invalid block length\n"); 4152 goto out; 4153 } 4154 4155 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { 4156 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4157 goto out; 4158 } 4159 4160 rc = true; 4161 out: 4162 return rc; 4163 } 4164 4165 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) 4166 { 4167 bool rc = false; 4168 4169 switch (tp->version) { 4170 case RTL_VER_10: 4171 case RTL_VER_11: 4172 case RTL_VER_12: 4173 case RTL_VER_13: 4174 case RTL_VER_15: 4175 break; 4176 default: 4177 goto out; 4178 } 4179 4180 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) { 4181 dev_err(&tp->intf->dev, "invalid block length\n"); 4182 goto out; 4183 } 4184 4185 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) { 4186 dev_err(&tp->intf->dev, "invalid phy ver addr\n"); 4187 goto out; 4188 } 4189 4190 rc = true; 4191 out: 4192 return rc; 4193 } 4194 4195 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) 4196 { 4197 bool rc = false; 4198 4199 switch (tp->version) { 4200 case RTL_VER_10: 4201 case RTL_VER_11: 4202 case RTL_VER_12: 4203 case RTL_VER_13: 4204 case RTL_VER_15: 4205 break; 4206 default: 4207 goto out; 4208 } 4209 4210 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) { 4211 dev_err(&tp->intf->dev, "invalid block length\n"); 4212 goto out; 4213 } 4214 4215 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD || 4216 __le16_to_cpu(fix->setting.data) != BIT(7)) { 4217 dev_err(&tp->intf->dev, "invalid phy fixup\n"); 4218 goto out; 4219 } 4220 4221 rc = true; 4222 out: 4223 return rc; 4224 } 4225 4226 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) 4227 { 4228 u16 fw_offset; 4229 u32 length; 4230 bool rc = false; 4231 4232 switch (tp->version) { 4233 case RTL_VER_10: 4234 case RTL_VER_11: 4235 case RTL_VER_12: 4236 case RTL_VER_13: 4237 case RTL_VER_15: 4238 break; 4239 default: 4240 goto out; 4241 } 4242 4243 fw_offset = __le16_to_cpu(phy->fw_offset); 4244 length = __le32_to_cpu(phy->blk_hdr.length); 4245 if (fw_offset < sizeof(*phy) || length <= fw_offset) { 4246 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4247 goto out; 4248 } 4249 4250 length -= fw_offset; 4251 if (length & 1) { 4252 dev_err(&tp->intf->dev, "invalid block length\n"); 4253 goto out; 4254 } 4255 4256 if (phy->pre_num > 2) { 4257 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num); 4258 goto out; 4259 } 4260 4261 if (phy->bp_num > 8) { 4262 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num); 4263 goto out; 4264 } 4265 4266 rc = true; 4267 out: 4268 return rc; 4269 } 4270 4271 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) 4272 { 4273 u32 length; 4274 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start; 4275 bool rc = false; 4276 4277 switch (tp->version) { 4278 case RTL_VER_04: 4279 case RTL_VER_05: 4280 case RTL_VER_06: 4281 fw_reg = 0xa014; 4282 ba_reg = 0xa012; 4283 patch_en_addr = 0xa01a; 4284 mode_reg = 0xb820; 4285 bp_start = 0xa000; 4286 break; 4287 default: 4288 goto out; 4289 } 4290 4291 fw_offset = __le16_to_cpu(phy->fw_offset); 4292 if (fw_offset < sizeof(*phy)) { 4293 dev_err(&tp->intf->dev, "fw_offset too small\n"); 4294 goto out; 4295 } 4296 4297 length = __le32_to_cpu(phy->blk_hdr.length); 4298 if (length < fw_offset) { 4299 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4300 goto out; 4301 } 4302 4303 length -= __le16_to_cpu(phy->fw_offset); 4304 if (!length || (length & 1)) { 4305 dev_err(&tp->intf->dev, "invalid block length\n"); 4306 goto out; 4307 } 4308 4309 if (__le16_to_cpu(phy->fw_reg) != fw_reg) { 4310 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4311 goto out; 4312 } 4313 4314 if (__le16_to_cpu(phy->ba_reg) != ba_reg) { 4315 dev_err(&tp->intf->dev, "invalid base address register\n"); 4316 goto out; 4317 } 4318 4319 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) { 4320 dev_err(&tp->intf->dev, 4321 "invalid patch mode enabled register\n"); 4322 goto out; 4323 } 4324 4325 if (__le16_to_cpu(phy->mode_reg) != mode_reg) { 4326 dev_err(&tp->intf->dev, 4327 "invalid register to switch the mode\n"); 4328 goto out; 4329 } 4330 4331 if (__le16_to_cpu(phy->bp_start) != bp_start) { 4332 dev_err(&tp->intf->dev, 4333 "invalid start register of break point\n"); 4334 goto out; 4335 } 4336 4337 if (__le16_to_cpu(phy->bp_num) > 4) { 4338 dev_err(&tp->intf->dev, "invalid break point number\n"); 4339 goto out; 4340 } 4341 4342 rc = true; 4343 out: 4344 return rc; 4345 } 4346 4347 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac) 4348 { 4349 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset; 4350 bool rc = false; 4351 u32 length, type; 4352 int i, max_bp; 4353 4354 type = __le32_to_cpu(mac->blk_hdr.type); 4355 if (type == RTL_FW_PLA) { 4356 switch (tp->version) { 4357 case RTL_VER_01: 4358 case RTL_VER_02: 4359 case RTL_VER_07: 4360 fw_reg = 0xf800; 4361 bp_ba_addr = PLA_BP_BA; 4362 bp_en_addr = 0; 4363 bp_start = PLA_BP_0; 4364 max_bp = 8; 4365 break; 4366 case RTL_VER_03: 4367 case RTL_VER_04: 4368 case RTL_VER_05: 4369 case RTL_VER_06: 4370 case RTL_VER_08: 4371 case RTL_VER_09: 4372 case RTL_VER_11: 4373 case RTL_VER_12: 4374 case RTL_VER_13: 4375 case RTL_VER_15: 4376 fw_reg = 0xf800; 4377 bp_ba_addr = PLA_BP_BA; 4378 bp_en_addr = PLA_BP_EN; 4379 bp_start = PLA_BP_0; 4380 max_bp = 8; 4381 break; 4382 case RTL_VER_14: 4383 fw_reg = 0xf800; 4384 bp_ba_addr = PLA_BP_BA; 4385 bp_en_addr = USB_BP2_EN; 4386 bp_start = PLA_BP_0; 4387 max_bp = 16; 4388 break; 4389 default: 4390 goto out; 4391 } 4392 } else if (type == RTL_FW_USB) { 4393 switch (tp->version) { 4394 case RTL_VER_03: 4395 case RTL_VER_04: 4396 case RTL_VER_05: 4397 case RTL_VER_06: 4398 fw_reg = 0xf800; 4399 bp_ba_addr = USB_BP_BA; 4400 bp_en_addr = USB_BP_EN; 4401 bp_start = USB_BP_0; 4402 max_bp = 8; 4403 break; 4404 case RTL_VER_08: 4405 case RTL_VER_09: 4406 case RTL_VER_11: 4407 case RTL_VER_12: 4408 case RTL_VER_13: 4409 case RTL_VER_14: 4410 case RTL_VER_15: 4411 fw_reg = 0xe600; 4412 bp_ba_addr = USB_BP_BA; 4413 bp_en_addr = USB_BP2_EN; 4414 bp_start = USB_BP_0; 4415 max_bp = 16; 4416 break; 4417 case RTL_VER_01: 4418 case RTL_VER_02: 4419 case RTL_VER_07: 4420 default: 4421 goto out; 4422 } 4423 } else { 4424 goto out; 4425 } 4426 4427 fw_offset = __le16_to_cpu(mac->fw_offset); 4428 if (fw_offset < sizeof(*mac)) { 4429 dev_err(&tp->intf->dev, "fw_offset too small\n"); 4430 goto out; 4431 } 4432 4433 length = __le32_to_cpu(mac->blk_hdr.length); 4434 if (length < fw_offset) { 4435 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4436 goto out; 4437 } 4438 4439 length -= fw_offset; 4440 if (length < 4 || (length & 3)) { 4441 dev_err(&tp->intf->dev, "invalid block length\n"); 4442 goto out; 4443 } 4444 4445 if (__le16_to_cpu(mac->fw_reg) != fw_reg) { 4446 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4447 goto out; 4448 } 4449 4450 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) { 4451 dev_err(&tp->intf->dev, "invalid base address register\n"); 4452 goto out; 4453 } 4454 4455 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) { 4456 dev_err(&tp->intf->dev, "invalid enabled mask register\n"); 4457 goto out; 4458 } 4459 4460 if (__le16_to_cpu(mac->bp_start) != bp_start) { 4461 dev_err(&tp->intf->dev, 4462 "invalid start register of break point\n"); 4463 goto out; 4464 } 4465 4466 if (__le16_to_cpu(mac->bp_num) > max_bp) { 4467 dev_err(&tp->intf->dev, "invalid break point number\n"); 4468 goto out; 4469 } 4470 4471 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) { 4472 if (mac->bp[i]) { 4473 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i); 4474 goto out; 4475 } 4476 } 4477 4478 rc = true; 4479 out: 4480 return rc; 4481 } 4482 4483 /* Verify the checksum for the firmware file. It is calculated from the version 4484 * field to the end of the file. Compare the result with the checksum field to 4485 * make sure the file is correct. 4486 */ 4487 static long rtl8152_fw_verify_checksum(struct r8152 *tp, 4488 struct fw_header *fw_hdr, size_t size) 4489 { 4490 unsigned char checksum[sizeof(fw_hdr->checksum)]; 4491 struct crypto_shash *alg; 4492 struct shash_desc *sdesc; 4493 size_t len; 4494 long rc; 4495 4496 alg = crypto_alloc_shash("sha256", 0, 0); 4497 if (IS_ERR(alg)) { 4498 rc = PTR_ERR(alg); 4499 goto out; 4500 } 4501 4502 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) { 4503 rc = -EFAULT; 4504 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n", 4505 crypto_shash_digestsize(alg)); 4506 goto free_shash; 4507 } 4508 4509 len = sizeof(*sdesc) + crypto_shash_descsize(alg); 4510 sdesc = kmalloc(len, GFP_KERNEL); 4511 if (!sdesc) { 4512 rc = -ENOMEM; 4513 goto free_shash; 4514 } 4515 sdesc->tfm = alg; 4516 4517 len = size - sizeof(fw_hdr->checksum); 4518 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum); 4519 kfree(sdesc); 4520 if (rc) 4521 goto free_shash; 4522 4523 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) { 4524 dev_err(&tp->intf->dev, "checksum fail\n"); 4525 rc = -EFAULT; 4526 } 4527 4528 free_shash: 4529 crypto_free_shash(alg); 4530 out: 4531 return rc; 4532 } 4533 4534 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw) 4535 { 4536 const struct firmware *fw = rtl_fw->fw; 4537 struct fw_header *fw_hdr = (struct fw_header *)fw->data; 4538 unsigned long fw_flags = 0; 4539 long ret = -EFAULT; 4540 int i; 4541 4542 if (fw->size < sizeof(*fw_hdr)) { 4543 dev_err(&tp->intf->dev, "file too small\n"); 4544 goto fail; 4545 } 4546 4547 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size); 4548 if (ret) 4549 goto fail; 4550 4551 ret = -EFAULT; 4552 4553 for (i = sizeof(*fw_hdr); i < fw->size;) { 4554 struct fw_block *block = (struct fw_block *)&fw->data[i]; 4555 u32 type; 4556 4557 if ((i + sizeof(*block)) > fw->size) 4558 goto fail; 4559 4560 type = __le32_to_cpu(block->type); 4561 switch (type) { 4562 case RTL_FW_END: 4563 if (__le32_to_cpu(block->length) != sizeof(*block)) 4564 goto fail; 4565 goto fw_end; 4566 case RTL_FW_PLA: 4567 if (test_bit(FW_FLAGS_PLA, &fw_flags)) { 4568 dev_err(&tp->intf->dev, 4569 "multiple PLA firmware encountered"); 4570 goto fail; 4571 } 4572 4573 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { 4574 dev_err(&tp->intf->dev, 4575 "check PLA firmware failed\n"); 4576 goto fail; 4577 } 4578 __set_bit(FW_FLAGS_PLA, &fw_flags); 4579 break; 4580 case RTL_FW_USB: 4581 if (test_bit(FW_FLAGS_USB, &fw_flags)) { 4582 dev_err(&tp->intf->dev, 4583 "multiple USB firmware encountered"); 4584 goto fail; 4585 } 4586 4587 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { 4588 dev_err(&tp->intf->dev, 4589 "check USB firmware failed\n"); 4590 goto fail; 4591 } 4592 __set_bit(FW_FLAGS_USB, &fw_flags); 4593 break; 4594 case RTL_FW_PHY_START: 4595 if (test_bit(FW_FLAGS_START, &fw_flags) || 4596 test_bit(FW_FLAGS_NC, &fw_flags) || 4597 test_bit(FW_FLAGS_NC1, &fw_flags) || 4598 test_bit(FW_FLAGS_NC2, &fw_flags) || 4599 test_bit(FW_FLAGS_UC2, &fw_flags) || 4600 test_bit(FW_FLAGS_UC, &fw_flags) || 4601 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4602 dev_err(&tp->intf->dev, 4603 "check PHY_START fail\n"); 4604 goto fail; 4605 } 4606 4607 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) { 4608 dev_err(&tp->intf->dev, 4609 "Invalid length for PHY_START\n"); 4610 goto fail; 4611 } 4612 __set_bit(FW_FLAGS_START, &fw_flags); 4613 break; 4614 case RTL_FW_PHY_STOP: 4615 if (test_bit(FW_FLAGS_STOP, &fw_flags) || 4616 !test_bit(FW_FLAGS_START, &fw_flags)) { 4617 dev_err(&tp->intf->dev, 4618 "Check PHY_STOP fail\n"); 4619 goto fail; 4620 } 4621 4622 if (__le32_to_cpu(block->length) != sizeof(*block)) { 4623 dev_err(&tp->intf->dev, 4624 "Invalid length for PHY_STOP\n"); 4625 goto fail; 4626 } 4627 __set_bit(FW_FLAGS_STOP, &fw_flags); 4628 break; 4629 case RTL_FW_PHY_NC: 4630 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4631 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4632 dev_err(&tp->intf->dev, 4633 "check PHY_NC fail\n"); 4634 goto fail; 4635 } 4636 4637 if (test_bit(FW_FLAGS_NC, &fw_flags)) { 4638 dev_err(&tp->intf->dev, 4639 "multiple PHY NC encountered\n"); 4640 goto fail; 4641 } 4642 4643 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) { 4644 dev_err(&tp->intf->dev, 4645 "check PHY NC firmware failed\n"); 4646 goto fail; 4647 } 4648 __set_bit(FW_FLAGS_NC, &fw_flags); 4649 break; 4650 case RTL_FW_PHY_UNION_NC: 4651 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4652 test_bit(FW_FLAGS_NC1, &fw_flags) || 4653 test_bit(FW_FLAGS_NC2, &fw_flags) || 4654 test_bit(FW_FLAGS_UC2, &fw_flags) || 4655 test_bit(FW_FLAGS_UC, &fw_flags) || 4656 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4657 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n"); 4658 goto fail; 4659 } 4660 4661 if (test_bit(FW_FLAGS_NC, &fw_flags)) { 4662 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n"); 4663 goto fail; 4664 } 4665 4666 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4667 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n"); 4668 goto fail; 4669 } 4670 __set_bit(FW_FLAGS_NC, &fw_flags); 4671 break; 4672 case RTL_FW_PHY_UNION_NC1: 4673 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4674 test_bit(FW_FLAGS_NC2, &fw_flags) || 4675 test_bit(FW_FLAGS_UC2, &fw_flags) || 4676 test_bit(FW_FLAGS_UC, &fw_flags) || 4677 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4678 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n"); 4679 goto fail; 4680 } 4681 4682 if (test_bit(FW_FLAGS_NC1, &fw_flags)) { 4683 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n"); 4684 goto fail; 4685 } 4686 4687 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4688 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n"); 4689 goto fail; 4690 } 4691 __set_bit(FW_FLAGS_NC1, &fw_flags); 4692 break; 4693 case RTL_FW_PHY_UNION_NC2: 4694 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4695 test_bit(FW_FLAGS_UC2, &fw_flags) || 4696 test_bit(FW_FLAGS_UC, &fw_flags) || 4697 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4698 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n"); 4699 goto fail; 4700 } 4701 4702 if (test_bit(FW_FLAGS_NC2, &fw_flags)) { 4703 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n"); 4704 goto fail; 4705 } 4706 4707 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4708 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n"); 4709 goto fail; 4710 } 4711 __set_bit(FW_FLAGS_NC2, &fw_flags); 4712 break; 4713 case RTL_FW_PHY_UNION_UC2: 4714 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4715 test_bit(FW_FLAGS_UC, &fw_flags) || 4716 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4717 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n"); 4718 goto fail; 4719 } 4720 4721 if (test_bit(FW_FLAGS_UC2, &fw_flags)) { 4722 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n"); 4723 goto fail; 4724 } 4725 4726 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4727 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n"); 4728 goto fail; 4729 } 4730 __set_bit(FW_FLAGS_UC2, &fw_flags); 4731 break; 4732 case RTL_FW_PHY_UNION_UC: 4733 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4734 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4735 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n"); 4736 goto fail; 4737 } 4738 4739 if (test_bit(FW_FLAGS_UC, &fw_flags)) { 4740 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n"); 4741 goto fail; 4742 } 4743 4744 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4745 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n"); 4746 goto fail; 4747 } 4748 __set_bit(FW_FLAGS_UC, &fw_flags); 4749 break; 4750 case RTL_FW_PHY_UNION_MISC: 4751 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4752 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n"); 4753 goto fail; 4754 } 4755 break; 4756 case RTL_FW_PHY_FIXUP: 4757 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) { 4758 dev_err(&tp->intf->dev, "check PHY fixup failed\n"); 4759 goto fail; 4760 } 4761 break; 4762 case RTL_FW_PHY_SPEED_UP: 4763 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) { 4764 dev_err(&tp->intf->dev, "multiple PHY firmware encountered"); 4765 goto fail; 4766 } 4767 4768 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) { 4769 dev_err(&tp->intf->dev, "check PHY speed up failed\n"); 4770 goto fail; 4771 } 4772 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags); 4773 break; 4774 case RTL_FW_PHY_VER: 4775 if (test_bit(FW_FLAGS_START, &fw_flags) || 4776 test_bit(FW_FLAGS_NC, &fw_flags) || 4777 test_bit(FW_FLAGS_NC1, &fw_flags) || 4778 test_bit(FW_FLAGS_NC2, &fw_flags) || 4779 test_bit(FW_FLAGS_UC2, &fw_flags) || 4780 test_bit(FW_FLAGS_UC, &fw_flags) || 4781 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4782 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n"); 4783 goto fail; 4784 } 4785 4786 if (test_bit(FW_FLAGS_VER, &fw_flags)) { 4787 dev_err(&tp->intf->dev, "multiple PHY version encountered"); 4788 goto fail; 4789 } 4790 4791 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) { 4792 dev_err(&tp->intf->dev, "check PHY version failed\n"); 4793 goto fail; 4794 } 4795 __set_bit(FW_FLAGS_VER, &fw_flags); 4796 break; 4797 default: 4798 dev_warn(&tp->intf->dev, "Unknown type %u is found\n", 4799 type); 4800 break; 4801 } 4802 4803 /* next block */ 4804 i += ALIGN(__le32_to_cpu(block->length), 8); 4805 } 4806 4807 fw_end: 4808 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) { 4809 dev_err(&tp->intf->dev, "without PHY_STOP\n"); 4810 goto fail; 4811 } 4812 4813 return 0; 4814 fail: 4815 return ret; 4816 } 4817 4818 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) 4819 { 4820 u32 len; 4821 u8 *data; 4822 4823 rtl_reset_ocp_base(tp); 4824 4825 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) { 4826 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); 4827 return; 4828 } 4829 4830 len = __le32_to_cpu(phy->blk_hdr.length); 4831 len -= __le16_to_cpu(phy->fw_offset); 4832 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset); 4833 4834 if (rtl_phy_patch_request(tp, true, wait)) 4835 return; 4836 4837 while (len) { 4838 u32 ocp_data, size; 4839 int i; 4840 4841 if (len < 2048) 4842 size = len; 4843 else 4844 size = 2048; 4845 4846 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); 4847 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; 4848 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); 4849 4850 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); 4851 4852 data += size; 4853 len -= size; 4854 4855 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); 4856 ocp_data |= POL_GPHY_PATCH; 4857 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); 4858 4859 for (i = 0; i < 1000; i++) { 4860 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) 4861 break; 4862 } 4863 4864 if (i == 1000) { 4865 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n"); 4866 break; 4867 } 4868 } 4869 4870 rtl_reset_ocp_base(tp); 4871 4872 rtl_phy_patch_request(tp, false, wait); 4873 4874 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version)) 4875 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 4876 else 4877 dev_err(&tp->intf->dev, "ram code speedup mode fail\n"); 4878 } 4879 4880 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) 4881 { 4882 u16 ver_addr, ver; 4883 4884 ver_addr = __le16_to_cpu(phy_ver->ver.addr); 4885 ver = __le16_to_cpu(phy_ver->ver.data); 4886 4887 rtl_reset_ocp_base(tp); 4888 4889 if (sram_read(tp, ver_addr) >= ver) { 4890 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); 4891 return 0; 4892 } 4893 4894 sram_write(tp, ver_addr, ver); 4895 4896 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver); 4897 4898 return ver; 4899 } 4900 4901 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) 4902 { 4903 u16 addr, data; 4904 4905 rtl_reset_ocp_base(tp); 4906 4907 addr = __le16_to_cpu(fix->setting.addr); 4908 data = ocp_reg_read(tp, addr); 4909 4910 switch (__le16_to_cpu(fix->bit_cmd)) { 4911 case FW_FIXUP_AND: 4912 data &= __le16_to_cpu(fix->setting.data); 4913 break; 4914 case FW_FIXUP_OR: 4915 data |= __le16_to_cpu(fix->setting.data); 4916 break; 4917 case FW_FIXUP_NOT: 4918 data &= ~__le16_to_cpu(fix->setting.data); 4919 break; 4920 case FW_FIXUP_XOR: 4921 data ^= __le16_to_cpu(fix->setting.data); 4922 break; 4923 default: 4924 return; 4925 } 4926 4927 ocp_reg_write(tp, addr, data); 4928 4929 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data); 4930 } 4931 4932 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) 4933 { 4934 __le16 *data; 4935 u32 length; 4936 int i, num; 4937 4938 rtl_reset_ocp_base(tp); 4939 4940 num = phy->pre_num; 4941 for (i = 0; i < num; i++) 4942 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr), 4943 __le16_to_cpu(phy->pre_set[i].data)); 4944 4945 length = __le32_to_cpu(phy->blk_hdr.length); 4946 length -= __le16_to_cpu(phy->fw_offset); 4947 num = length / 2; 4948 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); 4949 4950 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); 4951 for (i = 0; i < num; i++) 4952 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); 4953 4954 num = phy->bp_num; 4955 for (i = 0; i < num; i++) 4956 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data)); 4957 4958 if (phy->bp_num && phy->bp_en.addr) 4959 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data)); 4960 4961 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 4962 } 4963 4964 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) 4965 { 4966 u16 mode_reg, bp_index; 4967 u32 length, i, num; 4968 __le16 *data; 4969 4970 rtl_reset_ocp_base(tp); 4971 4972 mode_reg = __le16_to_cpu(phy->mode_reg); 4973 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre)); 4974 sram_write(tp, __le16_to_cpu(phy->ba_reg), 4975 __le16_to_cpu(phy->ba_data)); 4976 4977 length = __le32_to_cpu(phy->blk_hdr.length); 4978 length -= __le16_to_cpu(phy->fw_offset); 4979 num = length / 2; 4980 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); 4981 4982 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); 4983 for (i = 0; i < num; i++) 4984 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); 4985 4986 sram_write(tp, __le16_to_cpu(phy->patch_en_addr), 4987 __le16_to_cpu(phy->patch_en_value)); 4988 4989 bp_index = __le16_to_cpu(phy->bp_start); 4990 num = __le16_to_cpu(phy->bp_num); 4991 for (i = 0; i < num; i++) { 4992 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i])); 4993 bp_index += 2; 4994 } 4995 4996 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post)); 4997 4998 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 4999 } 5000 5001 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) 5002 { 5003 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg; 5004 u32 length; 5005 u8 *data; 5006 int i; 5007 5008 switch (__le32_to_cpu(mac->blk_hdr.type)) { 5009 case RTL_FW_PLA: 5010 type = MCU_TYPE_PLA; 5011 break; 5012 case RTL_FW_USB: 5013 type = MCU_TYPE_USB; 5014 break; 5015 default: 5016 return; 5017 } 5018 5019 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); 5020 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) { 5021 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB"); 5022 return; 5023 } 5024 5025 rtl_clear_bp(tp, type); 5026 5027 /* Enable backup/restore of MACDBG. This is required after clearing PLA 5028 * break points and before applying the PLA firmware. 5029 */ 5030 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA && 5031 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) { 5032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM); 5033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM); 5034 } 5035 5036 length = __le32_to_cpu(mac->blk_hdr.length); 5037 length -= __le16_to_cpu(mac->fw_offset); 5038 5039 data = (u8 *)mac; 5040 data += __le16_to_cpu(mac->fw_offset); 5041 5042 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data, 5043 type); 5044 5045 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), 5046 __le16_to_cpu(mac->bp_ba_value)); 5047 5048 bp_index = __le16_to_cpu(mac->bp_start); 5049 bp_num = __le16_to_cpu(mac->bp_num); 5050 for (i = 0; i < bp_num; i++) { 5051 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i])); 5052 bp_index += 2; 5053 } 5054 5055 bp_en_addr = __le16_to_cpu(mac->bp_en_addr); 5056 if (bp_en_addr) 5057 ocp_write_word(tp, type, bp_en_addr, 5058 __le16_to_cpu(mac->bp_en_value)); 5059 5060 if (fw_ver_reg) 5061 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, 5062 mac->fw_ver_data); 5063 5064 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); 5065 } 5066 5067 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) 5068 { 5069 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5070 const struct firmware *fw; 5071 struct fw_header *fw_hdr; 5072 struct fw_phy_patch_key *key; 5073 u16 key_addr = 0; 5074 int i, patch_phy = 1; 5075 5076 if (IS_ERR_OR_NULL(rtl_fw->fw)) 5077 return; 5078 5079 fw = rtl_fw->fw; 5080 fw_hdr = (struct fw_header *)fw->data; 5081 5082 if (rtl_fw->pre_fw) 5083 rtl_fw->pre_fw(tp); 5084 5085 for (i = offsetof(struct fw_header, blocks); i < fw->size;) { 5086 struct fw_block *block = (struct fw_block *)&fw->data[i]; 5087 5088 switch (__le32_to_cpu(block->type)) { 5089 case RTL_FW_END: 5090 goto post_fw; 5091 case RTL_FW_PLA: 5092 case RTL_FW_USB: 5093 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); 5094 break; 5095 case RTL_FW_PHY_START: 5096 if (!patch_phy) 5097 break; 5098 key = (struct fw_phy_patch_key *)block; 5099 key_addr = __le16_to_cpu(key->key_reg); 5100 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); 5101 break; 5102 case RTL_FW_PHY_STOP: 5103 if (!patch_phy) 5104 break; 5105 WARN_ON(!key_addr); 5106 rtl_post_ram_code(tp, key_addr, !power_cut); 5107 break; 5108 case RTL_FW_PHY_NC: 5109 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); 5110 break; 5111 case RTL_FW_PHY_VER: 5112 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block); 5113 break; 5114 case RTL_FW_PHY_UNION_NC: 5115 case RTL_FW_PHY_UNION_NC1: 5116 case RTL_FW_PHY_UNION_NC2: 5117 case RTL_FW_PHY_UNION_UC2: 5118 case RTL_FW_PHY_UNION_UC: 5119 case RTL_FW_PHY_UNION_MISC: 5120 if (patch_phy) 5121 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block); 5122 break; 5123 case RTL_FW_PHY_FIXUP: 5124 if (patch_phy) 5125 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block); 5126 break; 5127 case RTL_FW_PHY_SPEED_UP: 5128 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut); 5129 break; 5130 default: 5131 break; 5132 } 5133 5134 i += ALIGN(__le32_to_cpu(block->length), 8); 5135 } 5136 5137 post_fw: 5138 if (rtl_fw->post_fw) 5139 rtl_fw->post_fw(tp); 5140 5141 rtl_reset_ocp_base(tp); 5142 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE); 5143 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version); 5144 } 5145 5146 static void rtl8152_release_firmware(struct r8152 *tp) 5147 { 5148 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5149 5150 if (!IS_ERR_OR_NULL(rtl_fw->fw)) { 5151 release_firmware(rtl_fw->fw); 5152 rtl_fw->fw = NULL; 5153 } 5154 } 5155 5156 static int rtl8152_request_firmware(struct r8152 *tp) 5157 { 5158 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5159 long rc; 5160 5161 if (rtl_fw->fw || !rtl_fw->fw_name) { 5162 dev_info(&tp->intf->dev, "skip request firmware\n"); 5163 rc = 0; 5164 goto result; 5165 } 5166 5167 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev); 5168 if (rc < 0) 5169 goto result; 5170 5171 rc = rtl8152_check_firmware(tp, rtl_fw); 5172 if (rc < 0) 5173 release_firmware(rtl_fw->fw); 5174 5175 result: 5176 if (rc) { 5177 rtl_fw->fw = ERR_PTR(rc); 5178 5179 dev_warn(&tp->intf->dev, 5180 "unable to load firmware patch %s (%ld)\n", 5181 rtl_fw->fw_name, rc); 5182 } 5183 5184 return rc; 5185 } 5186 5187 static void r8152_aldps_en(struct r8152 *tp, bool enable) 5188 { 5189 if (enable) { 5190 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 5191 LINKENA | DIS_SDSAVE); 5192 } else { 5193 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 5194 DIS_SDSAVE); 5195 msleep(20); 5196 } 5197 } 5198 5199 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 5200 { 5201 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 5202 ocp_reg_write(tp, OCP_EEE_DATA, reg); 5203 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 5204 } 5205 5206 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 5207 { 5208 u16 data; 5209 5210 r8152_mmd_indirect(tp, dev, reg); 5211 data = ocp_reg_read(tp, OCP_EEE_DATA); 5212 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 5213 5214 return data; 5215 } 5216 5217 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 5218 { 5219 r8152_mmd_indirect(tp, dev, reg); 5220 ocp_reg_write(tp, OCP_EEE_DATA, data); 5221 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 5222 } 5223 5224 static void r8152_eee_en(struct r8152 *tp, bool enable) 5225 { 5226 u16 config1, config2, config3; 5227 u32 ocp_data; 5228 5229 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 5230 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 5231 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 5232 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 5233 5234 if (enable) { 5235 ocp_data |= EEE_RX_EN | EEE_TX_EN; 5236 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 5237 config1 |= sd_rise_time(1); 5238 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 5239 config3 |= fast_snr(42); 5240 } else { 5241 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 5242 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 5243 RX_QUIET_EN); 5244 config1 |= sd_rise_time(7); 5245 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 5246 config3 |= fast_snr(511); 5247 } 5248 5249 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 5250 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 5251 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 5252 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 5253 } 5254 5255 static void r8153_eee_en(struct r8152 *tp, bool enable) 5256 { 5257 u32 ocp_data; 5258 u16 config; 5259 5260 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 5261 config = ocp_reg_read(tp, OCP_EEE_CFG); 5262 5263 if (enable) { 5264 ocp_data |= EEE_RX_EN | EEE_TX_EN; 5265 config |= EEE10_EN; 5266 } else { 5267 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 5268 config &= ~EEE10_EN; 5269 } 5270 5271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 5272 ocp_reg_write(tp, OCP_EEE_CFG, config); 5273 5274 tp->ups_info.eee = enable; 5275 } 5276 5277 static void r8156_eee_en(struct r8152 *tp, bool enable) 5278 { 5279 u16 config; 5280 5281 r8153_eee_en(tp, enable); 5282 5283 config = ocp_reg_read(tp, OCP_EEE_ADV2); 5284 5285 if (enable) 5286 config |= MDIO_EEE_2_5GT; 5287 else 5288 config &= ~MDIO_EEE_2_5GT; 5289 5290 ocp_reg_write(tp, OCP_EEE_ADV2, config); 5291 } 5292 5293 static void rtl_eee_enable(struct r8152 *tp, bool enable) 5294 { 5295 switch (tp->version) { 5296 case RTL_VER_01: 5297 case RTL_VER_02: 5298 case RTL_VER_07: 5299 if (enable) { 5300 r8152_eee_en(tp, true); 5301 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 5302 tp->eee_adv); 5303 } else { 5304 r8152_eee_en(tp, false); 5305 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); 5306 } 5307 break; 5308 case RTL_VER_03: 5309 case RTL_VER_04: 5310 case RTL_VER_05: 5311 case RTL_VER_06: 5312 case RTL_VER_08: 5313 case RTL_VER_09: 5314 case RTL_VER_14: 5315 if (enable) { 5316 r8153_eee_en(tp, true); 5317 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 5318 } else { 5319 r8153_eee_en(tp, false); 5320 ocp_reg_write(tp, OCP_EEE_ADV, 0); 5321 } 5322 break; 5323 case RTL_VER_10: 5324 case RTL_VER_11: 5325 case RTL_VER_12: 5326 case RTL_VER_13: 5327 case RTL_VER_15: 5328 if (enable) { 5329 r8156_eee_en(tp, true); 5330 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 5331 } else { 5332 r8156_eee_en(tp, false); 5333 ocp_reg_write(tp, OCP_EEE_ADV, 0); 5334 } 5335 break; 5336 default: 5337 break; 5338 } 5339 } 5340 5341 static void r8152b_enable_fc(struct r8152 *tp) 5342 { 5343 u16 anar; 5344 5345 anar = r8152_mdio_read(tp, MII_ADVERTISE); 5346 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 5347 r8152_mdio_write(tp, MII_ADVERTISE, anar); 5348 5349 tp->ups_info.flow_control = true; 5350 } 5351 5352 static void rtl8152_disable(struct r8152 *tp) 5353 { 5354 r8152_aldps_en(tp, false); 5355 rtl_disable(tp); 5356 r8152_aldps_en(tp, true); 5357 } 5358 5359 static void r8152b_hw_phy_cfg(struct r8152 *tp) 5360 { 5361 rtl8152_apply_firmware(tp, false); 5362 rtl_eee_enable(tp, tp->eee_en); 5363 r8152_aldps_en(tp, true); 5364 r8152b_enable_fc(tp); 5365 5366 set_bit(PHY_RESET, &tp->flags); 5367 } 5368 5369 static void wait_oob_link_list_ready(struct r8152 *tp) 5370 { 5371 u32 ocp_data; 5372 int i; 5373 5374 for (i = 0; i < 1000; i++) { 5375 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5376 if (ocp_data & LINK_LIST_READY) 5377 break; 5378 usleep_range(1000, 2000); 5379 } 5380 } 5381 5382 static void r8156b_wait_loading_flash(struct r8152 *tp) 5383 { 5384 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) && 5385 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) { 5386 int i; 5387 5388 for (i = 0; i < 100; i++) { 5389 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE) 5390 break; 5391 usleep_range(1000, 2000); 5392 } 5393 } 5394 } 5395 5396 static void r8152b_exit_oob(struct r8152 *tp) 5397 { 5398 u32 ocp_data; 5399 5400 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5401 ocp_data &= ~RCR_ACPT_ALL; 5402 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5403 5404 rxdy_gated_en(tp, true); 5405 r8153_teredo_off(tp); 5406 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 5407 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 5408 5409 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5410 ocp_data &= ~NOW_IS_OOB; 5411 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5412 5413 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5414 ocp_data &= ~MCU_BORW_EN; 5415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5416 5417 wait_oob_link_list_ready(tp); 5418 5419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5420 ocp_data |= RE_INIT_LL; 5421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5422 5423 wait_oob_link_list_ready(tp); 5424 5425 rtl8152_nic_reset(tp); 5426 5427 /* rx share fifo credit full threshold */ 5428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 5429 5430 if (tp->udev->speed == USB_SPEED_FULL || 5431 tp->udev->speed == USB_SPEED_LOW) { 5432 /* rx share fifo credit near full threshold */ 5433 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 5434 RXFIFO_THR2_FULL); 5435 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 5436 RXFIFO_THR3_FULL); 5437 } else { 5438 /* rx share fifo credit near full threshold */ 5439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 5440 RXFIFO_THR2_HIGH); 5441 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 5442 RXFIFO_THR3_HIGH); 5443 } 5444 5445 /* TX share fifo free credit full threshold */ 5446 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 5447 5448 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 5449 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 5450 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 5451 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 5452 5453 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 5454 5455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 5456 5457 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 5458 ocp_data |= TCR0_AUTO_FIFO; 5459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 5460 } 5461 5462 static void r8152b_enter_oob(struct r8152 *tp) 5463 { 5464 u32 ocp_data; 5465 5466 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5467 ocp_data &= ~NOW_IS_OOB; 5468 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5469 5470 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 5471 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 5472 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 5473 5474 rtl_disable(tp); 5475 5476 wait_oob_link_list_ready(tp); 5477 5478 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5479 ocp_data |= RE_INIT_LL; 5480 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5481 5482 wait_oob_link_list_ready(tp); 5483 5484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 5485 5486 rtl_rx_vlan_en(tp, true); 5487 5488 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 5489 ocp_data |= ALDPS_PROXY_MODE; 5490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 5491 5492 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5493 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 5494 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5495 5496 rxdy_gated_en(tp, false); 5497 5498 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5499 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 5500 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5501 } 5502 5503 static int r8153_pre_firmware_1(struct r8152 *tp) 5504 { 5505 int i; 5506 5507 /* Wait till the WTD timer is ready. It would take at most 104 ms. */ 5508 for (i = 0; i < 104; i++) { 5509 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL); 5510 5511 if (!(ocp_data & WTD1_EN)) 5512 break; 5513 usleep_range(1000, 2000); 5514 } 5515 5516 return 0; 5517 } 5518 5519 static int r8153_post_firmware_1(struct r8152 *tp) 5520 { 5521 /* set USB_BP_4 to support USB_SPEED_SUPER only */ 5522 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) 5523 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY); 5524 5525 /* reset UPHY timer to 36 ms */ 5526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); 5527 5528 return 0; 5529 } 5530 5531 static int r8153_pre_firmware_2(struct r8152 *tp) 5532 { 5533 u32 ocp_data; 5534 5535 r8153_pre_firmware_1(tp); 5536 5537 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); 5538 ocp_data &= ~FW_FIX_SUSPEND; 5539 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); 5540 5541 return 0; 5542 } 5543 5544 static int r8153_post_firmware_2(struct r8152 *tp) 5545 { 5546 u32 ocp_data; 5547 5548 /* enable bp0 if support USB_SPEED_SUPER only */ 5549 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { 5550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); 5551 ocp_data |= BIT(0); 5552 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); 5553 } 5554 5555 /* reset UPHY timer to 36 ms */ 5556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); 5557 5558 /* enable U3P3 check, set the counter to 4 */ 5559 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); 5560 5561 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); 5562 ocp_data |= FW_FIX_SUSPEND; 5563 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); 5564 5565 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 5566 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 5567 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 5568 5569 return 0; 5570 } 5571 5572 static int r8153_post_firmware_3(struct r8152 *tp) 5573 { 5574 u32 ocp_data; 5575 5576 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 5577 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 5578 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 5579 5580 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5581 ocp_data |= FW_IP_RESET_EN; 5582 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5583 5584 return 0; 5585 } 5586 5587 static int r8153b_pre_firmware_1(struct r8152 *tp) 5588 { 5589 /* enable fc timer and set timer to 1 second. */ 5590 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, 5591 CTRL_TIMER_EN | (1000 / 8)); 5592 5593 return 0; 5594 } 5595 5596 static int r8153b_post_firmware_1(struct r8152 *tp) 5597 { 5598 u32 ocp_data; 5599 5600 /* enable bp0 for RTL8153-BND */ 5601 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 5602 if (ocp_data & BND_MASK) { 5603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); 5604 ocp_data |= BIT(0); 5605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); 5606 } 5607 5608 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 5609 ocp_data |= FLOW_CTRL_PATCH_OPT; 5610 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 5611 5612 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 5613 ocp_data |= FC_PATCH_TASK; 5614 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 5615 5616 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5617 ocp_data |= FW_IP_RESET_EN; 5618 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5619 5620 return 0; 5621 } 5622 5623 static int r8153c_post_firmware_1(struct r8152 *tp) 5624 { 5625 u32 ocp_data; 5626 5627 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 5628 ocp_data |= FLOW_CTRL_PATCH_2; 5629 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 5630 5631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 5632 ocp_data |= FC_PATCH_TASK; 5633 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 5634 5635 return 0; 5636 } 5637 5638 static int r8156a_post_firmware_1(struct r8152 *tp) 5639 { 5640 u32 ocp_data; 5641 5642 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5643 ocp_data |= FW_IP_RESET_EN; 5644 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5645 5646 /* Modify U3PHY parameter for compatibility issue */ 5647 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); 5648 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); 5649 5650 return 0; 5651 } 5652 5653 static void r8153_aldps_en(struct r8152 *tp, bool enable) 5654 { 5655 u16 data; 5656 5657 data = ocp_reg_read(tp, OCP_POWER_CFG); 5658 if (enable) { 5659 data |= EN_ALDPS; 5660 ocp_reg_write(tp, OCP_POWER_CFG, data); 5661 } else { 5662 int i; 5663 5664 data &= ~EN_ALDPS; 5665 ocp_reg_write(tp, OCP_POWER_CFG, data); 5666 for (i = 0; i < 20; i++) { 5667 usleep_range(1000, 2000); 5668 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 5669 break; 5670 } 5671 } 5672 5673 tp->ups_info.aldps = enable; 5674 } 5675 5676 static void r8153_hw_phy_cfg(struct r8152 *tp) 5677 { 5678 u32 ocp_data; 5679 u16 data; 5680 5681 /* disable ALDPS before updating the PHY parameters */ 5682 r8153_aldps_en(tp, false); 5683 5684 /* disable EEE before updating the PHY parameters */ 5685 rtl_eee_enable(tp, false); 5686 5687 rtl8152_apply_firmware(tp, false); 5688 5689 if (tp->version == RTL_VER_03) { 5690 data = ocp_reg_read(tp, OCP_EEE_CFG); 5691 data &= ~CTAP_SHORT_EN; 5692 ocp_reg_write(tp, OCP_EEE_CFG, data); 5693 } 5694 5695 data = ocp_reg_read(tp, OCP_POWER_CFG); 5696 data |= EEE_CLKDIV_EN; 5697 ocp_reg_write(tp, OCP_POWER_CFG, data); 5698 5699 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 5700 data |= EN_10M_BGOFF; 5701 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 5702 data = ocp_reg_read(tp, OCP_POWER_CFG); 5703 data |= EN_10M_PLLOFF; 5704 ocp_reg_write(tp, OCP_POWER_CFG, data); 5705 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 5706 5707 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 5708 ocp_data |= PFM_PWM_SWITCH; 5709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 5710 5711 /* Enable LPF corner auto tune */ 5712 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 5713 5714 /* Adjust 10M Amplitude */ 5715 sram_write(tp, SRAM_10M_AMP1, 0x00af); 5716 sram_write(tp, SRAM_10M_AMP2, 0x0208); 5717 5718 if (tp->eee_en) 5719 rtl_eee_enable(tp, true); 5720 5721 r8153_aldps_en(tp, true); 5722 r8152b_enable_fc(tp); 5723 5724 switch (tp->version) { 5725 case RTL_VER_03: 5726 case RTL_VER_04: 5727 break; 5728 case RTL_VER_05: 5729 case RTL_VER_06: 5730 default: 5731 r8153_u2p3en(tp, true); 5732 break; 5733 } 5734 5735 set_bit(PHY_RESET, &tp->flags); 5736 } 5737 5738 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 5739 { 5740 u32 ocp_data; 5741 5742 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 5743 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 5744 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 5745 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 5746 5747 return ocp_data; 5748 } 5749 5750 static void r8153b_hw_phy_cfg(struct r8152 *tp) 5751 { 5752 u32 ocp_data; 5753 u16 data; 5754 5755 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 5756 if (ocp_data & PCUT_STATUS) { 5757 ocp_data &= ~PCUT_STATUS; 5758 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 5759 } 5760 5761 /* disable ALDPS before updating the PHY parameters */ 5762 r8153_aldps_en(tp, false); 5763 5764 /* disable EEE before updating the PHY parameters */ 5765 rtl_eee_enable(tp, false); 5766 5767 /* U1/U2/L1 idle timer. 500 us */ 5768 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 5769 5770 data = r8153_phy_status(tp, 0); 5771 5772 switch (data) { 5773 case PHY_STAT_PWRDN: 5774 case PHY_STAT_EXT_INIT: 5775 rtl8152_apply_firmware(tp, true); 5776 5777 data = r8152_mdio_read(tp, MII_BMCR); 5778 data &= ~BMCR_PDOWN; 5779 r8152_mdio_write(tp, MII_BMCR, data); 5780 break; 5781 case PHY_STAT_LAN_ON: 5782 default: 5783 rtl8152_apply_firmware(tp, false); 5784 break; 5785 } 5786 5787 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 5788 5789 data = sram_read(tp, SRAM_GREEN_CFG); 5790 data |= R_TUNE_EN; 5791 sram_write(tp, SRAM_GREEN_CFG, data); 5792 data = ocp_reg_read(tp, OCP_NCTL_CFG); 5793 data |= PGA_RETURN_EN; 5794 ocp_reg_write(tp, OCP_NCTL_CFG, data); 5795 5796 /* ADC Bias Calibration: 5797 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 5798 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 5799 * ADC ioffset. 5800 */ 5801 ocp_data = r8152_efuse_read(tp, 0x7d); 5802 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 5803 if (data != 0xffff) 5804 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 5805 5806 /* ups mode tx-link-pulse timing adjustment: 5807 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 5808 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 5809 */ 5810 ocp_data = ocp_reg_read(tp, 0xc426); 5811 ocp_data &= 0x3fff; 5812 if (ocp_data) { 5813 u32 swr_cnt_1ms_ini; 5814 5815 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 5816 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 5817 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 5818 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 5819 } 5820 5821 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 5822 ocp_data |= PFM_PWM_SWITCH; 5823 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 5824 5825 /* Advnace EEE */ 5826 if (!rtl_phy_patch_request(tp, true, true)) { 5827 data = ocp_reg_read(tp, OCP_POWER_CFG); 5828 data |= EEE_CLKDIV_EN; 5829 ocp_reg_write(tp, OCP_POWER_CFG, data); 5830 tp->ups_info.eee_ckdiv = true; 5831 5832 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 5833 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 5834 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 5835 tp->ups_info.eee_cmod_lv = true; 5836 tp->ups_info._10m_ckdiv = true; 5837 tp->ups_info.eee_plloff_giga = true; 5838 5839 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 5840 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 5841 tp->ups_info._250m_ckdiv = true; 5842 5843 rtl_phy_patch_request(tp, false, true); 5844 } 5845 5846 if (tp->eee_en) 5847 rtl_eee_enable(tp, true); 5848 5849 r8153_aldps_en(tp, true); 5850 r8152b_enable_fc(tp); 5851 5852 set_bit(PHY_RESET, &tp->flags); 5853 } 5854 5855 static void r8153c_hw_phy_cfg(struct r8152 *tp) 5856 { 5857 r8153b_hw_phy_cfg(tp); 5858 5859 tp->ups_info.r_tune = true; 5860 } 5861 5862 static void rtl8153_change_mtu(struct r8152 *tp) 5863 { 5864 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); 5865 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 5866 } 5867 5868 static void r8153_first_init(struct r8152 *tp) 5869 { 5870 u32 ocp_data; 5871 5872 rxdy_gated_en(tp, true); 5873 r8153_teredo_off(tp); 5874 5875 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5876 ocp_data &= ~RCR_ACPT_ALL; 5877 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5878 5879 rtl8152_nic_reset(tp); 5880 rtl_reset_bmu(tp); 5881 5882 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5883 ocp_data &= ~NOW_IS_OOB; 5884 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5885 5886 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5887 ocp_data &= ~MCU_BORW_EN; 5888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5889 5890 wait_oob_link_list_ready(tp); 5891 5892 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5893 ocp_data |= RE_INIT_LL; 5894 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5895 5896 wait_oob_link_list_ready(tp); 5897 5898 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 5899 5900 rtl8153_change_mtu(tp); 5901 5902 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 5903 ocp_data |= TCR0_AUTO_FIFO; 5904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 5905 5906 rtl8152_nic_reset(tp); 5907 5908 /* rx share fifo credit full threshold */ 5909 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 5910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 5911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 5912 /* TX share fifo free credit full threshold */ 5913 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 5914 } 5915 5916 static void r8153_enter_oob(struct r8152 *tp) 5917 { 5918 u32 ocp_data; 5919 5920 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5921 ocp_data &= ~NOW_IS_OOB; 5922 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5923 5924 /* RX FIFO settings for OOB */ 5925 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 5926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 5927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 5928 5929 rtl_disable(tp); 5930 rtl_reset_bmu(tp); 5931 5932 wait_oob_link_list_ready(tp); 5933 5934 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5935 ocp_data |= RE_INIT_LL; 5936 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5937 5938 wait_oob_link_list_ready(tp); 5939 5940 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); 5941 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); 5942 5943 switch (tp->version) { 5944 case RTL_VER_03: 5945 case RTL_VER_04: 5946 case RTL_VER_05: 5947 case RTL_VER_06: 5948 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 5949 ocp_data &= ~TEREDO_WAKE_MASK; 5950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 5951 break; 5952 5953 case RTL_VER_08: 5954 case RTL_VER_09: 5955 case RTL_VER_14: 5956 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 5957 * type. Set it to zero. bits[7:0] are the W1C bits about 5958 * the events. Set them to all 1 to clear them. 5959 */ 5960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 5961 break; 5962 5963 default: 5964 break; 5965 } 5966 5967 rtl_rx_vlan_en(tp, true); 5968 5969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 5970 ocp_data |= ALDPS_PROXY_MODE; 5971 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 5972 5973 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5974 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 5975 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5976 5977 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5978 ocp_data |= MCU_BORW_EN; 5979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5980 5981 rxdy_gated_en(tp, false); 5982 5983 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5984 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 5985 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5986 } 5987 5988 static void rtl8153_disable(struct r8152 *tp) 5989 { 5990 r8153_aldps_en(tp, false); 5991 rtl_disable(tp); 5992 rtl_reset_bmu(tp); 5993 r8153_aldps_en(tp, true); 5994 } 5995 5996 static u32 fc_pause_on_auto(struct r8152 *tp) 5997 { 5998 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024); 5999 } 6000 6001 static u32 fc_pause_off_auto(struct r8152 *tp) 6002 { 6003 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024); 6004 } 6005 6006 static void r8156_fc_parameter(struct r8152 *tp) 6007 { 6008 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp); 6009 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp); 6010 6011 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16); 6012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16); 6013 } 6014 6015 static int rtl8156_enable(struct r8152 *tp) 6016 { 6017 u32 ocp_data; 6018 u16 speed; 6019 6020 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6021 return -ENODEV; 6022 6023 r8156_fc_parameter(tp); 6024 set_tx_qlen(tp); 6025 rtl_set_eee_plus(tp); 6026 r8153_set_rx_early_timeout(tp); 6027 r8153_set_rx_early_size(tp); 6028 6029 speed = rtl8152_get_speed(tp); 6030 rtl_set_ifg(tp, speed); 6031 6032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 6033 if (speed & _2500bps) 6034 ocp_data &= ~IDLE_SPDWN_EN; 6035 else 6036 ocp_data |= IDLE_SPDWN_EN; 6037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 6038 6039 if (speed & _1000bps) 6040 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); 6041 else if (speed & _500bps) 6042 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); 6043 6044 if (tp->udev->speed == USB_SPEED_HIGH) { 6045 /* USB 0xb45e[3:0] l1_nyet_hird */ 6046 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); 6047 ocp_data &= ~0xf; 6048 if (is_flow_control(speed)) 6049 ocp_data |= 0xf; 6050 else 6051 ocp_data |= 0x1; 6052 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); 6053 } 6054 6055 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 6056 ocp_data &= ~FC_PATCH_TASK; 6057 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6058 usleep_range(1000, 2000); 6059 ocp_data |= FC_PATCH_TASK; 6060 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6061 6062 return rtl_enable(tp); 6063 } 6064 6065 static void rtl8156_disable(struct r8152 *tp) 6066 { 6067 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0); 6068 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0); 6069 6070 rtl8153_disable(tp); 6071 } 6072 6073 static int rtl8156b_enable(struct r8152 *tp) 6074 { 6075 u32 ocp_data; 6076 u16 speed; 6077 6078 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6079 return -ENODEV; 6080 6081 set_tx_qlen(tp); 6082 rtl_set_eee_plus(tp); 6083 6084 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); 6085 ocp_data &= ~RX_AGGR_NUM_MASK; 6086 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); 6087 6088 r8153_set_rx_early_timeout(tp); 6089 r8153_set_rx_early_size(tp); 6090 6091 speed = rtl8152_get_speed(tp); 6092 rtl_set_ifg(tp, speed); 6093 6094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 6095 if (speed & _2500bps) 6096 ocp_data &= ~IDLE_SPDWN_EN; 6097 else 6098 ocp_data |= IDLE_SPDWN_EN; 6099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 6100 6101 if (tp->udev->speed == USB_SPEED_HIGH) { 6102 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); 6103 ocp_data &= ~0xf; 6104 if (is_flow_control(speed)) 6105 ocp_data |= 0xf; 6106 else 6107 ocp_data |= 0x1; 6108 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); 6109 } 6110 6111 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 6112 ocp_data &= ~FC_PATCH_TASK; 6113 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6114 usleep_range(1000, 2000); 6115 ocp_data |= FC_PATCH_TASK; 6116 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6117 6118 return rtl_enable(tp); 6119 } 6120 6121 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, 6122 u32 advertising) 6123 { 6124 u16 bmcr; 6125 int ret = 0; 6126 6127 if (autoneg == AUTONEG_DISABLE) { 6128 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL) 6129 return -EINVAL; 6130 6131 switch (speed) { 6132 case SPEED_10: 6133 bmcr = BMCR_SPEED10; 6134 if (duplex == DUPLEX_FULL) { 6135 bmcr |= BMCR_FULLDPLX; 6136 tp->ups_info.speed_duplex = FORCE_10M_FULL; 6137 } else { 6138 tp->ups_info.speed_duplex = FORCE_10M_HALF; 6139 } 6140 break; 6141 case SPEED_100: 6142 bmcr = BMCR_SPEED100; 6143 if (duplex == DUPLEX_FULL) { 6144 bmcr |= BMCR_FULLDPLX; 6145 tp->ups_info.speed_duplex = FORCE_100M_FULL; 6146 } else { 6147 tp->ups_info.speed_duplex = FORCE_100M_HALF; 6148 } 6149 break; 6150 case SPEED_1000: 6151 if (tp->mii.supports_gmii) { 6152 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX; 6153 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 6154 break; 6155 } 6156 fallthrough; 6157 default: 6158 ret = -EINVAL; 6159 goto out; 6160 } 6161 6162 if (duplex == DUPLEX_FULL) 6163 tp->mii.full_duplex = 1; 6164 else 6165 tp->mii.full_duplex = 0; 6166 6167 tp->mii.force_media = 1; 6168 } else { 6169 u16 orig, new1; 6170 u32 support; 6171 6172 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 6173 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 6174 6175 if (tp->mii.supports_gmii) { 6176 support |= RTL_ADVERTISED_1000_FULL; 6177 6178 if (tp->support_2500full) 6179 support |= RTL_ADVERTISED_2500_FULL; 6180 } 6181 6182 if (!(advertising & support)) 6183 return -EINVAL; 6184 6185 orig = r8152_mdio_read(tp, MII_ADVERTISE); 6186 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 6187 ADVERTISE_100HALF | ADVERTISE_100FULL); 6188 if (advertising & RTL_ADVERTISED_10_HALF) { 6189 new1 |= ADVERTISE_10HALF; 6190 tp->ups_info.speed_duplex = NWAY_10M_HALF; 6191 } 6192 if (advertising & RTL_ADVERTISED_10_FULL) { 6193 new1 |= ADVERTISE_10FULL; 6194 tp->ups_info.speed_duplex = NWAY_10M_FULL; 6195 } 6196 6197 if (advertising & RTL_ADVERTISED_100_HALF) { 6198 new1 |= ADVERTISE_100HALF; 6199 tp->ups_info.speed_duplex = NWAY_100M_HALF; 6200 } 6201 if (advertising & RTL_ADVERTISED_100_FULL) { 6202 new1 |= ADVERTISE_100FULL; 6203 tp->ups_info.speed_duplex = NWAY_100M_FULL; 6204 } 6205 6206 if (orig != new1) { 6207 r8152_mdio_write(tp, MII_ADVERTISE, new1); 6208 tp->mii.advertising = new1; 6209 } 6210 6211 if (tp->mii.supports_gmii) { 6212 orig = r8152_mdio_read(tp, MII_CTRL1000); 6213 new1 = orig & ~(ADVERTISE_1000FULL | 6214 ADVERTISE_1000HALF); 6215 6216 if (advertising & RTL_ADVERTISED_1000_FULL) { 6217 new1 |= ADVERTISE_1000FULL; 6218 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 6219 } 6220 6221 if (orig != new1) 6222 r8152_mdio_write(tp, MII_CTRL1000, new1); 6223 } 6224 6225 if (tp->support_2500full) { 6226 orig = ocp_reg_read(tp, OCP_10GBT_CTRL); 6227 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; 6228 6229 if (advertising & RTL_ADVERTISED_2500_FULL) { 6230 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; 6231 tp->ups_info.speed_duplex = NWAY_2500M_FULL; 6232 } 6233 6234 if (orig != new1) 6235 ocp_reg_write(tp, OCP_10GBT_CTRL, new1); 6236 } 6237 6238 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 6239 6240 tp->mii.force_media = 0; 6241 } 6242 6243 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 6244 bmcr |= BMCR_RESET; 6245 6246 r8152_mdio_write(tp, MII_BMCR, bmcr); 6247 6248 if (bmcr & BMCR_RESET) { 6249 int i; 6250 6251 for (i = 0; i < 50; i++) { 6252 msleep(20); 6253 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 6254 break; 6255 } 6256 } 6257 6258 out: 6259 return ret; 6260 } 6261 6262 static void rtl8152_up(struct r8152 *tp) 6263 { 6264 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6265 return; 6266 6267 r8152_aldps_en(tp, false); 6268 r8152b_exit_oob(tp); 6269 r8152_aldps_en(tp, true); 6270 } 6271 6272 static void rtl8152_down(struct r8152 *tp) 6273 { 6274 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 6275 rtl_drop_queued_tx(tp); 6276 return; 6277 } 6278 6279 r8152_power_cut_en(tp, false); 6280 r8152_aldps_en(tp, false); 6281 r8152b_enter_oob(tp); 6282 r8152_aldps_en(tp, true); 6283 } 6284 6285 static void rtl8153_up(struct r8152 *tp) 6286 { 6287 u32 ocp_data; 6288 6289 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6290 return; 6291 6292 r8153_u1u2en(tp, false); 6293 r8153_u2p3en(tp, false); 6294 r8153_aldps_en(tp, false); 6295 r8153_first_init(tp); 6296 6297 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 6298 ocp_data |= LANWAKE_CLR_EN; 6299 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 6300 6301 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); 6302 ocp_data &= ~LANWAKE_PIN; 6303 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); 6304 6305 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); 6306 ocp_data &= ~DELAY_PHY_PWR_CHG; 6307 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); 6308 6309 r8153_aldps_en(tp, true); 6310 6311 switch (tp->version) { 6312 case RTL_VER_03: 6313 case RTL_VER_04: 6314 break; 6315 case RTL_VER_05: 6316 case RTL_VER_06: 6317 default: 6318 r8153_u2p3en(tp, true); 6319 break; 6320 } 6321 6322 r8153_u1u2en(tp, true); 6323 } 6324 6325 static void rtl8153_down(struct r8152 *tp) 6326 { 6327 u32 ocp_data; 6328 6329 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 6330 rtl_drop_queued_tx(tp); 6331 return; 6332 } 6333 6334 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 6335 ocp_data &= ~LANWAKE_CLR_EN; 6336 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 6337 6338 r8153_u1u2en(tp, false); 6339 r8153_u2p3en(tp, false); 6340 r8153_power_cut_en(tp, false); 6341 r8153_aldps_en(tp, false); 6342 r8153_enter_oob(tp); 6343 r8153_aldps_en(tp, true); 6344 } 6345 6346 static void rtl8153b_up(struct r8152 *tp) 6347 { 6348 u32 ocp_data; 6349 6350 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6351 return; 6352 6353 r8153b_u1u2en(tp, false); 6354 r8153_u2p3en(tp, false); 6355 r8153_aldps_en(tp, false); 6356 6357 r8153_first_init(tp); 6358 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 6359 6360 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6361 ocp_data &= ~PLA_MCU_SPDWN_EN; 6362 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6363 6364 r8153_aldps_en(tp, true); 6365 6366 if (tp->udev->speed >= USB_SPEED_SUPER) 6367 r8153b_u1u2en(tp, true); 6368 } 6369 6370 static void rtl8153b_down(struct r8152 *tp) 6371 { 6372 u32 ocp_data; 6373 6374 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 6375 rtl_drop_queued_tx(tp); 6376 return; 6377 } 6378 6379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6380 ocp_data |= PLA_MCU_SPDWN_EN; 6381 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6382 6383 r8153b_u1u2en(tp, false); 6384 r8153_u2p3en(tp, false); 6385 r8153b_power_cut_en(tp, false); 6386 r8153_aldps_en(tp, false); 6387 r8153_enter_oob(tp); 6388 r8153_aldps_en(tp, true); 6389 } 6390 6391 static void rtl8153c_change_mtu(struct r8152 *tp) 6392 { 6393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); 6394 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); 6395 6396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); 6397 6398 /* Adjust the tx fifo free credit full threshold, otherwise 6399 * the fifo would be too small to send a jumbo frame packet. 6400 */ 6401 if (tp->netdev->mtu < 8000) 6402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8); 6403 else 6404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8); 6405 } 6406 6407 static void rtl8153c_up(struct r8152 *tp) 6408 { 6409 u32 ocp_data; 6410 6411 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6412 return; 6413 6414 r8153b_u1u2en(tp, false); 6415 r8153_u2p3en(tp, false); 6416 r8153_aldps_en(tp, false); 6417 6418 rxdy_gated_en(tp, true); 6419 r8153_teredo_off(tp); 6420 6421 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6422 ocp_data &= ~RCR_ACPT_ALL; 6423 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6424 6425 rtl8152_nic_reset(tp); 6426 rtl_reset_bmu(tp); 6427 6428 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6429 ocp_data &= ~NOW_IS_OOB; 6430 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6431 6432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6433 ocp_data &= ~MCU_BORW_EN; 6434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6435 6436 wait_oob_link_list_ready(tp); 6437 6438 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6439 ocp_data |= RE_INIT_LL; 6440 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6441 6442 wait_oob_link_list_ready(tp); 6443 6444 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 6445 6446 rtl8153c_change_mtu(tp); 6447 6448 rtl8152_nic_reset(tp); 6449 6450 /* rx share fifo credit full threshold */ 6451 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); 6452 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); 6453 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 6454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 6455 6456 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 6457 6458 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 6459 6460 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 6461 ocp_data |= BIT(8); 6462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 6463 6464 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 6465 6466 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6467 ocp_data &= ~PLA_MCU_SPDWN_EN; 6468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6469 6470 r8153_aldps_en(tp, true); 6471 r8153b_u1u2en(tp, true); 6472 } 6473 6474 static void rtl8156_change_mtu(struct r8152 *tp) 6475 { 6476 u32 rx_max_size = mtu_to_size(tp->netdev->mtu); 6477 6478 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size); 6479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 6480 r8156_fc_parameter(tp); 6481 6482 /* TX share fifo free credit full threshold */ 6483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); 6484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 6485 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); 6486 } 6487 6488 static void rtl8156_up(struct r8152 *tp) 6489 { 6490 u32 ocp_data; 6491 6492 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6493 return; 6494 6495 r8153b_u1u2en(tp, false); 6496 r8153_u2p3en(tp, false); 6497 r8153_aldps_en(tp, false); 6498 6499 rxdy_gated_en(tp, true); 6500 r8153_teredo_off(tp); 6501 6502 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6503 ocp_data &= ~RCR_ACPT_ALL; 6504 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6505 6506 rtl8152_nic_reset(tp); 6507 rtl_reset_bmu(tp); 6508 6509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6510 ocp_data &= ~NOW_IS_OOB; 6511 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6512 6513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6514 ocp_data &= ~MCU_BORW_EN; 6515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6516 6517 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 6518 6519 rtl8156_change_mtu(tp); 6520 6521 switch (tp->version) { 6522 case RTL_TEST_01: 6523 case RTL_VER_10: 6524 case RTL_VER_11: 6525 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); 6526 ocp_data |= ACT_ODMA; 6527 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); 6528 break; 6529 default: 6530 break; 6531 } 6532 6533 /* share FIFO settings */ 6534 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); 6535 ocp_data &= ~RXFIFO_FULL_MASK; 6536 ocp_data |= 0x08; 6537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); 6538 6539 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6540 ocp_data &= ~PLA_MCU_SPDWN_EN; 6541 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6542 6543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); 6544 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); 6545 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); 6546 6547 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); 6548 6549 if (tp->saved_wolopts != __rtl_get_wol(tp)) { 6550 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); 6551 __rtl_set_wol(tp, tp->saved_wolopts); 6552 } 6553 6554 r8153_aldps_en(tp, true); 6555 r8153_u2p3en(tp, true); 6556 6557 if (tp->udev->speed >= USB_SPEED_SUPER) 6558 r8153b_u1u2en(tp, true); 6559 } 6560 6561 static void rtl8156_down(struct r8152 *tp) 6562 { 6563 u32 ocp_data; 6564 6565 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 6566 rtl_drop_queued_tx(tp); 6567 return; 6568 } 6569 6570 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6571 ocp_data |= PLA_MCU_SPDWN_EN; 6572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6573 6574 r8153b_u1u2en(tp, false); 6575 r8153_u2p3en(tp, false); 6576 r8153b_power_cut_en(tp, false); 6577 r8153_aldps_en(tp, false); 6578 6579 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6580 ocp_data &= ~NOW_IS_OOB; 6581 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6582 6583 /* RX FIFO settings for OOB */ 6584 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); 6585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16); 6586 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16); 6587 6588 rtl_disable(tp); 6589 rtl_reset_bmu(tp); 6590 6591 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); 6592 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); 6593 6594 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 6595 * type. Set it to zero. bits[7:0] are the W1C bits about 6596 * the events. Set them to all 1 to clear them. 6597 */ 6598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 6599 6600 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6601 ocp_data |= NOW_IS_OOB; 6602 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6603 6604 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6605 ocp_data |= MCU_BORW_EN; 6606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6607 6608 rtl_rx_vlan_en(tp, true); 6609 rxdy_gated_en(tp, false); 6610 6611 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6612 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 6613 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6614 6615 r8153_aldps_en(tp, true); 6616 } 6617 6618 static bool rtl8152_in_nway(struct r8152 *tp) 6619 { 6620 u16 nway_state; 6621 6622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 6623 tp->ocp_base = 0x2000; 6624 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 6625 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 6626 6627 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 6628 if (nway_state & 0xc000) 6629 return false; 6630 else 6631 return true; 6632 } 6633 6634 static bool rtl8153_in_nway(struct r8152 *tp) 6635 { 6636 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 6637 6638 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 6639 return false; 6640 else 6641 return true; 6642 } 6643 6644 static void r8156_mdio_force_mode(struct r8152 *tp) 6645 { 6646 u16 data; 6647 6648 /* Select force mode through 0xa5b4 bit 15 6649 * 0: MDIO force mode 6650 * 1: MMD force mode 6651 */ 6652 data = ocp_reg_read(tp, 0xa5b4); 6653 if (data & BIT(15)) { 6654 data &= ~BIT(15); 6655 ocp_reg_write(tp, 0xa5b4, data); 6656 } 6657 } 6658 6659 static void set_carrier(struct r8152 *tp) 6660 { 6661 struct net_device *netdev = tp->netdev; 6662 struct napi_struct *napi = &tp->napi; 6663 u16 speed; 6664 6665 speed = rtl8152_get_speed(tp); 6666 6667 if (speed & LINK_STATUS) { 6668 if (!netif_carrier_ok(netdev)) { 6669 tp->rtl_ops.enable(tp); 6670 netif_stop_queue(netdev); 6671 napi_disable(napi); 6672 netif_carrier_on(netdev); 6673 rtl_start_rx(tp); 6674 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 6675 _rtl8152_set_rx_mode(netdev); 6676 napi_enable(napi); 6677 netif_wake_queue(netdev); 6678 netif_info(tp, link, netdev, "carrier on\n"); 6679 } else if (netif_queue_stopped(netdev) && 6680 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 6681 netif_wake_queue(netdev); 6682 } 6683 } else { 6684 if (netif_carrier_ok(netdev)) { 6685 netif_carrier_off(netdev); 6686 tasklet_disable(&tp->tx_tl); 6687 napi_disable(napi); 6688 tp->rtl_ops.disable(tp); 6689 napi_enable(napi); 6690 tasklet_enable(&tp->tx_tl); 6691 netif_info(tp, link, netdev, "carrier off\n"); 6692 } 6693 } 6694 } 6695 6696 static void rtl_work_func_t(struct work_struct *work) 6697 { 6698 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 6699 6700 /* If the device is unplugged or !netif_running(), the workqueue 6701 * doesn't need to wake the device, and could return directly. 6702 */ 6703 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 6704 return; 6705 6706 if (usb_autopm_get_interface(tp->intf) < 0) 6707 return; 6708 6709 if (!test_bit(WORK_ENABLE, &tp->flags)) 6710 goto out1; 6711 6712 if (!mutex_trylock(&tp->control)) { 6713 schedule_delayed_work(&tp->schedule, 0); 6714 goto out1; 6715 } 6716 6717 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 6718 set_carrier(tp); 6719 6720 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 6721 _rtl8152_set_rx_mode(tp->netdev); 6722 6723 /* don't schedule tasket before linking */ 6724 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && 6725 netif_carrier_ok(tp->netdev)) 6726 tasklet_schedule(&tp->tx_tl); 6727 6728 if (test_and_clear_bit(RX_EPROTO, &tp->flags) && 6729 !list_empty(&tp->rx_done)) 6730 napi_schedule(&tp->napi); 6731 6732 mutex_unlock(&tp->control); 6733 6734 out1: 6735 usb_autopm_put_interface(tp->intf); 6736 } 6737 6738 static void rtl_hw_phy_work_func_t(struct work_struct *work) 6739 { 6740 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 6741 6742 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6743 return; 6744 6745 if (usb_autopm_get_interface(tp->intf) < 0) 6746 return; 6747 6748 mutex_lock(&tp->control); 6749 6750 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) { 6751 tp->rtl_fw.retry = false; 6752 tp->rtl_fw.fw = NULL; 6753 6754 /* Delay execution in case request_firmware() is not ready yet. 6755 */ 6756 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10); 6757 goto ignore_once; 6758 } 6759 6760 tp->rtl_ops.hw_phy_cfg(tp); 6761 6762 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex, 6763 tp->advertising); 6764 6765 ignore_once: 6766 mutex_unlock(&tp->control); 6767 6768 usb_autopm_put_interface(tp->intf); 6769 } 6770 6771 #ifdef CONFIG_PM_SLEEP 6772 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 6773 void *data) 6774 { 6775 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 6776 6777 switch (action) { 6778 case PM_HIBERNATION_PREPARE: 6779 case PM_SUSPEND_PREPARE: 6780 usb_autopm_get_interface(tp->intf); 6781 break; 6782 6783 case PM_POST_HIBERNATION: 6784 case PM_POST_SUSPEND: 6785 usb_autopm_put_interface(tp->intf); 6786 break; 6787 6788 case PM_POST_RESTORE: 6789 case PM_RESTORE_PREPARE: 6790 default: 6791 break; 6792 } 6793 6794 return NOTIFY_DONE; 6795 } 6796 #endif 6797 6798 static int rtl8152_open(struct net_device *netdev) 6799 { 6800 struct r8152 *tp = netdev_priv(netdev); 6801 int res = 0; 6802 6803 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) { 6804 cancel_delayed_work_sync(&tp->hw_phy_work); 6805 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work); 6806 } 6807 6808 res = alloc_all_mem(tp); 6809 if (res) 6810 goto out; 6811 6812 res = usb_autopm_get_interface(tp->intf); 6813 if (res < 0) 6814 goto out_free; 6815 6816 mutex_lock(&tp->control); 6817 6818 tp->rtl_ops.up(tp); 6819 6820 netif_carrier_off(netdev); 6821 netif_start_queue(netdev); 6822 set_bit(WORK_ENABLE, &tp->flags); 6823 6824 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 6825 if (res) { 6826 if (res == -ENODEV) 6827 netif_device_detach(tp->netdev); 6828 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 6829 res); 6830 goto out_unlock; 6831 } 6832 napi_enable(&tp->napi); 6833 tasklet_enable(&tp->tx_tl); 6834 6835 mutex_unlock(&tp->control); 6836 6837 usb_autopm_put_interface(tp->intf); 6838 #ifdef CONFIG_PM_SLEEP 6839 tp->pm_notifier.notifier_call = rtl_notifier; 6840 register_pm_notifier(&tp->pm_notifier); 6841 #endif 6842 return 0; 6843 6844 out_unlock: 6845 mutex_unlock(&tp->control); 6846 usb_autopm_put_interface(tp->intf); 6847 out_free: 6848 free_all_mem(tp); 6849 out: 6850 return res; 6851 } 6852 6853 static int rtl8152_close(struct net_device *netdev) 6854 { 6855 struct r8152 *tp = netdev_priv(netdev); 6856 int res = 0; 6857 6858 #ifdef CONFIG_PM_SLEEP 6859 unregister_pm_notifier(&tp->pm_notifier); 6860 #endif 6861 tasklet_disable(&tp->tx_tl); 6862 clear_bit(WORK_ENABLE, &tp->flags); 6863 usb_kill_urb(tp->intr_urb); 6864 cancel_delayed_work_sync(&tp->schedule); 6865 napi_disable(&tp->napi); 6866 netif_stop_queue(netdev); 6867 6868 res = usb_autopm_get_interface(tp->intf); 6869 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 6870 rtl_drop_queued_tx(tp); 6871 rtl_stop_rx(tp); 6872 } else { 6873 mutex_lock(&tp->control); 6874 6875 tp->rtl_ops.down(tp); 6876 6877 mutex_unlock(&tp->control); 6878 } 6879 6880 if (!res) 6881 usb_autopm_put_interface(tp->intf); 6882 6883 free_all_mem(tp); 6884 6885 return res; 6886 } 6887 6888 static void rtl_tally_reset(struct r8152 *tp) 6889 { 6890 u32 ocp_data; 6891 6892 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 6893 ocp_data |= TALLY_RESET; 6894 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 6895 } 6896 6897 static void r8152b_init(struct r8152 *tp) 6898 { 6899 u32 ocp_data; 6900 u16 data; 6901 6902 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6903 return; 6904 6905 data = r8152_mdio_read(tp, MII_BMCR); 6906 if (data & BMCR_PDOWN) { 6907 data &= ~BMCR_PDOWN; 6908 r8152_mdio_write(tp, MII_BMCR, data); 6909 } 6910 6911 r8152_aldps_en(tp, false); 6912 6913 if (tp->version == RTL_VER_01) { 6914 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 6915 ocp_data &= ~LED_MODE_MASK; 6916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 6917 } 6918 6919 r8152_power_cut_en(tp, false); 6920 6921 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 6922 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 6923 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 6924 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 6925 ocp_data &= ~MCU_CLK_RATIO_MASK; 6926 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 6927 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 6928 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 6929 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 6930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 6931 6932 rtl_tally_reset(tp); 6933 6934 /* enable rx aggregation */ 6935 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 6936 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 6937 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 6938 } 6939 6940 static void r8153_init(struct r8152 *tp) 6941 { 6942 u32 ocp_data; 6943 u16 data; 6944 int i; 6945 6946 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6947 return; 6948 6949 r8153_u1u2en(tp, false); 6950 6951 for (i = 0; i < 500; i++) { 6952 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 6953 AUTOLOAD_DONE) 6954 break; 6955 6956 msleep(20); 6957 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 6958 break; 6959 } 6960 6961 data = r8153_phy_status(tp, 0); 6962 6963 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 6964 tp->version == RTL_VER_05) 6965 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 6966 6967 data = r8152_mdio_read(tp, MII_BMCR); 6968 if (data & BMCR_PDOWN) { 6969 data &= ~BMCR_PDOWN; 6970 r8152_mdio_write(tp, MII_BMCR, data); 6971 } 6972 6973 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 6974 6975 r8153_u2p3en(tp, false); 6976 6977 if (tp->version == RTL_VER_04) { 6978 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 6979 ocp_data &= ~pwd_dn_scale_mask; 6980 ocp_data |= pwd_dn_scale(96); 6981 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 6982 6983 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 6984 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 6985 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 6986 } else if (tp->version == RTL_VER_05) { 6987 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 6988 ocp_data &= ~ECM_ALDPS; 6989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 6990 6991 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 6992 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 6993 ocp_data &= ~DYNAMIC_BURST; 6994 else 6995 ocp_data |= DYNAMIC_BURST; 6996 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 6997 } else if (tp->version == RTL_VER_06) { 6998 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 6999 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 7000 ocp_data &= ~DYNAMIC_BURST; 7001 else 7002 ocp_data |= DYNAMIC_BURST; 7003 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 7004 7005 r8153_queue_wake(tp, false); 7006 7007 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7008 if (rtl8152_get_speed(tp) & LINK_STATUS) 7009 ocp_data |= CUR_LINK_OK; 7010 else 7011 ocp_data &= ~CUR_LINK_OK; 7012 ocp_data |= POLL_LINK_CHG; 7013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7014 } 7015 7016 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 7017 ocp_data |= EP4_FULL_FC; 7018 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 7019 7020 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 7021 ocp_data &= ~TIMER11_EN; 7022 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 7023 7024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 7025 ocp_data &= ~LED_MODE_MASK; 7026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 7027 7028 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 7029 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 7030 ocp_data |= LPM_TIMER_500MS; 7031 else 7032 ocp_data |= LPM_TIMER_500US; 7033 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 7034 7035 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 7036 ocp_data &= ~SEN_VAL_MASK; 7037 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 7038 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 7039 7040 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 7041 7042 r8153_power_cut_en(tp, false); 7043 rtl_runtime_suspend_enable(tp, false); 7044 r8153_mac_clk_speed_down(tp, false); 7045 r8153_u1u2en(tp, true); 7046 usb_enable_lpm(tp->udev); 7047 7048 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 7049 ocp_data |= LANWAKE_CLR_EN; 7050 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 7051 7052 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); 7053 ocp_data &= ~LANWAKE_PIN; 7054 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); 7055 7056 /* rx aggregation */ 7057 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7058 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7059 if (tp->dell_tb_rx_agg_bug) 7060 ocp_data |= RX_AGG_DISABLE; 7061 7062 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7063 7064 rtl_tally_reset(tp); 7065 7066 switch (tp->udev->speed) { 7067 case USB_SPEED_SUPER: 7068 case USB_SPEED_SUPER_PLUS: 7069 tp->coalesce = COALESCE_SUPER; 7070 break; 7071 case USB_SPEED_HIGH: 7072 tp->coalesce = COALESCE_HIGH; 7073 break; 7074 default: 7075 tp->coalesce = COALESCE_SLOW; 7076 break; 7077 } 7078 } 7079 7080 static void r8153b_init(struct r8152 *tp) 7081 { 7082 u32 ocp_data; 7083 u16 data; 7084 int i; 7085 7086 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 7087 return; 7088 7089 r8153b_u1u2en(tp, false); 7090 7091 for (i = 0; i < 500; i++) { 7092 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7093 AUTOLOAD_DONE) 7094 break; 7095 7096 msleep(20); 7097 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 7098 break; 7099 } 7100 7101 data = r8153_phy_status(tp, 0); 7102 7103 data = r8152_mdio_read(tp, MII_BMCR); 7104 if (data & BMCR_PDOWN) { 7105 data &= ~BMCR_PDOWN; 7106 r8152_mdio_write(tp, MII_BMCR, data); 7107 } 7108 7109 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7110 7111 r8153_u2p3en(tp, false); 7112 7113 /* MSC timer = 0xfff * 8ms = 32760 ms */ 7114 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 7115 7116 r8153b_power_cut_en(tp, false); 7117 r8153b_ups_en(tp, false); 7118 r8153_queue_wake(tp, false); 7119 rtl_runtime_suspend_enable(tp, false); 7120 7121 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7122 if (rtl8152_get_speed(tp) & LINK_STATUS) 7123 ocp_data |= CUR_LINK_OK; 7124 else 7125 ocp_data &= ~CUR_LINK_OK; 7126 ocp_data |= POLL_LINK_CHG; 7127 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7128 7129 if (tp->udev->speed >= USB_SPEED_SUPER) 7130 r8153b_u1u2en(tp, true); 7131 7132 usb_enable_lpm(tp->udev); 7133 7134 /* MAC clock speed down */ 7135 r8153_mac_clk_speed_down(tp, true); 7136 7137 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 7138 ocp_data &= ~PLA_MCU_SPDWN_EN; 7139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 7140 7141 if (tp->version == RTL_VER_09) { 7142 /* Disable Test IO for 32QFN */ 7143 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { 7144 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7145 ocp_data |= TEST_IO_OFF; 7146 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7147 } 7148 } 7149 7150 set_bit(GREEN_ETHERNET, &tp->flags); 7151 7152 /* rx aggregation */ 7153 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7154 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7155 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7156 7157 rtl_tally_reset(tp); 7158 7159 tp->coalesce = 15000; /* 15 us */ 7160 } 7161 7162 static void r8153c_init(struct r8152 *tp) 7163 { 7164 u32 ocp_data; 7165 u16 data; 7166 int i; 7167 7168 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 7169 return; 7170 7171 r8153b_u1u2en(tp, false); 7172 7173 /* Disable spi_en */ 7174 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 7175 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 7176 ocp_data &= ~BIT(3); 7177 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 7178 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); 7179 ocp_data |= BIT(1); 7180 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); 7181 7182 for (i = 0; i < 500; i++) { 7183 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7184 AUTOLOAD_DONE) 7185 break; 7186 7187 msleep(20); 7188 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 7189 return; 7190 } 7191 7192 data = r8153_phy_status(tp, 0); 7193 7194 data = r8152_mdio_read(tp, MII_BMCR); 7195 if (data & BMCR_PDOWN) { 7196 data &= ~BMCR_PDOWN; 7197 r8152_mdio_write(tp, MII_BMCR, data); 7198 } 7199 7200 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7201 7202 r8153_u2p3en(tp, false); 7203 7204 /* MSC timer = 0xfff * 8ms = 32760 ms */ 7205 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 7206 7207 r8153b_power_cut_en(tp, false); 7208 r8153c_ups_en(tp, false); 7209 r8153_queue_wake(tp, false); 7210 rtl_runtime_suspend_enable(tp, false); 7211 7212 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7213 if (rtl8152_get_speed(tp) & LINK_STATUS) 7214 ocp_data |= CUR_LINK_OK; 7215 else 7216 ocp_data &= ~CUR_LINK_OK; 7217 7218 ocp_data |= POLL_LINK_CHG; 7219 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7220 7221 r8153b_u1u2en(tp, true); 7222 7223 usb_enable_lpm(tp->udev); 7224 7225 /* MAC clock speed down */ 7226 r8153_mac_clk_speed_down(tp, true); 7227 7228 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 7229 ocp_data &= ~BIT(7); 7230 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 7231 7232 set_bit(GREEN_ETHERNET, &tp->flags); 7233 7234 /* rx aggregation */ 7235 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7236 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7237 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7238 7239 rtl_tally_reset(tp); 7240 7241 tp->coalesce = 15000; /* 15 us */ 7242 } 7243 7244 static void r8156_hw_phy_cfg(struct r8152 *tp) 7245 { 7246 u32 ocp_data; 7247 u16 data; 7248 7249 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 7250 if (ocp_data & PCUT_STATUS) { 7251 ocp_data &= ~PCUT_STATUS; 7252 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 7253 } 7254 7255 data = r8153_phy_status(tp, 0); 7256 switch (data) { 7257 case PHY_STAT_EXT_INIT: 7258 rtl8152_apply_firmware(tp, true); 7259 7260 data = ocp_reg_read(tp, 0xa468); 7261 data &= ~(BIT(3) | BIT(1)); 7262 ocp_reg_write(tp, 0xa468, data); 7263 break; 7264 case PHY_STAT_LAN_ON: 7265 case PHY_STAT_PWRDN: 7266 default: 7267 rtl8152_apply_firmware(tp, false); 7268 break; 7269 } 7270 7271 /* disable ALDPS before updating the PHY parameters */ 7272 r8153_aldps_en(tp, false); 7273 7274 /* disable EEE before updating the PHY parameters */ 7275 rtl_eee_enable(tp, false); 7276 7277 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7278 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 7279 7280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7281 ocp_data |= PFM_PWM_SWITCH; 7282 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7283 7284 switch (tp->version) { 7285 case RTL_VER_10: 7286 data = ocp_reg_read(tp, 0xad40); 7287 data &= ~0x3ff; 7288 data |= BIT(7) | BIT(2); 7289 ocp_reg_write(tp, 0xad40, data); 7290 7291 data = ocp_reg_read(tp, 0xad4e); 7292 data |= BIT(4); 7293 ocp_reg_write(tp, 0xad4e, data); 7294 data = ocp_reg_read(tp, 0xad16); 7295 data &= ~0x3ff; 7296 data |= 0x6; 7297 ocp_reg_write(tp, 0xad16, data); 7298 data = ocp_reg_read(tp, 0xad32); 7299 data &= ~0x3f; 7300 data |= 6; 7301 ocp_reg_write(tp, 0xad32, data); 7302 data = ocp_reg_read(tp, 0xac08); 7303 data &= ~(BIT(12) | BIT(8)); 7304 ocp_reg_write(tp, 0xac08, data); 7305 data = ocp_reg_read(tp, 0xac8a); 7306 data |= BIT(12) | BIT(13) | BIT(14); 7307 data &= ~BIT(15); 7308 ocp_reg_write(tp, 0xac8a, data); 7309 data = ocp_reg_read(tp, 0xad18); 7310 data |= BIT(10); 7311 ocp_reg_write(tp, 0xad18, data); 7312 data = ocp_reg_read(tp, 0xad1a); 7313 data |= 0x3ff; 7314 ocp_reg_write(tp, 0xad1a, data); 7315 data = ocp_reg_read(tp, 0xad1c); 7316 data |= 0x3ff; 7317 ocp_reg_write(tp, 0xad1c, data); 7318 7319 data = sram_read(tp, 0x80ea); 7320 data &= ~0xff00; 7321 data |= 0xc400; 7322 sram_write(tp, 0x80ea, data); 7323 data = sram_read(tp, 0x80eb); 7324 data &= ~0x0700; 7325 data |= 0x0300; 7326 sram_write(tp, 0x80eb, data); 7327 data = sram_read(tp, 0x80f8); 7328 data &= ~0xff00; 7329 data |= 0x1c00; 7330 sram_write(tp, 0x80f8, data); 7331 data = sram_read(tp, 0x80f1); 7332 data &= ~0xff00; 7333 data |= 0x3000; 7334 sram_write(tp, 0x80f1, data); 7335 7336 data = sram_read(tp, 0x80fe); 7337 data &= ~0xff00; 7338 data |= 0xa500; 7339 sram_write(tp, 0x80fe, data); 7340 data = sram_read(tp, 0x8102); 7341 data &= ~0xff00; 7342 data |= 0x5000; 7343 sram_write(tp, 0x8102, data); 7344 data = sram_read(tp, 0x8015); 7345 data &= ~0xff00; 7346 data |= 0x3300; 7347 sram_write(tp, 0x8015, data); 7348 data = sram_read(tp, 0x8100); 7349 data &= ~0xff00; 7350 data |= 0x7000; 7351 sram_write(tp, 0x8100, data); 7352 data = sram_read(tp, 0x8014); 7353 data &= ~0xff00; 7354 data |= 0xf000; 7355 sram_write(tp, 0x8014, data); 7356 data = sram_read(tp, 0x8016); 7357 data &= ~0xff00; 7358 data |= 0x6500; 7359 sram_write(tp, 0x8016, data); 7360 data = sram_read(tp, 0x80dc); 7361 data &= ~0xff00; 7362 data |= 0xed00; 7363 sram_write(tp, 0x80dc, data); 7364 data = sram_read(tp, 0x80df); 7365 data |= BIT(8); 7366 sram_write(tp, 0x80df, data); 7367 data = sram_read(tp, 0x80e1); 7368 data &= ~BIT(8); 7369 sram_write(tp, 0x80e1, data); 7370 7371 data = ocp_reg_read(tp, 0xbf06); 7372 data &= ~0x003f; 7373 data |= 0x0038; 7374 ocp_reg_write(tp, 0xbf06, data); 7375 7376 sram_write(tp, 0x819f, 0xddb6); 7377 7378 ocp_reg_write(tp, 0xbc34, 0x5555); 7379 data = ocp_reg_read(tp, 0xbf0a); 7380 data &= ~0x0e00; 7381 data |= 0x0a00; 7382 ocp_reg_write(tp, 0xbf0a, data); 7383 7384 data = ocp_reg_read(tp, 0xbd2c); 7385 data &= ~BIT(13); 7386 ocp_reg_write(tp, 0xbd2c, data); 7387 break; 7388 case RTL_VER_11: 7389 data = ocp_reg_read(tp, 0xad16); 7390 data |= 0x3ff; 7391 ocp_reg_write(tp, 0xad16, data); 7392 data = ocp_reg_read(tp, 0xad32); 7393 data &= ~0x3f; 7394 data |= 6; 7395 ocp_reg_write(tp, 0xad32, data); 7396 data = ocp_reg_read(tp, 0xac08); 7397 data &= ~(BIT(12) | BIT(8)); 7398 ocp_reg_write(tp, 0xac08, data); 7399 data = ocp_reg_read(tp, 0xacc0); 7400 data &= ~0x3; 7401 data |= BIT(1); 7402 ocp_reg_write(tp, 0xacc0, data); 7403 data = ocp_reg_read(tp, 0xad40); 7404 data &= ~0xe7; 7405 data |= BIT(6) | BIT(2); 7406 ocp_reg_write(tp, 0xad40, data); 7407 data = ocp_reg_read(tp, 0xac14); 7408 data &= ~BIT(7); 7409 ocp_reg_write(tp, 0xac14, data); 7410 data = ocp_reg_read(tp, 0xac80); 7411 data &= ~(BIT(8) | BIT(9)); 7412 ocp_reg_write(tp, 0xac80, data); 7413 data = ocp_reg_read(tp, 0xac5e); 7414 data &= ~0x7; 7415 data |= BIT(1); 7416 ocp_reg_write(tp, 0xac5e, data); 7417 ocp_reg_write(tp, 0xad4c, 0x00a8); 7418 ocp_reg_write(tp, 0xac5c, 0x01ff); 7419 data = ocp_reg_read(tp, 0xac8a); 7420 data &= ~0xf0; 7421 data |= BIT(4) | BIT(5); 7422 ocp_reg_write(tp, 0xac8a, data); 7423 ocp_reg_write(tp, 0xb87c, 0x8157); 7424 data = ocp_reg_read(tp, 0xb87e); 7425 data &= ~0xff00; 7426 data |= 0x0500; 7427 ocp_reg_write(tp, 0xb87e, data); 7428 ocp_reg_write(tp, 0xb87c, 0x8159); 7429 data = ocp_reg_read(tp, 0xb87e); 7430 data &= ~0xff00; 7431 data |= 0x0700; 7432 ocp_reg_write(tp, 0xb87e, data); 7433 7434 /* AAGC */ 7435 ocp_reg_write(tp, 0xb87c, 0x80a2); 7436 ocp_reg_write(tp, 0xb87e, 0x0153); 7437 ocp_reg_write(tp, 0xb87c, 0x809c); 7438 ocp_reg_write(tp, 0xb87e, 0x0153); 7439 7440 /* EEE parameter */ 7441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); 7442 7443 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); 7444 ocp_data |= EN_XG_LIP | EN_G_LIP; 7445 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); 7446 7447 sram_write(tp, 0x8257, 0x020f); /* XG PLL */ 7448 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ 7449 7450 if (rtl_phy_patch_request(tp, true, true)) 7451 return; 7452 7453 /* Advance EEE */ 7454 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 7455 ocp_data |= EEE_SPDWN_EN; 7456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 7457 7458 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 7459 data &= ~(EN_EEE_100 | EN_EEE_1000); 7460 data |= EN_10M_CLKDIV; 7461 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 7462 tp->ups_info._10m_ckdiv = true; 7463 tp->ups_info.eee_plloff_100 = false; 7464 tp->ups_info.eee_plloff_giga = false; 7465 7466 data = ocp_reg_read(tp, OCP_POWER_CFG); 7467 data &= ~EEE_CLKDIV_EN; 7468 ocp_reg_write(tp, OCP_POWER_CFG, data); 7469 tp->ups_info.eee_ckdiv = false; 7470 7471 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 7472 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5)); 7473 tp->ups_info._250m_ckdiv = false; 7474 7475 rtl_phy_patch_request(tp, false, true); 7476 7477 /* enable ADC Ibias Cal */ 7478 data = ocp_reg_read(tp, 0xd068); 7479 data |= BIT(13); 7480 ocp_reg_write(tp, 0xd068, data); 7481 7482 /* enable Thermal Sensor */ 7483 data = sram_read(tp, 0x81a2); 7484 data &= ~BIT(8); 7485 sram_write(tp, 0x81a2, data); 7486 data = ocp_reg_read(tp, 0xb54c); 7487 data &= ~0xff00; 7488 data |= 0xdb00; 7489 ocp_reg_write(tp, 0xb54c, data); 7490 7491 /* Nway 2.5G Lite */ 7492 data = ocp_reg_read(tp, 0xa454); 7493 data &= ~BIT(0); 7494 ocp_reg_write(tp, 0xa454, data); 7495 7496 /* CS DSP solution */ 7497 data = ocp_reg_read(tp, OCP_10GBT_CTRL); 7498 data |= RTL_ADV2_5G_F_R; 7499 ocp_reg_write(tp, OCP_10GBT_CTRL, data); 7500 data = ocp_reg_read(tp, 0xad4e); 7501 data &= ~BIT(4); 7502 ocp_reg_write(tp, 0xad4e, data); 7503 data = ocp_reg_read(tp, 0xa86a); 7504 data &= ~BIT(0); 7505 ocp_reg_write(tp, 0xa86a, data); 7506 7507 /* MDI SWAP */ 7508 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && 7509 (ocp_reg_read(tp, 0xd068) & BIT(1))) { 7510 u16 swap_a, swap_b; 7511 7512 data = ocp_reg_read(tp, 0xd068); 7513 data &= ~0x1f; 7514 data |= 0x1; /* p0 */ 7515 ocp_reg_write(tp, 0xd068, data); 7516 swap_a = ocp_reg_read(tp, 0xd06a); 7517 data &= ~0x18; 7518 data |= 0x18; /* p3 */ 7519 ocp_reg_write(tp, 0xd068, data); 7520 swap_b = ocp_reg_read(tp, 0xd06a); 7521 data &= ~0x18; /* p0 */ 7522 ocp_reg_write(tp, 0xd068, data); 7523 ocp_reg_write(tp, 0xd06a, 7524 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); 7525 data |= 0x18; /* p3 */ 7526 ocp_reg_write(tp, 0xd068, data); 7527 ocp_reg_write(tp, 0xd06a, 7528 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); 7529 data &= ~0x18; 7530 data |= 0x08; /* p1 */ 7531 ocp_reg_write(tp, 0xd068, data); 7532 swap_a = ocp_reg_read(tp, 0xd06a); 7533 data &= ~0x18; 7534 data |= 0x10; /* p2 */ 7535 ocp_reg_write(tp, 0xd068, data); 7536 swap_b = ocp_reg_read(tp, 0xd06a); 7537 data &= ~0x18; 7538 data |= 0x08; /* p1 */ 7539 ocp_reg_write(tp, 0xd068, data); 7540 ocp_reg_write(tp, 0xd06a, 7541 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); 7542 data &= ~0x18; 7543 data |= 0x10; /* p2 */ 7544 ocp_reg_write(tp, 0xd068, data); 7545 ocp_reg_write(tp, 0xd06a, 7546 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); 7547 swap_a = ocp_reg_read(tp, 0xbd5a); 7548 swap_b = ocp_reg_read(tp, 0xbd5c); 7549 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | 7550 ((swap_b & 0x1f) << 8) | 7551 ((swap_b >> 8) & 0x1f)); 7552 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | 7553 ((swap_a & 0x1f) << 8) | 7554 ((swap_a >> 8) & 0x1f)); 7555 swap_a = ocp_reg_read(tp, 0xbc18); 7556 swap_b = ocp_reg_read(tp, 0xbc1a); 7557 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | 7558 ((swap_b & 0x1f) << 8) | 7559 ((swap_b >> 8) & 0x1f)); 7560 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | 7561 ((swap_a & 0x1f) << 8) | 7562 ((swap_a >> 8) & 0x1f)); 7563 } 7564 7565 /* Notify the MAC when the speed is changed to force mode. */ 7566 data = ocp_reg_read(tp, OCP_INTR_EN); 7567 data |= INTR_SPEED_FORCE; 7568 ocp_reg_write(tp, OCP_INTR_EN, data); 7569 break; 7570 default: 7571 break; 7572 } 7573 7574 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 7575 7576 data = ocp_reg_read(tp, 0xa428); 7577 data &= ~BIT(9); 7578 ocp_reg_write(tp, 0xa428, data); 7579 data = ocp_reg_read(tp, 0xa5ea); 7580 data &= ~BIT(0); 7581 ocp_reg_write(tp, 0xa5ea, data); 7582 tp->ups_info.lite_mode = 0; 7583 7584 if (tp->eee_en) 7585 rtl_eee_enable(tp, true); 7586 7587 r8153_aldps_en(tp, true); 7588 r8152b_enable_fc(tp); 7589 r8153_u2p3en(tp, true); 7590 7591 set_bit(PHY_RESET, &tp->flags); 7592 } 7593 7594 static void r8156b_hw_phy_cfg(struct r8152 *tp) 7595 { 7596 u32 ocp_data; 7597 u16 data; 7598 7599 switch (tp->version) { 7600 case RTL_VER_12: 7601 ocp_reg_write(tp, 0xbf86, 0x9000); 7602 data = ocp_reg_read(tp, 0xc402); 7603 data |= BIT(10); 7604 ocp_reg_write(tp, 0xc402, data); 7605 data &= ~BIT(10); 7606 ocp_reg_write(tp, 0xc402, data); 7607 ocp_reg_write(tp, 0xbd86, 0x1010); 7608 ocp_reg_write(tp, 0xbd88, 0x1010); 7609 data = ocp_reg_read(tp, 0xbd4e); 7610 data &= ~(BIT(10) | BIT(11)); 7611 data |= BIT(11); 7612 ocp_reg_write(tp, 0xbd4e, data); 7613 data = ocp_reg_read(tp, 0xbf46); 7614 data &= ~0xf00; 7615 data |= 0x700; 7616 ocp_reg_write(tp, 0xbf46, data); 7617 break; 7618 case RTL_VER_13: 7619 case RTL_VER_15: 7620 r8156b_wait_loading_flash(tp); 7621 break; 7622 default: 7623 break; 7624 } 7625 7626 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 7627 if (ocp_data & PCUT_STATUS) { 7628 ocp_data &= ~PCUT_STATUS; 7629 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 7630 } 7631 7632 data = r8153_phy_status(tp, 0); 7633 switch (data) { 7634 case PHY_STAT_EXT_INIT: 7635 rtl8152_apply_firmware(tp, true); 7636 7637 data = ocp_reg_read(tp, 0xa466); 7638 data &= ~BIT(0); 7639 ocp_reg_write(tp, 0xa466, data); 7640 7641 data = ocp_reg_read(tp, 0xa468); 7642 data &= ~(BIT(3) | BIT(1)); 7643 ocp_reg_write(tp, 0xa468, data); 7644 break; 7645 case PHY_STAT_LAN_ON: 7646 case PHY_STAT_PWRDN: 7647 default: 7648 rtl8152_apply_firmware(tp, false); 7649 break; 7650 } 7651 7652 data = r8152_mdio_read(tp, MII_BMCR); 7653 if (data & BMCR_PDOWN) { 7654 data &= ~BMCR_PDOWN; 7655 r8152_mdio_write(tp, MII_BMCR, data); 7656 } 7657 7658 /* disable ALDPS before updating the PHY parameters */ 7659 r8153_aldps_en(tp, false); 7660 7661 /* disable EEE before updating the PHY parameters */ 7662 rtl_eee_enable(tp, false); 7663 7664 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7665 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 7666 7667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7668 ocp_data |= PFM_PWM_SWITCH; 7669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7670 7671 switch (tp->version) { 7672 case RTL_VER_12: 7673 data = ocp_reg_read(tp, 0xbc08); 7674 data |= BIT(3) | BIT(2); 7675 ocp_reg_write(tp, 0xbc08, data); 7676 7677 data = sram_read(tp, 0x8fff); 7678 data &= ~0xff00; 7679 data |= 0x0400; 7680 sram_write(tp, 0x8fff, data); 7681 7682 data = ocp_reg_read(tp, 0xacda); 7683 data |= 0xff00; 7684 ocp_reg_write(tp, 0xacda, data); 7685 data = ocp_reg_read(tp, 0xacde); 7686 data |= 0xf000; 7687 ocp_reg_write(tp, 0xacde, data); 7688 ocp_reg_write(tp, 0xac8c, 0x0ffc); 7689 ocp_reg_write(tp, 0xac46, 0xb7b4); 7690 ocp_reg_write(tp, 0xac50, 0x0fbc); 7691 ocp_reg_write(tp, 0xac3c, 0x9240); 7692 ocp_reg_write(tp, 0xac4e, 0x0db4); 7693 ocp_reg_write(tp, 0xacc6, 0x0707); 7694 ocp_reg_write(tp, 0xacc8, 0xa0d3); 7695 ocp_reg_write(tp, 0xad08, 0x0007); 7696 7697 ocp_reg_write(tp, 0xb87c, 0x8560); 7698 ocp_reg_write(tp, 0xb87e, 0x19cc); 7699 ocp_reg_write(tp, 0xb87c, 0x8562); 7700 ocp_reg_write(tp, 0xb87e, 0x19cc); 7701 ocp_reg_write(tp, 0xb87c, 0x8564); 7702 ocp_reg_write(tp, 0xb87e, 0x19cc); 7703 ocp_reg_write(tp, 0xb87c, 0x8566); 7704 ocp_reg_write(tp, 0xb87e, 0x147d); 7705 ocp_reg_write(tp, 0xb87c, 0x8568); 7706 ocp_reg_write(tp, 0xb87e, 0x147d); 7707 ocp_reg_write(tp, 0xb87c, 0x856a); 7708 ocp_reg_write(tp, 0xb87e, 0x147d); 7709 ocp_reg_write(tp, 0xb87c, 0x8ffe); 7710 ocp_reg_write(tp, 0xb87e, 0x0907); 7711 ocp_reg_write(tp, 0xb87c, 0x80d6); 7712 ocp_reg_write(tp, 0xb87e, 0x2801); 7713 ocp_reg_write(tp, 0xb87c, 0x80f2); 7714 ocp_reg_write(tp, 0xb87e, 0x2801); 7715 ocp_reg_write(tp, 0xb87c, 0x80f4); 7716 ocp_reg_write(tp, 0xb87e, 0x6077); 7717 ocp_reg_write(tp, 0xb506, 0x01e7); 7718 7719 ocp_reg_write(tp, 0xb87c, 0x8013); 7720 ocp_reg_write(tp, 0xb87e, 0x0700); 7721 ocp_reg_write(tp, 0xb87c, 0x8fb9); 7722 ocp_reg_write(tp, 0xb87e, 0x2801); 7723 ocp_reg_write(tp, 0xb87c, 0x8fba); 7724 ocp_reg_write(tp, 0xb87e, 0x0100); 7725 ocp_reg_write(tp, 0xb87c, 0x8fbc); 7726 ocp_reg_write(tp, 0xb87e, 0x1900); 7727 ocp_reg_write(tp, 0xb87c, 0x8fbe); 7728 ocp_reg_write(tp, 0xb87e, 0xe100); 7729 ocp_reg_write(tp, 0xb87c, 0x8fc0); 7730 ocp_reg_write(tp, 0xb87e, 0x0800); 7731 ocp_reg_write(tp, 0xb87c, 0x8fc2); 7732 ocp_reg_write(tp, 0xb87e, 0xe500); 7733 ocp_reg_write(tp, 0xb87c, 0x8fc4); 7734 ocp_reg_write(tp, 0xb87e, 0x0f00); 7735 ocp_reg_write(tp, 0xb87c, 0x8fc6); 7736 ocp_reg_write(tp, 0xb87e, 0xf100); 7737 ocp_reg_write(tp, 0xb87c, 0x8fc8); 7738 ocp_reg_write(tp, 0xb87e, 0x0400); 7739 ocp_reg_write(tp, 0xb87c, 0x8fca); 7740 ocp_reg_write(tp, 0xb87e, 0xf300); 7741 ocp_reg_write(tp, 0xb87c, 0x8fcc); 7742 ocp_reg_write(tp, 0xb87e, 0xfd00); 7743 ocp_reg_write(tp, 0xb87c, 0x8fce); 7744 ocp_reg_write(tp, 0xb87e, 0xff00); 7745 ocp_reg_write(tp, 0xb87c, 0x8fd0); 7746 ocp_reg_write(tp, 0xb87e, 0xfb00); 7747 ocp_reg_write(tp, 0xb87c, 0x8fd2); 7748 ocp_reg_write(tp, 0xb87e, 0x0100); 7749 ocp_reg_write(tp, 0xb87c, 0x8fd4); 7750 ocp_reg_write(tp, 0xb87e, 0xf400); 7751 ocp_reg_write(tp, 0xb87c, 0x8fd6); 7752 ocp_reg_write(tp, 0xb87e, 0xff00); 7753 ocp_reg_write(tp, 0xb87c, 0x8fd8); 7754 ocp_reg_write(tp, 0xb87e, 0xf600); 7755 7756 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); 7757 ocp_data |= EN_XG_LIP | EN_G_LIP; 7758 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); 7759 ocp_reg_write(tp, 0xb87c, 0x813d); 7760 ocp_reg_write(tp, 0xb87e, 0x390e); 7761 ocp_reg_write(tp, 0xb87c, 0x814f); 7762 ocp_reg_write(tp, 0xb87e, 0x790e); 7763 ocp_reg_write(tp, 0xb87c, 0x80b0); 7764 ocp_reg_write(tp, 0xb87e, 0x0f31); 7765 data = ocp_reg_read(tp, 0xbf4c); 7766 data |= BIT(1); 7767 ocp_reg_write(tp, 0xbf4c, data); 7768 data = ocp_reg_read(tp, 0xbcca); 7769 data |= BIT(9) | BIT(8); 7770 ocp_reg_write(tp, 0xbcca, data); 7771 ocp_reg_write(tp, 0xb87c, 0x8141); 7772 ocp_reg_write(tp, 0xb87e, 0x320e); 7773 ocp_reg_write(tp, 0xb87c, 0x8153); 7774 ocp_reg_write(tp, 0xb87e, 0x720e); 7775 ocp_reg_write(tp, 0xb87c, 0x8529); 7776 ocp_reg_write(tp, 0xb87e, 0x050e); 7777 data = ocp_reg_read(tp, OCP_EEE_CFG); 7778 data &= ~CTAP_SHORT_EN; 7779 ocp_reg_write(tp, OCP_EEE_CFG, data); 7780 7781 sram_write(tp, 0x816c, 0xc4a0); 7782 sram_write(tp, 0x8170, 0xc4a0); 7783 sram_write(tp, 0x8174, 0x04a0); 7784 sram_write(tp, 0x8178, 0x04a0); 7785 sram_write(tp, 0x817c, 0x0719); 7786 sram_write(tp, 0x8ff4, 0x0400); 7787 sram_write(tp, 0x8ff1, 0x0404); 7788 7789 ocp_reg_write(tp, 0xbf4a, 0x001b); 7790 ocp_reg_write(tp, 0xb87c, 0x8033); 7791 ocp_reg_write(tp, 0xb87e, 0x7c13); 7792 ocp_reg_write(tp, 0xb87c, 0x8037); 7793 ocp_reg_write(tp, 0xb87e, 0x7c13); 7794 ocp_reg_write(tp, 0xb87c, 0x803b); 7795 ocp_reg_write(tp, 0xb87e, 0xfc32); 7796 ocp_reg_write(tp, 0xb87c, 0x803f); 7797 ocp_reg_write(tp, 0xb87e, 0x7c13); 7798 ocp_reg_write(tp, 0xb87c, 0x8043); 7799 ocp_reg_write(tp, 0xb87e, 0x7c13); 7800 ocp_reg_write(tp, 0xb87c, 0x8047); 7801 ocp_reg_write(tp, 0xb87e, 0x7c13); 7802 7803 ocp_reg_write(tp, 0xb87c, 0x8145); 7804 ocp_reg_write(tp, 0xb87e, 0x370e); 7805 ocp_reg_write(tp, 0xb87c, 0x8157); 7806 ocp_reg_write(tp, 0xb87e, 0x770e); 7807 ocp_reg_write(tp, 0xb87c, 0x8169); 7808 ocp_reg_write(tp, 0xb87e, 0x0d0a); 7809 ocp_reg_write(tp, 0xb87c, 0x817b); 7810 ocp_reg_write(tp, 0xb87e, 0x1d0a); 7811 7812 data = sram_read(tp, 0x8217); 7813 data &= ~0xff00; 7814 data |= 0x5000; 7815 sram_write(tp, 0x8217, data); 7816 data = sram_read(tp, 0x821a); 7817 data &= ~0xff00; 7818 data |= 0x5000; 7819 sram_write(tp, 0x821a, data); 7820 sram_write(tp, 0x80da, 0x0403); 7821 data = sram_read(tp, 0x80dc); 7822 data &= ~0xff00; 7823 data |= 0x1000; 7824 sram_write(tp, 0x80dc, data); 7825 sram_write(tp, 0x80b3, 0x0384); 7826 sram_write(tp, 0x80b7, 0x2007); 7827 data = sram_read(tp, 0x80ba); 7828 data &= ~0xff00; 7829 data |= 0x6c00; 7830 sram_write(tp, 0x80ba, data); 7831 sram_write(tp, 0x80b5, 0xf009); 7832 data = sram_read(tp, 0x80bd); 7833 data &= ~0xff00; 7834 data |= 0x9f00; 7835 sram_write(tp, 0x80bd, data); 7836 sram_write(tp, 0x80c7, 0xf083); 7837 sram_write(tp, 0x80dd, 0x03f0); 7838 data = sram_read(tp, 0x80df); 7839 data &= ~0xff00; 7840 data |= 0x1000; 7841 sram_write(tp, 0x80df, data); 7842 sram_write(tp, 0x80cb, 0x2007); 7843 data = sram_read(tp, 0x80ce); 7844 data &= ~0xff00; 7845 data |= 0x6c00; 7846 sram_write(tp, 0x80ce, data); 7847 sram_write(tp, 0x80c9, 0x8009); 7848 data = sram_read(tp, 0x80d1); 7849 data &= ~0xff00; 7850 data |= 0x8000; 7851 sram_write(tp, 0x80d1, data); 7852 sram_write(tp, 0x80a3, 0x200a); 7853 sram_write(tp, 0x80a5, 0xf0ad); 7854 sram_write(tp, 0x809f, 0x6073); 7855 sram_write(tp, 0x80a1, 0x000b); 7856 data = sram_read(tp, 0x80a9); 7857 data &= ~0xff00; 7858 data |= 0xc000; 7859 sram_write(tp, 0x80a9, data); 7860 7861 if (rtl_phy_patch_request(tp, true, true)) 7862 return; 7863 7864 data = ocp_reg_read(tp, 0xb896); 7865 data &= ~BIT(0); 7866 ocp_reg_write(tp, 0xb896, data); 7867 data = ocp_reg_read(tp, 0xb892); 7868 data &= ~0xff00; 7869 ocp_reg_write(tp, 0xb892, data); 7870 ocp_reg_write(tp, 0xb88e, 0xc23e); 7871 ocp_reg_write(tp, 0xb890, 0x0000); 7872 ocp_reg_write(tp, 0xb88e, 0xc240); 7873 ocp_reg_write(tp, 0xb890, 0x0103); 7874 ocp_reg_write(tp, 0xb88e, 0xc242); 7875 ocp_reg_write(tp, 0xb890, 0x0507); 7876 ocp_reg_write(tp, 0xb88e, 0xc244); 7877 ocp_reg_write(tp, 0xb890, 0x090b); 7878 ocp_reg_write(tp, 0xb88e, 0xc246); 7879 ocp_reg_write(tp, 0xb890, 0x0c0e); 7880 ocp_reg_write(tp, 0xb88e, 0xc248); 7881 ocp_reg_write(tp, 0xb890, 0x1012); 7882 ocp_reg_write(tp, 0xb88e, 0xc24a); 7883 ocp_reg_write(tp, 0xb890, 0x1416); 7884 data = ocp_reg_read(tp, 0xb896); 7885 data |= BIT(0); 7886 ocp_reg_write(tp, 0xb896, data); 7887 7888 rtl_phy_patch_request(tp, false, true); 7889 7890 data = ocp_reg_read(tp, 0xa86a); 7891 data |= BIT(0); 7892 ocp_reg_write(tp, 0xa86a, data); 7893 data = ocp_reg_read(tp, 0xa6f0); 7894 data |= BIT(0); 7895 ocp_reg_write(tp, 0xa6f0, data); 7896 7897 ocp_reg_write(tp, 0xbfa0, 0xd70d); 7898 ocp_reg_write(tp, 0xbfa2, 0x4100); 7899 ocp_reg_write(tp, 0xbfa4, 0xe868); 7900 ocp_reg_write(tp, 0xbfa6, 0xdc59); 7901 ocp_reg_write(tp, 0xb54c, 0x3c18); 7902 data = ocp_reg_read(tp, 0xbfa4); 7903 data &= ~BIT(5); 7904 ocp_reg_write(tp, 0xbfa4, data); 7905 data = sram_read(tp, 0x817d); 7906 data |= BIT(12); 7907 sram_write(tp, 0x817d, data); 7908 break; 7909 case RTL_VER_13: 7910 /* 2.5G INRX */ 7911 data = ocp_reg_read(tp, 0xac46); 7912 data &= ~0x00f0; 7913 data |= 0x0090; 7914 ocp_reg_write(tp, 0xac46, data); 7915 data = ocp_reg_read(tp, 0xad30); 7916 data &= ~0x0003; 7917 data |= 0x0001; 7918 ocp_reg_write(tp, 0xad30, data); 7919 fallthrough; 7920 case RTL_VER_15: 7921 /* EEE parameter */ 7922 ocp_reg_write(tp, 0xb87c, 0x80f5); 7923 ocp_reg_write(tp, 0xb87e, 0x760e); 7924 ocp_reg_write(tp, 0xb87c, 0x8107); 7925 ocp_reg_write(tp, 0xb87e, 0x360e); 7926 ocp_reg_write(tp, 0xb87c, 0x8551); 7927 data = ocp_reg_read(tp, 0xb87e); 7928 data &= ~0xff00; 7929 data |= 0x0800; 7930 ocp_reg_write(tp, 0xb87e, data); 7931 7932 /* ADC_PGA parameter */ 7933 data = ocp_reg_read(tp, 0xbf00); 7934 data &= ~0xe000; 7935 data |= 0xa000; 7936 ocp_reg_write(tp, 0xbf00, data); 7937 data = ocp_reg_read(tp, 0xbf46); 7938 data &= ~0x0f00; 7939 data |= 0x0300; 7940 ocp_reg_write(tp, 0xbf46, data); 7941 7942 /* Green Table-PGA, 1G full viterbi */ 7943 sram_write(tp, 0x8044, 0x2417); 7944 sram_write(tp, 0x804a, 0x2417); 7945 sram_write(tp, 0x8050, 0x2417); 7946 sram_write(tp, 0x8056, 0x2417); 7947 sram_write(tp, 0x805c, 0x2417); 7948 sram_write(tp, 0x8062, 0x2417); 7949 sram_write(tp, 0x8068, 0x2417); 7950 sram_write(tp, 0x806e, 0x2417); 7951 sram_write(tp, 0x8074, 0x2417); 7952 sram_write(tp, 0x807a, 0x2417); 7953 7954 /* XG PLL */ 7955 data = ocp_reg_read(tp, 0xbf84); 7956 data &= ~0xe000; 7957 data |= 0xa000; 7958 ocp_reg_write(tp, 0xbf84, data); 7959 break; 7960 default: 7961 break; 7962 } 7963 7964 /* Notify the MAC when the speed is changed to force mode. */ 7965 data = ocp_reg_read(tp, OCP_INTR_EN); 7966 data |= INTR_SPEED_FORCE; 7967 ocp_reg_write(tp, OCP_INTR_EN, data); 7968 7969 if (rtl_phy_patch_request(tp, true, true)) 7970 return; 7971 7972 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 7973 ocp_data |= EEE_SPDWN_EN; 7974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 7975 7976 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 7977 data &= ~(EN_EEE_100 | EN_EEE_1000); 7978 data |= EN_10M_CLKDIV; 7979 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 7980 tp->ups_info._10m_ckdiv = true; 7981 tp->ups_info.eee_plloff_100 = false; 7982 tp->ups_info.eee_plloff_giga = false; 7983 7984 data = ocp_reg_read(tp, OCP_POWER_CFG); 7985 data &= ~EEE_CLKDIV_EN; 7986 ocp_reg_write(tp, OCP_POWER_CFG, data); 7987 tp->ups_info.eee_ckdiv = false; 7988 7989 rtl_phy_patch_request(tp, false, true); 7990 7991 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 7992 7993 data = ocp_reg_read(tp, 0xa428); 7994 data &= ~BIT(9); 7995 ocp_reg_write(tp, 0xa428, data); 7996 data = ocp_reg_read(tp, 0xa5ea); 7997 data &= ~BIT(0); 7998 ocp_reg_write(tp, 0xa5ea, data); 7999 tp->ups_info.lite_mode = 0; 8000 8001 if (tp->eee_en) 8002 rtl_eee_enable(tp, true); 8003 8004 r8153_aldps_en(tp, true); 8005 r8152b_enable_fc(tp); 8006 r8153_u2p3en(tp, true); 8007 8008 set_bit(PHY_RESET, &tp->flags); 8009 } 8010 8011 static void r8156_init(struct r8152 *tp) 8012 { 8013 u32 ocp_data; 8014 u16 data; 8015 int i; 8016 8017 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 8018 return; 8019 8020 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); 8021 ocp_data &= ~EN_ALL_SPEED; 8022 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); 8023 8024 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 8025 8026 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); 8027 ocp_data |= BYPASS_MAC_RESET; 8028 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); 8029 8030 r8153b_u1u2en(tp, false); 8031 8032 for (i = 0; i < 500; i++) { 8033 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 8034 AUTOLOAD_DONE) 8035 break; 8036 8037 msleep(20); 8038 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 8039 return; 8040 } 8041 8042 data = r8153_phy_status(tp, 0); 8043 if (data == PHY_STAT_EXT_INIT) { 8044 data = ocp_reg_read(tp, 0xa468); 8045 data &= ~(BIT(3) | BIT(1)); 8046 ocp_reg_write(tp, 0xa468, data); 8047 } 8048 8049 data = r8152_mdio_read(tp, MII_BMCR); 8050 if (data & BMCR_PDOWN) { 8051 data &= ~BMCR_PDOWN; 8052 r8152_mdio_write(tp, MII_BMCR, data); 8053 } 8054 8055 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 8056 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 8057 8058 r8153_u2p3en(tp, false); 8059 8060 /* MSC timer = 0xfff * 8ms = 32760 ms */ 8061 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 8062 8063 /* U1/U2/L1 idle timer. 500 us */ 8064 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 8065 8066 r8153b_power_cut_en(tp, false); 8067 r8156_ups_en(tp, false); 8068 r8153_queue_wake(tp, false); 8069 rtl_runtime_suspend_enable(tp, false); 8070 8071 if (tp->udev->speed >= USB_SPEED_SUPER) 8072 r8153b_u1u2en(tp, true); 8073 8074 usb_enable_lpm(tp->udev); 8075 8076 r8156_mac_clk_spd(tp, true); 8077 8078 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 8079 ocp_data &= ~PLA_MCU_SPDWN_EN; 8080 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 8081 8082 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 8083 if (rtl8152_get_speed(tp) & LINK_STATUS) 8084 ocp_data |= CUR_LINK_OK; 8085 else 8086 ocp_data &= ~CUR_LINK_OK; 8087 ocp_data |= POLL_LINK_CHG; 8088 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 8089 8090 set_bit(GREEN_ETHERNET, &tp->flags); 8091 8092 /* rx aggregation */ 8093 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 8094 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 8095 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 8096 8097 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); 8098 ocp_data |= ACT_ODMA; 8099 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); 8100 8101 r8156_mdio_force_mode(tp); 8102 rtl_tally_reset(tp); 8103 8104 tp->coalesce = 15000; /* 15 us */ 8105 } 8106 8107 static void r8156b_init(struct r8152 *tp) 8108 { 8109 u32 ocp_data; 8110 u16 data; 8111 int i; 8112 8113 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 8114 return; 8115 8116 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); 8117 ocp_data &= ~EN_ALL_SPEED; 8118 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); 8119 8120 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 8121 8122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); 8123 ocp_data |= BYPASS_MAC_RESET; 8124 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); 8125 8126 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 8127 ocp_data |= RX_DETECT8; 8128 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 8129 8130 r8153b_u1u2en(tp, false); 8131 8132 switch (tp->version) { 8133 case RTL_VER_13: 8134 case RTL_VER_15: 8135 r8156b_wait_loading_flash(tp); 8136 break; 8137 default: 8138 break; 8139 } 8140 8141 for (i = 0; i < 500; i++) { 8142 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 8143 AUTOLOAD_DONE) 8144 break; 8145 8146 msleep(20); 8147 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 8148 return; 8149 } 8150 8151 data = r8153_phy_status(tp, 0); 8152 if (data == PHY_STAT_EXT_INIT) { 8153 data = ocp_reg_read(tp, 0xa468); 8154 data &= ~(BIT(3) | BIT(1)); 8155 ocp_reg_write(tp, 0xa468, data); 8156 8157 data = ocp_reg_read(tp, 0xa466); 8158 data &= ~BIT(0); 8159 ocp_reg_write(tp, 0xa466, data); 8160 } 8161 8162 data = r8152_mdio_read(tp, MII_BMCR); 8163 if (data & BMCR_PDOWN) { 8164 data &= ~BMCR_PDOWN; 8165 r8152_mdio_write(tp, MII_BMCR, data); 8166 } 8167 8168 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 8169 8170 r8153_u2p3en(tp, false); 8171 8172 /* MSC timer = 0xfff * 8ms = 32760 ms */ 8173 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 8174 8175 /* U1/U2/L1 idle timer. 500 us */ 8176 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 8177 8178 r8153b_power_cut_en(tp, false); 8179 r8156_ups_en(tp, false); 8180 r8153_queue_wake(tp, false); 8181 rtl_runtime_suspend_enable(tp, false); 8182 8183 if (tp->udev->speed >= USB_SPEED_SUPER) 8184 r8153b_u1u2en(tp, true); 8185 8186 usb_enable_lpm(tp->udev); 8187 8188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); 8189 ocp_data &= ~SLOT_EN; 8190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 8191 8192 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 8193 ocp_data |= FLOW_CTRL_EN; 8194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 8195 8196 /* enable fc timer and set timer to 600 ms. */ 8197 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, 8198 CTRL_TIMER_EN | (600 / 8)); 8199 8200 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 8201 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) 8202 ocp_data |= FLOW_CTRL_PATCH_2; 8203 ocp_data &= ~AUTO_SPEEDUP; 8204 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 8205 8206 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 8207 ocp_data |= FC_PATCH_TASK; 8208 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 8209 8210 r8156_mac_clk_spd(tp, true); 8211 8212 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 8213 ocp_data &= ~PLA_MCU_SPDWN_EN; 8214 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 8215 8216 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 8217 if (rtl8152_get_speed(tp) & LINK_STATUS) 8218 ocp_data |= CUR_LINK_OK; 8219 else 8220 ocp_data &= ~CUR_LINK_OK; 8221 ocp_data |= POLL_LINK_CHG; 8222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 8223 8224 set_bit(GREEN_ETHERNET, &tp->flags); 8225 8226 /* rx aggregation */ 8227 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 8228 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 8229 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 8230 8231 r8156_mdio_force_mode(tp); 8232 rtl_tally_reset(tp); 8233 8234 tp->coalesce = 15000; /* 15 us */ 8235 } 8236 8237 static bool rtl_check_vendor_ok(struct usb_interface *intf) 8238 { 8239 struct usb_host_interface *alt = intf->cur_altsetting; 8240 struct usb_endpoint_descriptor *in, *out, *intr; 8241 8242 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { 8243 dev_err(&intf->dev, "Expected endpoints are not found\n"); 8244 return false; 8245 } 8246 8247 /* Check Rx endpoint address */ 8248 if (usb_endpoint_num(in) != 1) { 8249 dev_err(&intf->dev, "Invalid Rx endpoint address\n"); 8250 return false; 8251 } 8252 8253 /* Check Tx endpoint address */ 8254 if (usb_endpoint_num(out) != 2) { 8255 dev_err(&intf->dev, "Invalid Tx endpoint address\n"); 8256 return false; 8257 } 8258 8259 /* Check interrupt endpoint address */ 8260 if (usb_endpoint_num(intr) != 3) { 8261 dev_err(&intf->dev, "Invalid interrupt endpoint address\n"); 8262 return false; 8263 } 8264 8265 return true; 8266 } 8267 8268 static int rtl8152_pre_reset(struct usb_interface *intf) 8269 { 8270 struct r8152 *tp = usb_get_intfdata(intf); 8271 struct net_device *netdev; 8272 8273 if (!tp) 8274 return 0; 8275 8276 netdev = tp->netdev; 8277 if (!netif_running(netdev)) 8278 return 0; 8279 8280 netif_stop_queue(netdev); 8281 tasklet_disable(&tp->tx_tl); 8282 clear_bit(WORK_ENABLE, &tp->flags); 8283 usb_kill_urb(tp->intr_urb); 8284 cancel_delayed_work_sync(&tp->schedule); 8285 napi_disable(&tp->napi); 8286 if (netif_carrier_ok(netdev)) { 8287 mutex_lock(&tp->control); 8288 tp->rtl_ops.disable(tp); 8289 mutex_unlock(&tp->control); 8290 } 8291 8292 return 0; 8293 } 8294 8295 static int rtl8152_post_reset(struct usb_interface *intf) 8296 { 8297 struct r8152 *tp = usb_get_intfdata(intf); 8298 struct net_device *netdev; 8299 struct sockaddr sa; 8300 8301 if (!tp) 8302 return 0; 8303 8304 /* reset the MAC address in case of policy change */ 8305 if (determine_ethernet_addr(tp, &sa) >= 0) { 8306 rtnl_lock(); 8307 dev_set_mac_address (tp->netdev, &sa, NULL); 8308 rtnl_unlock(); 8309 } 8310 8311 netdev = tp->netdev; 8312 if (!netif_running(netdev)) 8313 return 0; 8314 8315 set_bit(WORK_ENABLE, &tp->flags); 8316 if (netif_carrier_ok(netdev)) { 8317 mutex_lock(&tp->control); 8318 tp->rtl_ops.enable(tp); 8319 rtl_start_rx(tp); 8320 _rtl8152_set_rx_mode(netdev); 8321 mutex_unlock(&tp->control); 8322 } 8323 8324 napi_enable(&tp->napi); 8325 tasklet_enable(&tp->tx_tl); 8326 netif_wake_queue(netdev); 8327 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 8328 8329 if (!list_empty(&tp->rx_done)) 8330 napi_schedule(&tp->napi); 8331 8332 return 0; 8333 } 8334 8335 static bool delay_autosuspend(struct r8152 *tp) 8336 { 8337 bool sw_linking = !!netif_carrier_ok(tp->netdev); 8338 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 8339 8340 /* This means a linking change occurs and the driver doesn't detect it, 8341 * yet. If the driver has disabled tx/rx and hw is linking on, the 8342 * device wouldn't wake up by receiving any packet. 8343 */ 8344 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 8345 return true; 8346 8347 /* If the linking down is occurred by nway, the device may miss the 8348 * linking change event. And it wouldn't wake when linking on. 8349 */ 8350 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 8351 return true; 8352 else if (!skb_queue_empty(&tp->tx_queue)) 8353 return true; 8354 else 8355 return false; 8356 } 8357 8358 static int rtl8152_runtime_resume(struct r8152 *tp) 8359 { 8360 struct net_device *netdev = tp->netdev; 8361 8362 if (netif_running(netdev) && netdev->flags & IFF_UP) { 8363 struct napi_struct *napi = &tp->napi; 8364 8365 tp->rtl_ops.autosuspend_en(tp, false); 8366 napi_disable(napi); 8367 set_bit(WORK_ENABLE, &tp->flags); 8368 8369 if (netif_carrier_ok(netdev)) { 8370 if (rtl8152_get_speed(tp) & LINK_STATUS) { 8371 rtl_start_rx(tp); 8372 } else { 8373 netif_carrier_off(netdev); 8374 tp->rtl_ops.disable(tp); 8375 netif_info(tp, link, netdev, "linking down\n"); 8376 } 8377 } 8378 8379 napi_enable(napi); 8380 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8381 smp_mb__after_atomic(); 8382 8383 if (!list_empty(&tp->rx_done)) 8384 napi_schedule(&tp->napi); 8385 8386 usb_submit_urb(tp->intr_urb, GFP_NOIO); 8387 } else { 8388 if (netdev->flags & IFF_UP) 8389 tp->rtl_ops.autosuspend_en(tp, false); 8390 8391 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8392 } 8393 8394 return 0; 8395 } 8396 8397 static int rtl8152_system_resume(struct r8152 *tp) 8398 { 8399 struct net_device *netdev = tp->netdev; 8400 8401 netif_device_attach(netdev); 8402 8403 if (netif_running(netdev) && (netdev->flags & IFF_UP)) { 8404 tp->rtl_ops.up(tp); 8405 netif_carrier_off(netdev); 8406 set_bit(WORK_ENABLE, &tp->flags); 8407 usb_submit_urb(tp->intr_urb, GFP_NOIO); 8408 } 8409 8410 return 0; 8411 } 8412 8413 static int rtl8152_runtime_suspend(struct r8152 *tp) 8414 { 8415 struct net_device *netdev = tp->netdev; 8416 int ret = 0; 8417 8418 if (!tp->rtl_ops.autosuspend_en) 8419 return -EBUSY; 8420 8421 set_bit(SELECTIVE_SUSPEND, &tp->flags); 8422 smp_mb__after_atomic(); 8423 8424 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 8425 u32 rcr = 0; 8426 8427 if (netif_carrier_ok(netdev)) { 8428 u32 ocp_data; 8429 8430 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 8431 ocp_data = rcr & ~RCR_ACPT_ALL; 8432 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 8433 rxdy_gated_en(tp, true); 8434 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 8435 PLA_OOB_CTRL); 8436 if (!(ocp_data & RXFIFO_EMPTY)) { 8437 rxdy_gated_en(tp, false); 8438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 8439 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8440 smp_mb__after_atomic(); 8441 ret = -EBUSY; 8442 goto out1; 8443 } 8444 } 8445 8446 clear_bit(WORK_ENABLE, &tp->flags); 8447 usb_kill_urb(tp->intr_urb); 8448 8449 tp->rtl_ops.autosuspend_en(tp, true); 8450 8451 if (netif_carrier_ok(netdev)) { 8452 struct napi_struct *napi = &tp->napi; 8453 8454 napi_disable(napi); 8455 rtl_stop_rx(tp); 8456 rxdy_gated_en(tp, false); 8457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 8458 napi_enable(napi); 8459 } 8460 8461 if (delay_autosuspend(tp)) { 8462 rtl8152_runtime_resume(tp); 8463 ret = -EBUSY; 8464 } 8465 } 8466 8467 out1: 8468 return ret; 8469 } 8470 8471 static int rtl8152_system_suspend(struct r8152 *tp) 8472 { 8473 struct net_device *netdev = tp->netdev; 8474 8475 netif_device_detach(netdev); 8476 8477 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 8478 struct napi_struct *napi = &tp->napi; 8479 8480 clear_bit(WORK_ENABLE, &tp->flags); 8481 usb_kill_urb(tp->intr_urb); 8482 tasklet_disable(&tp->tx_tl); 8483 napi_disable(napi); 8484 cancel_delayed_work_sync(&tp->schedule); 8485 tp->rtl_ops.down(tp); 8486 napi_enable(napi); 8487 tasklet_enable(&tp->tx_tl); 8488 } 8489 8490 return 0; 8491 } 8492 8493 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 8494 { 8495 struct r8152 *tp = usb_get_intfdata(intf); 8496 int ret; 8497 8498 mutex_lock(&tp->control); 8499 8500 if (PMSG_IS_AUTO(message)) 8501 ret = rtl8152_runtime_suspend(tp); 8502 else 8503 ret = rtl8152_system_suspend(tp); 8504 8505 mutex_unlock(&tp->control); 8506 8507 return ret; 8508 } 8509 8510 static int rtl8152_resume(struct usb_interface *intf) 8511 { 8512 struct r8152 *tp = usb_get_intfdata(intf); 8513 int ret; 8514 8515 mutex_lock(&tp->control); 8516 8517 rtl_reset_ocp_base(tp); 8518 8519 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 8520 ret = rtl8152_runtime_resume(tp); 8521 else 8522 ret = rtl8152_system_resume(tp); 8523 8524 mutex_unlock(&tp->control); 8525 8526 return ret; 8527 } 8528 8529 static int rtl8152_reset_resume(struct usb_interface *intf) 8530 { 8531 struct r8152 *tp = usb_get_intfdata(intf); 8532 8533 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8534 rtl_reset_ocp_base(tp); 8535 tp->rtl_ops.init(tp); 8536 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 8537 set_ethernet_addr(tp, true); 8538 return rtl8152_resume(intf); 8539 } 8540 8541 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 8542 { 8543 struct r8152 *tp = netdev_priv(dev); 8544 8545 if (usb_autopm_get_interface(tp->intf) < 0) 8546 return; 8547 8548 if (!rtl_can_wakeup(tp)) { 8549 wol->supported = 0; 8550 wol->wolopts = 0; 8551 } else { 8552 mutex_lock(&tp->control); 8553 wol->supported = WAKE_ANY; 8554 wol->wolopts = __rtl_get_wol(tp); 8555 mutex_unlock(&tp->control); 8556 } 8557 8558 usb_autopm_put_interface(tp->intf); 8559 } 8560 8561 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 8562 { 8563 struct r8152 *tp = netdev_priv(dev); 8564 int ret; 8565 8566 if (!rtl_can_wakeup(tp)) 8567 return -EOPNOTSUPP; 8568 8569 if (wol->wolopts & ~WAKE_ANY) 8570 return -EINVAL; 8571 8572 ret = usb_autopm_get_interface(tp->intf); 8573 if (ret < 0) 8574 goto out_set_wol; 8575 8576 mutex_lock(&tp->control); 8577 8578 __rtl_set_wol(tp, wol->wolopts); 8579 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 8580 8581 mutex_unlock(&tp->control); 8582 8583 usb_autopm_put_interface(tp->intf); 8584 8585 out_set_wol: 8586 return ret; 8587 } 8588 8589 static u32 rtl8152_get_msglevel(struct net_device *dev) 8590 { 8591 struct r8152 *tp = netdev_priv(dev); 8592 8593 return tp->msg_enable; 8594 } 8595 8596 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 8597 { 8598 struct r8152 *tp = netdev_priv(dev); 8599 8600 tp->msg_enable = value; 8601 } 8602 8603 static void rtl8152_get_drvinfo(struct net_device *netdev, 8604 struct ethtool_drvinfo *info) 8605 { 8606 struct r8152 *tp = netdev_priv(netdev); 8607 8608 strscpy(info->driver, MODULENAME, sizeof(info->driver)); 8609 strscpy(info->version, DRIVER_VERSION, sizeof(info->version)); 8610 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 8611 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw)) 8612 strscpy(info->fw_version, tp->rtl_fw.version, 8613 sizeof(info->fw_version)); 8614 } 8615 8616 static 8617 int rtl8152_get_link_ksettings(struct net_device *netdev, 8618 struct ethtool_link_ksettings *cmd) 8619 { 8620 struct r8152 *tp = netdev_priv(netdev); 8621 int ret; 8622 8623 if (!tp->mii.mdio_read) 8624 return -EOPNOTSUPP; 8625 8626 ret = usb_autopm_get_interface(tp->intf); 8627 if (ret < 0) 8628 goto out; 8629 8630 mutex_lock(&tp->control); 8631 8632 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 8633 8634 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8635 cmd->link_modes.supported, tp->support_2500full); 8636 8637 if (tp->support_2500full) { 8638 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8639 cmd->link_modes.advertising, 8640 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); 8641 8642 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8643 cmd->link_modes.lp_advertising, 8644 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); 8645 8646 if (is_speed_2500(rtl8152_get_speed(tp))) 8647 cmd->base.speed = SPEED_2500; 8648 } 8649 8650 mutex_unlock(&tp->control); 8651 8652 usb_autopm_put_interface(tp->intf); 8653 8654 out: 8655 return ret; 8656 } 8657 8658 static int rtl8152_set_link_ksettings(struct net_device *dev, 8659 const struct ethtool_link_ksettings *cmd) 8660 { 8661 struct r8152 *tp = netdev_priv(dev); 8662 u32 advertising = 0; 8663 int ret; 8664 8665 ret = usb_autopm_get_interface(tp->intf); 8666 if (ret < 0) 8667 goto out; 8668 8669 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 8670 cmd->link_modes.advertising)) 8671 advertising |= RTL_ADVERTISED_10_HALF; 8672 8673 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 8674 cmd->link_modes.advertising)) 8675 advertising |= RTL_ADVERTISED_10_FULL; 8676 8677 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 8678 cmd->link_modes.advertising)) 8679 advertising |= RTL_ADVERTISED_100_HALF; 8680 8681 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 8682 cmd->link_modes.advertising)) 8683 advertising |= RTL_ADVERTISED_100_FULL; 8684 8685 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 8686 cmd->link_modes.advertising)) 8687 advertising |= RTL_ADVERTISED_1000_HALF; 8688 8689 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 8690 cmd->link_modes.advertising)) 8691 advertising |= RTL_ADVERTISED_1000_FULL; 8692 8693 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8694 cmd->link_modes.advertising)) 8695 advertising |= RTL_ADVERTISED_2500_FULL; 8696 8697 mutex_lock(&tp->control); 8698 8699 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 8700 cmd->base.duplex, advertising); 8701 if (!ret) { 8702 tp->autoneg = cmd->base.autoneg; 8703 tp->speed = cmd->base.speed; 8704 tp->duplex = cmd->base.duplex; 8705 tp->advertising = advertising; 8706 } 8707 8708 mutex_unlock(&tp->control); 8709 8710 usb_autopm_put_interface(tp->intf); 8711 8712 out: 8713 return ret; 8714 } 8715 8716 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 8717 "tx_packets", 8718 "rx_packets", 8719 "tx_errors", 8720 "rx_errors", 8721 "rx_missed", 8722 "align_errors", 8723 "tx_single_collisions", 8724 "tx_multi_collisions", 8725 "rx_unicast", 8726 "rx_broadcast", 8727 "rx_multicast", 8728 "tx_aborted", 8729 "tx_underrun", 8730 }; 8731 8732 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 8733 { 8734 switch (sset) { 8735 case ETH_SS_STATS: 8736 return ARRAY_SIZE(rtl8152_gstrings); 8737 default: 8738 return -EOPNOTSUPP; 8739 } 8740 } 8741 8742 static void rtl8152_get_ethtool_stats(struct net_device *dev, 8743 struct ethtool_stats *stats, u64 *data) 8744 { 8745 struct r8152 *tp = netdev_priv(dev); 8746 struct tally_counter tally; 8747 8748 if (usb_autopm_get_interface(tp->intf) < 0) 8749 return; 8750 8751 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 8752 8753 usb_autopm_put_interface(tp->intf); 8754 8755 data[0] = le64_to_cpu(tally.tx_packets); 8756 data[1] = le64_to_cpu(tally.rx_packets); 8757 data[2] = le64_to_cpu(tally.tx_errors); 8758 data[3] = le32_to_cpu(tally.rx_errors); 8759 data[4] = le16_to_cpu(tally.rx_missed); 8760 data[5] = le16_to_cpu(tally.align_errors); 8761 data[6] = le32_to_cpu(tally.tx_one_collision); 8762 data[7] = le32_to_cpu(tally.tx_multi_collision); 8763 data[8] = le64_to_cpu(tally.rx_unicast); 8764 data[9] = le64_to_cpu(tally.rx_broadcast); 8765 data[10] = le32_to_cpu(tally.rx_multicast); 8766 data[11] = le16_to_cpu(tally.tx_aborted); 8767 data[12] = le16_to_cpu(tally.tx_underrun); 8768 } 8769 8770 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 8771 { 8772 switch (stringset) { 8773 case ETH_SS_STATS: 8774 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings)); 8775 break; 8776 } 8777 } 8778 8779 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 8780 { 8781 u32 lp, adv, supported = 0; 8782 u16 val; 8783 8784 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 8785 supported = mmd_eee_cap_to_ethtool_sup_t(val); 8786 8787 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 8788 adv = mmd_eee_adv_to_ethtool_adv_t(val); 8789 8790 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 8791 lp = mmd_eee_adv_to_ethtool_adv_t(val); 8792 8793 eee->eee_enabled = tp->eee_en; 8794 eee->eee_active = !!(supported & adv & lp); 8795 eee->supported = supported; 8796 eee->advertised = tp->eee_adv; 8797 eee->lp_advertised = lp; 8798 8799 return 0; 8800 } 8801 8802 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 8803 { 8804 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 8805 8806 tp->eee_en = eee->eee_enabled; 8807 tp->eee_adv = val; 8808 8809 rtl_eee_enable(tp, tp->eee_en); 8810 8811 return 0; 8812 } 8813 8814 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 8815 { 8816 u32 lp, adv, supported = 0; 8817 u16 val; 8818 8819 val = ocp_reg_read(tp, OCP_EEE_ABLE); 8820 supported = mmd_eee_cap_to_ethtool_sup_t(val); 8821 8822 val = ocp_reg_read(tp, OCP_EEE_ADV); 8823 adv = mmd_eee_adv_to_ethtool_adv_t(val); 8824 8825 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 8826 lp = mmd_eee_adv_to_ethtool_adv_t(val); 8827 8828 eee->eee_enabled = tp->eee_en; 8829 eee->eee_active = !!(supported & adv & lp); 8830 eee->supported = supported; 8831 eee->advertised = tp->eee_adv; 8832 eee->lp_advertised = lp; 8833 8834 return 0; 8835 } 8836 8837 static int 8838 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 8839 { 8840 struct r8152 *tp = netdev_priv(net); 8841 int ret; 8842 8843 if (!tp->rtl_ops.eee_get) { 8844 ret = -EOPNOTSUPP; 8845 goto out; 8846 } 8847 8848 ret = usb_autopm_get_interface(tp->intf); 8849 if (ret < 0) 8850 goto out; 8851 8852 mutex_lock(&tp->control); 8853 8854 ret = tp->rtl_ops.eee_get(tp, edata); 8855 8856 mutex_unlock(&tp->control); 8857 8858 usb_autopm_put_interface(tp->intf); 8859 8860 out: 8861 return ret; 8862 } 8863 8864 static int 8865 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 8866 { 8867 struct r8152 *tp = netdev_priv(net); 8868 int ret; 8869 8870 if (!tp->rtl_ops.eee_set) { 8871 ret = -EOPNOTSUPP; 8872 goto out; 8873 } 8874 8875 ret = usb_autopm_get_interface(tp->intf); 8876 if (ret < 0) 8877 goto out; 8878 8879 mutex_lock(&tp->control); 8880 8881 ret = tp->rtl_ops.eee_set(tp, edata); 8882 if (!ret) 8883 ret = mii_nway_restart(&tp->mii); 8884 8885 mutex_unlock(&tp->control); 8886 8887 usb_autopm_put_interface(tp->intf); 8888 8889 out: 8890 return ret; 8891 } 8892 8893 static int rtl8152_nway_reset(struct net_device *dev) 8894 { 8895 struct r8152 *tp = netdev_priv(dev); 8896 int ret; 8897 8898 ret = usb_autopm_get_interface(tp->intf); 8899 if (ret < 0) 8900 goto out; 8901 8902 mutex_lock(&tp->control); 8903 8904 ret = mii_nway_restart(&tp->mii); 8905 8906 mutex_unlock(&tp->control); 8907 8908 usb_autopm_put_interface(tp->intf); 8909 8910 out: 8911 return ret; 8912 } 8913 8914 static int rtl8152_get_coalesce(struct net_device *netdev, 8915 struct ethtool_coalesce *coalesce, 8916 struct kernel_ethtool_coalesce *kernel_coal, 8917 struct netlink_ext_ack *extack) 8918 { 8919 struct r8152 *tp = netdev_priv(netdev); 8920 8921 switch (tp->version) { 8922 case RTL_VER_01: 8923 case RTL_VER_02: 8924 case RTL_VER_07: 8925 return -EOPNOTSUPP; 8926 default: 8927 break; 8928 } 8929 8930 coalesce->rx_coalesce_usecs = tp->coalesce; 8931 8932 return 0; 8933 } 8934 8935 static int rtl8152_set_coalesce(struct net_device *netdev, 8936 struct ethtool_coalesce *coalesce, 8937 struct kernel_ethtool_coalesce *kernel_coal, 8938 struct netlink_ext_ack *extack) 8939 { 8940 struct r8152 *tp = netdev_priv(netdev); 8941 int ret; 8942 8943 switch (tp->version) { 8944 case RTL_VER_01: 8945 case RTL_VER_02: 8946 case RTL_VER_07: 8947 return -EOPNOTSUPP; 8948 default: 8949 break; 8950 } 8951 8952 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 8953 return -EINVAL; 8954 8955 ret = usb_autopm_get_interface(tp->intf); 8956 if (ret < 0) 8957 return ret; 8958 8959 mutex_lock(&tp->control); 8960 8961 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 8962 tp->coalesce = coalesce->rx_coalesce_usecs; 8963 8964 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 8965 netif_stop_queue(netdev); 8966 napi_disable(&tp->napi); 8967 tp->rtl_ops.disable(tp); 8968 tp->rtl_ops.enable(tp); 8969 rtl_start_rx(tp); 8970 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 8971 _rtl8152_set_rx_mode(netdev); 8972 napi_enable(&tp->napi); 8973 netif_wake_queue(netdev); 8974 } 8975 } 8976 8977 mutex_unlock(&tp->control); 8978 8979 usb_autopm_put_interface(tp->intf); 8980 8981 return ret; 8982 } 8983 8984 static int rtl8152_get_tunable(struct net_device *netdev, 8985 const struct ethtool_tunable *tunable, void *d) 8986 { 8987 struct r8152 *tp = netdev_priv(netdev); 8988 8989 switch (tunable->id) { 8990 case ETHTOOL_RX_COPYBREAK: 8991 *(u32 *)d = tp->rx_copybreak; 8992 break; 8993 default: 8994 return -EOPNOTSUPP; 8995 } 8996 8997 return 0; 8998 } 8999 9000 static int rtl8152_set_tunable(struct net_device *netdev, 9001 const struct ethtool_tunable *tunable, 9002 const void *d) 9003 { 9004 struct r8152 *tp = netdev_priv(netdev); 9005 u32 val; 9006 9007 switch (tunable->id) { 9008 case ETHTOOL_RX_COPYBREAK: 9009 val = *(u32 *)d; 9010 if (val < ETH_ZLEN) { 9011 netif_err(tp, rx_err, netdev, 9012 "Invalid rx copy break value\n"); 9013 return -EINVAL; 9014 } 9015 9016 if (tp->rx_copybreak != val) { 9017 if (netdev->flags & IFF_UP) { 9018 mutex_lock(&tp->control); 9019 napi_disable(&tp->napi); 9020 tp->rx_copybreak = val; 9021 napi_enable(&tp->napi); 9022 mutex_unlock(&tp->control); 9023 } else { 9024 tp->rx_copybreak = val; 9025 } 9026 } 9027 break; 9028 default: 9029 return -EOPNOTSUPP; 9030 } 9031 9032 return 0; 9033 } 9034 9035 static void rtl8152_get_ringparam(struct net_device *netdev, 9036 struct ethtool_ringparam *ring, 9037 struct kernel_ethtool_ringparam *kernel_ring, 9038 struct netlink_ext_ack *extack) 9039 { 9040 struct r8152 *tp = netdev_priv(netdev); 9041 9042 ring->rx_max_pending = RTL8152_RX_MAX_PENDING; 9043 ring->rx_pending = tp->rx_pending; 9044 } 9045 9046 static int rtl8152_set_ringparam(struct net_device *netdev, 9047 struct ethtool_ringparam *ring, 9048 struct kernel_ethtool_ringparam *kernel_ring, 9049 struct netlink_ext_ack *extack) 9050 { 9051 struct r8152 *tp = netdev_priv(netdev); 9052 9053 if (ring->rx_pending < (RTL8152_MAX_RX * 2)) 9054 return -EINVAL; 9055 9056 if (tp->rx_pending != ring->rx_pending) { 9057 if (netdev->flags & IFF_UP) { 9058 mutex_lock(&tp->control); 9059 napi_disable(&tp->napi); 9060 tp->rx_pending = ring->rx_pending; 9061 napi_enable(&tp->napi); 9062 mutex_unlock(&tp->control); 9063 } else { 9064 tp->rx_pending = ring->rx_pending; 9065 } 9066 } 9067 9068 return 0; 9069 } 9070 9071 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 9072 { 9073 struct r8152 *tp = netdev_priv(netdev); 9074 u16 bmcr, lcladv, rmtadv; 9075 u8 cap; 9076 9077 if (usb_autopm_get_interface(tp->intf) < 0) 9078 return; 9079 9080 mutex_lock(&tp->control); 9081 9082 bmcr = r8152_mdio_read(tp, MII_BMCR); 9083 lcladv = r8152_mdio_read(tp, MII_ADVERTISE); 9084 rmtadv = r8152_mdio_read(tp, MII_LPA); 9085 9086 mutex_unlock(&tp->control); 9087 9088 usb_autopm_put_interface(tp->intf); 9089 9090 if (!(bmcr & BMCR_ANENABLE)) { 9091 pause->autoneg = 0; 9092 pause->rx_pause = 0; 9093 pause->tx_pause = 0; 9094 return; 9095 } 9096 9097 pause->autoneg = 1; 9098 9099 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 9100 9101 if (cap & FLOW_CTRL_RX) 9102 pause->rx_pause = 1; 9103 9104 if (cap & FLOW_CTRL_TX) 9105 pause->tx_pause = 1; 9106 } 9107 9108 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 9109 { 9110 struct r8152 *tp = netdev_priv(netdev); 9111 u16 old, new1; 9112 u8 cap = 0; 9113 int ret; 9114 9115 ret = usb_autopm_get_interface(tp->intf); 9116 if (ret < 0) 9117 return ret; 9118 9119 mutex_lock(&tp->control); 9120 9121 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) { 9122 ret = -EINVAL; 9123 goto out; 9124 } 9125 9126 if (pause->rx_pause) 9127 cap |= FLOW_CTRL_RX; 9128 9129 if (pause->tx_pause) 9130 cap |= FLOW_CTRL_TX; 9131 9132 old = r8152_mdio_read(tp, MII_ADVERTISE); 9133 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap); 9134 if (old != new1) 9135 r8152_mdio_write(tp, MII_ADVERTISE, new1); 9136 9137 out: 9138 mutex_unlock(&tp->control); 9139 usb_autopm_put_interface(tp->intf); 9140 9141 return ret; 9142 } 9143 9144 static const struct ethtool_ops ops = { 9145 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 9146 .get_drvinfo = rtl8152_get_drvinfo, 9147 .get_link = ethtool_op_get_link, 9148 .nway_reset = rtl8152_nway_reset, 9149 .get_msglevel = rtl8152_get_msglevel, 9150 .set_msglevel = rtl8152_set_msglevel, 9151 .get_wol = rtl8152_get_wol, 9152 .set_wol = rtl8152_set_wol, 9153 .get_strings = rtl8152_get_strings, 9154 .get_sset_count = rtl8152_get_sset_count, 9155 .get_ethtool_stats = rtl8152_get_ethtool_stats, 9156 .get_coalesce = rtl8152_get_coalesce, 9157 .set_coalesce = rtl8152_set_coalesce, 9158 .get_eee = rtl_ethtool_get_eee, 9159 .set_eee = rtl_ethtool_set_eee, 9160 .get_link_ksettings = rtl8152_get_link_ksettings, 9161 .set_link_ksettings = rtl8152_set_link_ksettings, 9162 .get_tunable = rtl8152_get_tunable, 9163 .set_tunable = rtl8152_set_tunable, 9164 .get_ringparam = rtl8152_get_ringparam, 9165 .set_ringparam = rtl8152_set_ringparam, 9166 .get_pauseparam = rtl8152_get_pauseparam, 9167 .set_pauseparam = rtl8152_set_pauseparam, 9168 }; 9169 9170 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 9171 { 9172 struct r8152 *tp = netdev_priv(netdev); 9173 struct mii_ioctl_data *data = if_mii(rq); 9174 int res; 9175 9176 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 9177 return -ENODEV; 9178 9179 res = usb_autopm_get_interface(tp->intf); 9180 if (res < 0) 9181 goto out; 9182 9183 switch (cmd) { 9184 case SIOCGMIIPHY: 9185 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 9186 break; 9187 9188 case SIOCGMIIREG: 9189 mutex_lock(&tp->control); 9190 data->val_out = r8152_mdio_read(tp, data->reg_num); 9191 mutex_unlock(&tp->control); 9192 break; 9193 9194 case SIOCSMIIREG: 9195 if (!capable(CAP_NET_ADMIN)) { 9196 res = -EPERM; 9197 break; 9198 } 9199 mutex_lock(&tp->control); 9200 r8152_mdio_write(tp, data->reg_num, data->val_in); 9201 mutex_unlock(&tp->control); 9202 break; 9203 9204 default: 9205 res = -EOPNOTSUPP; 9206 } 9207 9208 usb_autopm_put_interface(tp->intf); 9209 9210 out: 9211 return res; 9212 } 9213 9214 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 9215 { 9216 struct r8152 *tp = netdev_priv(dev); 9217 int ret; 9218 9219 switch (tp->version) { 9220 case RTL_VER_01: 9221 case RTL_VER_02: 9222 case RTL_VER_07: 9223 dev->mtu = new_mtu; 9224 return 0; 9225 default: 9226 break; 9227 } 9228 9229 ret = usb_autopm_get_interface(tp->intf); 9230 if (ret < 0) 9231 return ret; 9232 9233 mutex_lock(&tp->control); 9234 9235 dev->mtu = new_mtu; 9236 9237 if (netif_running(dev)) { 9238 if (tp->rtl_ops.change_mtu) 9239 tp->rtl_ops.change_mtu(tp); 9240 9241 if (netif_carrier_ok(dev)) { 9242 netif_stop_queue(dev); 9243 napi_disable(&tp->napi); 9244 tasklet_disable(&tp->tx_tl); 9245 tp->rtl_ops.disable(tp); 9246 tp->rtl_ops.enable(tp); 9247 rtl_start_rx(tp); 9248 tasklet_enable(&tp->tx_tl); 9249 napi_enable(&tp->napi); 9250 rtl8152_set_rx_mode(dev); 9251 netif_wake_queue(dev); 9252 } 9253 } 9254 9255 mutex_unlock(&tp->control); 9256 9257 usb_autopm_put_interface(tp->intf); 9258 9259 return ret; 9260 } 9261 9262 static const struct net_device_ops rtl8152_netdev_ops = { 9263 .ndo_open = rtl8152_open, 9264 .ndo_stop = rtl8152_close, 9265 .ndo_eth_ioctl = rtl8152_ioctl, 9266 .ndo_start_xmit = rtl8152_start_xmit, 9267 .ndo_tx_timeout = rtl8152_tx_timeout, 9268 .ndo_set_features = rtl8152_set_features, 9269 .ndo_set_rx_mode = rtl8152_set_rx_mode, 9270 .ndo_set_mac_address = rtl8152_set_mac_address, 9271 .ndo_change_mtu = rtl8152_change_mtu, 9272 .ndo_validate_addr = eth_validate_addr, 9273 .ndo_features_check = rtl8152_features_check, 9274 }; 9275 9276 static void rtl8152_unload(struct r8152 *tp) 9277 { 9278 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 9279 return; 9280 9281 if (tp->version != RTL_VER_01) 9282 r8152_power_cut_en(tp, true); 9283 } 9284 9285 static void rtl8153_unload(struct r8152 *tp) 9286 { 9287 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 9288 return; 9289 9290 r8153_power_cut_en(tp, false); 9291 } 9292 9293 static void rtl8153b_unload(struct r8152 *tp) 9294 { 9295 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 9296 return; 9297 9298 r8153b_power_cut_en(tp, false); 9299 } 9300 9301 static int rtl_ops_init(struct r8152 *tp) 9302 { 9303 struct rtl_ops *ops = &tp->rtl_ops; 9304 int ret = 0; 9305 9306 switch (tp->version) { 9307 case RTL_VER_01: 9308 case RTL_VER_02: 9309 case RTL_VER_07: 9310 ops->init = r8152b_init; 9311 ops->enable = rtl8152_enable; 9312 ops->disable = rtl8152_disable; 9313 ops->up = rtl8152_up; 9314 ops->down = rtl8152_down; 9315 ops->unload = rtl8152_unload; 9316 ops->eee_get = r8152_get_eee; 9317 ops->eee_set = r8152_set_eee; 9318 ops->in_nway = rtl8152_in_nway; 9319 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 9320 ops->autosuspend_en = rtl_runtime_suspend_enable; 9321 tp->rx_buf_sz = 16 * 1024; 9322 tp->eee_en = true; 9323 tp->eee_adv = MDIO_EEE_100TX; 9324 break; 9325 9326 case RTL_VER_03: 9327 case RTL_VER_04: 9328 case RTL_VER_05: 9329 case RTL_VER_06: 9330 ops->init = r8153_init; 9331 ops->enable = rtl8153_enable; 9332 ops->disable = rtl8153_disable; 9333 ops->up = rtl8153_up; 9334 ops->down = rtl8153_down; 9335 ops->unload = rtl8153_unload; 9336 ops->eee_get = r8153_get_eee; 9337 ops->eee_set = r8152_set_eee; 9338 ops->in_nway = rtl8153_in_nway; 9339 ops->hw_phy_cfg = r8153_hw_phy_cfg; 9340 ops->autosuspend_en = rtl8153_runtime_enable; 9341 ops->change_mtu = rtl8153_change_mtu; 9342 if (tp->udev->speed < USB_SPEED_SUPER) 9343 tp->rx_buf_sz = 16 * 1024; 9344 else 9345 tp->rx_buf_sz = 32 * 1024; 9346 tp->eee_en = true; 9347 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9348 break; 9349 9350 case RTL_VER_08: 9351 case RTL_VER_09: 9352 ops->init = r8153b_init; 9353 ops->enable = rtl8153_enable; 9354 ops->disable = rtl8153_disable; 9355 ops->up = rtl8153b_up; 9356 ops->down = rtl8153b_down; 9357 ops->unload = rtl8153b_unload; 9358 ops->eee_get = r8153_get_eee; 9359 ops->eee_set = r8152_set_eee; 9360 ops->in_nway = rtl8153_in_nway; 9361 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 9362 ops->autosuspend_en = rtl8153b_runtime_enable; 9363 ops->change_mtu = rtl8153_change_mtu; 9364 tp->rx_buf_sz = 32 * 1024; 9365 tp->eee_en = true; 9366 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9367 break; 9368 9369 case RTL_VER_11: 9370 tp->eee_en = true; 9371 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9372 fallthrough; 9373 case RTL_VER_10: 9374 ops->init = r8156_init; 9375 ops->enable = rtl8156_enable; 9376 ops->disable = rtl8156_disable; 9377 ops->up = rtl8156_up; 9378 ops->down = rtl8156_down; 9379 ops->unload = rtl8153_unload; 9380 ops->eee_get = r8153_get_eee; 9381 ops->eee_set = r8152_set_eee; 9382 ops->in_nway = rtl8153_in_nway; 9383 ops->hw_phy_cfg = r8156_hw_phy_cfg; 9384 ops->autosuspend_en = rtl8156_runtime_enable; 9385 ops->change_mtu = rtl8156_change_mtu; 9386 tp->rx_buf_sz = 48 * 1024; 9387 tp->support_2500full = 1; 9388 break; 9389 9390 case RTL_VER_12: 9391 case RTL_VER_13: 9392 tp->support_2500full = 1; 9393 fallthrough; 9394 case RTL_VER_15: 9395 tp->eee_en = true; 9396 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9397 ops->init = r8156b_init; 9398 ops->enable = rtl8156b_enable; 9399 ops->disable = rtl8153_disable; 9400 ops->up = rtl8156_up; 9401 ops->down = rtl8156_down; 9402 ops->unload = rtl8153_unload; 9403 ops->eee_get = r8153_get_eee; 9404 ops->eee_set = r8152_set_eee; 9405 ops->in_nway = rtl8153_in_nway; 9406 ops->hw_phy_cfg = r8156b_hw_phy_cfg; 9407 ops->autosuspend_en = rtl8156_runtime_enable; 9408 ops->change_mtu = rtl8156_change_mtu; 9409 tp->rx_buf_sz = 48 * 1024; 9410 break; 9411 9412 case RTL_VER_14: 9413 ops->init = r8153c_init; 9414 ops->enable = rtl8153_enable; 9415 ops->disable = rtl8153_disable; 9416 ops->up = rtl8153c_up; 9417 ops->down = rtl8153b_down; 9418 ops->unload = rtl8153_unload; 9419 ops->eee_get = r8153_get_eee; 9420 ops->eee_set = r8152_set_eee; 9421 ops->in_nway = rtl8153_in_nway; 9422 ops->hw_phy_cfg = r8153c_hw_phy_cfg; 9423 ops->autosuspend_en = rtl8153c_runtime_enable; 9424 ops->change_mtu = rtl8153c_change_mtu; 9425 tp->rx_buf_sz = 32 * 1024; 9426 tp->eee_en = true; 9427 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9428 break; 9429 9430 default: 9431 ret = -ENODEV; 9432 dev_err(&tp->intf->dev, "Unknown Device\n"); 9433 break; 9434 } 9435 9436 return ret; 9437 } 9438 9439 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw" 9440 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" 9441 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" 9442 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" 9443 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" 9444 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw" 9445 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw" 9446 9447 MODULE_FIRMWARE(FIRMWARE_8153A_2); 9448 MODULE_FIRMWARE(FIRMWARE_8153A_3); 9449 MODULE_FIRMWARE(FIRMWARE_8153A_4); 9450 MODULE_FIRMWARE(FIRMWARE_8153B_2); 9451 MODULE_FIRMWARE(FIRMWARE_8153C_1); 9452 MODULE_FIRMWARE(FIRMWARE_8156A_2); 9453 MODULE_FIRMWARE(FIRMWARE_8156B_2); 9454 9455 static int rtl_fw_init(struct r8152 *tp) 9456 { 9457 struct rtl_fw *rtl_fw = &tp->rtl_fw; 9458 9459 switch (tp->version) { 9460 case RTL_VER_04: 9461 rtl_fw->fw_name = FIRMWARE_8153A_2; 9462 rtl_fw->pre_fw = r8153_pre_firmware_1; 9463 rtl_fw->post_fw = r8153_post_firmware_1; 9464 break; 9465 case RTL_VER_05: 9466 rtl_fw->fw_name = FIRMWARE_8153A_3; 9467 rtl_fw->pre_fw = r8153_pre_firmware_2; 9468 rtl_fw->post_fw = r8153_post_firmware_2; 9469 break; 9470 case RTL_VER_06: 9471 rtl_fw->fw_name = FIRMWARE_8153A_4; 9472 rtl_fw->post_fw = r8153_post_firmware_3; 9473 break; 9474 case RTL_VER_09: 9475 rtl_fw->fw_name = FIRMWARE_8153B_2; 9476 rtl_fw->pre_fw = r8153b_pre_firmware_1; 9477 rtl_fw->post_fw = r8153b_post_firmware_1; 9478 break; 9479 case RTL_VER_11: 9480 rtl_fw->fw_name = FIRMWARE_8156A_2; 9481 rtl_fw->post_fw = r8156a_post_firmware_1; 9482 break; 9483 case RTL_VER_13: 9484 case RTL_VER_15: 9485 rtl_fw->fw_name = FIRMWARE_8156B_2; 9486 break; 9487 case RTL_VER_14: 9488 rtl_fw->fw_name = FIRMWARE_8153C_1; 9489 rtl_fw->pre_fw = r8153b_pre_firmware_1; 9490 rtl_fw->post_fw = r8153c_post_firmware_1; 9491 break; 9492 default: 9493 break; 9494 } 9495 9496 return 0; 9497 } 9498 9499 static u8 __rtl_get_hw_ver(struct usb_device *udev) 9500 { 9501 u32 ocp_data = 0; 9502 __le32 *tmp; 9503 u8 version; 9504 int ret; 9505 9506 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 9507 if (!tmp) 9508 return 0; 9509 9510 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 9511 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 9512 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 9513 if (ret > 0) 9514 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 9515 9516 kfree(tmp); 9517 9518 switch (ocp_data) { 9519 case 0x4c00: 9520 version = RTL_VER_01; 9521 break; 9522 case 0x4c10: 9523 version = RTL_VER_02; 9524 break; 9525 case 0x5c00: 9526 version = RTL_VER_03; 9527 break; 9528 case 0x5c10: 9529 version = RTL_VER_04; 9530 break; 9531 case 0x5c20: 9532 version = RTL_VER_05; 9533 break; 9534 case 0x5c30: 9535 version = RTL_VER_06; 9536 break; 9537 case 0x4800: 9538 version = RTL_VER_07; 9539 break; 9540 case 0x6000: 9541 version = RTL_VER_08; 9542 break; 9543 case 0x6010: 9544 version = RTL_VER_09; 9545 break; 9546 case 0x7010: 9547 version = RTL_TEST_01; 9548 break; 9549 case 0x7020: 9550 version = RTL_VER_10; 9551 break; 9552 case 0x7030: 9553 version = RTL_VER_11; 9554 break; 9555 case 0x7400: 9556 version = RTL_VER_12; 9557 break; 9558 case 0x7410: 9559 version = RTL_VER_13; 9560 break; 9561 case 0x6400: 9562 version = RTL_VER_14; 9563 break; 9564 case 0x7420: 9565 version = RTL_VER_15; 9566 break; 9567 default: 9568 version = RTL_VER_UNKNOWN; 9569 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); 9570 break; 9571 } 9572 9573 return version; 9574 } 9575 9576 u8 rtl8152_get_version(struct usb_interface *intf) 9577 { 9578 u8 version; 9579 9580 version = __rtl_get_hw_ver(interface_to_usbdev(intf)); 9581 9582 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 9583 9584 return version; 9585 } 9586 EXPORT_SYMBOL_GPL(rtl8152_get_version); 9587 9588 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev) 9589 { 9590 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor); 9591 int product_id = le16_to_cpu(udev->descriptor.idProduct); 9592 int vendor_id = le16_to_cpu(udev->descriptor.idVendor); 9593 9594 if (vendor_id == VENDOR_ID_LENOVO) { 9595 switch (product_id) { 9596 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB: 9597 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK: 9598 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2: 9599 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2: 9600 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3: 9601 case DEVICE_ID_THINKPAD_USB_C_DONGLE: 9602 return 1; 9603 } 9604 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) { 9605 switch (product_id) { 9606 case 0x8153: 9607 return 1; 9608 } 9609 } 9610 return 0; 9611 } 9612 9613 static int rtl8152_probe(struct usb_interface *intf, 9614 const struct usb_device_id *id) 9615 { 9616 struct usb_device *udev = interface_to_usbdev(intf); 9617 struct r8152 *tp; 9618 struct net_device *netdev; 9619 u8 version; 9620 int ret; 9621 9622 if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) 9623 return -ENODEV; 9624 9625 if (!rtl_check_vendor_ok(intf)) 9626 return -ENODEV; 9627 9628 version = rtl8152_get_version(intf); 9629 if (version == RTL_VER_UNKNOWN) 9630 return -ENODEV; 9631 9632 usb_reset_device(udev); 9633 netdev = alloc_etherdev(sizeof(struct r8152)); 9634 if (!netdev) { 9635 dev_err(&intf->dev, "Out of memory\n"); 9636 return -ENOMEM; 9637 } 9638 9639 SET_NETDEV_DEV(netdev, &intf->dev); 9640 tp = netdev_priv(netdev); 9641 tp->msg_enable = 0x7FFF; 9642 9643 tp->udev = udev; 9644 tp->netdev = netdev; 9645 tp->intf = intf; 9646 tp->version = version; 9647 9648 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); 9649 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); 9650 tp->pipe_in = usb_rcvbulkpipe(udev, 1); 9651 tp->pipe_out = usb_sndbulkpipe(udev, 2); 9652 tp->pipe_intr = usb_rcvintpipe(udev, 3); 9653 9654 switch (version) { 9655 case RTL_VER_01: 9656 case RTL_VER_02: 9657 case RTL_VER_07: 9658 tp->mii.supports_gmii = 0; 9659 break; 9660 default: 9661 tp->mii.supports_gmii = 1; 9662 break; 9663 } 9664 9665 ret = rtl_ops_init(tp); 9666 if (ret) 9667 goto out; 9668 9669 rtl_fw_init(tp); 9670 9671 mutex_init(&tp->control); 9672 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 9673 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 9674 tasklet_setup(&tp->tx_tl, bottom_half); 9675 tasklet_disable(&tp->tx_tl); 9676 9677 netdev->netdev_ops = &rtl8152_netdev_ops; 9678 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 9679 9680 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 9681 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 9682 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 9683 NETIF_F_HW_VLAN_CTAG_TX; 9684 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 9685 NETIF_F_TSO | NETIF_F_FRAGLIST | 9686 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 9687 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 9688 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 9689 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 9690 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 9691 9692 if (tp->version == RTL_VER_01) { 9693 netdev->features &= ~NETIF_F_RXCSUM; 9694 netdev->hw_features &= ~NETIF_F_RXCSUM; 9695 } 9696 9697 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev); 9698 9699 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 9700 (!strcmp(udev->serial, "000001000000") || 9701 !strcmp(udev->serial, "000002000000"))) { 9702 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 9703 tp->dell_tb_rx_agg_bug = 1; 9704 } 9705 9706 netdev->ethtool_ops = &ops; 9707 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 9708 9709 /* MTU range: 68 - 1500 or 9194 */ 9710 netdev->min_mtu = ETH_MIN_MTU; 9711 switch (tp->version) { 9712 case RTL_VER_03: 9713 case RTL_VER_04: 9714 case RTL_VER_05: 9715 case RTL_VER_06: 9716 case RTL_VER_08: 9717 case RTL_VER_09: 9718 case RTL_VER_14: 9719 netdev->max_mtu = size_to_mtu(9 * 1024); 9720 break; 9721 case RTL_VER_10: 9722 case RTL_VER_11: 9723 netdev->max_mtu = size_to_mtu(15 * 1024); 9724 break; 9725 case RTL_VER_12: 9726 case RTL_VER_13: 9727 case RTL_VER_15: 9728 netdev->max_mtu = size_to_mtu(16 * 1024); 9729 break; 9730 case RTL_VER_01: 9731 case RTL_VER_02: 9732 case RTL_VER_07: 9733 default: 9734 netdev->max_mtu = ETH_DATA_LEN; 9735 break; 9736 } 9737 9738 tp->mii.dev = netdev; 9739 tp->mii.mdio_read = read_mii_word; 9740 tp->mii.mdio_write = write_mii_word; 9741 tp->mii.phy_id_mask = 0x3f; 9742 tp->mii.reg_num_mask = 0x1f; 9743 tp->mii.phy_id = R8152_PHY_ID; 9744 9745 tp->autoneg = AUTONEG_ENABLE; 9746 tp->speed = SPEED_100; 9747 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 9748 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 9749 if (tp->mii.supports_gmii) { 9750 if (tp->support_2500full && 9751 tp->udev->speed >= USB_SPEED_SUPER) { 9752 tp->speed = SPEED_2500; 9753 tp->advertising |= RTL_ADVERTISED_2500_FULL; 9754 } else { 9755 tp->speed = SPEED_1000; 9756 } 9757 tp->advertising |= RTL_ADVERTISED_1000_FULL; 9758 } 9759 tp->duplex = DUPLEX_FULL; 9760 9761 tp->rx_copybreak = RTL8152_RXFG_HEADSZ; 9762 tp->rx_pending = 10 * RTL8152_MAX_RX; 9763 9764 intf->needs_remote_wakeup = 1; 9765 9766 if (!rtl_can_wakeup(tp)) 9767 __rtl_set_wol(tp, 0); 9768 else 9769 tp->saved_wolopts = __rtl_get_wol(tp); 9770 9771 tp->rtl_ops.init(tp); 9772 #if IS_BUILTIN(CONFIG_USB_RTL8152) 9773 /* Retry in case request_firmware() is not ready yet. */ 9774 tp->rtl_fw.retry = true; 9775 #endif 9776 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 9777 set_ethernet_addr(tp, false); 9778 9779 usb_set_intfdata(intf, tp); 9780 9781 netif_napi_add_weight(netdev, &tp->napi, r8152_poll, 9782 tp->support_2500full ? 256 : 64); 9783 9784 ret = register_netdev(netdev); 9785 if (ret != 0) { 9786 dev_err(&intf->dev, "couldn't register the device\n"); 9787 goto out1; 9788 } 9789 9790 if (tp->saved_wolopts) 9791 device_set_wakeup_enable(&udev->dev, true); 9792 else 9793 device_set_wakeup_enable(&udev->dev, false); 9794 9795 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 9796 9797 return 0; 9798 9799 out1: 9800 tasklet_kill(&tp->tx_tl); 9801 usb_set_intfdata(intf, NULL); 9802 out: 9803 free_netdev(netdev); 9804 return ret; 9805 } 9806 9807 static void rtl8152_disconnect(struct usb_interface *intf) 9808 { 9809 struct r8152 *tp = usb_get_intfdata(intf); 9810 9811 usb_set_intfdata(intf, NULL); 9812 if (tp) { 9813 rtl_set_unplug(tp); 9814 9815 unregister_netdev(tp->netdev); 9816 tasklet_kill(&tp->tx_tl); 9817 cancel_delayed_work_sync(&tp->hw_phy_work); 9818 if (tp->rtl_ops.unload) 9819 tp->rtl_ops.unload(tp); 9820 rtl8152_release_firmware(tp); 9821 free_netdev(tp->netdev); 9822 } 9823 } 9824 9825 /* table of devices that work with this driver */ 9826 static const struct usb_device_id rtl8152_table[] = { 9827 /* Realtek */ 9828 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) }, 9829 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) }, 9830 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) }, 9831 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, 9832 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, 9833 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, 9834 9835 /* Microsoft */ 9836 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, 9837 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) }, 9838 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) }, 9839 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) }, 9840 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) }, 9841 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) }, 9842 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) }, 9843 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) }, 9844 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) }, 9845 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) }, 9846 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) }, 9847 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) }, 9848 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) }, 9849 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) }, 9850 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) }, 9851 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, 9852 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, 9853 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, 9854 {} 9855 }; 9856 9857 MODULE_DEVICE_TABLE(usb, rtl8152_table); 9858 9859 static struct usb_driver rtl8152_driver = { 9860 .name = MODULENAME, 9861 .id_table = rtl8152_table, 9862 .probe = rtl8152_probe, 9863 .disconnect = rtl8152_disconnect, 9864 .suspend = rtl8152_suspend, 9865 .resume = rtl8152_resume, 9866 .reset_resume = rtl8152_reset_resume, 9867 .pre_reset = rtl8152_pre_reset, 9868 .post_reset = rtl8152_post_reset, 9869 .supports_autosuspend = 1, 9870 .disable_hub_initiated_lpm = 1, 9871 }; 9872 9873 static int rtl8152_cfgselector_probe(struct usb_device *udev) 9874 { 9875 struct usb_host_config *c; 9876 int i, num_configs; 9877 9878 /* Switch the device to vendor mode, if and only if the vendor mode 9879 * driver supports it. 9880 */ 9881 if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN) 9882 return 0; 9883 9884 /* The vendor mode is not always config #1, so to find it out. */ 9885 c = udev->config; 9886 num_configs = udev->descriptor.bNumConfigurations; 9887 for (i = 0; i < num_configs; (i++, c++)) { 9888 struct usb_interface_descriptor *desc = NULL; 9889 9890 if (!c->desc.bNumInterfaces) 9891 continue; 9892 desc = &c->intf_cache[0]->altsetting->desc; 9893 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) 9894 break; 9895 } 9896 9897 if (i == num_configs) 9898 return -ENODEV; 9899 9900 if (usb_set_configuration(udev, c->desc.bConfigurationValue)) { 9901 dev_err(&udev->dev, "Failed to set configuration %d\n", 9902 c->desc.bConfigurationValue); 9903 return -ENODEV; 9904 } 9905 9906 return 0; 9907 } 9908 9909 static struct usb_device_driver rtl8152_cfgselector_driver = { 9910 .name = MODULENAME "-cfgselector", 9911 .probe = rtl8152_cfgselector_probe, 9912 .id_table = rtl8152_table, 9913 .generic_subclass = 1, 9914 .supports_autosuspend = 1, 9915 }; 9916 9917 static int __init rtl8152_driver_init(void) 9918 { 9919 int ret; 9920 9921 ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE); 9922 if (ret) 9923 return ret; 9924 return usb_register(&rtl8152_driver); 9925 } 9926 9927 static void __exit rtl8152_driver_exit(void) 9928 { 9929 usb_deregister(&rtl8152_driver); 9930 usb_deregister_device_driver(&rtl8152_cfgselector_driver); 9931 } 9932 9933 module_init(rtl8152_driver_init); 9934 module_exit(rtl8152_driver_exit); 9935 9936 MODULE_AUTHOR(DRIVER_AUTHOR); 9937 MODULE_DESCRIPTION(DRIVER_DESC); 9938 MODULE_LICENSE("GPL"); 9939 MODULE_VERSION(DRIVER_VERSION); 9940