1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/acpi.h> 26 27 /* Information for net-next */ 28 #define NETNEXT_VERSION "09" 29 30 /* Information for net */ 31 #define NET_VERSION "10" 32 33 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 34 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 35 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 36 #define MODULENAME "r8152" 37 38 #define R8152_PHY_ID 32 39 40 #define PLA_IDR 0xc000 41 #define PLA_RCR 0xc010 42 #define PLA_RMS 0xc016 43 #define PLA_RXFIFO_CTRL0 0xc0a0 44 #define PLA_RXFIFO_CTRL1 0xc0a4 45 #define PLA_RXFIFO_CTRL2 0xc0a8 46 #define PLA_DMY_REG0 0xc0b0 47 #define PLA_FMC 0xc0b4 48 #define PLA_CFG_WOL 0xc0b6 49 #define PLA_TEREDO_CFG 0xc0bc 50 #define PLA_TEREDO_WAKE_BASE 0xc0c4 51 #define PLA_MAR 0xcd00 52 #define PLA_BACKUP 0xd000 53 #define PLA_BDC_CR 0xd1a0 54 #define PLA_TEREDO_TIMER 0xd2cc 55 #define PLA_REALWOW_TIMER 0xd2e8 56 #define PLA_SUSPEND_FLAG 0xd38a 57 #define PLA_INDICATE_FALG 0xd38c 58 #define PLA_EXTRA_STATUS 0xd398 59 #define PLA_EFUSE_DATA 0xdd00 60 #define PLA_EFUSE_CMD 0xdd02 61 #define PLA_LEDSEL 0xdd90 62 #define PLA_LED_FEATURE 0xdd92 63 #define PLA_PHYAR 0xde00 64 #define PLA_BOOT_CTRL 0xe004 65 #define PLA_GPHY_INTR_IMR 0xe022 66 #define PLA_EEE_CR 0xe040 67 #define PLA_EEEP_CR 0xe080 68 #define PLA_MAC_PWR_CTRL 0xe0c0 69 #define PLA_MAC_PWR_CTRL2 0xe0ca 70 #define PLA_MAC_PWR_CTRL3 0xe0cc 71 #define PLA_MAC_PWR_CTRL4 0xe0ce 72 #define PLA_WDT6_CTRL 0xe428 73 #define PLA_TCR0 0xe610 74 #define PLA_TCR1 0xe612 75 #define PLA_MTPS 0xe615 76 #define PLA_TXFIFO_CTRL 0xe618 77 #define PLA_RSTTALLY 0xe800 78 #define PLA_CR 0xe813 79 #define PLA_CRWECR 0xe81c 80 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 81 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 82 #define PLA_CONFIG5 0xe822 83 #define PLA_PHY_PWR 0xe84c 84 #define PLA_OOB_CTRL 0xe84f 85 #define PLA_CPCR 0xe854 86 #define PLA_MISC_0 0xe858 87 #define PLA_MISC_1 0xe85a 88 #define PLA_OCP_GPHY_BASE 0xe86c 89 #define PLA_TALLYCNT 0xe890 90 #define PLA_SFF_STS_7 0xe8de 91 #define PLA_PHYSTATUS 0xe908 92 #define PLA_BP_BA 0xfc26 93 #define PLA_BP_0 0xfc28 94 #define PLA_BP_1 0xfc2a 95 #define PLA_BP_2 0xfc2c 96 #define PLA_BP_3 0xfc2e 97 #define PLA_BP_4 0xfc30 98 #define PLA_BP_5 0xfc32 99 #define PLA_BP_6 0xfc34 100 #define PLA_BP_7 0xfc36 101 #define PLA_BP_EN 0xfc38 102 103 #define USB_USB2PHY 0xb41e 104 #define USB_SSPHYLINK2 0xb428 105 #define USB_U2P3_CTRL 0xb460 106 #define USB_CSR_DUMMY1 0xb464 107 #define USB_CSR_DUMMY2 0xb466 108 #define USB_DEV_STAT 0xb808 109 #define USB_CONNECT_TIMER 0xcbf8 110 #define USB_MSC_TIMER 0xcbfc 111 #define USB_BURST_SIZE 0xcfc0 112 #define USB_LPM_CONFIG 0xcfd8 113 #define USB_USB_CTRL 0xd406 114 #define USB_PHY_CTRL 0xd408 115 #define USB_TX_AGG 0xd40a 116 #define USB_RX_BUF_TH 0xd40c 117 #define USB_USB_TIMER 0xd428 118 #define USB_RX_EARLY_TIMEOUT 0xd42c 119 #define USB_RX_EARLY_SIZE 0xd42e 120 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 121 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 122 #define USB_TX_DMA 0xd434 123 #define USB_UPT_RXDMA_OWN 0xd437 124 #define USB_TOLERANCE 0xd490 125 #define USB_LPM_CTRL 0xd41a 126 #define USB_BMU_RESET 0xd4b0 127 #define USB_U1U2_TIMER 0xd4da 128 #define USB_UPS_CTRL 0xd800 129 #define USB_POWER_CUT 0xd80a 130 #define USB_MISC_0 0xd81a 131 #define USB_MISC_1 0xd81f 132 #define USB_AFE_CTRL2 0xd824 133 #define USB_UPS_CFG 0xd842 134 #define USB_UPS_FLAGS 0xd848 135 #define USB_WDT11_CTRL 0xe43c 136 #define USB_BP_BA 0xfc26 137 #define USB_BP_0 0xfc28 138 #define USB_BP_1 0xfc2a 139 #define USB_BP_2 0xfc2c 140 #define USB_BP_3 0xfc2e 141 #define USB_BP_4 0xfc30 142 #define USB_BP_5 0xfc32 143 #define USB_BP_6 0xfc34 144 #define USB_BP_7 0xfc36 145 #define USB_BP_EN 0xfc38 146 #define USB_BP_8 0xfc38 147 #define USB_BP_9 0xfc3a 148 #define USB_BP_10 0xfc3c 149 #define USB_BP_11 0xfc3e 150 #define USB_BP_12 0xfc40 151 #define USB_BP_13 0xfc42 152 #define USB_BP_14 0xfc44 153 #define USB_BP_15 0xfc46 154 #define USB_BP2_EN 0xfc48 155 156 /* OCP Registers */ 157 #define OCP_ALDPS_CONFIG 0x2010 158 #define OCP_EEE_CONFIG1 0x2080 159 #define OCP_EEE_CONFIG2 0x2092 160 #define OCP_EEE_CONFIG3 0x2094 161 #define OCP_BASE_MII 0xa400 162 #define OCP_EEE_AR 0xa41a 163 #define OCP_EEE_DATA 0xa41c 164 #define OCP_PHY_STATUS 0xa420 165 #define OCP_NCTL_CFG 0xa42c 166 #define OCP_POWER_CFG 0xa430 167 #define OCP_EEE_CFG 0xa432 168 #define OCP_SRAM_ADDR 0xa436 169 #define OCP_SRAM_DATA 0xa438 170 #define OCP_DOWN_SPEED 0xa442 171 #define OCP_EEE_ABLE 0xa5c4 172 #define OCP_EEE_ADV 0xa5d0 173 #define OCP_EEE_LPABLE 0xa5d2 174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 175 #define OCP_PHY_PATCH_STAT 0xb800 176 #define OCP_PHY_PATCH_CMD 0xb820 177 #define OCP_ADC_IOFFSET 0xbcfc 178 #define OCP_ADC_CFG 0xbc06 179 #define OCP_SYSCLK_CFG 0xc416 180 181 /* SRAM Register */ 182 #define SRAM_GREEN_CFG 0x8011 183 #define SRAM_LPF_CFG 0x8012 184 #define SRAM_10M_AMP1 0x8080 185 #define SRAM_10M_AMP2 0x8082 186 #define SRAM_IMPEDANCE 0x8084 187 188 /* PLA_RCR */ 189 #define RCR_AAP 0x00000001 190 #define RCR_APM 0x00000002 191 #define RCR_AM 0x00000004 192 #define RCR_AB 0x00000008 193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 194 195 /* PLA_RXFIFO_CTRL0 */ 196 #define RXFIFO_THR1_NORMAL 0x00080002 197 #define RXFIFO_THR1_OOB 0x01800003 198 199 /* PLA_RXFIFO_CTRL1 */ 200 #define RXFIFO_THR2_FULL 0x00000060 201 #define RXFIFO_THR2_HIGH 0x00000038 202 #define RXFIFO_THR2_OOB 0x0000004a 203 #define RXFIFO_THR2_NORMAL 0x00a0 204 205 /* PLA_RXFIFO_CTRL2 */ 206 #define RXFIFO_THR3_FULL 0x00000078 207 #define RXFIFO_THR3_HIGH 0x00000048 208 #define RXFIFO_THR3_OOB 0x0000005a 209 #define RXFIFO_THR3_NORMAL 0x0110 210 211 /* PLA_TXFIFO_CTRL */ 212 #define TXFIFO_THR_NORMAL 0x00400008 213 #define TXFIFO_THR_NORMAL2 0x01000008 214 215 /* PLA_DMY_REG0 */ 216 #define ECM_ALDPS 0x0002 217 218 /* PLA_FMC */ 219 #define FMC_FCR_MCU_EN 0x0001 220 221 /* PLA_EEEP_CR */ 222 #define EEEP_CR_EEEP_TX 0x0002 223 224 /* PLA_WDT6_CTRL */ 225 #define WDT6_SET_MODE 0x0010 226 227 /* PLA_TCR0 */ 228 #define TCR0_TX_EMPTY 0x0800 229 #define TCR0_AUTO_FIFO 0x0080 230 231 /* PLA_TCR1 */ 232 #define VERSION_MASK 0x7cf0 233 234 /* PLA_MTPS */ 235 #define MTPS_JUMBO (12 * 1024 / 64) 236 #define MTPS_DEFAULT (6 * 1024 / 64) 237 238 /* PLA_RSTTALLY */ 239 #define TALLY_RESET 0x0001 240 241 /* PLA_CR */ 242 #define CR_RST 0x10 243 #define CR_RE 0x08 244 #define CR_TE 0x04 245 246 /* PLA_CRWECR */ 247 #define CRWECR_NORAML 0x00 248 #define CRWECR_CONFIG 0xc0 249 250 /* PLA_OOB_CTRL */ 251 #define NOW_IS_OOB 0x80 252 #define TXFIFO_EMPTY 0x20 253 #define RXFIFO_EMPTY 0x10 254 #define LINK_LIST_READY 0x02 255 #define DIS_MCU_CLROOB 0x01 256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 257 258 /* PLA_MISC_1 */ 259 #define RXDY_GATED_EN 0x0008 260 261 /* PLA_SFF_STS_7 */ 262 #define RE_INIT_LL 0x8000 263 #define MCU_BORW_EN 0x4000 264 265 /* PLA_CPCR */ 266 #define CPCR_RX_VLAN 0x0040 267 268 /* PLA_CFG_WOL */ 269 #define MAGIC_EN 0x0001 270 271 /* PLA_TEREDO_CFG */ 272 #define TEREDO_SEL 0x8000 273 #define TEREDO_WAKE_MASK 0x7f00 274 #define TEREDO_RS_EVENT_MASK 0x00fe 275 #define OOB_TEREDO_EN 0x0001 276 277 /* PLA_BDC_CR */ 278 #define ALDPS_PROXY_MODE 0x0001 279 280 /* PLA_EFUSE_CMD */ 281 #define EFUSE_READ_CMD BIT(15) 282 #define EFUSE_DATA_BIT16 BIT(7) 283 284 /* PLA_CONFIG34 */ 285 #define LINK_ON_WAKE_EN 0x0010 286 #define LINK_OFF_WAKE_EN 0x0008 287 288 /* PLA_CONFIG5 */ 289 #define BWF_EN 0x0040 290 #define MWF_EN 0x0020 291 #define UWF_EN 0x0010 292 #define LAN_WAKE_EN 0x0002 293 294 /* PLA_LED_FEATURE */ 295 #define LED_MODE_MASK 0x0700 296 297 /* PLA_PHY_PWR */ 298 #define TX_10M_IDLE_EN 0x0080 299 #define PFM_PWM_SWITCH 0x0040 300 301 /* PLA_MAC_PWR_CTRL */ 302 #define D3_CLK_GATED_EN 0x00004000 303 #define MCU_CLK_RATIO 0x07010f07 304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 305 #define ALDPS_SPDWN_RATIO 0x0f87 306 307 /* PLA_MAC_PWR_CTRL2 */ 308 #define EEE_SPDWN_RATIO 0x8007 309 #define MAC_CLK_SPDWN_EN BIT(15) 310 311 /* PLA_MAC_PWR_CTRL3 */ 312 #define PKT_AVAIL_SPDWN_EN 0x0100 313 #define SUSPEND_SPDWN_EN 0x0004 314 #define U1U2_SPDWN_EN 0x0002 315 #define L1_SPDWN_EN 0x0001 316 317 /* PLA_MAC_PWR_CTRL4 */ 318 #define PWRSAVE_SPDWN_EN 0x1000 319 #define RXDV_SPDWN_EN 0x0800 320 #define TX10MIDLE_EN 0x0100 321 #define TP100_SPDWN_EN 0x0020 322 #define TP500_SPDWN_EN 0x0010 323 #define TP1000_SPDWN_EN 0x0008 324 #define EEE_SPDWN_EN 0x0001 325 326 /* PLA_GPHY_INTR_IMR */ 327 #define GPHY_STS_MSK 0x0001 328 #define SPEED_DOWN_MSK 0x0002 329 #define SPDWN_RXDV_MSK 0x0004 330 #define SPDWN_LINKCHG_MSK 0x0008 331 332 /* PLA_PHYAR */ 333 #define PHYAR_FLAG 0x80000000 334 335 /* PLA_EEE_CR */ 336 #define EEE_RX_EN 0x0001 337 #define EEE_TX_EN 0x0002 338 339 /* PLA_BOOT_CTRL */ 340 #define AUTOLOAD_DONE 0x0002 341 342 /* PLA_SUSPEND_FLAG */ 343 #define LINK_CHG_EVENT BIT(0) 344 345 /* PLA_INDICATE_FALG */ 346 #define UPCOMING_RUNTIME_D3 BIT(0) 347 348 /* PLA_EXTRA_STATUS */ 349 #define LINK_CHANGE_FLAG BIT(8) 350 351 /* USB_USB2PHY */ 352 #define USB2PHY_SUSPEND 0x0001 353 #define USB2PHY_L1 0x0002 354 355 /* USB_SSPHYLINK2 */ 356 #define pwd_dn_scale_mask 0x3ffe 357 #define pwd_dn_scale(x) ((x) << 1) 358 359 /* USB_CSR_DUMMY1 */ 360 #define DYNAMIC_BURST 0x0001 361 362 /* USB_CSR_DUMMY2 */ 363 #define EP4_FULL_FC 0x0001 364 365 /* USB_DEV_STAT */ 366 #define STAT_SPEED_MASK 0x0006 367 #define STAT_SPEED_HIGH 0x0000 368 #define STAT_SPEED_FULL 0x0002 369 370 /* USB_LPM_CONFIG */ 371 #define LPM_U1U2_EN BIT(0) 372 373 /* USB_TX_AGG */ 374 #define TX_AGG_MAX_THRESHOLD 0x03 375 376 /* USB_RX_BUF_TH */ 377 #define RX_THR_SUPPER 0x0c350180 378 #define RX_THR_HIGH 0x7a120180 379 #define RX_THR_SLOW 0xffff0180 380 #define RX_THR_B 0x00010001 381 382 /* USB_TX_DMA */ 383 #define TEST_MODE_DISABLE 0x00000001 384 #define TX_SIZE_ADJUST1 0x00000100 385 386 /* USB_BMU_RESET */ 387 #define BMU_RESET_EP_IN 0x01 388 #define BMU_RESET_EP_OUT 0x02 389 390 /* USB_UPT_RXDMA_OWN */ 391 #define OWN_UPDATE BIT(0) 392 #define OWN_CLEAR BIT(1) 393 394 /* USB_UPS_CTRL */ 395 #define POWER_CUT 0x0100 396 397 /* USB_PM_CTRL_STATUS */ 398 #define RESUME_INDICATE 0x0001 399 400 /* USB_USB_CTRL */ 401 #define RX_AGG_DISABLE 0x0010 402 #define RX_ZERO_EN 0x0080 403 404 /* USB_U2P3_CTRL */ 405 #define U2P3_ENABLE 0x0001 406 407 /* USB_POWER_CUT */ 408 #define PWR_EN 0x0001 409 #define PHASE2_EN 0x0008 410 #define UPS_EN BIT(4) 411 #define USP_PREWAKE BIT(5) 412 413 /* USB_MISC_0 */ 414 #define PCUT_STATUS 0x0001 415 416 /* USB_RX_EARLY_TIMEOUT */ 417 #define COALESCE_SUPER 85000U 418 #define COALESCE_HIGH 250000U 419 #define COALESCE_SLOW 524280U 420 421 /* USB_WDT11_CTRL */ 422 #define TIMER11_EN 0x0001 423 424 /* USB_LPM_CTRL */ 425 /* bit 4 ~ 5: fifo empty boundary */ 426 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 427 /* bit 2 ~ 3: LMP timer */ 428 #define LPM_TIMER_MASK 0x0c 429 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 430 #define LPM_TIMER_500US 0x0c /* 500 us */ 431 #define ROK_EXIT_LPM 0x02 432 433 /* USB_AFE_CTRL2 */ 434 #define SEN_VAL_MASK 0xf800 435 #define SEN_VAL_NORMAL 0xa000 436 #define SEL_RXIDLE 0x0100 437 438 /* USB_UPS_CFG */ 439 #define SAW_CNT_1MS_MASK 0x0fff 440 441 /* USB_UPS_FLAGS */ 442 #define UPS_FLAGS_R_TUNE BIT(0) 443 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 444 #define UPS_FLAGS_250M_CKDIV BIT(2) 445 #define UPS_FLAGS_EN_ALDPS BIT(3) 446 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 447 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 448 #define ups_flags_speed(x) ((x) << 16) 449 #define UPS_FLAGS_EN_EEE BIT(20) 450 #define UPS_FLAGS_EN_500M_EEE BIT(21) 451 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 452 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 453 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 454 #define UPS_FLAGS_EN_GREEN BIT(26) 455 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 456 457 enum spd_duplex { 458 NWAY_10M_HALF = 1, 459 NWAY_10M_FULL, 460 NWAY_100M_HALF, 461 NWAY_100M_FULL, 462 NWAY_1000M_FULL, 463 FORCE_10M_HALF, 464 FORCE_10M_FULL, 465 FORCE_100M_HALF, 466 FORCE_100M_FULL, 467 }; 468 469 /* OCP_ALDPS_CONFIG */ 470 #define ENPWRSAVE 0x8000 471 #define ENPDNPS 0x0200 472 #define LINKENA 0x0100 473 #define DIS_SDSAVE 0x0010 474 475 /* OCP_PHY_STATUS */ 476 #define PHY_STAT_MASK 0x0007 477 #define PHY_STAT_EXT_INIT 2 478 #define PHY_STAT_LAN_ON 3 479 #define PHY_STAT_PWRDN 5 480 481 /* OCP_NCTL_CFG */ 482 #define PGA_RETURN_EN BIT(1) 483 484 /* OCP_POWER_CFG */ 485 #define EEE_CLKDIV_EN 0x8000 486 #define EN_ALDPS 0x0004 487 #define EN_10M_PLLOFF 0x0001 488 489 /* OCP_EEE_CONFIG1 */ 490 #define RG_TXLPI_MSK_HFDUP 0x8000 491 #define RG_MATCLR_EN 0x4000 492 #define EEE_10_CAP 0x2000 493 #define EEE_NWAY_EN 0x1000 494 #define TX_QUIET_EN 0x0200 495 #define RX_QUIET_EN 0x0100 496 #define sd_rise_time_mask 0x0070 497 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 498 #define RG_RXLPI_MSK_HFDUP 0x0008 499 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 500 501 /* OCP_EEE_CONFIG2 */ 502 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 503 #define RG_DACQUIET_EN 0x0400 504 #define RG_LDVQUIET_EN 0x0200 505 #define RG_CKRSEL 0x0020 506 #define RG_EEEPRG_EN 0x0010 507 508 /* OCP_EEE_CONFIG3 */ 509 #define fast_snr_mask 0xff80 510 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 511 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 512 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 513 514 /* OCP_EEE_AR */ 515 /* bit[15:14] function */ 516 #define FUN_ADDR 0x0000 517 #define FUN_DATA 0x4000 518 /* bit[4:0] device addr */ 519 520 /* OCP_EEE_CFG */ 521 #define CTAP_SHORT_EN 0x0040 522 #define EEE10_EN 0x0010 523 524 /* OCP_DOWN_SPEED */ 525 #define EN_EEE_CMODE BIT(14) 526 #define EN_EEE_1000 BIT(13) 527 #define EN_EEE_100 BIT(12) 528 #define EN_10M_CLKDIV BIT(11) 529 #define EN_10M_BGOFF 0x0080 530 531 /* OCP_PHY_STATE */ 532 #define TXDIS_STATE 0x01 533 #define ABD_STATE 0x02 534 535 /* OCP_PHY_PATCH_STAT */ 536 #define PATCH_READY BIT(6) 537 538 /* OCP_PHY_PATCH_CMD */ 539 #define PATCH_REQUEST BIT(4) 540 541 /* OCP_ADC_CFG */ 542 #define CKADSEL_L 0x0100 543 #define ADC_EN 0x0080 544 #define EN_EMI_L 0x0040 545 546 /* OCP_SYSCLK_CFG */ 547 #define clk_div_expo(x) (min(x, 5) << 8) 548 549 /* SRAM_GREEN_CFG */ 550 #define GREEN_ETH_EN BIT(15) 551 #define R_TUNE_EN BIT(11) 552 553 /* SRAM_LPF_CFG */ 554 #define LPF_AUTO_TUNE 0x8000 555 556 /* SRAM_10M_AMP1 */ 557 #define GDAC_IB_UPALL 0x0008 558 559 /* SRAM_10M_AMP2 */ 560 #define AMP_DN 0x0200 561 562 /* SRAM_IMPEDANCE */ 563 #define RX_DRIVING_MASK 0x6000 564 565 /* MAC PASSTHRU */ 566 #define AD_MASK 0xfee0 567 #define BND_MASK 0x0004 568 #define BD_MASK 0x0001 569 #define EFUSE 0xcfdb 570 #define PASS_THRU_MASK 0x1 571 572 enum rtl_register_content { 573 _1000bps = 0x10, 574 _100bps = 0x08, 575 _10bps = 0x04, 576 LINK_STATUS = 0x02, 577 FULL_DUP = 0x01, 578 }; 579 580 #define RTL8152_MAX_TX 4 581 #define RTL8152_MAX_RX 10 582 #define INTBUFSIZE 2 583 #define TX_ALIGN 4 584 #define RX_ALIGN 8 585 586 #define INTR_LINK 0x0004 587 588 #define RTL8152_REQT_READ 0xc0 589 #define RTL8152_REQT_WRITE 0x40 590 #define RTL8152_REQ_GET_REGS 0x05 591 #define RTL8152_REQ_SET_REGS 0x05 592 593 #define BYTE_EN_DWORD 0xff 594 #define BYTE_EN_WORD 0x33 595 #define BYTE_EN_BYTE 0x11 596 #define BYTE_EN_SIX_BYTES 0x3f 597 #define BYTE_EN_START_MASK 0x0f 598 #define BYTE_EN_END_MASK 0xf0 599 600 #define RTL8153_MAX_PACKET 9216 /* 9K */ 601 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 602 ETH_FCS_LEN) 603 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 604 #define RTL8153_RMS RTL8153_MAX_PACKET 605 #define RTL8152_TX_TIMEOUT (5 * HZ) 606 #define RTL8152_NAPI_WEIGHT 64 607 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 608 sizeof(struct rx_desc) + RX_ALIGN) 609 610 /* rtl8152 flags */ 611 enum rtl8152_flags { 612 RTL8152_UNPLUG = 0, 613 RTL8152_SET_RX_MODE, 614 WORK_ENABLE, 615 RTL8152_LINK_CHG, 616 SELECTIVE_SUSPEND, 617 PHY_RESET, 618 SCHEDULE_NAPI, 619 GREEN_ETHERNET, 620 DELL_TB_RX_AGG_BUG, 621 }; 622 623 /* Define these values to match your device */ 624 #define VENDOR_ID_REALTEK 0x0bda 625 #define VENDOR_ID_MICROSOFT 0x045e 626 #define VENDOR_ID_SAMSUNG 0x04e8 627 #define VENDOR_ID_LENOVO 0x17ef 628 #define VENDOR_ID_LINKSYS 0x13b1 629 #define VENDOR_ID_NVIDIA 0x0955 630 #define VENDOR_ID_TPLINK 0x2357 631 632 #define MCU_TYPE_PLA 0x0100 633 #define MCU_TYPE_USB 0x0000 634 635 struct tally_counter { 636 __le64 tx_packets; 637 __le64 rx_packets; 638 __le64 tx_errors; 639 __le32 rx_errors; 640 __le16 rx_missed; 641 __le16 align_errors; 642 __le32 tx_one_collision; 643 __le32 tx_multi_collision; 644 __le64 rx_unicast; 645 __le64 rx_broadcast; 646 __le32 rx_multicast; 647 __le16 tx_aborted; 648 __le16 tx_underrun; 649 }; 650 651 struct rx_desc { 652 __le32 opts1; 653 #define RX_LEN_MASK 0x7fff 654 655 __le32 opts2; 656 #define RD_UDP_CS BIT(23) 657 #define RD_TCP_CS BIT(22) 658 #define RD_IPV6_CS BIT(20) 659 #define RD_IPV4_CS BIT(19) 660 661 __le32 opts3; 662 #define IPF BIT(23) /* IP checksum fail */ 663 #define UDPF BIT(22) /* UDP checksum fail */ 664 #define TCPF BIT(21) /* TCP checksum fail */ 665 #define RX_VLAN_TAG BIT(16) 666 667 __le32 opts4; 668 __le32 opts5; 669 __le32 opts6; 670 }; 671 672 struct tx_desc { 673 __le32 opts1; 674 #define TX_FS BIT(31) /* First segment of a packet */ 675 #define TX_LS BIT(30) /* Final segment of a packet */ 676 #define GTSENDV4 BIT(28) 677 #define GTSENDV6 BIT(27) 678 #define GTTCPHO_SHIFT 18 679 #define GTTCPHO_MAX 0x7fU 680 #define TX_LEN_MAX 0x3ffffU 681 682 __le32 opts2; 683 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 684 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 685 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 686 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 687 #define MSS_SHIFT 17 688 #define MSS_MAX 0x7ffU 689 #define TCPHO_SHIFT 17 690 #define TCPHO_MAX 0x7ffU 691 #define TX_VLAN_TAG BIT(16) 692 }; 693 694 struct r8152; 695 696 struct rx_agg { 697 struct list_head list; 698 struct urb *urb; 699 struct r8152 *context; 700 void *buffer; 701 void *head; 702 }; 703 704 struct tx_agg { 705 struct list_head list; 706 struct urb *urb; 707 struct r8152 *context; 708 void *buffer; 709 void *head; 710 u32 skb_num; 711 u32 skb_len; 712 }; 713 714 struct r8152 { 715 unsigned long flags; 716 struct usb_device *udev; 717 struct napi_struct napi; 718 struct usb_interface *intf; 719 struct net_device *netdev; 720 struct urb *intr_urb; 721 struct tx_agg tx_info[RTL8152_MAX_TX]; 722 struct rx_agg rx_info[RTL8152_MAX_RX]; 723 struct list_head rx_done, tx_free; 724 struct sk_buff_head tx_queue, rx_queue; 725 spinlock_t rx_lock, tx_lock; 726 struct delayed_work schedule, hw_phy_work; 727 struct mii_if_info mii; 728 struct mutex control; /* use for hw setting */ 729 #ifdef CONFIG_PM_SLEEP 730 struct notifier_block pm_notifier; 731 #endif 732 733 struct rtl_ops { 734 void (*init)(struct r8152 *); 735 int (*enable)(struct r8152 *); 736 void (*disable)(struct r8152 *); 737 void (*up)(struct r8152 *); 738 void (*down)(struct r8152 *); 739 void (*unload)(struct r8152 *); 740 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 741 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 742 bool (*in_nway)(struct r8152 *); 743 void (*hw_phy_cfg)(struct r8152 *); 744 void (*autosuspend_en)(struct r8152 *tp, bool enable); 745 } rtl_ops; 746 747 int intr_interval; 748 u32 saved_wolopts; 749 u32 msg_enable; 750 u32 tx_qlen; 751 u32 coalesce; 752 u16 ocp_base; 753 u16 speed; 754 u8 *intr_buff; 755 u8 version; 756 u8 duplex; 757 u8 autoneg; 758 }; 759 760 enum rtl_version { 761 RTL_VER_UNKNOWN = 0, 762 RTL_VER_01, 763 RTL_VER_02, 764 RTL_VER_03, 765 RTL_VER_04, 766 RTL_VER_05, 767 RTL_VER_06, 768 RTL_VER_07, 769 RTL_VER_08, 770 RTL_VER_09, 771 RTL_VER_MAX 772 }; 773 774 enum tx_csum_stat { 775 TX_CSUM_SUCCESS = 0, 776 TX_CSUM_TSO, 777 TX_CSUM_NONE 778 }; 779 780 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 781 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 782 */ 783 static const int multicast_filter_limit = 32; 784 static unsigned int agg_buf_sz = 16384; 785 786 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 787 VLAN_ETH_HLEN - ETH_FCS_LEN) 788 789 static 790 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 791 { 792 int ret; 793 void *tmp; 794 795 tmp = kmalloc(size, GFP_KERNEL); 796 if (!tmp) 797 return -ENOMEM; 798 799 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 800 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 801 value, index, tmp, size, 500); 802 if (ret < 0) 803 memset(data, 0xff, size); 804 else 805 memcpy(data, tmp, size); 806 807 kfree(tmp); 808 809 return ret; 810 } 811 812 static 813 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 814 { 815 int ret; 816 void *tmp; 817 818 tmp = kmemdup(data, size, GFP_KERNEL); 819 if (!tmp) 820 return -ENOMEM; 821 822 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 823 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 824 value, index, tmp, size, 500); 825 826 kfree(tmp); 827 828 return ret; 829 } 830 831 static void rtl_set_unplug(struct r8152 *tp) 832 { 833 if (tp->udev->state == USB_STATE_NOTATTACHED) { 834 set_bit(RTL8152_UNPLUG, &tp->flags); 835 smp_mb__after_atomic(); 836 } 837 } 838 839 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 840 void *data, u16 type) 841 { 842 u16 limit = 64; 843 int ret = 0; 844 845 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 846 return -ENODEV; 847 848 /* both size and indix must be 4 bytes align */ 849 if ((size & 3) || !size || (index & 3) || !data) 850 return -EPERM; 851 852 if ((u32)index + (u32)size > 0xffff) 853 return -EPERM; 854 855 while (size) { 856 if (size > limit) { 857 ret = get_registers(tp, index, type, limit, data); 858 if (ret < 0) 859 break; 860 861 index += limit; 862 data += limit; 863 size -= limit; 864 } else { 865 ret = get_registers(tp, index, type, size, data); 866 if (ret < 0) 867 break; 868 869 index += size; 870 data += size; 871 size = 0; 872 break; 873 } 874 } 875 876 if (ret == -ENODEV) 877 rtl_set_unplug(tp); 878 879 return ret; 880 } 881 882 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 883 u16 size, void *data, u16 type) 884 { 885 int ret; 886 u16 byteen_start, byteen_end, byen; 887 u16 limit = 512; 888 889 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 890 return -ENODEV; 891 892 /* both size and indix must be 4 bytes align */ 893 if ((size & 3) || !size || (index & 3) || !data) 894 return -EPERM; 895 896 if ((u32)index + (u32)size > 0xffff) 897 return -EPERM; 898 899 byteen_start = byteen & BYTE_EN_START_MASK; 900 byteen_end = byteen & BYTE_EN_END_MASK; 901 902 byen = byteen_start | (byteen_start << 4); 903 ret = set_registers(tp, index, type | byen, 4, data); 904 if (ret < 0) 905 goto error1; 906 907 index += 4; 908 data += 4; 909 size -= 4; 910 911 if (size) { 912 size -= 4; 913 914 while (size) { 915 if (size > limit) { 916 ret = set_registers(tp, index, 917 type | BYTE_EN_DWORD, 918 limit, data); 919 if (ret < 0) 920 goto error1; 921 922 index += limit; 923 data += limit; 924 size -= limit; 925 } else { 926 ret = set_registers(tp, index, 927 type | BYTE_EN_DWORD, 928 size, data); 929 if (ret < 0) 930 goto error1; 931 932 index += size; 933 data += size; 934 size = 0; 935 break; 936 } 937 } 938 939 byen = byteen_end | (byteen_end >> 4); 940 ret = set_registers(tp, index, type | byen, 4, data); 941 if (ret < 0) 942 goto error1; 943 } 944 945 error1: 946 if (ret == -ENODEV) 947 rtl_set_unplug(tp); 948 949 return ret; 950 } 951 952 static inline 953 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 954 { 955 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 956 } 957 958 static inline 959 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 960 { 961 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 962 } 963 964 static inline 965 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 966 { 967 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 968 } 969 970 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 971 { 972 __le32 data; 973 974 generic_ocp_read(tp, index, sizeof(data), &data, type); 975 976 return __le32_to_cpu(data); 977 } 978 979 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 980 { 981 __le32 tmp = __cpu_to_le32(data); 982 983 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 984 } 985 986 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 987 { 988 u32 data; 989 __le32 tmp; 990 u16 byen = BYTE_EN_WORD; 991 u8 shift = index & 2; 992 993 index &= ~3; 994 byen <<= shift; 995 996 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 997 998 data = __le32_to_cpu(tmp); 999 data >>= (shift * 8); 1000 data &= 0xffff; 1001 1002 return (u16)data; 1003 } 1004 1005 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1006 { 1007 u32 mask = 0xffff; 1008 __le32 tmp; 1009 u16 byen = BYTE_EN_WORD; 1010 u8 shift = index & 2; 1011 1012 data &= mask; 1013 1014 if (index & 2) { 1015 byen <<= shift; 1016 mask <<= (shift * 8); 1017 data <<= (shift * 8); 1018 index &= ~3; 1019 } 1020 1021 tmp = __cpu_to_le32(data); 1022 1023 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1024 } 1025 1026 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1027 { 1028 u32 data; 1029 __le32 tmp; 1030 u8 shift = index & 3; 1031 1032 index &= ~3; 1033 1034 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1035 1036 data = __le32_to_cpu(tmp); 1037 data >>= (shift * 8); 1038 data &= 0xff; 1039 1040 return (u8)data; 1041 } 1042 1043 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1044 { 1045 u32 mask = 0xff; 1046 __le32 tmp; 1047 u16 byen = BYTE_EN_BYTE; 1048 u8 shift = index & 3; 1049 1050 data &= mask; 1051 1052 if (index & 3) { 1053 byen <<= shift; 1054 mask <<= (shift * 8); 1055 data <<= (shift * 8); 1056 index &= ~3; 1057 } 1058 1059 tmp = __cpu_to_le32(data); 1060 1061 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1062 } 1063 1064 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1065 { 1066 u16 ocp_base, ocp_index; 1067 1068 ocp_base = addr & 0xf000; 1069 if (ocp_base != tp->ocp_base) { 1070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1071 tp->ocp_base = ocp_base; 1072 } 1073 1074 ocp_index = (addr & 0x0fff) | 0xb000; 1075 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1076 } 1077 1078 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1079 { 1080 u16 ocp_base, ocp_index; 1081 1082 ocp_base = addr & 0xf000; 1083 if (ocp_base != tp->ocp_base) { 1084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1085 tp->ocp_base = ocp_base; 1086 } 1087 1088 ocp_index = (addr & 0x0fff) | 0xb000; 1089 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1090 } 1091 1092 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1093 { 1094 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1095 } 1096 1097 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1098 { 1099 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1100 } 1101 1102 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1103 { 1104 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1105 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1106 } 1107 1108 static u16 sram_read(struct r8152 *tp, u16 addr) 1109 { 1110 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1111 return ocp_reg_read(tp, OCP_SRAM_DATA); 1112 } 1113 1114 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1115 { 1116 struct r8152 *tp = netdev_priv(netdev); 1117 int ret; 1118 1119 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1120 return -ENODEV; 1121 1122 if (phy_id != R8152_PHY_ID) 1123 return -EINVAL; 1124 1125 ret = r8152_mdio_read(tp, reg); 1126 1127 return ret; 1128 } 1129 1130 static 1131 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1132 { 1133 struct r8152 *tp = netdev_priv(netdev); 1134 1135 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1136 return; 1137 1138 if (phy_id != R8152_PHY_ID) 1139 return; 1140 1141 r8152_mdio_write(tp, reg, val); 1142 } 1143 1144 static int 1145 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1146 1147 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1148 { 1149 struct r8152 *tp = netdev_priv(netdev); 1150 struct sockaddr *addr = p; 1151 int ret = -EADDRNOTAVAIL; 1152 1153 if (!is_valid_ether_addr(addr->sa_data)) 1154 goto out1; 1155 1156 ret = usb_autopm_get_interface(tp->intf); 1157 if (ret < 0) 1158 goto out1; 1159 1160 mutex_lock(&tp->control); 1161 1162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1163 1164 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1165 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1166 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1167 1168 mutex_unlock(&tp->control); 1169 1170 usb_autopm_put_interface(tp->intf); 1171 out1: 1172 return ret; 1173 } 1174 1175 /* Devices containing proper chips can support a persistent 1176 * host system provided MAC address. 1177 * Examples of this are Dell TB15 and Dell WD15 docks 1178 */ 1179 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1180 { 1181 acpi_status status; 1182 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1183 union acpi_object *obj; 1184 int ret = -EINVAL; 1185 u32 ocp_data; 1186 unsigned char buf[6]; 1187 1188 /* test for -AD variant of RTL8153 */ 1189 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1190 if ((ocp_data & AD_MASK) == 0x1000) { 1191 /* test for MAC address pass-through bit */ 1192 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1193 if ((ocp_data & PASS_THRU_MASK) != 1) { 1194 netif_dbg(tp, probe, tp->netdev, 1195 "No efuse for RTL8153-AD MAC pass through\n"); 1196 return -ENODEV; 1197 } 1198 } else { 1199 /* test for RTL8153-BND and RTL8153-BD */ 1200 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1201 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1202 netif_dbg(tp, probe, tp->netdev, 1203 "Invalid variant for MAC pass through\n"); 1204 return -ENODEV; 1205 } 1206 } 1207 1208 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1209 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1210 obj = (union acpi_object *)buffer.pointer; 1211 if (!ACPI_SUCCESS(status)) 1212 return -ENODEV; 1213 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1214 netif_warn(tp, probe, tp->netdev, 1215 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1216 obj->type, obj->string.length); 1217 goto amacout; 1218 } 1219 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1220 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1221 netif_warn(tp, probe, tp->netdev, 1222 "Invalid header when reading pass-thru MAC addr\n"); 1223 goto amacout; 1224 } 1225 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1226 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1227 netif_warn(tp, probe, tp->netdev, 1228 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1229 ret, buf); 1230 ret = -EINVAL; 1231 goto amacout; 1232 } 1233 memcpy(sa->sa_data, buf, 6); 1234 netif_info(tp, probe, tp->netdev, 1235 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1236 1237 amacout: 1238 kfree(obj); 1239 return ret; 1240 } 1241 1242 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1243 { 1244 struct net_device *dev = tp->netdev; 1245 int ret; 1246 1247 sa->sa_family = dev->type; 1248 1249 if (tp->version == RTL_VER_01) { 1250 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1251 } else { 1252 /* if device doesn't support MAC pass through this will 1253 * be expected to be non-zero 1254 */ 1255 ret = vendor_mac_passthru_addr_read(tp, sa); 1256 if (ret < 0) 1257 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1258 } 1259 1260 if (ret < 0) { 1261 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1262 } else if (!is_valid_ether_addr(sa->sa_data)) { 1263 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1264 sa->sa_data); 1265 eth_hw_addr_random(dev); 1266 ether_addr_copy(sa->sa_data, dev->dev_addr); 1267 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1268 sa->sa_data); 1269 return 0; 1270 } 1271 1272 return ret; 1273 } 1274 1275 static int set_ethernet_addr(struct r8152 *tp) 1276 { 1277 struct net_device *dev = tp->netdev; 1278 struct sockaddr sa; 1279 int ret; 1280 1281 ret = determine_ethernet_addr(tp, &sa); 1282 if (ret < 0) 1283 return ret; 1284 1285 if (tp->version == RTL_VER_01) 1286 ether_addr_copy(dev->dev_addr, sa.sa_data); 1287 else 1288 ret = rtl8152_set_mac_address(dev, &sa); 1289 1290 return ret; 1291 } 1292 1293 static void read_bulk_callback(struct urb *urb) 1294 { 1295 struct net_device *netdev; 1296 int status = urb->status; 1297 struct rx_agg *agg; 1298 struct r8152 *tp; 1299 unsigned long flags; 1300 1301 agg = urb->context; 1302 if (!agg) 1303 return; 1304 1305 tp = agg->context; 1306 if (!tp) 1307 return; 1308 1309 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1310 return; 1311 1312 if (!test_bit(WORK_ENABLE, &tp->flags)) 1313 return; 1314 1315 netdev = tp->netdev; 1316 1317 /* When link down, the driver would cancel all bulks. */ 1318 /* This avoid the re-submitting bulk */ 1319 if (!netif_carrier_ok(netdev)) 1320 return; 1321 1322 usb_mark_last_busy(tp->udev); 1323 1324 switch (status) { 1325 case 0: 1326 if (urb->actual_length < ETH_ZLEN) 1327 break; 1328 1329 spin_lock_irqsave(&tp->rx_lock, flags); 1330 list_add_tail(&agg->list, &tp->rx_done); 1331 spin_unlock_irqrestore(&tp->rx_lock, flags); 1332 napi_schedule(&tp->napi); 1333 return; 1334 case -ESHUTDOWN: 1335 rtl_set_unplug(tp); 1336 netif_device_detach(tp->netdev); 1337 return; 1338 case -ENOENT: 1339 return; /* the urb is in unlink state */ 1340 case -ETIME: 1341 if (net_ratelimit()) 1342 netdev_warn(netdev, "maybe reset is needed?\n"); 1343 break; 1344 default: 1345 if (net_ratelimit()) 1346 netdev_warn(netdev, "Rx status %d\n", status); 1347 break; 1348 } 1349 1350 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1351 } 1352 1353 static void write_bulk_callback(struct urb *urb) 1354 { 1355 struct net_device_stats *stats; 1356 struct net_device *netdev; 1357 struct tx_agg *agg; 1358 struct r8152 *tp; 1359 unsigned long flags; 1360 int status = urb->status; 1361 1362 agg = urb->context; 1363 if (!agg) 1364 return; 1365 1366 tp = agg->context; 1367 if (!tp) 1368 return; 1369 1370 netdev = tp->netdev; 1371 stats = &netdev->stats; 1372 if (status) { 1373 if (net_ratelimit()) 1374 netdev_warn(netdev, "Tx status %d\n", status); 1375 stats->tx_errors += agg->skb_num; 1376 } else { 1377 stats->tx_packets += agg->skb_num; 1378 stats->tx_bytes += agg->skb_len; 1379 } 1380 1381 spin_lock_irqsave(&tp->tx_lock, flags); 1382 list_add_tail(&agg->list, &tp->tx_free); 1383 spin_unlock_irqrestore(&tp->tx_lock, flags); 1384 1385 usb_autopm_put_interface_async(tp->intf); 1386 1387 if (!netif_carrier_ok(netdev)) 1388 return; 1389 1390 if (!test_bit(WORK_ENABLE, &tp->flags)) 1391 return; 1392 1393 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1394 return; 1395 1396 if (!skb_queue_empty(&tp->tx_queue)) 1397 napi_schedule(&tp->napi); 1398 } 1399 1400 static void intr_callback(struct urb *urb) 1401 { 1402 struct r8152 *tp; 1403 __le16 *d; 1404 int status = urb->status; 1405 int res; 1406 1407 tp = urb->context; 1408 if (!tp) 1409 return; 1410 1411 if (!test_bit(WORK_ENABLE, &tp->flags)) 1412 return; 1413 1414 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1415 return; 1416 1417 switch (status) { 1418 case 0: /* success */ 1419 break; 1420 case -ECONNRESET: /* unlink */ 1421 case -ESHUTDOWN: 1422 netif_device_detach(tp->netdev); 1423 /* fall through */ 1424 case -ENOENT: 1425 case -EPROTO: 1426 netif_info(tp, intr, tp->netdev, 1427 "Stop submitting intr, status %d\n", status); 1428 return; 1429 case -EOVERFLOW: 1430 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1431 goto resubmit; 1432 /* -EPIPE: should clear the halt */ 1433 default: 1434 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1435 goto resubmit; 1436 } 1437 1438 d = urb->transfer_buffer; 1439 if (INTR_LINK & __le16_to_cpu(d[0])) { 1440 if (!netif_carrier_ok(tp->netdev)) { 1441 set_bit(RTL8152_LINK_CHG, &tp->flags); 1442 schedule_delayed_work(&tp->schedule, 0); 1443 } 1444 } else { 1445 if (netif_carrier_ok(tp->netdev)) { 1446 netif_stop_queue(tp->netdev); 1447 set_bit(RTL8152_LINK_CHG, &tp->flags); 1448 schedule_delayed_work(&tp->schedule, 0); 1449 } 1450 } 1451 1452 resubmit: 1453 res = usb_submit_urb(urb, GFP_ATOMIC); 1454 if (res == -ENODEV) { 1455 rtl_set_unplug(tp); 1456 netif_device_detach(tp->netdev); 1457 } else if (res) { 1458 netif_err(tp, intr, tp->netdev, 1459 "can't resubmit intr, status %d\n", res); 1460 } 1461 } 1462 1463 static inline void *rx_agg_align(void *data) 1464 { 1465 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1466 } 1467 1468 static inline void *tx_agg_align(void *data) 1469 { 1470 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1471 } 1472 1473 static void free_all_mem(struct r8152 *tp) 1474 { 1475 int i; 1476 1477 for (i = 0; i < RTL8152_MAX_RX; i++) { 1478 usb_free_urb(tp->rx_info[i].urb); 1479 tp->rx_info[i].urb = NULL; 1480 1481 kfree(tp->rx_info[i].buffer); 1482 tp->rx_info[i].buffer = NULL; 1483 tp->rx_info[i].head = NULL; 1484 } 1485 1486 for (i = 0; i < RTL8152_MAX_TX; i++) { 1487 usb_free_urb(tp->tx_info[i].urb); 1488 tp->tx_info[i].urb = NULL; 1489 1490 kfree(tp->tx_info[i].buffer); 1491 tp->tx_info[i].buffer = NULL; 1492 tp->tx_info[i].head = NULL; 1493 } 1494 1495 usb_free_urb(tp->intr_urb); 1496 tp->intr_urb = NULL; 1497 1498 kfree(tp->intr_buff); 1499 tp->intr_buff = NULL; 1500 } 1501 1502 static int alloc_all_mem(struct r8152 *tp) 1503 { 1504 struct net_device *netdev = tp->netdev; 1505 struct usb_interface *intf = tp->intf; 1506 struct usb_host_interface *alt = intf->cur_altsetting; 1507 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1508 struct urb *urb; 1509 int node, i; 1510 u8 *buf; 1511 1512 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1513 1514 spin_lock_init(&tp->rx_lock); 1515 spin_lock_init(&tp->tx_lock); 1516 INIT_LIST_HEAD(&tp->tx_free); 1517 INIT_LIST_HEAD(&tp->rx_done); 1518 skb_queue_head_init(&tp->tx_queue); 1519 skb_queue_head_init(&tp->rx_queue); 1520 1521 for (i = 0; i < RTL8152_MAX_RX; i++) { 1522 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1523 if (!buf) 1524 goto err1; 1525 1526 if (buf != rx_agg_align(buf)) { 1527 kfree(buf); 1528 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1529 node); 1530 if (!buf) 1531 goto err1; 1532 } 1533 1534 urb = usb_alloc_urb(0, GFP_KERNEL); 1535 if (!urb) { 1536 kfree(buf); 1537 goto err1; 1538 } 1539 1540 INIT_LIST_HEAD(&tp->rx_info[i].list); 1541 tp->rx_info[i].context = tp; 1542 tp->rx_info[i].urb = urb; 1543 tp->rx_info[i].buffer = buf; 1544 tp->rx_info[i].head = rx_agg_align(buf); 1545 } 1546 1547 for (i = 0; i < RTL8152_MAX_TX; i++) { 1548 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1549 if (!buf) 1550 goto err1; 1551 1552 if (buf != tx_agg_align(buf)) { 1553 kfree(buf); 1554 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1555 node); 1556 if (!buf) 1557 goto err1; 1558 } 1559 1560 urb = usb_alloc_urb(0, GFP_KERNEL); 1561 if (!urb) { 1562 kfree(buf); 1563 goto err1; 1564 } 1565 1566 INIT_LIST_HEAD(&tp->tx_info[i].list); 1567 tp->tx_info[i].context = tp; 1568 tp->tx_info[i].urb = urb; 1569 tp->tx_info[i].buffer = buf; 1570 tp->tx_info[i].head = tx_agg_align(buf); 1571 1572 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1573 } 1574 1575 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1576 if (!tp->intr_urb) 1577 goto err1; 1578 1579 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1580 if (!tp->intr_buff) 1581 goto err1; 1582 1583 tp->intr_interval = (int)ep_intr->desc.bInterval; 1584 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1585 tp->intr_buff, INTBUFSIZE, intr_callback, 1586 tp, tp->intr_interval); 1587 1588 return 0; 1589 1590 err1: 1591 free_all_mem(tp); 1592 return -ENOMEM; 1593 } 1594 1595 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1596 { 1597 struct tx_agg *agg = NULL; 1598 unsigned long flags; 1599 1600 if (list_empty(&tp->tx_free)) 1601 return NULL; 1602 1603 spin_lock_irqsave(&tp->tx_lock, flags); 1604 if (!list_empty(&tp->tx_free)) { 1605 struct list_head *cursor; 1606 1607 cursor = tp->tx_free.next; 1608 list_del_init(cursor); 1609 agg = list_entry(cursor, struct tx_agg, list); 1610 } 1611 spin_unlock_irqrestore(&tp->tx_lock, flags); 1612 1613 return agg; 1614 } 1615 1616 /* r8152_csum_workaround() 1617 * The hw limites the value the transport offset. When the offset is out of the 1618 * range, calculate the checksum by sw. 1619 */ 1620 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1621 struct sk_buff_head *list) 1622 { 1623 if (skb_shinfo(skb)->gso_size) { 1624 netdev_features_t features = tp->netdev->features; 1625 struct sk_buff_head seg_list; 1626 struct sk_buff *segs, *nskb; 1627 1628 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1629 segs = skb_gso_segment(skb, features); 1630 if (IS_ERR(segs) || !segs) 1631 goto drop; 1632 1633 __skb_queue_head_init(&seg_list); 1634 1635 do { 1636 nskb = segs; 1637 segs = segs->next; 1638 nskb->next = NULL; 1639 __skb_queue_tail(&seg_list, nskb); 1640 } while (segs); 1641 1642 skb_queue_splice(&seg_list, list); 1643 dev_kfree_skb(skb); 1644 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1645 if (skb_checksum_help(skb) < 0) 1646 goto drop; 1647 1648 __skb_queue_head(list, skb); 1649 } else { 1650 struct net_device_stats *stats; 1651 1652 drop: 1653 stats = &tp->netdev->stats; 1654 stats->tx_dropped++; 1655 dev_kfree_skb(skb); 1656 } 1657 } 1658 1659 /* msdn_giant_send_check() 1660 * According to the document of microsoft, the TCP Pseudo Header excludes the 1661 * packet length for IPv6 TCP large packets. 1662 */ 1663 static int msdn_giant_send_check(struct sk_buff *skb) 1664 { 1665 const struct ipv6hdr *ipv6h; 1666 struct tcphdr *th; 1667 int ret; 1668 1669 ret = skb_cow_head(skb, 0); 1670 if (ret) 1671 return ret; 1672 1673 ipv6h = ipv6_hdr(skb); 1674 th = tcp_hdr(skb); 1675 1676 th->check = 0; 1677 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1678 1679 return ret; 1680 } 1681 1682 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1683 { 1684 if (skb_vlan_tag_present(skb)) { 1685 u32 opts2; 1686 1687 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1688 desc->opts2 |= cpu_to_le32(opts2); 1689 } 1690 } 1691 1692 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1693 { 1694 u32 opts2 = le32_to_cpu(desc->opts2); 1695 1696 if (opts2 & RX_VLAN_TAG) 1697 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1698 swab16(opts2 & 0xffff)); 1699 } 1700 1701 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1702 struct sk_buff *skb, u32 len, u32 transport_offset) 1703 { 1704 u32 mss = skb_shinfo(skb)->gso_size; 1705 u32 opts1, opts2 = 0; 1706 int ret = TX_CSUM_SUCCESS; 1707 1708 WARN_ON_ONCE(len > TX_LEN_MAX); 1709 1710 opts1 = len | TX_FS | TX_LS; 1711 1712 if (mss) { 1713 if (transport_offset > GTTCPHO_MAX) { 1714 netif_warn(tp, tx_err, tp->netdev, 1715 "Invalid transport offset 0x%x for TSO\n", 1716 transport_offset); 1717 ret = TX_CSUM_TSO; 1718 goto unavailable; 1719 } 1720 1721 switch (vlan_get_protocol(skb)) { 1722 case htons(ETH_P_IP): 1723 opts1 |= GTSENDV4; 1724 break; 1725 1726 case htons(ETH_P_IPV6): 1727 if (msdn_giant_send_check(skb)) { 1728 ret = TX_CSUM_TSO; 1729 goto unavailable; 1730 } 1731 opts1 |= GTSENDV6; 1732 break; 1733 1734 default: 1735 WARN_ON_ONCE(1); 1736 break; 1737 } 1738 1739 opts1 |= transport_offset << GTTCPHO_SHIFT; 1740 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1741 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1742 u8 ip_protocol; 1743 1744 if (transport_offset > TCPHO_MAX) { 1745 netif_warn(tp, tx_err, tp->netdev, 1746 "Invalid transport offset 0x%x\n", 1747 transport_offset); 1748 ret = TX_CSUM_NONE; 1749 goto unavailable; 1750 } 1751 1752 switch (vlan_get_protocol(skb)) { 1753 case htons(ETH_P_IP): 1754 opts2 |= IPV4_CS; 1755 ip_protocol = ip_hdr(skb)->protocol; 1756 break; 1757 1758 case htons(ETH_P_IPV6): 1759 opts2 |= IPV6_CS; 1760 ip_protocol = ipv6_hdr(skb)->nexthdr; 1761 break; 1762 1763 default: 1764 ip_protocol = IPPROTO_RAW; 1765 break; 1766 } 1767 1768 if (ip_protocol == IPPROTO_TCP) 1769 opts2 |= TCP_CS; 1770 else if (ip_protocol == IPPROTO_UDP) 1771 opts2 |= UDP_CS; 1772 else 1773 WARN_ON_ONCE(1); 1774 1775 opts2 |= transport_offset << TCPHO_SHIFT; 1776 } 1777 1778 desc->opts2 = cpu_to_le32(opts2); 1779 desc->opts1 = cpu_to_le32(opts1); 1780 1781 unavailable: 1782 return ret; 1783 } 1784 1785 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1786 { 1787 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1788 int remain, ret; 1789 u8 *tx_data; 1790 1791 __skb_queue_head_init(&skb_head); 1792 spin_lock(&tx_queue->lock); 1793 skb_queue_splice_init(tx_queue, &skb_head); 1794 spin_unlock(&tx_queue->lock); 1795 1796 tx_data = agg->head; 1797 agg->skb_num = 0; 1798 agg->skb_len = 0; 1799 remain = agg_buf_sz; 1800 1801 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1802 struct tx_desc *tx_desc; 1803 struct sk_buff *skb; 1804 unsigned int len; 1805 u32 offset; 1806 1807 skb = __skb_dequeue(&skb_head); 1808 if (!skb) 1809 break; 1810 1811 len = skb->len + sizeof(*tx_desc); 1812 1813 if (len > remain) { 1814 __skb_queue_head(&skb_head, skb); 1815 break; 1816 } 1817 1818 tx_data = tx_agg_align(tx_data); 1819 tx_desc = (struct tx_desc *)tx_data; 1820 1821 offset = (u32)skb_transport_offset(skb); 1822 1823 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1824 r8152_csum_workaround(tp, skb, &skb_head); 1825 continue; 1826 } 1827 1828 rtl_tx_vlan_tag(tx_desc, skb); 1829 1830 tx_data += sizeof(*tx_desc); 1831 1832 len = skb->len; 1833 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1834 struct net_device_stats *stats = &tp->netdev->stats; 1835 1836 stats->tx_dropped++; 1837 dev_kfree_skb_any(skb); 1838 tx_data -= sizeof(*tx_desc); 1839 continue; 1840 } 1841 1842 tx_data += len; 1843 agg->skb_len += len; 1844 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1845 1846 dev_kfree_skb_any(skb); 1847 1848 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1849 1850 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1851 break; 1852 } 1853 1854 if (!skb_queue_empty(&skb_head)) { 1855 spin_lock(&tx_queue->lock); 1856 skb_queue_splice(&skb_head, tx_queue); 1857 spin_unlock(&tx_queue->lock); 1858 } 1859 1860 netif_tx_lock(tp->netdev); 1861 1862 if (netif_queue_stopped(tp->netdev) && 1863 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1864 netif_wake_queue(tp->netdev); 1865 1866 netif_tx_unlock(tp->netdev); 1867 1868 ret = usb_autopm_get_interface_async(tp->intf); 1869 if (ret < 0) 1870 goto out_tx_fill; 1871 1872 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1873 agg->head, (int)(tx_data - (u8 *)agg->head), 1874 (usb_complete_t)write_bulk_callback, agg); 1875 1876 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1877 if (ret < 0) 1878 usb_autopm_put_interface_async(tp->intf); 1879 1880 out_tx_fill: 1881 return ret; 1882 } 1883 1884 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1885 { 1886 u8 checksum = CHECKSUM_NONE; 1887 u32 opts2, opts3; 1888 1889 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1890 goto return_result; 1891 1892 opts2 = le32_to_cpu(rx_desc->opts2); 1893 opts3 = le32_to_cpu(rx_desc->opts3); 1894 1895 if (opts2 & RD_IPV4_CS) { 1896 if (opts3 & IPF) 1897 checksum = CHECKSUM_NONE; 1898 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1899 checksum = CHECKSUM_UNNECESSARY; 1900 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1901 checksum = CHECKSUM_UNNECESSARY; 1902 } else if (opts2 & RD_IPV6_CS) { 1903 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1904 checksum = CHECKSUM_UNNECESSARY; 1905 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1906 checksum = CHECKSUM_UNNECESSARY; 1907 } 1908 1909 return_result: 1910 return checksum; 1911 } 1912 1913 static int rx_bottom(struct r8152 *tp, int budget) 1914 { 1915 unsigned long flags; 1916 struct list_head *cursor, *next, rx_queue; 1917 int ret = 0, work_done = 0; 1918 struct napi_struct *napi = &tp->napi; 1919 1920 if (!skb_queue_empty(&tp->rx_queue)) { 1921 while (work_done < budget) { 1922 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1923 struct net_device *netdev = tp->netdev; 1924 struct net_device_stats *stats = &netdev->stats; 1925 unsigned int pkt_len; 1926 1927 if (!skb) 1928 break; 1929 1930 pkt_len = skb->len; 1931 napi_gro_receive(napi, skb); 1932 work_done++; 1933 stats->rx_packets++; 1934 stats->rx_bytes += pkt_len; 1935 } 1936 } 1937 1938 if (list_empty(&tp->rx_done)) 1939 goto out1; 1940 1941 INIT_LIST_HEAD(&rx_queue); 1942 spin_lock_irqsave(&tp->rx_lock, flags); 1943 list_splice_init(&tp->rx_done, &rx_queue); 1944 spin_unlock_irqrestore(&tp->rx_lock, flags); 1945 1946 list_for_each_safe(cursor, next, &rx_queue) { 1947 struct rx_desc *rx_desc; 1948 struct rx_agg *agg; 1949 int len_used = 0; 1950 struct urb *urb; 1951 u8 *rx_data; 1952 1953 list_del_init(cursor); 1954 1955 agg = list_entry(cursor, struct rx_agg, list); 1956 urb = agg->urb; 1957 if (urb->actual_length < ETH_ZLEN) 1958 goto submit; 1959 1960 rx_desc = agg->head; 1961 rx_data = agg->head; 1962 len_used += sizeof(struct rx_desc); 1963 1964 while (urb->actual_length > len_used) { 1965 struct net_device *netdev = tp->netdev; 1966 struct net_device_stats *stats = &netdev->stats; 1967 unsigned int pkt_len; 1968 struct sk_buff *skb; 1969 1970 /* limite the skb numbers for rx_queue */ 1971 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1972 break; 1973 1974 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1975 if (pkt_len < ETH_ZLEN) 1976 break; 1977 1978 len_used += pkt_len; 1979 if (urb->actual_length < len_used) 1980 break; 1981 1982 pkt_len -= ETH_FCS_LEN; 1983 rx_data += sizeof(struct rx_desc); 1984 1985 skb = napi_alloc_skb(napi, pkt_len); 1986 if (!skb) { 1987 stats->rx_dropped++; 1988 goto find_next_rx; 1989 } 1990 1991 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1992 memcpy(skb->data, rx_data, pkt_len); 1993 skb_put(skb, pkt_len); 1994 skb->protocol = eth_type_trans(skb, netdev); 1995 rtl_rx_vlan_tag(rx_desc, skb); 1996 if (work_done < budget) { 1997 napi_gro_receive(napi, skb); 1998 work_done++; 1999 stats->rx_packets++; 2000 stats->rx_bytes += pkt_len; 2001 } else { 2002 __skb_queue_tail(&tp->rx_queue, skb); 2003 } 2004 2005 find_next_rx: 2006 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 2007 rx_desc = (struct rx_desc *)rx_data; 2008 len_used = (int)(rx_data - (u8 *)agg->head); 2009 len_used += sizeof(struct rx_desc); 2010 } 2011 2012 submit: 2013 if (!ret) { 2014 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2015 } else { 2016 urb->actual_length = 0; 2017 list_add_tail(&agg->list, next); 2018 } 2019 } 2020 2021 if (!list_empty(&rx_queue)) { 2022 spin_lock_irqsave(&tp->rx_lock, flags); 2023 list_splice_tail(&rx_queue, &tp->rx_done); 2024 spin_unlock_irqrestore(&tp->rx_lock, flags); 2025 } 2026 2027 out1: 2028 return work_done; 2029 } 2030 2031 static void tx_bottom(struct r8152 *tp) 2032 { 2033 int res; 2034 2035 do { 2036 struct tx_agg *agg; 2037 2038 if (skb_queue_empty(&tp->tx_queue)) 2039 break; 2040 2041 agg = r8152_get_tx_agg(tp); 2042 if (!agg) 2043 break; 2044 2045 res = r8152_tx_agg_fill(tp, agg); 2046 if (res) { 2047 struct net_device *netdev = tp->netdev; 2048 2049 if (res == -ENODEV) { 2050 rtl_set_unplug(tp); 2051 netif_device_detach(netdev); 2052 } else { 2053 struct net_device_stats *stats = &netdev->stats; 2054 unsigned long flags; 2055 2056 netif_warn(tp, tx_err, netdev, 2057 "failed tx_urb %d\n", res); 2058 stats->tx_dropped += agg->skb_num; 2059 2060 spin_lock_irqsave(&tp->tx_lock, flags); 2061 list_add_tail(&agg->list, &tp->tx_free); 2062 spin_unlock_irqrestore(&tp->tx_lock, flags); 2063 } 2064 } 2065 } while (res == 0); 2066 } 2067 2068 static void bottom_half(struct r8152 *tp) 2069 { 2070 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2071 return; 2072 2073 if (!test_bit(WORK_ENABLE, &tp->flags)) 2074 return; 2075 2076 /* When link down, the driver would cancel all bulks. */ 2077 /* This avoid the re-submitting bulk */ 2078 if (!netif_carrier_ok(tp->netdev)) 2079 return; 2080 2081 clear_bit(SCHEDULE_NAPI, &tp->flags); 2082 2083 tx_bottom(tp); 2084 } 2085 2086 static int r8152_poll(struct napi_struct *napi, int budget) 2087 { 2088 struct r8152 *tp = container_of(napi, struct r8152, napi); 2089 int work_done; 2090 2091 work_done = rx_bottom(tp, budget); 2092 bottom_half(tp); 2093 2094 if (work_done < budget) { 2095 if (!napi_complete_done(napi, work_done)) 2096 goto out; 2097 if (!list_empty(&tp->rx_done)) 2098 napi_schedule(napi); 2099 else if (!skb_queue_empty(&tp->tx_queue) && 2100 !list_empty(&tp->tx_free)) 2101 napi_schedule(napi); 2102 } 2103 2104 out: 2105 return work_done; 2106 } 2107 2108 static 2109 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2110 { 2111 int ret; 2112 2113 /* The rx would be stopped, so skip submitting */ 2114 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2115 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2116 return 0; 2117 2118 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2119 agg->head, agg_buf_sz, 2120 (usb_complete_t)read_bulk_callback, agg); 2121 2122 ret = usb_submit_urb(agg->urb, mem_flags); 2123 if (ret == -ENODEV) { 2124 rtl_set_unplug(tp); 2125 netif_device_detach(tp->netdev); 2126 } else if (ret) { 2127 struct urb *urb = agg->urb; 2128 unsigned long flags; 2129 2130 urb->actual_length = 0; 2131 spin_lock_irqsave(&tp->rx_lock, flags); 2132 list_add_tail(&agg->list, &tp->rx_done); 2133 spin_unlock_irqrestore(&tp->rx_lock, flags); 2134 2135 netif_err(tp, rx_err, tp->netdev, 2136 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2137 2138 napi_schedule(&tp->napi); 2139 } 2140 2141 return ret; 2142 } 2143 2144 static void rtl_drop_queued_tx(struct r8152 *tp) 2145 { 2146 struct net_device_stats *stats = &tp->netdev->stats; 2147 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2148 struct sk_buff *skb; 2149 2150 if (skb_queue_empty(tx_queue)) 2151 return; 2152 2153 __skb_queue_head_init(&skb_head); 2154 spin_lock_bh(&tx_queue->lock); 2155 skb_queue_splice_init(tx_queue, &skb_head); 2156 spin_unlock_bh(&tx_queue->lock); 2157 2158 while ((skb = __skb_dequeue(&skb_head))) { 2159 dev_kfree_skb(skb); 2160 stats->tx_dropped++; 2161 } 2162 } 2163 2164 static void rtl8152_tx_timeout(struct net_device *netdev) 2165 { 2166 struct r8152 *tp = netdev_priv(netdev); 2167 2168 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2169 2170 usb_queue_reset_device(tp->intf); 2171 } 2172 2173 static void rtl8152_set_rx_mode(struct net_device *netdev) 2174 { 2175 struct r8152 *tp = netdev_priv(netdev); 2176 2177 if (netif_carrier_ok(netdev)) { 2178 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2179 schedule_delayed_work(&tp->schedule, 0); 2180 } 2181 } 2182 2183 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2184 { 2185 struct r8152 *tp = netdev_priv(netdev); 2186 u32 mc_filter[2]; /* Multicast hash filter */ 2187 __le32 tmp[2]; 2188 u32 ocp_data; 2189 2190 netif_stop_queue(netdev); 2191 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2192 ocp_data &= ~RCR_ACPT_ALL; 2193 ocp_data |= RCR_AB | RCR_APM; 2194 2195 if (netdev->flags & IFF_PROMISC) { 2196 /* Unconditionally log net taps. */ 2197 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2198 ocp_data |= RCR_AM | RCR_AAP; 2199 mc_filter[1] = 0xffffffff; 2200 mc_filter[0] = 0xffffffff; 2201 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2202 (netdev->flags & IFF_ALLMULTI)) { 2203 /* Too many to filter perfectly -- accept all multicasts. */ 2204 ocp_data |= RCR_AM; 2205 mc_filter[1] = 0xffffffff; 2206 mc_filter[0] = 0xffffffff; 2207 } else { 2208 struct netdev_hw_addr *ha; 2209 2210 mc_filter[1] = 0; 2211 mc_filter[0] = 0; 2212 netdev_for_each_mc_addr(ha, netdev) { 2213 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2214 2215 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2216 ocp_data |= RCR_AM; 2217 } 2218 } 2219 2220 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2221 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2222 2223 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2224 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2225 netif_wake_queue(netdev); 2226 } 2227 2228 static netdev_features_t 2229 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2230 netdev_features_t features) 2231 { 2232 u32 mss = skb_shinfo(skb)->gso_size; 2233 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2234 int offset = skb_transport_offset(skb); 2235 2236 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2237 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2238 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2239 features &= ~NETIF_F_GSO_MASK; 2240 2241 return features; 2242 } 2243 2244 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2245 struct net_device *netdev) 2246 { 2247 struct r8152 *tp = netdev_priv(netdev); 2248 2249 skb_tx_timestamp(skb); 2250 2251 skb_queue_tail(&tp->tx_queue, skb); 2252 2253 if (!list_empty(&tp->tx_free)) { 2254 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2255 set_bit(SCHEDULE_NAPI, &tp->flags); 2256 schedule_delayed_work(&tp->schedule, 0); 2257 } else { 2258 usb_mark_last_busy(tp->udev); 2259 napi_schedule(&tp->napi); 2260 } 2261 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2262 netif_stop_queue(netdev); 2263 } 2264 2265 return NETDEV_TX_OK; 2266 } 2267 2268 static void r8152b_reset_packet_filter(struct r8152 *tp) 2269 { 2270 u32 ocp_data; 2271 2272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2273 ocp_data &= ~FMC_FCR_MCU_EN; 2274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2275 ocp_data |= FMC_FCR_MCU_EN; 2276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2277 } 2278 2279 static void rtl8152_nic_reset(struct r8152 *tp) 2280 { 2281 int i; 2282 2283 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2284 2285 for (i = 0; i < 1000; i++) { 2286 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2287 break; 2288 usleep_range(100, 400); 2289 } 2290 } 2291 2292 static void set_tx_qlen(struct r8152 *tp) 2293 { 2294 struct net_device *netdev = tp->netdev; 2295 2296 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2297 sizeof(struct tx_desc)); 2298 } 2299 2300 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2301 { 2302 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2303 } 2304 2305 static void rtl_set_eee_plus(struct r8152 *tp) 2306 { 2307 u32 ocp_data; 2308 u8 speed; 2309 2310 speed = rtl8152_get_speed(tp); 2311 if (speed & _10bps) { 2312 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2313 ocp_data |= EEEP_CR_EEEP_TX; 2314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2315 } else { 2316 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2317 ocp_data &= ~EEEP_CR_EEEP_TX; 2318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2319 } 2320 } 2321 2322 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2323 { 2324 u32 ocp_data; 2325 2326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2327 if (enable) 2328 ocp_data |= RXDY_GATED_EN; 2329 else 2330 ocp_data &= ~RXDY_GATED_EN; 2331 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2332 } 2333 2334 static int rtl_start_rx(struct r8152 *tp) 2335 { 2336 int i, ret = 0; 2337 2338 INIT_LIST_HEAD(&tp->rx_done); 2339 for (i = 0; i < RTL8152_MAX_RX; i++) { 2340 INIT_LIST_HEAD(&tp->rx_info[i].list); 2341 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2342 if (ret) 2343 break; 2344 } 2345 2346 if (ret && ++i < RTL8152_MAX_RX) { 2347 struct list_head rx_queue; 2348 unsigned long flags; 2349 2350 INIT_LIST_HEAD(&rx_queue); 2351 2352 do { 2353 struct rx_agg *agg = &tp->rx_info[i++]; 2354 struct urb *urb = agg->urb; 2355 2356 urb->actual_length = 0; 2357 list_add_tail(&agg->list, &rx_queue); 2358 } while (i < RTL8152_MAX_RX); 2359 2360 spin_lock_irqsave(&tp->rx_lock, flags); 2361 list_splice_tail(&rx_queue, &tp->rx_done); 2362 spin_unlock_irqrestore(&tp->rx_lock, flags); 2363 } 2364 2365 return ret; 2366 } 2367 2368 static int rtl_stop_rx(struct r8152 *tp) 2369 { 2370 int i; 2371 2372 for (i = 0; i < RTL8152_MAX_RX; i++) 2373 usb_kill_urb(tp->rx_info[i].urb); 2374 2375 while (!skb_queue_empty(&tp->rx_queue)) 2376 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2377 2378 return 0; 2379 } 2380 2381 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2382 { 2383 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2384 OWN_UPDATE | OWN_CLEAR); 2385 } 2386 2387 static int rtl_enable(struct r8152 *tp) 2388 { 2389 u32 ocp_data; 2390 2391 r8152b_reset_packet_filter(tp); 2392 2393 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2394 ocp_data |= CR_RE | CR_TE; 2395 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2396 2397 switch (tp->version) { 2398 case RTL_VER_08: 2399 case RTL_VER_09: 2400 r8153b_rx_agg_chg_indicate(tp); 2401 break; 2402 default: 2403 break; 2404 } 2405 2406 rxdy_gated_en(tp, false); 2407 2408 return 0; 2409 } 2410 2411 static int rtl8152_enable(struct r8152 *tp) 2412 { 2413 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2414 return -ENODEV; 2415 2416 set_tx_qlen(tp); 2417 rtl_set_eee_plus(tp); 2418 2419 return rtl_enable(tp); 2420 } 2421 2422 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2423 { 2424 u32 ocp_data = tp->coalesce / 8; 2425 2426 switch (tp->version) { 2427 case RTL_VER_03: 2428 case RTL_VER_04: 2429 case RTL_VER_05: 2430 case RTL_VER_06: 2431 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2432 ocp_data); 2433 break; 2434 2435 case RTL_VER_08: 2436 case RTL_VER_09: 2437 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2438 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2439 */ 2440 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2441 128 / 8); 2442 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2443 ocp_data); 2444 break; 2445 2446 default: 2447 break; 2448 } 2449 } 2450 2451 static void r8153_set_rx_early_size(struct r8152 *tp) 2452 { 2453 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2454 2455 switch (tp->version) { 2456 case RTL_VER_03: 2457 case RTL_VER_04: 2458 case RTL_VER_05: 2459 case RTL_VER_06: 2460 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2461 ocp_data / 4); 2462 break; 2463 case RTL_VER_08: 2464 case RTL_VER_09: 2465 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2466 ocp_data / 8); 2467 break; 2468 default: 2469 WARN_ON_ONCE(1); 2470 break; 2471 } 2472 } 2473 2474 static int rtl8153_enable(struct r8152 *tp) 2475 { 2476 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2477 return -ENODEV; 2478 2479 set_tx_qlen(tp); 2480 rtl_set_eee_plus(tp); 2481 r8153_set_rx_early_timeout(tp); 2482 r8153_set_rx_early_size(tp); 2483 2484 return rtl_enable(tp); 2485 } 2486 2487 static void rtl_disable(struct r8152 *tp) 2488 { 2489 u32 ocp_data; 2490 int i; 2491 2492 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2493 rtl_drop_queued_tx(tp); 2494 return; 2495 } 2496 2497 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2498 ocp_data &= ~RCR_ACPT_ALL; 2499 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2500 2501 rtl_drop_queued_tx(tp); 2502 2503 for (i = 0; i < RTL8152_MAX_TX; i++) 2504 usb_kill_urb(tp->tx_info[i].urb); 2505 2506 rxdy_gated_en(tp, true); 2507 2508 for (i = 0; i < 1000; i++) { 2509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2510 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2511 break; 2512 usleep_range(1000, 2000); 2513 } 2514 2515 for (i = 0; i < 1000; i++) { 2516 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2517 break; 2518 usleep_range(1000, 2000); 2519 } 2520 2521 rtl_stop_rx(tp); 2522 2523 rtl8152_nic_reset(tp); 2524 } 2525 2526 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2527 { 2528 u32 ocp_data; 2529 2530 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2531 if (enable) 2532 ocp_data |= POWER_CUT; 2533 else 2534 ocp_data &= ~POWER_CUT; 2535 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2536 2537 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2538 ocp_data &= ~RESUME_INDICATE; 2539 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2540 } 2541 2542 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2543 { 2544 u32 ocp_data; 2545 2546 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2547 if (enable) 2548 ocp_data |= CPCR_RX_VLAN; 2549 else 2550 ocp_data &= ~CPCR_RX_VLAN; 2551 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2552 } 2553 2554 static int rtl8152_set_features(struct net_device *dev, 2555 netdev_features_t features) 2556 { 2557 netdev_features_t changed = features ^ dev->features; 2558 struct r8152 *tp = netdev_priv(dev); 2559 int ret; 2560 2561 ret = usb_autopm_get_interface(tp->intf); 2562 if (ret < 0) 2563 goto out; 2564 2565 mutex_lock(&tp->control); 2566 2567 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2568 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2569 rtl_rx_vlan_en(tp, true); 2570 else 2571 rtl_rx_vlan_en(tp, false); 2572 } 2573 2574 mutex_unlock(&tp->control); 2575 2576 usb_autopm_put_interface(tp->intf); 2577 2578 out: 2579 return ret; 2580 } 2581 2582 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2583 2584 static u32 __rtl_get_wol(struct r8152 *tp) 2585 { 2586 u32 ocp_data; 2587 u32 wolopts = 0; 2588 2589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2590 if (ocp_data & LINK_ON_WAKE_EN) 2591 wolopts |= WAKE_PHY; 2592 2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2594 if (ocp_data & UWF_EN) 2595 wolopts |= WAKE_UCAST; 2596 if (ocp_data & BWF_EN) 2597 wolopts |= WAKE_BCAST; 2598 if (ocp_data & MWF_EN) 2599 wolopts |= WAKE_MCAST; 2600 2601 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2602 if (ocp_data & MAGIC_EN) 2603 wolopts |= WAKE_MAGIC; 2604 2605 return wolopts; 2606 } 2607 2608 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2609 { 2610 u32 ocp_data; 2611 2612 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2613 2614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2615 ocp_data &= ~LINK_ON_WAKE_EN; 2616 if (wolopts & WAKE_PHY) 2617 ocp_data |= LINK_ON_WAKE_EN; 2618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2619 2620 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2621 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2622 if (wolopts & WAKE_UCAST) 2623 ocp_data |= UWF_EN; 2624 if (wolopts & WAKE_BCAST) 2625 ocp_data |= BWF_EN; 2626 if (wolopts & WAKE_MCAST) 2627 ocp_data |= MWF_EN; 2628 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2629 2630 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2631 2632 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2633 ocp_data &= ~MAGIC_EN; 2634 if (wolopts & WAKE_MAGIC) 2635 ocp_data |= MAGIC_EN; 2636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2637 2638 if (wolopts & WAKE_ANY) 2639 device_set_wakeup_enable(&tp->udev->dev, true); 2640 else 2641 device_set_wakeup_enable(&tp->udev->dev, false); 2642 } 2643 2644 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2645 { 2646 /* MAC clock speed down */ 2647 if (enable) { 2648 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2649 ALDPS_SPDWN_RATIO); 2650 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2651 EEE_SPDWN_RATIO); 2652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2653 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2654 U1U2_SPDWN_EN | L1_SPDWN_EN); 2655 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2656 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2657 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2658 TP1000_SPDWN_EN); 2659 } else { 2660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2661 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2663 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2664 } 2665 } 2666 2667 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2668 { 2669 u8 u1u2[8]; 2670 2671 if (enable) 2672 memset(u1u2, 0xff, sizeof(u1u2)); 2673 else 2674 memset(u1u2, 0x00, sizeof(u1u2)); 2675 2676 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2677 } 2678 2679 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2680 { 2681 u32 ocp_data; 2682 2683 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2684 if (enable) 2685 ocp_data |= LPM_U1U2_EN; 2686 else 2687 ocp_data &= ~LPM_U1U2_EN; 2688 2689 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2690 } 2691 2692 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2693 { 2694 u32 ocp_data; 2695 2696 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2697 if (enable) 2698 ocp_data |= U2P3_ENABLE; 2699 else 2700 ocp_data &= ~U2P3_ENABLE; 2701 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2702 } 2703 2704 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2705 { 2706 u32 ocp_data; 2707 2708 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2709 ocp_data &= ~clear; 2710 ocp_data |= set; 2711 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2712 } 2713 2714 static void r8153b_green_en(struct r8152 *tp, bool enable) 2715 { 2716 u16 data; 2717 2718 if (enable) { 2719 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2720 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2721 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2722 } else { 2723 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2724 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2725 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2726 } 2727 2728 data = sram_read(tp, SRAM_GREEN_CFG); 2729 data |= GREEN_ETH_EN; 2730 sram_write(tp, SRAM_GREEN_CFG, data); 2731 2732 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2733 } 2734 2735 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2736 { 2737 u16 data; 2738 int i; 2739 2740 for (i = 0; i < 500; i++) { 2741 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2742 data &= PHY_STAT_MASK; 2743 if (desired) { 2744 if (data == desired) 2745 break; 2746 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2747 data == PHY_STAT_EXT_INIT) { 2748 break; 2749 } 2750 2751 msleep(20); 2752 } 2753 2754 return data; 2755 } 2756 2757 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2758 { 2759 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2760 2761 if (enable) { 2762 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2763 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2764 2765 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2766 ocp_data |= BIT(0); 2767 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2768 } else { 2769 u16 data; 2770 2771 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2772 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2773 2774 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2775 ocp_data &= ~BIT(0); 2776 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2777 2778 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2779 ocp_data &= ~PCUT_STATUS; 2780 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2781 2782 data = r8153_phy_status(tp, 0); 2783 2784 switch (data) { 2785 case PHY_STAT_PWRDN: 2786 case PHY_STAT_EXT_INIT: 2787 r8153b_green_en(tp, 2788 test_bit(GREEN_ETHERNET, &tp->flags)); 2789 2790 data = r8152_mdio_read(tp, MII_BMCR); 2791 data &= ~BMCR_PDOWN; 2792 data |= BMCR_RESET; 2793 r8152_mdio_write(tp, MII_BMCR, data); 2794 2795 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2796 /* fall through */ 2797 2798 default: 2799 if (data != PHY_STAT_LAN_ON) 2800 netif_warn(tp, link, tp->netdev, 2801 "PHY not ready"); 2802 break; 2803 } 2804 } 2805 } 2806 2807 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2808 { 2809 u32 ocp_data; 2810 2811 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2812 if (enable) 2813 ocp_data |= PWR_EN | PHASE2_EN; 2814 else 2815 ocp_data &= ~(PWR_EN | PHASE2_EN); 2816 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2817 2818 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2819 ocp_data &= ~PCUT_STATUS; 2820 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2821 } 2822 2823 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2824 { 2825 u32 ocp_data; 2826 2827 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2828 if (enable) 2829 ocp_data |= PWR_EN | PHASE2_EN; 2830 else 2831 ocp_data &= ~PWR_EN; 2832 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2833 2834 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2835 ocp_data &= ~PCUT_STATUS; 2836 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2837 } 2838 2839 static void r8153_queue_wake(struct r8152 *tp, bool enable) 2840 { 2841 u32 ocp_data; 2842 2843 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 2844 if (enable) 2845 ocp_data |= UPCOMING_RUNTIME_D3; 2846 else 2847 ocp_data &= ~UPCOMING_RUNTIME_D3; 2848 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 2849 2850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 2851 ocp_data &= ~LINK_CHG_EVENT; 2852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 2853 2854 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 2855 ocp_data &= ~LINK_CHANGE_FLAG; 2856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 2857 } 2858 2859 static bool rtl_can_wakeup(struct r8152 *tp) 2860 { 2861 struct usb_device *udev = tp->udev; 2862 2863 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2864 } 2865 2866 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2867 { 2868 if (enable) { 2869 u32 ocp_data; 2870 2871 __rtl_set_wol(tp, WAKE_ANY); 2872 2873 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2874 2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2876 ocp_data |= LINK_OFF_WAKE_EN; 2877 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2878 2879 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2880 } else { 2881 u32 ocp_data; 2882 2883 __rtl_set_wol(tp, tp->saved_wolopts); 2884 2885 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2886 2887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2888 ocp_data &= ~LINK_OFF_WAKE_EN; 2889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2890 2891 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2892 } 2893 } 2894 2895 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2896 { 2897 if (enable) { 2898 r8153_u1u2en(tp, false); 2899 r8153_u2p3en(tp, false); 2900 r8153_mac_clk_spd(tp, true); 2901 rtl_runtime_suspend_enable(tp, true); 2902 } else { 2903 rtl_runtime_suspend_enable(tp, false); 2904 r8153_mac_clk_spd(tp, false); 2905 2906 switch (tp->version) { 2907 case RTL_VER_03: 2908 case RTL_VER_04: 2909 break; 2910 case RTL_VER_05: 2911 case RTL_VER_06: 2912 default: 2913 r8153_u2p3en(tp, true); 2914 break; 2915 } 2916 2917 r8153_u1u2en(tp, true); 2918 } 2919 } 2920 2921 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2922 { 2923 if (enable) { 2924 r8153_queue_wake(tp, true); 2925 r8153b_u1u2en(tp, false); 2926 r8153_u2p3en(tp, false); 2927 rtl_runtime_suspend_enable(tp, true); 2928 r8153b_ups_en(tp, true); 2929 } else { 2930 r8153b_ups_en(tp, false); 2931 r8153_queue_wake(tp, false); 2932 rtl_runtime_suspend_enable(tp, false); 2933 r8153_u2p3en(tp, true); 2934 r8153b_u1u2en(tp, true); 2935 } 2936 } 2937 2938 static void r8153_teredo_off(struct r8152 *tp) 2939 { 2940 u32 ocp_data; 2941 2942 switch (tp->version) { 2943 case RTL_VER_01: 2944 case RTL_VER_02: 2945 case RTL_VER_03: 2946 case RTL_VER_04: 2947 case RTL_VER_05: 2948 case RTL_VER_06: 2949 case RTL_VER_07: 2950 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2951 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2952 OOB_TEREDO_EN); 2953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2954 break; 2955 2956 case RTL_VER_08: 2957 case RTL_VER_09: 2958 /* The bit 0 ~ 7 are relative with teredo settings. They are 2959 * W1C (write 1 to clear), so set all 1 to disable it. 2960 */ 2961 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2962 break; 2963 2964 default: 2965 break; 2966 } 2967 2968 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2970 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2971 } 2972 2973 static void rtl_reset_bmu(struct r8152 *tp) 2974 { 2975 u32 ocp_data; 2976 2977 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2978 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2979 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2980 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2981 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2982 } 2983 2984 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2985 { 2986 if (enable) { 2987 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2988 LINKENA | DIS_SDSAVE); 2989 } else { 2990 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2991 DIS_SDSAVE); 2992 msleep(20); 2993 } 2994 } 2995 2996 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2997 { 2998 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2999 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3000 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3001 } 3002 3003 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3004 { 3005 u16 data; 3006 3007 r8152_mmd_indirect(tp, dev, reg); 3008 data = ocp_reg_read(tp, OCP_EEE_DATA); 3009 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3010 3011 return data; 3012 } 3013 3014 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3015 { 3016 r8152_mmd_indirect(tp, dev, reg); 3017 ocp_reg_write(tp, OCP_EEE_DATA, data); 3018 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3019 } 3020 3021 static void r8152_eee_en(struct r8152 *tp, bool enable) 3022 { 3023 u16 config1, config2, config3; 3024 u32 ocp_data; 3025 3026 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3027 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3028 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3029 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3030 3031 if (enable) { 3032 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3033 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3034 config1 |= sd_rise_time(1); 3035 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3036 config3 |= fast_snr(42); 3037 } else { 3038 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3039 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3040 RX_QUIET_EN); 3041 config1 |= sd_rise_time(7); 3042 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3043 config3 |= fast_snr(511); 3044 } 3045 3046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3047 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3048 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3049 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3050 } 3051 3052 static void r8152b_enable_eee(struct r8152 *tp) 3053 { 3054 r8152_eee_en(tp, true); 3055 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3056 } 3057 3058 static void r8152b_enable_fc(struct r8152 *tp) 3059 { 3060 u16 anar; 3061 3062 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3063 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3064 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3065 } 3066 3067 static void rtl8152_disable(struct r8152 *tp) 3068 { 3069 r8152_aldps_en(tp, false); 3070 rtl_disable(tp); 3071 r8152_aldps_en(tp, true); 3072 } 3073 3074 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3075 { 3076 r8152b_enable_eee(tp); 3077 r8152_aldps_en(tp, true); 3078 r8152b_enable_fc(tp); 3079 3080 set_bit(PHY_RESET, &tp->flags); 3081 } 3082 3083 static void r8152b_exit_oob(struct r8152 *tp) 3084 { 3085 u32 ocp_data; 3086 int i; 3087 3088 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3089 ocp_data &= ~RCR_ACPT_ALL; 3090 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3091 3092 rxdy_gated_en(tp, true); 3093 r8153_teredo_off(tp); 3094 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3095 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3096 3097 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3098 ocp_data &= ~NOW_IS_OOB; 3099 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3100 3101 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3102 ocp_data &= ~MCU_BORW_EN; 3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3104 3105 for (i = 0; i < 1000; i++) { 3106 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3107 if (ocp_data & LINK_LIST_READY) 3108 break; 3109 usleep_range(1000, 2000); 3110 } 3111 3112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3113 ocp_data |= RE_INIT_LL; 3114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3115 3116 for (i = 0; i < 1000; i++) { 3117 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3118 if (ocp_data & LINK_LIST_READY) 3119 break; 3120 usleep_range(1000, 2000); 3121 } 3122 3123 rtl8152_nic_reset(tp); 3124 3125 /* rx share fifo credit full threshold */ 3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3127 3128 if (tp->udev->speed == USB_SPEED_FULL || 3129 tp->udev->speed == USB_SPEED_LOW) { 3130 /* rx share fifo credit near full threshold */ 3131 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3132 RXFIFO_THR2_FULL); 3133 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3134 RXFIFO_THR3_FULL); 3135 } else { 3136 /* rx share fifo credit near full threshold */ 3137 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3138 RXFIFO_THR2_HIGH); 3139 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3140 RXFIFO_THR3_HIGH); 3141 } 3142 3143 /* TX share fifo free credit full threshold */ 3144 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3145 3146 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3147 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3148 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3149 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3150 3151 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3152 3153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3154 3155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3156 ocp_data |= TCR0_AUTO_FIFO; 3157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3158 } 3159 3160 static void r8152b_enter_oob(struct r8152 *tp) 3161 { 3162 u32 ocp_data; 3163 int i; 3164 3165 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3166 ocp_data &= ~NOW_IS_OOB; 3167 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3168 3169 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3170 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3171 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3172 3173 rtl_disable(tp); 3174 3175 for (i = 0; i < 1000; i++) { 3176 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3177 if (ocp_data & LINK_LIST_READY) 3178 break; 3179 usleep_range(1000, 2000); 3180 } 3181 3182 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3183 ocp_data |= RE_INIT_LL; 3184 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3185 3186 for (i = 0; i < 1000; i++) { 3187 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3188 if (ocp_data & LINK_LIST_READY) 3189 break; 3190 usleep_range(1000, 2000); 3191 } 3192 3193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3194 3195 rtl_rx_vlan_en(tp, true); 3196 3197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3198 ocp_data |= ALDPS_PROXY_MODE; 3199 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3200 3201 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3202 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3203 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3204 3205 rxdy_gated_en(tp, false); 3206 3207 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3208 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3209 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3210 } 3211 3212 static int r8153_patch_request(struct r8152 *tp, bool request) 3213 { 3214 u16 data; 3215 int i; 3216 3217 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3218 if (request) 3219 data |= PATCH_REQUEST; 3220 else 3221 data &= ~PATCH_REQUEST; 3222 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3223 3224 for (i = 0; request && i < 5000; i++) { 3225 usleep_range(1000, 2000); 3226 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3227 break; 3228 } 3229 3230 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3231 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3232 r8153_patch_request(tp, false); 3233 return -ETIME; 3234 } else { 3235 return 0; 3236 } 3237 } 3238 3239 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3240 { 3241 u16 data; 3242 3243 data = ocp_reg_read(tp, OCP_POWER_CFG); 3244 if (enable) { 3245 data |= EN_ALDPS; 3246 ocp_reg_write(tp, OCP_POWER_CFG, data); 3247 } else { 3248 int i; 3249 3250 data &= ~EN_ALDPS; 3251 ocp_reg_write(tp, OCP_POWER_CFG, data); 3252 for (i = 0; i < 20; i++) { 3253 usleep_range(1000, 2000); 3254 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3255 break; 3256 } 3257 } 3258 } 3259 3260 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3261 { 3262 r8153_aldps_en(tp, enable); 3263 3264 if (enable) 3265 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3266 else 3267 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3268 } 3269 3270 static void r8153_eee_en(struct r8152 *tp, bool enable) 3271 { 3272 u32 ocp_data; 3273 u16 config; 3274 3275 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3276 config = ocp_reg_read(tp, OCP_EEE_CFG); 3277 3278 if (enable) { 3279 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3280 config |= EEE10_EN; 3281 } else { 3282 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3283 config &= ~EEE10_EN; 3284 } 3285 3286 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3287 ocp_reg_write(tp, OCP_EEE_CFG, config); 3288 } 3289 3290 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3291 { 3292 r8153_eee_en(tp, enable); 3293 3294 if (enable) 3295 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3296 else 3297 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3298 } 3299 3300 static void r8153b_enable_fc(struct r8152 *tp) 3301 { 3302 r8152b_enable_fc(tp); 3303 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3304 } 3305 3306 static void r8153_hw_phy_cfg(struct r8152 *tp) 3307 { 3308 u32 ocp_data; 3309 u16 data; 3310 3311 /* disable ALDPS before updating the PHY parameters */ 3312 r8153_aldps_en(tp, false); 3313 3314 /* disable EEE before updating the PHY parameters */ 3315 r8153_eee_en(tp, false); 3316 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3317 3318 if (tp->version == RTL_VER_03) { 3319 data = ocp_reg_read(tp, OCP_EEE_CFG); 3320 data &= ~CTAP_SHORT_EN; 3321 ocp_reg_write(tp, OCP_EEE_CFG, data); 3322 } 3323 3324 data = ocp_reg_read(tp, OCP_POWER_CFG); 3325 data |= EEE_CLKDIV_EN; 3326 ocp_reg_write(tp, OCP_POWER_CFG, data); 3327 3328 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3329 data |= EN_10M_BGOFF; 3330 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3331 data = ocp_reg_read(tp, OCP_POWER_CFG); 3332 data |= EN_10M_PLLOFF; 3333 ocp_reg_write(tp, OCP_POWER_CFG, data); 3334 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3335 3336 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3337 ocp_data |= PFM_PWM_SWITCH; 3338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3339 3340 /* Enable LPF corner auto tune */ 3341 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3342 3343 /* Adjust 10M Amplitude */ 3344 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3345 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3346 3347 r8153_eee_en(tp, true); 3348 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3349 3350 r8153_aldps_en(tp, true); 3351 r8152b_enable_fc(tp); 3352 3353 switch (tp->version) { 3354 case RTL_VER_03: 3355 case RTL_VER_04: 3356 break; 3357 case RTL_VER_05: 3358 case RTL_VER_06: 3359 default: 3360 r8153_u2p3en(tp, true); 3361 break; 3362 } 3363 3364 set_bit(PHY_RESET, &tp->flags); 3365 } 3366 3367 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3368 { 3369 u32 ocp_data; 3370 3371 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3373 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3374 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3375 3376 return ocp_data; 3377 } 3378 3379 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3380 { 3381 u32 ocp_data, ups_flags = 0; 3382 u16 data; 3383 3384 /* disable ALDPS before updating the PHY parameters */ 3385 r8153b_aldps_en(tp, false); 3386 3387 /* disable EEE before updating the PHY parameters */ 3388 r8153b_eee_en(tp, false); 3389 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3390 3391 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3392 3393 data = sram_read(tp, SRAM_GREEN_CFG); 3394 data |= R_TUNE_EN; 3395 sram_write(tp, SRAM_GREEN_CFG, data); 3396 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3397 data |= PGA_RETURN_EN; 3398 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3399 3400 /* ADC Bias Calibration: 3401 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3402 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3403 * ADC ioffset. 3404 */ 3405 ocp_data = r8152_efuse_read(tp, 0x7d); 3406 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3407 if (data != 0xffff) 3408 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3409 3410 /* ups mode tx-link-pulse timing adjustment: 3411 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3412 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3413 */ 3414 ocp_data = ocp_reg_read(tp, 0xc426); 3415 ocp_data &= 0x3fff; 3416 if (ocp_data) { 3417 u32 swr_cnt_1ms_ini; 3418 3419 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3420 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3421 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3422 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3423 } 3424 3425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3426 ocp_data |= PFM_PWM_SWITCH; 3427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3428 3429 /* Advnace EEE */ 3430 if (!r8153_patch_request(tp, true)) { 3431 data = ocp_reg_read(tp, OCP_POWER_CFG); 3432 data |= EEE_CLKDIV_EN; 3433 ocp_reg_write(tp, OCP_POWER_CFG, data); 3434 3435 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3436 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3437 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3438 3439 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3440 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3441 3442 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3443 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3444 UPS_FLAGS_EEE_PLLOFF_GIGA; 3445 3446 r8153_patch_request(tp, false); 3447 } 3448 3449 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3450 3451 r8153b_eee_en(tp, true); 3452 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3453 3454 r8153b_aldps_en(tp, true); 3455 r8153b_enable_fc(tp); 3456 r8153_u2p3en(tp, true); 3457 3458 set_bit(PHY_RESET, &tp->flags); 3459 } 3460 3461 static void r8153_first_init(struct r8152 *tp) 3462 { 3463 u32 ocp_data; 3464 int i; 3465 3466 r8153_mac_clk_spd(tp, false); 3467 rxdy_gated_en(tp, true); 3468 r8153_teredo_off(tp); 3469 3470 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3471 ocp_data &= ~RCR_ACPT_ALL; 3472 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3473 3474 rtl8152_nic_reset(tp); 3475 rtl_reset_bmu(tp); 3476 3477 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3478 ocp_data &= ~NOW_IS_OOB; 3479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3480 3481 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3482 ocp_data &= ~MCU_BORW_EN; 3483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3484 3485 for (i = 0; i < 1000; i++) { 3486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3487 if (ocp_data & LINK_LIST_READY) 3488 break; 3489 usleep_range(1000, 2000); 3490 } 3491 3492 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3493 ocp_data |= RE_INIT_LL; 3494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3495 3496 for (i = 0; i < 1000; i++) { 3497 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3498 if (ocp_data & LINK_LIST_READY) 3499 break; 3500 usleep_range(1000, 2000); 3501 } 3502 3503 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3504 3505 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3507 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3508 3509 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3510 ocp_data |= TCR0_AUTO_FIFO; 3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3512 3513 rtl8152_nic_reset(tp); 3514 3515 /* rx share fifo credit full threshold */ 3516 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3517 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3519 /* TX share fifo free credit full threshold */ 3520 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3521 } 3522 3523 static void r8153_enter_oob(struct r8152 *tp) 3524 { 3525 u32 ocp_data; 3526 int i; 3527 3528 r8153_mac_clk_spd(tp, true); 3529 3530 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3531 ocp_data &= ~NOW_IS_OOB; 3532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3533 3534 rtl_disable(tp); 3535 rtl_reset_bmu(tp); 3536 3537 for (i = 0; i < 1000; i++) { 3538 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3539 if (ocp_data & LINK_LIST_READY) 3540 break; 3541 usleep_range(1000, 2000); 3542 } 3543 3544 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3545 ocp_data |= RE_INIT_LL; 3546 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3547 3548 for (i = 0; i < 1000; i++) { 3549 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3550 if (ocp_data & LINK_LIST_READY) 3551 break; 3552 usleep_range(1000, 2000); 3553 } 3554 3555 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3557 3558 switch (tp->version) { 3559 case RTL_VER_03: 3560 case RTL_VER_04: 3561 case RTL_VER_05: 3562 case RTL_VER_06: 3563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3564 ocp_data &= ~TEREDO_WAKE_MASK; 3565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3566 break; 3567 3568 case RTL_VER_08: 3569 case RTL_VER_09: 3570 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3571 * type. Set it to zero. bits[7:0] are the W1C bits about 3572 * the events. Set them to all 1 to clear them. 3573 */ 3574 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3575 break; 3576 3577 default: 3578 break; 3579 } 3580 3581 rtl_rx_vlan_en(tp, true); 3582 3583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3584 ocp_data |= ALDPS_PROXY_MODE; 3585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3586 3587 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3588 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3589 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3590 3591 rxdy_gated_en(tp, false); 3592 3593 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3594 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3596 } 3597 3598 static void rtl8153_disable(struct r8152 *tp) 3599 { 3600 r8153_aldps_en(tp, false); 3601 rtl_disable(tp); 3602 rtl_reset_bmu(tp); 3603 r8153_aldps_en(tp, true); 3604 } 3605 3606 static void rtl8153b_disable(struct r8152 *tp) 3607 { 3608 r8153b_aldps_en(tp, false); 3609 rtl_disable(tp); 3610 rtl_reset_bmu(tp); 3611 r8153b_aldps_en(tp, true); 3612 } 3613 3614 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3615 { 3616 u16 bmcr, anar, gbcr; 3617 enum spd_duplex speed_duplex; 3618 int ret = 0; 3619 3620 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3621 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3622 ADVERTISE_100HALF | ADVERTISE_100FULL); 3623 if (tp->mii.supports_gmii) { 3624 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3625 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3626 } else { 3627 gbcr = 0; 3628 } 3629 3630 if (autoneg == AUTONEG_DISABLE) { 3631 if (speed == SPEED_10) { 3632 bmcr = 0; 3633 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3634 speed_duplex = FORCE_10M_HALF; 3635 } else if (speed == SPEED_100) { 3636 bmcr = BMCR_SPEED100; 3637 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3638 speed_duplex = FORCE_100M_HALF; 3639 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3640 bmcr = BMCR_SPEED1000; 3641 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3642 speed_duplex = NWAY_1000M_FULL; 3643 } else { 3644 ret = -EINVAL; 3645 goto out; 3646 } 3647 3648 if (duplex == DUPLEX_FULL) { 3649 bmcr |= BMCR_FULLDPLX; 3650 if (speed != SPEED_1000) 3651 speed_duplex++; 3652 } 3653 } else { 3654 if (speed == SPEED_10) { 3655 if (duplex == DUPLEX_FULL) { 3656 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3657 speed_duplex = NWAY_10M_FULL; 3658 } else { 3659 anar |= ADVERTISE_10HALF; 3660 speed_duplex = NWAY_10M_HALF; 3661 } 3662 } else if (speed == SPEED_100) { 3663 if (duplex == DUPLEX_FULL) { 3664 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3665 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3666 speed_duplex = NWAY_100M_FULL; 3667 } else { 3668 anar |= ADVERTISE_10HALF; 3669 anar |= ADVERTISE_100HALF; 3670 speed_duplex = NWAY_100M_HALF; 3671 } 3672 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3673 if (duplex == DUPLEX_FULL) { 3674 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3675 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3676 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3677 } else { 3678 anar |= ADVERTISE_10HALF; 3679 anar |= ADVERTISE_100HALF; 3680 gbcr |= ADVERTISE_1000HALF; 3681 } 3682 speed_duplex = NWAY_1000M_FULL; 3683 } else { 3684 ret = -EINVAL; 3685 goto out; 3686 } 3687 3688 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3689 } 3690 3691 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3692 bmcr |= BMCR_RESET; 3693 3694 if (tp->mii.supports_gmii) 3695 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3696 3697 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3698 r8152_mdio_write(tp, MII_BMCR, bmcr); 3699 3700 switch (tp->version) { 3701 case RTL_VER_08: 3702 case RTL_VER_09: 3703 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3704 UPS_FLAGS_SPEED_MASK); 3705 break; 3706 3707 default: 3708 break; 3709 } 3710 3711 if (bmcr & BMCR_RESET) { 3712 int i; 3713 3714 for (i = 0; i < 50; i++) { 3715 msleep(20); 3716 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3717 break; 3718 } 3719 } 3720 3721 out: 3722 return ret; 3723 } 3724 3725 static void rtl8152_up(struct r8152 *tp) 3726 { 3727 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3728 return; 3729 3730 r8152_aldps_en(tp, false); 3731 r8152b_exit_oob(tp); 3732 r8152_aldps_en(tp, true); 3733 } 3734 3735 static void rtl8152_down(struct r8152 *tp) 3736 { 3737 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3738 rtl_drop_queued_tx(tp); 3739 return; 3740 } 3741 3742 r8152_power_cut_en(tp, false); 3743 r8152_aldps_en(tp, false); 3744 r8152b_enter_oob(tp); 3745 r8152_aldps_en(tp, true); 3746 } 3747 3748 static void rtl8153_up(struct r8152 *tp) 3749 { 3750 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3751 return; 3752 3753 r8153_u1u2en(tp, false); 3754 r8153_u2p3en(tp, false); 3755 r8153_aldps_en(tp, false); 3756 r8153_first_init(tp); 3757 r8153_aldps_en(tp, true); 3758 3759 switch (tp->version) { 3760 case RTL_VER_03: 3761 case RTL_VER_04: 3762 break; 3763 case RTL_VER_05: 3764 case RTL_VER_06: 3765 default: 3766 r8153_u2p3en(tp, true); 3767 break; 3768 } 3769 3770 r8153_u1u2en(tp, true); 3771 } 3772 3773 static void rtl8153_down(struct r8152 *tp) 3774 { 3775 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3776 rtl_drop_queued_tx(tp); 3777 return; 3778 } 3779 3780 r8153_u1u2en(tp, false); 3781 r8153_u2p3en(tp, false); 3782 r8153_power_cut_en(tp, false); 3783 r8153_aldps_en(tp, false); 3784 r8153_enter_oob(tp); 3785 r8153_aldps_en(tp, true); 3786 } 3787 3788 static void rtl8153b_up(struct r8152 *tp) 3789 { 3790 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3791 return; 3792 3793 r8153b_u1u2en(tp, false); 3794 r8153_u2p3en(tp, false); 3795 r8153b_aldps_en(tp, false); 3796 3797 r8153_first_init(tp); 3798 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3799 3800 r8153b_aldps_en(tp, true); 3801 r8153_u2p3en(tp, true); 3802 r8153b_u1u2en(tp, true); 3803 } 3804 3805 static void rtl8153b_down(struct r8152 *tp) 3806 { 3807 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3808 rtl_drop_queued_tx(tp); 3809 return; 3810 } 3811 3812 r8153b_u1u2en(tp, false); 3813 r8153_u2p3en(tp, false); 3814 r8153b_power_cut_en(tp, false); 3815 r8153b_aldps_en(tp, false); 3816 r8153_enter_oob(tp); 3817 r8153b_aldps_en(tp, true); 3818 } 3819 3820 static bool rtl8152_in_nway(struct r8152 *tp) 3821 { 3822 u16 nway_state; 3823 3824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3825 tp->ocp_base = 0x2000; 3826 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3827 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3828 3829 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3830 if (nway_state & 0xc000) 3831 return false; 3832 else 3833 return true; 3834 } 3835 3836 static bool rtl8153_in_nway(struct r8152 *tp) 3837 { 3838 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3839 3840 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3841 return false; 3842 else 3843 return true; 3844 } 3845 3846 static void set_carrier(struct r8152 *tp) 3847 { 3848 struct net_device *netdev = tp->netdev; 3849 struct napi_struct *napi = &tp->napi; 3850 u8 speed; 3851 3852 speed = rtl8152_get_speed(tp); 3853 3854 if (speed & LINK_STATUS) { 3855 if (!netif_carrier_ok(netdev)) { 3856 tp->rtl_ops.enable(tp); 3857 netif_stop_queue(netdev); 3858 napi_disable(napi); 3859 netif_carrier_on(netdev); 3860 rtl_start_rx(tp); 3861 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 3862 _rtl8152_set_rx_mode(netdev); 3863 napi_enable(&tp->napi); 3864 netif_wake_queue(netdev); 3865 netif_info(tp, link, netdev, "carrier on\n"); 3866 } else if (netif_queue_stopped(netdev) && 3867 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3868 netif_wake_queue(netdev); 3869 } 3870 } else { 3871 if (netif_carrier_ok(netdev)) { 3872 netif_carrier_off(netdev); 3873 napi_disable(napi); 3874 tp->rtl_ops.disable(tp); 3875 napi_enable(napi); 3876 netif_info(tp, link, netdev, "carrier off\n"); 3877 } 3878 } 3879 } 3880 3881 static void rtl_work_func_t(struct work_struct *work) 3882 { 3883 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3884 3885 /* If the device is unplugged or !netif_running(), the workqueue 3886 * doesn't need to wake the device, and could return directly. 3887 */ 3888 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3889 return; 3890 3891 if (usb_autopm_get_interface(tp->intf) < 0) 3892 return; 3893 3894 if (!test_bit(WORK_ENABLE, &tp->flags)) 3895 goto out1; 3896 3897 if (!mutex_trylock(&tp->control)) { 3898 schedule_delayed_work(&tp->schedule, 0); 3899 goto out1; 3900 } 3901 3902 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3903 set_carrier(tp); 3904 3905 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3906 _rtl8152_set_rx_mode(tp->netdev); 3907 3908 /* don't schedule napi before linking */ 3909 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3910 netif_carrier_ok(tp->netdev)) 3911 napi_schedule(&tp->napi); 3912 3913 mutex_unlock(&tp->control); 3914 3915 out1: 3916 usb_autopm_put_interface(tp->intf); 3917 } 3918 3919 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3920 { 3921 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3922 3923 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3924 return; 3925 3926 if (usb_autopm_get_interface(tp->intf) < 0) 3927 return; 3928 3929 mutex_lock(&tp->control); 3930 3931 tp->rtl_ops.hw_phy_cfg(tp); 3932 3933 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3934 3935 mutex_unlock(&tp->control); 3936 3937 usb_autopm_put_interface(tp->intf); 3938 } 3939 3940 #ifdef CONFIG_PM_SLEEP 3941 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3942 void *data) 3943 { 3944 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3945 3946 switch (action) { 3947 case PM_HIBERNATION_PREPARE: 3948 case PM_SUSPEND_PREPARE: 3949 usb_autopm_get_interface(tp->intf); 3950 break; 3951 3952 case PM_POST_HIBERNATION: 3953 case PM_POST_SUSPEND: 3954 usb_autopm_put_interface(tp->intf); 3955 break; 3956 3957 case PM_POST_RESTORE: 3958 case PM_RESTORE_PREPARE: 3959 default: 3960 break; 3961 } 3962 3963 return NOTIFY_DONE; 3964 } 3965 #endif 3966 3967 static int rtl8152_open(struct net_device *netdev) 3968 { 3969 struct r8152 *tp = netdev_priv(netdev); 3970 int res = 0; 3971 3972 res = alloc_all_mem(tp); 3973 if (res) 3974 goto out; 3975 3976 res = usb_autopm_get_interface(tp->intf); 3977 if (res < 0) 3978 goto out_free; 3979 3980 mutex_lock(&tp->control); 3981 3982 tp->rtl_ops.up(tp); 3983 3984 netif_carrier_off(netdev); 3985 netif_start_queue(netdev); 3986 set_bit(WORK_ENABLE, &tp->flags); 3987 3988 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3989 if (res) { 3990 if (res == -ENODEV) 3991 netif_device_detach(tp->netdev); 3992 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3993 res); 3994 goto out_unlock; 3995 } 3996 napi_enable(&tp->napi); 3997 3998 mutex_unlock(&tp->control); 3999 4000 usb_autopm_put_interface(tp->intf); 4001 #ifdef CONFIG_PM_SLEEP 4002 tp->pm_notifier.notifier_call = rtl_notifier; 4003 register_pm_notifier(&tp->pm_notifier); 4004 #endif 4005 return 0; 4006 4007 out_unlock: 4008 mutex_unlock(&tp->control); 4009 usb_autopm_put_interface(tp->intf); 4010 out_free: 4011 free_all_mem(tp); 4012 out: 4013 return res; 4014 } 4015 4016 static int rtl8152_close(struct net_device *netdev) 4017 { 4018 struct r8152 *tp = netdev_priv(netdev); 4019 int res = 0; 4020 4021 #ifdef CONFIG_PM_SLEEP 4022 unregister_pm_notifier(&tp->pm_notifier); 4023 #endif 4024 if (!test_bit(RTL8152_UNPLUG, &tp->flags)) 4025 napi_disable(&tp->napi); 4026 clear_bit(WORK_ENABLE, &tp->flags); 4027 usb_kill_urb(tp->intr_urb); 4028 cancel_delayed_work_sync(&tp->schedule); 4029 netif_stop_queue(netdev); 4030 4031 res = usb_autopm_get_interface(tp->intf); 4032 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 4033 rtl_drop_queued_tx(tp); 4034 rtl_stop_rx(tp); 4035 } else { 4036 mutex_lock(&tp->control); 4037 4038 tp->rtl_ops.down(tp); 4039 4040 mutex_unlock(&tp->control); 4041 4042 usb_autopm_put_interface(tp->intf); 4043 } 4044 4045 free_all_mem(tp); 4046 4047 return res; 4048 } 4049 4050 static void rtl_tally_reset(struct r8152 *tp) 4051 { 4052 u32 ocp_data; 4053 4054 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4055 ocp_data |= TALLY_RESET; 4056 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4057 } 4058 4059 static void r8152b_init(struct r8152 *tp) 4060 { 4061 u32 ocp_data; 4062 u16 data; 4063 4064 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4065 return; 4066 4067 data = r8152_mdio_read(tp, MII_BMCR); 4068 if (data & BMCR_PDOWN) { 4069 data &= ~BMCR_PDOWN; 4070 r8152_mdio_write(tp, MII_BMCR, data); 4071 } 4072 4073 r8152_aldps_en(tp, false); 4074 4075 if (tp->version == RTL_VER_01) { 4076 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4077 ocp_data &= ~LED_MODE_MASK; 4078 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4079 } 4080 4081 r8152_power_cut_en(tp, false); 4082 4083 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4084 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4085 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4086 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4087 ocp_data &= ~MCU_CLK_RATIO_MASK; 4088 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4090 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4091 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4092 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4093 4094 rtl_tally_reset(tp); 4095 4096 /* enable rx aggregation */ 4097 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4098 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4099 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4100 } 4101 4102 static void r8153_init(struct r8152 *tp) 4103 { 4104 u32 ocp_data; 4105 u16 data; 4106 int i; 4107 4108 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4109 return; 4110 4111 r8153_u1u2en(tp, false); 4112 4113 for (i = 0; i < 500; i++) { 4114 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4115 AUTOLOAD_DONE) 4116 break; 4117 msleep(20); 4118 } 4119 4120 data = r8153_phy_status(tp, 0); 4121 4122 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4123 tp->version == RTL_VER_05) 4124 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4125 4126 data = r8152_mdio_read(tp, MII_BMCR); 4127 if (data & BMCR_PDOWN) { 4128 data &= ~BMCR_PDOWN; 4129 r8152_mdio_write(tp, MII_BMCR, data); 4130 } 4131 4132 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4133 4134 r8153_u2p3en(tp, false); 4135 4136 if (tp->version == RTL_VER_04) { 4137 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4138 ocp_data &= ~pwd_dn_scale_mask; 4139 ocp_data |= pwd_dn_scale(96); 4140 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4141 4142 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4143 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4144 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4145 } else if (tp->version == RTL_VER_05) { 4146 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4147 ocp_data &= ~ECM_ALDPS; 4148 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4149 4150 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4151 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4152 ocp_data &= ~DYNAMIC_BURST; 4153 else 4154 ocp_data |= DYNAMIC_BURST; 4155 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4156 } else if (tp->version == RTL_VER_06) { 4157 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4158 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4159 ocp_data &= ~DYNAMIC_BURST; 4160 else 4161 ocp_data |= DYNAMIC_BURST; 4162 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4163 } 4164 4165 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4166 ocp_data |= EP4_FULL_FC; 4167 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4168 4169 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4170 ocp_data &= ~TIMER11_EN; 4171 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4172 4173 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4174 ocp_data &= ~LED_MODE_MASK; 4175 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4176 4177 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4178 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4179 ocp_data |= LPM_TIMER_500MS; 4180 else 4181 ocp_data |= LPM_TIMER_500US; 4182 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4183 4184 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4185 ocp_data &= ~SEN_VAL_MASK; 4186 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4187 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4188 4189 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4190 4191 r8153_power_cut_en(tp, false); 4192 r8153_u1u2en(tp, true); 4193 r8153_mac_clk_spd(tp, false); 4194 usb_enable_lpm(tp->udev); 4195 4196 /* rx aggregation */ 4197 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4198 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4199 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4200 ocp_data |= RX_AGG_DISABLE; 4201 4202 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4203 4204 rtl_tally_reset(tp); 4205 4206 switch (tp->udev->speed) { 4207 case USB_SPEED_SUPER: 4208 case USB_SPEED_SUPER_PLUS: 4209 tp->coalesce = COALESCE_SUPER; 4210 break; 4211 case USB_SPEED_HIGH: 4212 tp->coalesce = COALESCE_HIGH; 4213 break; 4214 default: 4215 tp->coalesce = COALESCE_SLOW; 4216 break; 4217 } 4218 } 4219 4220 static void r8153b_init(struct r8152 *tp) 4221 { 4222 u32 ocp_data; 4223 u16 data; 4224 int i; 4225 4226 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4227 return; 4228 4229 r8153b_u1u2en(tp, false); 4230 4231 for (i = 0; i < 500; i++) { 4232 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4233 AUTOLOAD_DONE) 4234 break; 4235 msleep(20); 4236 } 4237 4238 data = r8153_phy_status(tp, 0); 4239 4240 data = r8152_mdio_read(tp, MII_BMCR); 4241 if (data & BMCR_PDOWN) { 4242 data &= ~BMCR_PDOWN; 4243 r8152_mdio_write(tp, MII_BMCR, data); 4244 } 4245 4246 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4247 4248 r8153_u2p3en(tp, false); 4249 4250 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4251 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4252 4253 /* U1/U2/L1 idle timer. 500 us */ 4254 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4255 4256 r8153b_power_cut_en(tp, false); 4257 r8153b_ups_en(tp, false); 4258 r8153_queue_wake(tp, false); 4259 rtl_runtime_suspend_enable(tp, false); 4260 r8153b_u1u2en(tp, true); 4261 usb_enable_lpm(tp->udev); 4262 4263 /* MAC clock speed down */ 4264 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4265 ocp_data |= MAC_CLK_SPDWN_EN; 4266 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4267 4268 set_bit(GREEN_ETHERNET, &tp->flags); 4269 4270 /* rx aggregation */ 4271 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4272 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4273 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4274 4275 rtl_tally_reset(tp); 4276 4277 tp->coalesce = 15000; /* 15 us */ 4278 } 4279 4280 static int rtl8152_pre_reset(struct usb_interface *intf) 4281 { 4282 struct r8152 *tp = usb_get_intfdata(intf); 4283 struct net_device *netdev; 4284 4285 if (!tp) 4286 return 0; 4287 4288 netdev = tp->netdev; 4289 if (!netif_running(netdev)) 4290 return 0; 4291 4292 netif_stop_queue(netdev); 4293 napi_disable(&tp->napi); 4294 clear_bit(WORK_ENABLE, &tp->flags); 4295 usb_kill_urb(tp->intr_urb); 4296 cancel_delayed_work_sync(&tp->schedule); 4297 if (netif_carrier_ok(netdev)) { 4298 mutex_lock(&tp->control); 4299 tp->rtl_ops.disable(tp); 4300 mutex_unlock(&tp->control); 4301 } 4302 4303 return 0; 4304 } 4305 4306 static int rtl8152_post_reset(struct usb_interface *intf) 4307 { 4308 struct r8152 *tp = usb_get_intfdata(intf); 4309 struct net_device *netdev; 4310 struct sockaddr sa; 4311 4312 if (!tp) 4313 return 0; 4314 4315 /* reset the MAC adddress in case of policy change */ 4316 if (determine_ethernet_addr(tp, &sa) >= 0) { 4317 rtnl_lock(); 4318 dev_set_mac_address (tp->netdev, &sa, NULL); 4319 rtnl_unlock(); 4320 } 4321 4322 netdev = tp->netdev; 4323 if (!netif_running(netdev)) 4324 return 0; 4325 4326 set_bit(WORK_ENABLE, &tp->flags); 4327 if (netif_carrier_ok(netdev)) { 4328 mutex_lock(&tp->control); 4329 tp->rtl_ops.enable(tp); 4330 rtl_start_rx(tp); 4331 _rtl8152_set_rx_mode(netdev); 4332 mutex_unlock(&tp->control); 4333 } 4334 4335 napi_enable(&tp->napi); 4336 netif_wake_queue(netdev); 4337 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4338 4339 if (!list_empty(&tp->rx_done)) 4340 napi_schedule(&tp->napi); 4341 4342 return 0; 4343 } 4344 4345 static bool delay_autosuspend(struct r8152 *tp) 4346 { 4347 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4348 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4349 4350 /* This means a linking change occurs and the driver doesn't detect it, 4351 * yet. If the driver has disabled tx/rx and hw is linking on, the 4352 * device wouldn't wake up by receiving any packet. 4353 */ 4354 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4355 return true; 4356 4357 /* If the linking down is occurred by nway, the device may miss the 4358 * linking change event. And it wouldn't wake when linking on. 4359 */ 4360 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4361 return true; 4362 else if (!skb_queue_empty(&tp->tx_queue)) 4363 return true; 4364 else 4365 return false; 4366 } 4367 4368 static int rtl8152_runtime_resume(struct r8152 *tp) 4369 { 4370 struct net_device *netdev = tp->netdev; 4371 4372 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4373 struct napi_struct *napi = &tp->napi; 4374 4375 tp->rtl_ops.autosuspend_en(tp, false); 4376 napi_disable(napi); 4377 set_bit(WORK_ENABLE, &tp->flags); 4378 4379 if (netif_carrier_ok(netdev)) { 4380 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4381 rtl_start_rx(tp); 4382 } else { 4383 netif_carrier_off(netdev); 4384 tp->rtl_ops.disable(tp); 4385 netif_info(tp, link, netdev, "linking down\n"); 4386 } 4387 } 4388 4389 napi_enable(napi); 4390 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4391 smp_mb__after_atomic(); 4392 4393 if (!list_empty(&tp->rx_done)) 4394 napi_schedule(&tp->napi); 4395 4396 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4397 } else { 4398 if (netdev->flags & IFF_UP) 4399 tp->rtl_ops.autosuspend_en(tp, false); 4400 4401 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4402 } 4403 4404 return 0; 4405 } 4406 4407 static int rtl8152_system_resume(struct r8152 *tp) 4408 { 4409 struct net_device *netdev = tp->netdev; 4410 4411 netif_device_attach(netdev); 4412 4413 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4414 tp->rtl_ops.up(tp); 4415 netif_carrier_off(netdev); 4416 set_bit(WORK_ENABLE, &tp->flags); 4417 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4418 } 4419 4420 return 0; 4421 } 4422 4423 static int rtl8152_runtime_suspend(struct r8152 *tp) 4424 { 4425 struct net_device *netdev = tp->netdev; 4426 int ret = 0; 4427 4428 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4429 smp_mb__after_atomic(); 4430 4431 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4432 u32 rcr = 0; 4433 4434 if (netif_carrier_ok(netdev)) { 4435 u32 ocp_data; 4436 4437 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4438 ocp_data = rcr & ~RCR_ACPT_ALL; 4439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4440 rxdy_gated_en(tp, true); 4441 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4442 PLA_OOB_CTRL); 4443 if (!(ocp_data & RXFIFO_EMPTY)) { 4444 rxdy_gated_en(tp, false); 4445 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4446 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4447 smp_mb__after_atomic(); 4448 ret = -EBUSY; 4449 goto out1; 4450 } 4451 } 4452 4453 clear_bit(WORK_ENABLE, &tp->flags); 4454 usb_kill_urb(tp->intr_urb); 4455 4456 tp->rtl_ops.autosuspend_en(tp, true); 4457 4458 if (netif_carrier_ok(netdev)) { 4459 struct napi_struct *napi = &tp->napi; 4460 4461 napi_disable(napi); 4462 rtl_stop_rx(tp); 4463 rxdy_gated_en(tp, false); 4464 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4465 napi_enable(napi); 4466 } 4467 4468 if (delay_autosuspend(tp)) { 4469 rtl8152_runtime_resume(tp); 4470 ret = -EBUSY; 4471 } 4472 } 4473 4474 out1: 4475 return ret; 4476 } 4477 4478 static int rtl8152_system_suspend(struct r8152 *tp) 4479 { 4480 struct net_device *netdev = tp->netdev; 4481 4482 netif_device_detach(netdev); 4483 4484 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4485 struct napi_struct *napi = &tp->napi; 4486 4487 clear_bit(WORK_ENABLE, &tp->flags); 4488 usb_kill_urb(tp->intr_urb); 4489 napi_disable(napi); 4490 cancel_delayed_work_sync(&tp->schedule); 4491 tp->rtl_ops.down(tp); 4492 napi_enable(napi); 4493 } 4494 4495 return 0; 4496 } 4497 4498 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4499 { 4500 struct r8152 *tp = usb_get_intfdata(intf); 4501 int ret; 4502 4503 mutex_lock(&tp->control); 4504 4505 if (PMSG_IS_AUTO(message)) 4506 ret = rtl8152_runtime_suspend(tp); 4507 else 4508 ret = rtl8152_system_suspend(tp); 4509 4510 mutex_unlock(&tp->control); 4511 4512 return ret; 4513 } 4514 4515 static int rtl8152_resume(struct usb_interface *intf) 4516 { 4517 struct r8152 *tp = usb_get_intfdata(intf); 4518 int ret; 4519 4520 mutex_lock(&tp->control); 4521 4522 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4523 ret = rtl8152_runtime_resume(tp); 4524 else 4525 ret = rtl8152_system_resume(tp); 4526 4527 mutex_unlock(&tp->control); 4528 4529 return ret; 4530 } 4531 4532 static int rtl8152_reset_resume(struct usb_interface *intf) 4533 { 4534 struct r8152 *tp = usb_get_intfdata(intf); 4535 4536 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4537 mutex_lock(&tp->control); 4538 tp->rtl_ops.init(tp); 4539 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4540 mutex_unlock(&tp->control); 4541 return rtl8152_resume(intf); 4542 } 4543 4544 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4545 { 4546 struct r8152 *tp = netdev_priv(dev); 4547 4548 if (usb_autopm_get_interface(tp->intf) < 0) 4549 return; 4550 4551 if (!rtl_can_wakeup(tp)) { 4552 wol->supported = 0; 4553 wol->wolopts = 0; 4554 } else { 4555 mutex_lock(&tp->control); 4556 wol->supported = WAKE_ANY; 4557 wol->wolopts = __rtl_get_wol(tp); 4558 mutex_unlock(&tp->control); 4559 } 4560 4561 usb_autopm_put_interface(tp->intf); 4562 } 4563 4564 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4565 { 4566 struct r8152 *tp = netdev_priv(dev); 4567 int ret; 4568 4569 if (!rtl_can_wakeup(tp)) 4570 return -EOPNOTSUPP; 4571 4572 if (wol->wolopts & ~WAKE_ANY) 4573 return -EINVAL; 4574 4575 ret = usb_autopm_get_interface(tp->intf); 4576 if (ret < 0) 4577 goto out_set_wol; 4578 4579 mutex_lock(&tp->control); 4580 4581 __rtl_set_wol(tp, wol->wolopts); 4582 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4583 4584 mutex_unlock(&tp->control); 4585 4586 usb_autopm_put_interface(tp->intf); 4587 4588 out_set_wol: 4589 return ret; 4590 } 4591 4592 static u32 rtl8152_get_msglevel(struct net_device *dev) 4593 { 4594 struct r8152 *tp = netdev_priv(dev); 4595 4596 return tp->msg_enable; 4597 } 4598 4599 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4600 { 4601 struct r8152 *tp = netdev_priv(dev); 4602 4603 tp->msg_enable = value; 4604 } 4605 4606 static void rtl8152_get_drvinfo(struct net_device *netdev, 4607 struct ethtool_drvinfo *info) 4608 { 4609 struct r8152 *tp = netdev_priv(netdev); 4610 4611 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4612 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4613 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4614 } 4615 4616 static 4617 int rtl8152_get_link_ksettings(struct net_device *netdev, 4618 struct ethtool_link_ksettings *cmd) 4619 { 4620 struct r8152 *tp = netdev_priv(netdev); 4621 int ret; 4622 4623 if (!tp->mii.mdio_read) 4624 return -EOPNOTSUPP; 4625 4626 ret = usb_autopm_get_interface(tp->intf); 4627 if (ret < 0) 4628 goto out; 4629 4630 mutex_lock(&tp->control); 4631 4632 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4633 4634 mutex_unlock(&tp->control); 4635 4636 usb_autopm_put_interface(tp->intf); 4637 4638 out: 4639 return ret; 4640 } 4641 4642 static int rtl8152_set_link_ksettings(struct net_device *dev, 4643 const struct ethtool_link_ksettings *cmd) 4644 { 4645 struct r8152 *tp = netdev_priv(dev); 4646 int ret; 4647 4648 ret = usb_autopm_get_interface(tp->intf); 4649 if (ret < 0) 4650 goto out; 4651 4652 mutex_lock(&tp->control); 4653 4654 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4655 cmd->base.duplex); 4656 if (!ret) { 4657 tp->autoneg = cmd->base.autoneg; 4658 tp->speed = cmd->base.speed; 4659 tp->duplex = cmd->base.duplex; 4660 } 4661 4662 mutex_unlock(&tp->control); 4663 4664 usb_autopm_put_interface(tp->intf); 4665 4666 out: 4667 return ret; 4668 } 4669 4670 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4671 "tx_packets", 4672 "rx_packets", 4673 "tx_errors", 4674 "rx_errors", 4675 "rx_missed", 4676 "align_errors", 4677 "tx_single_collisions", 4678 "tx_multi_collisions", 4679 "rx_unicast", 4680 "rx_broadcast", 4681 "rx_multicast", 4682 "tx_aborted", 4683 "tx_underrun", 4684 }; 4685 4686 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4687 { 4688 switch (sset) { 4689 case ETH_SS_STATS: 4690 return ARRAY_SIZE(rtl8152_gstrings); 4691 default: 4692 return -EOPNOTSUPP; 4693 } 4694 } 4695 4696 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4697 struct ethtool_stats *stats, u64 *data) 4698 { 4699 struct r8152 *tp = netdev_priv(dev); 4700 struct tally_counter tally; 4701 4702 if (usb_autopm_get_interface(tp->intf) < 0) 4703 return; 4704 4705 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4706 4707 usb_autopm_put_interface(tp->intf); 4708 4709 data[0] = le64_to_cpu(tally.tx_packets); 4710 data[1] = le64_to_cpu(tally.rx_packets); 4711 data[2] = le64_to_cpu(tally.tx_errors); 4712 data[3] = le32_to_cpu(tally.rx_errors); 4713 data[4] = le16_to_cpu(tally.rx_missed); 4714 data[5] = le16_to_cpu(tally.align_errors); 4715 data[6] = le32_to_cpu(tally.tx_one_collision); 4716 data[7] = le32_to_cpu(tally.tx_multi_collision); 4717 data[8] = le64_to_cpu(tally.rx_unicast); 4718 data[9] = le64_to_cpu(tally.rx_broadcast); 4719 data[10] = le32_to_cpu(tally.rx_multicast); 4720 data[11] = le16_to_cpu(tally.tx_aborted); 4721 data[12] = le16_to_cpu(tally.tx_underrun); 4722 } 4723 4724 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4725 { 4726 switch (stringset) { 4727 case ETH_SS_STATS: 4728 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4729 break; 4730 } 4731 } 4732 4733 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4734 { 4735 u32 ocp_data, lp, adv, supported = 0; 4736 u16 val; 4737 4738 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4739 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4740 4741 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4742 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4743 4744 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4745 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4746 4747 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4748 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4749 4750 eee->eee_enabled = !!ocp_data; 4751 eee->eee_active = !!(supported & adv & lp); 4752 eee->supported = supported; 4753 eee->advertised = adv; 4754 eee->lp_advertised = lp; 4755 4756 return 0; 4757 } 4758 4759 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4760 { 4761 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4762 4763 r8152_eee_en(tp, eee->eee_enabled); 4764 4765 if (!eee->eee_enabled) 4766 val = 0; 4767 4768 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4769 4770 return 0; 4771 } 4772 4773 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4774 { 4775 u32 ocp_data, lp, adv, supported = 0; 4776 u16 val; 4777 4778 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4779 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4780 4781 val = ocp_reg_read(tp, OCP_EEE_ADV); 4782 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4783 4784 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4785 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4786 4787 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4788 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4789 4790 eee->eee_enabled = !!ocp_data; 4791 eee->eee_active = !!(supported & adv & lp); 4792 eee->supported = supported; 4793 eee->advertised = adv; 4794 eee->lp_advertised = lp; 4795 4796 return 0; 4797 } 4798 4799 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4800 { 4801 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4802 4803 r8153_eee_en(tp, eee->eee_enabled); 4804 4805 if (!eee->eee_enabled) 4806 val = 0; 4807 4808 ocp_reg_write(tp, OCP_EEE_ADV, val); 4809 4810 return 0; 4811 } 4812 4813 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4814 { 4815 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4816 4817 r8153b_eee_en(tp, eee->eee_enabled); 4818 4819 if (!eee->eee_enabled) 4820 val = 0; 4821 4822 ocp_reg_write(tp, OCP_EEE_ADV, val); 4823 4824 return 0; 4825 } 4826 4827 static int 4828 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4829 { 4830 struct r8152 *tp = netdev_priv(net); 4831 int ret; 4832 4833 ret = usb_autopm_get_interface(tp->intf); 4834 if (ret < 0) 4835 goto out; 4836 4837 mutex_lock(&tp->control); 4838 4839 ret = tp->rtl_ops.eee_get(tp, edata); 4840 4841 mutex_unlock(&tp->control); 4842 4843 usb_autopm_put_interface(tp->intf); 4844 4845 out: 4846 return ret; 4847 } 4848 4849 static int 4850 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4851 { 4852 struct r8152 *tp = netdev_priv(net); 4853 int ret; 4854 4855 ret = usb_autopm_get_interface(tp->intf); 4856 if (ret < 0) 4857 goto out; 4858 4859 mutex_lock(&tp->control); 4860 4861 ret = tp->rtl_ops.eee_set(tp, edata); 4862 if (!ret) 4863 ret = mii_nway_restart(&tp->mii); 4864 4865 mutex_unlock(&tp->control); 4866 4867 usb_autopm_put_interface(tp->intf); 4868 4869 out: 4870 return ret; 4871 } 4872 4873 static int rtl8152_nway_reset(struct net_device *dev) 4874 { 4875 struct r8152 *tp = netdev_priv(dev); 4876 int ret; 4877 4878 ret = usb_autopm_get_interface(tp->intf); 4879 if (ret < 0) 4880 goto out; 4881 4882 mutex_lock(&tp->control); 4883 4884 ret = mii_nway_restart(&tp->mii); 4885 4886 mutex_unlock(&tp->control); 4887 4888 usb_autopm_put_interface(tp->intf); 4889 4890 out: 4891 return ret; 4892 } 4893 4894 static int rtl8152_get_coalesce(struct net_device *netdev, 4895 struct ethtool_coalesce *coalesce) 4896 { 4897 struct r8152 *tp = netdev_priv(netdev); 4898 4899 switch (tp->version) { 4900 case RTL_VER_01: 4901 case RTL_VER_02: 4902 case RTL_VER_07: 4903 return -EOPNOTSUPP; 4904 default: 4905 break; 4906 } 4907 4908 coalesce->rx_coalesce_usecs = tp->coalesce; 4909 4910 return 0; 4911 } 4912 4913 static int rtl8152_set_coalesce(struct net_device *netdev, 4914 struct ethtool_coalesce *coalesce) 4915 { 4916 struct r8152 *tp = netdev_priv(netdev); 4917 int ret; 4918 4919 switch (tp->version) { 4920 case RTL_VER_01: 4921 case RTL_VER_02: 4922 case RTL_VER_07: 4923 return -EOPNOTSUPP; 4924 default: 4925 break; 4926 } 4927 4928 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4929 return -EINVAL; 4930 4931 ret = usb_autopm_get_interface(tp->intf); 4932 if (ret < 0) 4933 return ret; 4934 4935 mutex_lock(&tp->control); 4936 4937 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4938 tp->coalesce = coalesce->rx_coalesce_usecs; 4939 4940 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 4941 netif_stop_queue(netdev); 4942 napi_disable(&tp->napi); 4943 tp->rtl_ops.disable(tp); 4944 tp->rtl_ops.enable(tp); 4945 rtl_start_rx(tp); 4946 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 4947 _rtl8152_set_rx_mode(netdev); 4948 napi_enable(&tp->napi); 4949 netif_wake_queue(netdev); 4950 } 4951 } 4952 4953 mutex_unlock(&tp->control); 4954 4955 usb_autopm_put_interface(tp->intf); 4956 4957 return ret; 4958 } 4959 4960 static const struct ethtool_ops ops = { 4961 .get_drvinfo = rtl8152_get_drvinfo, 4962 .get_link = ethtool_op_get_link, 4963 .nway_reset = rtl8152_nway_reset, 4964 .get_msglevel = rtl8152_get_msglevel, 4965 .set_msglevel = rtl8152_set_msglevel, 4966 .get_wol = rtl8152_get_wol, 4967 .set_wol = rtl8152_set_wol, 4968 .get_strings = rtl8152_get_strings, 4969 .get_sset_count = rtl8152_get_sset_count, 4970 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4971 .get_coalesce = rtl8152_get_coalesce, 4972 .set_coalesce = rtl8152_set_coalesce, 4973 .get_eee = rtl_ethtool_get_eee, 4974 .set_eee = rtl_ethtool_set_eee, 4975 .get_link_ksettings = rtl8152_get_link_ksettings, 4976 .set_link_ksettings = rtl8152_set_link_ksettings, 4977 }; 4978 4979 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4980 { 4981 struct r8152 *tp = netdev_priv(netdev); 4982 struct mii_ioctl_data *data = if_mii(rq); 4983 int res; 4984 4985 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4986 return -ENODEV; 4987 4988 res = usb_autopm_get_interface(tp->intf); 4989 if (res < 0) 4990 goto out; 4991 4992 switch (cmd) { 4993 case SIOCGMIIPHY: 4994 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4995 break; 4996 4997 case SIOCGMIIREG: 4998 mutex_lock(&tp->control); 4999 data->val_out = r8152_mdio_read(tp, data->reg_num); 5000 mutex_unlock(&tp->control); 5001 break; 5002 5003 case SIOCSMIIREG: 5004 if (!capable(CAP_NET_ADMIN)) { 5005 res = -EPERM; 5006 break; 5007 } 5008 mutex_lock(&tp->control); 5009 r8152_mdio_write(tp, data->reg_num, data->val_in); 5010 mutex_unlock(&tp->control); 5011 break; 5012 5013 default: 5014 res = -EOPNOTSUPP; 5015 } 5016 5017 usb_autopm_put_interface(tp->intf); 5018 5019 out: 5020 return res; 5021 } 5022 5023 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 5024 { 5025 struct r8152 *tp = netdev_priv(dev); 5026 int ret; 5027 5028 switch (tp->version) { 5029 case RTL_VER_01: 5030 case RTL_VER_02: 5031 case RTL_VER_07: 5032 dev->mtu = new_mtu; 5033 return 0; 5034 default: 5035 break; 5036 } 5037 5038 ret = usb_autopm_get_interface(tp->intf); 5039 if (ret < 0) 5040 return ret; 5041 5042 mutex_lock(&tp->control); 5043 5044 dev->mtu = new_mtu; 5045 5046 if (netif_running(dev)) { 5047 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5048 5049 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5050 5051 if (netif_carrier_ok(dev)) 5052 r8153_set_rx_early_size(tp); 5053 } 5054 5055 mutex_unlock(&tp->control); 5056 5057 usb_autopm_put_interface(tp->intf); 5058 5059 return ret; 5060 } 5061 5062 static const struct net_device_ops rtl8152_netdev_ops = { 5063 .ndo_open = rtl8152_open, 5064 .ndo_stop = rtl8152_close, 5065 .ndo_do_ioctl = rtl8152_ioctl, 5066 .ndo_start_xmit = rtl8152_start_xmit, 5067 .ndo_tx_timeout = rtl8152_tx_timeout, 5068 .ndo_set_features = rtl8152_set_features, 5069 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5070 .ndo_set_mac_address = rtl8152_set_mac_address, 5071 .ndo_change_mtu = rtl8152_change_mtu, 5072 .ndo_validate_addr = eth_validate_addr, 5073 .ndo_features_check = rtl8152_features_check, 5074 }; 5075 5076 static void rtl8152_unload(struct r8152 *tp) 5077 { 5078 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5079 return; 5080 5081 if (tp->version != RTL_VER_01) 5082 r8152_power_cut_en(tp, true); 5083 } 5084 5085 static void rtl8153_unload(struct r8152 *tp) 5086 { 5087 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5088 return; 5089 5090 r8153_power_cut_en(tp, false); 5091 } 5092 5093 static void rtl8153b_unload(struct r8152 *tp) 5094 { 5095 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5096 return; 5097 5098 r8153b_power_cut_en(tp, false); 5099 } 5100 5101 static int rtl_ops_init(struct r8152 *tp) 5102 { 5103 struct rtl_ops *ops = &tp->rtl_ops; 5104 int ret = 0; 5105 5106 switch (tp->version) { 5107 case RTL_VER_01: 5108 case RTL_VER_02: 5109 case RTL_VER_07: 5110 ops->init = r8152b_init; 5111 ops->enable = rtl8152_enable; 5112 ops->disable = rtl8152_disable; 5113 ops->up = rtl8152_up; 5114 ops->down = rtl8152_down; 5115 ops->unload = rtl8152_unload; 5116 ops->eee_get = r8152_get_eee; 5117 ops->eee_set = r8152_set_eee; 5118 ops->in_nway = rtl8152_in_nway; 5119 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5120 ops->autosuspend_en = rtl_runtime_suspend_enable; 5121 break; 5122 5123 case RTL_VER_03: 5124 case RTL_VER_04: 5125 case RTL_VER_05: 5126 case RTL_VER_06: 5127 ops->init = r8153_init; 5128 ops->enable = rtl8153_enable; 5129 ops->disable = rtl8153_disable; 5130 ops->up = rtl8153_up; 5131 ops->down = rtl8153_down; 5132 ops->unload = rtl8153_unload; 5133 ops->eee_get = r8153_get_eee; 5134 ops->eee_set = r8153_set_eee; 5135 ops->in_nway = rtl8153_in_nway; 5136 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5137 ops->autosuspend_en = rtl8153_runtime_enable; 5138 break; 5139 5140 case RTL_VER_08: 5141 case RTL_VER_09: 5142 ops->init = r8153b_init; 5143 ops->enable = rtl8153_enable; 5144 ops->disable = rtl8153b_disable; 5145 ops->up = rtl8153b_up; 5146 ops->down = rtl8153b_down; 5147 ops->unload = rtl8153b_unload; 5148 ops->eee_get = r8153_get_eee; 5149 ops->eee_set = r8153b_set_eee; 5150 ops->in_nway = rtl8153_in_nway; 5151 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5152 ops->autosuspend_en = rtl8153b_runtime_enable; 5153 break; 5154 5155 default: 5156 ret = -ENODEV; 5157 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5158 break; 5159 } 5160 5161 return ret; 5162 } 5163 5164 static u8 rtl_get_version(struct usb_interface *intf) 5165 { 5166 struct usb_device *udev = interface_to_usbdev(intf); 5167 u32 ocp_data = 0; 5168 __le32 *tmp; 5169 u8 version; 5170 int ret; 5171 5172 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5173 if (!tmp) 5174 return 0; 5175 5176 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5177 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5178 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5179 if (ret > 0) 5180 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5181 5182 kfree(tmp); 5183 5184 switch (ocp_data) { 5185 case 0x4c00: 5186 version = RTL_VER_01; 5187 break; 5188 case 0x4c10: 5189 version = RTL_VER_02; 5190 break; 5191 case 0x5c00: 5192 version = RTL_VER_03; 5193 break; 5194 case 0x5c10: 5195 version = RTL_VER_04; 5196 break; 5197 case 0x5c20: 5198 version = RTL_VER_05; 5199 break; 5200 case 0x5c30: 5201 version = RTL_VER_06; 5202 break; 5203 case 0x4800: 5204 version = RTL_VER_07; 5205 break; 5206 case 0x6000: 5207 version = RTL_VER_08; 5208 break; 5209 case 0x6010: 5210 version = RTL_VER_09; 5211 break; 5212 default: 5213 version = RTL_VER_UNKNOWN; 5214 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5215 break; 5216 } 5217 5218 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5219 5220 return version; 5221 } 5222 5223 static int rtl8152_probe(struct usb_interface *intf, 5224 const struct usb_device_id *id) 5225 { 5226 struct usb_device *udev = interface_to_usbdev(intf); 5227 u8 version = rtl_get_version(intf); 5228 struct r8152 *tp; 5229 struct net_device *netdev; 5230 int ret; 5231 5232 if (version == RTL_VER_UNKNOWN) 5233 return -ENODEV; 5234 5235 if (udev->actconfig->desc.bConfigurationValue != 1) { 5236 usb_driver_set_configuration(udev, 1); 5237 return -ENODEV; 5238 } 5239 5240 usb_reset_device(udev); 5241 netdev = alloc_etherdev(sizeof(struct r8152)); 5242 if (!netdev) { 5243 dev_err(&intf->dev, "Out of memory\n"); 5244 return -ENOMEM; 5245 } 5246 5247 SET_NETDEV_DEV(netdev, &intf->dev); 5248 tp = netdev_priv(netdev); 5249 tp->msg_enable = 0x7FFF; 5250 5251 tp->udev = udev; 5252 tp->netdev = netdev; 5253 tp->intf = intf; 5254 tp->version = version; 5255 5256 switch (version) { 5257 case RTL_VER_01: 5258 case RTL_VER_02: 5259 case RTL_VER_07: 5260 tp->mii.supports_gmii = 0; 5261 break; 5262 default: 5263 tp->mii.supports_gmii = 1; 5264 break; 5265 } 5266 5267 ret = rtl_ops_init(tp); 5268 if (ret) 5269 goto out; 5270 5271 mutex_init(&tp->control); 5272 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5273 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5274 5275 netdev->netdev_ops = &rtl8152_netdev_ops; 5276 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5277 5278 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5279 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5280 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5281 NETIF_F_HW_VLAN_CTAG_TX; 5282 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5283 NETIF_F_TSO | NETIF_F_FRAGLIST | 5284 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5285 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5286 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5287 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5288 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5289 5290 if (tp->version == RTL_VER_01) { 5291 netdev->features &= ~NETIF_F_RXCSUM; 5292 netdev->hw_features &= ~NETIF_F_RXCSUM; 5293 } 5294 5295 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5296 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5297 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5298 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5299 } 5300 5301 netdev->ethtool_ops = &ops; 5302 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5303 5304 /* MTU range: 68 - 1500 or 9194 */ 5305 netdev->min_mtu = ETH_MIN_MTU; 5306 switch (tp->version) { 5307 case RTL_VER_01: 5308 case RTL_VER_02: 5309 netdev->max_mtu = ETH_DATA_LEN; 5310 break; 5311 default: 5312 netdev->max_mtu = RTL8153_MAX_MTU; 5313 break; 5314 } 5315 5316 tp->mii.dev = netdev; 5317 tp->mii.mdio_read = read_mii_word; 5318 tp->mii.mdio_write = write_mii_word; 5319 tp->mii.phy_id_mask = 0x3f; 5320 tp->mii.reg_num_mask = 0x1f; 5321 tp->mii.phy_id = R8152_PHY_ID; 5322 5323 tp->autoneg = AUTONEG_ENABLE; 5324 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5325 tp->duplex = DUPLEX_FULL; 5326 5327 intf->needs_remote_wakeup = 1; 5328 5329 tp->rtl_ops.init(tp); 5330 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5331 set_ethernet_addr(tp); 5332 5333 usb_set_intfdata(intf, tp); 5334 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5335 5336 ret = register_netdev(netdev); 5337 if (ret != 0) { 5338 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5339 goto out1; 5340 } 5341 5342 if (!rtl_can_wakeup(tp)) 5343 __rtl_set_wol(tp, 0); 5344 5345 tp->saved_wolopts = __rtl_get_wol(tp); 5346 if (tp->saved_wolopts) 5347 device_set_wakeup_enable(&udev->dev, true); 5348 else 5349 device_set_wakeup_enable(&udev->dev, false); 5350 5351 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5352 5353 return 0; 5354 5355 out1: 5356 netif_napi_del(&tp->napi); 5357 usb_set_intfdata(intf, NULL); 5358 out: 5359 free_netdev(netdev); 5360 return ret; 5361 } 5362 5363 static void rtl8152_disconnect(struct usb_interface *intf) 5364 { 5365 struct r8152 *tp = usb_get_intfdata(intf); 5366 5367 usb_set_intfdata(intf, NULL); 5368 if (tp) { 5369 rtl_set_unplug(tp); 5370 5371 netif_napi_del(&tp->napi); 5372 unregister_netdev(tp->netdev); 5373 cancel_delayed_work_sync(&tp->hw_phy_work); 5374 tp->rtl_ops.unload(tp); 5375 free_netdev(tp->netdev); 5376 } 5377 } 5378 5379 #define REALTEK_USB_DEVICE(vend, prod) \ 5380 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5381 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5382 .idVendor = (vend), \ 5383 .idProduct = (prod), \ 5384 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5385 }, \ 5386 { \ 5387 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5388 USB_DEVICE_ID_MATCH_DEVICE, \ 5389 .idVendor = (vend), \ 5390 .idProduct = (prod), \ 5391 .bInterfaceClass = USB_CLASS_COMM, \ 5392 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5393 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5394 5395 /* table of devices that work with this driver */ 5396 static const struct usb_device_id rtl8152_table[] = { 5397 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5398 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5399 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5400 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5401 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5402 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5403 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5404 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5405 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5406 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5407 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5408 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5409 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5410 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5411 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5412 {} 5413 }; 5414 5415 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5416 5417 static struct usb_driver rtl8152_driver = { 5418 .name = MODULENAME, 5419 .id_table = rtl8152_table, 5420 .probe = rtl8152_probe, 5421 .disconnect = rtl8152_disconnect, 5422 .suspend = rtl8152_suspend, 5423 .resume = rtl8152_resume, 5424 .reset_resume = rtl8152_reset_resume, 5425 .pre_reset = rtl8152_pre_reset, 5426 .post_reset = rtl8152_post_reset, 5427 .supports_autosuspend = 1, 5428 .disable_hub_initiated_lpm = 1, 5429 }; 5430 5431 module_usb_driver(rtl8152_driver); 5432 5433 MODULE_AUTHOR(DRIVER_AUTHOR); 5434 MODULE_DESCRIPTION(DRIVER_DESC); 5435 MODULE_LICENSE("GPL"); 5436 MODULE_VERSION(DRIVER_VERSION); 5437