1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "09" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_TEREDO_WAKE_BASE 0xc0c4 55 #define PLA_MAR 0xcd00 56 #define PLA_BACKUP 0xd000 57 #define PAL_BDC_CR 0xd1a0 58 #define PLA_TEREDO_TIMER 0xd2cc 59 #define PLA_REALWOW_TIMER 0xd2e8 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_MISC_1 0xd81f 133 #define USB_AFE_CTRL2 0xd824 134 #define USB_UPS_CFG 0xd842 135 #define USB_UPS_FLAGS 0xd848 136 #define USB_WDT11_CTRL 0xe43c 137 #define USB_BP_BA 0xfc26 138 #define USB_BP_0 0xfc28 139 #define USB_BP_1 0xfc2a 140 #define USB_BP_2 0xfc2c 141 #define USB_BP_3 0xfc2e 142 #define USB_BP_4 0xfc30 143 #define USB_BP_5 0xfc32 144 #define USB_BP_6 0xfc34 145 #define USB_BP_7 0xfc36 146 #define USB_BP_EN 0xfc38 147 #define USB_BP_8 0xfc38 148 #define USB_BP_9 0xfc3a 149 #define USB_BP_10 0xfc3c 150 #define USB_BP_11 0xfc3e 151 #define USB_BP_12 0xfc40 152 #define USB_BP_13 0xfc42 153 #define USB_BP_14 0xfc44 154 #define USB_BP_15 0xfc46 155 #define USB_BP2_EN 0xfc48 156 157 /* OCP Registers */ 158 #define OCP_ALDPS_CONFIG 0x2010 159 #define OCP_EEE_CONFIG1 0x2080 160 #define OCP_EEE_CONFIG2 0x2092 161 #define OCP_EEE_CONFIG3 0x2094 162 #define OCP_BASE_MII 0xa400 163 #define OCP_EEE_AR 0xa41a 164 #define OCP_EEE_DATA 0xa41c 165 #define OCP_PHY_STATUS 0xa420 166 #define OCP_NCTL_CFG 0xa42c 167 #define OCP_POWER_CFG 0xa430 168 #define OCP_EEE_CFG 0xa432 169 #define OCP_SRAM_ADDR 0xa436 170 #define OCP_SRAM_DATA 0xa438 171 #define OCP_DOWN_SPEED 0xa442 172 #define OCP_EEE_ABLE 0xa5c4 173 #define OCP_EEE_ADV 0xa5d0 174 #define OCP_EEE_LPABLE 0xa5d2 175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 176 #define OCP_PHY_PATCH_STAT 0xb800 177 #define OCP_PHY_PATCH_CMD 0xb820 178 #define OCP_ADC_IOFFSET 0xbcfc 179 #define OCP_ADC_CFG 0xbc06 180 #define OCP_SYSCLK_CFG 0xc416 181 182 /* SRAM Register */ 183 #define SRAM_GREEN_CFG 0x8011 184 #define SRAM_LPF_CFG 0x8012 185 #define SRAM_10M_AMP1 0x8080 186 #define SRAM_10M_AMP2 0x8082 187 #define SRAM_IMPEDANCE 0x8084 188 189 /* PLA_RCR */ 190 #define RCR_AAP 0x00000001 191 #define RCR_APM 0x00000002 192 #define RCR_AM 0x00000004 193 #define RCR_AB 0x00000008 194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 195 196 /* PLA_RXFIFO_CTRL0 */ 197 #define RXFIFO_THR1_NORMAL 0x00080002 198 #define RXFIFO_THR1_OOB 0x01800003 199 200 /* PLA_RXFIFO_CTRL1 */ 201 #define RXFIFO_THR2_FULL 0x00000060 202 #define RXFIFO_THR2_HIGH 0x00000038 203 #define RXFIFO_THR2_OOB 0x0000004a 204 #define RXFIFO_THR2_NORMAL 0x00a0 205 206 /* PLA_RXFIFO_CTRL2 */ 207 #define RXFIFO_THR3_FULL 0x00000078 208 #define RXFIFO_THR3_HIGH 0x00000048 209 #define RXFIFO_THR3_OOB 0x0000005a 210 #define RXFIFO_THR3_NORMAL 0x0110 211 212 /* PLA_TXFIFO_CTRL */ 213 #define TXFIFO_THR_NORMAL 0x00400008 214 #define TXFIFO_THR_NORMAL2 0x01000008 215 216 /* PLA_DMY_REG0 */ 217 #define ECM_ALDPS 0x0002 218 219 /* PLA_FMC */ 220 #define FMC_FCR_MCU_EN 0x0001 221 222 /* PLA_EEEP_CR */ 223 #define EEEP_CR_EEEP_TX 0x0002 224 225 /* PLA_WDT6_CTRL */ 226 #define WDT6_SET_MODE 0x0010 227 228 /* PLA_TCR0 */ 229 #define TCR0_TX_EMPTY 0x0800 230 #define TCR0_AUTO_FIFO 0x0080 231 232 /* PLA_TCR1 */ 233 #define VERSION_MASK 0x7cf0 234 235 /* PLA_MTPS */ 236 #define MTPS_JUMBO (12 * 1024 / 64) 237 #define MTPS_DEFAULT (6 * 1024 / 64) 238 239 /* PLA_RSTTALLY */ 240 #define TALLY_RESET 0x0001 241 242 /* PLA_CR */ 243 #define CR_RST 0x10 244 #define CR_RE 0x08 245 #define CR_TE 0x04 246 247 /* PLA_CRWECR */ 248 #define CRWECR_NORAML 0x00 249 #define CRWECR_CONFIG 0xc0 250 251 /* PLA_OOB_CTRL */ 252 #define NOW_IS_OOB 0x80 253 #define TXFIFO_EMPTY 0x20 254 #define RXFIFO_EMPTY 0x10 255 #define LINK_LIST_READY 0x02 256 #define DIS_MCU_CLROOB 0x01 257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 258 259 /* PLA_MISC_1 */ 260 #define RXDY_GATED_EN 0x0008 261 262 /* PLA_SFF_STS_7 */ 263 #define RE_INIT_LL 0x8000 264 #define MCU_BORW_EN 0x4000 265 266 /* PLA_CPCR */ 267 #define CPCR_RX_VLAN 0x0040 268 269 /* PLA_CFG_WOL */ 270 #define MAGIC_EN 0x0001 271 272 /* PLA_TEREDO_CFG */ 273 #define TEREDO_SEL 0x8000 274 #define TEREDO_WAKE_MASK 0x7f00 275 #define TEREDO_RS_EVENT_MASK 0x00fe 276 #define OOB_TEREDO_EN 0x0001 277 278 /* PAL_BDC_CR */ 279 #define ALDPS_PROXY_MODE 0x0001 280 281 /* PLA_EFUSE_CMD */ 282 #define EFUSE_READ_CMD BIT(15) 283 #define EFUSE_DATA_BIT16 BIT(7) 284 285 /* PLA_CONFIG34 */ 286 #define LINK_ON_WAKE_EN 0x0010 287 #define LINK_OFF_WAKE_EN 0x0008 288 289 /* PLA_CONFIG5 */ 290 #define BWF_EN 0x0040 291 #define MWF_EN 0x0020 292 #define UWF_EN 0x0010 293 #define LAN_WAKE_EN 0x0002 294 295 /* PLA_LED_FEATURE */ 296 #define LED_MODE_MASK 0x0700 297 298 /* PLA_PHY_PWR */ 299 #define TX_10M_IDLE_EN 0x0080 300 #define PFM_PWM_SWITCH 0x0040 301 302 /* PLA_MAC_PWR_CTRL */ 303 #define D3_CLK_GATED_EN 0x00004000 304 #define MCU_CLK_RATIO 0x07010f07 305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 306 #define ALDPS_SPDWN_RATIO 0x0f87 307 308 /* PLA_MAC_PWR_CTRL2 */ 309 #define EEE_SPDWN_RATIO 0x8007 310 #define MAC_CLK_SPDWN_EN BIT(15) 311 312 /* PLA_MAC_PWR_CTRL3 */ 313 #define PKT_AVAIL_SPDWN_EN 0x0100 314 #define SUSPEND_SPDWN_EN 0x0004 315 #define U1U2_SPDWN_EN 0x0002 316 #define L1_SPDWN_EN 0x0001 317 318 /* PLA_MAC_PWR_CTRL4 */ 319 #define PWRSAVE_SPDWN_EN 0x1000 320 #define RXDV_SPDWN_EN 0x0800 321 #define TX10MIDLE_EN 0x0100 322 #define TP100_SPDWN_EN 0x0020 323 #define TP500_SPDWN_EN 0x0010 324 #define TP1000_SPDWN_EN 0x0008 325 #define EEE_SPDWN_EN 0x0001 326 327 /* PLA_GPHY_INTR_IMR */ 328 #define GPHY_STS_MSK 0x0001 329 #define SPEED_DOWN_MSK 0x0002 330 #define SPDWN_RXDV_MSK 0x0004 331 #define SPDWN_LINKCHG_MSK 0x0008 332 333 /* PLA_PHYAR */ 334 #define PHYAR_FLAG 0x80000000 335 336 /* PLA_EEE_CR */ 337 #define EEE_RX_EN 0x0001 338 #define EEE_TX_EN 0x0002 339 340 /* PLA_BOOT_CTRL */ 341 #define AUTOLOAD_DONE 0x0002 342 343 /* USB_USB2PHY */ 344 #define USB2PHY_SUSPEND 0x0001 345 #define USB2PHY_L1 0x0002 346 347 /* USB_SSPHYLINK2 */ 348 #define pwd_dn_scale_mask 0x3ffe 349 #define pwd_dn_scale(x) ((x) << 1) 350 351 /* USB_CSR_DUMMY1 */ 352 #define DYNAMIC_BURST 0x0001 353 354 /* USB_CSR_DUMMY2 */ 355 #define EP4_FULL_FC 0x0001 356 357 /* USB_DEV_STAT */ 358 #define STAT_SPEED_MASK 0x0006 359 #define STAT_SPEED_HIGH 0x0000 360 #define STAT_SPEED_FULL 0x0002 361 362 /* USB_LPM_CONFIG */ 363 #define LPM_U1U2_EN BIT(0) 364 365 /* USB_TX_AGG */ 366 #define TX_AGG_MAX_THRESHOLD 0x03 367 368 /* USB_RX_BUF_TH */ 369 #define RX_THR_SUPPER 0x0c350180 370 #define RX_THR_HIGH 0x7a120180 371 #define RX_THR_SLOW 0xffff0180 372 #define RX_THR_B 0x00010001 373 374 /* USB_TX_DMA */ 375 #define TEST_MODE_DISABLE 0x00000001 376 #define TX_SIZE_ADJUST1 0x00000100 377 378 /* USB_BMU_RESET */ 379 #define BMU_RESET_EP_IN 0x01 380 #define BMU_RESET_EP_OUT 0x02 381 382 /* USB_UPT_RXDMA_OWN */ 383 #define OWN_UPDATE BIT(0) 384 #define OWN_CLEAR BIT(1) 385 386 /* USB_UPS_CTRL */ 387 #define POWER_CUT 0x0100 388 389 /* USB_PM_CTRL_STATUS */ 390 #define RESUME_INDICATE 0x0001 391 392 /* USB_USB_CTRL */ 393 #define RX_AGG_DISABLE 0x0010 394 #define RX_ZERO_EN 0x0080 395 396 /* USB_U2P3_CTRL */ 397 #define U2P3_ENABLE 0x0001 398 399 /* USB_POWER_CUT */ 400 #define PWR_EN 0x0001 401 #define PHASE2_EN 0x0008 402 #define UPS_EN BIT(4) 403 #define USP_PREWAKE BIT(5) 404 405 /* USB_MISC_0 */ 406 #define PCUT_STATUS 0x0001 407 408 /* USB_RX_EARLY_TIMEOUT */ 409 #define COALESCE_SUPER 85000U 410 #define COALESCE_HIGH 250000U 411 #define COALESCE_SLOW 524280U 412 413 /* USB_WDT11_CTRL */ 414 #define TIMER11_EN 0x0001 415 416 /* USB_LPM_CTRL */ 417 /* bit 4 ~ 5: fifo empty boundary */ 418 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 419 /* bit 2 ~ 3: LMP timer */ 420 #define LPM_TIMER_MASK 0x0c 421 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 422 #define LPM_TIMER_500US 0x0c /* 500 us */ 423 #define ROK_EXIT_LPM 0x02 424 425 /* USB_AFE_CTRL2 */ 426 #define SEN_VAL_MASK 0xf800 427 #define SEN_VAL_NORMAL 0xa000 428 #define SEL_RXIDLE 0x0100 429 430 /* USB_UPS_CFG */ 431 #define SAW_CNT_1MS_MASK 0x0fff 432 433 /* USB_UPS_FLAGS */ 434 #define UPS_FLAGS_R_TUNE BIT(0) 435 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 436 #define UPS_FLAGS_250M_CKDIV BIT(2) 437 #define UPS_FLAGS_EN_ALDPS BIT(3) 438 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 439 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 440 #define ups_flags_speed(x) ((x) << 16) 441 #define UPS_FLAGS_EN_EEE BIT(20) 442 #define UPS_FLAGS_EN_500M_EEE BIT(21) 443 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 444 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 445 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 446 #define UPS_FLAGS_EN_GREEN BIT(26) 447 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 448 449 enum spd_duplex { 450 NWAY_10M_HALF = 1, 451 NWAY_10M_FULL, 452 NWAY_100M_HALF, 453 NWAY_100M_FULL, 454 NWAY_1000M_FULL, 455 FORCE_10M_HALF, 456 FORCE_10M_FULL, 457 FORCE_100M_HALF, 458 FORCE_100M_FULL, 459 }; 460 461 /* OCP_ALDPS_CONFIG */ 462 #define ENPWRSAVE 0x8000 463 #define ENPDNPS 0x0200 464 #define LINKENA 0x0100 465 #define DIS_SDSAVE 0x0010 466 467 /* OCP_PHY_STATUS */ 468 #define PHY_STAT_MASK 0x0007 469 #define PHY_STAT_EXT_INIT 2 470 #define PHY_STAT_LAN_ON 3 471 #define PHY_STAT_PWRDN 5 472 473 /* OCP_NCTL_CFG */ 474 #define PGA_RETURN_EN BIT(1) 475 476 /* OCP_POWER_CFG */ 477 #define EEE_CLKDIV_EN 0x8000 478 #define EN_ALDPS 0x0004 479 #define EN_10M_PLLOFF 0x0001 480 481 /* OCP_EEE_CONFIG1 */ 482 #define RG_TXLPI_MSK_HFDUP 0x8000 483 #define RG_MATCLR_EN 0x4000 484 #define EEE_10_CAP 0x2000 485 #define EEE_NWAY_EN 0x1000 486 #define TX_QUIET_EN 0x0200 487 #define RX_QUIET_EN 0x0100 488 #define sd_rise_time_mask 0x0070 489 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 490 #define RG_RXLPI_MSK_HFDUP 0x0008 491 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 492 493 /* OCP_EEE_CONFIG2 */ 494 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 495 #define RG_DACQUIET_EN 0x0400 496 #define RG_LDVQUIET_EN 0x0200 497 #define RG_CKRSEL 0x0020 498 #define RG_EEEPRG_EN 0x0010 499 500 /* OCP_EEE_CONFIG3 */ 501 #define fast_snr_mask 0xff80 502 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 503 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 504 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 505 506 /* OCP_EEE_AR */ 507 /* bit[15:14] function */ 508 #define FUN_ADDR 0x0000 509 #define FUN_DATA 0x4000 510 /* bit[4:0] device addr */ 511 512 /* OCP_EEE_CFG */ 513 #define CTAP_SHORT_EN 0x0040 514 #define EEE10_EN 0x0010 515 516 /* OCP_DOWN_SPEED */ 517 #define EN_EEE_CMODE BIT(14) 518 #define EN_EEE_1000 BIT(13) 519 #define EN_EEE_100 BIT(12) 520 #define EN_10M_CLKDIV BIT(11) 521 #define EN_10M_BGOFF 0x0080 522 523 /* OCP_PHY_STATE */ 524 #define TXDIS_STATE 0x01 525 #define ABD_STATE 0x02 526 527 /* OCP_PHY_PATCH_STAT */ 528 #define PATCH_READY BIT(6) 529 530 /* OCP_PHY_PATCH_CMD */ 531 #define PATCH_REQUEST BIT(4) 532 533 /* OCP_ADC_CFG */ 534 #define CKADSEL_L 0x0100 535 #define ADC_EN 0x0080 536 #define EN_EMI_L 0x0040 537 538 /* OCP_SYSCLK_CFG */ 539 #define clk_div_expo(x) (min(x, 5) << 8) 540 541 /* SRAM_GREEN_CFG */ 542 #define GREEN_ETH_EN BIT(15) 543 #define R_TUNE_EN BIT(11) 544 545 /* SRAM_LPF_CFG */ 546 #define LPF_AUTO_TUNE 0x8000 547 548 /* SRAM_10M_AMP1 */ 549 #define GDAC_IB_UPALL 0x0008 550 551 /* SRAM_10M_AMP2 */ 552 #define AMP_DN 0x0200 553 554 /* SRAM_IMPEDANCE */ 555 #define RX_DRIVING_MASK 0x6000 556 557 /* MAC PASSTHRU */ 558 #define AD_MASK 0xfee0 559 #define BND_MASK 0x0004 560 #define BD_MASK 0x0001 561 #define EFUSE 0xcfdb 562 #define PASS_THRU_MASK 0x1 563 564 enum rtl_register_content { 565 _1000bps = 0x10, 566 _100bps = 0x08, 567 _10bps = 0x04, 568 LINK_STATUS = 0x02, 569 FULL_DUP = 0x01, 570 }; 571 572 #define RTL8152_MAX_TX 4 573 #define RTL8152_MAX_RX 10 574 #define INTBUFSIZE 2 575 #define TX_ALIGN 4 576 #define RX_ALIGN 8 577 578 #define INTR_LINK 0x0004 579 580 #define RTL8152_REQT_READ 0xc0 581 #define RTL8152_REQT_WRITE 0x40 582 #define RTL8152_REQ_GET_REGS 0x05 583 #define RTL8152_REQ_SET_REGS 0x05 584 585 #define BYTE_EN_DWORD 0xff 586 #define BYTE_EN_WORD 0x33 587 #define BYTE_EN_BYTE 0x11 588 #define BYTE_EN_SIX_BYTES 0x3f 589 #define BYTE_EN_START_MASK 0x0f 590 #define BYTE_EN_END_MASK 0xf0 591 592 #define RTL8153_MAX_PACKET 9216 /* 9K */ 593 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 594 ETH_FCS_LEN) 595 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 596 #define RTL8153_RMS RTL8153_MAX_PACKET 597 #define RTL8152_TX_TIMEOUT (5 * HZ) 598 #define RTL8152_NAPI_WEIGHT 64 599 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 600 sizeof(struct rx_desc) + RX_ALIGN) 601 602 /* rtl8152 flags */ 603 enum rtl8152_flags { 604 RTL8152_UNPLUG = 0, 605 RTL8152_SET_RX_MODE, 606 WORK_ENABLE, 607 RTL8152_LINK_CHG, 608 SELECTIVE_SUSPEND, 609 PHY_RESET, 610 SCHEDULE_NAPI, 611 GREEN_ETHERNET, 612 DELL_TB_RX_AGG_BUG, 613 }; 614 615 /* Define these values to match your device */ 616 #define VENDOR_ID_REALTEK 0x0bda 617 #define VENDOR_ID_MICROSOFT 0x045e 618 #define VENDOR_ID_SAMSUNG 0x04e8 619 #define VENDOR_ID_LENOVO 0x17ef 620 #define VENDOR_ID_LINKSYS 0x13b1 621 #define VENDOR_ID_NVIDIA 0x0955 622 #define VENDOR_ID_TPLINK 0x2357 623 624 #define MCU_TYPE_PLA 0x0100 625 #define MCU_TYPE_USB 0x0000 626 627 struct tally_counter { 628 __le64 tx_packets; 629 __le64 rx_packets; 630 __le64 tx_errors; 631 __le32 rx_errors; 632 __le16 rx_missed; 633 __le16 align_errors; 634 __le32 tx_one_collision; 635 __le32 tx_multi_collision; 636 __le64 rx_unicast; 637 __le64 rx_broadcast; 638 __le32 rx_multicast; 639 __le16 tx_aborted; 640 __le16 tx_underrun; 641 }; 642 643 struct rx_desc { 644 __le32 opts1; 645 #define RX_LEN_MASK 0x7fff 646 647 __le32 opts2; 648 #define RD_UDP_CS BIT(23) 649 #define RD_TCP_CS BIT(22) 650 #define RD_IPV6_CS BIT(20) 651 #define RD_IPV4_CS BIT(19) 652 653 __le32 opts3; 654 #define IPF BIT(23) /* IP checksum fail */ 655 #define UDPF BIT(22) /* UDP checksum fail */ 656 #define TCPF BIT(21) /* TCP checksum fail */ 657 #define RX_VLAN_TAG BIT(16) 658 659 __le32 opts4; 660 __le32 opts5; 661 __le32 opts6; 662 }; 663 664 struct tx_desc { 665 __le32 opts1; 666 #define TX_FS BIT(31) /* First segment of a packet */ 667 #define TX_LS BIT(30) /* Final segment of a packet */ 668 #define GTSENDV4 BIT(28) 669 #define GTSENDV6 BIT(27) 670 #define GTTCPHO_SHIFT 18 671 #define GTTCPHO_MAX 0x7fU 672 #define TX_LEN_MAX 0x3ffffU 673 674 __le32 opts2; 675 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 676 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 677 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 678 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 679 #define MSS_SHIFT 17 680 #define MSS_MAX 0x7ffU 681 #define TCPHO_SHIFT 17 682 #define TCPHO_MAX 0x7ffU 683 #define TX_VLAN_TAG BIT(16) 684 }; 685 686 struct r8152; 687 688 struct rx_agg { 689 struct list_head list; 690 struct urb *urb; 691 struct r8152 *context; 692 void *buffer; 693 void *head; 694 }; 695 696 struct tx_agg { 697 struct list_head list; 698 struct urb *urb; 699 struct r8152 *context; 700 void *buffer; 701 void *head; 702 u32 skb_num; 703 u32 skb_len; 704 }; 705 706 struct r8152 { 707 unsigned long flags; 708 struct usb_device *udev; 709 struct napi_struct napi; 710 struct usb_interface *intf; 711 struct net_device *netdev; 712 struct urb *intr_urb; 713 struct tx_agg tx_info[RTL8152_MAX_TX]; 714 struct rx_agg rx_info[RTL8152_MAX_RX]; 715 struct list_head rx_done, tx_free; 716 struct sk_buff_head tx_queue, rx_queue; 717 spinlock_t rx_lock, tx_lock; 718 struct delayed_work schedule, hw_phy_work; 719 struct mii_if_info mii; 720 struct mutex control; /* use for hw setting */ 721 #ifdef CONFIG_PM_SLEEP 722 struct notifier_block pm_notifier; 723 #endif 724 725 struct rtl_ops { 726 void (*init)(struct r8152 *); 727 int (*enable)(struct r8152 *); 728 void (*disable)(struct r8152 *); 729 void (*up)(struct r8152 *); 730 void (*down)(struct r8152 *); 731 void (*unload)(struct r8152 *); 732 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 733 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 734 bool (*in_nway)(struct r8152 *); 735 void (*hw_phy_cfg)(struct r8152 *); 736 void (*autosuspend_en)(struct r8152 *tp, bool enable); 737 } rtl_ops; 738 739 int intr_interval; 740 u32 saved_wolopts; 741 u32 msg_enable; 742 u32 tx_qlen; 743 u32 coalesce; 744 u16 ocp_base; 745 u16 speed; 746 u8 *intr_buff; 747 u8 version; 748 u8 duplex; 749 u8 autoneg; 750 }; 751 752 enum rtl_version { 753 RTL_VER_UNKNOWN = 0, 754 RTL_VER_01, 755 RTL_VER_02, 756 RTL_VER_03, 757 RTL_VER_04, 758 RTL_VER_05, 759 RTL_VER_06, 760 RTL_VER_07, 761 RTL_VER_08, 762 RTL_VER_09, 763 RTL_VER_MAX 764 }; 765 766 enum tx_csum_stat { 767 TX_CSUM_SUCCESS = 0, 768 TX_CSUM_TSO, 769 TX_CSUM_NONE 770 }; 771 772 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 773 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 774 */ 775 static const int multicast_filter_limit = 32; 776 static unsigned int agg_buf_sz = 16384; 777 778 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 779 VLAN_ETH_HLEN - ETH_FCS_LEN) 780 781 static 782 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 783 { 784 int ret; 785 void *tmp; 786 787 tmp = kmalloc(size, GFP_KERNEL); 788 if (!tmp) 789 return -ENOMEM; 790 791 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 792 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 793 value, index, tmp, size, 500); 794 795 memcpy(data, tmp, size); 796 kfree(tmp); 797 798 return ret; 799 } 800 801 static 802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 803 { 804 int ret; 805 void *tmp; 806 807 tmp = kmemdup(data, size, GFP_KERNEL); 808 if (!tmp) 809 return -ENOMEM; 810 811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 812 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 813 value, index, tmp, size, 500); 814 815 kfree(tmp); 816 817 return ret; 818 } 819 820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 821 void *data, u16 type) 822 { 823 u16 limit = 64; 824 int ret = 0; 825 826 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 827 return -ENODEV; 828 829 /* both size and indix must be 4 bytes align */ 830 if ((size & 3) || !size || (index & 3) || !data) 831 return -EPERM; 832 833 if ((u32)index + (u32)size > 0xffff) 834 return -EPERM; 835 836 while (size) { 837 if (size > limit) { 838 ret = get_registers(tp, index, type, limit, data); 839 if (ret < 0) 840 break; 841 842 index += limit; 843 data += limit; 844 size -= limit; 845 } else { 846 ret = get_registers(tp, index, type, size, data); 847 if (ret < 0) 848 break; 849 850 index += size; 851 data += size; 852 size = 0; 853 break; 854 } 855 } 856 857 if (ret == -ENODEV) 858 set_bit(RTL8152_UNPLUG, &tp->flags); 859 860 return ret; 861 } 862 863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 864 u16 size, void *data, u16 type) 865 { 866 int ret; 867 u16 byteen_start, byteen_end, byen; 868 u16 limit = 512; 869 870 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 871 return -ENODEV; 872 873 /* both size and indix must be 4 bytes align */ 874 if ((size & 3) || !size || (index & 3) || !data) 875 return -EPERM; 876 877 if ((u32)index + (u32)size > 0xffff) 878 return -EPERM; 879 880 byteen_start = byteen & BYTE_EN_START_MASK; 881 byteen_end = byteen & BYTE_EN_END_MASK; 882 883 byen = byteen_start | (byteen_start << 4); 884 ret = set_registers(tp, index, type | byen, 4, data); 885 if (ret < 0) 886 goto error1; 887 888 index += 4; 889 data += 4; 890 size -= 4; 891 892 if (size) { 893 size -= 4; 894 895 while (size) { 896 if (size > limit) { 897 ret = set_registers(tp, index, 898 type | BYTE_EN_DWORD, 899 limit, data); 900 if (ret < 0) 901 goto error1; 902 903 index += limit; 904 data += limit; 905 size -= limit; 906 } else { 907 ret = set_registers(tp, index, 908 type | BYTE_EN_DWORD, 909 size, data); 910 if (ret < 0) 911 goto error1; 912 913 index += size; 914 data += size; 915 size = 0; 916 break; 917 } 918 } 919 920 byen = byteen_end | (byteen_end >> 4); 921 ret = set_registers(tp, index, type | byen, 4, data); 922 if (ret < 0) 923 goto error1; 924 } 925 926 error1: 927 if (ret == -ENODEV) 928 set_bit(RTL8152_UNPLUG, &tp->flags); 929 930 return ret; 931 } 932 933 static inline 934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 935 { 936 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 937 } 938 939 static inline 940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 941 { 942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 943 } 944 945 static inline 946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 947 { 948 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 949 } 950 951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 952 { 953 __le32 data; 954 955 generic_ocp_read(tp, index, sizeof(data), &data, type); 956 957 return __le32_to_cpu(data); 958 } 959 960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 961 { 962 __le32 tmp = __cpu_to_le32(data); 963 964 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 965 } 966 967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 968 { 969 u32 data; 970 __le32 tmp; 971 u16 byen = BYTE_EN_WORD; 972 u8 shift = index & 2; 973 974 index &= ~3; 975 byen <<= shift; 976 977 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 978 979 data = __le32_to_cpu(tmp); 980 data >>= (shift * 8); 981 data &= 0xffff; 982 983 return (u16)data; 984 } 985 986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 987 { 988 u32 mask = 0xffff; 989 __le32 tmp; 990 u16 byen = BYTE_EN_WORD; 991 u8 shift = index & 2; 992 993 data &= mask; 994 995 if (index & 2) { 996 byen <<= shift; 997 mask <<= (shift * 8); 998 data <<= (shift * 8); 999 index &= ~3; 1000 } 1001 1002 tmp = __cpu_to_le32(data); 1003 1004 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1005 } 1006 1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1008 { 1009 u32 data; 1010 __le32 tmp; 1011 u8 shift = index & 3; 1012 1013 index &= ~3; 1014 1015 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1016 1017 data = __le32_to_cpu(tmp); 1018 data >>= (shift * 8); 1019 data &= 0xff; 1020 1021 return (u8)data; 1022 } 1023 1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1025 { 1026 u32 mask = 0xff; 1027 __le32 tmp; 1028 u16 byen = BYTE_EN_BYTE; 1029 u8 shift = index & 3; 1030 1031 data &= mask; 1032 1033 if (index & 3) { 1034 byen <<= shift; 1035 mask <<= (shift * 8); 1036 data <<= (shift * 8); 1037 index &= ~3; 1038 } 1039 1040 tmp = __cpu_to_le32(data); 1041 1042 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1043 } 1044 1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1046 { 1047 u16 ocp_base, ocp_index; 1048 1049 ocp_base = addr & 0xf000; 1050 if (ocp_base != tp->ocp_base) { 1051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1052 tp->ocp_base = ocp_base; 1053 } 1054 1055 ocp_index = (addr & 0x0fff) | 0xb000; 1056 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1057 } 1058 1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1060 { 1061 u16 ocp_base, ocp_index; 1062 1063 ocp_base = addr & 0xf000; 1064 if (ocp_base != tp->ocp_base) { 1065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1066 tp->ocp_base = ocp_base; 1067 } 1068 1069 ocp_index = (addr & 0x0fff) | 0xb000; 1070 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1071 } 1072 1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1074 { 1075 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1076 } 1077 1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1079 { 1080 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1081 } 1082 1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1084 { 1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1086 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1087 } 1088 1089 static u16 sram_read(struct r8152 *tp, u16 addr) 1090 { 1091 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1092 return ocp_reg_read(tp, OCP_SRAM_DATA); 1093 } 1094 1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1096 { 1097 struct r8152 *tp = netdev_priv(netdev); 1098 int ret; 1099 1100 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1101 return -ENODEV; 1102 1103 if (phy_id != R8152_PHY_ID) 1104 return -EINVAL; 1105 1106 ret = r8152_mdio_read(tp, reg); 1107 1108 return ret; 1109 } 1110 1111 static 1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1113 { 1114 struct r8152 *tp = netdev_priv(netdev); 1115 1116 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1117 return; 1118 1119 if (phy_id != R8152_PHY_ID) 1120 return; 1121 1122 r8152_mdio_write(tp, reg, val); 1123 } 1124 1125 static int 1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1127 1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1129 { 1130 struct r8152 *tp = netdev_priv(netdev); 1131 struct sockaddr *addr = p; 1132 int ret = -EADDRNOTAVAIL; 1133 1134 if (!is_valid_ether_addr(addr->sa_data)) 1135 goto out1; 1136 1137 ret = usb_autopm_get_interface(tp->intf); 1138 if (ret < 0) 1139 goto out1; 1140 1141 mutex_lock(&tp->control); 1142 1143 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1144 1145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1146 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1148 1149 mutex_unlock(&tp->control); 1150 1151 usb_autopm_put_interface(tp->intf); 1152 out1: 1153 return ret; 1154 } 1155 1156 /* Devices containing proper chips can support a persistent 1157 * host system provided MAC address. 1158 * Examples of this are Dell TB15 and Dell WD15 docks 1159 */ 1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1161 { 1162 acpi_status status; 1163 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1164 union acpi_object *obj; 1165 int ret = -EINVAL; 1166 u32 ocp_data; 1167 unsigned char buf[6]; 1168 1169 /* test for -AD variant of RTL8153 */ 1170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1171 if ((ocp_data & AD_MASK) == 0x1000) { 1172 /* test for MAC address pass-through bit */ 1173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1174 if ((ocp_data & PASS_THRU_MASK) != 1) { 1175 netif_dbg(tp, probe, tp->netdev, 1176 "No efuse for RTL8153-AD MAC pass through\n"); 1177 return -ENODEV; 1178 } 1179 } else { 1180 /* test for RTL8153-BND and RTL8153-BD */ 1181 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1182 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1183 netif_dbg(tp, probe, tp->netdev, 1184 "Invalid variant for MAC pass through\n"); 1185 return -ENODEV; 1186 } 1187 } 1188 1189 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1190 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1191 obj = (union acpi_object *)buffer.pointer; 1192 if (!ACPI_SUCCESS(status)) 1193 return -ENODEV; 1194 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1195 netif_warn(tp, probe, tp->netdev, 1196 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1197 obj->type, obj->string.length); 1198 goto amacout; 1199 } 1200 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1201 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1202 netif_warn(tp, probe, tp->netdev, 1203 "Invalid header when reading pass-thru MAC addr\n"); 1204 goto amacout; 1205 } 1206 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1207 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1208 netif_warn(tp, probe, tp->netdev, 1209 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1210 ret, buf); 1211 ret = -EINVAL; 1212 goto amacout; 1213 } 1214 memcpy(sa->sa_data, buf, 6); 1215 netif_info(tp, probe, tp->netdev, 1216 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1217 1218 amacout: 1219 kfree(obj); 1220 return ret; 1221 } 1222 1223 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1224 { 1225 struct net_device *dev = tp->netdev; 1226 int ret; 1227 1228 sa->sa_family = dev->type; 1229 1230 if (tp->version == RTL_VER_01) { 1231 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1232 } else { 1233 /* if device doesn't support MAC pass through this will 1234 * be expected to be non-zero 1235 */ 1236 ret = vendor_mac_passthru_addr_read(tp, sa); 1237 if (ret < 0) 1238 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1239 } 1240 1241 if (ret < 0) { 1242 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1243 } else if (!is_valid_ether_addr(sa->sa_data)) { 1244 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1245 sa->sa_data); 1246 eth_hw_addr_random(dev); 1247 ether_addr_copy(sa->sa_data, dev->dev_addr); 1248 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1249 sa->sa_data); 1250 return 0; 1251 } 1252 1253 return ret; 1254 } 1255 1256 static int set_ethernet_addr(struct r8152 *tp) 1257 { 1258 struct net_device *dev = tp->netdev; 1259 struct sockaddr sa; 1260 int ret; 1261 1262 ret = determine_ethernet_addr(tp, &sa); 1263 if (ret < 0) 1264 return ret; 1265 1266 if (tp->version == RTL_VER_01) 1267 ether_addr_copy(dev->dev_addr, sa.sa_data); 1268 else 1269 ret = rtl8152_set_mac_address(dev, &sa); 1270 1271 return ret; 1272 } 1273 1274 static void read_bulk_callback(struct urb *urb) 1275 { 1276 struct net_device *netdev; 1277 int status = urb->status; 1278 struct rx_agg *agg; 1279 struct r8152 *tp; 1280 unsigned long flags; 1281 1282 agg = urb->context; 1283 if (!agg) 1284 return; 1285 1286 tp = agg->context; 1287 if (!tp) 1288 return; 1289 1290 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1291 return; 1292 1293 if (!test_bit(WORK_ENABLE, &tp->flags)) 1294 return; 1295 1296 netdev = tp->netdev; 1297 1298 /* When link down, the driver would cancel all bulks. */ 1299 /* This avoid the re-submitting bulk */ 1300 if (!netif_carrier_ok(netdev)) 1301 return; 1302 1303 usb_mark_last_busy(tp->udev); 1304 1305 switch (status) { 1306 case 0: 1307 if (urb->actual_length < ETH_ZLEN) 1308 break; 1309 1310 spin_lock_irqsave(&tp->rx_lock, flags); 1311 list_add_tail(&agg->list, &tp->rx_done); 1312 spin_unlock_irqrestore(&tp->rx_lock, flags); 1313 napi_schedule(&tp->napi); 1314 return; 1315 case -ESHUTDOWN: 1316 set_bit(RTL8152_UNPLUG, &tp->flags); 1317 netif_device_detach(tp->netdev); 1318 return; 1319 case -ENOENT: 1320 return; /* the urb is in unlink state */ 1321 case -ETIME: 1322 if (net_ratelimit()) 1323 netdev_warn(netdev, "maybe reset is needed?\n"); 1324 break; 1325 default: 1326 if (net_ratelimit()) 1327 netdev_warn(netdev, "Rx status %d\n", status); 1328 break; 1329 } 1330 1331 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1332 } 1333 1334 static void write_bulk_callback(struct urb *urb) 1335 { 1336 struct net_device_stats *stats; 1337 struct net_device *netdev; 1338 struct tx_agg *agg; 1339 struct r8152 *tp; 1340 unsigned long flags; 1341 int status = urb->status; 1342 1343 agg = urb->context; 1344 if (!agg) 1345 return; 1346 1347 tp = agg->context; 1348 if (!tp) 1349 return; 1350 1351 netdev = tp->netdev; 1352 stats = &netdev->stats; 1353 if (status) { 1354 if (net_ratelimit()) 1355 netdev_warn(netdev, "Tx status %d\n", status); 1356 stats->tx_errors += agg->skb_num; 1357 } else { 1358 stats->tx_packets += agg->skb_num; 1359 stats->tx_bytes += agg->skb_len; 1360 } 1361 1362 spin_lock_irqsave(&tp->tx_lock, flags); 1363 list_add_tail(&agg->list, &tp->tx_free); 1364 spin_unlock_irqrestore(&tp->tx_lock, flags); 1365 1366 usb_autopm_put_interface_async(tp->intf); 1367 1368 if (!netif_carrier_ok(netdev)) 1369 return; 1370 1371 if (!test_bit(WORK_ENABLE, &tp->flags)) 1372 return; 1373 1374 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1375 return; 1376 1377 if (!skb_queue_empty(&tp->tx_queue)) 1378 napi_schedule(&tp->napi); 1379 } 1380 1381 static void intr_callback(struct urb *urb) 1382 { 1383 struct r8152 *tp; 1384 __le16 *d; 1385 int status = urb->status; 1386 int res; 1387 1388 tp = urb->context; 1389 if (!tp) 1390 return; 1391 1392 if (!test_bit(WORK_ENABLE, &tp->flags)) 1393 return; 1394 1395 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1396 return; 1397 1398 switch (status) { 1399 case 0: /* success */ 1400 break; 1401 case -ECONNRESET: /* unlink */ 1402 case -ESHUTDOWN: 1403 netif_device_detach(tp->netdev); 1404 /* fall through */ 1405 case -ENOENT: 1406 case -EPROTO: 1407 netif_info(tp, intr, tp->netdev, 1408 "Stop submitting intr, status %d\n", status); 1409 return; 1410 case -EOVERFLOW: 1411 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1412 goto resubmit; 1413 /* -EPIPE: should clear the halt */ 1414 default: 1415 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1416 goto resubmit; 1417 } 1418 1419 d = urb->transfer_buffer; 1420 if (INTR_LINK & __le16_to_cpu(d[0])) { 1421 if (!netif_carrier_ok(tp->netdev)) { 1422 set_bit(RTL8152_LINK_CHG, &tp->flags); 1423 schedule_delayed_work(&tp->schedule, 0); 1424 } 1425 } else { 1426 if (netif_carrier_ok(tp->netdev)) { 1427 netif_stop_queue(tp->netdev); 1428 set_bit(RTL8152_LINK_CHG, &tp->flags); 1429 schedule_delayed_work(&tp->schedule, 0); 1430 } 1431 } 1432 1433 resubmit: 1434 res = usb_submit_urb(urb, GFP_ATOMIC); 1435 if (res == -ENODEV) { 1436 set_bit(RTL8152_UNPLUG, &tp->flags); 1437 netif_device_detach(tp->netdev); 1438 } else if (res) { 1439 netif_err(tp, intr, tp->netdev, 1440 "can't resubmit intr, status %d\n", res); 1441 } 1442 } 1443 1444 static inline void *rx_agg_align(void *data) 1445 { 1446 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1447 } 1448 1449 static inline void *tx_agg_align(void *data) 1450 { 1451 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1452 } 1453 1454 static void free_all_mem(struct r8152 *tp) 1455 { 1456 int i; 1457 1458 for (i = 0; i < RTL8152_MAX_RX; i++) { 1459 usb_free_urb(tp->rx_info[i].urb); 1460 tp->rx_info[i].urb = NULL; 1461 1462 kfree(tp->rx_info[i].buffer); 1463 tp->rx_info[i].buffer = NULL; 1464 tp->rx_info[i].head = NULL; 1465 } 1466 1467 for (i = 0; i < RTL8152_MAX_TX; i++) { 1468 usb_free_urb(tp->tx_info[i].urb); 1469 tp->tx_info[i].urb = NULL; 1470 1471 kfree(tp->tx_info[i].buffer); 1472 tp->tx_info[i].buffer = NULL; 1473 tp->tx_info[i].head = NULL; 1474 } 1475 1476 usb_free_urb(tp->intr_urb); 1477 tp->intr_urb = NULL; 1478 1479 kfree(tp->intr_buff); 1480 tp->intr_buff = NULL; 1481 } 1482 1483 static int alloc_all_mem(struct r8152 *tp) 1484 { 1485 struct net_device *netdev = tp->netdev; 1486 struct usb_interface *intf = tp->intf; 1487 struct usb_host_interface *alt = intf->cur_altsetting; 1488 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1489 struct urb *urb; 1490 int node, i; 1491 u8 *buf; 1492 1493 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1494 1495 spin_lock_init(&tp->rx_lock); 1496 spin_lock_init(&tp->tx_lock); 1497 INIT_LIST_HEAD(&tp->tx_free); 1498 INIT_LIST_HEAD(&tp->rx_done); 1499 skb_queue_head_init(&tp->tx_queue); 1500 skb_queue_head_init(&tp->rx_queue); 1501 1502 for (i = 0; i < RTL8152_MAX_RX; i++) { 1503 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1504 if (!buf) 1505 goto err1; 1506 1507 if (buf != rx_agg_align(buf)) { 1508 kfree(buf); 1509 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1510 node); 1511 if (!buf) 1512 goto err1; 1513 } 1514 1515 urb = usb_alloc_urb(0, GFP_KERNEL); 1516 if (!urb) { 1517 kfree(buf); 1518 goto err1; 1519 } 1520 1521 INIT_LIST_HEAD(&tp->rx_info[i].list); 1522 tp->rx_info[i].context = tp; 1523 tp->rx_info[i].urb = urb; 1524 tp->rx_info[i].buffer = buf; 1525 tp->rx_info[i].head = rx_agg_align(buf); 1526 } 1527 1528 for (i = 0; i < RTL8152_MAX_TX; i++) { 1529 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1530 if (!buf) 1531 goto err1; 1532 1533 if (buf != tx_agg_align(buf)) { 1534 kfree(buf); 1535 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1536 node); 1537 if (!buf) 1538 goto err1; 1539 } 1540 1541 urb = usb_alloc_urb(0, GFP_KERNEL); 1542 if (!urb) { 1543 kfree(buf); 1544 goto err1; 1545 } 1546 1547 INIT_LIST_HEAD(&tp->tx_info[i].list); 1548 tp->tx_info[i].context = tp; 1549 tp->tx_info[i].urb = urb; 1550 tp->tx_info[i].buffer = buf; 1551 tp->tx_info[i].head = tx_agg_align(buf); 1552 1553 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1554 } 1555 1556 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1557 if (!tp->intr_urb) 1558 goto err1; 1559 1560 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1561 if (!tp->intr_buff) 1562 goto err1; 1563 1564 tp->intr_interval = (int)ep_intr->desc.bInterval; 1565 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1566 tp->intr_buff, INTBUFSIZE, intr_callback, 1567 tp, tp->intr_interval); 1568 1569 return 0; 1570 1571 err1: 1572 free_all_mem(tp); 1573 return -ENOMEM; 1574 } 1575 1576 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1577 { 1578 struct tx_agg *agg = NULL; 1579 unsigned long flags; 1580 1581 if (list_empty(&tp->tx_free)) 1582 return NULL; 1583 1584 spin_lock_irqsave(&tp->tx_lock, flags); 1585 if (!list_empty(&tp->tx_free)) { 1586 struct list_head *cursor; 1587 1588 cursor = tp->tx_free.next; 1589 list_del_init(cursor); 1590 agg = list_entry(cursor, struct tx_agg, list); 1591 } 1592 spin_unlock_irqrestore(&tp->tx_lock, flags); 1593 1594 return agg; 1595 } 1596 1597 /* r8152_csum_workaround() 1598 * The hw limites the value the transport offset. When the offset is out of the 1599 * range, calculate the checksum by sw. 1600 */ 1601 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1602 struct sk_buff_head *list) 1603 { 1604 if (skb_shinfo(skb)->gso_size) { 1605 netdev_features_t features = tp->netdev->features; 1606 struct sk_buff_head seg_list; 1607 struct sk_buff *segs, *nskb; 1608 1609 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1610 segs = skb_gso_segment(skb, features); 1611 if (IS_ERR(segs) || !segs) 1612 goto drop; 1613 1614 __skb_queue_head_init(&seg_list); 1615 1616 do { 1617 nskb = segs; 1618 segs = segs->next; 1619 nskb->next = NULL; 1620 __skb_queue_tail(&seg_list, nskb); 1621 } while (segs); 1622 1623 skb_queue_splice(&seg_list, list); 1624 dev_kfree_skb(skb); 1625 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1626 if (skb_checksum_help(skb) < 0) 1627 goto drop; 1628 1629 __skb_queue_head(list, skb); 1630 } else { 1631 struct net_device_stats *stats; 1632 1633 drop: 1634 stats = &tp->netdev->stats; 1635 stats->tx_dropped++; 1636 dev_kfree_skb(skb); 1637 } 1638 } 1639 1640 /* msdn_giant_send_check() 1641 * According to the document of microsoft, the TCP Pseudo Header excludes the 1642 * packet length for IPv6 TCP large packets. 1643 */ 1644 static int msdn_giant_send_check(struct sk_buff *skb) 1645 { 1646 const struct ipv6hdr *ipv6h; 1647 struct tcphdr *th; 1648 int ret; 1649 1650 ret = skb_cow_head(skb, 0); 1651 if (ret) 1652 return ret; 1653 1654 ipv6h = ipv6_hdr(skb); 1655 th = tcp_hdr(skb); 1656 1657 th->check = 0; 1658 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1659 1660 return ret; 1661 } 1662 1663 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1664 { 1665 if (skb_vlan_tag_present(skb)) { 1666 u32 opts2; 1667 1668 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1669 desc->opts2 |= cpu_to_le32(opts2); 1670 } 1671 } 1672 1673 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1674 { 1675 u32 opts2 = le32_to_cpu(desc->opts2); 1676 1677 if (opts2 & RX_VLAN_TAG) 1678 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1679 swab16(opts2 & 0xffff)); 1680 } 1681 1682 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1683 struct sk_buff *skb, u32 len, u32 transport_offset) 1684 { 1685 u32 mss = skb_shinfo(skb)->gso_size; 1686 u32 opts1, opts2 = 0; 1687 int ret = TX_CSUM_SUCCESS; 1688 1689 WARN_ON_ONCE(len > TX_LEN_MAX); 1690 1691 opts1 = len | TX_FS | TX_LS; 1692 1693 if (mss) { 1694 if (transport_offset > GTTCPHO_MAX) { 1695 netif_warn(tp, tx_err, tp->netdev, 1696 "Invalid transport offset 0x%x for TSO\n", 1697 transport_offset); 1698 ret = TX_CSUM_TSO; 1699 goto unavailable; 1700 } 1701 1702 switch (vlan_get_protocol(skb)) { 1703 case htons(ETH_P_IP): 1704 opts1 |= GTSENDV4; 1705 break; 1706 1707 case htons(ETH_P_IPV6): 1708 if (msdn_giant_send_check(skb)) { 1709 ret = TX_CSUM_TSO; 1710 goto unavailable; 1711 } 1712 opts1 |= GTSENDV6; 1713 break; 1714 1715 default: 1716 WARN_ON_ONCE(1); 1717 break; 1718 } 1719 1720 opts1 |= transport_offset << GTTCPHO_SHIFT; 1721 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1722 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1723 u8 ip_protocol; 1724 1725 if (transport_offset > TCPHO_MAX) { 1726 netif_warn(tp, tx_err, tp->netdev, 1727 "Invalid transport offset 0x%x\n", 1728 transport_offset); 1729 ret = TX_CSUM_NONE; 1730 goto unavailable; 1731 } 1732 1733 switch (vlan_get_protocol(skb)) { 1734 case htons(ETH_P_IP): 1735 opts2 |= IPV4_CS; 1736 ip_protocol = ip_hdr(skb)->protocol; 1737 break; 1738 1739 case htons(ETH_P_IPV6): 1740 opts2 |= IPV6_CS; 1741 ip_protocol = ipv6_hdr(skb)->nexthdr; 1742 break; 1743 1744 default: 1745 ip_protocol = IPPROTO_RAW; 1746 break; 1747 } 1748 1749 if (ip_protocol == IPPROTO_TCP) 1750 opts2 |= TCP_CS; 1751 else if (ip_protocol == IPPROTO_UDP) 1752 opts2 |= UDP_CS; 1753 else 1754 WARN_ON_ONCE(1); 1755 1756 opts2 |= transport_offset << TCPHO_SHIFT; 1757 } 1758 1759 desc->opts2 = cpu_to_le32(opts2); 1760 desc->opts1 = cpu_to_le32(opts1); 1761 1762 unavailable: 1763 return ret; 1764 } 1765 1766 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1767 { 1768 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1769 int remain, ret; 1770 u8 *tx_data; 1771 1772 __skb_queue_head_init(&skb_head); 1773 spin_lock(&tx_queue->lock); 1774 skb_queue_splice_init(tx_queue, &skb_head); 1775 spin_unlock(&tx_queue->lock); 1776 1777 tx_data = agg->head; 1778 agg->skb_num = 0; 1779 agg->skb_len = 0; 1780 remain = agg_buf_sz; 1781 1782 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1783 struct tx_desc *tx_desc; 1784 struct sk_buff *skb; 1785 unsigned int len; 1786 u32 offset; 1787 1788 skb = __skb_dequeue(&skb_head); 1789 if (!skb) 1790 break; 1791 1792 len = skb->len + sizeof(*tx_desc); 1793 1794 if (len > remain) { 1795 __skb_queue_head(&skb_head, skb); 1796 break; 1797 } 1798 1799 tx_data = tx_agg_align(tx_data); 1800 tx_desc = (struct tx_desc *)tx_data; 1801 1802 offset = (u32)skb_transport_offset(skb); 1803 1804 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1805 r8152_csum_workaround(tp, skb, &skb_head); 1806 continue; 1807 } 1808 1809 rtl_tx_vlan_tag(tx_desc, skb); 1810 1811 tx_data += sizeof(*tx_desc); 1812 1813 len = skb->len; 1814 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1815 struct net_device_stats *stats = &tp->netdev->stats; 1816 1817 stats->tx_dropped++; 1818 dev_kfree_skb_any(skb); 1819 tx_data -= sizeof(*tx_desc); 1820 continue; 1821 } 1822 1823 tx_data += len; 1824 agg->skb_len += len; 1825 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1826 1827 dev_kfree_skb_any(skb); 1828 1829 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1830 1831 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1832 break; 1833 } 1834 1835 if (!skb_queue_empty(&skb_head)) { 1836 spin_lock(&tx_queue->lock); 1837 skb_queue_splice(&skb_head, tx_queue); 1838 spin_unlock(&tx_queue->lock); 1839 } 1840 1841 netif_tx_lock(tp->netdev); 1842 1843 if (netif_queue_stopped(tp->netdev) && 1844 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1845 netif_wake_queue(tp->netdev); 1846 1847 netif_tx_unlock(tp->netdev); 1848 1849 ret = usb_autopm_get_interface_async(tp->intf); 1850 if (ret < 0) 1851 goto out_tx_fill; 1852 1853 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1854 agg->head, (int)(tx_data - (u8 *)agg->head), 1855 (usb_complete_t)write_bulk_callback, agg); 1856 1857 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1858 if (ret < 0) 1859 usb_autopm_put_interface_async(tp->intf); 1860 1861 out_tx_fill: 1862 return ret; 1863 } 1864 1865 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1866 { 1867 u8 checksum = CHECKSUM_NONE; 1868 u32 opts2, opts3; 1869 1870 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1871 goto return_result; 1872 1873 opts2 = le32_to_cpu(rx_desc->opts2); 1874 opts3 = le32_to_cpu(rx_desc->opts3); 1875 1876 if (opts2 & RD_IPV4_CS) { 1877 if (opts3 & IPF) 1878 checksum = CHECKSUM_NONE; 1879 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1880 checksum = CHECKSUM_UNNECESSARY; 1881 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1882 checksum = CHECKSUM_UNNECESSARY; 1883 } else if (opts2 & RD_IPV6_CS) { 1884 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1885 checksum = CHECKSUM_UNNECESSARY; 1886 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1887 checksum = CHECKSUM_UNNECESSARY; 1888 } 1889 1890 return_result: 1891 return checksum; 1892 } 1893 1894 static int rx_bottom(struct r8152 *tp, int budget) 1895 { 1896 unsigned long flags; 1897 struct list_head *cursor, *next, rx_queue; 1898 int ret = 0, work_done = 0; 1899 struct napi_struct *napi = &tp->napi; 1900 1901 if (!skb_queue_empty(&tp->rx_queue)) { 1902 while (work_done < budget) { 1903 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1904 struct net_device *netdev = tp->netdev; 1905 struct net_device_stats *stats = &netdev->stats; 1906 unsigned int pkt_len; 1907 1908 if (!skb) 1909 break; 1910 1911 pkt_len = skb->len; 1912 napi_gro_receive(napi, skb); 1913 work_done++; 1914 stats->rx_packets++; 1915 stats->rx_bytes += pkt_len; 1916 } 1917 } 1918 1919 if (list_empty(&tp->rx_done)) 1920 goto out1; 1921 1922 INIT_LIST_HEAD(&rx_queue); 1923 spin_lock_irqsave(&tp->rx_lock, flags); 1924 list_splice_init(&tp->rx_done, &rx_queue); 1925 spin_unlock_irqrestore(&tp->rx_lock, flags); 1926 1927 list_for_each_safe(cursor, next, &rx_queue) { 1928 struct rx_desc *rx_desc; 1929 struct rx_agg *agg; 1930 int len_used = 0; 1931 struct urb *urb; 1932 u8 *rx_data; 1933 1934 list_del_init(cursor); 1935 1936 agg = list_entry(cursor, struct rx_agg, list); 1937 urb = agg->urb; 1938 if (urb->actual_length < ETH_ZLEN) 1939 goto submit; 1940 1941 rx_desc = agg->head; 1942 rx_data = agg->head; 1943 len_used += sizeof(struct rx_desc); 1944 1945 while (urb->actual_length > len_used) { 1946 struct net_device *netdev = tp->netdev; 1947 struct net_device_stats *stats = &netdev->stats; 1948 unsigned int pkt_len; 1949 struct sk_buff *skb; 1950 1951 /* limite the skb numbers for rx_queue */ 1952 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1953 break; 1954 1955 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1956 if (pkt_len < ETH_ZLEN) 1957 break; 1958 1959 len_used += pkt_len; 1960 if (urb->actual_length < len_used) 1961 break; 1962 1963 pkt_len -= ETH_FCS_LEN; 1964 rx_data += sizeof(struct rx_desc); 1965 1966 skb = napi_alloc_skb(napi, pkt_len); 1967 if (!skb) { 1968 stats->rx_dropped++; 1969 goto find_next_rx; 1970 } 1971 1972 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1973 memcpy(skb->data, rx_data, pkt_len); 1974 skb_put(skb, pkt_len); 1975 skb->protocol = eth_type_trans(skb, netdev); 1976 rtl_rx_vlan_tag(rx_desc, skb); 1977 if (work_done < budget) { 1978 napi_gro_receive(napi, skb); 1979 work_done++; 1980 stats->rx_packets++; 1981 stats->rx_bytes += pkt_len; 1982 } else { 1983 __skb_queue_tail(&tp->rx_queue, skb); 1984 } 1985 1986 find_next_rx: 1987 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1988 rx_desc = (struct rx_desc *)rx_data; 1989 len_used = (int)(rx_data - (u8 *)agg->head); 1990 len_used += sizeof(struct rx_desc); 1991 } 1992 1993 submit: 1994 if (!ret) { 1995 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1996 } else { 1997 urb->actual_length = 0; 1998 list_add_tail(&agg->list, next); 1999 } 2000 } 2001 2002 if (!list_empty(&rx_queue)) { 2003 spin_lock_irqsave(&tp->rx_lock, flags); 2004 list_splice_tail(&rx_queue, &tp->rx_done); 2005 spin_unlock_irqrestore(&tp->rx_lock, flags); 2006 } 2007 2008 out1: 2009 return work_done; 2010 } 2011 2012 static void tx_bottom(struct r8152 *tp) 2013 { 2014 int res; 2015 2016 do { 2017 struct tx_agg *agg; 2018 2019 if (skb_queue_empty(&tp->tx_queue)) 2020 break; 2021 2022 agg = r8152_get_tx_agg(tp); 2023 if (!agg) 2024 break; 2025 2026 res = r8152_tx_agg_fill(tp, agg); 2027 if (res) { 2028 struct net_device *netdev = tp->netdev; 2029 2030 if (res == -ENODEV) { 2031 set_bit(RTL8152_UNPLUG, &tp->flags); 2032 netif_device_detach(netdev); 2033 } else { 2034 struct net_device_stats *stats = &netdev->stats; 2035 unsigned long flags; 2036 2037 netif_warn(tp, tx_err, netdev, 2038 "failed tx_urb %d\n", res); 2039 stats->tx_dropped += agg->skb_num; 2040 2041 spin_lock_irqsave(&tp->tx_lock, flags); 2042 list_add_tail(&agg->list, &tp->tx_free); 2043 spin_unlock_irqrestore(&tp->tx_lock, flags); 2044 } 2045 } 2046 } while (res == 0); 2047 } 2048 2049 static void bottom_half(struct r8152 *tp) 2050 { 2051 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2052 return; 2053 2054 if (!test_bit(WORK_ENABLE, &tp->flags)) 2055 return; 2056 2057 /* When link down, the driver would cancel all bulks. */ 2058 /* This avoid the re-submitting bulk */ 2059 if (!netif_carrier_ok(tp->netdev)) 2060 return; 2061 2062 clear_bit(SCHEDULE_NAPI, &tp->flags); 2063 2064 tx_bottom(tp); 2065 } 2066 2067 static int r8152_poll(struct napi_struct *napi, int budget) 2068 { 2069 struct r8152 *tp = container_of(napi, struct r8152, napi); 2070 int work_done; 2071 2072 work_done = rx_bottom(tp, budget); 2073 bottom_half(tp); 2074 2075 if (work_done < budget) { 2076 if (!napi_complete_done(napi, work_done)) 2077 goto out; 2078 if (!list_empty(&tp->rx_done)) 2079 napi_schedule(napi); 2080 else if (!skb_queue_empty(&tp->tx_queue) && 2081 !list_empty(&tp->tx_free)) 2082 napi_schedule(napi); 2083 } 2084 2085 out: 2086 return work_done; 2087 } 2088 2089 static 2090 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2091 { 2092 int ret; 2093 2094 /* The rx would be stopped, so skip submitting */ 2095 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2096 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2097 return 0; 2098 2099 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2100 agg->head, agg_buf_sz, 2101 (usb_complete_t)read_bulk_callback, agg); 2102 2103 ret = usb_submit_urb(agg->urb, mem_flags); 2104 if (ret == -ENODEV) { 2105 set_bit(RTL8152_UNPLUG, &tp->flags); 2106 netif_device_detach(tp->netdev); 2107 } else if (ret) { 2108 struct urb *urb = agg->urb; 2109 unsigned long flags; 2110 2111 urb->actual_length = 0; 2112 spin_lock_irqsave(&tp->rx_lock, flags); 2113 list_add_tail(&agg->list, &tp->rx_done); 2114 spin_unlock_irqrestore(&tp->rx_lock, flags); 2115 2116 netif_err(tp, rx_err, tp->netdev, 2117 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2118 2119 napi_schedule(&tp->napi); 2120 } 2121 2122 return ret; 2123 } 2124 2125 static void rtl_drop_queued_tx(struct r8152 *tp) 2126 { 2127 struct net_device_stats *stats = &tp->netdev->stats; 2128 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2129 struct sk_buff *skb; 2130 2131 if (skb_queue_empty(tx_queue)) 2132 return; 2133 2134 __skb_queue_head_init(&skb_head); 2135 spin_lock_bh(&tx_queue->lock); 2136 skb_queue_splice_init(tx_queue, &skb_head); 2137 spin_unlock_bh(&tx_queue->lock); 2138 2139 while ((skb = __skb_dequeue(&skb_head))) { 2140 dev_kfree_skb(skb); 2141 stats->tx_dropped++; 2142 } 2143 } 2144 2145 static void rtl8152_tx_timeout(struct net_device *netdev) 2146 { 2147 struct r8152 *tp = netdev_priv(netdev); 2148 2149 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2150 2151 usb_queue_reset_device(tp->intf); 2152 } 2153 2154 static void rtl8152_set_rx_mode(struct net_device *netdev) 2155 { 2156 struct r8152 *tp = netdev_priv(netdev); 2157 2158 if (netif_carrier_ok(netdev)) { 2159 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2160 schedule_delayed_work(&tp->schedule, 0); 2161 } 2162 } 2163 2164 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2165 { 2166 struct r8152 *tp = netdev_priv(netdev); 2167 u32 mc_filter[2]; /* Multicast hash filter */ 2168 __le32 tmp[2]; 2169 u32 ocp_data; 2170 2171 netif_stop_queue(netdev); 2172 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2173 ocp_data &= ~RCR_ACPT_ALL; 2174 ocp_data |= RCR_AB | RCR_APM; 2175 2176 if (netdev->flags & IFF_PROMISC) { 2177 /* Unconditionally log net taps. */ 2178 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2179 ocp_data |= RCR_AM | RCR_AAP; 2180 mc_filter[1] = 0xffffffff; 2181 mc_filter[0] = 0xffffffff; 2182 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2183 (netdev->flags & IFF_ALLMULTI)) { 2184 /* Too many to filter perfectly -- accept all multicasts. */ 2185 ocp_data |= RCR_AM; 2186 mc_filter[1] = 0xffffffff; 2187 mc_filter[0] = 0xffffffff; 2188 } else { 2189 struct netdev_hw_addr *ha; 2190 2191 mc_filter[1] = 0; 2192 mc_filter[0] = 0; 2193 netdev_for_each_mc_addr(ha, netdev) { 2194 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2195 2196 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2197 ocp_data |= RCR_AM; 2198 } 2199 } 2200 2201 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2202 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2203 2204 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2205 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2206 netif_wake_queue(netdev); 2207 } 2208 2209 static netdev_features_t 2210 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2211 netdev_features_t features) 2212 { 2213 u32 mss = skb_shinfo(skb)->gso_size; 2214 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2215 int offset = skb_transport_offset(skb); 2216 2217 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2218 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2219 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2220 features &= ~NETIF_F_GSO_MASK; 2221 2222 return features; 2223 } 2224 2225 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2226 struct net_device *netdev) 2227 { 2228 struct r8152 *tp = netdev_priv(netdev); 2229 2230 skb_tx_timestamp(skb); 2231 2232 skb_queue_tail(&tp->tx_queue, skb); 2233 2234 if (!list_empty(&tp->tx_free)) { 2235 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2236 set_bit(SCHEDULE_NAPI, &tp->flags); 2237 schedule_delayed_work(&tp->schedule, 0); 2238 } else { 2239 usb_mark_last_busy(tp->udev); 2240 napi_schedule(&tp->napi); 2241 } 2242 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2243 netif_stop_queue(netdev); 2244 } 2245 2246 return NETDEV_TX_OK; 2247 } 2248 2249 static void r8152b_reset_packet_filter(struct r8152 *tp) 2250 { 2251 u32 ocp_data; 2252 2253 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2254 ocp_data &= ~FMC_FCR_MCU_EN; 2255 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2256 ocp_data |= FMC_FCR_MCU_EN; 2257 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2258 } 2259 2260 static void rtl8152_nic_reset(struct r8152 *tp) 2261 { 2262 int i; 2263 2264 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2265 2266 for (i = 0; i < 1000; i++) { 2267 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2268 break; 2269 usleep_range(100, 400); 2270 } 2271 } 2272 2273 static void set_tx_qlen(struct r8152 *tp) 2274 { 2275 struct net_device *netdev = tp->netdev; 2276 2277 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2278 sizeof(struct tx_desc)); 2279 } 2280 2281 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2282 { 2283 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2284 } 2285 2286 static void rtl_set_eee_plus(struct r8152 *tp) 2287 { 2288 u32 ocp_data; 2289 u8 speed; 2290 2291 speed = rtl8152_get_speed(tp); 2292 if (speed & _10bps) { 2293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2294 ocp_data |= EEEP_CR_EEEP_TX; 2295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2296 } else { 2297 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2298 ocp_data &= ~EEEP_CR_EEEP_TX; 2299 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2300 } 2301 } 2302 2303 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2304 { 2305 u32 ocp_data; 2306 2307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2308 if (enable) 2309 ocp_data |= RXDY_GATED_EN; 2310 else 2311 ocp_data &= ~RXDY_GATED_EN; 2312 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2313 } 2314 2315 static int rtl_start_rx(struct r8152 *tp) 2316 { 2317 int i, ret = 0; 2318 2319 INIT_LIST_HEAD(&tp->rx_done); 2320 for (i = 0; i < RTL8152_MAX_RX; i++) { 2321 INIT_LIST_HEAD(&tp->rx_info[i].list); 2322 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2323 if (ret) 2324 break; 2325 } 2326 2327 if (ret && ++i < RTL8152_MAX_RX) { 2328 struct list_head rx_queue; 2329 unsigned long flags; 2330 2331 INIT_LIST_HEAD(&rx_queue); 2332 2333 do { 2334 struct rx_agg *agg = &tp->rx_info[i++]; 2335 struct urb *urb = agg->urb; 2336 2337 urb->actual_length = 0; 2338 list_add_tail(&agg->list, &rx_queue); 2339 } while (i < RTL8152_MAX_RX); 2340 2341 spin_lock_irqsave(&tp->rx_lock, flags); 2342 list_splice_tail(&rx_queue, &tp->rx_done); 2343 spin_unlock_irqrestore(&tp->rx_lock, flags); 2344 } 2345 2346 return ret; 2347 } 2348 2349 static int rtl_stop_rx(struct r8152 *tp) 2350 { 2351 int i; 2352 2353 for (i = 0; i < RTL8152_MAX_RX; i++) 2354 usb_kill_urb(tp->rx_info[i].urb); 2355 2356 while (!skb_queue_empty(&tp->rx_queue)) 2357 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2358 2359 return 0; 2360 } 2361 2362 static int rtl_enable(struct r8152 *tp) 2363 { 2364 u32 ocp_data; 2365 2366 r8152b_reset_packet_filter(tp); 2367 2368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2369 ocp_data |= CR_RE | CR_TE; 2370 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2371 2372 rxdy_gated_en(tp, false); 2373 2374 return 0; 2375 } 2376 2377 static int rtl8152_enable(struct r8152 *tp) 2378 { 2379 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2380 return -ENODEV; 2381 2382 set_tx_qlen(tp); 2383 rtl_set_eee_plus(tp); 2384 2385 return rtl_enable(tp); 2386 } 2387 2388 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2389 { 2390 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2391 OWN_UPDATE | OWN_CLEAR); 2392 } 2393 2394 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2395 { 2396 u32 ocp_data = tp->coalesce / 8; 2397 2398 switch (tp->version) { 2399 case RTL_VER_03: 2400 case RTL_VER_04: 2401 case RTL_VER_05: 2402 case RTL_VER_06: 2403 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2404 ocp_data); 2405 break; 2406 2407 case RTL_VER_08: 2408 case RTL_VER_09: 2409 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2410 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2411 */ 2412 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2413 128 / 8); 2414 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2415 ocp_data); 2416 r8153b_rx_agg_chg_indicate(tp); 2417 break; 2418 2419 default: 2420 break; 2421 } 2422 } 2423 2424 static void r8153_set_rx_early_size(struct r8152 *tp) 2425 { 2426 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2427 2428 switch (tp->version) { 2429 case RTL_VER_03: 2430 case RTL_VER_04: 2431 case RTL_VER_05: 2432 case RTL_VER_06: 2433 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2434 ocp_data / 4); 2435 break; 2436 case RTL_VER_08: 2437 case RTL_VER_09: 2438 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2439 ocp_data / 8); 2440 r8153b_rx_agg_chg_indicate(tp); 2441 break; 2442 default: 2443 WARN_ON_ONCE(1); 2444 break; 2445 } 2446 } 2447 2448 static int rtl8153_enable(struct r8152 *tp) 2449 { 2450 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2451 return -ENODEV; 2452 2453 set_tx_qlen(tp); 2454 rtl_set_eee_plus(tp); 2455 r8153_set_rx_early_timeout(tp); 2456 r8153_set_rx_early_size(tp); 2457 2458 return rtl_enable(tp); 2459 } 2460 2461 static void rtl_disable(struct r8152 *tp) 2462 { 2463 u32 ocp_data; 2464 int i; 2465 2466 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2467 rtl_drop_queued_tx(tp); 2468 return; 2469 } 2470 2471 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2472 ocp_data &= ~RCR_ACPT_ALL; 2473 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2474 2475 rtl_drop_queued_tx(tp); 2476 2477 for (i = 0; i < RTL8152_MAX_TX; i++) 2478 usb_kill_urb(tp->tx_info[i].urb); 2479 2480 rxdy_gated_en(tp, true); 2481 2482 for (i = 0; i < 1000; i++) { 2483 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2484 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2485 break; 2486 usleep_range(1000, 2000); 2487 } 2488 2489 for (i = 0; i < 1000; i++) { 2490 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2491 break; 2492 usleep_range(1000, 2000); 2493 } 2494 2495 rtl_stop_rx(tp); 2496 2497 rtl8152_nic_reset(tp); 2498 } 2499 2500 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2501 { 2502 u32 ocp_data; 2503 2504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2505 if (enable) 2506 ocp_data |= POWER_CUT; 2507 else 2508 ocp_data &= ~POWER_CUT; 2509 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2510 2511 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2512 ocp_data &= ~RESUME_INDICATE; 2513 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2514 } 2515 2516 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2517 { 2518 u32 ocp_data; 2519 2520 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2521 if (enable) 2522 ocp_data |= CPCR_RX_VLAN; 2523 else 2524 ocp_data &= ~CPCR_RX_VLAN; 2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2526 } 2527 2528 static int rtl8152_set_features(struct net_device *dev, 2529 netdev_features_t features) 2530 { 2531 netdev_features_t changed = features ^ dev->features; 2532 struct r8152 *tp = netdev_priv(dev); 2533 int ret; 2534 2535 ret = usb_autopm_get_interface(tp->intf); 2536 if (ret < 0) 2537 goto out; 2538 2539 mutex_lock(&tp->control); 2540 2541 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2542 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2543 rtl_rx_vlan_en(tp, true); 2544 else 2545 rtl_rx_vlan_en(tp, false); 2546 } 2547 2548 mutex_unlock(&tp->control); 2549 2550 usb_autopm_put_interface(tp->intf); 2551 2552 out: 2553 return ret; 2554 } 2555 2556 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2557 2558 static u32 __rtl_get_wol(struct r8152 *tp) 2559 { 2560 u32 ocp_data; 2561 u32 wolopts = 0; 2562 2563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2564 if (ocp_data & LINK_ON_WAKE_EN) 2565 wolopts |= WAKE_PHY; 2566 2567 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2568 if (ocp_data & UWF_EN) 2569 wolopts |= WAKE_UCAST; 2570 if (ocp_data & BWF_EN) 2571 wolopts |= WAKE_BCAST; 2572 if (ocp_data & MWF_EN) 2573 wolopts |= WAKE_MCAST; 2574 2575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2576 if (ocp_data & MAGIC_EN) 2577 wolopts |= WAKE_MAGIC; 2578 2579 return wolopts; 2580 } 2581 2582 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2583 { 2584 u32 ocp_data; 2585 2586 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2587 2588 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2589 ocp_data &= ~LINK_ON_WAKE_EN; 2590 if (wolopts & WAKE_PHY) 2591 ocp_data |= LINK_ON_WAKE_EN; 2592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2593 2594 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2595 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2596 if (wolopts & WAKE_UCAST) 2597 ocp_data |= UWF_EN; 2598 if (wolopts & WAKE_BCAST) 2599 ocp_data |= BWF_EN; 2600 if (wolopts & WAKE_MCAST) 2601 ocp_data |= MWF_EN; 2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2603 2604 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2605 2606 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2607 ocp_data &= ~MAGIC_EN; 2608 if (wolopts & WAKE_MAGIC) 2609 ocp_data |= MAGIC_EN; 2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2611 2612 if (wolopts & WAKE_ANY) 2613 device_set_wakeup_enable(&tp->udev->dev, true); 2614 else 2615 device_set_wakeup_enable(&tp->udev->dev, false); 2616 } 2617 2618 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2619 { 2620 /* MAC clock speed down */ 2621 if (enable) { 2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2623 ALDPS_SPDWN_RATIO); 2624 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2625 EEE_SPDWN_RATIO); 2626 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2627 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2628 U1U2_SPDWN_EN | L1_SPDWN_EN); 2629 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2630 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2631 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2632 TP1000_SPDWN_EN); 2633 } else { 2634 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2635 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2637 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2638 } 2639 } 2640 2641 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2642 { 2643 u8 u1u2[8]; 2644 2645 if (enable) 2646 memset(u1u2, 0xff, sizeof(u1u2)); 2647 else 2648 memset(u1u2, 0x00, sizeof(u1u2)); 2649 2650 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2651 } 2652 2653 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2654 { 2655 u32 ocp_data; 2656 2657 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2658 if (enable) 2659 ocp_data |= LPM_U1U2_EN; 2660 else 2661 ocp_data &= ~LPM_U1U2_EN; 2662 2663 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2664 } 2665 2666 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2667 { 2668 u32 ocp_data; 2669 2670 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2671 if (enable) 2672 ocp_data |= U2P3_ENABLE; 2673 else 2674 ocp_data &= ~U2P3_ENABLE; 2675 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2676 } 2677 2678 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2679 { 2680 u32 ocp_data; 2681 2682 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2683 ocp_data &= ~clear; 2684 ocp_data |= set; 2685 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2686 } 2687 2688 static void r8153b_green_en(struct r8152 *tp, bool enable) 2689 { 2690 u16 data; 2691 2692 if (enable) { 2693 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2694 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2695 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2696 } else { 2697 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2698 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2699 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2700 } 2701 2702 data = sram_read(tp, SRAM_GREEN_CFG); 2703 data |= GREEN_ETH_EN; 2704 sram_write(tp, SRAM_GREEN_CFG, data); 2705 2706 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2707 } 2708 2709 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2710 { 2711 u16 data; 2712 int i; 2713 2714 for (i = 0; i < 500; i++) { 2715 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2716 data &= PHY_STAT_MASK; 2717 if (desired) { 2718 if (data == desired) 2719 break; 2720 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2721 data == PHY_STAT_EXT_INIT) { 2722 break; 2723 } 2724 2725 msleep(20); 2726 } 2727 2728 return data; 2729 } 2730 2731 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2732 { 2733 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2734 2735 if (enable) { 2736 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2737 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2738 2739 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2740 ocp_data |= BIT(0); 2741 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2742 } else { 2743 u16 data; 2744 2745 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2746 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2747 2748 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2749 ocp_data &= ~BIT(0); 2750 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2751 2752 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2753 ocp_data &= ~PCUT_STATUS; 2754 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2755 2756 data = r8153_phy_status(tp, 0); 2757 2758 switch (data) { 2759 case PHY_STAT_PWRDN: 2760 case PHY_STAT_EXT_INIT: 2761 r8153b_green_en(tp, 2762 test_bit(GREEN_ETHERNET, &tp->flags)); 2763 2764 data = r8152_mdio_read(tp, MII_BMCR); 2765 data &= ~BMCR_PDOWN; 2766 data |= BMCR_RESET; 2767 r8152_mdio_write(tp, MII_BMCR, data); 2768 2769 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2770 /* fall through */ 2771 2772 default: 2773 if (data != PHY_STAT_LAN_ON) 2774 netif_warn(tp, link, tp->netdev, 2775 "PHY not ready"); 2776 break; 2777 } 2778 } 2779 } 2780 2781 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2782 { 2783 u32 ocp_data; 2784 2785 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2786 if (enable) 2787 ocp_data |= PWR_EN | PHASE2_EN; 2788 else 2789 ocp_data &= ~(PWR_EN | PHASE2_EN); 2790 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2791 2792 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2793 ocp_data &= ~PCUT_STATUS; 2794 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2795 } 2796 2797 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2798 { 2799 u32 ocp_data; 2800 2801 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2802 if (enable) 2803 ocp_data |= PWR_EN | PHASE2_EN; 2804 else 2805 ocp_data &= ~PWR_EN; 2806 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2807 2808 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2809 ocp_data &= ~PCUT_STATUS; 2810 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2811 } 2812 2813 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2814 { 2815 u32 ocp_data; 2816 2817 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2818 if (enable) 2819 ocp_data |= BIT(0); 2820 else 2821 ocp_data &= ~BIT(0); 2822 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2823 2824 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2825 ocp_data &= ~BIT(0); 2826 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2827 } 2828 2829 static bool rtl_can_wakeup(struct r8152 *tp) 2830 { 2831 struct usb_device *udev = tp->udev; 2832 2833 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2834 } 2835 2836 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2837 { 2838 if (enable) { 2839 u32 ocp_data; 2840 2841 __rtl_set_wol(tp, WAKE_ANY); 2842 2843 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2844 2845 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2846 ocp_data |= LINK_OFF_WAKE_EN; 2847 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2848 2849 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2850 } else { 2851 u32 ocp_data; 2852 2853 __rtl_set_wol(tp, tp->saved_wolopts); 2854 2855 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2856 2857 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2858 ocp_data &= ~LINK_OFF_WAKE_EN; 2859 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2860 2861 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2862 } 2863 } 2864 2865 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2866 { 2867 if (enable) { 2868 r8153_u1u2en(tp, false); 2869 r8153_u2p3en(tp, false); 2870 r8153_mac_clk_spd(tp, true); 2871 rtl_runtime_suspend_enable(tp, true); 2872 } else { 2873 rtl_runtime_suspend_enable(tp, false); 2874 r8153_mac_clk_spd(tp, false); 2875 2876 switch (tp->version) { 2877 case RTL_VER_03: 2878 case RTL_VER_04: 2879 break; 2880 case RTL_VER_05: 2881 case RTL_VER_06: 2882 default: 2883 r8153_u2p3en(tp, true); 2884 break; 2885 } 2886 2887 r8153_u1u2en(tp, true); 2888 } 2889 } 2890 2891 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2892 { 2893 if (enable) { 2894 r8153b_queue_wake(tp, true); 2895 r8153b_u1u2en(tp, false); 2896 r8153_u2p3en(tp, false); 2897 rtl_runtime_suspend_enable(tp, true); 2898 r8153b_ups_en(tp, true); 2899 } else { 2900 r8153b_ups_en(tp, false); 2901 r8153b_queue_wake(tp, false); 2902 rtl_runtime_suspend_enable(tp, false); 2903 r8153_u2p3en(tp, true); 2904 r8153b_u1u2en(tp, true); 2905 } 2906 } 2907 2908 static void r8153_teredo_off(struct r8152 *tp) 2909 { 2910 u32 ocp_data; 2911 2912 switch (tp->version) { 2913 case RTL_VER_01: 2914 case RTL_VER_02: 2915 case RTL_VER_03: 2916 case RTL_VER_04: 2917 case RTL_VER_05: 2918 case RTL_VER_06: 2919 case RTL_VER_07: 2920 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2921 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2922 OOB_TEREDO_EN); 2923 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2924 break; 2925 2926 case RTL_VER_08: 2927 case RTL_VER_09: 2928 /* The bit 0 ~ 7 are relative with teredo settings. They are 2929 * W1C (write 1 to clear), so set all 1 to disable it. 2930 */ 2931 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2932 break; 2933 2934 default: 2935 break; 2936 } 2937 2938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2940 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2941 } 2942 2943 static void rtl_reset_bmu(struct r8152 *tp) 2944 { 2945 u32 ocp_data; 2946 2947 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2948 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2949 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2950 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2951 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2952 } 2953 2954 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2955 { 2956 if (enable) { 2957 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2958 LINKENA | DIS_SDSAVE); 2959 } else { 2960 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2961 DIS_SDSAVE); 2962 msleep(20); 2963 } 2964 } 2965 2966 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2967 { 2968 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2969 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2970 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2971 } 2972 2973 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2974 { 2975 u16 data; 2976 2977 r8152_mmd_indirect(tp, dev, reg); 2978 data = ocp_reg_read(tp, OCP_EEE_DATA); 2979 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2980 2981 return data; 2982 } 2983 2984 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2985 { 2986 r8152_mmd_indirect(tp, dev, reg); 2987 ocp_reg_write(tp, OCP_EEE_DATA, data); 2988 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2989 } 2990 2991 static void r8152_eee_en(struct r8152 *tp, bool enable) 2992 { 2993 u16 config1, config2, config3; 2994 u32 ocp_data; 2995 2996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2997 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2998 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2999 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3000 3001 if (enable) { 3002 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3003 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3004 config1 |= sd_rise_time(1); 3005 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3006 config3 |= fast_snr(42); 3007 } else { 3008 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3009 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3010 RX_QUIET_EN); 3011 config1 |= sd_rise_time(7); 3012 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3013 config3 |= fast_snr(511); 3014 } 3015 3016 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3017 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3018 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3019 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3020 } 3021 3022 static void r8152b_enable_eee(struct r8152 *tp) 3023 { 3024 r8152_eee_en(tp, true); 3025 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3026 } 3027 3028 static void r8152b_enable_fc(struct r8152 *tp) 3029 { 3030 u16 anar; 3031 3032 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3033 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3034 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3035 } 3036 3037 static void rtl8152_disable(struct r8152 *tp) 3038 { 3039 r8152_aldps_en(tp, false); 3040 rtl_disable(tp); 3041 r8152_aldps_en(tp, true); 3042 } 3043 3044 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3045 { 3046 r8152b_enable_eee(tp); 3047 r8152_aldps_en(tp, true); 3048 r8152b_enable_fc(tp); 3049 3050 set_bit(PHY_RESET, &tp->flags); 3051 } 3052 3053 static void r8152b_exit_oob(struct r8152 *tp) 3054 { 3055 u32 ocp_data; 3056 int i; 3057 3058 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3059 ocp_data &= ~RCR_ACPT_ALL; 3060 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3061 3062 rxdy_gated_en(tp, true); 3063 r8153_teredo_off(tp); 3064 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3065 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3066 3067 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3068 ocp_data &= ~NOW_IS_OOB; 3069 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3070 3071 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3072 ocp_data &= ~MCU_BORW_EN; 3073 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3074 3075 for (i = 0; i < 1000; i++) { 3076 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3077 if (ocp_data & LINK_LIST_READY) 3078 break; 3079 usleep_range(1000, 2000); 3080 } 3081 3082 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3083 ocp_data |= RE_INIT_LL; 3084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3085 3086 for (i = 0; i < 1000; i++) { 3087 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3088 if (ocp_data & LINK_LIST_READY) 3089 break; 3090 usleep_range(1000, 2000); 3091 } 3092 3093 rtl8152_nic_reset(tp); 3094 3095 /* rx share fifo credit full threshold */ 3096 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3097 3098 if (tp->udev->speed == USB_SPEED_FULL || 3099 tp->udev->speed == USB_SPEED_LOW) { 3100 /* rx share fifo credit near full threshold */ 3101 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3102 RXFIFO_THR2_FULL); 3103 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3104 RXFIFO_THR3_FULL); 3105 } else { 3106 /* rx share fifo credit near full threshold */ 3107 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3108 RXFIFO_THR2_HIGH); 3109 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3110 RXFIFO_THR3_HIGH); 3111 } 3112 3113 /* TX share fifo free credit full threshold */ 3114 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3115 3116 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3117 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3118 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3119 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3120 3121 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3122 3123 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3124 3125 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3126 ocp_data |= TCR0_AUTO_FIFO; 3127 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3128 } 3129 3130 static void r8152b_enter_oob(struct r8152 *tp) 3131 { 3132 u32 ocp_data; 3133 int i; 3134 3135 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3136 ocp_data &= ~NOW_IS_OOB; 3137 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3138 3139 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3140 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3141 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3142 3143 rtl_disable(tp); 3144 3145 for (i = 0; i < 1000; i++) { 3146 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3147 if (ocp_data & LINK_LIST_READY) 3148 break; 3149 usleep_range(1000, 2000); 3150 } 3151 3152 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3153 ocp_data |= RE_INIT_LL; 3154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3155 3156 for (i = 0; i < 1000; i++) { 3157 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3158 if (ocp_data & LINK_LIST_READY) 3159 break; 3160 usleep_range(1000, 2000); 3161 } 3162 3163 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3164 3165 rtl_rx_vlan_en(tp, true); 3166 3167 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3168 ocp_data |= ALDPS_PROXY_MODE; 3169 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3170 3171 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3172 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3173 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3174 3175 rxdy_gated_en(tp, false); 3176 3177 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3178 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3179 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3180 } 3181 3182 static int r8153_patch_request(struct r8152 *tp, bool request) 3183 { 3184 u16 data; 3185 int i; 3186 3187 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3188 if (request) 3189 data |= PATCH_REQUEST; 3190 else 3191 data &= ~PATCH_REQUEST; 3192 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3193 3194 for (i = 0; request && i < 5000; i++) { 3195 usleep_range(1000, 2000); 3196 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3197 break; 3198 } 3199 3200 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3201 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3202 r8153_patch_request(tp, false); 3203 return -ETIME; 3204 } else { 3205 return 0; 3206 } 3207 } 3208 3209 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3210 { 3211 u16 data; 3212 3213 data = ocp_reg_read(tp, OCP_POWER_CFG); 3214 if (enable) { 3215 data |= EN_ALDPS; 3216 ocp_reg_write(tp, OCP_POWER_CFG, data); 3217 } else { 3218 int i; 3219 3220 data &= ~EN_ALDPS; 3221 ocp_reg_write(tp, OCP_POWER_CFG, data); 3222 for (i = 0; i < 20; i++) { 3223 usleep_range(1000, 2000); 3224 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3225 break; 3226 } 3227 } 3228 } 3229 3230 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3231 { 3232 r8153_aldps_en(tp, enable); 3233 3234 if (enable) 3235 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3236 else 3237 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3238 } 3239 3240 static void r8153_eee_en(struct r8152 *tp, bool enable) 3241 { 3242 u32 ocp_data; 3243 u16 config; 3244 3245 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3246 config = ocp_reg_read(tp, OCP_EEE_CFG); 3247 3248 if (enable) { 3249 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3250 config |= EEE10_EN; 3251 } else { 3252 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3253 config &= ~EEE10_EN; 3254 } 3255 3256 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3257 ocp_reg_write(tp, OCP_EEE_CFG, config); 3258 } 3259 3260 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3261 { 3262 r8153_eee_en(tp, enable); 3263 3264 if (enable) 3265 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3266 else 3267 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3268 } 3269 3270 static void r8153b_enable_fc(struct r8152 *tp) 3271 { 3272 r8152b_enable_fc(tp); 3273 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3274 } 3275 3276 static void r8153_hw_phy_cfg(struct r8152 *tp) 3277 { 3278 u32 ocp_data; 3279 u16 data; 3280 3281 /* disable ALDPS before updating the PHY parameters */ 3282 r8153_aldps_en(tp, false); 3283 3284 /* disable EEE before updating the PHY parameters */ 3285 r8153_eee_en(tp, false); 3286 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3287 3288 if (tp->version == RTL_VER_03) { 3289 data = ocp_reg_read(tp, OCP_EEE_CFG); 3290 data &= ~CTAP_SHORT_EN; 3291 ocp_reg_write(tp, OCP_EEE_CFG, data); 3292 } 3293 3294 data = ocp_reg_read(tp, OCP_POWER_CFG); 3295 data |= EEE_CLKDIV_EN; 3296 ocp_reg_write(tp, OCP_POWER_CFG, data); 3297 3298 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3299 data |= EN_10M_BGOFF; 3300 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3301 data = ocp_reg_read(tp, OCP_POWER_CFG); 3302 data |= EN_10M_PLLOFF; 3303 ocp_reg_write(tp, OCP_POWER_CFG, data); 3304 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3305 3306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3307 ocp_data |= PFM_PWM_SWITCH; 3308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3309 3310 /* Enable LPF corner auto tune */ 3311 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3312 3313 /* Adjust 10M Amplitude */ 3314 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3315 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3316 3317 r8153_eee_en(tp, true); 3318 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3319 3320 r8153_aldps_en(tp, true); 3321 r8152b_enable_fc(tp); 3322 3323 switch (tp->version) { 3324 case RTL_VER_03: 3325 case RTL_VER_04: 3326 break; 3327 case RTL_VER_05: 3328 case RTL_VER_06: 3329 default: 3330 r8153_u2p3en(tp, true); 3331 break; 3332 } 3333 3334 set_bit(PHY_RESET, &tp->flags); 3335 } 3336 3337 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3338 { 3339 u32 ocp_data; 3340 3341 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3342 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3343 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3344 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3345 3346 return ocp_data; 3347 } 3348 3349 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3350 { 3351 u32 ocp_data, ups_flags = 0; 3352 u16 data; 3353 3354 /* disable ALDPS before updating the PHY parameters */ 3355 r8153b_aldps_en(tp, false); 3356 3357 /* disable EEE before updating the PHY parameters */ 3358 r8153b_eee_en(tp, false); 3359 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3360 3361 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3362 3363 data = sram_read(tp, SRAM_GREEN_CFG); 3364 data |= R_TUNE_EN; 3365 sram_write(tp, SRAM_GREEN_CFG, data); 3366 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3367 data |= PGA_RETURN_EN; 3368 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3369 3370 /* ADC Bias Calibration: 3371 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3372 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3373 * ADC ioffset. 3374 */ 3375 ocp_data = r8152_efuse_read(tp, 0x7d); 3376 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3377 if (data != 0xffff) 3378 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3379 3380 /* ups mode tx-link-pulse timing adjustment: 3381 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3382 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3383 */ 3384 ocp_data = ocp_reg_read(tp, 0xc426); 3385 ocp_data &= 0x3fff; 3386 if (ocp_data) { 3387 u32 swr_cnt_1ms_ini; 3388 3389 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3390 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3391 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3392 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3393 } 3394 3395 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3396 ocp_data |= PFM_PWM_SWITCH; 3397 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3398 3399 /* Advnace EEE */ 3400 if (!r8153_patch_request(tp, true)) { 3401 data = ocp_reg_read(tp, OCP_POWER_CFG); 3402 data |= EEE_CLKDIV_EN; 3403 ocp_reg_write(tp, OCP_POWER_CFG, data); 3404 3405 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3406 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3407 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3408 3409 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3410 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3411 3412 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3413 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3414 UPS_FLAGS_EEE_PLLOFF_GIGA; 3415 3416 r8153_patch_request(tp, false); 3417 } 3418 3419 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3420 3421 r8153b_eee_en(tp, true); 3422 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3423 3424 r8153b_aldps_en(tp, true); 3425 r8153b_enable_fc(tp); 3426 r8153_u2p3en(tp, true); 3427 3428 set_bit(PHY_RESET, &tp->flags); 3429 } 3430 3431 static void r8153_first_init(struct r8152 *tp) 3432 { 3433 u32 ocp_data; 3434 int i; 3435 3436 r8153_mac_clk_spd(tp, false); 3437 rxdy_gated_en(tp, true); 3438 r8153_teredo_off(tp); 3439 3440 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3441 ocp_data &= ~RCR_ACPT_ALL; 3442 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3443 3444 rtl8152_nic_reset(tp); 3445 rtl_reset_bmu(tp); 3446 3447 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3448 ocp_data &= ~NOW_IS_OOB; 3449 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3450 3451 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3452 ocp_data &= ~MCU_BORW_EN; 3453 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3454 3455 for (i = 0; i < 1000; i++) { 3456 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3457 if (ocp_data & LINK_LIST_READY) 3458 break; 3459 usleep_range(1000, 2000); 3460 } 3461 3462 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3463 ocp_data |= RE_INIT_LL; 3464 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3465 3466 for (i = 0; i < 1000; i++) { 3467 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3468 if (ocp_data & LINK_LIST_READY) 3469 break; 3470 usleep_range(1000, 2000); 3471 } 3472 3473 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3474 3475 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3476 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3477 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3478 3479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3480 ocp_data |= TCR0_AUTO_FIFO; 3481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3482 3483 rtl8152_nic_reset(tp); 3484 3485 /* rx share fifo credit full threshold */ 3486 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3489 /* TX share fifo free credit full threshold */ 3490 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3491 } 3492 3493 static void r8153_enter_oob(struct r8152 *tp) 3494 { 3495 u32 ocp_data; 3496 int i; 3497 3498 r8153_mac_clk_spd(tp, true); 3499 3500 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3501 ocp_data &= ~NOW_IS_OOB; 3502 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3503 3504 rtl_disable(tp); 3505 rtl_reset_bmu(tp); 3506 3507 for (i = 0; i < 1000; i++) { 3508 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3509 if (ocp_data & LINK_LIST_READY) 3510 break; 3511 usleep_range(1000, 2000); 3512 } 3513 3514 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3515 ocp_data |= RE_INIT_LL; 3516 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3517 3518 for (i = 0; i < 1000; i++) { 3519 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3520 if (ocp_data & LINK_LIST_READY) 3521 break; 3522 usleep_range(1000, 2000); 3523 } 3524 3525 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3527 3528 switch (tp->version) { 3529 case RTL_VER_03: 3530 case RTL_VER_04: 3531 case RTL_VER_05: 3532 case RTL_VER_06: 3533 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3534 ocp_data &= ~TEREDO_WAKE_MASK; 3535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3536 break; 3537 3538 case RTL_VER_08: 3539 case RTL_VER_09: 3540 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3541 * type. Set it to zero. bits[7:0] are the W1C bits about 3542 * the events. Set them to all 1 to clear them. 3543 */ 3544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3545 break; 3546 3547 default: 3548 break; 3549 } 3550 3551 rtl_rx_vlan_en(tp, true); 3552 3553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3554 ocp_data |= ALDPS_PROXY_MODE; 3555 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3556 3557 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3558 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3559 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3560 3561 rxdy_gated_en(tp, false); 3562 3563 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3564 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3565 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3566 } 3567 3568 static void rtl8153_disable(struct r8152 *tp) 3569 { 3570 r8153_aldps_en(tp, false); 3571 rtl_disable(tp); 3572 rtl_reset_bmu(tp); 3573 r8153_aldps_en(tp, true); 3574 } 3575 3576 static void rtl8153b_disable(struct r8152 *tp) 3577 { 3578 r8153b_aldps_en(tp, false); 3579 rtl_disable(tp); 3580 rtl_reset_bmu(tp); 3581 r8153b_aldps_en(tp, true); 3582 } 3583 3584 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3585 { 3586 u16 bmcr, anar, gbcr; 3587 enum spd_duplex speed_duplex; 3588 int ret = 0; 3589 3590 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3591 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3592 ADVERTISE_100HALF | ADVERTISE_100FULL); 3593 if (tp->mii.supports_gmii) { 3594 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3595 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3596 } else { 3597 gbcr = 0; 3598 } 3599 3600 if (autoneg == AUTONEG_DISABLE) { 3601 if (speed == SPEED_10) { 3602 bmcr = 0; 3603 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3604 speed_duplex = FORCE_10M_HALF; 3605 } else if (speed == SPEED_100) { 3606 bmcr = BMCR_SPEED100; 3607 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3608 speed_duplex = FORCE_100M_HALF; 3609 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3610 bmcr = BMCR_SPEED1000; 3611 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3612 speed_duplex = NWAY_1000M_FULL; 3613 } else { 3614 ret = -EINVAL; 3615 goto out; 3616 } 3617 3618 if (duplex == DUPLEX_FULL) { 3619 bmcr |= BMCR_FULLDPLX; 3620 if (speed != SPEED_1000) 3621 speed_duplex++; 3622 } 3623 } else { 3624 if (speed == SPEED_10) { 3625 if (duplex == DUPLEX_FULL) { 3626 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3627 speed_duplex = NWAY_10M_FULL; 3628 } else { 3629 anar |= ADVERTISE_10HALF; 3630 speed_duplex = NWAY_10M_HALF; 3631 } 3632 } else if (speed == SPEED_100) { 3633 if (duplex == DUPLEX_FULL) { 3634 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3635 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3636 speed_duplex = NWAY_100M_FULL; 3637 } else { 3638 anar |= ADVERTISE_10HALF; 3639 anar |= ADVERTISE_100HALF; 3640 speed_duplex = NWAY_100M_HALF; 3641 } 3642 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3643 if (duplex == DUPLEX_FULL) { 3644 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3645 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3646 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3647 } else { 3648 anar |= ADVERTISE_10HALF; 3649 anar |= ADVERTISE_100HALF; 3650 gbcr |= ADVERTISE_1000HALF; 3651 } 3652 speed_duplex = NWAY_1000M_FULL; 3653 } else { 3654 ret = -EINVAL; 3655 goto out; 3656 } 3657 3658 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3659 } 3660 3661 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3662 bmcr |= BMCR_RESET; 3663 3664 if (tp->mii.supports_gmii) 3665 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3666 3667 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3668 r8152_mdio_write(tp, MII_BMCR, bmcr); 3669 3670 switch (tp->version) { 3671 case RTL_VER_08: 3672 case RTL_VER_09: 3673 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3674 UPS_FLAGS_SPEED_MASK); 3675 break; 3676 3677 default: 3678 break; 3679 } 3680 3681 if (bmcr & BMCR_RESET) { 3682 int i; 3683 3684 for (i = 0; i < 50; i++) { 3685 msleep(20); 3686 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3687 break; 3688 } 3689 } 3690 3691 out: 3692 return ret; 3693 } 3694 3695 static void rtl8152_up(struct r8152 *tp) 3696 { 3697 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3698 return; 3699 3700 r8152_aldps_en(tp, false); 3701 r8152b_exit_oob(tp); 3702 r8152_aldps_en(tp, true); 3703 } 3704 3705 static void rtl8152_down(struct r8152 *tp) 3706 { 3707 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3708 rtl_drop_queued_tx(tp); 3709 return; 3710 } 3711 3712 r8152_power_cut_en(tp, false); 3713 r8152_aldps_en(tp, false); 3714 r8152b_enter_oob(tp); 3715 r8152_aldps_en(tp, true); 3716 } 3717 3718 static void rtl8153_up(struct r8152 *tp) 3719 { 3720 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3721 return; 3722 3723 r8153_u1u2en(tp, false); 3724 r8153_u2p3en(tp, false); 3725 r8153_aldps_en(tp, false); 3726 r8153_first_init(tp); 3727 r8153_aldps_en(tp, true); 3728 3729 switch (tp->version) { 3730 case RTL_VER_03: 3731 case RTL_VER_04: 3732 break; 3733 case RTL_VER_05: 3734 case RTL_VER_06: 3735 default: 3736 r8153_u2p3en(tp, true); 3737 break; 3738 } 3739 3740 r8153_u1u2en(tp, true); 3741 } 3742 3743 static void rtl8153_down(struct r8152 *tp) 3744 { 3745 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3746 rtl_drop_queued_tx(tp); 3747 return; 3748 } 3749 3750 r8153_u1u2en(tp, false); 3751 r8153_u2p3en(tp, false); 3752 r8153_power_cut_en(tp, false); 3753 r8153_aldps_en(tp, false); 3754 r8153_enter_oob(tp); 3755 r8153_aldps_en(tp, true); 3756 } 3757 3758 static void rtl8153b_up(struct r8152 *tp) 3759 { 3760 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3761 return; 3762 3763 r8153b_u1u2en(tp, false); 3764 r8153_u2p3en(tp, false); 3765 r8153b_aldps_en(tp, false); 3766 3767 r8153_first_init(tp); 3768 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3769 3770 r8153b_aldps_en(tp, true); 3771 r8153_u2p3en(tp, true); 3772 r8153b_u1u2en(tp, true); 3773 } 3774 3775 static void rtl8153b_down(struct r8152 *tp) 3776 { 3777 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3778 rtl_drop_queued_tx(tp); 3779 return; 3780 } 3781 3782 r8153b_u1u2en(tp, false); 3783 r8153_u2p3en(tp, false); 3784 r8153b_power_cut_en(tp, false); 3785 r8153b_aldps_en(tp, false); 3786 r8153_enter_oob(tp); 3787 r8153b_aldps_en(tp, true); 3788 } 3789 3790 static bool rtl8152_in_nway(struct r8152 *tp) 3791 { 3792 u16 nway_state; 3793 3794 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3795 tp->ocp_base = 0x2000; 3796 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3797 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3798 3799 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3800 if (nway_state & 0xc000) 3801 return false; 3802 else 3803 return true; 3804 } 3805 3806 static bool rtl8153_in_nway(struct r8152 *tp) 3807 { 3808 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3809 3810 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3811 return false; 3812 else 3813 return true; 3814 } 3815 3816 static void set_carrier(struct r8152 *tp) 3817 { 3818 struct net_device *netdev = tp->netdev; 3819 struct napi_struct *napi = &tp->napi; 3820 u8 speed; 3821 3822 speed = rtl8152_get_speed(tp); 3823 3824 if (speed & LINK_STATUS) { 3825 if (!netif_carrier_ok(netdev)) { 3826 tp->rtl_ops.enable(tp); 3827 netif_stop_queue(netdev); 3828 napi_disable(napi); 3829 netif_carrier_on(netdev); 3830 rtl_start_rx(tp); 3831 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 3832 _rtl8152_set_rx_mode(netdev); 3833 napi_enable(&tp->napi); 3834 netif_wake_queue(netdev); 3835 netif_info(tp, link, netdev, "carrier on\n"); 3836 } else if (netif_queue_stopped(netdev) && 3837 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3838 netif_wake_queue(netdev); 3839 } 3840 } else { 3841 if (netif_carrier_ok(netdev)) { 3842 netif_carrier_off(netdev); 3843 napi_disable(napi); 3844 tp->rtl_ops.disable(tp); 3845 napi_enable(napi); 3846 netif_info(tp, link, netdev, "carrier off\n"); 3847 } 3848 } 3849 } 3850 3851 static void rtl_work_func_t(struct work_struct *work) 3852 { 3853 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3854 3855 /* If the device is unplugged or !netif_running(), the workqueue 3856 * doesn't need to wake the device, and could return directly. 3857 */ 3858 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3859 return; 3860 3861 if (usb_autopm_get_interface(tp->intf) < 0) 3862 return; 3863 3864 if (!test_bit(WORK_ENABLE, &tp->flags)) 3865 goto out1; 3866 3867 if (!mutex_trylock(&tp->control)) { 3868 schedule_delayed_work(&tp->schedule, 0); 3869 goto out1; 3870 } 3871 3872 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3873 set_carrier(tp); 3874 3875 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3876 _rtl8152_set_rx_mode(tp->netdev); 3877 3878 /* don't schedule napi before linking */ 3879 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3880 netif_carrier_ok(tp->netdev)) 3881 napi_schedule(&tp->napi); 3882 3883 mutex_unlock(&tp->control); 3884 3885 out1: 3886 usb_autopm_put_interface(tp->intf); 3887 } 3888 3889 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3890 { 3891 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3892 3893 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3894 return; 3895 3896 if (usb_autopm_get_interface(tp->intf) < 0) 3897 return; 3898 3899 mutex_lock(&tp->control); 3900 3901 tp->rtl_ops.hw_phy_cfg(tp); 3902 3903 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3904 3905 mutex_unlock(&tp->control); 3906 3907 usb_autopm_put_interface(tp->intf); 3908 } 3909 3910 #ifdef CONFIG_PM_SLEEP 3911 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3912 void *data) 3913 { 3914 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3915 3916 switch (action) { 3917 case PM_HIBERNATION_PREPARE: 3918 case PM_SUSPEND_PREPARE: 3919 usb_autopm_get_interface(tp->intf); 3920 break; 3921 3922 case PM_POST_HIBERNATION: 3923 case PM_POST_SUSPEND: 3924 usb_autopm_put_interface(tp->intf); 3925 break; 3926 3927 case PM_POST_RESTORE: 3928 case PM_RESTORE_PREPARE: 3929 default: 3930 break; 3931 } 3932 3933 return NOTIFY_DONE; 3934 } 3935 #endif 3936 3937 static int rtl8152_open(struct net_device *netdev) 3938 { 3939 struct r8152 *tp = netdev_priv(netdev); 3940 int res = 0; 3941 3942 res = alloc_all_mem(tp); 3943 if (res) 3944 goto out; 3945 3946 res = usb_autopm_get_interface(tp->intf); 3947 if (res < 0) 3948 goto out_free; 3949 3950 mutex_lock(&tp->control); 3951 3952 tp->rtl_ops.up(tp); 3953 3954 netif_carrier_off(netdev); 3955 netif_start_queue(netdev); 3956 set_bit(WORK_ENABLE, &tp->flags); 3957 3958 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3959 if (res) { 3960 if (res == -ENODEV) 3961 netif_device_detach(tp->netdev); 3962 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3963 res); 3964 goto out_unlock; 3965 } 3966 napi_enable(&tp->napi); 3967 3968 mutex_unlock(&tp->control); 3969 3970 usb_autopm_put_interface(tp->intf); 3971 #ifdef CONFIG_PM_SLEEP 3972 tp->pm_notifier.notifier_call = rtl_notifier; 3973 register_pm_notifier(&tp->pm_notifier); 3974 #endif 3975 return 0; 3976 3977 out_unlock: 3978 mutex_unlock(&tp->control); 3979 usb_autopm_put_interface(tp->intf); 3980 out_free: 3981 free_all_mem(tp); 3982 out: 3983 return res; 3984 } 3985 3986 static int rtl8152_close(struct net_device *netdev) 3987 { 3988 struct r8152 *tp = netdev_priv(netdev); 3989 int res = 0; 3990 3991 #ifdef CONFIG_PM_SLEEP 3992 unregister_pm_notifier(&tp->pm_notifier); 3993 #endif 3994 if (!test_bit(RTL8152_UNPLUG, &tp->flags)) 3995 napi_disable(&tp->napi); 3996 clear_bit(WORK_ENABLE, &tp->flags); 3997 usb_kill_urb(tp->intr_urb); 3998 cancel_delayed_work_sync(&tp->schedule); 3999 netif_stop_queue(netdev); 4000 4001 res = usb_autopm_get_interface(tp->intf); 4002 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 4003 rtl_drop_queued_tx(tp); 4004 rtl_stop_rx(tp); 4005 } else { 4006 mutex_lock(&tp->control); 4007 4008 tp->rtl_ops.down(tp); 4009 4010 mutex_unlock(&tp->control); 4011 4012 usb_autopm_put_interface(tp->intf); 4013 } 4014 4015 free_all_mem(tp); 4016 4017 return res; 4018 } 4019 4020 static void rtl_tally_reset(struct r8152 *tp) 4021 { 4022 u32 ocp_data; 4023 4024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4025 ocp_data |= TALLY_RESET; 4026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4027 } 4028 4029 static void r8152b_init(struct r8152 *tp) 4030 { 4031 u32 ocp_data; 4032 u16 data; 4033 4034 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4035 return; 4036 4037 data = r8152_mdio_read(tp, MII_BMCR); 4038 if (data & BMCR_PDOWN) { 4039 data &= ~BMCR_PDOWN; 4040 r8152_mdio_write(tp, MII_BMCR, data); 4041 } 4042 4043 r8152_aldps_en(tp, false); 4044 4045 if (tp->version == RTL_VER_01) { 4046 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4047 ocp_data &= ~LED_MODE_MASK; 4048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4049 } 4050 4051 r8152_power_cut_en(tp, false); 4052 4053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4054 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4056 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4057 ocp_data &= ~MCU_CLK_RATIO_MASK; 4058 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4059 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4060 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4061 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4062 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4063 4064 rtl_tally_reset(tp); 4065 4066 /* enable rx aggregation */ 4067 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4068 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4069 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4070 } 4071 4072 static void r8153_init(struct r8152 *tp) 4073 { 4074 u32 ocp_data; 4075 u16 data; 4076 int i; 4077 4078 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4079 return; 4080 4081 r8153_u1u2en(tp, false); 4082 4083 for (i = 0; i < 500; i++) { 4084 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4085 AUTOLOAD_DONE) 4086 break; 4087 msleep(20); 4088 } 4089 4090 data = r8153_phy_status(tp, 0); 4091 4092 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4093 tp->version == RTL_VER_05) 4094 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4095 4096 data = r8152_mdio_read(tp, MII_BMCR); 4097 if (data & BMCR_PDOWN) { 4098 data &= ~BMCR_PDOWN; 4099 r8152_mdio_write(tp, MII_BMCR, data); 4100 } 4101 4102 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4103 4104 r8153_u2p3en(tp, false); 4105 4106 if (tp->version == RTL_VER_04) { 4107 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4108 ocp_data &= ~pwd_dn_scale_mask; 4109 ocp_data |= pwd_dn_scale(96); 4110 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4111 4112 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4113 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4114 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4115 } else if (tp->version == RTL_VER_05) { 4116 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4117 ocp_data &= ~ECM_ALDPS; 4118 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4119 4120 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4121 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4122 ocp_data &= ~DYNAMIC_BURST; 4123 else 4124 ocp_data |= DYNAMIC_BURST; 4125 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4126 } else if (tp->version == RTL_VER_06) { 4127 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4128 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4129 ocp_data &= ~DYNAMIC_BURST; 4130 else 4131 ocp_data |= DYNAMIC_BURST; 4132 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4133 } 4134 4135 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4136 ocp_data |= EP4_FULL_FC; 4137 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4138 4139 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4140 ocp_data &= ~TIMER11_EN; 4141 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4142 4143 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4144 ocp_data &= ~LED_MODE_MASK; 4145 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4146 4147 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4148 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4149 ocp_data |= LPM_TIMER_500MS; 4150 else 4151 ocp_data |= LPM_TIMER_500US; 4152 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4153 4154 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4155 ocp_data &= ~SEN_VAL_MASK; 4156 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4157 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4158 4159 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4160 4161 r8153_power_cut_en(tp, false); 4162 r8153_u1u2en(tp, true); 4163 r8153_mac_clk_spd(tp, false); 4164 usb_enable_lpm(tp->udev); 4165 4166 /* rx aggregation */ 4167 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4168 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4169 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4170 ocp_data |= RX_AGG_DISABLE; 4171 4172 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4173 4174 rtl_tally_reset(tp); 4175 4176 switch (tp->udev->speed) { 4177 case USB_SPEED_SUPER: 4178 case USB_SPEED_SUPER_PLUS: 4179 tp->coalesce = COALESCE_SUPER; 4180 break; 4181 case USB_SPEED_HIGH: 4182 tp->coalesce = COALESCE_HIGH; 4183 break; 4184 default: 4185 tp->coalesce = COALESCE_SLOW; 4186 break; 4187 } 4188 } 4189 4190 static void r8153b_init(struct r8152 *tp) 4191 { 4192 u32 ocp_data; 4193 u16 data; 4194 int i; 4195 4196 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4197 return; 4198 4199 r8153b_u1u2en(tp, false); 4200 4201 for (i = 0; i < 500; i++) { 4202 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4203 AUTOLOAD_DONE) 4204 break; 4205 msleep(20); 4206 } 4207 4208 data = r8153_phy_status(tp, 0); 4209 4210 data = r8152_mdio_read(tp, MII_BMCR); 4211 if (data & BMCR_PDOWN) { 4212 data &= ~BMCR_PDOWN; 4213 r8152_mdio_write(tp, MII_BMCR, data); 4214 } 4215 4216 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4217 4218 r8153_u2p3en(tp, false); 4219 4220 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4221 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4222 4223 /* U1/U2/L1 idle timer. 500 us */ 4224 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4225 4226 r8153b_power_cut_en(tp, false); 4227 r8153b_ups_en(tp, false); 4228 r8153b_queue_wake(tp, false); 4229 rtl_runtime_suspend_enable(tp, false); 4230 r8153b_u1u2en(tp, true); 4231 usb_enable_lpm(tp->udev); 4232 4233 /* MAC clock speed down */ 4234 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4235 ocp_data |= MAC_CLK_SPDWN_EN; 4236 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4237 4238 set_bit(GREEN_ETHERNET, &tp->flags); 4239 4240 /* rx aggregation */ 4241 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4242 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4243 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4244 4245 rtl_tally_reset(tp); 4246 4247 tp->coalesce = 15000; /* 15 us */ 4248 } 4249 4250 static int rtl8152_pre_reset(struct usb_interface *intf) 4251 { 4252 struct r8152 *tp = usb_get_intfdata(intf); 4253 struct net_device *netdev; 4254 4255 if (!tp) 4256 return 0; 4257 4258 netdev = tp->netdev; 4259 if (!netif_running(netdev)) 4260 return 0; 4261 4262 netif_stop_queue(netdev); 4263 napi_disable(&tp->napi); 4264 clear_bit(WORK_ENABLE, &tp->flags); 4265 usb_kill_urb(tp->intr_urb); 4266 cancel_delayed_work_sync(&tp->schedule); 4267 if (netif_carrier_ok(netdev)) { 4268 mutex_lock(&tp->control); 4269 tp->rtl_ops.disable(tp); 4270 mutex_unlock(&tp->control); 4271 } 4272 4273 return 0; 4274 } 4275 4276 static int rtl8152_post_reset(struct usb_interface *intf) 4277 { 4278 struct r8152 *tp = usb_get_intfdata(intf); 4279 struct net_device *netdev; 4280 struct sockaddr sa; 4281 4282 if (!tp) 4283 return 0; 4284 4285 /* reset the MAC adddress in case of policy change */ 4286 if (determine_ethernet_addr(tp, &sa) >= 0) { 4287 rtnl_lock(); 4288 dev_set_mac_address (tp->netdev, &sa, NULL); 4289 rtnl_unlock(); 4290 } 4291 4292 netdev = tp->netdev; 4293 if (!netif_running(netdev)) 4294 return 0; 4295 4296 set_bit(WORK_ENABLE, &tp->flags); 4297 if (netif_carrier_ok(netdev)) { 4298 mutex_lock(&tp->control); 4299 tp->rtl_ops.enable(tp); 4300 rtl_start_rx(tp); 4301 _rtl8152_set_rx_mode(netdev); 4302 mutex_unlock(&tp->control); 4303 } 4304 4305 napi_enable(&tp->napi); 4306 netif_wake_queue(netdev); 4307 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4308 4309 if (!list_empty(&tp->rx_done)) 4310 napi_schedule(&tp->napi); 4311 4312 return 0; 4313 } 4314 4315 static bool delay_autosuspend(struct r8152 *tp) 4316 { 4317 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4318 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4319 4320 /* This means a linking change occurs and the driver doesn't detect it, 4321 * yet. If the driver has disabled tx/rx and hw is linking on, the 4322 * device wouldn't wake up by receiving any packet. 4323 */ 4324 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4325 return true; 4326 4327 /* If the linking down is occurred by nway, the device may miss the 4328 * linking change event. And it wouldn't wake when linking on. 4329 */ 4330 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4331 return true; 4332 else if (!skb_queue_empty(&tp->tx_queue)) 4333 return true; 4334 else 4335 return false; 4336 } 4337 4338 static int rtl8152_runtime_resume(struct r8152 *tp) 4339 { 4340 struct net_device *netdev = tp->netdev; 4341 4342 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4343 struct napi_struct *napi = &tp->napi; 4344 4345 tp->rtl_ops.autosuspend_en(tp, false); 4346 napi_disable(napi); 4347 set_bit(WORK_ENABLE, &tp->flags); 4348 4349 if (netif_carrier_ok(netdev)) { 4350 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4351 rtl_start_rx(tp); 4352 } else { 4353 netif_carrier_off(netdev); 4354 tp->rtl_ops.disable(tp); 4355 netif_info(tp, link, netdev, "linking down\n"); 4356 } 4357 } 4358 4359 napi_enable(napi); 4360 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4361 smp_mb__after_atomic(); 4362 4363 if (!list_empty(&tp->rx_done)) 4364 napi_schedule(&tp->napi); 4365 4366 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4367 } else { 4368 if (netdev->flags & IFF_UP) 4369 tp->rtl_ops.autosuspend_en(tp, false); 4370 4371 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4372 } 4373 4374 return 0; 4375 } 4376 4377 static int rtl8152_system_resume(struct r8152 *tp) 4378 { 4379 struct net_device *netdev = tp->netdev; 4380 4381 netif_device_attach(netdev); 4382 4383 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4384 tp->rtl_ops.up(tp); 4385 netif_carrier_off(netdev); 4386 set_bit(WORK_ENABLE, &tp->flags); 4387 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4388 } 4389 4390 return 0; 4391 } 4392 4393 static int rtl8152_runtime_suspend(struct r8152 *tp) 4394 { 4395 struct net_device *netdev = tp->netdev; 4396 int ret = 0; 4397 4398 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4399 smp_mb__after_atomic(); 4400 4401 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4402 u32 rcr = 0; 4403 4404 if (netif_carrier_ok(netdev)) { 4405 u32 ocp_data; 4406 4407 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4408 ocp_data = rcr & ~RCR_ACPT_ALL; 4409 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4410 rxdy_gated_en(tp, true); 4411 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4412 PLA_OOB_CTRL); 4413 if (!(ocp_data & RXFIFO_EMPTY)) { 4414 rxdy_gated_en(tp, false); 4415 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4416 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4417 smp_mb__after_atomic(); 4418 ret = -EBUSY; 4419 goto out1; 4420 } 4421 } 4422 4423 clear_bit(WORK_ENABLE, &tp->flags); 4424 usb_kill_urb(tp->intr_urb); 4425 4426 tp->rtl_ops.autosuspend_en(tp, true); 4427 4428 if (netif_carrier_ok(netdev)) { 4429 struct napi_struct *napi = &tp->napi; 4430 4431 napi_disable(napi); 4432 rtl_stop_rx(tp); 4433 rxdy_gated_en(tp, false); 4434 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4435 napi_enable(napi); 4436 } 4437 4438 if (delay_autosuspend(tp)) { 4439 rtl8152_runtime_resume(tp); 4440 ret = -EBUSY; 4441 } 4442 } 4443 4444 out1: 4445 return ret; 4446 } 4447 4448 static int rtl8152_system_suspend(struct r8152 *tp) 4449 { 4450 struct net_device *netdev = tp->netdev; 4451 4452 netif_device_detach(netdev); 4453 4454 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4455 struct napi_struct *napi = &tp->napi; 4456 4457 clear_bit(WORK_ENABLE, &tp->flags); 4458 usb_kill_urb(tp->intr_urb); 4459 napi_disable(napi); 4460 cancel_delayed_work_sync(&tp->schedule); 4461 tp->rtl_ops.down(tp); 4462 napi_enable(napi); 4463 } 4464 4465 return 0; 4466 } 4467 4468 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4469 { 4470 struct r8152 *tp = usb_get_intfdata(intf); 4471 int ret; 4472 4473 mutex_lock(&tp->control); 4474 4475 if (PMSG_IS_AUTO(message)) 4476 ret = rtl8152_runtime_suspend(tp); 4477 else 4478 ret = rtl8152_system_suspend(tp); 4479 4480 mutex_unlock(&tp->control); 4481 4482 return ret; 4483 } 4484 4485 static int rtl8152_resume(struct usb_interface *intf) 4486 { 4487 struct r8152 *tp = usb_get_intfdata(intf); 4488 int ret; 4489 4490 mutex_lock(&tp->control); 4491 4492 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4493 ret = rtl8152_runtime_resume(tp); 4494 else 4495 ret = rtl8152_system_resume(tp); 4496 4497 mutex_unlock(&tp->control); 4498 4499 return ret; 4500 } 4501 4502 static int rtl8152_reset_resume(struct usb_interface *intf) 4503 { 4504 struct r8152 *tp = usb_get_intfdata(intf); 4505 4506 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4507 mutex_lock(&tp->control); 4508 tp->rtl_ops.init(tp); 4509 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4510 mutex_unlock(&tp->control); 4511 return rtl8152_resume(intf); 4512 } 4513 4514 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4515 { 4516 struct r8152 *tp = netdev_priv(dev); 4517 4518 if (usb_autopm_get_interface(tp->intf) < 0) 4519 return; 4520 4521 if (!rtl_can_wakeup(tp)) { 4522 wol->supported = 0; 4523 wol->wolopts = 0; 4524 } else { 4525 mutex_lock(&tp->control); 4526 wol->supported = WAKE_ANY; 4527 wol->wolopts = __rtl_get_wol(tp); 4528 mutex_unlock(&tp->control); 4529 } 4530 4531 usb_autopm_put_interface(tp->intf); 4532 } 4533 4534 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4535 { 4536 struct r8152 *tp = netdev_priv(dev); 4537 int ret; 4538 4539 if (!rtl_can_wakeup(tp)) 4540 return -EOPNOTSUPP; 4541 4542 if (wol->wolopts & ~WAKE_ANY) 4543 return -EINVAL; 4544 4545 ret = usb_autopm_get_interface(tp->intf); 4546 if (ret < 0) 4547 goto out_set_wol; 4548 4549 mutex_lock(&tp->control); 4550 4551 __rtl_set_wol(tp, wol->wolopts); 4552 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4553 4554 mutex_unlock(&tp->control); 4555 4556 usb_autopm_put_interface(tp->intf); 4557 4558 out_set_wol: 4559 return ret; 4560 } 4561 4562 static u32 rtl8152_get_msglevel(struct net_device *dev) 4563 { 4564 struct r8152 *tp = netdev_priv(dev); 4565 4566 return tp->msg_enable; 4567 } 4568 4569 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4570 { 4571 struct r8152 *tp = netdev_priv(dev); 4572 4573 tp->msg_enable = value; 4574 } 4575 4576 static void rtl8152_get_drvinfo(struct net_device *netdev, 4577 struct ethtool_drvinfo *info) 4578 { 4579 struct r8152 *tp = netdev_priv(netdev); 4580 4581 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4582 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4583 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4584 } 4585 4586 static 4587 int rtl8152_get_link_ksettings(struct net_device *netdev, 4588 struct ethtool_link_ksettings *cmd) 4589 { 4590 struct r8152 *tp = netdev_priv(netdev); 4591 int ret; 4592 4593 if (!tp->mii.mdio_read) 4594 return -EOPNOTSUPP; 4595 4596 ret = usb_autopm_get_interface(tp->intf); 4597 if (ret < 0) 4598 goto out; 4599 4600 mutex_lock(&tp->control); 4601 4602 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4603 4604 mutex_unlock(&tp->control); 4605 4606 usb_autopm_put_interface(tp->intf); 4607 4608 out: 4609 return ret; 4610 } 4611 4612 static int rtl8152_set_link_ksettings(struct net_device *dev, 4613 const struct ethtool_link_ksettings *cmd) 4614 { 4615 struct r8152 *tp = netdev_priv(dev); 4616 int ret; 4617 4618 ret = usb_autopm_get_interface(tp->intf); 4619 if (ret < 0) 4620 goto out; 4621 4622 mutex_lock(&tp->control); 4623 4624 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4625 cmd->base.duplex); 4626 if (!ret) { 4627 tp->autoneg = cmd->base.autoneg; 4628 tp->speed = cmd->base.speed; 4629 tp->duplex = cmd->base.duplex; 4630 } 4631 4632 mutex_unlock(&tp->control); 4633 4634 usb_autopm_put_interface(tp->intf); 4635 4636 out: 4637 return ret; 4638 } 4639 4640 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4641 "tx_packets", 4642 "rx_packets", 4643 "tx_errors", 4644 "rx_errors", 4645 "rx_missed", 4646 "align_errors", 4647 "tx_single_collisions", 4648 "tx_multi_collisions", 4649 "rx_unicast", 4650 "rx_broadcast", 4651 "rx_multicast", 4652 "tx_aborted", 4653 "tx_underrun", 4654 }; 4655 4656 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4657 { 4658 switch (sset) { 4659 case ETH_SS_STATS: 4660 return ARRAY_SIZE(rtl8152_gstrings); 4661 default: 4662 return -EOPNOTSUPP; 4663 } 4664 } 4665 4666 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4667 struct ethtool_stats *stats, u64 *data) 4668 { 4669 struct r8152 *tp = netdev_priv(dev); 4670 struct tally_counter tally; 4671 4672 if (usb_autopm_get_interface(tp->intf) < 0) 4673 return; 4674 4675 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4676 4677 usb_autopm_put_interface(tp->intf); 4678 4679 data[0] = le64_to_cpu(tally.tx_packets); 4680 data[1] = le64_to_cpu(tally.rx_packets); 4681 data[2] = le64_to_cpu(tally.tx_errors); 4682 data[3] = le32_to_cpu(tally.rx_errors); 4683 data[4] = le16_to_cpu(tally.rx_missed); 4684 data[5] = le16_to_cpu(tally.align_errors); 4685 data[6] = le32_to_cpu(tally.tx_one_collision); 4686 data[7] = le32_to_cpu(tally.tx_multi_collision); 4687 data[8] = le64_to_cpu(tally.rx_unicast); 4688 data[9] = le64_to_cpu(tally.rx_broadcast); 4689 data[10] = le32_to_cpu(tally.rx_multicast); 4690 data[11] = le16_to_cpu(tally.tx_aborted); 4691 data[12] = le16_to_cpu(tally.tx_underrun); 4692 } 4693 4694 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4695 { 4696 switch (stringset) { 4697 case ETH_SS_STATS: 4698 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4699 break; 4700 } 4701 } 4702 4703 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4704 { 4705 u32 ocp_data, lp, adv, supported = 0; 4706 u16 val; 4707 4708 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4709 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4710 4711 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4712 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4713 4714 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4715 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4716 4717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4718 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4719 4720 eee->eee_enabled = !!ocp_data; 4721 eee->eee_active = !!(supported & adv & lp); 4722 eee->supported = supported; 4723 eee->advertised = adv; 4724 eee->lp_advertised = lp; 4725 4726 return 0; 4727 } 4728 4729 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4730 { 4731 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4732 4733 r8152_eee_en(tp, eee->eee_enabled); 4734 4735 if (!eee->eee_enabled) 4736 val = 0; 4737 4738 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4739 4740 return 0; 4741 } 4742 4743 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4744 { 4745 u32 ocp_data, lp, adv, supported = 0; 4746 u16 val; 4747 4748 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4749 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4750 4751 val = ocp_reg_read(tp, OCP_EEE_ADV); 4752 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4753 4754 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4755 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4756 4757 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4758 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4759 4760 eee->eee_enabled = !!ocp_data; 4761 eee->eee_active = !!(supported & adv & lp); 4762 eee->supported = supported; 4763 eee->advertised = adv; 4764 eee->lp_advertised = lp; 4765 4766 return 0; 4767 } 4768 4769 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4770 { 4771 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4772 4773 r8153_eee_en(tp, eee->eee_enabled); 4774 4775 if (!eee->eee_enabled) 4776 val = 0; 4777 4778 ocp_reg_write(tp, OCP_EEE_ADV, val); 4779 4780 return 0; 4781 } 4782 4783 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4784 { 4785 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4786 4787 r8153b_eee_en(tp, eee->eee_enabled); 4788 4789 if (!eee->eee_enabled) 4790 val = 0; 4791 4792 ocp_reg_write(tp, OCP_EEE_ADV, val); 4793 4794 return 0; 4795 } 4796 4797 static int 4798 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4799 { 4800 struct r8152 *tp = netdev_priv(net); 4801 int ret; 4802 4803 ret = usb_autopm_get_interface(tp->intf); 4804 if (ret < 0) 4805 goto out; 4806 4807 mutex_lock(&tp->control); 4808 4809 ret = tp->rtl_ops.eee_get(tp, edata); 4810 4811 mutex_unlock(&tp->control); 4812 4813 usb_autopm_put_interface(tp->intf); 4814 4815 out: 4816 return ret; 4817 } 4818 4819 static int 4820 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4821 { 4822 struct r8152 *tp = netdev_priv(net); 4823 int ret; 4824 4825 ret = usb_autopm_get_interface(tp->intf); 4826 if (ret < 0) 4827 goto out; 4828 4829 mutex_lock(&tp->control); 4830 4831 ret = tp->rtl_ops.eee_set(tp, edata); 4832 if (!ret) 4833 ret = mii_nway_restart(&tp->mii); 4834 4835 mutex_unlock(&tp->control); 4836 4837 usb_autopm_put_interface(tp->intf); 4838 4839 out: 4840 return ret; 4841 } 4842 4843 static int rtl8152_nway_reset(struct net_device *dev) 4844 { 4845 struct r8152 *tp = netdev_priv(dev); 4846 int ret; 4847 4848 ret = usb_autopm_get_interface(tp->intf); 4849 if (ret < 0) 4850 goto out; 4851 4852 mutex_lock(&tp->control); 4853 4854 ret = mii_nway_restart(&tp->mii); 4855 4856 mutex_unlock(&tp->control); 4857 4858 usb_autopm_put_interface(tp->intf); 4859 4860 out: 4861 return ret; 4862 } 4863 4864 static int rtl8152_get_coalesce(struct net_device *netdev, 4865 struct ethtool_coalesce *coalesce) 4866 { 4867 struct r8152 *tp = netdev_priv(netdev); 4868 4869 switch (tp->version) { 4870 case RTL_VER_01: 4871 case RTL_VER_02: 4872 case RTL_VER_07: 4873 return -EOPNOTSUPP; 4874 default: 4875 break; 4876 } 4877 4878 coalesce->rx_coalesce_usecs = tp->coalesce; 4879 4880 return 0; 4881 } 4882 4883 static int rtl8152_set_coalesce(struct net_device *netdev, 4884 struct ethtool_coalesce *coalesce) 4885 { 4886 struct r8152 *tp = netdev_priv(netdev); 4887 int ret; 4888 4889 switch (tp->version) { 4890 case RTL_VER_01: 4891 case RTL_VER_02: 4892 case RTL_VER_07: 4893 return -EOPNOTSUPP; 4894 default: 4895 break; 4896 } 4897 4898 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4899 return -EINVAL; 4900 4901 ret = usb_autopm_get_interface(tp->intf); 4902 if (ret < 0) 4903 return ret; 4904 4905 mutex_lock(&tp->control); 4906 4907 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4908 tp->coalesce = coalesce->rx_coalesce_usecs; 4909 4910 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4911 r8153_set_rx_early_timeout(tp); 4912 } 4913 4914 mutex_unlock(&tp->control); 4915 4916 usb_autopm_put_interface(tp->intf); 4917 4918 return ret; 4919 } 4920 4921 static const struct ethtool_ops ops = { 4922 .get_drvinfo = rtl8152_get_drvinfo, 4923 .get_link = ethtool_op_get_link, 4924 .nway_reset = rtl8152_nway_reset, 4925 .get_msglevel = rtl8152_get_msglevel, 4926 .set_msglevel = rtl8152_set_msglevel, 4927 .get_wol = rtl8152_get_wol, 4928 .set_wol = rtl8152_set_wol, 4929 .get_strings = rtl8152_get_strings, 4930 .get_sset_count = rtl8152_get_sset_count, 4931 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4932 .get_coalesce = rtl8152_get_coalesce, 4933 .set_coalesce = rtl8152_set_coalesce, 4934 .get_eee = rtl_ethtool_get_eee, 4935 .set_eee = rtl_ethtool_set_eee, 4936 .get_link_ksettings = rtl8152_get_link_ksettings, 4937 .set_link_ksettings = rtl8152_set_link_ksettings, 4938 }; 4939 4940 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4941 { 4942 struct r8152 *tp = netdev_priv(netdev); 4943 struct mii_ioctl_data *data = if_mii(rq); 4944 int res; 4945 4946 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4947 return -ENODEV; 4948 4949 res = usb_autopm_get_interface(tp->intf); 4950 if (res < 0) 4951 goto out; 4952 4953 switch (cmd) { 4954 case SIOCGMIIPHY: 4955 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4956 break; 4957 4958 case SIOCGMIIREG: 4959 mutex_lock(&tp->control); 4960 data->val_out = r8152_mdio_read(tp, data->reg_num); 4961 mutex_unlock(&tp->control); 4962 break; 4963 4964 case SIOCSMIIREG: 4965 if (!capable(CAP_NET_ADMIN)) { 4966 res = -EPERM; 4967 break; 4968 } 4969 mutex_lock(&tp->control); 4970 r8152_mdio_write(tp, data->reg_num, data->val_in); 4971 mutex_unlock(&tp->control); 4972 break; 4973 4974 default: 4975 res = -EOPNOTSUPP; 4976 } 4977 4978 usb_autopm_put_interface(tp->intf); 4979 4980 out: 4981 return res; 4982 } 4983 4984 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4985 { 4986 struct r8152 *tp = netdev_priv(dev); 4987 int ret; 4988 4989 switch (tp->version) { 4990 case RTL_VER_01: 4991 case RTL_VER_02: 4992 case RTL_VER_07: 4993 dev->mtu = new_mtu; 4994 return 0; 4995 default: 4996 break; 4997 } 4998 4999 ret = usb_autopm_get_interface(tp->intf); 5000 if (ret < 0) 5001 return ret; 5002 5003 mutex_lock(&tp->control); 5004 5005 dev->mtu = new_mtu; 5006 5007 if (netif_running(dev)) { 5008 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5009 5010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5011 5012 if (netif_carrier_ok(dev)) 5013 r8153_set_rx_early_size(tp); 5014 } 5015 5016 mutex_unlock(&tp->control); 5017 5018 usb_autopm_put_interface(tp->intf); 5019 5020 return ret; 5021 } 5022 5023 static const struct net_device_ops rtl8152_netdev_ops = { 5024 .ndo_open = rtl8152_open, 5025 .ndo_stop = rtl8152_close, 5026 .ndo_do_ioctl = rtl8152_ioctl, 5027 .ndo_start_xmit = rtl8152_start_xmit, 5028 .ndo_tx_timeout = rtl8152_tx_timeout, 5029 .ndo_set_features = rtl8152_set_features, 5030 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5031 .ndo_set_mac_address = rtl8152_set_mac_address, 5032 .ndo_change_mtu = rtl8152_change_mtu, 5033 .ndo_validate_addr = eth_validate_addr, 5034 .ndo_features_check = rtl8152_features_check, 5035 }; 5036 5037 static void rtl8152_unload(struct r8152 *tp) 5038 { 5039 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5040 return; 5041 5042 if (tp->version != RTL_VER_01) 5043 r8152_power_cut_en(tp, true); 5044 } 5045 5046 static void rtl8153_unload(struct r8152 *tp) 5047 { 5048 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5049 return; 5050 5051 r8153_power_cut_en(tp, false); 5052 } 5053 5054 static void rtl8153b_unload(struct r8152 *tp) 5055 { 5056 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5057 return; 5058 5059 r8153b_power_cut_en(tp, false); 5060 } 5061 5062 static int rtl_ops_init(struct r8152 *tp) 5063 { 5064 struct rtl_ops *ops = &tp->rtl_ops; 5065 int ret = 0; 5066 5067 switch (tp->version) { 5068 case RTL_VER_01: 5069 case RTL_VER_02: 5070 case RTL_VER_07: 5071 ops->init = r8152b_init; 5072 ops->enable = rtl8152_enable; 5073 ops->disable = rtl8152_disable; 5074 ops->up = rtl8152_up; 5075 ops->down = rtl8152_down; 5076 ops->unload = rtl8152_unload; 5077 ops->eee_get = r8152_get_eee; 5078 ops->eee_set = r8152_set_eee; 5079 ops->in_nway = rtl8152_in_nway; 5080 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5081 ops->autosuspend_en = rtl_runtime_suspend_enable; 5082 break; 5083 5084 case RTL_VER_03: 5085 case RTL_VER_04: 5086 case RTL_VER_05: 5087 case RTL_VER_06: 5088 ops->init = r8153_init; 5089 ops->enable = rtl8153_enable; 5090 ops->disable = rtl8153_disable; 5091 ops->up = rtl8153_up; 5092 ops->down = rtl8153_down; 5093 ops->unload = rtl8153_unload; 5094 ops->eee_get = r8153_get_eee; 5095 ops->eee_set = r8153_set_eee; 5096 ops->in_nway = rtl8153_in_nway; 5097 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5098 ops->autosuspend_en = rtl8153_runtime_enable; 5099 break; 5100 5101 case RTL_VER_08: 5102 case RTL_VER_09: 5103 ops->init = r8153b_init; 5104 ops->enable = rtl8153_enable; 5105 ops->disable = rtl8153b_disable; 5106 ops->up = rtl8153b_up; 5107 ops->down = rtl8153b_down; 5108 ops->unload = rtl8153b_unload; 5109 ops->eee_get = r8153_get_eee; 5110 ops->eee_set = r8153b_set_eee; 5111 ops->in_nway = rtl8153_in_nway; 5112 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5113 ops->autosuspend_en = rtl8153b_runtime_enable; 5114 break; 5115 5116 default: 5117 ret = -ENODEV; 5118 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5119 break; 5120 } 5121 5122 return ret; 5123 } 5124 5125 static u8 rtl_get_version(struct usb_interface *intf) 5126 { 5127 struct usb_device *udev = interface_to_usbdev(intf); 5128 u32 ocp_data = 0; 5129 __le32 *tmp; 5130 u8 version; 5131 int ret; 5132 5133 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5134 if (!tmp) 5135 return 0; 5136 5137 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5138 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5139 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5140 if (ret > 0) 5141 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5142 5143 kfree(tmp); 5144 5145 switch (ocp_data) { 5146 case 0x4c00: 5147 version = RTL_VER_01; 5148 break; 5149 case 0x4c10: 5150 version = RTL_VER_02; 5151 break; 5152 case 0x5c00: 5153 version = RTL_VER_03; 5154 break; 5155 case 0x5c10: 5156 version = RTL_VER_04; 5157 break; 5158 case 0x5c20: 5159 version = RTL_VER_05; 5160 break; 5161 case 0x5c30: 5162 version = RTL_VER_06; 5163 break; 5164 case 0x4800: 5165 version = RTL_VER_07; 5166 break; 5167 case 0x6000: 5168 version = RTL_VER_08; 5169 break; 5170 case 0x6010: 5171 version = RTL_VER_09; 5172 break; 5173 default: 5174 version = RTL_VER_UNKNOWN; 5175 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5176 break; 5177 } 5178 5179 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5180 5181 return version; 5182 } 5183 5184 static int rtl8152_probe(struct usb_interface *intf, 5185 const struct usb_device_id *id) 5186 { 5187 struct usb_device *udev = interface_to_usbdev(intf); 5188 u8 version = rtl_get_version(intf); 5189 struct r8152 *tp; 5190 struct net_device *netdev; 5191 int ret; 5192 5193 if (version == RTL_VER_UNKNOWN) 5194 return -ENODEV; 5195 5196 if (udev->actconfig->desc.bConfigurationValue != 1) { 5197 usb_driver_set_configuration(udev, 1); 5198 return -ENODEV; 5199 } 5200 5201 usb_reset_device(udev); 5202 netdev = alloc_etherdev(sizeof(struct r8152)); 5203 if (!netdev) { 5204 dev_err(&intf->dev, "Out of memory\n"); 5205 return -ENOMEM; 5206 } 5207 5208 SET_NETDEV_DEV(netdev, &intf->dev); 5209 tp = netdev_priv(netdev); 5210 tp->msg_enable = 0x7FFF; 5211 5212 tp->udev = udev; 5213 tp->netdev = netdev; 5214 tp->intf = intf; 5215 tp->version = version; 5216 5217 switch (version) { 5218 case RTL_VER_01: 5219 case RTL_VER_02: 5220 case RTL_VER_07: 5221 tp->mii.supports_gmii = 0; 5222 break; 5223 default: 5224 tp->mii.supports_gmii = 1; 5225 break; 5226 } 5227 5228 ret = rtl_ops_init(tp); 5229 if (ret) 5230 goto out; 5231 5232 mutex_init(&tp->control); 5233 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5234 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5235 5236 netdev->netdev_ops = &rtl8152_netdev_ops; 5237 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5238 5239 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5240 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5241 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5242 NETIF_F_HW_VLAN_CTAG_TX; 5243 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5244 NETIF_F_TSO | NETIF_F_FRAGLIST | 5245 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5246 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5247 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5248 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5249 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5250 5251 if (tp->version == RTL_VER_01) { 5252 netdev->features &= ~NETIF_F_RXCSUM; 5253 netdev->hw_features &= ~NETIF_F_RXCSUM; 5254 } 5255 5256 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5257 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5258 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5259 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5260 } 5261 5262 netdev->ethtool_ops = &ops; 5263 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5264 5265 /* MTU range: 68 - 1500 or 9194 */ 5266 netdev->min_mtu = ETH_MIN_MTU; 5267 switch (tp->version) { 5268 case RTL_VER_01: 5269 case RTL_VER_02: 5270 netdev->max_mtu = ETH_DATA_LEN; 5271 break; 5272 default: 5273 netdev->max_mtu = RTL8153_MAX_MTU; 5274 break; 5275 } 5276 5277 tp->mii.dev = netdev; 5278 tp->mii.mdio_read = read_mii_word; 5279 tp->mii.mdio_write = write_mii_word; 5280 tp->mii.phy_id_mask = 0x3f; 5281 tp->mii.reg_num_mask = 0x1f; 5282 tp->mii.phy_id = R8152_PHY_ID; 5283 5284 tp->autoneg = AUTONEG_ENABLE; 5285 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5286 tp->duplex = DUPLEX_FULL; 5287 5288 intf->needs_remote_wakeup = 1; 5289 5290 tp->rtl_ops.init(tp); 5291 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5292 set_ethernet_addr(tp); 5293 5294 usb_set_intfdata(intf, tp); 5295 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5296 5297 ret = register_netdev(netdev); 5298 if (ret != 0) { 5299 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5300 goto out1; 5301 } 5302 5303 if (!rtl_can_wakeup(tp)) 5304 __rtl_set_wol(tp, 0); 5305 5306 tp->saved_wolopts = __rtl_get_wol(tp); 5307 if (tp->saved_wolopts) 5308 device_set_wakeup_enable(&udev->dev, true); 5309 else 5310 device_set_wakeup_enable(&udev->dev, false); 5311 5312 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5313 5314 return 0; 5315 5316 out1: 5317 netif_napi_del(&tp->napi); 5318 usb_set_intfdata(intf, NULL); 5319 out: 5320 free_netdev(netdev); 5321 return ret; 5322 } 5323 5324 static void rtl8152_disconnect(struct usb_interface *intf) 5325 { 5326 struct r8152 *tp = usb_get_intfdata(intf); 5327 5328 usb_set_intfdata(intf, NULL); 5329 if (tp) { 5330 struct usb_device *udev = tp->udev; 5331 5332 if (udev->state == USB_STATE_NOTATTACHED) 5333 set_bit(RTL8152_UNPLUG, &tp->flags); 5334 5335 netif_napi_del(&tp->napi); 5336 unregister_netdev(tp->netdev); 5337 cancel_delayed_work_sync(&tp->hw_phy_work); 5338 tp->rtl_ops.unload(tp); 5339 free_netdev(tp->netdev); 5340 } 5341 } 5342 5343 #define REALTEK_USB_DEVICE(vend, prod) \ 5344 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5345 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5346 .idVendor = (vend), \ 5347 .idProduct = (prod), \ 5348 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5349 }, \ 5350 { \ 5351 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5352 USB_DEVICE_ID_MATCH_DEVICE, \ 5353 .idVendor = (vend), \ 5354 .idProduct = (prod), \ 5355 .bInterfaceClass = USB_CLASS_COMM, \ 5356 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5357 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5358 5359 /* table of devices that work with this driver */ 5360 static const struct usb_device_id rtl8152_table[] = { 5361 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5362 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5363 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5364 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5365 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5366 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5367 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5368 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5369 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5370 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5371 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5372 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5373 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5374 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5375 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5376 {} 5377 }; 5378 5379 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5380 5381 static struct usb_driver rtl8152_driver = { 5382 .name = MODULENAME, 5383 .id_table = rtl8152_table, 5384 .probe = rtl8152_probe, 5385 .disconnect = rtl8152_disconnect, 5386 .suspend = rtl8152_suspend, 5387 .resume = rtl8152_resume, 5388 .reset_resume = rtl8152_reset_resume, 5389 .pre_reset = rtl8152_pre_reset, 5390 .post_reset = rtl8152_post_reset, 5391 .supports_autosuspend = 1, 5392 .disable_hub_initiated_lpm = 1, 5393 }; 5394 5395 module_usb_driver(rtl8152_driver); 5396 5397 MODULE_AUTHOR(DRIVER_AUTHOR); 5398 MODULE_DESCRIPTION(DRIVER_DESC); 5399 MODULE_LICENSE("GPL"); 5400 MODULE_VERSION(DRIVER_VERSION); 5401