1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/atomic.h> 26 #include <linux/acpi.h> 27 28 /* Information for net-next */ 29 #define NETNEXT_VERSION "10" 30 31 /* Information for net */ 32 #define NET_VERSION "10" 33 34 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 35 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 36 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 37 #define MODULENAME "r8152" 38 39 #define R8152_PHY_ID 32 40 41 #define PLA_IDR 0xc000 42 #define PLA_RCR 0xc010 43 #define PLA_RMS 0xc016 44 #define PLA_RXFIFO_CTRL0 0xc0a0 45 #define PLA_RXFIFO_CTRL1 0xc0a4 46 #define PLA_RXFIFO_CTRL2 0xc0a8 47 #define PLA_DMY_REG0 0xc0b0 48 #define PLA_FMC 0xc0b4 49 #define PLA_CFG_WOL 0xc0b6 50 #define PLA_TEREDO_CFG 0xc0bc 51 #define PLA_TEREDO_WAKE_BASE 0xc0c4 52 #define PLA_MAR 0xcd00 53 #define PLA_BACKUP 0xd000 54 #define PLA_BDC_CR 0xd1a0 55 #define PLA_TEREDO_TIMER 0xd2cc 56 #define PLA_REALWOW_TIMER 0xd2e8 57 #define PLA_SUSPEND_FLAG 0xd38a 58 #define PLA_INDICATE_FALG 0xd38c 59 #define PLA_EXTRA_STATUS 0xd398 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_MISC_1 0xd81f 133 #define USB_AFE_CTRL2 0xd824 134 #define USB_UPS_CFG 0xd842 135 #define USB_UPS_FLAGS 0xd848 136 #define USB_WDT11_CTRL 0xe43c 137 #define USB_BP_BA 0xfc26 138 #define USB_BP_0 0xfc28 139 #define USB_BP_1 0xfc2a 140 #define USB_BP_2 0xfc2c 141 #define USB_BP_3 0xfc2e 142 #define USB_BP_4 0xfc30 143 #define USB_BP_5 0xfc32 144 #define USB_BP_6 0xfc34 145 #define USB_BP_7 0xfc36 146 #define USB_BP_EN 0xfc38 147 #define USB_BP_8 0xfc38 148 #define USB_BP_9 0xfc3a 149 #define USB_BP_10 0xfc3c 150 #define USB_BP_11 0xfc3e 151 #define USB_BP_12 0xfc40 152 #define USB_BP_13 0xfc42 153 #define USB_BP_14 0xfc44 154 #define USB_BP_15 0xfc46 155 #define USB_BP2_EN 0xfc48 156 157 /* OCP Registers */ 158 #define OCP_ALDPS_CONFIG 0x2010 159 #define OCP_EEE_CONFIG1 0x2080 160 #define OCP_EEE_CONFIG2 0x2092 161 #define OCP_EEE_CONFIG3 0x2094 162 #define OCP_BASE_MII 0xa400 163 #define OCP_EEE_AR 0xa41a 164 #define OCP_EEE_DATA 0xa41c 165 #define OCP_PHY_STATUS 0xa420 166 #define OCP_NCTL_CFG 0xa42c 167 #define OCP_POWER_CFG 0xa430 168 #define OCP_EEE_CFG 0xa432 169 #define OCP_SRAM_ADDR 0xa436 170 #define OCP_SRAM_DATA 0xa438 171 #define OCP_DOWN_SPEED 0xa442 172 #define OCP_EEE_ABLE 0xa5c4 173 #define OCP_EEE_ADV 0xa5d0 174 #define OCP_EEE_LPABLE 0xa5d2 175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 176 #define OCP_PHY_PATCH_STAT 0xb800 177 #define OCP_PHY_PATCH_CMD 0xb820 178 #define OCP_ADC_IOFFSET 0xbcfc 179 #define OCP_ADC_CFG 0xbc06 180 #define OCP_SYSCLK_CFG 0xc416 181 182 /* SRAM Register */ 183 #define SRAM_GREEN_CFG 0x8011 184 #define SRAM_LPF_CFG 0x8012 185 #define SRAM_10M_AMP1 0x8080 186 #define SRAM_10M_AMP2 0x8082 187 #define SRAM_IMPEDANCE 0x8084 188 189 /* PLA_RCR */ 190 #define RCR_AAP 0x00000001 191 #define RCR_APM 0x00000002 192 #define RCR_AM 0x00000004 193 #define RCR_AB 0x00000008 194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 195 196 /* PLA_RXFIFO_CTRL0 */ 197 #define RXFIFO_THR1_NORMAL 0x00080002 198 #define RXFIFO_THR1_OOB 0x01800003 199 200 /* PLA_RXFIFO_CTRL1 */ 201 #define RXFIFO_THR2_FULL 0x00000060 202 #define RXFIFO_THR2_HIGH 0x00000038 203 #define RXFIFO_THR2_OOB 0x0000004a 204 #define RXFIFO_THR2_NORMAL 0x00a0 205 206 /* PLA_RXFIFO_CTRL2 */ 207 #define RXFIFO_THR3_FULL 0x00000078 208 #define RXFIFO_THR3_HIGH 0x00000048 209 #define RXFIFO_THR3_OOB 0x0000005a 210 #define RXFIFO_THR3_NORMAL 0x0110 211 212 /* PLA_TXFIFO_CTRL */ 213 #define TXFIFO_THR_NORMAL 0x00400008 214 #define TXFIFO_THR_NORMAL2 0x01000008 215 216 /* PLA_DMY_REG0 */ 217 #define ECM_ALDPS 0x0002 218 219 /* PLA_FMC */ 220 #define FMC_FCR_MCU_EN 0x0001 221 222 /* PLA_EEEP_CR */ 223 #define EEEP_CR_EEEP_TX 0x0002 224 225 /* PLA_WDT6_CTRL */ 226 #define WDT6_SET_MODE 0x0010 227 228 /* PLA_TCR0 */ 229 #define TCR0_TX_EMPTY 0x0800 230 #define TCR0_AUTO_FIFO 0x0080 231 232 /* PLA_TCR1 */ 233 #define VERSION_MASK 0x7cf0 234 235 /* PLA_MTPS */ 236 #define MTPS_JUMBO (12 * 1024 / 64) 237 #define MTPS_DEFAULT (6 * 1024 / 64) 238 239 /* PLA_RSTTALLY */ 240 #define TALLY_RESET 0x0001 241 242 /* PLA_CR */ 243 #define CR_RST 0x10 244 #define CR_RE 0x08 245 #define CR_TE 0x04 246 247 /* PLA_CRWECR */ 248 #define CRWECR_NORAML 0x00 249 #define CRWECR_CONFIG 0xc0 250 251 /* PLA_OOB_CTRL */ 252 #define NOW_IS_OOB 0x80 253 #define TXFIFO_EMPTY 0x20 254 #define RXFIFO_EMPTY 0x10 255 #define LINK_LIST_READY 0x02 256 #define DIS_MCU_CLROOB 0x01 257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 258 259 /* PLA_MISC_1 */ 260 #define RXDY_GATED_EN 0x0008 261 262 /* PLA_SFF_STS_7 */ 263 #define RE_INIT_LL 0x8000 264 #define MCU_BORW_EN 0x4000 265 266 /* PLA_CPCR */ 267 #define CPCR_RX_VLAN 0x0040 268 269 /* PLA_CFG_WOL */ 270 #define MAGIC_EN 0x0001 271 272 /* PLA_TEREDO_CFG */ 273 #define TEREDO_SEL 0x8000 274 #define TEREDO_WAKE_MASK 0x7f00 275 #define TEREDO_RS_EVENT_MASK 0x00fe 276 #define OOB_TEREDO_EN 0x0001 277 278 /* PLA_BDC_CR */ 279 #define ALDPS_PROXY_MODE 0x0001 280 281 /* PLA_EFUSE_CMD */ 282 #define EFUSE_READ_CMD BIT(15) 283 #define EFUSE_DATA_BIT16 BIT(7) 284 285 /* PLA_CONFIG34 */ 286 #define LINK_ON_WAKE_EN 0x0010 287 #define LINK_OFF_WAKE_EN 0x0008 288 289 /* PLA_CONFIG5 */ 290 #define BWF_EN 0x0040 291 #define MWF_EN 0x0020 292 #define UWF_EN 0x0010 293 #define LAN_WAKE_EN 0x0002 294 295 /* PLA_LED_FEATURE */ 296 #define LED_MODE_MASK 0x0700 297 298 /* PLA_PHY_PWR */ 299 #define TX_10M_IDLE_EN 0x0080 300 #define PFM_PWM_SWITCH 0x0040 301 302 /* PLA_MAC_PWR_CTRL */ 303 #define D3_CLK_GATED_EN 0x00004000 304 #define MCU_CLK_RATIO 0x07010f07 305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 306 #define ALDPS_SPDWN_RATIO 0x0f87 307 308 /* PLA_MAC_PWR_CTRL2 */ 309 #define EEE_SPDWN_RATIO 0x8007 310 #define MAC_CLK_SPDWN_EN BIT(15) 311 312 /* PLA_MAC_PWR_CTRL3 */ 313 #define PKT_AVAIL_SPDWN_EN 0x0100 314 #define SUSPEND_SPDWN_EN 0x0004 315 #define U1U2_SPDWN_EN 0x0002 316 #define L1_SPDWN_EN 0x0001 317 318 /* PLA_MAC_PWR_CTRL4 */ 319 #define PWRSAVE_SPDWN_EN 0x1000 320 #define RXDV_SPDWN_EN 0x0800 321 #define TX10MIDLE_EN 0x0100 322 #define TP100_SPDWN_EN 0x0020 323 #define TP500_SPDWN_EN 0x0010 324 #define TP1000_SPDWN_EN 0x0008 325 #define EEE_SPDWN_EN 0x0001 326 327 /* PLA_GPHY_INTR_IMR */ 328 #define GPHY_STS_MSK 0x0001 329 #define SPEED_DOWN_MSK 0x0002 330 #define SPDWN_RXDV_MSK 0x0004 331 #define SPDWN_LINKCHG_MSK 0x0008 332 333 /* PLA_PHYAR */ 334 #define PHYAR_FLAG 0x80000000 335 336 /* PLA_EEE_CR */ 337 #define EEE_RX_EN 0x0001 338 #define EEE_TX_EN 0x0002 339 340 /* PLA_BOOT_CTRL */ 341 #define AUTOLOAD_DONE 0x0002 342 343 /* PLA_SUSPEND_FLAG */ 344 #define LINK_CHG_EVENT BIT(0) 345 346 /* PLA_INDICATE_FALG */ 347 #define UPCOMING_RUNTIME_D3 BIT(0) 348 349 /* PLA_EXTRA_STATUS */ 350 #define LINK_CHANGE_FLAG BIT(8) 351 352 /* USB_USB2PHY */ 353 #define USB2PHY_SUSPEND 0x0001 354 #define USB2PHY_L1 0x0002 355 356 /* USB_SSPHYLINK2 */ 357 #define pwd_dn_scale_mask 0x3ffe 358 #define pwd_dn_scale(x) ((x) << 1) 359 360 /* USB_CSR_DUMMY1 */ 361 #define DYNAMIC_BURST 0x0001 362 363 /* USB_CSR_DUMMY2 */ 364 #define EP4_FULL_FC 0x0001 365 366 /* USB_DEV_STAT */ 367 #define STAT_SPEED_MASK 0x0006 368 #define STAT_SPEED_HIGH 0x0000 369 #define STAT_SPEED_FULL 0x0002 370 371 /* USB_LPM_CONFIG */ 372 #define LPM_U1U2_EN BIT(0) 373 374 /* USB_TX_AGG */ 375 #define TX_AGG_MAX_THRESHOLD 0x03 376 377 /* USB_RX_BUF_TH */ 378 #define RX_THR_SUPPER 0x0c350180 379 #define RX_THR_HIGH 0x7a120180 380 #define RX_THR_SLOW 0xffff0180 381 #define RX_THR_B 0x00010001 382 383 /* USB_TX_DMA */ 384 #define TEST_MODE_DISABLE 0x00000001 385 #define TX_SIZE_ADJUST1 0x00000100 386 387 /* USB_BMU_RESET */ 388 #define BMU_RESET_EP_IN 0x01 389 #define BMU_RESET_EP_OUT 0x02 390 391 /* USB_UPT_RXDMA_OWN */ 392 #define OWN_UPDATE BIT(0) 393 #define OWN_CLEAR BIT(1) 394 395 /* USB_UPS_CTRL */ 396 #define POWER_CUT 0x0100 397 398 /* USB_PM_CTRL_STATUS */ 399 #define RESUME_INDICATE 0x0001 400 401 /* USB_USB_CTRL */ 402 #define RX_AGG_DISABLE 0x0010 403 #define RX_ZERO_EN 0x0080 404 405 /* USB_U2P3_CTRL */ 406 #define U2P3_ENABLE 0x0001 407 408 /* USB_POWER_CUT */ 409 #define PWR_EN 0x0001 410 #define PHASE2_EN 0x0008 411 #define UPS_EN BIT(4) 412 #define USP_PREWAKE BIT(5) 413 414 /* USB_MISC_0 */ 415 #define PCUT_STATUS 0x0001 416 417 /* USB_RX_EARLY_TIMEOUT */ 418 #define COALESCE_SUPER 85000U 419 #define COALESCE_HIGH 250000U 420 #define COALESCE_SLOW 524280U 421 422 /* USB_WDT11_CTRL */ 423 #define TIMER11_EN 0x0001 424 425 /* USB_LPM_CTRL */ 426 /* bit 4 ~ 5: fifo empty boundary */ 427 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 428 /* bit 2 ~ 3: LMP timer */ 429 #define LPM_TIMER_MASK 0x0c 430 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 431 #define LPM_TIMER_500US 0x0c /* 500 us */ 432 #define ROK_EXIT_LPM 0x02 433 434 /* USB_AFE_CTRL2 */ 435 #define SEN_VAL_MASK 0xf800 436 #define SEN_VAL_NORMAL 0xa000 437 #define SEL_RXIDLE 0x0100 438 439 /* USB_UPS_CFG */ 440 #define SAW_CNT_1MS_MASK 0x0fff 441 442 /* USB_UPS_FLAGS */ 443 #define UPS_FLAGS_R_TUNE BIT(0) 444 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 445 #define UPS_FLAGS_250M_CKDIV BIT(2) 446 #define UPS_FLAGS_EN_ALDPS BIT(3) 447 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 448 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 449 #define ups_flags_speed(x) ((x) << 16) 450 #define UPS_FLAGS_EN_EEE BIT(20) 451 #define UPS_FLAGS_EN_500M_EEE BIT(21) 452 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 453 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 454 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 455 #define UPS_FLAGS_EN_GREEN BIT(26) 456 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 457 458 enum spd_duplex { 459 NWAY_10M_HALF = 1, 460 NWAY_10M_FULL, 461 NWAY_100M_HALF, 462 NWAY_100M_FULL, 463 NWAY_1000M_FULL, 464 FORCE_10M_HALF, 465 FORCE_10M_FULL, 466 FORCE_100M_HALF, 467 FORCE_100M_FULL, 468 }; 469 470 /* OCP_ALDPS_CONFIG */ 471 #define ENPWRSAVE 0x8000 472 #define ENPDNPS 0x0200 473 #define LINKENA 0x0100 474 #define DIS_SDSAVE 0x0010 475 476 /* OCP_PHY_STATUS */ 477 #define PHY_STAT_MASK 0x0007 478 #define PHY_STAT_EXT_INIT 2 479 #define PHY_STAT_LAN_ON 3 480 #define PHY_STAT_PWRDN 5 481 482 /* OCP_NCTL_CFG */ 483 #define PGA_RETURN_EN BIT(1) 484 485 /* OCP_POWER_CFG */ 486 #define EEE_CLKDIV_EN 0x8000 487 #define EN_ALDPS 0x0004 488 #define EN_10M_PLLOFF 0x0001 489 490 /* OCP_EEE_CONFIG1 */ 491 #define RG_TXLPI_MSK_HFDUP 0x8000 492 #define RG_MATCLR_EN 0x4000 493 #define EEE_10_CAP 0x2000 494 #define EEE_NWAY_EN 0x1000 495 #define TX_QUIET_EN 0x0200 496 #define RX_QUIET_EN 0x0100 497 #define sd_rise_time_mask 0x0070 498 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 499 #define RG_RXLPI_MSK_HFDUP 0x0008 500 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 501 502 /* OCP_EEE_CONFIG2 */ 503 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 504 #define RG_DACQUIET_EN 0x0400 505 #define RG_LDVQUIET_EN 0x0200 506 #define RG_CKRSEL 0x0020 507 #define RG_EEEPRG_EN 0x0010 508 509 /* OCP_EEE_CONFIG3 */ 510 #define fast_snr_mask 0xff80 511 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 512 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 513 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 514 515 /* OCP_EEE_AR */ 516 /* bit[15:14] function */ 517 #define FUN_ADDR 0x0000 518 #define FUN_DATA 0x4000 519 /* bit[4:0] device addr */ 520 521 /* OCP_EEE_CFG */ 522 #define CTAP_SHORT_EN 0x0040 523 #define EEE10_EN 0x0010 524 525 /* OCP_DOWN_SPEED */ 526 #define EN_EEE_CMODE BIT(14) 527 #define EN_EEE_1000 BIT(13) 528 #define EN_EEE_100 BIT(12) 529 #define EN_10M_CLKDIV BIT(11) 530 #define EN_10M_BGOFF 0x0080 531 532 /* OCP_PHY_STATE */ 533 #define TXDIS_STATE 0x01 534 #define ABD_STATE 0x02 535 536 /* OCP_PHY_PATCH_STAT */ 537 #define PATCH_READY BIT(6) 538 539 /* OCP_PHY_PATCH_CMD */ 540 #define PATCH_REQUEST BIT(4) 541 542 /* OCP_ADC_CFG */ 543 #define CKADSEL_L 0x0100 544 #define ADC_EN 0x0080 545 #define EN_EMI_L 0x0040 546 547 /* OCP_SYSCLK_CFG */ 548 #define clk_div_expo(x) (min(x, 5) << 8) 549 550 /* SRAM_GREEN_CFG */ 551 #define GREEN_ETH_EN BIT(15) 552 #define R_TUNE_EN BIT(11) 553 554 /* SRAM_LPF_CFG */ 555 #define LPF_AUTO_TUNE 0x8000 556 557 /* SRAM_10M_AMP1 */ 558 #define GDAC_IB_UPALL 0x0008 559 560 /* SRAM_10M_AMP2 */ 561 #define AMP_DN 0x0200 562 563 /* SRAM_IMPEDANCE */ 564 #define RX_DRIVING_MASK 0x6000 565 566 /* MAC PASSTHRU */ 567 #define AD_MASK 0xfee0 568 #define BND_MASK 0x0004 569 #define BD_MASK 0x0001 570 #define EFUSE 0xcfdb 571 #define PASS_THRU_MASK 0x1 572 573 enum rtl_register_content { 574 _1000bps = 0x10, 575 _100bps = 0x08, 576 _10bps = 0x04, 577 LINK_STATUS = 0x02, 578 FULL_DUP = 0x01, 579 }; 580 581 #define RTL8152_MAX_TX 4 582 #define RTL8152_MAX_RX 10 583 #define INTBUFSIZE 2 584 #define TX_ALIGN 4 585 #define RX_ALIGN 8 586 587 #define RTL8152_RX_MAX_PENDING 4096 588 #define RTL8152_RXFG_HEADSZ 256 589 590 #define INTR_LINK 0x0004 591 592 #define RTL8152_REQT_READ 0xc0 593 #define RTL8152_REQT_WRITE 0x40 594 #define RTL8152_REQ_GET_REGS 0x05 595 #define RTL8152_REQ_SET_REGS 0x05 596 597 #define BYTE_EN_DWORD 0xff 598 #define BYTE_EN_WORD 0x33 599 #define BYTE_EN_BYTE 0x11 600 #define BYTE_EN_SIX_BYTES 0x3f 601 #define BYTE_EN_START_MASK 0x0f 602 #define BYTE_EN_END_MASK 0xf0 603 604 #define RTL8153_MAX_PACKET 9216 /* 9K */ 605 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 606 ETH_FCS_LEN) 607 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 608 #define RTL8153_RMS RTL8153_MAX_PACKET 609 #define RTL8152_TX_TIMEOUT (5 * HZ) 610 #define RTL8152_NAPI_WEIGHT 64 611 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 612 sizeof(struct rx_desc) + RX_ALIGN) 613 614 /* rtl8152 flags */ 615 enum rtl8152_flags { 616 RTL8152_UNPLUG = 0, 617 RTL8152_SET_RX_MODE, 618 WORK_ENABLE, 619 RTL8152_LINK_CHG, 620 SELECTIVE_SUSPEND, 621 PHY_RESET, 622 SCHEDULE_NAPI, 623 GREEN_ETHERNET, 624 DELL_TB_RX_AGG_BUG, 625 }; 626 627 /* Define these values to match your device */ 628 #define VENDOR_ID_REALTEK 0x0bda 629 #define VENDOR_ID_MICROSOFT 0x045e 630 #define VENDOR_ID_SAMSUNG 0x04e8 631 #define VENDOR_ID_LENOVO 0x17ef 632 #define VENDOR_ID_LINKSYS 0x13b1 633 #define VENDOR_ID_NVIDIA 0x0955 634 #define VENDOR_ID_TPLINK 0x2357 635 636 #define MCU_TYPE_PLA 0x0100 637 #define MCU_TYPE_USB 0x0000 638 639 struct tally_counter { 640 __le64 tx_packets; 641 __le64 rx_packets; 642 __le64 tx_errors; 643 __le32 rx_errors; 644 __le16 rx_missed; 645 __le16 align_errors; 646 __le32 tx_one_collision; 647 __le32 tx_multi_collision; 648 __le64 rx_unicast; 649 __le64 rx_broadcast; 650 __le32 rx_multicast; 651 __le16 tx_aborted; 652 __le16 tx_underrun; 653 }; 654 655 struct rx_desc { 656 __le32 opts1; 657 #define RX_LEN_MASK 0x7fff 658 659 __le32 opts2; 660 #define RD_UDP_CS BIT(23) 661 #define RD_TCP_CS BIT(22) 662 #define RD_IPV6_CS BIT(20) 663 #define RD_IPV4_CS BIT(19) 664 665 __le32 opts3; 666 #define IPF BIT(23) /* IP checksum fail */ 667 #define UDPF BIT(22) /* UDP checksum fail */ 668 #define TCPF BIT(21) /* TCP checksum fail */ 669 #define RX_VLAN_TAG BIT(16) 670 671 __le32 opts4; 672 __le32 opts5; 673 __le32 opts6; 674 }; 675 676 struct tx_desc { 677 __le32 opts1; 678 #define TX_FS BIT(31) /* First segment of a packet */ 679 #define TX_LS BIT(30) /* Final segment of a packet */ 680 #define GTSENDV4 BIT(28) 681 #define GTSENDV6 BIT(27) 682 #define GTTCPHO_SHIFT 18 683 #define GTTCPHO_MAX 0x7fU 684 #define TX_LEN_MAX 0x3ffffU 685 686 __le32 opts2; 687 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 688 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 689 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 690 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 691 #define MSS_SHIFT 17 692 #define MSS_MAX 0x7ffU 693 #define TCPHO_SHIFT 17 694 #define TCPHO_MAX 0x7ffU 695 #define TX_VLAN_TAG BIT(16) 696 }; 697 698 struct r8152; 699 700 struct rx_agg { 701 struct list_head list, info_list; 702 struct urb *urb; 703 struct r8152 *context; 704 struct page *page; 705 void *buffer; 706 }; 707 708 struct tx_agg { 709 struct list_head list; 710 struct urb *urb; 711 struct r8152 *context; 712 void *buffer; 713 void *head; 714 u32 skb_num; 715 u32 skb_len; 716 }; 717 718 struct r8152 { 719 unsigned long flags; 720 struct usb_device *udev; 721 struct napi_struct napi; 722 struct usb_interface *intf; 723 struct net_device *netdev; 724 struct urb *intr_urb; 725 struct tx_agg tx_info[RTL8152_MAX_TX]; 726 struct list_head rx_info, rx_used; 727 struct list_head rx_done, tx_free; 728 struct sk_buff_head tx_queue, rx_queue; 729 spinlock_t rx_lock, tx_lock; 730 struct delayed_work schedule, hw_phy_work; 731 struct mii_if_info mii; 732 struct mutex control; /* use for hw setting */ 733 #ifdef CONFIG_PM_SLEEP 734 struct notifier_block pm_notifier; 735 #endif 736 737 struct rtl_ops { 738 void (*init)(struct r8152 *); 739 int (*enable)(struct r8152 *); 740 void (*disable)(struct r8152 *); 741 void (*up)(struct r8152 *); 742 void (*down)(struct r8152 *); 743 void (*unload)(struct r8152 *); 744 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 745 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 746 bool (*in_nway)(struct r8152 *); 747 void (*hw_phy_cfg)(struct r8152 *); 748 void (*autosuspend_en)(struct r8152 *tp, bool enable); 749 } rtl_ops; 750 751 atomic_t rx_count; 752 753 int intr_interval; 754 u32 saved_wolopts; 755 u32 msg_enable; 756 u32 tx_qlen; 757 u32 coalesce; 758 u32 rx_buf_sz; 759 u32 rx_copybreak; 760 u32 rx_pending; 761 762 u16 ocp_base; 763 u16 speed; 764 u8 *intr_buff; 765 u8 version; 766 u8 duplex; 767 u8 autoneg; 768 }; 769 770 enum rtl_version { 771 RTL_VER_UNKNOWN = 0, 772 RTL_VER_01, 773 RTL_VER_02, 774 RTL_VER_03, 775 RTL_VER_04, 776 RTL_VER_05, 777 RTL_VER_06, 778 RTL_VER_07, 779 RTL_VER_08, 780 RTL_VER_09, 781 RTL_VER_MAX 782 }; 783 784 enum tx_csum_stat { 785 TX_CSUM_SUCCESS = 0, 786 TX_CSUM_TSO, 787 TX_CSUM_NONE 788 }; 789 790 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 791 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 792 */ 793 static const int multicast_filter_limit = 32; 794 static unsigned int agg_buf_sz = 16384; 795 796 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 797 VLAN_ETH_HLEN - ETH_FCS_LEN) 798 799 static 800 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 801 { 802 int ret; 803 void *tmp; 804 805 tmp = kmalloc(size, GFP_KERNEL); 806 if (!tmp) 807 return -ENOMEM; 808 809 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 810 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 811 value, index, tmp, size, 500); 812 813 memcpy(data, tmp, size); 814 kfree(tmp); 815 816 return ret; 817 } 818 819 static 820 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 821 { 822 int ret; 823 void *tmp; 824 825 tmp = kmemdup(data, size, GFP_KERNEL); 826 if (!tmp) 827 return -ENOMEM; 828 829 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 830 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 831 value, index, tmp, size, 500); 832 833 kfree(tmp); 834 835 return ret; 836 } 837 838 static void rtl_set_unplug(struct r8152 *tp) 839 { 840 if (tp->udev->state == USB_STATE_NOTATTACHED) { 841 set_bit(RTL8152_UNPLUG, &tp->flags); 842 smp_mb__after_atomic(); 843 } 844 } 845 846 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 847 void *data, u16 type) 848 { 849 u16 limit = 64; 850 int ret = 0; 851 852 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 853 return -ENODEV; 854 855 /* both size and indix must be 4 bytes align */ 856 if ((size & 3) || !size || (index & 3) || !data) 857 return -EPERM; 858 859 if ((u32)index + (u32)size > 0xffff) 860 return -EPERM; 861 862 while (size) { 863 if (size > limit) { 864 ret = get_registers(tp, index, type, limit, data); 865 if (ret < 0) 866 break; 867 868 index += limit; 869 data += limit; 870 size -= limit; 871 } else { 872 ret = get_registers(tp, index, type, size, data); 873 if (ret < 0) 874 break; 875 876 index += size; 877 data += size; 878 size = 0; 879 break; 880 } 881 } 882 883 if (ret == -ENODEV) 884 rtl_set_unplug(tp); 885 886 return ret; 887 } 888 889 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 890 u16 size, void *data, u16 type) 891 { 892 int ret; 893 u16 byteen_start, byteen_end, byen; 894 u16 limit = 512; 895 896 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 897 return -ENODEV; 898 899 /* both size and indix must be 4 bytes align */ 900 if ((size & 3) || !size || (index & 3) || !data) 901 return -EPERM; 902 903 if ((u32)index + (u32)size > 0xffff) 904 return -EPERM; 905 906 byteen_start = byteen & BYTE_EN_START_MASK; 907 byteen_end = byteen & BYTE_EN_END_MASK; 908 909 byen = byteen_start | (byteen_start << 4); 910 ret = set_registers(tp, index, type | byen, 4, data); 911 if (ret < 0) 912 goto error1; 913 914 index += 4; 915 data += 4; 916 size -= 4; 917 918 if (size) { 919 size -= 4; 920 921 while (size) { 922 if (size > limit) { 923 ret = set_registers(tp, index, 924 type | BYTE_EN_DWORD, 925 limit, data); 926 if (ret < 0) 927 goto error1; 928 929 index += limit; 930 data += limit; 931 size -= limit; 932 } else { 933 ret = set_registers(tp, index, 934 type | BYTE_EN_DWORD, 935 size, data); 936 if (ret < 0) 937 goto error1; 938 939 index += size; 940 data += size; 941 size = 0; 942 break; 943 } 944 } 945 946 byen = byteen_end | (byteen_end >> 4); 947 ret = set_registers(tp, index, type | byen, 4, data); 948 if (ret < 0) 949 goto error1; 950 } 951 952 error1: 953 if (ret == -ENODEV) 954 rtl_set_unplug(tp); 955 956 return ret; 957 } 958 959 static inline 960 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 961 { 962 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 963 } 964 965 static inline 966 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 967 { 968 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 969 } 970 971 static inline 972 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 973 { 974 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 975 } 976 977 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 978 { 979 __le32 data; 980 981 generic_ocp_read(tp, index, sizeof(data), &data, type); 982 983 return __le32_to_cpu(data); 984 } 985 986 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 987 { 988 __le32 tmp = __cpu_to_le32(data); 989 990 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 991 } 992 993 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 994 { 995 u32 data; 996 __le32 tmp; 997 u16 byen = BYTE_EN_WORD; 998 u8 shift = index & 2; 999 1000 index &= ~3; 1001 byen <<= shift; 1002 1003 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 1004 1005 data = __le32_to_cpu(tmp); 1006 data >>= (shift * 8); 1007 data &= 0xffff; 1008 1009 return (u16)data; 1010 } 1011 1012 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1013 { 1014 u32 mask = 0xffff; 1015 __le32 tmp; 1016 u16 byen = BYTE_EN_WORD; 1017 u8 shift = index & 2; 1018 1019 data &= mask; 1020 1021 if (index & 2) { 1022 byen <<= shift; 1023 mask <<= (shift * 8); 1024 data <<= (shift * 8); 1025 index &= ~3; 1026 } 1027 1028 tmp = __cpu_to_le32(data); 1029 1030 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1031 } 1032 1033 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1034 { 1035 u32 data; 1036 __le32 tmp; 1037 u8 shift = index & 3; 1038 1039 index &= ~3; 1040 1041 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1042 1043 data = __le32_to_cpu(tmp); 1044 data >>= (shift * 8); 1045 data &= 0xff; 1046 1047 return (u8)data; 1048 } 1049 1050 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1051 { 1052 u32 mask = 0xff; 1053 __le32 tmp; 1054 u16 byen = BYTE_EN_BYTE; 1055 u8 shift = index & 3; 1056 1057 data &= mask; 1058 1059 if (index & 3) { 1060 byen <<= shift; 1061 mask <<= (shift * 8); 1062 data <<= (shift * 8); 1063 index &= ~3; 1064 } 1065 1066 tmp = __cpu_to_le32(data); 1067 1068 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1069 } 1070 1071 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1072 { 1073 u16 ocp_base, ocp_index; 1074 1075 ocp_base = addr & 0xf000; 1076 if (ocp_base != tp->ocp_base) { 1077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1078 tp->ocp_base = ocp_base; 1079 } 1080 1081 ocp_index = (addr & 0x0fff) | 0xb000; 1082 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1083 } 1084 1085 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1086 { 1087 u16 ocp_base, ocp_index; 1088 1089 ocp_base = addr & 0xf000; 1090 if (ocp_base != tp->ocp_base) { 1091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1092 tp->ocp_base = ocp_base; 1093 } 1094 1095 ocp_index = (addr & 0x0fff) | 0xb000; 1096 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1097 } 1098 1099 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1100 { 1101 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1102 } 1103 1104 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1105 { 1106 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1107 } 1108 1109 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1110 { 1111 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1112 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1113 } 1114 1115 static u16 sram_read(struct r8152 *tp, u16 addr) 1116 { 1117 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1118 return ocp_reg_read(tp, OCP_SRAM_DATA); 1119 } 1120 1121 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1122 { 1123 struct r8152 *tp = netdev_priv(netdev); 1124 int ret; 1125 1126 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1127 return -ENODEV; 1128 1129 if (phy_id != R8152_PHY_ID) 1130 return -EINVAL; 1131 1132 ret = r8152_mdio_read(tp, reg); 1133 1134 return ret; 1135 } 1136 1137 static 1138 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1139 { 1140 struct r8152 *tp = netdev_priv(netdev); 1141 1142 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1143 return; 1144 1145 if (phy_id != R8152_PHY_ID) 1146 return; 1147 1148 r8152_mdio_write(tp, reg, val); 1149 } 1150 1151 static int 1152 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1153 1154 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1155 { 1156 struct r8152 *tp = netdev_priv(netdev); 1157 struct sockaddr *addr = p; 1158 int ret = -EADDRNOTAVAIL; 1159 1160 if (!is_valid_ether_addr(addr->sa_data)) 1161 goto out1; 1162 1163 ret = usb_autopm_get_interface(tp->intf); 1164 if (ret < 0) 1165 goto out1; 1166 1167 mutex_lock(&tp->control); 1168 1169 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1170 1171 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1172 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1173 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1174 1175 mutex_unlock(&tp->control); 1176 1177 usb_autopm_put_interface(tp->intf); 1178 out1: 1179 return ret; 1180 } 1181 1182 /* Devices containing proper chips can support a persistent 1183 * host system provided MAC address. 1184 * Examples of this are Dell TB15 and Dell WD15 docks 1185 */ 1186 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1187 { 1188 acpi_status status; 1189 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1190 union acpi_object *obj; 1191 int ret = -EINVAL; 1192 u32 ocp_data; 1193 unsigned char buf[6]; 1194 1195 /* test for -AD variant of RTL8153 */ 1196 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1197 if ((ocp_data & AD_MASK) == 0x1000) { 1198 /* test for MAC address pass-through bit */ 1199 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1200 if ((ocp_data & PASS_THRU_MASK) != 1) { 1201 netif_dbg(tp, probe, tp->netdev, 1202 "No efuse for RTL8153-AD MAC pass through\n"); 1203 return -ENODEV; 1204 } 1205 } else { 1206 /* test for RTL8153-BND and RTL8153-BD */ 1207 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1208 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1209 netif_dbg(tp, probe, tp->netdev, 1210 "Invalid variant for MAC pass through\n"); 1211 return -ENODEV; 1212 } 1213 } 1214 1215 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1216 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1217 obj = (union acpi_object *)buffer.pointer; 1218 if (!ACPI_SUCCESS(status)) 1219 return -ENODEV; 1220 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1221 netif_warn(tp, probe, tp->netdev, 1222 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1223 obj->type, obj->string.length); 1224 goto amacout; 1225 } 1226 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1227 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1228 netif_warn(tp, probe, tp->netdev, 1229 "Invalid header when reading pass-thru MAC addr\n"); 1230 goto amacout; 1231 } 1232 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1233 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1234 netif_warn(tp, probe, tp->netdev, 1235 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1236 ret, buf); 1237 ret = -EINVAL; 1238 goto amacout; 1239 } 1240 memcpy(sa->sa_data, buf, 6); 1241 netif_info(tp, probe, tp->netdev, 1242 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1243 1244 amacout: 1245 kfree(obj); 1246 return ret; 1247 } 1248 1249 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1250 { 1251 struct net_device *dev = tp->netdev; 1252 int ret; 1253 1254 sa->sa_family = dev->type; 1255 1256 if (tp->version == RTL_VER_01) { 1257 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1258 } else { 1259 /* if device doesn't support MAC pass through this will 1260 * be expected to be non-zero 1261 */ 1262 ret = vendor_mac_passthru_addr_read(tp, sa); 1263 if (ret < 0) 1264 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1265 } 1266 1267 if (ret < 0) { 1268 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1269 } else if (!is_valid_ether_addr(sa->sa_data)) { 1270 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1271 sa->sa_data); 1272 eth_hw_addr_random(dev); 1273 ether_addr_copy(sa->sa_data, dev->dev_addr); 1274 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1275 sa->sa_data); 1276 return 0; 1277 } 1278 1279 return ret; 1280 } 1281 1282 static int set_ethernet_addr(struct r8152 *tp) 1283 { 1284 struct net_device *dev = tp->netdev; 1285 struct sockaddr sa; 1286 int ret; 1287 1288 ret = determine_ethernet_addr(tp, &sa); 1289 if (ret < 0) 1290 return ret; 1291 1292 if (tp->version == RTL_VER_01) 1293 ether_addr_copy(dev->dev_addr, sa.sa_data); 1294 else 1295 ret = rtl8152_set_mac_address(dev, &sa); 1296 1297 return ret; 1298 } 1299 1300 static void read_bulk_callback(struct urb *urb) 1301 { 1302 struct net_device *netdev; 1303 int status = urb->status; 1304 struct rx_agg *agg; 1305 struct r8152 *tp; 1306 unsigned long flags; 1307 1308 agg = urb->context; 1309 if (!agg) 1310 return; 1311 1312 tp = agg->context; 1313 if (!tp) 1314 return; 1315 1316 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1317 return; 1318 1319 if (!test_bit(WORK_ENABLE, &tp->flags)) 1320 return; 1321 1322 netdev = tp->netdev; 1323 1324 /* When link down, the driver would cancel all bulks. */ 1325 /* This avoid the re-submitting bulk */ 1326 if (!netif_carrier_ok(netdev)) 1327 return; 1328 1329 usb_mark_last_busy(tp->udev); 1330 1331 switch (status) { 1332 case 0: 1333 if (urb->actual_length < ETH_ZLEN) 1334 break; 1335 1336 spin_lock_irqsave(&tp->rx_lock, flags); 1337 list_add_tail(&agg->list, &tp->rx_done); 1338 spin_unlock_irqrestore(&tp->rx_lock, flags); 1339 napi_schedule(&tp->napi); 1340 return; 1341 case -ESHUTDOWN: 1342 rtl_set_unplug(tp); 1343 netif_device_detach(tp->netdev); 1344 return; 1345 case -ENOENT: 1346 return; /* the urb is in unlink state */ 1347 case -ETIME: 1348 if (net_ratelimit()) 1349 netdev_warn(netdev, "maybe reset is needed?\n"); 1350 break; 1351 default: 1352 if (net_ratelimit()) 1353 netdev_warn(netdev, "Rx status %d\n", status); 1354 break; 1355 } 1356 1357 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1358 } 1359 1360 static void write_bulk_callback(struct urb *urb) 1361 { 1362 struct net_device_stats *stats; 1363 struct net_device *netdev; 1364 struct tx_agg *agg; 1365 struct r8152 *tp; 1366 unsigned long flags; 1367 int status = urb->status; 1368 1369 agg = urb->context; 1370 if (!agg) 1371 return; 1372 1373 tp = agg->context; 1374 if (!tp) 1375 return; 1376 1377 netdev = tp->netdev; 1378 stats = &netdev->stats; 1379 if (status) { 1380 if (net_ratelimit()) 1381 netdev_warn(netdev, "Tx status %d\n", status); 1382 stats->tx_errors += agg->skb_num; 1383 } else { 1384 stats->tx_packets += agg->skb_num; 1385 stats->tx_bytes += agg->skb_len; 1386 } 1387 1388 spin_lock_irqsave(&tp->tx_lock, flags); 1389 list_add_tail(&agg->list, &tp->tx_free); 1390 spin_unlock_irqrestore(&tp->tx_lock, flags); 1391 1392 usb_autopm_put_interface_async(tp->intf); 1393 1394 if (!netif_carrier_ok(netdev)) 1395 return; 1396 1397 if (!test_bit(WORK_ENABLE, &tp->flags)) 1398 return; 1399 1400 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1401 return; 1402 1403 if (!skb_queue_empty(&tp->tx_queue)) 1404 napi_schedule(&tp->napi); 1405 } 1406 1407 static void intr_callback(struct urb *urb) 1408 { 1409 struct r8152 *tp; 1410 __le16 *d; 1411 int status = urb->status; 1412 int res; 1413 1414 tp = urb->context; 1415 if (!tp) 1416 return; 1417 1418 if (!test_bit(WORK_ENABLE, &tp->flags)) 1419 return; 1420 1421 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1422 return; 1423 1424 switch (status) { 1425 case 0: /* success */ 1426 break; 1427 case -ECONNRESET: /* unlink */ 1428 case -ESHUTDOWN: 1429 netif_device_detach(tp->netdev); 1430 /* fall through */ 1431 case -ENOENT: 1432 case -EPROTO: 1433 netif_info(tp, intr, tp->netdev, 1434 "Stop submitting intr, status %d\n", status); 1435 return; 1436 case -EOVERFLOW: 1437 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1438 goto resubmit; 1439 /* -EPIPE: should clear the halt */ 1440 default: 1441 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1442 goto resubmit; 1443 } 1444 1445 d = urb->transfer_buffer; 1446 if (INTR_LINK & __le16_to_cpu(d[0])) { 1447 if (!netif_carrier_ok(tp->netdev)) { 1448 set_bit(RTL8152_LINK_CHG, &tp->flags); 1449 schedule_delayed_work(&tp->schedule, 0); 1450 } 1451 } else { 1452 if (netif_carrier_ok(tp->netdev)) { 1453 netif_stop_queue(tp->netdev); 1454 set_bit(RTL8152_LINK_CHG, &tp->flags); 1455 schedule_delayed_work(&tp->schedule, 0); 1456 } 1457 } 1458 1459 resubmit: 1460 res = usb_submit_urb(urb, GFP_ATOMIC); 1461 if (res == -ENODEV) { 1462 rtl_set_unplug(tp); 1463 netif_device_detach(tp->netdev); 1464 } else if (res) { 1465 netif_err(tp, intr, tp->netdev, 1466 "can't resubmit intr, status %d\n", res); 1467 } 1468 } 1469 1470 static inline void *rx_agg_align(void *data) 1471 { 1472 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1473 } 1474 1475 static inline void *tx_agg_align(void *data) 1476 { 1477 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1478 } 1479 1480 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) 1481 { 1482 list_del(&agg->info_list); 1483 1484 usb_free_urb(agg->urb); 1485 put_page(agg->page); 1486 kfree(agg); 1487 1488 atomic_dec(&tp->rx_count); 1489 } 1490 1491 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) 1492 { 1493 struct net_device *netdev = tp->netdev; 1494 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1495 unsigned int order = get_order(tp->rx_buf_sz); 1496 struct rx_agg *rx_agg; 1497 unsigned long flags; 1498 1499 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); 1500 if (!rx_agg) 1501 return NULL; 1502 1503 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order); 1504 if (!rx_agg->page) 1505 goto free_rx; 1506 1507 rx_agg->buffer = page_address(rx_agg->page); 1508 1509 rx_agg->urb = usb_alloc_urb(0, mflags); 1510 if (!rx_agg->urb) 1511 goto free_buf; 1512 1513 rx_agg->context = tp; 1514 1515 INIT_LIST_HEAD(&rx_agg->list); 1516 INIT_LIST_HEAD(&rx_agg->info_list); 1517 spin_lock_irqsave(&tp->rx_lock, flags); 1518 list_add_tail(&rx_agg->info_list, &tp->rx_info); 1519 spin_unlock_irqrestore(&tp->rx_lock, flags); 1520 1521 atomic_inc(&tp->rx_count); 1522 1523 return rx_agg; 1524 1525 free_buf: 1526 __free_pages(rx_agg->page, order); 1527 free_rx: 1528 kfree(rx_agg); 1529 return NULL; 1530 } 1531 1532 static void free_all_mem(struct r8152 *tp) 1533 { 1534 struct rx_agg *agg, *agg_next; 1535 unsigned long flags; 1536 int i; 1537 1538 spin_lock_irqsave(&tp->rx_lock, flags); 1539 1540 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) 1541 free_rx_agg(tp, agg); 1542 1543 spin_unlock_irqrestore(&tp->rx_lock, flags); 1544 1545 WARN_ON(atomic_read(&tp->rx_count)); 1546 1547 for (i = 0; i < RTL8152_MAX_TX; i++) { 1548 usb_free_urb(tp->tx_info[i].urb); 1549 tp->tx_info[i].urb = NULL; 1550 1551 kfree(tp->tx_info[i].buffer); 1552 tp->tx_info[i].buffer = NULL; 1553 tp->tx_info[i].head = NULL; 1554 } 1555 1556 usb_free_urb(tp->intr_urb); 1557 tp->intr_urb = NULL; 1558 1559 kfree(tp->intr_buff); 1560 tp->intr_buff = NULL; 1561 } 1562 1563 static int alloc_all_mem(struct r8152 *tp) 1564 { 1565 struct net_device *netdev = tp->netdev; 1566 struct usb_interface *intf = tp->intf; 1567 struct usb_host_interface *alt = intf->cur_altsetting; 1568 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1569 int node, i; 1570 1571 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1572 1573 spin_lock_init(&tp->rx_lock); 1574 spin_lock_init(&tp->tx_lock); 1575 INIT_LIST_HEAD(&tp->rx_info); 1576 INIT_LIST_HEAD(&tp->tx_free); 1577 INIT_LIST_HEAD(&tp->rx_done); 1578 skb_queue_head_init(&tp->tx_queue); 1579 skb_queue_head_init(&tp->rx_queue); 1580 atomic_set(&tp->rx_count, 0); 1581 1582 for (i = 0; i < RTL8152_MAX_RX; i++) { 1583 if (!alloc_rx_agg(tp, GFP_KERNEL)) 1584 goto err1; 1585 } 1586 1587 for (i = 0; i < RTL8152_MAX_TX; i++) { 1588 struct urb *urb; 1589 u8 *buf; 1590 1591 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1592 if (!buf) 1593 goto err1; 1594 1595 if (buf != tx_agg_align(buf)) { 1596 kfree(buf); 1597 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1598 node); 1599 if (!buf) 1600 goto err1; 1601 } 1602 1603 urb = usb_alloc_urb(0, GFP_KERNEL); 1604 if (!urb) { 1605 kfree(buf); 1606 goto err1; 1607 } 1608 1609 INIT_LIST_HEAD(&tp->tx_info[i].list); 1610 tp->tx_info[i].context = tp; 1611 tp->tx_info[i].urb = urb; 1612 tp->tx_info[i].buffer = buf; 1613 tp->tx_info[i].head = tx_agg_align(buf); 1614 1615 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1616 } 1617 1618 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1619 if (!tp->intr_urb) 1620 goto err1; 1621 1622 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1623 if (!tp->intr_buff) 1624 goto err1; 1625 1626 tp->intr_interval = (int)ep_intr->desc.bInterval; 1627 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1628 tp->intr_buff, INTBUFSIZE, intr_callback, 1629 tp, tp->intr_interval); 1630 1631 return 0; 1632 1633 err1: 1634 free_all_mem(tp); 1635 return -ENOMEM; 1636 } 1637 1638 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1639 { 1640 struct tx_agg *agg = NULL; 1641 unsigned long flags; 1642 1643 if (list_empty(&tp->tx_free)) 1644 return NULL; 1645 1646 spin_lock_irqsave(&tp->tx_lock, flags); 1647 if (!list_empty(&tp->tx_free)) { 1648 struct list_head *cursor; 1649 1650 cursor = tp->tx_free.next; 1651 list_del_init(cursor); 1652 agg = list_entry(cursor, struct tx_agg, list); 1653 } 1654 spin_unlock_irqrestore(&tp->tx_lock, flags); 1655 1656 return agg; 1657 } 1658 1659 /* r8152_csum_workaround() 1660 * The hw limites the value the transport offset. When the offset is out of the 1661 * range, calculate the checksum by sw. 1662 */ 1663 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1664 struct sk_buff_head *list) 1665 { 1666 if (skb_shinfo(skb)->gso_size) { 1667 netdev_features_t features = tp->netdev->features; 1668 struct sk_buff_head seg_list; 1669 struct sk_buff *segs, *nskb; 1670 1671 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1672 segs = skb_gso_segment(skb, features); 1673 if (IS_ERR(segs) || !segs) 1674 goto drop; 1675 1676 __skb_queue_head_init(&seg_list); 1677 1678 do { 1679 nskb = segs; 1680 segs = segs->next; 1681 nskb->next = NULL; 1682 __skb_queue_tail(&seg_list, nskb); 1683 } while (segs); 1684 1685 skb_queue_splice(&seg_list, list); 1686 dev_kfree_skb(skb); 1687 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1688 if (skb_checksum_help(skb) < 0) 1689 goto drop; 1690 1691 __skb_queue_head(list, skb); 1692 } else { 1693 struct net_device_stats *stats; 1694 1695 drop: 1696 stats = &tp->netdev->stats; 1697 stats->tx_dropped++; 1698 dev_kfree_skb(skb); 1699 } 1700 } 1701 1702 /* msdn_giant_send_check() 1703 * According to the document of microsoft, the TCP Pseudo Header excludes the 1704 * packet length for IPv6 TCP large packets. 1705 */ 1706 static int msdn_giant_send_check(struct sk_buff *skb) 1707 { 1708 const struct ipv6hdr *ipv6h; 1709 struct tcphdr *th; 1710 int ret; 1711 1712 ret = skb_cow_head(skb, 0); 1713 if (ret) 1714 return ret; 1715 1716 ipv6h = ipv6_hdr(skb); 1717 th = tcp_hdr(skb); 1718 1719 th->check = 0; 1720 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1721 1722 return ret; 1723 } 1724 1725 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1726 { 1727 if (skb_vlan_tag_present(skb)) { 1728 u32 opts2; 1729 1730 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1731 desc->opts2 |= cpu_to_le32(opts2); 1732 } 1733 } 1734 1735 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1736 { 1737 u32 opts2 = le32_to_cpu(desc->opts2); 1738 1739 if (opts2 & RX_VLAN_TAG) 1740 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1741 swab16(opts2 & 0xffff)); 1742 } 1743 1744 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1745 struct sk_buff *skb, u32 len, u32 transport_offset) 1746 { 1747 u32 mss = skb_shinfo(skb)->gso_size; 1748 u32 opts1, opts2 = 0; 1749 int ret = TX_CSUM_SUCCESS; 1750 1751 WARN_ON_ONCE(len > TX_LEN_MAX); 1752 1753 opts1 = len | TX_FS | TX_LS; 1754 1755 if (mss) { 1756 if (transport_offset > GTTCPHO_MAX) { 1757 netif_warn(tp, tx_err, tp->netdev, 1758 "Invalid transport offset 0x%x for TSO\n", 1759 transport_offset); 1760 ret = TX_CSUM_TSO; 1761 goto unavailable; 1762 } 1763 1764 switch (vlan_get_protocol(skb)) { 1765 case htons(ETH_P_IP): 1766 opts1 |= GTSENDV4; 1767 break; 1768 1769 case htons(ETH_P_IPV6): 1770 if (msdn_giant_send_check(skb)) { 1771 ret = TX_CSUM_TSO; 1772 goto unavailable; 1773 } 1774 opts1 |= GTSENDV6; 1775 break; 1776 1777 default: 1778 WARN_ON_ONCE(1); 1779 break; 1780 } 1781 1782 opts1 |= transport_offset << GTTCPHO_SHIFT; 1783 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1784 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1785 u8 ip_protocol; 1786 1787 if (transport_offset > TCPHO_MAX) { 1788 netif_warn(tp, tx_err, tp->netdev, 1789 "Invalid transport offset 0x%x\n", 1790 transport_offset); 1791 ret = TX_CSUM_NONE; 1792 goto unavailable; 1793 } 1794 1795 switch (vlan_get_protocol(skb)) { 1796 case htons(ETH_P_IP): 1797 opts2 |= IPV4_CS; 1798 ip_protocol = ip_hdr(skb)->protocol; 1799 break; 1800 1801 case htons(ETH_P_IPV6): 1802 opts2 |= IPV6_CS; 1803 ip_protocol = ipv6_hdr(skb)->nexthdr; 1804 break; 1805 1806 default: 1807 ip_protocol = IPPROTO_RAW; 1808 break; 1809 } 1810 1811 if (ip_protocol == IPPROTO_TCP) 1812 opts2 |= TCP_CS; 1813 else if (ip_protocol == IPPROTO_UDP) 1814 opts2 |= UDP_CS; 1815 else 1816 WARN_ON_ONCE(1); 1817 1818 opts2 |= transport_offset << TCPHO_SHIFT; 1819 } 1820 1821 desc->opts2 = cpu_to_le32(opts2); 1822 desc->opts1 = cpu_to_le32(opts1); 1823 1824 unavailable: 1825 return ret; 1826 } 1827 1828 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1829 { 1830 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1831 int remain, ret; 1832 u8 *tx_data; 1833 1834 __skb_queue_head_init(&skb_head); 1835 spin_lock(&tx_queue->lock); 1836 skb_queue_splice_init(tx_queue, &skb_head); 1837 spin_unlock(&tx_queue->lock); 1838 1839 tx_data = agg->head; 1840 agg->skb_num = 0; 1841 agg->skb_len = 0; 1842 remain = agg_buf_sz; 1843 1844 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1845 struct tx_desc *tx_desc; 1846 struct sk_buff *skb; 1847 unsigned int len; 1848 u32 offset; 1849 1850 skb = __skb_dequeue(&skb_head); 1851 if (!skb) 1852 break; 1853 1854 len = skb->len + sizeof(*tx_desc); 1855 1856 if (len > remain) { 1857 __skb_queue_head(&skb_head, skb); 1858 break; 1859 } 1860 1861 tx_data = tx_agg_align(tx_data); 1862 tx_desc = (struct tx_desc *)tx_data; 1863 1864 offset = (u32)skb_transport_offset(skb); 1865 1866 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1867 r8152_csum_workaround(tp, skb, &skb_head); 1868 continue; 1869 } 1870 1871 rtl_tx_vlan_tag(tx_desc, skb); 1872 1873 tx_data += sizeof(*tx_desc); 1874 1875 len = skb->len; 1876 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1877 struct net_device_stats *stats = &tp->netdev->stats; 1878 1879 stats->tx_dropped++; 1880 dev_kfree_skb_any(skb); 1881 tx_data -= sizeof(*tx_desc); 1882 continue; 1883 } 1884 1885 tx_data += len; 1886 agg->skb_len += len; 1887 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1888 1889 dev_kfree_skb_any(skb); 1890 1891 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1892 1893 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1894 break; 1895 } 1896 1897 if (!skb_queue_empty(&skb_head)) { 1898 spin_lock(&tx_queue->lock); 1899 skb_queue_splice(&skb_head, tx_queue); 1900 spin_unlock(&tx_queue->lock); 1901 } 1902 1903 netif_tx_lock(tp->netdev); 1904 1905 if (netif_queue_stopped(tp->netdev) && 1906 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1907 netif_wake_queue(tp->netdev); 1908 1909 netif_tx_unlock(tp->netdev); 1910 1911 ret = usb_autopm_get_interface_async(tp->intf); 1912 if (ret < 0) 1913 goto out_tx_fill; 1914 1915 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1916 agg->head, (int)(tx_data - (u8 *)agg->head), 1917 (usb_complete_t)write_bulk_callback, agg); 1918 1919 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1920 if (ret < 0) 1921 usb_autopm_put_interface_async(tp->intf); 1922 1923 out_tx_fill: 1924 return ret; 1925 } 1926 1927 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1928 { 1929 u8 checksum = CHECKSUM_NONE; 1930 u32 opts2, opts3; 1931 1932 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1933 goto return_result; 1934 1935 opts2 = le32_to_cpu(rx_desc->opts2); 1936 opts3 = le32_to_cpu(rx_desc->opts3); 1937 1938 if (opts2 & RD_IPV4_CS) { 1939 if (opts3 & IPF) 1940 checksum = CHECKSUM_NONE; 1941 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1942 checksum = CHECKSUM_UNNECESSARY; 1943 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1944 checksum = CHECKSUM_UNNECESSARY; 1945 } else if (opts2 & RD_IPV6_CS) { 1946 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1947 checksum = CHECKSUM_UNNECESSARY; 1948 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1949 checksum = CHECKSUM_UNNECESSARY; 1950 } 1951 1952 return_result: 1953 return checksum; 1954 } 1955 1956 static inline bool rx_count_exceed(struct r8152 *tp) 1957 { 1958 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; 1959 } 1960 1961 static inline int agg_offset(struct rx_agg *agg, void *addr) 1962 { 1963 return (int)(addr - agg->buffer); 1964 } 1965 1966 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) 1967 { 1968 struct rx_agg *agg, *agg_next, *agg_free = NULL; 1969 unsigned long flags; 1970 1971 spin_lock_irqsave(&tp->rx_lock, flags); 1972 1973 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { 1974 if (page_count(agg->page) == 1) { 1975 if (!agg_free) { 1976 list_del_init(&agg->list); 1977 agg_free = agg; 1978 continue; 1979 } 1980 if (rx_count_exceed(tp)) { 1981 list_del_init(&agg->list); 1982 free_rx_agg(tp, agg); 1983 } 1984 break; 1985 } 1986 } 1987 1988 spin_unlock_irqrestore(&tp->rx_lock, flags); 1989 1990 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) 1991 agg_free = alloc_rx_agg(tp, mflags); 1992 1993 return agg_free; 1994 } 1995 1996 static int rx_bottom(struct r8152 *tp, int budget) 1997 { 1998 unsigned long flags; 1999 struct list_head *cursor, *next, rx_queue; 2000 int ret = 0, work_done = 0; 2001 struct napi_struct *napi = &tp->napi; 2002 2003 if (!skb_queue_empty(&tp->rx_queue)) { 2004 while (work_done < budget) { 2005 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 2006 struct net_device *netdev = tp->netdev; 2007 struct net_device_stats *stats = &netdev->stats; 2008 unsigned int pkt_len; 2009 2010 if (!skb) 2011 break; 2012 2013 pkt_len = skb->len; 2014 napi_gro_receive(napi, skb); 2015 work_done++; 2016 stats->rx_packets++; 2017 stats->rx_bytes += pkt_len; 2018 } 2019 } 2020 2021 if (list_empty(&tp->rx_done)) 2022 goto out1; 2023 2024 INIT_LIST_HEAD(&rx_queue); 2025 spin_lock_irqsave(&tp->rx_lock, flags); 2026 list_splice_init(&tp->rx_done, &rx_queue); 2027 spin_unlock_irqrestore(&tp->rx_lock, flags); 2028 2029 list_for_each_safe(cursor, next, &rx_queue) { 2030 struct rx_desc *rx_desc; 2031 struct rx_agg *agg, *agg_free; 2032 int len_used = 0; 2033 struct urb *urb; 2034 u8 *rx_data; 2035 2036 list_del_init(cursor); 2037 2038 agg = list_entry(cursor, struct rx_agg, list); 2039 urb = agg->urb; 2040 if (urb->actual_length < ETH_ZLEN) 2041 goto submit; 2042 2043 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); 2044 2045 rx_desc = agg->buffer; 2046 rx_data = agg->buffer; 2047 len_used += sizeof(struct rx_desc); 2048 2049 while (urb->actual_length > len_used) { 2050 struct net_device *netdev = tp->netdev; 2051 struct net_device_stats *stats = &netdev->stats; 2052 unsigned int pkt_len, rx_frag_head_sz; 2053 struct sk_buff *skb; 2054 2055 /* limite the skb numbers for rx_queue */ 2056 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 2057 break; 2058 2059 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2060 if (pkt_len < ETH_ZLEN) 2061 break; 2062 2063 len_used += pkt_len; 2064 if (urb->actual_length < len_used) 2065 break; 2066 2067 pkt_len -= ETH_FCS_LEN; 2068 rx_data += sizeof(struct rx_desc); 2069 2070 if (!agg_free || tp->rx_copybreak > pkt_len) 2071 rx_frag_head_sz = pkt_len; 2072 else 2073 rx_frag_head_sz = tp->rx_copybreak; 2074 2075 skb = napi_alloc_skb(napi, rx_frag_head_sz); 2076 if (!skb) { 2077 stats->rx_dropped++; 2078 goto find_next_rx; 2079 } 2080 2081 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 2082 memcpy(skb->data, rx_data, rx_frag_head_sz); 2083 skb_put(skb, rx_frag_head_sz); 2084 pkt_len -= rx_frag_head_sz; 2085 rx_data += rx_frag_head_sz; 2086 if (pkt_len) { 2087 skb_add_rx_frag(skb, 0, agg->page, 2088 agg_offset(agg, rx_data), 2089 pkt_len, 2090 SKB_DATA_ALIGN(pkt_len)); 2091 get_page(agg->page); 2092 } 2093 2094 skb->protocol = eth_type_trans(skb, netdev); 2095 rtl_rx_vlan_tag(rx_desc, skb); 2096 if (work_done < budget) { 2097 napi_gro_receive(napi, skb); 2098 work_done++; 2099 stats->rx_packets++; 2100 stats->rx_bytes += skb->len; 2101 } else { 2102 __skb_queue_tail(&tp->rx_queue, skb); 2103 } 2104 2105 find_next_rx: 2106 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 2107 rx_desc = (struct rx_desc *)rx_data; 2108 len_used = agg_offset(agg, rx_data); 2109 len_used += sizeof(struct rx_desc); 2110 } 2111 2112 WARN_ON(!agg_free && page_count(agg->page) > 1); 2113 2114 if (agg_free) { 2115 spin_lock_irqsave(&tp->rx_lock, flags); 2116 if (page_count(agg->page) == 1) { 2117 list_add(&agg_free->list, &tp->rx_used); 2118 } else { 2119 list_add_tail(&agg->list, &tp->rx_used); 2120 agg = agg_free; 2121 urb = agg->urb; 2122 } 2123 spin_unlock_irqrestore(&tp->rx_lock, flags); 2124 } 2125 2126 submit: 2127 if (!ret) { 2128 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2129 } else { 2130 urb->actual_length = 0; 2131 list_add_tail(&agg->list, next); 2132 } 2133 } 2134 2135 if (!list_empty(&rx_queue)) { 2136 spin_lock_irqsave(&tp->rx_lock, flags); 2137 list_splice_tail(&rx_queue, &tp->rx_done); 2138 spin_unlock_irqrestore(&tp->rx_lock, flags); 2139 } 2140 2141 out1: 2142 return work_done; 2143 } 2144 2145 static void tx_bottom(struct r8152 *tp) 2146 { 2147 int res; 2148 2149 do { 2150 struct tx_agg *agg; 2151 2152 if (skb_queue_empty(&tp->tx_queue)) 2153 break; 2154 2155 agg = r8152_get_tx_agg(tp); 2156 if (!agg) 2157 break; 2158 2159 res = r8152_tx_agg_fill(tp, agg); 2160 if (res) { 2161 struct net_device *netdev = tp->netdev; 2162 2163 if (res == -ENODEV) { 2164 rtl_set_unplug(tp); 2165 netif_device_detach(netdev); 2166 } else { 2167 struct net_device_stats *stats = &netdev->stats; 2168 unsigned long flags; 2169 2170 netif_warn(tp, tx_err, netdev, 2171 "failed tx_urb %d\n", res); 2172 stats->tx_dropped += agg->skb_num; 2173 2174 spin_lock_irqsave(&tp->tx_lock, flags); 2175 list_add_tail(&agg->list, &tp->tx_free); 2176 spin_unlock_irqrestore(&tp->tx_lock, flags); 2177 } 2178 } 2179 } while (res == 0); 2180 } 2181 2182 static void bottom_half(struct r8152 *tp) 2183 { 2184 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2185 return; 2186 2187 if (!test_bit(WORK_ENABLE, &tp->flags)) 2188 return; 2189 2190 /* When link down, the driver would cancel all bulks. */ 2191 /* This avoid the re-submitting bulk */ 2192 if (!netif_carrier_ok(tp->netdev)) 2193 return; 2194 2195 clear_bit(SCHEDULE_NAPI, &tp->flags); 2196 2197 tx_bottom(tp); 2198 } 2199 2200 static int r8152_poll(struct napi_struct *napi, int budget) 2201 { 2202 struct r8152 *tp = container_of(napi, struct r8152, napi); 2203 int work_done; 2204 2205 work_done = rx_bottom(tp, budget); 2206 bottom_half(tp); 2207 2208 if (work_done < budget) { 2209 if (!napi_complete_done(napi, work_done)) 2210 goto out; 2211 if (!list_empty(&tp->rx_done)) 2212 napi_schedule(napi); 2213 else if (!skb_queue_empty(&tp->tx_queue) && 2214 !list_empty(&tp->tx_free)) 2215 napi_schedule(napi); 2216 } 2217 2218 out: 2219 return work_done; 2220 } 2221 2222 static 2223 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2224 { 2225 int ret; 2226 2227 /* The rx would be stopped, so skip submitting */ 2228 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2229 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2230 return 0; 2231 2232 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2233 agg->buffer, tp->rx_buf_sz, 2234 (usb_complete_t)read_bulk_callback, agg); 2235 2236 ret = usb_submit_urb(agg->urb, mem_flags); 2237 if (ret == -ENODEV) { 2238 rtl_set_unplug(tp); 2239 netif_device_detach(tp->netdev); 2240 } else if (ret) { 2241 struct urb *urb = agg->urb; 2242 unsigned long flags; 2243 2244 urb->actual_length = 0; 2245 spin_lock_irqsave(&tp->rx_lock, flags); 2246 list_add_tail(&agg->list, &tp->rx_done); 2247 spin_unlock_irqrestore(&tp->rx_lock, flags); 2248 2249 netif_err(tp, rx_err, tp->netdev, 2250 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2251 2252 napi_schedule(&tp->napi); 2253 } 2254 2255 return ret; 2256 } 2257 2258 static void rtl_drop_queued_tx(struct r8152 *tp) 2259 { 2260 struct net_device_stats *stats = &tp->netdev->stats; 2261 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2262 struct sk_buff *skb; 2263 2264 if (skb_queue_empty(tx_queue)) 2265 return; 2266 2267 __skb_queue_head_init(&skb_head); 2268 spin_lock_bh(&tx_queue->lock); 2269 skb_queue_splice_init(tx_queue, &skb_head); 2270 spin_unlock_bh(&tx_queue->lock); 2271 2272 while ((skb = __skb_dequeue(&skb_head))) { 2273 dev_kfree_skb(skb); 2274 stats->tx_dropped++; 2275 } 2276 } 2277 2278 static void rtl8152_tx_timeout(struct net_device *netdev) 2279 { 2280 struct r8152 *tp = netdev_priv(netdev); 2281 2282 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2283 2284 usb_queue_reset_device(tp->intf); 2285 } 2286 2287 static void rtl8152_set_rx_mode(struct net_device *netdev) 2288 { 2289 struct r8152 *tp = netdev_priv(netdev); 2290 2291 if (netif_carrier_ok(netdev)) { 2292 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2293 schedule_delayed_work(&tp->schedule, 0); 2294 } 2295 } 2296 2297 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2298 { 2299 struct r8152 *tp = netdev_priv(netdev); 2300 u32 mc_filter[2]; /* Multicast hash filter */ 2301 __le32 tmp[2]; 2302 u32 ocp_data; 2303 2304 netif_stop_queue(netdev); 2305 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2306 ocp_data &= ~RCR_ACPT_ALL; 2307 ocp_data |= RCR_AB | RCR_APM; 2308 2309 if (netdev->flags & IFF_PROMISC) { 2310 /* Unconditionally log net taps. */ 2311 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2312 ocp_data |= RCR_AM | RCR_AAP; 2313 mc_filter[1] = 0xffffffff; 2314 mc_filter[0] = 0xffffffff; 2315 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2316 (netdev->flags & IFF_ALLMULTI)) { 2317 /* Too many to filter perfectly -- accept all multicasts. */ 2318 ocp_data |= RCR_AM; 2319 mc_filter[1] = 0xffffffff; 2320 mc_filter[0] = 0xffffffff; 2321 } else { 2322 struct netdev_hw_addr *ha; 2323 2324 mc_filter[1] = 0; 2325 mc_filter[0] = 0; 2326 netdev_for_each_mc_addr(ha, netdev) { 2327 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2328 2329 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2330 ocp_data |= RCR_AM; 2331 } 2332 } 2333 2334 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2335 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2336 2337 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2338 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2339 netif_wake_queue(netdev); 2340 } 2341 2342 static netdev_features_t 2343 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2344 netdev_features_t features) 2345 { 2346 u32 mss = skb_shinfo(skb)->gso_size; 2347 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2348 int offset = skb_transport_offset(skb); 2349 2350 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2351 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2352 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2353 features &= ~NETIF_F_GSO_MASK; 2354 2355 return features; 2356 } 2357 2358 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2359 struct net_device *netdev) 2360 { 2361 struct r8152 *tp = netdev_priv(netdev); 2362 2363 skb_tx_timestamp(skb); 2364 2365 skb_queue_tail(&tp->tx_queue, skb); 2366 2367 if (!list_empty(&tp->tx_free)) { 2368 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2369 set_bit(SCHEDULE_NAPI, &tp->flags); 2370 schedule_delayed_work(&tp->schedule, 0); 2371 } else { 2372 usb_mark_last_busy(tp->udev); 2373 napi_schedule(&tp->napi); 2374 } 2375 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2376 netif_stop_queue(netdev); 2377 } 2378 2379 return NETDEV_TX_OK; 2380 } 2381 2382 static void r8152b_reset_packet_filter(struct r8152 *tp) 2383 { 2384 u32 ocp_data; 2385 2386 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2387 ocp_data &= ~FMC_FCR_MCU_EN; 2388 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2389 ocp_data |= FMC_FCR_MCU_EN; 2390 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2391 } 2392 2393 static void rtl8152_nic_reset(struct r8152 *tp) 2394 { 2395 int i; 2396 2397 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2398 2399 for (i = 0; i < 1000; i++) { 2400 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2401 break; 2402 usleep_range(100, 400); 2403 } 2404 } 2405 2406 static void set_tx_qlen(struct r8152 *tp) 2407 { 2408 struct net_device *netdev = tp->netdev; 2409 2410 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2411 sizeof(struct tx_desc)); 2412 } 2413 2414 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2415 { 2416 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2417 } 2418 2419 static void rtl_set_eee_plus(struct r8152 *tp) 2420 { 2421 u32 ocp_data; 2422 u8 speed; 2423 2424 speed = rtl8152_get_speed(tp); 2425 if (speed & _10bps) { 2426 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2427 ocp_data |= EEEP_CR_EEEP_TX; 2428 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2429 } else { 2430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2431 ocp_data &= ~EEEP_CR_EEEP_TX; 2432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2433 } 2434 } 2435 2436 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2437 { 2438 u32 ocp_data; 2439 2440 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2441 if (enable) 2442 ocp_data |= RXDY_GATED_EN; 2443 else 2444 ocp_data &= ~RXDY_GATED_EN; 2445 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2446 } 2447 2448 static int rtl_start_rx(struct r8152 *tp) 2449 { 2450 struct rx_agg *agg, *agg_next; 2451 struct list_head tmp_list; 2452 unsigned long flags; 2453 int ret = 0, i = 0; 2454 2455 INIT_LIST_HEAD(&tmp_list); 2456 2457 spin_lock_irqsave(&tp->rx_lock, flags); 2458 2459 INIT_LIST_HEAD(&tp->rx_done); 2460 INIT_LIST_HEAD(&tp->rx_used); 2461 2462 list_splice_init(&tp->rx_info, &tmp_list); 2463 2464 spin_unlock_irqrestore(&tp->rx_lock, flags); 2465 2466 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2467 INIT_LIST_HEAD(&agg->list); 2468 2469 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ 2470 if (++i > RTL8152_MAX_RX) { 2471 spin_lock_irqsave(&tp->rx_lock, flags); 2472 list_add_tail(&agg->list, &tp->rx_used); 2473 spin_unlock_irqrestore(&tp->rx_lock, flags); 2474 } else if (unlikely(ret < 0)) { 2475 spin_lock_irqsave(&tp->rx_lock, flags); 2476 list_add_tail(&agg->list, &tp->rx_done); 2477 spin_unlock_irqrestore(&tp->rx_lock, flags); 2478 } else { 2479 ret = r8152_submit_rx(tp, agg, GFP_KERNEL); 2480 } 2481 } 2482 2483 spin_lock_irqsave(&tp->rx_lock, flags); 2484 WARN_ON(!list_empty(&tp->rx_info)); 2485 list_splice(&tmp_list, &tp->rx_info); 2486 spin_unlock_irqrestore(&tp->rx_lock, flags); 2487 2488 return ret; 2489 } 2490 2491 static int rtl_stop_rx(struct r8152 *tp) 2492 { 2493 struct rx_agg *agg, *agg_next; 2494 struct list_head tmp_list; 2495 unsigned long flags; 2496 2497 INIT_LIST_HEAD(&tmp_list); 2498 2499 /* The usb_kill_urb() couldn't be used in atomic. 2500 * Therefore, move the list of rx_info to a tmp one. 2501 * Then, list_for_each_entry_safe could be used without 2502 * spin lock. 2503 */ 2504 2505 spin_lock_irqsave(&tp->rx_lock, flags); 2506 list_splice_init(&tp->rx_info, &tmp_list); 2507 spin_unlock_irqrestore(&tp->rx_lock, flags); 2508 2509 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2510 /* At least RTL8152_MAX_RX rx_agg have the page_count being 2511 * equal to 1, so the other ones could be freed safely. 2512 */ 2513 if (page_count(agg->page) > 1) 2514 free_rx_agg(tp, agg); 2515 else 2516 usb_kill_urb(agg->urb); 2517 } 2518 2519 /* Move back the list of temp to the rx_info */ 2520 spin_lock_irqsave(&tp->rx_lock, flags); 2521 WARN_ON(!list_empty(&tp->rx_info)); 2522 list_splice(&tmp_list, &tp->rx_info); 2523 spin_unlock_irqrestore(&tp->rx_lock, flags); 2524 2525 while (!skb_queue_empty(&tp->rx_queue)) 2526 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2527 2528 return 0; 2529 } 2530 2531 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2532 { 2533 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2534 OWN_UPDATE | OWN_CLEAR); 2535 } 2536 2537 static int rtl_enable(struct r8152 *tp) 2538 { 2539 u32 ocp_data; 2540 2541 r8152b_reset_packet_filter(tp); 2542 2543 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2544 ocp_data |= CR_RE | CR_TE; 2545 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2546 2547 switch (tp->version) { 2548 case RTL_VER_08: 2549 case RTL_VER_09: 2550 r8153b_rx_agg_chg_indicate(tp); 2551 break; 2552 default: 2553 break; 2554 } 2555 2556 rxdy_gated_en(tp, false); 2557 2558 return 0; 2559 } 2560 2561 static int rtl8152_enable(struct r8152 *tp) 2562 { 2563 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2564 return -ENODEV; 2565 2566 set_tx_qlen(tp); 2567 rtl_set_eee_plus(tp); 2568 2569 return rtl_enable(tp); 2570 } 2571 2572 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2573 { 2574 u32 ocp_data = tp->coalesce / 8; 2575 2576 switch (tp->version) { 2577 case RTL_VER_03: 2578 case RTL_VER_04: 2579 case RTL_VER_05: 2580 case RTL_VER_06: 2581 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2582 ocp_data); 2583 break; 2584 2585 case RTL_VER_08: 2586 case RTL_VER_09: 2587 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2588 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2589 */ 2590 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2591 128 / 8); 2592 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2593 ocp_data); 2594 break; 2595 2596 default: 2597 break; 2598 } 2599 } 2600 2601 static void r8153_set_rx_early_size(struct r8152 *tp) 2602 { 2603 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 2604 2605 switch (tp->version) { 2606 case RTL_VER_03: 2607 case RTL_VER_04: 2608 case RTL_VER_05: 2609 case RTL_VER_06: 2610 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2611 ocp_data / 4); 2612 break; 2613 case RTL_VER_08: 2614 case RTL_VER_09: 2615 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2616 ocp_data / 8); 2617 break; 2618 default: 2619 WARN_ON_ONCE(1); 2620 break; 2621 } 2622 } 2623 2624 static int rtl8153_enable(struct r8152 *tp) 2625 { 2626 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2627 return -ENODEV; 2628 2629 set_tx_qlen(tp); 2630 rtl_set_eee_plus(tp); 2631 r8153_set_rx_early_timeout(tp); 2632 r8153_set_rx_early_size(tp); 2633 2634 return rtl_enable(tp); 2635 } 2636 2637 static void rtl_disable(struct r8152 *tp) 2638 { 2639 u32 ocp_data; 2640 int i; 2641 2642 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2643 rtl_drop_queued_tx(tp); 2644 return; 2645 } 2646 2647 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2648 ocp_data &= ~RCR_ACPT_ALL; 2649 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2650 2651 rtl_drop_queued_tx(tp); 2652 2653 for (i = 0; i < RTL8152_MAX_TX; i++) 2654 usb_kill_urb(tp->tx_info[i].urb); 2655 2656 rxdy_gated_en(tp, true); 2657 2658 for (i = 0; i < 1000; i++) { 2659 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2660 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2661 break; 2662 usleep_range(1000, 2000); 2663 } 2664 2665 for (i = 0; i < 1000; i++) { 2666 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2667 break; 2668 usleep_range(1000, 2000); 2669 } 2670 2671 rtl_stop_rx(tp); 2672 2673 rtl8152_nic_reset(tp); 2674 } 2675 2676 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2677 { 2678 u32 ocp_data; 2679 2680 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2681 if (enable) 2682 ocp_data |= POWER_CUT; 2683 else 2684 ocp_data &= ~POWER_CUT; 2685 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2686 2687 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2688 ocp_data &= ~RESUME_INDICATE; 2689 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2690 } 2691 2692 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2693 { 2694 u32 ocp_data; 2695 2696 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2697 if (enable) 2698 ocp_data |= CPCR_RX_VLAN; 2699 else 2700 ocp_data &= ~CPCR_RX_VLAN; 2701 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2702 } 2703 2704 static int rtl8152_set_features(struct net_device *dev, 2705 netdev_features_t features) 2706 { 2707 netdev_features_t changed = features ^ dev->features; 2708 struct r8152 *tp = netdev_priv(dev); 2709 int ret; 2710 2711 ret = usb_autopm_get_interface(tp->intf); 2712 if (ret < 0) 2713 goto out; 2714 2715 mutex_lock(&tp->control); 2716 2717 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2718 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2719 rtl_rx_vlan_en(tp, true); 2720 else 2721 rtl_rx_vlan_en(tp, false); 2722 } 2723 2724 mutex_unlock(&tp->control); 2725 2726 usb_autopm_put_interface(tp->intf); 2727 2728 out: 2729 return ret; 2730 } 2731 2732 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2733 2734 static u32 __rtl_get_wol(struct r8152 *tp) 2735 { 2736 u32 ocp_data; 2737 u32 wolopts = 0; 2738 2739 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2740 if (ocp_data & LINK_ON_WAKE_EN) 2741 wolopts |= WAKE_PHY; 2742 2743 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2744 if (ocp_data & UWF_EN) 2745 wolopts |= WAKE_UCAST; 2746 if (ocp_data & BWF_EN) 2747 wolopts |= WAKE_BCAST; 2748 if (ocp_data & MWF_EN) 2749 wolopts |= WAKE_MCAST; 2750 2751 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2752 if (ocp_data & MAGIC_EN) 2753 wolopts |= WAKE_MAGIC; 2754 2755 return wolopts; 2756 } 2757 2758 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2759 { 2760 u32 ocp_data; 2761 2762 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2763 2764 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2765 ocp_data &= ~LINK_ON_WAKE_EN; 2766 if (wolopts & WAKE_PHY) 2767 ocp_data |= LINK_ON_WAKE_EN; 2768 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2769 2770 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2771 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2772 if (wolopts & WAKE_UCAST) 2773 ocp_data |= UWF_EN; 2774 if (wolopts & WAKE_BCAST) 2775 ocp_data |= BWF_EN; 2776 if (wolopts & WAKE_MCAST) 2777 ocp_data |= MWF_EN; 2778 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2779 2780 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2781 2782 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2783 ocp_data &= ~MAGIC_EN; 2784 if (wolopts & WAKE_MAGIC) 2785 ocp_data |= MAGIC_EN; 2786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2787 2788 if (wolopts & WAKE_ANY) 2789 device_set_wakeup_enable(&tp->udev->dev, true); 2790 else 2791 device_set_wakeup_enable(&tp->udev->dev, false); 2792 } 2793 2794 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2795 { 2796 /* MAC clock speed down */ 2797 if (enable) { 2798 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2799 ALDPS_SPDWN_RATIO); 2800 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2801 EEE_SPDWN_RATIO); 2802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2803 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2804 U1U2_SPDWN_EN | L1_SPDWN_EN); 2805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2806 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2807 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2808 TP1000_SPDWN_EN); 2809 } else { 2810 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2811 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2812 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2813 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2814 } 2815 } 2816 2817 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2818 { 2819 u8 u1u2[8]; 2820 2821 if (enable) 2822 memset(u1u2, 0xff, sizeof(u1u2)); 2823 else 2824 memset(u1u2, 0x00, sizeof(u1u2)); 2825 2826 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2827 } 2828 2829 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2830 { 2831 u32 ocp_data; 2832 2833 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2834 if (enable) 2835 ocp_data |= LPM_U1U2_EN; 2836 else 2837 ocp_data &= ~LPM_U1U2_EN; 2838 2839 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2840 } 2841 2842 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2843 { 2844 u32 ocp_data; 2845 2846 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2847 if (enable) 2848 ocp_data |= U2P3_ENABLE; 2849 else 2850 ocp_data &= ~U2P3_ENABLE; 2851 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2852 } 2853 2854 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2855 { 2856 u32 ocp_data; 2857 2858 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2859 ocp_data &= ~clear; 2860 ocp_data |= set; 2861 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2862 } 2863 2864 static void r8153b_green_en(struct r8152 *tp, bool enable) 2865 { 2866 u16 data; 2867 2868 if (enable) { 2869 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2870 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2871 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2872 } else { 2873 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2874 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2875 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2876 } 2877 2878 data = sram_read(tp, SRAM_GREEN_CFG); 2879 data |= GREEN_ETH_EN; 2880 sram_write(tp, SRAM_GREEN_CFG, data); 2881 2882 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2883 } 2884 2885 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2886 { 2887 u16 data; 2888 int i; 2889 2890 for (i = 0; i < 500; i++) { 2891 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2892 data &= PHY_STAT_MASK; 2893 if (desired) { 2894 if (data == desired) 2895 break; 2896 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2897 data == PHY_STAT_EXT_INIT) { 2898 break; 2899 } 2900 2901 msleep(20); 2902 } 2903 2904 return data; 2905 } 2906 2907 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2908 { 2909 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2910 2911 if (enable) { 2912 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2913 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2914 2915 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2916 ocp_data |= BIT(0); 2917 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2918 } else { 2919 u16 data; 2920 2921 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2922 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2923 2924 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2925 ocp_data &= ~BIT(0); 2926 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2927 2928 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2929 ocp_data &= ~PCUT_STATUS; 2930 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2931 2932 data = r8153_phy_status(tp, 0); 2933 2934 switch (data) { 2935 case PHY_STAT_PWRDN: 2936 case PHY_STAT_EXT_INIT: 2937 r8153b_green_en(tp, 2938 test_bit(GREEN_ETHERNET, &tp->flags)); 2939 2940 data = r8152_mdio_read(tp, MII_BMCR); 2941 data &= ~BMCR_PDOWN; 2942 data |= BMCR_RESET; 2943 r8152_mdio_write(tp, MII_BMCR, data); 2944 2945 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2946 /* fall through */ 2947 2948 default: 2949 if (data != PHY_STAT_LAN_ON) 2950 netif_warn(tp, link, tp->netdev, 2951 "PHY not ready"); 2952 break; 2953 } 2954 } 2955 } 2956 2957 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2958 { 2959 u32 ocp_data; 2960 2961 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2962 if (enable) 2963 ocp_data |= PWR_EN | PHASE2_EN; 2964 else 2965 ocp_data &= ~(PWR_EN | PHASE2_EN); 2966 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2967 2968 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2969 ocp_data &= ~PCUT_STATUS; 2970 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2971 } 2972 2973 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2974 { 2975 u32 ocp_data; 2976 2977 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2978 if (enable) 2979 ocp_data |= PWR_EN | PHASE2_EN; 2980 else 2981 ocp_data &= ~PWR_EN; 2982 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2983 2984 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2985 ocp_data &= ~PCUT_STATUS; 2986 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2987 } 2988 2989 static void r8153_queue_wake(struct r8152 *tp, bool enable) 2990 { 2991 u32 ocp_data; 2992 2993 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 2994 if (enable) 2995 ocp_data |= UPCOMING_RUNTIME_D3; 2996 else 2997 ocp_data &= ~UPCOMING_RUNTIME_D3; 2998 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 2999 3000 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 3001 ocp_data &= ~LINK_CHG_EVENT; 3002 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 3003 3004 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 3005 ocp_data &= ~LINK_CHANGE_FLAG; 3006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 3007 } 3008 3009 static bool rtl_can_wakeup(struct r8152 *tp) 3010 { 3011 struct usb_device *udev = tp->udev; 3012 3013 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 3014 } 3015 3016 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 3017 { 3018 if (enable) { 3019 u32 ocp_data; 3020 3021 __rtl_set_wol(tp, WAKE_ANY); 3022 3023 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3024 3025 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3026 ocp_data |= LINK_OFF_WAKE_EN; 3027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3028 3029 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3030 } else { 3031 u32 ocp_data; 3032 3033 __rtl_set_wol(tp, tp->saved_wolopts); 3034 3035 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3036 3037 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3038 ocp_data &= ~LINK_OFF_WAKE_EN; 3039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3040 3041 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3042 } 3043 } 3044 3045 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 3046 { 3047 if (enable) { 3048 r8153_u1u2en(tp, false); 3049 r8153_u2p3en(tp, false); 3050 r8153_mac_clk_spd(tp, true); 3051 rtl_runtime_suspend_enable(tp, true); 3052 } else { 3053 rtl_runtime_suspend_enable(tp, false); 3054 r8153_mac_clk_spd(tp, false); 3055 3056 switch (tp->version) { 3057 case RTL_VER_03: 3058 case RTL_VER_04: 3059 break; 3060 case RTL_VER_05: 3061 case RTL_VER_06: 3062 default: 3063 r8153_u2p3en(tp, true); 3064 break; 3065 } 3066 3067 r8153_u1u2en(tp, true); 3068 } 3069 } 3070 3071 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 3072 { 3073 if (enable) { 3074 r8153_queue_wake(tp, true); 3075 r8153b_u1u2en(tp, false); 3076 r8153_u2p3en(tp, false); 3077 rtl_runtime_suspend_enable(tp, true); 3078 r8153b_ups_en(tp, true); 3079 } else { 3080 r8153b_ups_en(tp, false); 3081 r8153_queue_wake(tp, false); 3082 rtl_runtime_suspend_enable(tp, false); 3083 r8153_u2p3en(tp, true); 3084 r8153b_u1u2en(tp, true); 3085 } 3086 } 3087 3088 static void r8153_teredo_off(struct r8152 *tp) 3089 { 3090 u32 ocp_data; 3091 3092 switch (tp->version) { 3093 case RTL_VER_01: 3094 case RTL_VER_02: 3095 case RTL_VER_03: 3096 case RTL_VER_04: 3097 case RTL_VER_05: 3098 case RTL_VER_06: 3099 case RTL_VER_07: 3100 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3101 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 3102 OOB_TEREDO_EN); 3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3104 break; 3105 3106 case RTL_VER_08: 3107 case RTL_VER_09: 3108 /* The bit 0 ~ 7 are relative with teredo settings. They are 3109 * W1C (write 1 to clear), so set all 1 to disable it. 3110 */ 3111 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 3112 break; 3113 3114 default: 3115 break; 3116 } 3117 3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 3119 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 3120 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 3121 } 3122 3123 static void rtl_reset_bmu(struct r8152 *tp) 3124 { 3125 u32 ocp_data; 3126 3127 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 3128 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 3129 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3130 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 3131 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3132 } 3133 3134 static void r8152_aldps_en(struct r8152 *tp, bool enable) 3135 { 3136 if (enable) { 3137 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 3138 LINKENA | DIS_SDSAVE); 3139 } else { 3140 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 3141 DIS_SDSAVE); 3142 msleep(20); 3143 } 3144 } 3145 3146 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3147 { 3148 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3149 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3150 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3151 } 3152 3153 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3154 { 3155 u16 data; 3156 3157 r8152_mmd_indirect(tp, dev, reg); 3158 data = ocp_reg_read(tp, OCP_EEE_DATA); 3159 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3160 3161 return data; 3162 } 3163 3164 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3165 { 3166 r8152_mmd_indirect(tp, dev, reg); 3167 ocp_reg_write(tp, OCP_EEE_DATA, data); 3168 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3169 } 3170 3171 static void r8152_eee_en(struct r8152 *tp, bool enable) 3172 { 3173 u16 config1, config2, config3; 3174 u32 ocp_data; 3175 3176 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3177 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3178 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3179 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3180 3181 if (enable) { 3182 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3183 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3184 config1 |= sd_rise_time(1); 3185 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3186 config3 |= fast_snr(42); 3187 } else { 3188 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3189 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3190 RX_QUIET_EN); 3191 config1 |= sd_rise_time(7); 3192 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3193 config3 |= fast_snr(511); 3194 } 3195 3196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3197 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3198 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3199 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3200 } 3201 3202 static void r8152b_enable_eee(struct r8152 *tp) 3203 { 3204 r8152_eee_en(tp, true); 3205 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3206 } 3207 3208 static void r8152b_enable_fc(struct r8152 *tp) 3209 { 3210 u16 anar; 3211 3212 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3213 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3214 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3215 } 3216 3217 static void rtl8152_disable(struct r8152 *tp) 3218 { 3219 r8152_aldps_en(tp, false); 3220 rtl_disable(tp); 3221 r8152_aldps_en(tp, true); 3222 } 3223 3224 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3225 { 3226 r8152b_enable_eee(tp); 3227 r8152_aldps_en(tp, true); 3228 r8152b_enable_fc(tp); 3229 3230 set_bit(PHY_RESET, &tp->flags); 3231 } 3232 3233 static void r8152b_exit_oob(struct r8152 *tp) 3234 { 3235 u32 ocp_data; 3236 int i; 3237 3238 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3239 ocp_data &= ~RCR_ACPT_ALL; 3240 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3241 3242 rxdy_gated_en(tp, true); 3243 r8153_teredo_off(tp); 3244 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3245 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3246 3247 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3248 ocp_data &= ~NOW_IS_OOB; 3249 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3250 3251 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3252 ocp_data &= ~MCU_BORW_EN; 3253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3254 3255 for (i = 0; i < 1000; i++) { 3256 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3257 if (ocp_data & LINK_LIST_READY) 3258 break; 3259 usleep_range(1000, 2000); 3260 } 3261 3262 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3263 ocp_data |= RE_INIT_LL; 3264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3265 3266 for (i = 0; i < 1000; i++) { 3267 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3268 if (ocp_data & LINK_LIST_READY) 3269 break; 3270 usleep_range(1000, 2000); 3271 } 3272 3273 rtl8152_nic_reset(tp); 3274 3275 /* rx share fifo credit full threshold */ 3276 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3277 3278 if (tp->udev->speed == USB_SPEED_FULL || 3279 tp->udev->speed == USB_SPEED_LOW) { 3280 /* rx share fifo credit near full threshold */ 3281 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3282 RXFIFO_THR2_FULL); 3283 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3284 RXFIFO_THR3_FULL); 3285 } else { 3286 /* rx share fifo credit near full threshold */ 3287 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3288 RXFIFO_THR2_HIGH); 3289 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3290 RXFIFO_THR3_HIGH); 3291 } 3292 3293 /* TX share fifo free credit full threshold */ 3294 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3295 3296 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3297 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3298 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3299 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3300 3301 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3302 3303 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3304 3305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3306 ocp_data |= TCR0_AUTO_FIFO; 3307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3308 } 3309 3310 static void r8152b_enter_oob(struct r8152 *tp) 3311 { 3312 u32 ocp_data; 3313 int i; 3314 3315 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3316 ocp_data &= ~NOW_IS_OOB; 3317 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3318 3319 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3320 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3321 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3322 3323 rtl_disable(tp); 3324 3325 for (i = 0; i < 1000; i++) { 3326 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3327 if (ocp_data & LINK_LIST_READY) 3328 break; 3329 usleep_range(1000, 2000); 3330 } 3331 3332 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3333 ocp_data |= RE_INIT_LL; 3334 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3335 3336 for (i = 0; i < 1000; i++) { 3337 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3338 if (ocp_data & LINK_LIST_READY) 3339 break; 3340 usleep_range(1000, 2000); 3341 } 3342 3343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3344 3345 rtl_rx_vlan_en(tp, true); 3346 3347 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3348 ocp_data |= ALDPS_PROXY_MODE; 3349 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3350 3351 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3352 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3353 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3354 3355 rxdy_gated_en(tp, false); 3356 3357 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3358 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3359 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3360 } 3361 3362 static int r8153_patch_request(struct r8152 *tp, bool request) 3363 { 3364 u16 data; 3365 int i; 3366 3367 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3368 if (request) 3369 data |= PATCH_REQUEST; 3370 else 3371 data &= ~PATCH_REQUEST; 3372 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3373 3374 for (i = 0; request && i < 5000; i++) { 3375 usleep_range(1000, 2000); 3376 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3377 break; 3378 } 3379 3380 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3381 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3382 r8153_patch_request(tp, false); 3383 return -ETIME; 3384 } else { 3385 return 0; 3386 } 3387 } 3388 3389 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3390 { 3391 u16 data; 3392 3393 data = ocp_reg_read(tp, OCP_POWER_CFG); 3394 if (enable) { 3395 data |= EN_ALDPS; 3396 ocp_reg_write(tp, OCP_POWER_CFG, data); 3397 } else { 3398 int i; 3399 3400 data &= ~EN_ALDPS; 3401 ocp_reg_write(tp, OCP_POWER_CFG, data); 3402 for (i = 0; i < 20; i++) { 3403 usleep_range(1000, 2000); 3404 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3405 break; 3406 } 3407 } 3408 } 3409 3410 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3411 { 3412 r8153_aldps_en(tp, enable); 3413 3414 if (enable) 3415 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3416 else 3417 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3418 } 3419 3420 static void r8153_eee_en(struct r8152 *tp, bool enable) 3421 { 3422 u32 ocp_data; 3423 u16 config; 3424 3425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3426 config = ocp_reg_read(tp, OCP_EEE_CFG); 3427 3428 if (enable) { 3429 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3430 config |= EEE10_EN; 3431 } else { 3432 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3433 config &= ~EEE10_EN; 3434 } 3435 3436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3437 ocp_reg_write(tp, OCP_EEE_CFG, config); 3438 } 3439 3440 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3441 { 3442 r8153_eee_en(tp, enable); 3443 3444 if (enable) 3445 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3446 else 3447 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3448 } 3449 3450 static void r8153b_enable_fc(struct r8152 *tp) 3451 { 3452 r8152b_enable_fc(tp); 3453 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3454 } 3455 3456 static void r8153_hw_phy_cfg(struct r8152 *tp) 3457 { 3458 u32 ocp_data; 3459 u16 data; 3460 3461 /* disable ALDPS before updating the PHY parameters */ 3462 r8153_aldps_en(tp, false); 3463 3464 /* disable EEE before updating the PHY parameters */ 3465 r8153_eee_en(tp, false); 3466 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3467 3468 if (tp->version == RTL_VER_03) { 3469 data = ocp_reg_read(tp, OCP_EEE_CFG); 3470 data &= ~CTAP_SHORT_EN; 3471 ocp_reg_write(tp, OCP_EEE_CFG, data); 3472 } 3473 3474 data = ocp_reg_read(tp, OCP_POWER_CFG); 3475 data |= EEE_CLKDIV_EN; 3476 ocp_reg_write(tp, OCP_POWER_CFG, data); 3477 3478 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3479 data |= EN_10M_BGOFF; 3480 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3481 data = ocp_reg_read(tp, OCP_POWER_CFG); 3482 data |= EN_10M_PLLOFF; 3483 ocp_reg_write(tp, OCP_POWER_CFG, data); 3484 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3485 3486 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3487 ocp_data |= PFM_PWM_SWITCH; 3488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3489 3490 /* Enable LPF corner auto tune */ 3491 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3492 3493 /* Adjust 10M Amplitude */ 3494 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3495 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3496 3497 r8153_eee_en(tp, true); 3498 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3499 3500 r8153_aldps_en(tp, true); 3501 r8152b_enable_fc(tp); 3502 3503 switch (tp->version) { 3504 case RTL_VER_03: 3505 case RTL_VER_04: 3506 break; 3507 case RTL_VER_05: 3508 case RTL_VER_06: 3509 default: 3510 r8153_u2p3en(tp, true); 3511 break; 3512 } 3513 3514 set_bit(PHY_RESET, &tp->flags); 3515 } 3516 3517 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3518 { 3519 u32 ocp_data; 3520 3521 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3522 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3523 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3524 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3525 3526 return ocp_data; 3527 } 3528 3529 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3530 { 3531 u32 ocp_data, ups_flags = 0; 3532 u16 data; 3533 3534 /* disable ALDPS before updating the PHY parameters */ 3535 r8153b_aldps_en(tp, false); 3536 3537 /* disable EEE before updating the PHY parameters */ 3538 r8153b_eee_en(tp, false); 3539 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3540 3541 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3542 3543 data = sram_read(tp, SRAM_GREEN_CFG); 3544 data |= R_TUNE_EN; 3545 sram_write(tp, SRAM_GREEN_CFG, data); 3546 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3547 data |= PGA_RETURN_EN; 3548 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3549 3550 /* ADC Bias Calibration: 3551 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3552 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3553 * ADC ioffset. 3554 */ 3555 ocp_data = r8152_efuse_read(tp, 0x7d); 3556 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3557 if (data != 0xffff) 3558 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3559 3560 /* ups mode tx-link-pulse timing adjustment: 3561 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3562 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3563 */ 3564 ocp_data = ocp_reg_read(tp, 0xc426); 3565 ocp_data &= 0x3fff; 3566 if (ocp_data) { 3567 u32 swr_cnt_1ms_ini; 3568 3569 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3570 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3571 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3572 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3573 } 3574 3575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3576 ocp_data |= PFM_PWM_SWITCH; 3577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3578 3579 /* Advnace EEE */ 3580 if (!r8153_patch_request(tp, true)) { 3581 data = ocp_reg_read(tp, OCP_POWER_CFG); 3582 data |= EEE_CLKDIV_EN; 3583 ocp_reg_write(tp, OCP_POWER_CFG, data); 3584 3585 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3586 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3587 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3588 3589 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3590 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3591 3592 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3593 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3594 UPS_FLAGS_EEE_PLLOFF_GIGA; 3595 3596 r8153_patch_request(tp, false); 3597 } 3598 3599 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3600 3601 r8153b_eee_en(tp, true); 3602 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3603 3604 r8153b_aldps_en(tp, true); 3605 r8153b_enable_fc(tp); 3606 r8153_u2p3en(tp, true); 3607 3608 set_bit(PHY_RESET, &tp->flags); 3609 } 3610 3611 static void r8153_first_init(struct r8152 *tp) 3612 { 3613 u32 ocp_data; 3614 int i; 3615 3616 r8153_mac_clk_spd(tp, false); 3617 rxdy_gated_en(tp, true); 3618 r8153_teredo_off(tp); 3619 3620 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3621 ocp_data &= ~RCR_ACPT_ALL; 3622 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3623 3624 rtl8152_nic_reset(tp); 3625 rtl_reset_bmu(tp); 3626 3627 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3628 ocp_data &= ~NOW_IS_OOB; 3629 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3630 3631 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3632 ocp_data &= ~MCU_BORW_EN; 3633 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3634 3635 for (i = 0; i < 1000; i++) { 3636 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3637 if (ocp_data & LINK_LIST_READY) 3638 break; 3639 usleep_range(1000, 2000); 3640 } 3641 3642 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3643 ocp_data |= RE_INIT_LL; 3644 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3645 3646 for (i = 0; i < 1000; i++) { 3647 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3648 if (ocp_data & LINK_LIST_READY) 3649 break; 3650 usleep_range(1000, 2000); 3651 } 3652 3653 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3654 3655 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3657 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3658 3659 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3660 ocp_data |= TCR0_AUTO_FIFO; 3661 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3662 3663 rtl8152_nic_reset(tp); 3664 3665 /* rx share fifo credit full threshold */ 3666 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3667 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3668 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3669 /* TX share fifo free credit full threshold */ 3670 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3671 } 3672 3673 static void r8153_enter_oob(struct r8152 *tp) 3674 { 3675 u32 ocp_data; 3676 int i; 3677 3678 r8153_mac_clk_spd(tp, true); 3679 3680 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3681 ocp_data &= ~NOW_IS_OOB; 3682 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3683 3684 rtl_disable(tp); 3685 rtl_reset_bmu(tp); 3686 3687 for (i = 0; i < 1000; i++) { 3688 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3689 if (ocp_data & LINK_LIST_READY) 3690 break; 3691 usleep_range(1000, 2000); 3692 } 3693 3694 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3695 ocp_data |= RE_INIT_LL; 3696 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3697 3698 for (i = 0; i < 1000; i++) { 3699 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3700 if (ocp_data & LINK_LIST_READY) 3701 break; 3702 usleep_range(1000, 2000); 3703 } 3704 3705 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3706 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3707 3708 switch (tp->version) { 3709 case RTL_VER_03: 3710 case RTL_VER_04: 3711 case RTL_VER_05: 3712 case RTL_VER_06: 3713 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3714 ocp_data &= ~TEREDO_WAKE_MASK; 3715 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3716 break; 3717 3718 case RTL_VER_08: 3719 case RTL_VER_09: 3720 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3721 * type. Set it to zero. bits[7:0] are the W1C bits about 3722 * the events. Set them to all 1 to clear them. 3723 */ 3724 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3725 break; 3726 3727 default: 3728 break; 3729 } 3730 3731 rtl_rx_vlan_en(tp, true); 3732 3733 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3734 ocp_data |= ALDPS_PROXY_MODE; 3735 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3736 3737 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3738 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3739 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3740 3741 rxdy_gated_en(tp, false); 3742 3743 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3744 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3745 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3746 } 3747 3748 static void rtl8153_disable(struct r8152 *tp) 3749 { 3750 r8153_aldps_en(tp, false); 3751 rtl_disable(tp); 3752 rtl_reset_bmu(tp); 3753 r8153_aldps_en(tp, true); 3754 } 3755 3756 static void rtl8153b_disable(struct r8152 *tp) 3757 { 3758 r8153b_aldps_en(tp, false); 3759 rtl_disable(tp); 3760 rtl_reset_bmu(tp); 3761 r8153b_aldps_en(tp, true); 3762 } 3763 3764 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3765 { 3766 u16 bmcr, anar, gbcr; 3767 enum spd_duplex speed_duplex; 3768 int ret = 0; 3769 3770 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3771 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3772 ADVERTISE_100HALF | ADVERTISE_100FULL); 3773 if (tp->mii.supports_gmii) { 3774 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3775 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3776 } else { 3777 gbcr = 0; 3778 } 3779 3780 if (autoneg == AUTONEG_DISABLE) { 3781 if (speed == SPEED_10) { 3782 bmcr = 0; 3783 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3784 speed_duplex = FORCE_10M_HALF; 3785 } else if (speed == SPEED_100) { 3786 bmcr = BMCR_SPEED100; 3787 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3788 speed_duplex = FORCE_100M_HALF; 3789 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3790 bmcr = BMCR_SPEED1000; 3791 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3792 speed_duplex = NWAY_1000M_FULL; 3793 } else { 3794 ret = -EINVAL; 3795 goto out; 3796 } 3797 3798 if (duplex == DUPLEX_FULL) { 3799 bmcr |= BMCR_FULLDPLX; 3800 if (speed != SPEED_1000) 3801 speed_duplex++; 3802 } 3803 } else { 3804 if (speed == SPEED_10) { 3805 if (duplex == DUPLEX_FULL) { 3806 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3807 speed_duplex = NWAY_10M_FULL; 3808 } else { 3809 anar |= ADVERTISE_10HALF; 3810 speed_duplex = NWAY_10M_HALF; 3811 } 3812 } else if (speed == SPEED_100) { 3813 if (duplex == DUPLEX_FULL) { 3814 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3815 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3816 speed_duplex = NWAY_100M_FULL; 3817 } else { 3818 anar |= ADVERTISE_10HALF; 3819 anar |= ADVERTISE_100HALF; 3820 speed_duplex = NWAY_100M_HALF; 3821 } 3822 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3823 if (duplex == DUPLEX_FULL) { 3824 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3825 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3826 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3827 } else { 3828 anar |= ADVERTISE_10HALF; 3829 anar |= ADVERTISE_100HALF; 3830 gbcr |= ADVERTISE_1000HALF; 3831 } 3832 speed_duplex = NWAY_1000M_FULL; 3833 } else { 3834 ret = -EINVAL; 3835 goto out; 3836 } 3837 3838 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3839 } 3840 3841 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3842 bmcr |= BMCR_RESET; 3843 3844 if (tp->mii.supports_gmii) 3845 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3846 3847 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3848 r8152_mdio_write(tp, MII_BMCR, bmcr); 3849 3850 switch (tp->version) { 3851 case RTL_VER_08: 3852 case RTL_VER_09: 3853 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3854 UPS_FLAGS_SPEED_MASK); 3855 break; 3856 3857 default: 3858 break; 3859 } 3860 3861 if (bmcr & BMCR_RESET) { 3862 int i; 3863 3864 for (i = 0; i < 50; i++) { 3865 msleep(20); 3866 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3867 break; 3868 } 3869 } 3870 3871 out: 3872 return ret; 3873 } 3874 3875 static void rtl8152_up(struct r8152 *tp) 3876 { 3877 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3878 return; 3879 3880 r8152_aldps_en(tp, false); 3881 r8152b_exit_oob(tp); 3882 r8152_aldps_en(tp, true); 3883 } 3884 3885 static void rtl8152_down(struct r8152 *tp) 3886 { 3887 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3888 rtl_drop_queued_tx(tp); 3889 return; 3890 } 3891 3892 r8152_power_cut_en(tp, false); 3893 r8152_aldps_en(tp, false); 3894 r8152b_enter_oob(tp); 3895 r8152_aldps_en(tp, true); 3896 } 3897 3898 static void rtl8153_up(struct r8152 *tp) 3899 { 3900 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3901 return; 3902 3903 r8153_u1u2en(tp, false); 3904 r8153_u2p3en(tp, false); 3905 r8153_aldps_en(tp, false); 3906 r8153_first_init(tp); 3907 r8153_aldps_en(tp, true); 3908 3909 switch (tp->version) { 3910 case RTL_VER_03: 3911 case RTL_VER_04: 3912 break; 3913 case RTL_VER_05: 3914 case RTL_VER_06: 3915 default: 3916 r8153_u2p3en(tp, true); 3917 break; 3918 } 3919 3920 r8153_u1u2en(tp, true); 3921 } 3922 3923 static void rtl8153_down(struct r8152 *tp) 3924 { 3925 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3926 rtl_drop_queued_tx(tp); 3927 return; 3928 } 3929 3930 r8153_u1u2en(tp, false); 3931 r8153_u2p3en(tp, false); 3932 r8153_power_cut_en(tp, false); 3933 r8153_aldps_en(tp, false); 3934 r8153_enter_oob(tp); 3935 r8153_aldps_en(tp, true); 3936 } 3937 3938 static void rtl8153b_up(struct r8152 *tp) 3939 { 3940 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3941 return; 3942 3943 r8153b_u1u2en(tp, false); 3944 r8153_u2p3en(tp, false); 3945 r8153b_aldps_en(tp, false); 3946 3947 r8153_first_init(tp); 3948 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3949 3950 r8153b_aldps_en(tp, true); 3951 r8153_u2p3en(tp, true); 3952 r8153b_u1u2en(tp, true); 3953 } 3954 3955 static void rtl8153b_down(struct r8152 *tp) 3956 { 3957 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3958 rtl_drop_queued_tx(tp); 3959 return; 3960 } 3961 3962 r8153b_u1u2en(tp, false); 3963 r8153_u2p3en(tp, false); 3964 r8153b_power_cut_en(tp, false); 3965 r8153b_aldps_en(tp, false); 3966 r8153_enter_oob(tp); 3967 r8153b_aldps_en(tp, true); 3968 } 3969 3970 static bool rtl8152_in_nway(struct r8152 *tp) 3971 { 3972 u16 nway_state; 3973 3974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3975 tp->ocp_base = 0x2000; 3976 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3977 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3978 3979 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3980 if (nway_state & 0xc000) 3981 return false; 3982 else 3983 return true; 3984 } 3985 3986 static bool rtl8153_in_nway(struct r8152 *tp) 3987 { 3988 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3989 3990 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3991 return false; 3992 else 3993 return true; 3994 } 3995 3996 static void set_carrier(struct r8152 *tp) 3997 { 3998 struct net_device *netdev = tp->netdev; 3999 struct napi_struct *napi = &tp->napi; 4000 u8 speed; 4001 4002 speed = rtl8152_get_speed(tp); 4003 4004 if (speed & LINK_STATUS) { 4005 if (!netif_carrier_ok(netdev)) { 4006 tp->rtl_ops.enable(tp); 4007 netif_stop_queue(netdev); 4008 napi_disable(napi); 4009 netif_carrier_on(netdev); 4010 rtl_start_rx(tp); 4011 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 4012 _rtl8152_set_rx_mode(netdev); 4013 napi_enable(&tp->napi); 4014 netif_wake_queue(netdev); 4015 netif_info(tp, link, netdev, "carrier on\n"); 4016 } else if (netif_queue_stopped(netdev) && 4017 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 4018 netif_wake_queue(netdev); 4019 } 4020 } else { 4021 if (netif_carrier_ok(netdev)) { 4022 netif_carrier_off(netdev); 4023 napi_disable(napi); 4024 tp->rtl_ops.disable(tp); 4025 napi_enable(napi); 4026 netif_info(tp, link, netdev, "carrier off\n"); 4027 } 4028 } 4029 } 4030 4031 static void rtl_work_func_t(struct work_struct *work) 4032 { 4033 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 4034 4035 /* If the device is unplugged or !netif_running(), the workqueue 4036 * doesn't need to wake the device, and could return directly. 4037 */ 4038 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 4039 return; 4040 4041 if (usb_autopm_get_interface(tp->intf) < 0) 4042 return; 4043 4044 if (!test_bit(WORK_ENABLE, &tp->flags)) 4045 goto out1; 4046 4047 if (!mutex_trylock(&tp->control)) { 4048 schedule_delayed_work(&tp->schedule, 0); 4049 goto out1; 4050 } 4051 4052 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 4053 set_carrier(tp); 4054 4055 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 4056 _rtl8152_set_rx_mode(tp->netdev); 4057 4058 /* don't schedule napi before linking */ 4059 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 4060 netif_carrier_ok(tp->netdev)) 4061 napi_schedule(&tp->napi); 4062 4063 mutex_unlock(&tp->control); 4064 4065 out1: 4066 usb_autopm_put_interface(tp->intf); 4067 } 4068 4069 static void rtl_hw_phy_work_func_t(struct work_struct *work) 4070 { 4071 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 4072 4073 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4074 return; 4075 4076 if (usb_autopm_get_interface(tp->intf) < 0) 4077 return; 4078 4079 mutex_lock(&tp->control); 4080 4081 tp->rtl_ops.hw_phy_cfg(tp); 4082 4083 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 4084 4085 mutex_unlock(&tp->control); 4086 4087 usb_autopm_put_interface(tp->intf); 4088 } 4089 4090 #ifdef CONFIG_PM_SLEEP 4091 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 4092 void *data) 4093 { 4094 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 4095 4096 switch (action) { 4097 case PM_HIBERNATION_PREPARE: 4098 case PM_SUSPEND_PREPARE: 4099 usb_autopm_get_interface(tp->intf); 4100 break; 4101 4102 case PM_POST_HIBERNATION: 4103 case PM_POST_SUSPEND: 4104 usb_autopm_put_interface(tp->intf); 4105 break; 4106 4107 case PM_POST_RESTORE: 4108 case PM_RESTORE_PREPARE: 4109 default: 4110 break; 4111 } 4112 4113 return NOTIFY_DONE; 4114 } 4115 #endif 4116 4117 static int rtl8152_open(struct net_device *netdev) 4118 { 4119 struct r8152 *tp = netdev_priv(netdev); 4120 int res = 0; 4121 4122 res = alloc_all_mem(tp); 4123 if (res) 4124 goto out; 4125 4126 res = usb_autopm_get_interface(tp->intf); 4127 if (res < 0) 4128 goto out_free; 4129 4130 mutex_lock(&tp->control); 4131 4132 tp->rtl_ops.up(tp); 4133 4134 netif_carrier_off(netdev); 4135 netif_start_queue(netdev); 4136 set_bit(WORK_ENABLE, &tp->flags); 4137 4138 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4139 if (res) { 4140 if (res == -ENODEV) 4141 netif_device_detach(tp->netdev); 4142 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 4143 res); 4144 goto out_unlock; 4145 } 4146 napi_enable(&tp->napi); 4147 4148 mutex_unlock(&tp->control); 4149 4150 usb_autopm_put_interface(tp->intf); 4151 #ifdef CONFIG_PM_SLEEP 4152 tp->pm_notifier.notifier_call = rtl_notifier; 4153 register_pm_notifier(&tp->pm_notifier); 4154 #endif 4155 return 0; 4156 4157 out_unlock: 4158 mutex_unlock(&tp->control); 4159 usb_autopm_put_interface(tp->intf); 4160 out_free: 4161 free_all_mem(tp); 4162 out: 4163 return res; 4164 } 4165 4166 static int rtl8152_close(struct net_device *netdev) 4167 { 4168 struct r8152 *tp = netdev_priv(netdev); 4169 int res = 0; 4170 4171 #ifdef CONFIG_PM_SLEEP 4172 unregister_pm_notifier(&tp->pm_notifier); 4173 #endif 4174 if (!test_bit(RTL8152_UNPLUG, &tp->flags)) 4175 napi_disable(&tp->napi); 4176 clear_bit(WORK_ENABLE, &tp->flags); 4177 usb_kill_urb(tp->intr_urb); 4178 cancel_delayed_work_sync(&tp->schedule); 4179 netif_stop_queue(netdev); 4180 4181 res = usb_autopm_get_interface(tp->intf); 4182 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 4183 rtl_drop_queued_tx(tp); 4184 rtl_stop_rx(tp); 4185 } else { 4186 mutex_lock(&tp->control); 4187 4188 tp->rtl_ops.down(tp); 4189 4190 mutex_unlock(&tp->control); 4191 4192 usb_autopm_put_interface(tp->intf); 4193 } 4194 4195 free_all_mem(tp); 4196 4197 return res; 4198 } 4199 4200 static void rtl_tally_reset(struct r8152 *tp) 4201 { 4202 u32 ocp_data; 4203 4204 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4205 ocp_data |= TALLY_RESET; 4206 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4207 } 4208 4209 static void r8152b_init(struct r8152 *tp) 4210 { 4211 u32 ocp_data; 4212 u16 data; 4213 4214 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4215 return; 4216 4217 data = r8152_mdio_read(tp, MII_BMCR); 4218 if (data & BMCR_PDOWN) { 4219 data &= ~BMCR_PDOWN; 4220 r8152_mdio_write(tp, MII_BMCR, data); 4221 } 4222 4223 r8152_aldps_en(tp, false); 4224 4225 if (tp->version == RTL_VER_01) { 4226 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4227 ocp_data &= ~LED_MODE_MASK; 4228 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4229 } 4230 4231 r8152_power_cut_en(tp, false); 4232 4233 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4234 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4235 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4236 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4237 ocp_data &= ~MCU_CLK_RATIO_MASK; 4238 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4239 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4240 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4241 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4242 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4243 4244 rtl_tally_reset(tp); 4245 4246 /* enable rx aggregation */ 4247 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4248 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4249 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4250 } 4251 4252 static void r8153_init(struct r8152 *tp) 4253 { 4254 u32 ocp_data; 4255 u16 data; 4256 int i; 4257 4258 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4259 return; 4260 4261 r8153_u1u2en(tp, false); 4262 4263 for (i = 0; i < 500; i++) { 4264 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4265 AUTOLOAD_DONE) 4266 break; 4267 msleep(20); 4268 } 4269 4270 data = r8153_phy_status(tp, 0); 4271 4272 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4273 tp->version == RTL_VER_05) 4274 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4275 4276 data = r8152_mdio_read(tp, MII_BMCR); 4277 if (data & BMCR_PDOWN) { 4278 data &= ~BMCR_PDOWN; 4279 r8152_mdio_write(tp, MII_BMCR, data); 4280 } 4281 4282 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4283 4284 r8153_u2p3en(tp, false); 4285 4286 if (tp->version == RTL_VER_04) { 4287 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4288 ocp_data &= ~pwd_dn_scale_mask; 4289 ocp_data |= pwd_dn_scale(96); 4290 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4291 4292 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4293 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4294 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4295 } else if (tp->version == RTL_VER_05) { 4296 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4297 ocp_data &= ~ECM_ALDPS; 4298 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4299 4300 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4301 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4302 ocp_data &= ~DYNAMIC_BURST; 4303 else 4304 ocp_data |= DYNAMIC_BURST; 4305 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4306 } else if (tp->version == RTL_VER_06) { 4307 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4308 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4309 ocp_data &= ~DYNAMIC_BURST; 4310 else 4311 ocp_data |= DYNAMIC_BURST; 4312 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4313 } 4314 4315 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4316 ocp_data |= EP4_FULL_FC; 4317 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4318 4319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4320 ocp_data &= ~TIMER11_EN; 4321 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4322 4323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4324 ocp_data &= ~LED_MODE_MASK; 4325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4326 4327 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4328 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4329 ocp_data |= LPM_TIMER_500MS; 4330 else 4331 ocp_data |= LPM_TIMER_500US; 4332 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4333 4334 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4335 ocp_data &= ~SEN_VAL_MASK; 4336 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4337 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4338 4339 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4340 4341 r8153_power_cut_en(tp, false); 4342 r8153_u1u2en(tp, true); 4343 r8153_mac_clk_spd(tp, false); 4344 usb_enable_lpm(tp->udev); 4345 4346 /* rx aggregation */ 4347 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4348 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4349 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4350 ocp_data |= RX_AGG_DISABLE; 4351 4352 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4353 4354 rtl_tally_reset(tp); 4355 4356 switch (tp->udev->speed) { 4357 case USB_SPEED_SUPER: 4358 case USB_SPEED_SUPER_PLUS: 4359 tp->coalesce = COALESCE_SUPER; 4360 break; 4361 case USB_SPEED_HIGH: 4362 tp->coalesce = COALESCE_HIGH; 4363 break; 4364 default: 4365 tp->coalesce = COALESCE_SLOW; 4366 break; 4367 } 4368 } 4369 4370 static void r8153b_init(struct r8152 *tp) 4371 { 4372 u32 ocp_data; 4373 u16 data; 4374 int i; 4375 4376 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4377 return; 4378 4379 r8153b_u1u2en(tp, false); 4380 4381 for (i = 0; i < 500; i++) { 4382 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4383 AUTOLOAD_DONE) 4384 break; 4385 msleep(20); 4386 } 4387 4388 data = r8153_phy_status(tp, 0); 4389 4390 data = r8152_mdio_read(tp, MII_BMCR); 4391 if (data & BMCR_PDOWN) { 4392 data &= ~BMCR_PDOWN; 4393 r8152_mdio_write(tp, MII_BMCR, data); 4394 } 4395 4396 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4397 4398 r8153_u2p3en(tp, false); 4399 4400 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4401 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4402 4403 /* U1/U2/L1 idle timer. 500 us */ 4404 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4405 4406 r8153b_power_cut_en(tp, false); 4407 r8153b_ups_en(tp, false); 4408 r8153_queue_wake(tp, false); 4409 rtl_runtime_suspend_enable(tp, false); 4410 r8153b_u1u2en(tp, true); 4411 usb_enable_lpm(tp->udev); 4412 4413 /* MAC clock speed down */ 4414 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4415 ocp_data |= MAC_CLK_SPDWN_EN; 4416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4417 4418 set_bit(GREEN_ETHERNET, &tp->flags); 4419 4420 /* rx aggregation */ 4421 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4422 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4423 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4424 4425 rtl_tally_reset(tp); 4426 4427 tp->coalesce = 15000; /* 15 us */ 4428 } 4429 4430 static int rtl8152_pre_reset(struct usb_interface *intf) 4431 { 4432 struct r8152 *tp = usb_get_intfdata(intf); 4433 struct net_device *netdev; 4434 4435 if (!tp) 4436 return 0; 4437 4438 netdev = tp->netdev; 4439 if (!netif_running(netdev)) 4440 return 0; 4441 4442 netif_stop_queue(netdev); 4443 napi_disable(&tp->napi); 4444 clear_bit(WORK_ENABLE, &tp->flags); 4445 usb_kill_urb(tp->intr_urb); 4446 cancel_delayed_work_sync(&tp->schedule); 4447 if (netif_carrier_ok(netdev)) { 4448 mutex_lock(&tp->control); 4449 tp->rtl_ops.disable(tp); 4450 mutex_unlock(&tp->control); 4451 } 4452 4453 return 0; 4454 } 4455 4456 static int rtl8152_post_reset(struct usb_interface *intf) 4457 { 4458 struct r8152 *tp = usb_get_intfdata(intf); 4459 struct net_device *netdev; 4460 struct sockaddr sa; 4461 4462 if (!tp) 4463 return 0; 4464 4465 /* reset the MAC adddress in case of policy change */ 4466 if (determine_ethernet_addr(tp, &sa) >= 0) { 4467 rtnl_lock(); 4468 dev_set_mac_address (tp->netdev, &sa, NULL); 4469 rtnl_unlock(); 4470 } 4471 4472 netdev = tp->netdev; 4473 if (!netif_running(netdev)) 4474 return 0; 4475 4476 set_bit(WORK_ENABLE, &tp->flags); 4477 if (netif_carrier_ok(netdev)) { 4478 mutex_lock(&tp->control); 4479 tp->rtl_ops.enable(tp); 4480 rtl_start_rx(tp); 4481 _rtl8152_set_rx_mode(netdev); 4482 mutex_unlock(&tp->control); 4483 } 4484 4485 napi_enable(&tp->napi); 4486 netif_wake_queue(netdev); 4487 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4488 4489 if (!list_empty(&tp->rx_done)) 4490 napi_schedule(&tp->napi); 4491 4492 return 0; 4493 } 4494 4495 static bool delay_autosuspend(struct r8152 *tp) 4496 { 4497 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4498 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4499 4500 /* This means a linking change occurs and the driver doesn't detect it, 4501 * yet. If the driver has disabled tx/rx and hw is linking on, the 4502 * device wouldn't wake up by receiving any packet. 4503 */ 4504 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4505 return true; 4506 4507 /* If the linking down is occurred by nway, the device may miss the 4508 * linking change event. And it wouldn't wake when linking on. 4509 */ 4510 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4511 return true; 4512 else if (!skb_queue_empty(&tp->tx_queue)) 4513 return true; 4514 else 4515 return false; 4516 } 4517 4518 static int rtl8152_runtime_resume(struct r8152 *tp) 4519 { 4520 struct net_device *netdev = tp->netdev; 4521 4522 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4523 struct napi_struct *napi = &tp->napi; 4524 4525 tp->rtl_ops.autosuspend_en(tp, false); 4526 napi_disable(napi); 4527 set_bit(WORK_ENABLE, &tp->flags); 4528 4529 if (netif_carrier_ok(netdev)) { 4530 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4531 rtl_start_rx(tp); 4532 } else { 4533 netif_carrier_off(netdev); 4534 tp->rtl_ops.disable(tp); 4535 netif_info(tp, link, netdev, "linking down\n"); 4536 } 4537 } 4538 4539 napi_enable(napi); 4540 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4541 smp_mb__after_atomic(); 4542 4543 if (!list_empty(&tp->rx_done)) 4544 napi_schedule(&tp->napi); 4545 4546 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4547 } else { 4548 if (netdev->flags & IFF_UP) 4549 tp->rtl_ops.autosuspend_en(tp, false); 4550 4551 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4552 } 4553 4554 return 0; 4555 } 4556 4557 static int rtl8152_system_resume(struct r8152 *tp) 4558 { 4559 struct net_device *netdev = tp->netdev; 4560 4561 netif_device_attach(netdev); 4562 4563 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4564 tp->rtl_ops.up(tp); 4565 netif_carrier_off(netdev); 4566 set_bit(WORK_ENABLE, &tp->flags); 4567 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4568 } 4569 4570 return 0; 4571 } 4572 4573 static int rtl8152_runtime_suspend(struct r8152 *tp) 4574 { 4575 struct net_device *netdev = tp->netdev; 4576 int ret = 0; 4577 4578 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4579 smp_mb__after_atomic(); 4580 4581 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4582 u32 rcr = 0; 4583 4584 if (netif_carrier_ok(netdev)) { 4585 u32 ocp_data; 4586 4587 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4588 ocp_data = rcr & ~RCR_ACPT_ALL; 4589 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4590 rxdy_gated_en(tp, true); 4591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4592 PLA_OOB_CTRL); 4593 if (!(ocp_data & RXFIFO_EMPTY)) { 4594 rxdy_gated_en(tp, false); 4595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4596 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4597 smp_mb__after_atomic(); 4598 ret = -EBUSY; 4599 goto out1; 4600 } 4601 } 4602 4603 clear_bit(WORK_ENABLE, &tp->flags); 4604 usb_kill_urb(tp->intr_urb); 4605 4606 tp->rtl_ops.autosuspend_en(tp, true); 4607 4608 if (netif_carrier_ok(netdev)) { 4609 struct napi_struct *napi = &tp->napi; 4610 4611 napi_disable(napi); 4612 rtl_stop_rx(tp); 4613 rxdy_gated_en(tp, false); 4614 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4615 napi_enable(napi); 4616 } 4617 4618 if (delay_autosuspend(tp)) { 4619 rtl8152_runtime_resume(tp); 4620 ret = -EBUSY; 4621 } 4622 } 4623 4624 out1: 4625 return ret; 4626 } 4627 4628 static int rtl8152_system_suspend(struct r8152 *tp) 4629 { 4630 struct net_device *netdev = tp->netdev; 4631 4632 netif_device_detach(netdev); 4633 4634 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4635 struct napi_struct *napi = &tp->napi; 4636 4637 clear_bit(WORK_ENABLE, &tp->flags); 4638 usb_kill_urb(tp->intr_urb); 4639 napi_disable(napi); 4640 cancel_delayed_work_sync(&tp->schedule); 4641 tp->rtl_ops.down(tp); 4642 napi_enable(napi); 4643 } 4644 4645 return 0; 4646 } 4647 4648 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4649 { 4650 struct r8152 *tp = usb_get_intfdata(intf); 4651 int ret; 4652 4653 mutex_lock(&tp->control); 4654 4655 if (PMSG_IS_AUTO(message)) 4656 ret = rtl8152_runtime_suspend(tp); 4657 else 4658 ret = rtl8152_system_suspend(tp); 4659 4660 mutex_unlock(&tp->control); 4661 4662 return ret; 4663 } 4664 4665 static int rtl8152_resume(struct usb_interface *intf) 4666 { 4667 struct r8152 *tp = usb_get_intfdata(intf); 4668 int ret; 4669 4670 mutex_lock(&tp->control); 4671 4672 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4673 ret = rtl8152_runtime_resume(tp); 4674 else 4675 ret = rtl8152_system_resume(tp); 4676 4677 mutex_unlock(&tp->control); 4678 4679 return ret; 4680 } 4681 4682 static int rtl8152_reset_resume(struct usb_interface *intf) 4683 { 4684 struct r8152 *tp = usb_get_intfdata(intf); 4685 4686 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4687 mutex_lock(&tp->control); 4688 tp->rtl_ops.init(tp); 4689 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4690 mutex_unlock(&tp->control); 4691 return rtl8152_resume(intf); 4692 } 4693 4694 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4695 { 4696 struct r8152 *tp = netdev_priv(dev); 4697 4698 if (usb_autopm_get_interface(tp->intf) < 0) 4699 return; 4700 4701 if (!rtl_can_wakeup(tp)) { 4702 wol->supported = 0; 4703 wol->wolopts = 0; 4704 } else { 4705 mutex_lock(&tp->control); 4706 wol->supported = WAKE_ANY; 4707 wol->wolopts = __rtl_get_wol(tp); 4708 mutex_unlock(&tp->control); 4709 } 4710 4711 usb_autopm_put_interface(tp->intf); 4712 } 4713 4714 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4715 { 4716 struct r8152 *tp = netdev_priv(dev); 4717 int ret; 4718 4719 if (!rtl_can_wakeup(tp)) 4720 return -EOPNOTSUPP; 4721 4722 if (wol->wolopts & ~WAKE_ANY) 4723 return -EINVAL; 4724 4725 ret = usb_autopm_get_interface(tp->intf); 4726 if (ret < 0) 4727 goto out_set_wol; 4728 4729 mutex_lock(&tp->control); 4730 4731 __rtl_set_wol(tp, wol->wolopts); 4732 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4733 4734 mutex_unlock(&tp->control); 4735 4736 usb_autopm_put_interface(tp->intf); 4737 4738 out_set_wol: 4739 return ret; 4740 } 4741 4742 static u32 rtl8152_get_msglevel(struct net_device *dev) 4743 { 4744 struct r8152 *tp = netdev_priv(dev); 4745 4746 return tp->msg_enable; 4747 } 4748 4749 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4750 { 4751 struct r8152 *tp = netdev_priv(dev); 4752 4753 tp->msg_enable = value; 4754 } 4755 4756 static void rtl8152_get_drvinfo(struct net_device *netdev, 4757 struct ethtool_drvinfo *info) 4758 { 4759 struct r8152 *tp = netdev_priv(netdev); 4760 4761 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4762 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4763 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4764 } 4765 4766 static 4767 int rtl8152_get_link_ksettings(struct net_device *netdev, 4768 struct ethtool_link_ksettings *cmd) 4769 { 4770 struct r8152 *tp = netdev_priv(netdev); 4771 int ret; 4772 4773 if (!tp->mii.mdio_read) 4774 return -EOPNOTSUPP; 4775 4776 ret = usb_autopm_get_interface(tp->intf); 4777 if (ret < 0) 4778 goto out; 4779 4780 mutex_lock(&tp->control); 4781 4782 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4783 4784 mutex_unlock(&tp->control); 4785 4786 usb_autopm_put_interface(tp->intf); 4787 4788 out: 4789 return ret; 4790 } 4791 4792 static int rtl8152_set_link_ksettings(struct net_device *dev, 4793 const struct ethtool_link_ksettings *cmd) 4794 { 4795 struct r8152 *tp = netdev_priv(dev); 4796 int ret; 4797 4798 ret = usb_autopm_get_interface(tp->intf); 4799 if (ret < 0) 4800 goto out; 4801 4802 mutex_lock(&tp->control); 4803 4804 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4805 cmd->base.duplex); 4806 if (!ret) { 4807 tp->autoneg = cmd->base.autoneg; 4808 tp->speed = cmd->base.speed; 4809 tp->duplex = cmd->base.duplex; 4810 } 4811 4812 mutex_unlock(&tp->control); 4813 4814 usb_autopm_put_interface(tp->intf); 4815 4816 out: 4817 return ret; 4818 } 4819 4820 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4821 "tx_packets", 4822 "rx_packets", 4823 "tx_errors", 4824 "rx_errors", 4825 "rx_missed", 4826 "align_errors", 4827 "tx_single_collisions", 4828 "tx_multi_collisions", 4829 "rx_unicast", 4830 "rx_broadcast", 4831 "rx_multicast", 4832 "tx_aborted", 4833 "tx_underrun", 4834 }; 4835 4836 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4837 { 4838 switch (sset) { 4839 case ETH_SS_STATS: 4840 return ARRAY_SIZE(rtl8152_gstrings); 4841 default: 4842 return -EOPNOTSUPP; 4843 } 4844 } 4845 4846 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4847 struct ethtool_stats *stats, u64 *data) 4848 { 4849 struct r8152 *tp = netdev_priv(dev); 4850 struct tally_counter tally; 4851 4852 if (usb_autopm_get_interface(tp->intf) < 0) 4853 return; 4854 4855 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4856 4857 usb_autopm_put_interface(tp->intf); 4858 4859 data[0] = le64_to_cpu(tally.tx_packets); 4860 data[1] = le64_to_cpu(tally.rx_packets); 4861 data[2] = le64_to_cpu(tally.tx_errors); 4862 data[3] = le32_to_cpu(tally.rx_errors); 4863 data[4] = le16_to_cpu(tally.rx_missed); 4864 data[5] = le16_to_cpu(tally.align_errors); 4865 data[6] = le32_to_cpu(tally.tx_one_collision); 4866 data[7] = le32_to_cpu(tally.tx_multi_collision); 4867 data[8] = le64_to_cpu(tally.rx_unicast); 4868 data[9] = le64_to_cpu(tally.rx_broadcast); 4869 data[10] = le32_to_cpu(tally.rx_multicast); 4870 data[11] = le16_to_cpu(tally.tx_aborted); 4871 data[12] = le16_to_cpu(tally.tx_underrun); 4872 } 4873 4874 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4875 { 4876 switch (stringset) { 4877 case ETH_SS_STATS: 4878 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4879 break; 4880 } 4881 } 4882 4883 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4884 { 4885 u32 ocp_data, lp, adv, supported = 0; 4886 u16 val; 4887 4888 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4889 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4890 4891 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4892 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4893 4894 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4895 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4896 4897 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4898 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4899 4900 eee->eee_enabled = !!ocp_data; 4901 eee->eee_active = !!(supported & adv & lp); 4902 eee->supported = supported; 4903 eee->advertised = adv; 4904 eee->lp_advertised = lp; 4905 4906 return 0; 4907 } 4908 4909 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4910 { 4911 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4912 4913 r8152_eee_en(tp, eee->eee_enabled); 4914 4915 if (!eee->eee_enabled) 4916 val = 0; 4917 4918 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4919 4920 return 0; 4921 } 4922 4923 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4924 { 4925 u32 ocp_data, lp, adv, supported = 0; 4926 u16 val; 4927 4928 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4929 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4930 4931 val = ocp_reg_read(tp, OCP_EEE_ADV); 4932 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4933 4934 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4935 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4936 4937 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4938 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4939 4940 eee->eee_enabled = !!ocp_data; 4941 eee->eee_active = !!(supported & adv & lp); 4942 eee->supported = supported; 4943 eee->advertised = adv; 4944 eee->lp_advertised = lp; 4945 4946 return 0; 4947 } 4948 4949 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4950 { 4951 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4952 4953 r8153_eee_en(tp, eee->eee_enabled); 4954 4955 if (!eee->eee_enabled) 4956 val = 0; 4957 4958 ocp_reg_write(tp, OCP_EEE_ADV, val); 4959 4960 return 0; 4961 } 4962 4963 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4964 { 4965 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4966 4967 r8153b_eee_en(tp, eee->eee_enabled); 4968 4969 if (!eee->eee_enabled) 4970 val = 0; 4971 4972 ocp_reg_write(tp, OCP_EEE_ADV, val); 4973 4974 return 0; 4975 } 4976 4977 static int 4978 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4979 { 4980 struct r8152 *tp = netdev_priv(net); 4981 int ret; 4982 4983 ret = usb_autopm_get_interface(tp->intf); 4984 if (ret < 0) 4985 goto out; 4986 4987 mutex_lock(&tp->control); 4988 4989 ret = tp->rtl_ops.eee_get(tp, edata); 4990 4991 mutex_unlock(&tp->control); 4992 4993 usb_autopm_put_interface(tp->intf); 4994 4995 out: 4996 return ret; 4997 } 4998 4999 static int 5000 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 5001 { 5002 struct r8152 *tp = netdev_priv(net); 5003 int ret; 5004 5005 ret = usb_autopm_get_interface(tp->intf); 5006 if (ret < 0) 5007 goto out; 5008 5009 mutex_lock(&tp->control); 5010 5011 ret = tp->rtl_ops.eee_set(tp, edata); 5012 if (!ret) 5013 ret = mii_nway_restart(&tp->mii); 5014 5015 mutex_unlock(&tp->control); 5016 5017 usb_autopm_put_interface(tp->intf); 5018 5019 out: 5020 return ret; 5021 } 5022 5023 static int rtl8152_nway_reset(struct net_device *dev) 5024 { 5025 struct r8152 *tp = netdev_priv(dev); 5026 int ret; 5027 5028 ret = usb_autopm_get_interface(tp->intf); 5029 if (ret < 0) 5030 goto out; 5031 5032 mutex_lock(&tp->control); 5033 5034 ret = mii_nway_restart(&tp->mii); 5035 5036 mutex_unlock(&tp->control); 5037 5038 usb_autopm_put_interface(tp->intf); 5039 5040 out: 5041 return ret; 5042 } 5043 5044 static int rtl8152_get_coalesce(struct net_device *netdev, 5045 struct ethtool_coalesce *coalesce) 5046 { 5047 struct r8152 *tp = netdev_priv(netdev); 5048 5049 switch (tp->version) { 5050 case RTL_VER_01: 5051 case RTL_VER_02: 5052 case RTL_VER_07: 5053 return -EOPNOTSUPP; 5054 default: 5055 break; 5056 } 5057 5058 coalesce->rx_coalesce_usecs = tp->coalesce; 5059 5060 return 0; 5061 } 5062 5063 static int rtl8152_set_coalesce(struct net_device *netdev, 5064 struct ethtool_coalesce *coalesce) 5065 { 5066 struct r8152 *tp = netdev_priv(netdev); 5067 int ret; 5068 5069 switch (tp->version) { 5070 case RTL_VER_01: 5071 case RTL_VER_02: 5072 case RTL_VER_07: 5073 return -EOPNOTSUPP; 5074 default: 5075 break; 5076 } 5077 5078 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 5079 return -EINVAL; 5080 5081 ret = usb_autopm_get_interface(tp->intf); 5082 if (ret < 0) 5083 return ret; 5084 5085 mutex_lock(&tp->control); 5086 5087 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 5088 tp->coalesce = coalesce->rx_coalesce_usecs; 5089 5090 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 5091 netif_stop_queue(netdev); 5092 napi_disable(&tp->napi); 5093 tp->rtl_ops.disable(tp); 5094 tp->rtl_ops.enable(tp); 5095 rtl_start_rx(tp); 5096 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 5097 _rtl8152_set_rx_mode(netdev); 5098 napi_enable(&tp->napi); 5099 netif_wake_queue(netdev); 5100 } 5101 } 5102 5103 mutex_unlock(&tp->control); 5104 5105 usb_autopm_put_interface(tp->intf); 5106 5107 return ret; 5108 } 5109 5110 static int rtl8152_get_tunable(struct net_device *netdev, 5111 const struct ethtool_tunable *tunable, void *d) 5112 { 5113 struct r8152 *tp = netdev_priv(netdev); 5114 5115 switch (tunable->id) { 5116 case ETHTOOL_RX_COPYBREAK: 5117 *(u32 *)d = tp->rx_copybreak; 5118 break; 5119 default: 5120 return -EOPNOTSUPP; 5121 } 5122 5123 return 0; 5124 } 5125 5126 static int rtl8152_set_tunable(struct net_device *netdev, 5127 const struct ethtool_tunable *tunable, 5128 const void *d) 5129 { 5130 struct r8152 *tp = netdev_priv(netdev); 5131 u32 val; 5132 5133 switch (tunable->id) { 5134 case ETHTOOL_RX_COPYBREAK: 5135 val = *(u32 *)d; 5136 if (val < ETH_ZLEN) { 5137 netif_err(tp, rx_err, netdev, 5138 "Invalid rx copy break value\n"); 5139 return -EINVAL; 5140 } 5141 5142 if (tp->rx_copybreak != val) { 5143 napi_disable(&tp->napi); 5144 tp->rx_copybreak = val; 5145 napi_enable(&tp->napi); 5146 } 5147 break; 5148 default: 5149 return -EOPNOTSUPP; 5150 } 5151 5152 return 0; 5153 } 5154 5155 static void rtl8152_get_ringparam(struct net_device *netdev, 5156 struct ethtool_ringparam *ring) 5157 { 5158 struct r8152 *tp = netdev_priv(netdev); 5159 5160 ring->rx_max_pending = RTL8152_RX_MAX_PENDING; 5161 ring->rx_pending = tp->rx_pending; 5162 } 5163 5164 static int rtl8152_set_ringparam(struct net_device *netdev, 5165 struct ethtool_ringparam *ring) 5166 { 5167 struct r8152 *tp = netdev_priv(netdev); 5168 5169 if (ring->rx_pending < (RTL8152_MAX_RX * 2)) 5170 return -EINVAL; 5171 5172 if (tp->rx_pending != ring->rx_pending) { 5173 napi_disable(&tp->napi); 5174 tp->rx_pending = ring->rx_pending; 5175 napi_enable(&tp->napi); 5176 } 5177 5178 return 0; 5179 } 5180 5181 static const struct ethtool_ops ops = { 5182 .get_drvinfo = rtl8152_get_drvinfo, 5183 .get_link = ethtool_op_get_link, 5184 .nway_reset = rtl8152_nway_reset, 5185 .get_msglevel = rtl8152_get_msglevel, 5186 .set_msglevel = rtl8152_set_msglevel, 5187 .get_wol = rtl8152_get_wol, 5188 .set_wol = rtl8152_set_wol, 5189 .get_strings = rtl8152_get_strings, 5190 .get_sset_count = rtl8152_get_sset_count, 5191 .get_ethtool_stats = rtl8152_get_ethtool_stats, 5192 .get_coalesce = rtl8152_get_coalesce, 5193 .set_coalesce = rtl8152_set_coalesce, 5194 .get_eee = rtl_ethtool_get_eee, 5195 .set_eee = rtl_ethtool_set_eee, 5196 .get_link_ksettings = rtl8152_get_link_ksettings, 5197 .set_link_ksettings = rtl8152_set_link_ksettings, 5198 .get_tunable = rtl8152_get_tunable, 5199 .set_tunable = rtl8152_set_tunable, 5200 .get_ringparam = rtl8152_get_ringparam, 5201 .set_ringparam = rtl8152_set_ringparam, 5202 }; 5203 5204 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 5205 { 5206 struct r8152 *tp = netdev_priv(netdev); 5207 struct mii_ioctl_data *data = if_mii(rq); 5208 int res; 5209 5210 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5211 return -ENODEV; 5212 5213 res = usb_autopm_get_interface(tp->intf); 5214 if (res < 0) 5215 goto out; 5216 5217 switch (cmd) { 5218 case SIOCGMIIPHY: 5219 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 5220 break; 5221 5222 case SIOCGMIIREG: 5223 mutex_lock(&tp->control); 5224 data->val_out = r8152_mdio_read(tp, data->reg_num); 5225 mutex_unlock(&tp->control); 5226 break; 5227 5228 case SIOCSMIIREG: 5229 if (!capable(CAP_NET_ADMIN)) { 5230 res = -EPERM; 5231 break; 5232 } 5233 mutex_lock(&tp->control); 5234 r8152_mdio_write(tp, data->reg_num, data->val_in); 5235 mutex_unlock(&tp->control); 5236 break; 5237 5238 default: 5239 res = -EOPNOTSUPP; 5240 } 5241 5242 usb_autopm_put_interface(tp->intf); 5243 5244 out: 5245 return res; 5246 } 5247 5248 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 5249 { 5250 struct r8152 *tp = netdev_priv(dev); 5251 int ret; 5252 5253 switch (tp->version) { 5254 case RTL_VER_01: 5255 case RTL_VER_02: 5256 case RTL_VER_07: 5257 dev->mtu = new_mtu; 5258 return 0; 5259 default: 5260 break; 5261 } 5262 5263 ret = usb_autopm_get_interface(tp->intf); 5264 if (ret < 0) 5265 return ret; 5266 5267 mutex_lock(&tp->control); 5268 5269 dev->mtu = new_mtu; 5270 5271 if (netif_running(dev)) { 5272 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5273 5274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5275 5276 if (netif_carrier_ok(dev)) 5277 r8153_set_rx_early_size(tp); 5278 } 5279 5280 mutex_unlock(&tp->control); 5281 5282 usb_autopm_put_interface(tp->intf); 5283 5284 return ret; 5285 } 5286 5287 static const struct net_device_ops rtl8152_netdev_ops = { 5288 .ndo_open = rtl8152_open, 5289 .ndo_stop = rtl8152_close, 5290 .ndo_do_ioctl = rtl8152_ioctl, 5291 .ndo_start_xmit = rtl8152_start_xmit, 5292 .ndo_tx_timeout = rtl8152_tx_timeout, 5293 .ndo_set_features = rtl8152_set_features, 5294 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5295 .ndo_set_mac_address = rtl8152_set_mac_address, 5296 .ndo_change_mtu = rtl8152_change_mtu, 5297 .ndo_validate_addr = eth_validate_addr, 5298 .ndo_features_check = rtl8152_features_check, 5299 }; 5300 5301 static void rtl8152_unload(struct r8152 *tp) 5302 { 5303 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5304 return; 5305 5306 if (tp->version != RTL_VER_01) 5307 r8152_power_cut_en(tp, true); 5308 } 5309 5310 static void rtl8153_unload(struct r8152 *tp) 5311 { 5312 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5313 return; 5314 5315 r8153_power_cut_en(tp, false); 5316 } 5317 5318 static void rtl8153b_unload(struct r8152 *tp) 5319 { 5320 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5321 return; 5322 5323 r8153b_power_cut_en(tp, false); 5324 } 5325 5326 static int rtl_ops_init(struct r8152 *tp) 5327 { 5328 struct rtl_ops *ops = &tp->rtl_ops; 5329 int ret = 0; 5330 5331 switch (tp->version) { 5332 case RTL_VER_01: 5333 case RTL_VER_02: 5334 case RTL_VER_07: 5335 ops->init = r8152b_init; 5336 ops->enable = rtl8152_enable; 5337 ops->disable = rtl8152_disable; 5338 ops->up = rtl8152_up; 5339 ops->down = rtl8152_down; 5340 ops->unload = rtl8152_unload; 5341 ops->eee_get = r8152_get_eee; 5342 ops->eee_set = r8152_set_eee; 5343 ops->in_nway = rtl8152_in_nway; 5344 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5345 ops->autosuspend_en = rtl_runtime_suspend_enable; 5346 tp->rx_buf_sz = 16 * 1024; 5347 break; 5348 5349 case RTL_VER_03: 5350 case RTL_VER_04: 5351 case RTL_VER_05: 5352 case RTL_VER_06: 5353 ops->init = r8153_init; 5354 ops->enable = rtl8153_enable; 5355 ops->disable = rtl8153_disable; 5356 ops->up = rtl8153_up; 5357 ops->down = rtl8153_down; 5358 ops->unload = rtl8153_unload; 5359 ops->eee_get = r8153_get_eee; 5360 ops->eee_set = r8153_set_eee; 5361 ops->in_nway = rtl8153_in_nway; 5362 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5363 ops->autosuspend_en = rtl8153_runtime_enable; 5364 tp->rx_buf_sz = 32 * 1024; 5365 break; 5366 5367 case RTL_VER_08: 5368 case RTL_VER_09: 5369 ops->init = r8153b_init; 5370 ops->enable = rtl8153_enable; 5371 ops->disable = rtl8153b_disable; 5372 ops->up = rtl8153b_up; 5373 ops->down = rtl8153b_down; 5374 ops->unload = rtl8153b_unload; 5375 ops->eee_get = r8153_get_eee; 5376 ops->eee_set = r8153b_set_eee; 5377 ops->in_nway = rtl8153_in_nway; 5378 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5379 ops->autosuspend_en = rtl8153b_runtime_enable; 5380 tp->rx_buf_sz = 32 * 1024; 5381 break; 5382 5383 default: 5384 ret = -ENODEV; 5385 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5386 break; 5387 } 5388 5389 return ret; 5390 } 5391 5392 static u8 rtl_get_version(struct usb_interface *intf) 5393 { 5394 struct usb_device *udev = interface_to_usbdev(intf); 5395 u32 ocp_data = 0; 5396 __le32 *tmp; 5397 u8 version; 5398 int ret; 5399 5400 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5401 if (!tmp) 5402 return 0; 5403 5404 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5405 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5406 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5407 if (ret > 0) 5408 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5409 5410 kfree(tmp); 5411 5412 switch (ocp_data) { 5413 case 0x4c00: 5414 version = RTL_VER_01; 5415 break; 5416 case 0x4c10: 5417 version = RTL_VER_02; 5418 break; 5419 case 0x5c00: 5420 version = RTL_VER_03; 5421 break; 5422 case 0x5c10: 5423 version = RTL_VER_04; 5424 break; 5425 case 0x5c20: 5426 version = RTL_VER_05; 5427 break; 5428 case 0x5c30: 5429 version = RTL_VER_06; 5430 break; 5431 case 0x4800: 5432 version = RTL_VER_07; 5433 break; 5434 case 0x6000: 5435 version = RTL_VER_08; 5436 break; 5437 case 0x6010: 5438 version = RTL_VER_09; 5439 break; 5440 default: 5441 version = RTL_VER_UNKNOWN; 5442 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5443 break; 5444 } 5445 5446 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5447 5448 return version; 5449 } 5450 5451 static int rtl8152_probe(struct usb_interface *intf, 5452 const struct usb_device_id *id) 5453 { 5454 struct usb_device *udev = interface_to_usbdev(intf); 5455 u8 version = rtl_get_version(intf); 5456 struct r8152 *tp; 5457 struct net_device *netdev; 5458 int ret; 5459 5460 if (version == RTL_VER_UNKNOWN) 5461 return -ENODEV; 5462 5463 if (udev->actconfig->desc.bConfigurationValue != 1) { 5464 usb_driver_set_configuration(udev, 1); 5465 return -ENODEV; 5466 } 5467 5468 usb_reset_device(udev); 5469 netdev = alloc_etherdev(sizeof(struct r8152)); 5470 if (!netdev) { 5471 dev_err(&intf->dev, "Out of memory\n"); 5472 return -ENOMEM; 5473 } 5474 5475 SET_NETDEV_DEV(netdev, &intf->dev); 5476 tp = netdev_priv(netdev); 5477 tp->msg_enable = 0x7FFF; 5478 5479 tp->udev = udev; 5480 tp->netdev = netdev; 5481 tp->intf = intf; 5482 tp->version = version; 5483 5484 switch (version) { 5485 case RTL_VER_01: 5486 case RTL_VER_02: 5487 case RTL_VER_07: 5488 tp->mii.supports_gmii = 0; 5489 break; 5490 default: 5491 tp->mii.supports_gmii = 1; 5492 break; 5493 } 5494 5495 ret = rtl_ops_init(tp); 5496 if (ret) 5497 goto out; 5498 5499 mutex_init(&tp->control); 5500 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5501 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5502 5503 netdev->netdev_ops = &rtl8152_netdev_ops; 5504 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5505 5506 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5507 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5508 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5509 NETIF_F_HW_VLAN_CTAG_TX; 5510 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5511 NETIF_F_TSO | NETIF_F_FRAGLIST | 5512 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5513 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5514 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5515 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5516 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5517 5518 if (tp->version == RTL_VER_01) { 5519 netdev->features &= ~NETIF_F_RXCSUM; 5520 netdev->hw_features &= ~NETIF_F_RXCSUM; 5521 } 5522 5523 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5524 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5525 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5526 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5527 } 5528 5529 netdev->ethtool_ops = &ops; 5530 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5531 5532 /* MTU range: 68 - 1500 or 9194 */ 5533 netdev->min_mtu = ETH_MIN_MTU; 5534 switch (tp->version) { 5535 case RTL_VER_01: 5536 case RTL_VER_02: 5537 netdev->max_mtu = ETH_DATA_LEN; 5538 break; 5539 default: 5540 netdev->max_mtu = RTL8153_MAX_MTU; 5541 break; 5542 } 5543 5544 tp->mii.dev = netdev; 5545 tp->mii.mdio_read = read_mii_word; 5546 tp->mii.mdio_write = write_mii_word; 5547 tp->mii.phy_id_mask = 0x3f; 5548 tp->mii.reg_num_mask = 0x1f; 5549 tp->mii.phy_id = R8152_PHY_ID; 5550 5551 tp->autoneg = AUTONEG_ENABLE; 5552 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5553 tp->duplex = DUPLEX_FULL; 5554 5555 tp->rx_copybreak = RTL8152_RXFG_HEADSZ; 5556 tp->rx_pending = 10 * RTL8152_MAX_RX; 5557 5558 intf->needs_remote_wakeup = 1; 5559 5560 tp->rtl_ops.init(tp); 5561 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5562 set_ethernet_addr(tp); 5563 5564 usb_set_intfdata(intf, tp); 5565 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5566 5567 ret = register_netdev(netdev); 5568 if (ret != 0) { 5569 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5570 goto out1; 5571 } 5572 5573 if (!rtl_can_wakeup(tp)) 5574 __rtl_set_wol(tp, 0); 5575 5576 tp->saved_wolopts = __rtl_get_wol(tp); 5577 if (tp->saved_wolopts) 5578 device_set_wakeup_enable(&udev->dev, true); 5579 else 5580 device_set_wakeup_enable(&udev->dev, false); 5581 5582 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5583 5584 return 0; 5585 5586 out1: 5587 netif_napi_del(&tp->napi); 5588 usb_set_intfdata(intf, NULL); 5589 out: 5590 free_netdev(netdev); 5591 return ret; 5592 } 5593 5594 static void rtl8152_disconnect(struct usb_interface *intf) 5595 { 5596 struct r8152 *tp = usb_get_intfdata(intf); 5597 5598 usb_set_intfdata(intf, NULL); 5599 if (tp) { 5600 rtl_set_unplug(tp); 5601 5602 netif_napi_del(&tp->napi); 5603 unregister_netdev(tp->netdev); 5604 cancel_delayed_work_sync(&tp->hw_phy_work); 5605 tp->rtl_ops.unload(tp); 5606 free_netdev(tp->netdev); 5607 } 5608 } 5609 5610 #define REALTEK_USB_DEVICE(vend, prod) \ 5611 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5612 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5613 .idVendor = (vend), \ 5614 .idProduct = (prod), \ 5615 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5616 }, \ 5617 { \ 5618 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5619 USB_DEVICE_ID_MATCH_DEVICE, \ 5620 .idVendor = (vend), \ 5621 .idProduct = (prod), \ 5622 .bInterfaceClass = USB_CLASS_COMM, \ 5623 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5624 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5625 5626 /* table of devices that work with this driver */ 5627 static const struct usb_device_id rtl8152_table[] = { 5628 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5629 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5630 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5631 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5632 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5633 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5634 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5635 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5636 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5637 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5638 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5639 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5640 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5641 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5642 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5643 {} 5644 }; 5645 5646 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5647 5648 static struct usb_driver rtl8152_driver = { 5649 .name = MODULENAME, 5650 .id_table = rtl8152_table, 5651 .probe = rtl8152_probe, 5652 .disconnect = rtl8152_disconnect, 5653 .suspend = rtl8152_suspend, 5654 .resume = rtl8152_resume, 5655 .reset_resume = rtl8152_reset_resume, 5656 .pre_reset = rtl8152_pre_reset, 5657 .post_reset = rtl8152_post_reset, 5658 .supports_autosuspend = 1, 5659 .disable_hub_initiated_lpm = 1, 5660 }; 5661 5662 module_usb_driver(rtl8152_driver); 5663 5664 MODULE_AUTHOR(DRIVER_AUTHOR); 5665 MODULE_DESCRIPTION(DRIVER_DESC); 5666 MODULE_LICENSE("GPL"); 5667 MODULE_VERSION(DRIVER_VERSION); 5668