1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 30 /* Information for net-next */ 31 #define NETNEXT_VERSION "08" 32 33 /* Information for net */ 34 #define NET_VERSION "3" 35 36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 39 #define MODULENAME "r8152" 40 41 #define R8152_PHY_ID 32 42 43 #define PLA_IDR 0xc000 44 #define PLA_RCR 0xc010 45 #define PLA_RMS 0xc016 46 #define PLA_RXFIFO_CTRL0 0xc0a0 47 #define PLA_RXFIFO_CTRL1 0xc0a4 48 #define PLA_RXFIFO_CTRL2 0xc0a8 49 #define PLA_DMY_REG0 0xc0b0 50 #define PLA_FMC 0xc0b4 51 #define PLA_CFG_WOL 0xc0b6 52 #define PLA_TEREDO_CFG 0xc0bc 53 #define PLA_MAR 0xcd00 54 #define PLA_BACKUP 0xd000 55 #define PAL_BDC_CR 0xd1a0 56 #define PLA_TEREDO_TIMER 0xd2cc 57 #define PLA_REALWOW_TIMER 0xd2e8 58 #define PLA_LEDSEL 0xdd90 59 #define PLA_LED_FEATURE 0xdd92 60 #define PLA_PHYAR 0xde00 61 #define PLA_BOOT_CTRL 0xe004 62 #define PLA_GPHY_INTR_IMR 0xe022 63 #define PLA_EEE_CR 0xe040 64 #define PLA_EEEP_CR 0xe080 65 #define PLA_MAC_PWR_CTRL 0xe0c0 66 #define PLA_MAC_PWR_CTRL2 0xe0ca 67 #define PLA_MAC_PWR_CTRL3 0xe0cc 68 #define PLA_MAC_PWR_CTRL4 0xe0ce 69 #define PLA_WDT6_CTRL 0xe428 70 #define PLA_TCR0 0xe610 71 #define PLA_TCR1 0xe612 72 #define PLA_MTPS 0xe615 73 #define PLA_TXFIFO_CTRL 0xe618 74 #define PLA_RSTTALLY 0xe800 75 #define PLA_CR 0xe813 76 #define PLA_CRWECR 0xe81c 77 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 78 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 79 #define PLA_CONFIG5 0xe822 80 #define PLA_PHY_PWR 0xe84c 81 #define PLA_OOB_CTRL 0xe84f 82 #define PLA_CPCR 0xe854 83 #define PLA_MISC_0 0xe858 84 #define PLA_MISC_1 0xe85a 85 #define PLA_OCP_GPHY_BASE 0xe86c 86 #define PLA_TALLYCNT 0xe890 87 #define PLA_SFF_STS_7 0xe8de 88 #define PLA_PHYSTATUS 0xe908 89 #define PLA_BP_BA 0xfc26 90 #define PLA_BP_0 0xfc28 91 #define PLA_BP_1 0xfc2a 92 #define PLA_BP_2 0xfc2c 93 #define PLA_BP_3 0xfc2e 94 #define PLA_BP_4 0xfc30 95 #define PLA_BP_5 0xfc32 96 #define PLA_BP_6 0xfc34 97 #define PLA_BP_7 0xfc36 98 #define PLA_BP_EN 0xfc38 99 100 #define USB_USB2PHY 0xb41e 101 #define USB_SSPHYLINK2 0xb428 102 #define USB_U2P3_CTRL 0xb460 103 #define USB_CSR_DUMMY1 0xb464 104 #define USB_CSR_DUMMY2 0xb466 105 #define USB_DEV_STAT 0xb808 106 #define USB_CONNECT_TIMER 0xcbf8 107 #define USB_BURST_SIZE 0xcfc0 108 #define USB_USB_CTRL 0xd406 109 #define USB_PHY_CTRL 0xd408 110 #define USB_TX_AGG 0xd40a 111 #define USB_RX_BUF_TH 0xd40c 112 #define USB_USB_TIMER 0xd428 113 #define USB_RX_EARLY_TIMEOUT 0xd42c 114 #define USB_RX_EARLY_SIZE 0xd42e 115 #define USB_PM_CTRL_STATUS 0xd432 116 #define USB_TX_DMA 0xd434 117 #define USB_TOLERANCE 0xd490 118 #define USB_LPM_CTRL 0xd41a 119 #define USB_UPS_CTRL 0xd800 120 #define USB_MISC_0 0xd81a 121 #define USB_POWER_CUT 0xd80a 122 #define USB_AFE_CTRL2 0xd824 123 #define USB_WDT11_CTRL 0xe43c 124 #define USB_BP_BA 0xfc26 125 #define USB_BP_0 0xfc28 126 #define USB_BP_1 0xfc2a 127 #define USB_BP_2 0xfc2c 128 #define USB_BP_3 0xfc2e 129 #define USB_BP_4 0xfc30 130 #define USB_BP_5 0xfc32 131 #define USB_BP_6 0xfc34 132 #define USB_BP_7 0xfc36 133 #define USB_BP_EN 0xfc38 134 135 /* OCP Registers */ 136 #define OCP_ALDPS_CONFIG 0x2010 137 #define OCP_EEE_CONFIG1 0x2080 138 #define OCP_EEE_CONFIG2 0x2092 139 #define OCP_EEE_CONFIG3 0x2094 140 #define OCP_BASE_MII 0xa400 141 #define OCP_EEE_AR 0xa41a 142 #define OCP_EEE_DATA 0xa41c 143 #define OCP_PHY_STATUS 0xa420 144 #define OCP_POWER_CFG 0xa430 145 #define OCP_EEE_CFG 0xa432 146 #define OCP_SRAM_ADDR 0xa436 147 #define OCP_SRAM_DATA 0xa438 148 #define OCP_DOWN_SPEED 0xa442 149 #define OCP_EEE_ABLE 0xa5c4 150 #define OCP_EEE_ADV 0xa5d0 151 #define OCP_EEE_LPABLE 0xa5d2 152 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 153 #define OCP_ADC_CFG 0xbc06 154 155 /* SRAM Register */ 156 #define SRAM_LPF_CFG 0x8012 157 #define SRAM_10M_AMP1 0x8080 158 #define SRAM_10M_AMP2 0x8082 159 #define SRAM_IMPEDANCE 0x8084 160 161 /* PLA_RCR */ 162 #define RCR_AAP 0x00000001 163 #define RCR_APM 0x00000002 164 #define RCR_AM 0x00000004 165 #define RCR_AB 0x00000008 166 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 167 168 /* PLA_RXFIFO_CTRL0 */ 169 #define RXFIFO_THR1_NORMAL 0x00080002 170 #define RXFIFO_THR1_OOB 0x01800003 171 172 /* PLA_RXFIFO_CTRL1 */ 173 #define RXFIFO_THR2_FULL 0x00000060 174 #define RXFIFO_THR2_HIGH 0x00000038 175 #define RXFIFO_THR2_OOB 0x0000004a 176 #define RXFIFO_THR2_NORMAL 0x00a0 177 178 /* PLA_RXFIFO_CTRL2 */ 179 #define RXFIFO_THR3_FULL 0x00000078 180 #define RXFIFO_THR3_HIGH 0x00000048 181 #define RXFIFO_THR3_OOB 0x0000005a 182 #define RXFIFO_THR3_NORMAL 0x0110 183 184 /* PLA_TXFIFO_CTRL */ 185 #define TXFIFO_THR_NORMAL 0x00400008 186 #define TXFIFO_THR_NORMAL2 0x01000008 187 188 /* PLA_DMY_REG0 */ 189 #define ECM_ALDPS 0x0002 190 191 /* PLA_FMC */ 192 #define FMC_FCR_MCU_EN 0x0001 193 194 /* PLA_EEEP_CR */ 195 #define EEEP_CR_EEEP_TX 0x0002 196 197 /* PLA_WDT6_CTRL */ 198 #define WDT6_SET_MODE 0x0010 199 200 /* PLA_TCR0 */ 201 #define TCR0_TX_EMPTY 0x0800 202 #define TCR0_AUTO_FIFO 0x0080 203 204 /* PLA_TCR1 */ 205 #define VERSION_MASK 0x7cf0 206 207 /* PLA_MTPS */ 208 #define MTPS_JUMBO (12 * 1024 / 64) 209 #define MTPS_DEFAULT (6 * 1024 / 64) 210 211 /* PLA_RSTTALLY */ 212 #define TALLY_RESET 0x0001 213 214 /* PLA_CR */ 215 #define CR_RST 0x10 216 #define CR_RE 0x08 217 #define CR_TE 0x04 218 219 /* PLA_CRWECR */ 220 #define CRWECR_NORAML 0x00 221 #define CRWECR_CONFIG 0xc0 222 223 /* PLA_OOB_CTRL */ 224 #define NOW_IS_OOB 0x80 225 #define TXFIFO_EMPTY 0x20 226 #define RXFIFO_EMPTY 0x10 227 #define LINK_LIST_READY 0x02 228 #define DIS_MCU_CLROOB 0x01 229 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 230 231 /* PLA_MISC_1 */ 232 #define RXDY_GATED_EN 0x0008 233 234 /* PLA_SFF_STS_7 */ 235 #define RE_INIT_LL 0x8000 236 #define MCU_BORW_EN 0x4000 237 238 /* PLA_CPCR */ 239 #define CPCR_RX_VLAN 0x0040 240 241 /* PLA_CFG_WOL */ 242 #define MAGIC_EN 0x0001 243 244 /* PLA_TEREDO_CFG */ 245 #define TEREDO_SEL 0x8000 246 #define TEREDO_WAKE_MASK 0x7f00 247 #define TEREDO_RS_EVENT_MASK 0x00fe 248 #define OOB_TEREDO_EN 0x0001 249 250 /* PAL_BDC_CR */ 251 #define ALDPS_PROXY_MODE 0x0001 252 253 /* PLA_CONFIG34 */ 254 #define LINK_ON_WAKE_EN 0x0010 255 #define LINK_OFF_WAKE_EN 0x0008 256 257 /* PLA_CONFIG5 */ 258 #define BWF_EN 0x0040 259 #define MWF_EN 0x0020 260 #define UWF_EN 0x0010 261 #define LAN_WAKE_EN 0x0002 262 263 /* PLA_LED_FEATURE */ 264 #define LED_MODE_MASK 0x0700 265 266 /* PLA_PHY_PWR */ 267 #define TX_10M_IDLE_EN 0x0080 268 #define PFM_PWM_SWITCH 0x0040 269 270 /* PLA_MAC_PWR_CTRL */ 271 #define D3_CLK_GATED_EN 0x00004000 272 #define MCU_CLK_RATIO 0x07010f07 273 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 274 #define ALDPS_SPDWN_RATIO 0x0f87 275 276 /* PLA_MAC_PWR_CTRL2 */ 277 #define EEE_SPDWN_RATIO 0x8007 278 279 /* PLA_MAC_PWR_CTRL3 */ 280 #define PKT_AVAIL_SPDWN_EN 0x0100 281 #define SUSPEND_SPDWN_EN 0x0004 282 #define U1U2_SPDWN_EN 0x0002 283 #define L1_SPDWN_EN 0x0001 284 285 /* PLA_MAC_PWR_CTRL4 */ 286 #define PWRSAVE_SPDWN_EN 0x1000 287 #define RXDV_SPDWN_EN 0x0800 288 #define TX10MIDLE_EN 0x0100 289 #define TP100_SPDWN_EN 0x0020 290 #define TP500_SPDWN_EN 0x0010 291 #define TP1000_SPDWN_EN 0x0008 292 #define EEE_SPDWN_EN 0x0001 293 294 /* PLA_GPHY_INTR_IMR */ 295 #define GPHY_STS_MSK 0x0001 296 #define SPEED_DOWN_MSK 0x0002 297 #define SPDWN_RXDV_MSK 0x0004 298 #define SPDWN_LINKCHG_MSK 0x0008 299 300 /* PLA_PHYAR */ 301 #define PHYAR_FLAG 0x80000000 302 303 /* PLA_EEE_CR */ 304 #define EEE_RX_EN 0x0001 305 #define EEE_TX_EN 0x0002 306 307 /* PLA_BOOT_CTRL */ 308 #define AUTOLOAD_DONE 0x0002 309 310 /* USB_USB2PHY */ 311 #define USB2PHY_SUSPEND 0x0001 312 #define USB2PHY_L1 0x0002 313 314 /* USB_SSPHYLINK2 */ 315 #define pwd_dn_scale_mask 0x3ffe 316 #define pwd_dn_scale(x) ((x) << 1) 317 318 /* USB_CSR_DUMMY1 */ 319 #define DYNAMIC_BURST 0x0001 320 321 /* USB_CSR_DUMMY2 */ 322 #define EP4_FULL_FC 0x0001 323 324 /* USB_DEV_STAT */ 325 #define STAT_SPEED_MASK 0x0006 326 #define STAT_SPEED_HIGH 0x0000 327 #define STAT_SPEED_FULL 0x0002 328 329 /* USB_TX_AGG */ 330 #define TX_AGG_MAX_THRESHOLD 0x03 331 332 /* USB_RX_BUF_TH */ 333 #define RX_THR_SUPPER 0x0c350180 334 #define RX_THR_HIGH 0x7a120180 335 #define RX_THR_SLOW 0xffff0180 336 337 /* USB_TX_DMA */ 338 #define TEST_MODE_DISABLE 0x00000001 339 #define TX_SIZE_ADJUST1 0x00000100 340 341 /* USB_UPS_CTRL */ 342 #define POWER_CUT 0x0100 343 344 /* USB_PM_CTRL_STATUS */ 345 #define RESUME_INDICATE 0x0001 346 347 /* USB_USB_CTRL */ 348 #define RX_AGG_DISABLE 0x0010 349 #define RX_ZERO_EN 0x0080 350 351 /* USB_U2P3_CTRL */ 352 #define U2P3_ENABLE 0x0001 353 354 /* USB_POWER_CUT */ 355 #define PWR_EN 0x0001 356 #define PHASE2_EN 0x0008 357 358 /* USB_MISC_0 */ 359 #define PCUT_STATUS 0x0001 360 361 /* USB_RX_EARLY_TIMEOUT */ 362 #define COALESCE_SUPER 85000U 363 #define COALESCE_HIGH 250000U 364 #define COALESCE_SLOW 524280U 365 366 /* USB_WDT11_CTRL */ 367 #define TIMER11_EN 0x0001 368 369 /* USB_LPM_CTRL */ 370 /* bit 4 ~ 5: fifo empty boundary */ 371 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 372 /* bit 2 ~ 3: LMP timer */ 373 #define LPM_TIMER_MASK 0x0c 374 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 375 #define LPM_TIMER_500US 0x0c /* 500 us */ 376 #define ROK_EXIT_LPM 0x02 377 378 /* USB_AFE_CTRL2 */ 379 #define SEN_VAL_MASK 0xf800 380 #define SEN_VAL_NORMAL 0xa000 381 #define SEL_RXIDLE 0x0100 382 383 /* OCP_ALDPS_CONFIG */ 384 #define ENPWRSAVE 0x8000 385 #define ENPDNPS 0x0200 386 #define LINKENA 0x0100 387 #define DIS_SDSAVE 0x0010 388 389 /* OCP_PHY_STATUS */ 390 #define PHY_STAT_MASK 0x0007 391 #define PHY_STAT_LAN_ON 3 392 #define PHY_STAT_PWRDN 5 393 394 /* OCP_POWER_CFG */ 395 #define EEE_CLKDIV_EN 0x8000 396 #define EN_ALDPS 0x0004 397 #define EN_10M_PLLOFF 0x0001 398 399 /* OCP_EEE_CONFIG1 */ 400 #define RG_TXLPI_MSK_HFDUP 0x8000 401 #define RG_MATCLR_EN 0x4000 402 #define EEE_10_CAP 0x2000 403 #define EEE_NWAY_EN 0x1000 404 #define TX_QUIET_EN 0x0200 405 #define RX_QUIET_EN 0x0100 406 #define sd_rise_time_mask 0x0070 407 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 408 #define RG_RXLPI_MSK_HFDUP 0x0008 409 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 410 411 /* OCP_EEE_CONFIG2 */ 412 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 413 #define RG_DACQUIET_EN 0x0400 414 #define RG_LDVQUIET_EN 0x0200 415 #define RG_CKRSEL 0x0020 416 #define RG_EEEPRG_EN 0x0010 417 418 /* OCP_EEE_CONFIG3 */ 419 #define fast_snr_mask 0xff80 420 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 421 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 422 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 423 424 /* OCP_EEE_AR */ 425 /* bit[15:14] function */ 426 #define FUN_ADDR 0x0000 427 #define FUN_DATA 0x4000 428 /* bit[4:0] device addr */ 429 430 /* OCP_EEE_CFG */ 431 #define CTAP_SHORT_EN 0x0040 432 #define EEE10_EN 0x0010 433 434 /* OCP_DOWN_SPEED */ 435 #define EN_10M_BGOFF 0x0080 436 437 /* OCP_PHY_STATE */ 438 #define TXDIS_STATE 0x01 439 #define ABD_STATE 0x02 440 441 /* OCP_ADC_CFG */ 442 #define CKADSEL_L 0x0100 443 #define ADC_EN 0x0080 444 #define EN_EMI_L 0x0040 445 446 /* SRAM_LPF_CFG */ 447 #define LPF_AUTO_TUNE 0x8000 448 449 /* SRAM_10M_AMP1 */ 450 #define GDAC_IB_UPALL 0x0008 451 452 /* SRAM_10M_AMP2 */ 453 #define AMP_DN 0x0200 454 455 /* SRAM_IMPEDANCE */ 456 #define RX_DRIVING_MASK 0x6000 457 458 enum rtl_register_content { 459 _1000bps = 0x10, 460 _100bps = 0x08, 461 _10bps = 0x04, 462 LINK_STATUS = 0x02, 463 FULL_DUP = 0x01, 464 }; 465 466 #define RTL8152_MAX_TX 4 467 #define RTL8152_MAX_RX 10 468 #define INTBUFSIZE 2 469 #define CRC_SIZE 4 470 #define TX_ALIGN 4 471 #define RX_ALIGN 8 472 473 #define INTR_LINK 0x0004 474 475 #define RTL8152_REQT_READ 0xc0 476 #define RTL8152_REQT_WRITE 0x40 477 #define RTL8152_REQ_GET_REGS 0x05 478 #define RTL8152_REQ_SET_REGS 0x05 479 480 #define BYTE_EN_DWORD 0xff 481 #define BYTE_EN_WORD 0x33 482 #define BYTE_EN_BYTE 0x11 483 #define BYTE_EN_SIX_BYTES 0x3f 484 #define BYTE_EN_START_MASK 0x0f 485 #define BYTE_EN_END_MASK 0xf0 486 487 #define RTL8153_MAX_PACKET 9216 /* 9K */ 488 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 489 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 490 #define RTL8153_RMS RTL8153_MAX_PACKET 491 #define RTL8152_TX_TIMEOUT (5 * HZ) 492 #define RTL8152_NAPI_WEIGHT 64 493 494 /* rtl8152 flags */ 495 enum rtl8152_flags { 496 RTL8152_UNPLUG = 0, 497 RTL8152_SET_RX_MODE, 498 WORK_ENABLE, 499 RTL8152_LINK_CHG, 500 SELECTIVE_SUSPEND, 501 PHY_RESET, 502 SCHEDULE_NAPI, 503 }; 504 505 /* Define these values to match your device */ 506 #define VENDOR_ID_REALTEK 0x0bda 507 #define VENDOR_ID_SAMSUNG 0x04e8 508 #define VENDOR_ID_LENOVO 0x17ef 509 #define VENDOR_ID_NVIDIA 0x0955 510 511 #define MCU_TYPE_PLA 0x0100 512 #define MCU_TYPE_USB 0x0000 513 514 struct tally_counter { 515 __le64 tx_packets; 516 __le64 rx_packets; 517 __le64 tx_errors; 518 __le32 rx_errors; 519 __le16 rx_missed; 520 __le16 align_errors; 521 __le32 tx_one_collision; 522 __le32 tx_multi_collision; 523 __le64 rx_unicast; 524 __le64 rx_broadcast; 525 __le32 rx_multicast; 526 __le16 tx_aborted; 527 __le16 tx_underrun; 528 }; 529 530 struct rx_desc { 531 __le32 opts1; 532 #define RX_LEN_MASK 0x7fff 533 534 __le32 opts2; 535 #define RD_UDP_CS BIT(23) 536 #define RD_TCP_CS BIT(22) 537 #define RD_IPV6_CS BIT(20) 538 #define RD_IPV4_CS BIT(19) 539 540 __le32 opts3; 541 #define IPF BIT(23) /* IP checksum fail */ 542 #define UDPF BIT(22) /* UDP checksum fail */ 543 #define TCPF BIT(21) /* TCP checksum fail */ 544 #define RX_VLAN_TAG BIT(16) 545 546 __le32 opts4; 547 __le32 opts5; 548 __le32 opts6; 549 }; 550 551 struct tx_desc { 552 __le32 opts1; 553 #define TX_FS BIT(31) /* First segment of a packet */ 554 #define TX_LS BIT(30) /* Final segment of a packet */ 555 #define GTSENDV4 BIT(28) 556 #define GTSENDV6 BIT(27) 557 #define GTTCPHO_SHIFT 18 558 #define GTTCPHO_MAX 0x7fU 559 #define TX_LEN_MAX 0x3ffffU 560 561 __le32 opts2; 562 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 563 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 564 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 565 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 566 #define MSS_SHIFT 17 567 #define MSS_MAX 0x7ffU 568 #define TCPHO_SHIFT 17 569 #define TCPHO_MAX 0x7ffU 570 #define TX_VLAN_TAG BIT(16) 571 }; 572 573 struct r8152; 574 575 struct rx_agg { 576 struct list_head list; 577 struct urb *urb; 578 struct r8152 *context; 579 void *buffer; 580 void *head; 581 }; 582 583 struct tx_agg { 584 struct list_head list; 585 struct urb *urb; 586 struct r8152 *context; 587 void *buffer; 588 void *head; 589 u32 skb_num; 590 u32 skb_len; 591 }; 592 593 struct r8152 { 594 unsigned long flags; 595 struct usb_device *udev; 596 struct napi_struct napi; 597 struct usb_interface *intf; 598 struct net_device *netdev; 599 struct urb *intr_urb; 600 struct tx_agg tx_info[RTL8152_MAX_TX]; 601 struct rx_agg rx_info[RTL8152_MAX_RX]; 602 struct list_head rx_done, tx_free; 603 struct sk_buff_head tx_queue, rx_queue; 604 spinlock_t rx_lock, tx_lock; 605 struct delayed_work schedule, hw_phy_work; 606 struct mii_if_info mii; 607 struct mutex control; /* use for hw setting */ 608 #ifdef CONFIG_PM_SLEEP 609 struct notifier_block pm_notifier; 610 #endif 611 612 struct rtl_ops { 613 void (*init)(struct r8152 *); 614 int (*enable)(struct r8152 *); 615 void (*disable)(struct r8152 *); 616 void (*up)(struct r8152 *); 617 void (*down)(struct r8152 *); 618 void (*unload)(struct r8152 *); 619 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 620 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 621 bool (*in_nway)(struct r8152 *); 622 void (*hw_phy_cfg)(struct r8152 *); 623 } rtl_ops; 624 625 int intr_interval; 626 u32 saved_wolopts; 627 u32 msg_enable; 628 u32 tx_qlen; 629 u32 coalesce; 630 u16 ocp_base; 631 u16 speed; 632 u8 *intr_buff; 633 u8 version; 634 u8 duplex; 635 u8 autoneg; 636 }; 637 638 enum rtl_version { 639 RTL_VER_UNKNOWN = 0, 640 RTL_VER_01, 641 RTL_VER_02, 642 RTL_VER_03, 643 RTL_VER_04, 644 RTL_VER_05, 645 RTL_VER_06, 646 RTL_VER_MAX 647 }; 648 649 enum tx_csum_stat { 650 TX_CSUM_SUCCESS = 0, 651 TX_CSUM_TSO, 652 TX_CSUM_NONE 653 }; 654 655 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 656 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 657 */ 658 static const int multicast_filter_limit = 32; 659 static unsigned int agg_buf_sz = 16384; 660 661 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 662 VLAN_ETH_HLEN - VLAN_HLEN) 663 664 static 665 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 666 { 667 int ret; 668 void *tmp; 669 670 tmp = kmalloc(size, GFP_KERNEL); 671 if (!tmp) 672 return -ENOMEM; 673 674 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 675 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 676 value, index, tmp, size, 500); 677 678 memcpy(data, tmp, size); 679 kfree(tmp); 680 681 return ret; 682 } 683 684 static 685 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 686 { 687 int ret; 688 void *tmp; 689 690 tmp = kmemdup(data, size, GFP_KERNEL); 691 if (!tmp) 692 return -ENOMEM; 693 694 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 695 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 696 value, index, tmp, size, 500); 697 698 kfree(tmp); 699 700 return ret; 701 } 702 703 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 704 void *data, u16 type) 705 { 706 u16 limit = 64; 707 int ret = 0; 708 709 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 710 return -ENODEV; 711 712 /* both size and indix must be 4 bytes align */ 713 if ((size & 3) || !size || (index & 3) || !data) 714 return -EPERM; 715 716 if ((u32)index + (u32)size > 0xffff) 717 return -EPERM; 718 719 while (size) { 720 if (size > limit) { 721 ret = get_registers(tp, index, type, limit, data); 722 if (ret < 0) 723 break; 724 725 index += limit; 726 data += limit; 727 size -= limit; 728 } else { 729 ret = get_registers(tp, index, type, size, data); 730 if (ret < 0) 731 break; 732 733 index += size; 734 data += size; 735 size = 0; 736 break; 737 } 738 } 739 740 if (ret == -ENODEV) 741 set_bit(RTL8152_UNPLUG, &tp->flags); 742 743 return ret; 744 } 745 746 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 747 u16 size, void *data, u16 type) 748 { 749 int ret; 750 u16 byteen_start, byteen_end, byen; 751 u16 limit = 512; 752 753 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 754 return -ENODEV; 755 756 /* both size and indix must be 4 bytes align */ 757 if ((size & 3) || !size || (index & 3) || !data) 758 return -EPERM; 759 760 if ((u32)index + (u32)size > 0xffff) 761 return -EPERM; 762 763 byteen_start = byteen & BYTE_EN_START_MASK; 764 byteen_end = byteen & BYTE_EN_END_MASK; 765 766 byen = byteen_start | (byteen_start << 4); 767 ret = set_registers(tp, index, type | byen, 4, data); 768 if (ret < 0) 769 goto error1; 770 771 index += 4; 772 data += 4; 773 size -= 4; 774 775 if (size) { 776 size -= 4; 777 778 while (size) { 779 if (size > limit) { 780 ret = set_registers(tp, index, 781 type | BYTE_EN_DWORD, 782 limit, data); 783 if (ret < 0) 784 goto error1; 785 786 index += limit; 787 data += limit; 788 size -= limit; 789 } else { 790 ret = set_registers(tp, index, 791 type | BYTE_EN_DWORD, 792 size, data); 793 if (ret < 0) 794 goto error1; 795 796 index += size; 797 data += size; 798 size = 0; 799 break; 800 } 801 } 802 803 byen = byteen_end | (byteen_end >> 4); 804 ret = set_registers(tp, index, type | byen, 4, data); 805 if (ret < 0) 806 goto error1; 807 } 808 809 error1: 810 if (ret == -ENODEV) 811 set_bit(RTL8152_UNPLUG, &tp->flags); 812 813 return ret; 814 } 815 816 static inline 817 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 818 { 819 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 820 } 821 822 static inline 823 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 824 { 825 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 826 } 827 828 static inline 829 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 830 { 831 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 832 } 833 834 static inline 835 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 836 { 837 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 838 } 839 840 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 841 { 842 __le32 data; 843 844 generic_ocp_read(tp, index, sizeof(data), &data, type); 845 846 return __le32_to_cpu(data); 847 } 848 849 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 850 { 851 __le32 tmp = __cpu_to_le32(data); 852 853 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 854 } 855 856 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 857 { 858 u32 data; 859 __le32 tmp; 860 u8 shift = index & 2; 861 862 index &= ~3; 863 864 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 865 866 data = __le32_to_cpu(tmp); 867 data >>= (shift * 8); 868 data &= 0xffff; 869 870 return (u16)data; 871 } 872 873 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 874 { 875 u32 mask = 0xffff; 876 __le32 tmp; 877 u16 byen = BYTE_EN_WORD; 878 u8 shift = index & 2; 879 880 data &= mask; 881 882 if (index & 2) { 883 byen <<= shift; 884 mask <<= (shift * 8); 885 data <<= (shift * 8); 886 index &= ~3; 887 } 888 889 tmp = __cpu_to_le32(data); 890 891 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 892 } 893 894 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 895 { 896 u32 data; 897 __le32 tmp; 898 u8 shift = index & 3; 899 900 index &= ~3; 901 902 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 903 904 data = __le32_to_cpu(tmp); 905 data >>= (shift * 8); 906 data &= 0xff; 907 908 return (u8)data; 909 } 910 911 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 912 { 913 u32 mask = 0xff; 914 __le32 tmp; 915 u16 byen = BYTE_EN_BYTE; 916 u8 shift = index & 3; 917 918 data &= mask; 919 920 if (index & 3) { 921 byen <<= shift; 922 mask <<= (shift * 8); 923 data <<= (shift * 8); 924 index &= ~3; 925 } 926 927 tmp = __cpu_to_le32(data); 928 929 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 930 } 931 932 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 933 { 934 u16 ocp_base, ocp_index; 935 936 ocp_base = addr & 0xf000; 937 if (ocp_base != tp->ocp_base) { 938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 939 tp->ocp_base = ocp_base; 940 } 941 942 ocp_index = (addr & 0x0fff) | 0xb000; 943 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 944 } 945 946 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 947 { 948 u16 ocp_base, ocp_index; 949 950 ocp_base = addr & 0xf000; 951 if (ocp_base != tp->ocp_base) { 952 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 953 tp->ocp_base = ocp_base; 954 } 955 956 ocp_index = (addr & 0x0fff) | 0xb000; 957 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 958 } 959 960 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 961 { 962 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 963 } 964 965 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 966 { 967 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 968 } 969 970 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 971 { 972 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 973 ocp_reg_write(tp, OCP_SRAM_DATA, data); 974 } 975 976 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 977 { 978 struct r8152 *tp = netdev_priv(netdev); 979 int ret; 980 981 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 982 return -ENODEV; 983 984 if (phy_id != R8152_PHY_ID) 985 return -EINVAL; 986 987 ret = r8152_mdio_read(tp, reg); 988 989 return ret; 990 } 991 992 static 993 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 994 { 995 struct r8152 *tp = netdev_priv(netdev); 996 997 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 998 return; 999 1000 if (phy_id != R8152_PHY_ID) 1001 return; 1002 1003 r8152_mdio_write(tp, reg, val); 1004 } 1005 1006 static int 1007 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1008 1009 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1010 { 1011 struct r8152 *tp = netdev_priv(netdev); 1012 struct sockaddr *addr = p; 1013 int ret = -EADDRNOTAVAIL; 1014 1015 if (!is_valid_ether_addr(addr->sa_data)) 1016 goto out1; 1017 1018 ret = usb_autopm_get_interface(tp->intf); 1019 if (ret < 0) 1020 goto out1; 1021 1022 mutex_lock(&tp->control); 1023 1024 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1025 1026 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1027 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1029 1030 mutex_unlock(&tp->control); 1031 1032 usb_autopm_put_interface(tp->intf); 1033 out1: 1034 return ret; 1035 } 1036 1037 static int set_ethernet_addr(struct r8152 *tp) 1038 { 1039 struct net_device *dev = tp->netdev; 1040 struct sockaddr sa; 1041 int ret; 1042 1043 if (tp->version == RTL_VER_01) 1044 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1045 else 1046 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1047 1048 if (ret < 0) { 1049 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1050 } else if (!is_valid_ether_addr(sa.sa_data)) { 1051 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1052 sa.sa_data); 1053 eth_hw_addr_random(dev); 1054 ether_addr_copy(sa.sa_data, dev->dev_addr); 1055 ret = rtl8152_set_mac_address(dev, &sa); 1056 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1057 sa.sa_data); 1058 } else { 1059 if (tp->version == RTL_VER_01) 1060 ether_addr_copy(dev->dev_addr, sa.sa_data); 1061 else 1062 ret = rtl8152_set_mac_address(dev, &sa); 1063 } 1064 1065 return ret; 1066 } 1067 1068 static void read_bulk_callback(struct urb *urb) 1069 { 1070 struct net_device *netdev; 1071 int status = urb->status; 1072 struct rx_agg *agg; 1073 struct r8152 *tp; 1074 1075 agg = urb->context; 1076 if (!agg) 1077 return; 1078 1079 tp = agg->context; 1080 if (!tp) 1081 return; 1082 1083 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1084 return; 1085 1086 if (!test_bit(WORK_ENABLE, &tp->flags)) 1087 return; 1088 1089 netdev = tp->netdev; 1090 1091 /* When link down, the driver would cancel all bulks. */ 1092 /* This avoid the re-submitting bulk */ 1093 if (!netif_carrier_ok(netdev)) 1094 return; 1095 1096 usb_mark_last_busy(tp->udev); 1097 1098 switch (status) { 1099 case 0: 1100 if (urb->actual_length < ETH_ZLEN) 1101 break; 1102 1103 spin_lock(&tp->rx_lock); 1104 list_add_tail(&agg->list, &tp->rx_done); 1105 spin_unlock(&tp->rx_lock); 1106 napi_schedule(&tp->napi); 1107 return; 1108 case -ESHUTDOWN: 1109 set_bit(RTL8152_UNPLUG, &tp->flags); 1110 netif_device_detach(tp->netdev); 1111 return; 1112 case -ENOENT: 1113 return; /* the urb is in unlink state */ 1114 case -ETIME: 1115 if (net_ratelimit()) 1116 netdev_warn(netdev, "maybe reset is needed?\n"); 1117 break; 1118 default: 1119 if (net_ratelimit()) 1120 netdev_warn(netdev, "Rx status %d\n", status); 1121 break; 1122 } 1123 1124 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1125 } 1126 1127 static void write_bulk_callback(struct urb *urb) 1128 { 1129 struct net_device_stats *stats; 1130 struct net_device *netdev; 1131 struct tx_agg *agg; 1132 struct r8152 *tp; 1133 int status = urb->status; 1134 1135 agg = urb->context; 1136 if (!agg) 1137 return; 1138 1139 tp = agg->context; 1140 if (!tp) 1141 return; 1142 1143 netdev = tp->netdev; 1144 stats = &netdev->stats; 1145 if (status) { 1146 if (net_ratelimit()) 1147 netdev_warn(netdev, "Tx status %d\n", status); 1148 stats->tx_errors += agg->skb_num; 1149 } else { 1150 stats->tx_packets += agg->skb_num; 1151 stats->tx_bytes += agg->skb_len; 1152 } 1153 1154 spin_lock(&tp->tx_lock); 1155 list_add_tail(&agg->list, &tp->tx_free); 1156 spin_unlock(&tp->tx_lock); 1157 1158 usb_autopm_put_interface_async(tp->intf); 1159 1160 if (!netif_carrier_ok(netdev)) 1161 return; 1162 1163 if (!test_bit(WORK_ENABLE, &tp->flags)) 1164 return; 1165 1166 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1167 return; 1168 1169 if (!skb_queue_empty(&tp->tx_queue)) 1170 napi_schedule(&tp->napi); 1171 } 1172 1173 static void intr_callback(struct urb *urb) 1174 { 1175 struct r8152 *tp; 1176 __le16 *d; 1177 int status = urb->status; 1178 int res; 1179 1180 tp = urb->context; 1181 if (!tp) 1182 return; 1183 1184 if (!test_bit(WORK_ENABLE, &tp->flags)) 1185 return; 1186 1187 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1188 return; 1189 1190 switch (status) { 1191 case 0: /* success */ 1192 break; 1193 case -ECONNRESET: /* unlink */ 1194 case -ESHUTDOWN: 1195 netif_device_detach(tp->netdev); 1196 case -ENOENT: 1197 case -EPROTO: 1198 netif_info(tp, intr, tp->netdev, 1199 "Stop submitting intr, status %d\n", status); 1200 return; 1201 case -EOVERFLOW: 1202 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1203 goto resubmit; 1204 /* -EPIPE: should clear the halt */ 1205 default: 1206 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1207 goto resubmit; 1208 } 1209 1210 d = urb->transfer_buffer; 1211 if (INTR_LINK & __le16_to_cpu(d[0])) { 1212 if (!netif_carrier_ok(tp->netdev)) { 1213 set_bit(RTL8152_LINK_CHG, &tp->flags); 1214 schedule_delayed_work(&tp->schedule, 0); 1215 } 1216 } else { 1217 if (netif_carrier_ok(tp->netdev)) { 1218 set_bit(RTL8152_LINK_CHG, &tp->flags); 1219 schedule_delayed_work(&tp->schedule, 0); 1220 } 1221 } 1222 1223 resubmit: 1224 res = usb_submit_urb(urb, GFP_ATOMIC); 1225 if (res == -ENODEV) { 1226 set_bit(RTL8152_UNPLUG, &tp->flags); 1227 netif_device_detach(tp->netdev); 1228 } else if (res) { 1229 netif_err(tp, intr, tp->netdev, 1230 "can't resubmit intr, status %d\n", res); 1231 } 1232 } 1233 1234 static inline void *rx_agg_align(void *data) 1235 { 1236 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1237 } 1238 1239 static inline void *tx_agg_align(void *data) 1240 { 1241 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1242 } 1243 1244 static void free_all_mem(struct r8152 *tp) 1245 { 1246 int i; 1247 1248 for (i = 0; i < RTL8152_MAX_RX; i++) { 1249 usb_free_urb(tp->rx_info[i].urb); 1250 tp->rx_info[i].urb = NULL; 1251 1252 kfree(tp->rx_info[i].buffer); 1253 tp->rx_info[i].buffer = NULL; 1254 tp->rx_info[i].head = NULL; 1255 } 1256 1257 for (i = 0; i < RTL8152_MAX_TX; i++) { 1258 usb_free_urb(tp->tx_info[i].urb); 1259 tp->tx_info[i].urb = NULL; 1260 1261 kfree(tp->tx_info[i].buffer); 1262 tp->tx_info[i].buffer = NULL; 1263 tp->tx_info[i].head = NULL; 1264 } 1265 1266 usb_free_urb(tp->intr_urb); 1267 tp->intr_urb = NULL; 1268 1269 kfree(tp->intr_buff); 1270 tp->intr_buff = NULL; 1271 } 1272 1273 static int alloc_all_mem(struct r8152 *tp) 1274 { 1275 struct net_device *netdev = tp->netdev; 1276 struct usb_interface *intf = tp->intf; 1277 struct usb_host_interface *alt = intf->cur_altsetting; 1278 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1279 struct urb *urb; 1280 int node, i; 1281 u8 *buf; 1282 1283 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1284 1285 spin_lock_init(&tp->rx_lock); 1286 spin_lock_init(&tp->tx_lock); 1287 INIT_LIST_HEAD(&tp->tx_free); 1288 skb_queue_head_init(&tp->tx_queue); 1289 skb_queue_head_init(&tp->rx_queue); 1290 1291 for (i = 0; i < RTL8152_MAX_RX; i++) { 1292 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1293 if (!buf) 1294 goto err1; 1295 1296 if (buf != rx_agg_align(buf)) { 1297 kfree(buf); 1298 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1299 node); 1300 if (!buf) 1301 goto err1; 1302 } 1303 1304 urb = usb_alloc_urb(0, GFP_KERNEL); 1305 if (!urb) { 1306 kfree(buf); 1307 goto err1; 1308 } 1309 1310 INIT_LIST_HEAD(&tp->rx_info[i].list); 1311 tp->rx_info[i].context = tp; 1312 tp->rx_info[i].urb = urb; 1313 tp->rx_info[i].buffer = buf; 1314 tp->rx_info[i].head = rx_agg_align(buf); 1315 } 1316 1317 for (i = 0; i < RTL8152_MAX_TX; i++) { 1318 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1319 if (!buf) 1320 goto err1; 1321 1322 if (buf != tx_agg_align(buf)) { 1323 kfree(buf); 1324 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1325 node); 1326 if (!buf) 1327 goto err1; 1328 } 1329 1330 urb = usb_alloc_urb(0, GFP_KERNEL); 1331 if (!urb) { 1332 kfree(buf); 1333 goto err1; 1334 } 1335 1336 INIT_LIST_HEAD(&tp->tx_info[i].list); 1337 tp->tx_info[i].context = tp; 1338 tp->tx_info[i].urb = urb; 1339 tp->tx_info[i].buffer = buf; 1340 tp->tx_info[i].head = tx_agg_align(buf); 1341 1342 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1343 } 1344 1345 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1346 if (!tp->intr_urb) 1347 goto err1; 1348 1349 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1350 if (!tp->intr_buff) 1351 goto err1; 1352 1353 tp->intr_interval = (int)ep_intr->desc.bInterval; 1354 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1355 tp->intr_buff, INTBUFSIZE, intr_callback, 1356 tp, tp->intr_interval); 1357 1358 return 0; 1359 1360 err1: 1361 free_all_mem(tp); 1362 return -ENOMEM; 1363 } 1364 1365 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1366 { 1367 struct tx_agg *agg = NULL; 1368 unsigned long flags; 1369 1370 if (list_empty(&tp->tx_free)) 1371 return NULL; 1372 1373 spin_lock_irqsave(&tp->tx_lock, flags); 1374 if (!list_empty(&tp->tx_free)) { 1375 struct list_head *cursor; 1376 1377 cursor = tp->tx_free.next; 1378 list_del_init(cursor); 1379 agg = list_entry(cursor, struct tx_agg, list); 1380 } 1381 spin_unlock_irqrestore(&tp->tx_lock, flags); 1382 1383 return agg; 1384 } 1385 1386 /* r8152_csum_workaround() 1387 * The hw limites the value the transport offset. When the offset is out of the 1388 * range, calculate the checksum by sw. 1389 */ 1390 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1391 struct sk_buff_head *list) 1392 { 1393 if (skb_shinfo(skb)->gso_size) { 1394 netdev_features_t features = tp->netdev->features; 1395 struct sk_buff_head seg_list; 1396 struct sk_buff *segs, *nskb; 1397 1398 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1399 segs = skb_gso_segment(skb, features); 1400 if (IS_ERR(segs) || !segs) 1401 goto drop; 1402 1403 __skb_queue_head_init(&seg_list); 1404 1405 do { 1406 nskb = segs; 1407 segs = segs->next; 1408 nskb->next = NULL; 1409 __skb_queue_tail(&seg_list, nskb); 1410 } while (segs); 1411 1412 skb_queue_splice(&seg_list, list); 1413 dev_kfree_skb(skb); 1414 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1415 if (skb_checksum_help(skb) < 0) 1416 goto drop; 1417 1418 __skb_queue_head(list, skb); 1419 } else { 1420 struct net_device_stats *stats; 1421 1422 drop: 1423 stats = &tp->netdev->stats; 1424 stats->tx_dropped++; 1425 dev_kfree_skb(skb); 1426 } 1427 } 1428 1429 /* msdn_giant_send_check() 1430 * According to the document of microsoft, the TCP Pseudo Header excludes the 1431 * packet length for IPv6 TCP large packets. 1432 */ 1433 static int msdn_giant_send_check(struct sk_buff *skb) 1434 { 1435 const struct ipv6hdr *ipv6h; 1436 struct tcphdr *th; 1437 int ret; 1438 1439 ret = skb_cow_head(skb, 0); 1440 if (ret) 1441 return ret; 1442 1443 ipv6h = ipv6_hdr(skb); 1444 th = tcp_hdr(skb); 1445 1446 th->check = 0; 1447 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1448 1449 return ret; 1450 } 1451 1452 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1453 { 1454 if (skb_vlan_tag_present(skb)) { 1455 u32 opts2; 1456 1457 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1458 desc->opts2 |= cpu_to_le32(opts2); 1459 } 1460 } 1461 1462 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1463 { 1464 u32 opts2 = le32_to_cpu(desc->opts2); 1465 1466 if (opts2 & RX_VLAN_TAG) 1467 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1468 swab16(opts2 & 0xffff)); 1469 } 1470 1471 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1472 struct sk_buff *skb, u32 len, u32 transport_offset) 1473 { 1474 u32 mss = skb_shinfo(skb)->gso_size; 1475 u32 opts1, opts2 = 0; 1476 int ret = TX_CSUM_SUCCESS; 1477 1478 WARN_ON_ONCE(len > TX_LEN_MAX); 1479 1480 opts1 = len | TX_FS | TX_LS; 1481 1482 if (mss) { 1483 if (transport_offset > GTTCPHO_MAX) { 1484 netif_warn(tp, tx_err, tp->netdev, 1485 "Invalid transport offset 0x%x for TSO\n", 1486 transport_offset); 1487 ret = TX_CSUM_TSO; 1488 goto unavailable; 1489 } 1490 1491 switch (vlan_get_protocol(skb)) { 1492 case htons(ETH_P_IP): 1493 opts1 |= GTSENDV4; 1494 break; 1495 1496 case htons(ETH_P_IPV6): 1497 if (msdn_giant_send_check(skb)) { 1498 ret = TX_CSUM_TSO; 1499 goto unavailable; 1500 } 1501 opts1 |= GTSENDV6; 1502 break; 1503 1504 default: 1505 WARN_ON_ONCE(1); 1506 break; 1507 } 1508 1509 opts1 |= transport_offset << GTTCPHO_SHIFT; 1510 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1511 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1512 u8 ip_protocol; 1513 1514 if (transport_offset > TCPHO_MAX) { 1515 netif_warn(tp, tx_err, tp->netdev, 1516 "Invalid transport offset 0x%x\n", 1517 transport_offset); 1518 ret = TX_CSUM_NONE; 1519 goto unavailable; 1520 } 1521 1522 switch (vlan_get_protocol(skb)) { 1523 case htons(ETH_P_IP): 1524 opts2 |= IPV4_CS; 1525 ip_protocol = ip_hdr(skb)->protocol; 1526 break; 1527 1528 case htons(ETH_P_IPV6): 1529 opts2 |= IPV6_CS; 1530 ip_protocol = ipv6_hdr(skb)->nexthdr; 1531 break; 1532 1533 default: 1534 ip_protocol = IPPROTO_RAW; 1535 break; 1536 } 1537 1538 if (ip_protocol == IPPROTO_TCP) 1539 opts2 |= TCP_CS; 1540 else if (ip_protocol == IPPROTO_UDP) 1541 opts2 |= UDP_CS; 1542 else 1543 WARN_ON_ONCE(1); 1544 1545 opts2 |= transport_offset << TCPHO_SHIFT; 1546 } 1547 1548 desc->opts2 = cpu_to_le32(opts2); 1549 desc->opts1 = cpu_to_le32(opts1); 1550 1551 unavailable: 1552 return ret; 1553 } 1554 1555 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1556 { 1557 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1558 int remain, ret; 1559 u8 *tx_data; 1560 1561 __skb_queue_head_init(&skb_head); 1562 spin_lock(&tx_queue->lock); 1563 skb_queue_splice_init(tx_queue, &skb_head); 1564 spin_unlock(&tx_queue->lock); 1565 1566 tx_data = agg->head; 1567 agg->skb_num = 0; 1568 agg->skb_len = 0; 1569 remain = agg_buf_sz; 1570 1571 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1572 struct tx_desc *tx_desc; 1573 struct sk_buff *skb; 1574 unsigned int len; 1575 u32 offset; 1576 1577 skb = __skb_dequeue(&skb_head); 1578 if (!skb) 1579 break; 1580 1581 len = skb->len + sizeof(*tx_desc); 1582 1583 if (len > remain) { 1584 __skb_queue_head(&skb_head, skb); 1585 break; 1586 } 1587 1588 tx_data = tx_agg_align(tx_data); 1589 tx_desc = (struct tx_desc *)tx_data; 1590 1591 offset = (u32)skb_transport_offset(skb); 1592 1593 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1594 r8152_csum_workaround(tp, skb, &skb_head); 1595 continue; 1596 } 1597 1598 rtl_tx_vlan_tag(tx_desc, skb); 1599 1600 tx_data += sizeof(*tx_desc); 1601 1602 len = skb->len; 1603 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1604 struct net_device_stats *stats = &tp->netdev->stats; 1605 1606 stats->tx_dropped++; 1607 dev_kfree_skb_any(skb); 1608 tx_data -= sizeof(*tx_desc); 1609 continue; 1610 } 1611 1612 tx_data += len; 1613 agg->skb_len += len; 1614 agg->skb_num++; 1615 1616 dev_kfree_skb_any(skb); 1617 1618 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1619 } 1620 1621 if (!skb_queue_empty(&skb_head)) { 1622 spin_lock(&tx_queue->lock); 1623 skb_queue_splice(&skb_head, tx_queue); 1624 spin_unlock(&tx_queue->lock); 1625 } 1626 1627 netif_tx_lock(tp->netdev); 1628 1629 if (netif_queue_stopped(tp->netdev) && 1630 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1631 netif_wake_queue(tp->netdev); 1632 1633 netif_tx_unlock(tp->netdev); 1634 1635 ret = usb_autopm_get_interface_async(tp->intf); 1636 if (ret < 0) 1637 goto out_tx_fill; 1638 1639 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1640 agg->head, (int)(tx_data - (u8 *)agg->head), 1641 (usb_complete_t)write_bulk_callback, agg); 1642 1643 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1644 if (ret < 0) 1645 usb_autopm_put_interface_async(tp->intf); 1646 1647 out_tx_fill: 1648 return ret; 1649 } 1650 1651 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1652 { 1653 u8 checksum = CHECKSUM_NONE; 1654 u32 opts2, opts3; 1655 1656 if (tp->version == RTL_VER_01) 1657 goto return_result; 1658 1659 opts2 = le32_to_cpu(rx_desc->opts2); 1660 opts3 = le32_to_cpu(rx_desc->opts3); 1661 1662 if (opts2 & RD_IPV4_CS) { 1663 if (opts3 & IPF) 1664 checksum = CHECKSUM_NONE; 1665 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1666 checksum = CHECKSUM_NONE; 1667 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1668 checksum = CHECKSUM_NONE; 1669 else 1670 checksum = CHECKSUM_UNNECESSARY; 1671 } else if (RD_IPV6_CS) { 1672 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1673 checksum = CHECKSUM_UNNECESSARY; 1674 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1675 checksum = CHECKSUM_UNNECESSARY; 1676 } 1677 1678 return_result: 1679 return checksum; 1680 } 1681 1682 static int rx_bottom(struct r8152 *tp, int budget) 1683 { 1684 unsigned long flags; 1685 struct list_head *cursor, *next, rx_queue; 1686 int ret = 0, work_done = 0; 1687 1688 if (!skb_queue_empty(&tp->rx_queue)) { 1689 while (work_done < budget) { 1690 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1691 struct net_device *netdev = tp->netdev; 1692 struct net_device_stats *stats = &netdev->stats; 1693 unsigned int pkt_len; 1694 1695 if (!skb) 1696 break; 1697 1698 pkt_len = skb->len; 1699 napi_gro_receive(&tp->napi, skb); 1700 work_done++; 1701 stats->rx_packets++; 1702 stats->rx_bytes += pkt_len; 1703 } 1704 } 1705 1706 if (list_empty(&tp->rx_done)) 1707 goto out1; 1708 1709 INIT_LIST_HEAD(&rx_queue); 1710 spin_lock_irqsave(&tp->rx_lock, flags); 1711 list_splice_init(&tp->rx_done, &rx_queue); 1712 spin_unlock_irqrestore(&tp->rx_lock, flags); 1713 1714 list_for_each_safe(cursor, next, &rx_queue) { 1715 struct rx_desc *rx_desc; 1716 struct rx_agg *agg; 1717 int len_used = 0; 1718 struct urb *urb; 1719 u8 *rx_data; 1720 1721 list_del_init(cursor); 1722 1723 agg = list_entry(cursor, struct rx_agg, list); 1724 urb = agg->urb; 1725 if (urb->actual_length < ETH_ZLEN) 1726 goto submit; 1727 1728 rx_desc = agg->head; 1729 rx_data = agg->head; 1730 len_used += sizeof(struct rx_desc); 1731 1732 while (urb->actual_length > len_used) { 1733 struct net_device *netdev = tp->netdev; 1734 struct net_device_stats *stats = &netdev->stats; 1735 unsigned int pkt_len; 1736 struct sk_buff *skb; 1737 1738 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1739 if (pkt_len < ETH_ZLEN) 1740 break; 1741 1742 len_used += pkt_len; 1743 if (urb->actual_length < len_used) 1744 break; 1745 1746 pkt_len -= CRC_SIZE; 1747 rx_data += sizeof(struct rx_desc); 1748 1749 skb = napi_alloc_skb(&tp->napi, pkt_len); 1750 if (!skb) { 1751 stats->rx_dropped++; 1752 goto find_next_rx; 1753 } 1754 1755 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1756 memcpy(skb->data, rx_data, pkt_len); 1757 skb_put(skb, pkt_len); 1758 skb->protocol = eth_type_trans(skb, netdev); 1759 rtl_rx_vlan_tag(rx_desc, skb); 1760 if (work_done < budget) { 1761 napi_gro_receive(&tp->napi, skb); 1762 work_done++; 1763 stats->rx_packets++; 1764 stats->rx_bytes += pkt_len; 1765 } else { 1766 __skb_queue_tail(&tp->rx_queue, skb); 1767 } 1768 1769 find_next_rx: 1770 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1771 rx_desc = (struct rx_desc *)rx_data; 1772 len_used = (int)(rx_data - (u8 *)agg->head); 1773 len_used += sizeof(struct rx_desc); 1774 } 1775 1776 submit: 1777 if (!ret) { 1778 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1779 } else { 1780 urb->actual_length = 0; 1781 list_add_tail(&agg->list, next); 1782 } 1783 } 1784 1785 if (!list_empty(&rx_queue)) { 1786 spin_lock_irqsave(&tp->rx_lock, flags); 1787 list_splice_tail(&rx_queue, &tp->rx_done); 1788 spin_unlock_irqrestore(&tp->rx_lock, flags); 1789 } 1790 1791 out1: 1792 return work_done; 1793 } 1794 1795 static void tx_bottom(struct r8152 *tp) 1796 { 1797 int res; 1798 1799 do { 1800 struct tx_agg *agg; 1801 1802 if (skb_queue_empty(&tp->tx_queue)) 1803 break; 1804 1805 agg = r8152_get_tx_agg(tp); 1806 if (!agg) 1807 break; 1808 1809 res = r8152_tx_agg_fill(tp, agg); 1810 if (res) { 1811 struct net_device *netdev = tp->netdev; 1812 1813 if (res == -ENODEV) { 1814 set_bit(RTL8152_UNPLUG, &tp->flags); 1815 netif_device_detach(netdev); 1816 } else { 1817 struct net_device_stats *stats = &netdev->stats; 1818 unsigned long flags; 1819 1820 netif_warn(tp, tx_err, netdev, 1821 "failed tx_urb %d\n", res); 1822 stats->tx_dropped += agg->skb_num; 1823 1824 spin_lock_irqsave(&tp->tx_lock, flags); 1825 list_add_tail(&agg->list, &tp->tx_free); 1826 spin_unlock_irqrestore(&tp->tx_lock, flags); 1827 } 1828 } 1829 } while (res == 0); 1830 } 1831 1832 static void bottom_half(struct r8152 *tp) 1833 { 1834 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1835 return; 1836 1837 if (!test_bit(WORK_ENABLE, &tp->flags)) 1838 return; 1839 1840 /* When link down, the driver would cancel all bulks. */ 1841 /* This avoid the re-submitting bulk */ 1842 if (!netif_carrier_ok(tp->netdev)) 1843 return; 1844 1845 clear_bit(SCHEDULE_NAPI, &tp->flags); 1846 1847 tx_bottom(tp); 1848 } 1849 1850 static int r8152_poll(struct napi_struct *napi, int budget) 1851 { 1852 struct r8152 *tp = container_of(napi, struct r8152, napi); 1853 int work_done; 1854 1855 work_done = rx_bottom(tp, budget); 1856 bottom_half(tp); 1857 1858 if (work_done < budget) { 1859 napi_complete(napi); 1860 if (!list_empty(&tp->rx_done)) 1861 napi_schedule(napi); 1862 } 1863 1864 return work_done; 1865 } 1866 1867 static 1868 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1869 { 1870 int ret; 1871 1872 /* The rx would be stopped, so skip submitting */ 1873 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1874 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1875 return 0; 1876 1877 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1878 agg->head, agg_buf_sz, 1879 (usb_complete_t)read_bulk_callback, agg); 1880 1881 ret = usb_submit_urb(agg->urb, mem_flags); 1882 if (ret == -ENODEV) { 1883 set_bit(RTL8152_UNPLUG, &tp->flags); 1884 netif_device_detach(tp->netdev); 1885 } else if (ret) { 1886 struct urb *urb = agg->urb; 1887 unsigned long flags; 1888 1889 urb->actual_length = 0; 1890 spin_lock_irqsave(&tp->rx_lock, flags); 1891 list_add_tail(&agg->list, &tp->rx_done); 1892 spin_unlock_irqrestore(&tp->rx_lock, flags); 1893 1894 netif_err(tp, rx_err, tp->netdev, 1895 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1896 1897 napi_schedule(&tp->napi); 1898 } 1899 1900 return ret; 1901 } 1902 1903 static void rtl_drop_queued_tx(struct r8152 *tp) 1904 { 1905 struct net_device_stats *stats = &tp->netdev->stats; 1906 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1907 struct sk_buff *skb; 1908 1909 if (skb_queue_empty(tx_queue)) 1910 return; 1911 1912 __skb_queue_head_init(&skb_head); 1913 spin_lock_bh(&tx_queue->lock); 1914 skb_queue_splice_init(tx_queue, &skb_head); 1915 spin_unlock_bh(&tx_queue->lock); 1916 1917 while ((skb = __skb_dequeue(&skb_head))) { 1918 dev_kfree_skb(skb); 1919 stats->tx_dropped++; 1920 } 1921 } 1922 1923 static void rtl8152_tx_timeout(struct net_device *netdev) 1924 { 1925 struct r8152 *tp = netdev_priv(netdev); 1926 1927 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1928 1929 usb_queue_reset_device(tp->intf); 1930 } 1931 1932 static void rtl8152_set_rx_mode(struct net_device *netdev) 1933 { 1934 struct r8152 *tp = netdev_priv(netdev); 1935 1936 if (netif_carrier_ok(netdev)) { 1937 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1938 schedule_delayed_work(&tp->schedule, 0); 1939 } 1940 } 1941 1942 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1943 { 1944 struct r8152 *tp = netdev_priv(netdev); 1945 u32 mc_filter[2]; /* Multicast hash filter */ 1946 __le32 tmp[2]; 1947 u32 ocp_data; 1948 1949 netif_stop_queue(netdev); 1950 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1951 ocp_data &= ~RCR_ACPT_ALL; 1952 ocp_data |= RCR_AB | RCR_APM; 1953 1954 if (netdev->flags & IFF_PROMISC) { 1955 /* Unconditionally log net taps. */ 1956 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1957 ocp_data |= RCR_AM | RCR_AAP; 1958 mc_filter[1] = 0xffffffff; 1959 mc_filter[0] = 0xffffffff; 1960 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1961 (netdev->flags & IFF_ALLMULTI)) { 1962 /* Too many to filter perfectly -- accept all multicasts. */ 1963 ocp_data |= RCR_AM; 1964 mc_filter[1] = 0xffffffff; 1965 mc_filter[0] = 0xffffffff; 1966 } else { 1967 struct netdev_hw_addr *ha; 1968 1969 mc_filter[1] = 0; 1970 mc_filter[0] = 0; 1971 netdev_for_each_mc_addr(ha, netdev) { 1972 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1973 1974 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1975 ocp_data |= RCR_AM; 1976 } 1977 } 1978 1979 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1980 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1981 1982 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1983 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1984 netif_wake_queue(netdev); 1985 } 1986 1987 static netdev_features_t 1988 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 1989 netdev_features_t features) 1990 { 1991 u32 mss = skb_shinfo(skb)->gso_size; 1992 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 1993 int offset = skb_transport_offset(skb); 1994 1995 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 1996 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1997 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 1998 features &= ~NETIF_F_GSO_MASK; 1999 2000 return features; 2001 } 2002 2003 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2004 struct net_device *netdev) 2005 { 2006 struct r8152 *tp = netdev_priv(netdev); 2007 2008 skb_tx_timestamp(skb); 2009 2010 skb_queue_tail(&tp->tx_queue, skb); 2011 2012 if (!list_empty(&tp->tx_free)) { 2013 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2014 set_bit(SCHEDULE_NAPI, &tp->flags); 2015 schedule_delayed_work(&tp->schedule, 0); 2016 } else { 2017 usb_mark_last_busy(tp->udev); 2018 napi_schedule(&tp->napi); 2019 } 2020 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2021 netif_stop_queue(netdev); 2022 } 2023 2024 return NETDEV_TX_OK; 2025 } 2026 2027 static void r8152b_reset_packet_filter(struct r8152 *tp) 2028 { 2029 u32 ocp_data; 2030 2031 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2032 ocp_data &= ~FMC_FCR_MCU_EN; 2033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2034 ocp_data |= FMC_FCR_MCU_EN; 2035 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2036 } 2037 2038 static void rtl8152_nic_reset(struct r8152 *tp) 2039 { 2040 int i; 2041 2042 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2043 2044 for (i = 0; i < 1000; i++) { 2045 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2046 break; 2047 usleep_range(100, 400); 2048 } 2049 } 2050 2051 static void set_tx_qlen(struct r8152 *tp) 2052 { 2053 struct net_device *netdev = tp->netdev; 2054 2055 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2056 sizeof(struct tx_desc)); 2057 } 2058 2059 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2060 { 2061 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2062 } 2063 2064 static void rtl_set_eee_plus(struct r8152 *tp) 2065 { 2066 u32 ocp_data; 2067 u8 speed; 2068 2069 speed = rtl8152_get_speed(tp); 2070 if (speed & _10bps) { 2071 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2072 ocp_data |= EEEP_CR_EEEP_TX; 2073 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2074 } else { 2075 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2076 ocp_data &= ~EEEP_CR_EEEP_TX; 2077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2078 } 2079 } 2080 2081 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2082 { 2083 u32 ocp_data; 2084 2085 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2086 if (enable) 2087 ocp_data |= RXDY_GATED_EN; 2088 else 2089 ocp_data &= ~RXDY_GATED_EN; 2090 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2091 } 2092 2093 static int rtl_start_rx(struct r8152 *tp) 2094 { 2095 int i, ret = 0; 2096 2097 INIT_LIST_HEAD(&tp->rx_done); 2098 for (i = 0; i < RTL8152_MAX_RX; i++) { 2099 INIT_LIST_HEAD(&tp->rx_info[i].list); 2100 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2101 if (ret) 2102 break; 2103 } 2104 2105 if (ret && ++i < RTL8152_MAX_RX) { 2106 struct list_head rx_queue; 2107 unsigned long flags; 2108 2109 INIT_LIST_HEAD(&rx_queue); 2110 2111 do { 2112 struct rx_agg *agg = &tp->rx_info[i++]; 2113 struct urb *urb = agg->urb; 2114 2115 urb->actual_length = 0; 2116 list_add_tail(&agg->list, &rx_queue); 2117 } while (i < RTL8152_MAX_RX); 2118 2119 spin_lock_irqsave(&tp->rx_lock, flags); 2120 list_splice_tail(&rx_queue, &tp->rx_done); 2121 spin_unlock_irqrestore(&tp->rx_lock, flags); 2122 } 2123 2124 return ret; 2125 } 2126 2127 static int rtl_stop_rx(struct r8152 *tp) 2128 { 2129 int i; 2130 2131 for (i = 0; i < RTL8152_MAX_RX; i++) 2132 usb_kill_urb(tp->rx_info[i].urb); 2133 2134 while (!skb_queue_empty(&tp->rx_queue)) 2135 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2136 2137 return 0; 2138 } 2139 2140 static int rtl_enable(struct r8152 *tp) 2141 { 2142 u32 ocp_data; 2143 2144 r8152b_reset_packet_filter(tp); 2145 2146 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2147 ocp_data |= CR_RE | CR_TE; 2148 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2149 2150 rxdy_gated_en(tp, false); 2151 2152 return 0; 2153 } 2154 2155 static int rtl8152_enable(struct r8152 *tp) 2156 { 2157 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2158 return -ENODEV; 2159 2160 set_tx_qlen(tp); 2161 rtl_set_eee_plus(tp); 2162 2163 return rtl_enable(tp); 2164 } 2165 2166 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2167 { 2168 u32 ocp_data = tp->coalesce / 8; 2169 2170 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 2171 } 2172 2173 static void r8153_set_rx_early_size(struct r8152 *tp) 2174 { 2175 u32 mtu = tp->netdev->mtu; 2176 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4; 2177 2178 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 2179 } 2180 2181 static int rtl8153_enable(struct r8152 *tp) 2182 { 2183 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2184 return -ENODEV; 2185 2186 usb_disable_lpm(tp->udev); 2187 set_tx_qlen(tp); 2188 rtl_set_eee_plus(tp); 2189 r8153_set_rx_early_timeout(tp); 2190 r8153_set_rx_early_size(tp); 2191 2192 return rtl_enable(tp); 2193 } 2194 2195 static void rtl_disable(struct r8152 *tp) 2196 { 2197 u32 ocp_data; 2198 int i; 2199 2200 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2201 rtl_drop_queued_tx(tp); 2202 return; 2203 } 2204 2205 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2206 ocp_data &= ~RCR_ACPT_ALL; 2207 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2208 2209 rtl_drop_queued_tx(tp); 2210 2211 for (i = 0; i < RTL8152_MAX_TX; i++) 2212 usb_kill_urb(tp->tx_info[i].urb); 2213 2214 rxdy_gated_en(tp, true); 2215 2216 for (i = 0; i < 1000; i++) { 2217 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2218 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2219 break; 2220 usleep_range(1000, 2000); 2221 } 2222 2223 for (i = 0; i < 1000; i++) { 2224 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2225 break; 2226 usleep_range(1000, 2000); 2227 } 2228 2229 rtl_stop_rx(tp); 2230 2231 rtl8152_nic_reset(tp); 2232 } 2233 2234 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2235 { 2236 u32 ocp_data; 2237 2238 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2239 if (enable) 2240 ocp_data |= POWER_CUT; 2241 else 2242 ocp_data &= ~POWER_CUT; 2243 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2244 2245 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2246 ocp_data &= ~RESUME_INDICATE; 2247 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2248 } 2249 2250 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2251 { 2252 u32 ocp_data; 2253 2254 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2255 if (enable) 2256 ocp_data |= CPCR_RX_VLAN; 2257 else 2258 ocp_data &= ~CPCR_RX_VLAN; 2259 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2260 } 2261 2262 static int rtl8152_set_features(struct net_device *dev, 2263 netdev_features_t features) 2264 { 2265 netdev_features_t changed = features ^ dev->features; 2266 struct r8152 *tp = netdev_priv(dev); 2267 int ret; 2268 2269 ret = usb_autopm_get_interface(tp->intf); 2270 if (ret < 0) 2271 goto out; 2272 2273 mutex_lock(&tp->control); 2274 2275 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2276 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2277 rtl_rx_vlan_en(tp, true); 2278 else 2279 rtl_rx_vlan_en(tp, false); 2280 } 2281 2282 mutex_unlock(&tp->control); 2283 2284 usb_autopm_put_interface(tp->intf); 2285 2286 out: 2287 return ret; 2288 } 2289 2290 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2291 2292 static u32 __rtl_get_wol(struct r8152 *tp) 2293 { 2294 u32 ocp_data; 2295 u32 wolopts = 0; 2296 2297 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2298 if (!(ocp_data & LAN_WAKE_EN)) 2299 return 0; 2300 2301 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2302 if (ocp_data & LINK_ON_WAKE_EN) 2303 wolopts |= WAKE_PHY; 2304 2305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2306 if (ocp_data & UWF_EN) 2307 wolopts |= WAKE_UCAST; 2308 if (ocp_data & BWF_EN) 2309 wolopts |= WAKE_BCAST; 2310 if (ocp_data & MWF_EN) 2311 wolopts |= WAKE_MCAST; 2312 2313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2314 if (ocp_data & MAGIC_EN) 2315 wolopts |= WAKE_MAGIC; 2316 2317 return wolopts; 2318 } 2319 2320 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2321 { 2322 u32 ocp_data; 2323 2324 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2325 2326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2327 ocp_data &= ~LINK_ON_WAKE_EN; 2328 if (wolopts & WAKE_PHY) 2329 ocp_data |= LINK_ON_WAKE_EN; 2330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2331 2332 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2333 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2334 if (wolopts & WAKE_UCAST) 2335 ocp_data |= UWF_EN; 2336 if (wolopts & WAKE_BCAST) 2337 ocp_data |= BWF_EN; 2338 if (wolopts & WAKE_MCAST) 2339 ocp_data |= MWF_EN; 2340 if (wolopts & WAKE_ANY) 2341 ocp_data |= LAN_WAKE_EN; 2342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2343 2344 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2345 2346 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2347 ocp_data &= ~MAGIC_EN; 2348 if (wolopts & WAKE_MAGIC) 2349 ocp_data |= MAGIC_EN; 2350 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2351 2352 if (wolopts & WAKE_ANY) 2353 device_set_wakeup_enable(&tp->udev->dev, true); 2354 else 2355 device_set_wakeup_enable(&tp->udev->dev, false); 2356 } 2357 2358 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2359 { 2360 u8 u1u2[8]; 2361 2362 if (enable) 2363 memset(u1u2, 0xff, sizeof(u1u2)); 2364 else 2365 memset(u1u2, 0x00, sizeof(u1u2)); 2366 2367 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2368 } 2369 2370 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2371 { 2372 u32 ocp_data; 2373 2374 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2375 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 2376 ocp_data |= U2P3_ENABLE; 2377 else 2378 ocp_data &= ~U2P3_ENABLE; 2379 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2380 } 2381 2382 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2383 { 2384 u32 ocp_data; 2385 2386 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2387 if (enable) 2388 ocp_data |= PWR_EN | PHASE2_EN; 2389 else 2390 ocp_data &= ~(PWR_EN | PHASE2_EN); 2391 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2392 2393 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2394 ocp_data &= ~PCUT_STATUS; 2395 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2396 } 2397 2398 static bool rtl_can_wakeup(struct r8152 *tp) 2399 { 2400 struct usb_device *udev = tp->udev; 2401 2402 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2403 } 2404 2405 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2406 { 2407 if (enable) { 2408 u32 ocp_data; 2409 2410 r8153_u1u2en(tp, false); 2411 r8153_u2p3en(tp, false); 2412 2413 __rtl_set_wol(tp, WAKE_ANY); 2414 2415 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2416 2417 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2418 ocp_data |= LINK_OFF_WAKE_EN; 2419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2420 2421 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2422 } else { 2423 __rtl_set_wol(tp, tp->saved_wolopts); 2424 r8153_u2p3en(tp, true); 2425 r8153_u1u2en(tp, true); 2426 } 2427 } 2428 2429 static void rtl_phy_reset(struct r8152 *tp) 2430 { 2431 u16 data; 2432 int i; 2433 2434 data = r8152_mdio_read(tp, MII_BMCR); 2435 2436 /* don't reset again before the previous one complete */ 2437 if (data & BMCR_RESET) 2438 return; 2439 2440 data |= BMCR_RESET; 2441 r8152_mdio_write(tp, MII_BMCR, data); 2442 2443 for (i = 0; i < 50; i++) { 2444 msleep(20); 2445 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2446 break; 2447 } 2448 } 2449 2450 static void r8153_teredo_off(struct r8152 *tp) 2451 { 2452 u32 ocp_data; 2453 2454 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2455 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2457 2458 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2460 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2461 } 2462 2463 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2464 { 2465 if (enable) { 2466 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2467 LINKENA | DIS_SDSAVE); 2468 } else { 2469 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2470 DIS_SDSAVE); 2471 msleep(20); 2472 } 2473 } 2474 2475 static void rtl8152_disable(struct r8152 *tp) 2476 { 2477 r8152_aldps_en(tp, false); 2478 rtl_disable(tp); 2479 r8152_aldps_en(tp, true); 2480 } 2481 2482 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2483 { 2484 u16 data; 2485 2486 data = r8152_mdio_read(tp, MII_BMCR); 2487 if (data & BMCR_PDOWN) { 2488 data &= ~BMCR_PDOWN; 2489 r8152_mdio_write(tp, MII_BMCR, data); 2490 } 2491 2492 set_bit(PHY_RESET, &tp->flags); 2493 } 2494 2495 static void r8152b_exit_oob(struct r8152 *tp) 2496 { 2497 u32 ocp_data; 2498 int i; 2499 2500 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2501 ocp_data &= ~RCR_ACPT_ALL; 2502 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2503 2504 rxdy_gated_en(tp, true); 2505 r8153_teredo_off(tp); 2506 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2507 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2508 2509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2510 ocp_data &= ~NOW_IS_OOB; 2511 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2512 2513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2514 ocp_data &= ~MCU_BORW_EN; 2515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2516 2517 for (i = 0; i < 1000; i++) { 2518 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2519 if (ocp_data & LINK_LIST_READY) 2520 break; 2521 usleep_range(1000, 2000); 2522 } 2523 2524 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2525 ocp_data |= RE_INIT_LL; 2526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2527 2528 for (i = 0; i < 1000; i++) { 2529 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2530 if (ocp_data & LINK_LIST_READY) 2531 break; 2532 usleep_range(1000, 2000); 2533 } 2534 2535 rtl8152_nic_reset(tp); 2536 2537 /* rx share fifo credit full threshold */ 2538 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2539 2540 if (tp->udev->speed == USB_SPEED_FULL || 2541 tp->udev->speed == USB_SPEED_LOW) { 2542 /* rx share fifo credit near full threshold */ 2543 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2544 RXFIFO_THR2_FULL); 2545 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2546 RXFIFO_THR3_FULL); 2547 } else { 2548 /* rx share fifo credit near full threshold */ 2549 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2550 RXFIFO_THR2_HIGH); 2551 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2552 RXFIFO_THR3_HIGH); 2553 } 2554 2555 /* TX share fifo free credit full threshold */ 2556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2557 2558 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2559 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2560 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2561 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2562 2563 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2564 2565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2566 2567 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2568 ocp_data |= TCR0_AUTO_FIFO; 2569 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2570 } 2571 2572 static void r8152b_enter_oob(struct r8152 *tp) 2573 { 2574 u32 ocp_data; 2575 int i; 2576 2577 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2578 ocp_data &= ~NOW_IS_OOB; 2579 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2580 2581 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2582 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2583 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2584 2585 rtl_disable(tp); 2586 2587 for (i = 0; i < 1000; i++) { 2588 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2589 if (ocp_data & LINK_LIST_READY) 2590 break; 2591 usleep_range(1000, 2000); 2592 } 2593 2594 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2595 ocp_data |= RE_INIT_LL; 2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2597 2598 for (i = 0; i < 1000; i++) { 2599 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2600 if (ocp_data & LINK_LIST_READY) 2601 break; 2602 usleep_range(1000, 2000); 2603 } 2604 2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2606 2607 rtl_rx_vlan_en(tp, true); 2608 2609 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2610 ocp_data |= ALDPS_PROXY_MODE; 2611 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2612 2613 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2614 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2615 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2616 2617 rxdy_gated_en(tp, false); 2618 2619 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2620 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2621 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2622 } 2623 2624 static void r8153_hw_phy_cfg(struct r8152 *tp) 2625 { 2626 u32 ocp_data; 2627 u16 data; 2628 2629 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 2630 tp->version == RTL_VER_05) 2631 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2632 2633 data = r8152_mdio_read(tp, MII_BMCR); 2634 if (data & BMCR_PDOWN) { 2635 data &= ~BMCR_PDOWN; 2636 r8152_mdio_write(tp, MII_BMCR, data); 2637 } 2638 2639 if (tp->version == RTL_VER_03) { 2640 data = ocp_reg_read(tp, OCP_EEE_CFG); 2641 data &= ~CTAP_SHORT_EN; 2642 ocp_reg_write(tp, OCP_EEE_CFG, data); 2643 } 2644 2645 data = ocp_reg_read(tp, OCP_POWER_CFG); 2646 data |= EEE_CLKDIV_EN; 2647 ocp_reg_write(tp, OCP_POWER_CFG, data); 2648 2649 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2650 data |= EN_10M_BGOFF; 2651 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2652 data = ocp_reg_read(tp, OCP_POWER_CFG); 2653 data |= EN_10M_PLLOFF; 2654 ocp_reg_write(tp, OCP_POWER_CFG, data); 2655 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2656 2657 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2658 ocp_data |= PFM_PWM_SWITCH; 2659 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2660 2661 /* Enable LPF corner auto tune */ 2662 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2663 2664 /* Adjust 10M Amplitude */ 2665 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2666 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2667 2668 set_bit(PHY_RESET, &tp->flags); 2669 } 2670 2671 static void r8153_first_init(struct r8152 *tp) 2672 { 2673 u32 ocp_data; 2674 int i; 2675 2676 rxdy_gated_en(tp, true); 2677 r8153_teredo_off(tp); 2678 2679 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2680 ocp_data &= ~RCR_ACPT_ALL; 2681 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2682 2683 rtl8152_nic_reset(tp); 2684 2685 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2686 ocp_data &= ~NOW_IS_OOB; 2687 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2688 2689 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2690 ocp_data &= ~MCU_BORW_EN; 2691 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2692 2693 for (i = 0; i < 1000; i++) { 2694 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2695 if (ocp_data & LINK_LIST_READY) 2696 break; 2697 usleep_range(1000, 2000); 2698 } 2699 2700 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2701 ocp_data |= RE_INIT_LL; 2702 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2703 2704 for (i = 0; i < 1000; i++) { 2705 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2706 if (ocp_data & LINK_LIST_READY) 2707 break; 2708 usleep_range(1000, 2000); 2709 } 2710 2711 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2712 2713 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2714 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2715 2716 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2717 ocp_data |= TCR0_AUTO_FIFO; 2718 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2719 2720 rtl8152_nic_reset(tp); 2721 2722 /* rx share fifo credit full threshold */ 2723 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2724 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2725 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2726 /* TX share fifo free credit full threshold */ 2727 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2728 2729 /* rx aggregation */ 2730 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2731 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 2732 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2733 } 2734 2735 static void r8153_enter_oob(struct r8152 *tp) 2736 { 2737 u32 ocp_data; 2738 int i; 2739 2740 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2741 ocp_data &= ~NOW_IS_OOB; 2742 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2743 2744 rtl_disable(tp); 2745 2746 for (i = 0; i < 1000; i++) { 2747 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2748 if (ocp_data & LINK_LIST_READY) 2749 break; 2750 usleep_range(1000, 2000); 2751 } 2752 2753 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2754 ocp_data |= RE_INIT_LL; 2755 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2756 2757 for (i = 0; i < 1000; i++) { 2758 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2759 if (ocp_data & LINK_LIST_READY) 2760 break; 2761 usleep_range(1000, 2000); 2762 } 2763 2764 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2765 2766 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2767 ocp_data &= ~TEREDO_WAKE_MASK; 2768 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2769 2770 rtl_rx_vlan_en(tp, true); 2771 2772 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2773 ocp_data |= ALDPS_PROXY_MODE; 2774 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2775 2776 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2777 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2778 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2779 2780 rxdy_gated_en(tp, false); 2781 2782 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2783 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2784 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2785 } 2786 2787 static void r8153_aldps_en(struct r8152 *tp, bool enable) 2788 { 2789 u16 data; 2790 2791 data = ocp_reg_read(tp, OCP_POWER_CFG); 2792 if (enable) { 2793 data |= EN_ALDPS; 2794 ocp_reg_write(tp, OCP_POWER_CFG, data); 2795 } else { 2796 data &= ~EN_ALDPS; 2797 ocp_reg_write(tp, OCP_POWER_CFG, data); 2798 msleep(20); 2799 } 2800 } 2801 2802 static void rtl8153_disable(struct r8152 *tp) 2803 { 2804 r8153_aldps_en(tp, false); 2805 rtl_disable(tp); 2806 r8153_aldps_en(tp, true); 2807 usb_enable_lpm(tp->udev); 2808 } 2809 2810 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2811 { 2812 u16 bmcr, anar, gbcr; 2813 int ret = 0; 2814 2815 cancel_delayed_work_sync(&tp->schedule); 2816 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2817 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2818 ADVERTISE_100HALF | ADVERTISE_100FULL); 2819 if (tp->mii.supports_gmii) { 2820 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2821 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2822 } else { 2823 gbcr = 0; 2824 } 2825 2826 if (autoneg == AUTONEG_DISABLE) { 2827 if (speed == SPEED_10) { 2828 bmcr = 0; 2829 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2830 } else if (speed == SPEED_100) { 2831 bmcr = BMCR_SPEED100; 2832 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2833 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2834 bmcr = BMCR_SPEED1000; 2835 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2836 } else { 2837 ret = -EINVAL; 2838 goto out; 2839 } 2840 2841 if (duplex == DUPLEX_FULL) 2842 bmcr |= BMCR_FULLDPLX; 2843 } else { 2844 if (speed == SPEED_10) { 2845 if (duplex == DUPLEX_FULL) 2846 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2847 else 2848 anar |= ADVERTISE_10HALF; 2849 } else if (speed == SPEED_100) { 2850 if (duplex == DUPLEX_FULL) { 2851 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2852 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2853 } else { 2854 anar |= ADVERTISE_10HALF; 2855 anar |= ADVERTISE_100HALF; 2856 } 2857 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2858 if (duplex == DUPLEX_FULL) { 2859 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2860 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2861 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2862 } else { 2863 anar |= ADVERTISE_10HALF; 2864 anar |= ADVERTISE_100HALF; 2865 gbcr |= ADVERTISE_1000HALF; 2866 } 2867 } else { 2868 ret = -EINVAL; 2869 goto out; 2870 } 2871 2872 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2873 } 2874 2875 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 2876 bmcr |= BMCR_RESET; 2877 2878 if (tp->mii.supports_gmii) 2879 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2880 2881 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2882 r8152_mdio_write(tp, MII_BMCR, bmcr); 2883 2884 if (bmcr & BMCR_RESET) { 2885 int i; 2886 2887 for (i = 0; i < 50; i++) { 2888 msleep(20); 2889 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2890 break; 2891 } 2892 } 2893 2894 out: 2895 return ret; 2896 } 2897 2898 static void rtl8152_up(struct r8152 *tp) 2899 { 2900 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2901 return; 2902 2903 r8152_aldps_en(tp, false); 2904 r8152b_exit_oob(tp); 2905 r8152_aldps_en(tp, true); 2906 } 2907 2908 static void rtl8152_down(struct r8152 *tp) 2909 { 2910 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2911 rtl_drop_queued_tx(tp); 2912 return; 2913 } 2914 2915 r8152_power_cut_en(tp, false); 2916 r8152_aldps_en(tp, false); 2917 r8152b_enter_oob(tp); 2918 r8152_aldps_en(tp, true); 2919 } 2920 2921 static void rtl8153_up(struct r8152 *tp) 2922 { 2923 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2924 return; 2925 2926 r8153_u1u2en(tp, false); 2927 r8153_aldps_en(tp, false); 2928 r8153_first_init(tp); 2929 r8153_aldps_en(tp, true); 2930 r8153_u2p3en(tp, true); 2931 r8153_u1u2en(tp, true); 2932 usb_enable_lpm(tp->udev); 2933 } 2934 2935 static void rtl8153_down(struct r8152 *tp) 2936 { 2937 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2938 rtl_drop_queued_tx(tp); 2939 return; 2940 } 2941 2942 r8153_u1u2en(tp, false); 2943 r8153_u2p3en(tp, false); 2944 r8153_power_cut_en(tp, false); 2945 r8153_aldps_en(tp, false); 2946 r8153_enter_oob(tp); 2947 r8153_aldps_en(tp, true); 2948 } 2949 2950 static bool rtl8152_in_nway(struct r8152 *tp) 2951 { 2952 u16 nway_state; 2953 2954 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 2955 tp->ocp_base = 0x2000; 2956 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 2957 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 2958 2959 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 2960 if (nway_state & 0xc000) 2961 return false; 2962 else 2963 return true; 2964 } 2965 2966 static bool rtl8153_in_nway(struct r8152 *tp) 2967 { 2968 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 2969 2970 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 2971 return false; 2972 else 2973 return true; 2974 } 2975 2976 static void set_carrier(struct r8152 *tp) 2977 { 2978 struct net_device *netdev = tp->netdev; 2979 u8 speed; 2980 2981 speed = rtl8152_get_speed(tp); 2982 2983 if (speed & LINK_STATUS) { 2984 if (!netif_carrier_ok(netdev)) { 2985 tp->rtl_ops.enable(tp); 2986 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2987 napi_disable(&tp->napi); 2988 netif_carrier_on(netdev); 2989 rtl_start_rx(tp); 2990 napi_enable(&tp->napi); 2991 } 2992 } else { 2993 if (netif_carrier_ok(netdev)) { 2994 netif_carrier_off(netdev); 2995 napi_disable(&tp->napi); 2996 tp->rtl_ops.disable(tp); 2997 napi_enable(&tp->napi); 2998 } 2999 } 3000 } 3001 3002 static void rtl_work_func_t(struct work_struct *work) 3003 { 3004 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3005 3006 /* If the device is unplugged or !netif_running(), the workqueue 3007 * doesn't need to wake the device, and could return directly. 3008 */ 3009 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3010 return; 3011 3012 if (usb_autopm_get_interface(tp->intf) < 0) 3013 return; 3014 3015 if (!test_bit(WORK_ENABLE, &tp->flags)) 3016 goto out1; 3017 3018 if (!mutex_trylock(&tp->control)) { 3019 schedule_delayed_work(&tp->schedule, 0); 3020 goto out1; 3021 } 3022 3023 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3024 set_carrier(tp); 3025 3026 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3027 _rtl8152_set_rx_mode(tp->netdev); 3028 3029 /* don't schedule napi before linking */ 3030 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3031 netif_carrier_ok(tp->netdev)) 3032 napi_schedule(&tp->napi); 3033 3034 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3035 rtl_phy_reset(tp); 3036 3037 mutex_unlock(&tp->control); 3038 3039 out1: 3040 usb_autopm_put_interface(tp->intf); 3041 } 3042 3043 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3044 { 3045 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3046 3047 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3048 return; 3049 3050 if (usb_autopm_get_interface(tp->intf) < 0) 3051 return; 3052 3053 mutex_lock(&tp->control); 3054 3055 tp->rtl_ops.hw_phy_cfg(tp); 3056 3057 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3058 3059 mutex_unlock(&tp->control); 3060 3061 usb_autopm_put_interface(tp->intf); 3062 } 3063 3064 #ifdef CONFIG_PM_SLEEP 3065 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3066 void *data) 3067 { 3068 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3069 3070 switch (action) { 3071 case PM_HIBERNATION_PREPARE: 3072 case PM_SUSPEND_PREPARE: 3073 usb_autopm_get_interface(tp->intf); 3074 break; 3075 3076 case PM_POST_HIBERNATION: 3077 case PM_POST_SUSPEND: 3078 usb_autopm_put_interface(tp->intf); 3079 break; 3080 3081 case PM_POST_RESTORE: 3082 case PM_RESTORE_PREPARE: 3083 default: 3084 break; 3085 } 3086 3087 return NOTIFY_DONE; 3088 } 3089 #endif 3090 3091 static int rtl8152_open(struct net_device *netdev) 3092 { 3093 struct r8152 *tp = netdev_priv(netdev); 3094 int res = 0; 3095 3096 res = alloc_all_mem(tp); 3097 if (res) 3098 goto out; 3099 3100 netif_carrier_off(netdev); 3101 3102 res = usb_autopm_get_interface(tp->intf); 3103 if (res < 0) { 3104 free_all_mem(tp); 3105 goto out; 3106 } 3107 3108 mutex_lock(&tp->control); 3109 3110 tp->rtl_ops.up(tp); 3111 3112 netif_carrier_off(netdev); 3113 netif_start_queue(netdev); 3114 set_bit(WORK_ENABLE, &tp->flags); 3115 3116 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3117 if (res) { 3118 if (res == -ENODEV) 3119 netif_device_detach(tp->netdev); 3120 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3121 res); 3122 free_all_mem(tp); 3123 } else { 3124 napi_enable(&tp->napi); 3125 } 3126 3127 mutex_unlock(&tp->control); 3128 3129 usb_autopm_put_interface(tp->intf); 3130 #ifdef CONFIG_PM_SLEEP 3131 tp->pm_notifier.notifier_call = rtl_notifier; 3132 register_pm_notifier(&tp->pm_notifier); 3133 #endif 3134 3135 out: 3136 return res; 3137 } 3138 3139 static int rtl8152_close(struct net_device *netdev) 3140 { 3141 struct r8152 *tp = netdev_priv(netdev); 3142 int res = 0; 3143 3144 #ifdef CONFIG_PM_SLEEP 3145 unregister_pm_notifier(&tp->pm_notifier); 3146 #endif 3147 napi_disable(&tp->napi); 3148 clear_bit(WORK_ENABLE, &tp->flags); 3149 usb_kill_urb(tp->intr_urb); 3150 cancel_delayed_work_sync(&tp->schedule); 3151 netif_stop_queue(netdev); 3152 3153 res = usb_autopm_get_interface(tp->intf); 3154 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3155 rtl_drop_queued_tx(tp); 3156 rtl_stop_rx(tp); 3157 } else { 3158 mutex_lock(&tp->control); 3159 3160 tp->rtl_ops.down(tp); 3161 3162 mutex_unlock(&tp->control); 3163 3164 usb_autopm_put_interface(tp->intf); 3165 } 3166 3167 free_all_mem(tp); 3168 3169 return res; 3170 } 3171 3172 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3173 { 3174 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3175 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3176 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3177 } 3178 3179 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3180 { 3181 u16 data; 3182 3183 r8152_mmd_indirect(tp, dev, reg); 3184 data = ocp_reg_read(tp, OCP_EEE_DATA); 3185 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3186 3187 return data; 3188 } 3189 3190 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3191 { 3192 r8152_mmd_indirect(tp, dev, reg); 3193 ocp_reg_write(tp, OCP_EEE_DATA, data); 3194 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3195 } 3196 3197 static void r8152_eee_en(struct r8152 *tp, bool enable) 3198 { 3199 u16 config1, config2, config3; 3200 u32 ocp_data; 3201 3202 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3203 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3204 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3205 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3206 3207 if (enable) { 3208 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3209 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3210 config1 |= sd_rise_time(1); 3211 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3212 config3 |= fast_snr(42); 3213 } else { 3214 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3215 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3216 RX_QUIET_EN); 3217 config1 |= sd_rise_time(7); 3218 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3219 config3 |= fast_snr(511); 3220 } 3221 3222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3223 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3224 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3225 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3226 } 3227 3228 static void r8152b_enable_eee(struct r8152 *tp) 3229 { 3230 r8152_eee_en(tp, true); 3231 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3232 } 3233 3234 static void r8153_eee_en(struct r8152 *tp, bool enable) 3235 { 3236 u32 ocp_data; 3237 u16 config; 3238 3239 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3240 config = ocp_reg_read(tp, OCP_EEE_CFG); 3241 3242 if (enable) { 3243 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3244 config |= EEE10_EN; 3245 } else { 3246 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3247 config &= ~EEE10_EN; 3248 } 3249 3250 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3251 ocp_reg_write(tp, OCP_EEE_CFG, config); 3252 } 3253 3254 static void r8153_enable_eee(struct r8152 *tp) 3255 { 3256 r8153_eee_en(tp, true); 3257 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3258 } 3259 3260 static void r8152b_enable_fc(struct r8152 *tp) 3261 { 3262 u16 anar; 3263 3264 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3265 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3266 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3267 } 3268 3269 static void rtl_tally_reset(struct r8152 *tp) 3270 { 3271 u32 ocp_data; 3272 3273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3274 ocp_data |= TALLY_RESET; 3275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3276 } 3277 3278 static void r8152b_init(struct r8152 *tp) 3279 { 3280 u32 ocp_data; 3281 3282 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3283 return; 3284 3285 r8152_aldps_en(tp, false); 3286 3287 if (tp->version == RTL_VER_01) { 3288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3289 ocp_data &= ~LED_MODE_MASK; 3290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3291 } 3292 3293 r8152_power_cut_en(tp, false); 3294 3295 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3296 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3298 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3299 ocp_data &= ~MCU_CLK_RATIO_MASK; 3300 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3302 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3303 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3304 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3305 3306 r8152b_enable_eee(tp); 3307 r8152_aldps_en(tp, true); 3308 r8152b_enable_fc(tp); 3309 rtl_tally_reset(tp); 3310 3311 /* enable rx aggregation */ 3312 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3313 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 3314 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3315 } 3316 3317 static void r8153_init(struct r8152 *tp) 3318 { 3319 u32 ocp_data; 3320 int i; 3321 3322 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3323 return; 3324 3325 r8153_aldps_en(tp, false); 3326 r8153_u1u2en(tp, false); 3327 3328 for (i = 0; i < 500; i++) { 3329 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3330 AUTOLOAD_DONE) 3331 break; 3332 msleep(20); 3333 } 3334 3335 for (i = 0; i < 500; i++) { 3336 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3337 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3338 break; 3339 msleep(20); 3340 } 3341 3342 usb_disable_lpm(tp->udev); 3343 r8153_u2p3en(tp, false); 3344 3345 if (tp->version == RTL_VER_04) { 3346 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3347 ocp_data &= ~pwd_dn_scale_mask; 3348 ocp_data |= pwd_dn_scale(96); 3349 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3350 3351 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3352 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3353 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3354 } else if (tp->version == RTL_VER_05) { 3355 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3356 ocp_data &= ~ECM_ALDPS; 3357 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3358 3359 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3360 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3361 ocp_data &= ~DYNAMIC_BURST; 3362 else 3363 ocp_data |= DYNAMIC_BURST; 3364 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3365 } else if (tp->version == RTL_VER_06) { 3366 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3367 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3368 ocp_data &= ~DYNAMIC_BURST; 3369 else 3370 ocp_data |= DYNAMIC_BURST; 3371 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3372 } 3373 3374 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3375 ocp_data |= EP4_FULL_FC; 3376 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3377 3378 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3379 ocp_data &= ~TIMER11_EN; 3380 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3381 3382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3383 ocp_data &= ~LED_MODE_MASK; 3384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3385 3386 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3387 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 3388 ocp_data |= LPM_TIMER_500MS; 3389 else 3390 ocp_data |= LPM_TIMER_500US; 3391 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3392 3393 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3394 ocp_data &= ~SEN_VAL_MASK; 3395 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3396 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3397 3398 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3399 3400 r8153_power_cut_en(tp, false); 3401 r8153_u1u2en(tp, true); 3402 3403 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3406 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3407 U1U2_SPDWN_EN | L1_SPDWN_EN); 3408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3409 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3410 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3411 EEE_SPDWN_EN); 3412 3413 r8153_enable_eee(tp); 3414 r8153_aldps_en(tp, true); 3415 r8152b_enable_fc(tp); 3416 rtl_tally_reset(tp); 3417 r8153_u2p3en(tp, true); 3418 } 3419 3420 static int rtl8152_pre_reset(struct usb_interface *intf) 3421 { 3422 struct r8152 *tp = usb_get_intfdata(intf); 3423 struct net_device *netdev; 3424 3425 if (!tp) 3426 return 0; 3427 3428 netdev = tp->netdev; 3429 if (!netif_running(netdev)) 3430 return 0; 3431 3432 napi_disable(&tp->napi); 3433 clear_bit(WORK_ENABLE, &tp->flags); 3434 usb_kill_urb(tp->intr_urb); 3435 cancel_delayed_work_sync(&tp->schedule); 3436 if (netif_carrier_ok(netdev)) { 3437 netif_stop_queue(netdev); 3438 mutex_lock(&tp->control); 3439 tp->rtl_ops.disable(tp); 3440 mutex_unlock(&tp->control); 3441 } 3442 3443 return 0; 3444 } 3445 3446 static int rtl8152_post_reset(struct usb_interface *intf) 3447 { 3448 struct r8152 *tp = usb_get_intfdata(intf); 3449 struct net_device *netdev; 3450 3451 if (!tp) 3452 return 0; 3453 3454 netdev = tp->netdev; 3455 if (!netif_running(netdev)) 3456 return 0; 3457 3458 set_bit(WORK_ENABLE, &tp->flags); 3459 if (netif_carrier_ok(netdev)) { 3460 mutex_lock(&tp->control); 3461 tp->rtl_ops.enable(tp); 3462 rtl8152_set_rx_mode(netdev); 3463 mutex_unlock(&tp->control); 3464 netif_wake_queue(netdev); 3465 } 3466 3467 napi_enable(&tp->napi); 3468 3469 return 0; 3470 } 3471 3472 static bool delay_autosuspend(struct r8152 *tp) 3473 { 3474 bool sw_linking = !!netif_carrier_ok(tp->netdev); 3475 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 3476 3477 /* This means a linking change occurs and the driver doesn't detect it, 3478 * yet. If the driver has disabled tx/rx and hw is linking on, the 3479 * device wouldn't wake up by receiving any packet. 3480 */ 3481 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 3482 return true; 3483 3484 /* If the linking down is occurred by nway, the device may miss the 3485 * linking change event. And it wouldn't wake when linking on. 3486 */ 3487 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 3488 return true; 3489 else 3490 return false; 3491 } 3492 3493 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3494 { 3495 struct r8152 *tp = usb_get_intfdata(intf); 3496 struct net_device *netdev = tp->netdev; 3497 int ret = 0; 3498 3499 mutex_lock(&tp->control); 3500 3501 if (PMSG_IS_AUTO(message)) { 3502 if (netif_running(netdev) && delay_autosuspend(tp)) { 3503 ret = -EBUSY; 3504 goto out1; 3505 } 3506 3507 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3508 } else { 3509 netif_device_detach(netdev); 3510 } 3511 3512 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3513 clear_bit(WORK_ENABLE, &tp->flags); 3514 usb_kill_urb(tp->intr_urb); 3515 napi_disable(&tp->napi); 3516 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3517 rtl_stop_rx(tp); 3518 rtl_runtime_suspend_enable(tp, true); 3519 } else { 3520 cancel_delayed_work_sync(&tp->schedule); 3521 tp->rtl_ops.down(tp); 3522 } 3523 napi_enable(&tp->napi); 3524 } 3525 out1: 3526 mutex_unlock(&tp->control); 3527 3528 return ret; 3529 } 3530 3531 static int rtl8152_resume(struct usb_interface *intf) 3532 { 3533 struct r8152 *tp = usb_get_intfdata(intf); 3534 3535 mutex_lock(&tp->control); 3536 3537 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3538 tp->rtl_ops.init(tp); 3539 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 3540 netif_device_attach(tp->netdev); 3541 } 3542 3543 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { 3544 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3545 rtl_runtime_suspend_enable(tp, false); 3546 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3547 napi_disable(&tp->napi); 3548 set_bit(WORK_ENABLE, &tp->flags); 3549 if (netif_carrier_ok(tp->netdev)) 3550 rtl_start_rx(tp); 3551 napi_enable(&tp->napi); 3552 } else { 3553 tp->rtl_ops.up(tp); 3554 netif_carrier_off(tp->netdev); 3555 set_bit(WORK_ENABLE, &tp->flags); 3556 } 3557 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3558 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3559 if (tp->netdev->flags & IFF_UP) 3560 rtl_runtime_suspend_enable(tp, false); 3561 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3562 } 3563 3564 mutex_unlock(&tp->control); 3565 3566 return 0; 3567 } 3568 3569 static int rtl8152_reset_resume(struct usb_interface *intf) 3570 { 3571 struct r8152 *tp = usb_get_intfdata(intf); 3572 3573 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3574 return rtl8152_resume(intf); 3575 } 3576 3577 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3578 { 3579 struct r8152 *tp = netdev_priv(dev); 3580 3581 if (usb_autopm_get_interface(tp->intf) < 0) 3582 return; 3583 3584 if (!rtl_can_wakeup(tp)) { 3585 wol->supported = 0; 3586 wol->wolopts = 0; 3587 } else { 3588 mutex_lock(&tp->control); 3589 wol->supported = WAKE_ANY; 3590 wol->wolopts = __rtl_get_wol(tp); 3591 mutex_unlock(&tp->control); 3592 } 3593 3594 usb_autopm_put_interface(tp->intf); 3595 } 3596 3597 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3598 { 3599 struct r8152 *tp = netdev_priv(dev); 3600 int ret; 3601 3602 if (!rtl_can_wakeup(tp)) 3603 return -EOPNOTSUPP; 3604 3605 ret = usb_autopm_get_interface(tp->intf); 3606 if (ret < 0) 3607 goto out_set_wol; 3608 3609 mutex_lock(&tp->control); 3610 3611 __rtl_set_wol(tp, wol->wolopts); 3612 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3613 3614 mutex_unlock(&tp->control); 3615 3616 usb_autopm_put_interface(tp->intf); 3617 3618 out_set_wol: 3619 return ret; 3620 } 3621 3622 static u32 rtl8152_get_msglevel(struct net_device *dev) 3623 { 3624 struct r8152 *tp = netdev_priv(dev); 3625 3626 return tp->msg_enable; 3627 } 3628 3629 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3630 { 3631 struct r8152 *tp = netdev_priv(dev); 3632 3633 tp->msg_enable = value; 3634 } 3635 3636 static void rtl8152_get_drvinfo(struct net_device *netdev, 3637 struct ethtool_drvinfo *info) 3638 { 3639 struct r8152 *tp = netdev_priv(netdev); 3640 3641 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3642 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3643 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3644 } 3645 3646 static 3647 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3648 { 3649 struct r8152 *tp = netdev_priv(netdev); 3650 int ret; 3651 3652 if (!tp->mii.mdio_read) 3653 return -EOPNOTSUPP; 3654 3655 ret = usb_autopm_get_interface(tp->intf); 3656 if (ret < 0) 3657 goto out; 3658 3659 mutex_lock(&tp->control); 3660 3661 ret = mii_ethtool_gset(&tp->mii, cmd); 3662 3663 mutex_unlock(&tp->control); 3664 3665 usb_autopm_put_interface(tp->intf); 3666 3667 out: 3668 return ret; 3669 } 3670 3671 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3672 { 3673 struct r8152 *tp = netdev_priv(dev); 3674 int ret; 3675 3676 ret = usb_autopm_get_interface(tp->intf); 3677 if (ret < 0) 3678 goto out; 3679 3680 mutex_lock(&tp->control); 3681 3682 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3683 if (!ret) { 3684 tp->autoneg = cmd->autoneg; 3685 tp->speed = cmd->speed; 3686 tp->duplex = cmd->duplex; 3687 } 3688 3689 mutex_unlock(&tp->control); 3690 3691 usb_autopm_put_interface(tp->intf); 3692 3693 out: 3694 return ret; 3695 } 3696 3697 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3698 "tx_packets", 3699 "rx_packets", 3700 "tx_errors", 3701 "rx_errors", 3702 "rx_missed", 3703 "align_errors", 3704 "tx_single_collisions", 3705 "tx_multi_collisions", 3706 "rx_unicast", 3707 "rx_broadcast", 3708 "rx_multicast", 3709 "tx_aborted", 3710 "tx_underrun", 3711 }; 3712 3713 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3714 { 3715 switch (sset) { 3716 case ETH_SS_STATS: 3717 return ARRAY_SIZE(rtl8152_gstrings); 3718 default: 3719 return -EOPNOTSUPP; 3720 } 3721 } 3722 3723 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3724 struct ethtool_stats *stats, u64 *data) 3725 { 3726 struct r8152 *tp = netdev_priv(dev); 3727 struct tally_counter tally; 3728 3729 if (usb_autopm_get_interface(tp->intf) < 0) 3730 return; 3731 3732 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3733 3734 usb_autopm_put_interface(tp->intf); 3735 3736 data[0] = le64_to_cpu(tally.tx_packets); 3737 data[1] = le64_to_cpu(tally.rx_packets); 3738 data[2] = le64_to_cpu(tally.tx_errors); 3739 data[3] = le32_to_cpu(tally.rx_errors); 3740 data[4] = le16_to_cpu(tally.rx_missed); 3741 data[5] = le16_to_cpu(tally.align_errors); 3742 data[6] = le32_to_cpu(tally.tx_one_collision); 3743 data[7] = le32_to_cpu(tally.tx_multi_collision); 3744 data[8] = le64_to_cpu(tally.rx_unicast); 3745 data[9] = le64_to_cpu(tally.rx_broadcast); 3746 data[10] = le32_to_cpu(tally.rx_multicast); 3747 data[11] = le16_to_cpu(tally.tx_aborted); 3748 data[12] = le16_to_cpu(tally.tx_underrun); 3749 } 3750 3751 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3752 { 3753 switch (stringset) { 3754 case ETH_SS_STATS: 3755 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3756 break; 3757 } 3758 } 3759 3760 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3761 { 3762 u32 ocp_data, lp, adv, supported = 0; 3763 u16 val; 3764 3765 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3766 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3767 3768 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3769 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3770 3771 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3772 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3773 3774 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3775 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3776 3777 eee->eee_enabled = !!ocp_data; 3778 eee->eee_active = !!(supported & adv & lp); 3779 eee->supported = supported; 3780 eee->advertised = adv; 3781 eee->lp_advertised = lp; 3782 3783 return 0; 3784 } 3785 3786 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3787 { 3788 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3789 3790 r8152_eee_en(tp, eee->eee_enabled); 3791 3792 if (!eee->eee_enabled) 3793 val = 0; 3794 3795 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3796 3797 return 0; 3798 } 3799 3800 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3801 { 3802 u32 ocp_data, lp, adv, supported = 0; 3803 u16 val; 3804 3805 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3806 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3807 3808 val = ocp_reg_read(tp, OCP_EEE_ADV); 3809 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3810 3811 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3812 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3813 3814 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3815 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3816 3817 eee->eee_enabled = !!ocp_data; 3818 eee->eee_active = !!(supported & adv & lp); 3819 eee->supported = supported; 3820 eee->advertised = adv; 3821 eee->lp_advertised = lp; 3822 3823 return 0; 3824 } 3825 3826 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3827 { 3828 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3829 3830 r8153_eee_en(tp, eee->eee_enabled); 3831 3832 if (!eee->eee_enabled) 3833 val = 0; 3834 3835 ocp_reg_write(tp, OCP_EEE_ADV, val); 3836 3837 return 0; 3838 } 3839 3840 static int 3841 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3842 { 3843 struct r8152 *tp = netdev_priv(net); 3844 int ret; 3845 3846 ret = usb_autopm_get_interface(tp->intf); 3847 if (ret < 0) 3848 goto out; 3849 3850 mutex_lock(&tp->control); 3851 3852 ret = tp->rtl_ops.eee_get(tp, edata); 3853 3854 mutex_unlock(&tp->control); 3855 3856 usb_autopm_put_interface(tp->intf); 3857 3858 out: 3859 return ret; 3860 } 3861 3862 static int 3863 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3864 { 3865 struct r8152 *tp = netdev_priv(net); 3866 int ret; 3867 3868 ret = usb_autopm_get_interface(tp->intf); 3869 if (ret < 0) 3870 goto out; 3871 3872 mutex_lock(&tp->control); 3873 3874 ret = tp->rtl_ops.eee_set(tp, edata); 3875 if (!ret) 3876 ret = mii_nway_restart(&tp->mii); 3877 3878 mutex_unlock(&tp->control); 3879 3880 usb_autopm_put_interface(tp->intf); 3881 3882 out: 3883 return ret; 3884 } 3885 3886 static int rtl8152_nway_reset(struct net_device *dev) 3887 { 3888 struct r8152 *tp = netdev_priv(dev); 3889 int ret; 3890 3891 ret = usb_autopm_get_interface(tp->intf); 3892 if (ret < 0) 3893 goto out; 3894 3895 mutex_lock(&tp->control); 3896 3897 ret = mii_nway_restart(&tp->mii); 3898 3899 mutex_unlock(&tp->control); 3900 3901 usb_autopm_put_interface(tp->intf); 3902 3903 out: 3904 return ret; 3905 } 3906 3907 static int rtl8152_get_coalesce(struct net_device *netdev, 3908 struct ethtool_coalesce *coalesce) 3909 { 3910 struct r8152 *tp = netdev_priv(netdev); 3911 3912 switch (tp->version) { 3913 case RTL_VER_01: 3914 case RTL_VER_02: 3915 return -EOPNOTSUPP; 3916 default: 3917 break; 3918 } 3919 3920 coalesce->rx_coalesce_usecs = tp->coalesce; 3921 3922 return 0; 3923 } 3924 3925 static int rtl8152_set_coalesce(struct net_device *netdev, 3926 struct ethtool_coalesce *coalesce) 3927 { 3928 struct r8152 *tp = netdev_priv(netdev); 3929 int ret; 3930 3931 switch (tp->version) { 3932 case RTL_VER_01: 3933 case RTL_VER_02: 3934 return -EOPNOTSUPP; 3935 default: 3936 break; 3937 } 3938 3939 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 3940 return -EINVAL; 3941 3942 ret = usb_autopm_get_interface(tp->intf); 3943 if (ret < 0) 3944 return ret; 3945 3946 mutex_lock(&tp->control); 3947 3948 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 3949 tp->coalesce = coalesce->rx_coalesce_usecs; 3950 3951 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 3952 r8153_set_rx_early_timeout(tp); 3953 } 3954 3955 mutex_unlock(&tp->control); 3956 3957 usb_autopm_put_interface(tp->intf); 3958 3959 return ret; 3960 } 3961 3962 static struct ethtool_ops ops = { 3963 .get_drvinfo = rtl8152_get_drvinfo, 3964 .get_settings = rtl8152_get_settings, 3965 .set_settings = rtl8152_set_settings, 3966 .get_link = ethtool_op_get_link, 3967 .nway_reset = rtl8152_nway_reset, 3968 .get_msglevel = rtl8152_get_msglevel, 3969 .set_msglevel = rtl8152_set_msglevel, 3970 .get_wol = rtl8152_get_wol, 3971 .set_wol = rtl8152_set_wol, 3972 .get_strings = rtl8152_get_strings, 3973 .get_sset_count = rtl8152_get_sset_count, 3974 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3975 .get_coalesce = rtl8152_get_coalesce, 3976 .set_coalesce = rtl8152_set_coalesce, 3977 .get_eee = rtl_ethtool_get_eee, 3978 .set_eee = rtl_ethtool_set_eee, 3979 }; 3980 3981 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3982 { 3983 struct r8152 *tp = netdev_priv(netdev); 3984 struct mii_ioctl_data *data = if_mii(rq); 3985 int res; 3986 3987 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3988 return -ENODEV; 3989 3990 res = usb_autopm_get_interface(tp->intf); 3991 if (res < 0) 3992 goto out; 3993 3994 switch (cmd) { 3995 case SIOCGMIIPHY: 3996 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3997 break; 3998 3999 case SIOCGMIIREG: 4000 mutex_lock(&tp->control); 4001 data->val_out = r8152_mdio_read(tp, data->reg_num); 4002 mutex_unlock(&tp->control); 4003 break; 4004 4005 case SIOCSMIIREG: 4006 if (!capable(CAP_NET_ADMIN)) { 4007 res = -EPERM; 4008 break; 4009 } 4010 mutex_lock(&tp->control); 4011 r8152_mdio_write(tp, data->reg_num, data->val_in); 4012 mutex_unlock(&tp->control); 4013 break; 4014 4015 default: 4016 res = -EOPNOTSUPP; 4017 } 4018 4019 usb_autopm_put_interface(tp->intf); 4020 4021 out: 4022 return res; 4023 } 4024 4025 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4026 { 4027 struct r8152 *tp = netdev_priv(dev); 4028 int ret; 4029 4030 switch (tp->version) { 4031 case RTL_VER_01: 4032 case RTL_VER_02: 4033 return eth_change_mtu(dev, new_mtu); 4034 default: 4035 break; 4036 } 4037 4038 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 4039 return -EINVAL; 4040 4041 ret = usb_autopm_get_interface(tp->intf); 4042 if (ret < 0) 4043 return ret; 4044 4045 mutex_lock(&tp->control); 4046 4047 dev->mtu = new_mtu; 4048 4049 if (netif_running(dev) && netif_carrier_ok(dev)) 4050 r8153_set_rx_early_size(tp); 4051 4052 mutex_unlock(&tp->control); 4053 4054 usb_autopm_put_interface(tp->intf); 4055 4056 return ret; 4057 } 4058 4059 static const struct net_device_ops rtl8152_netdev_ops = { 4060 .ndo_open = rtl8152_open, 4061 .ndo_stop = rtl8152_close, 4062 .ndo_do_ioctl = rtl8152_ioctl, 4063 .ndo_start_xmit = rtl8152_start_xmit, 4064 .ndo_tx_timeout = rtl8152_tx_timeout, 4065 .ndo_set_features = rtl8152_set_features, 4066 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4067 .ndo_set_mac_address = rtl8152_set_mac_address, 4068 .ndo_change_mtu = rtl8152_change_mtu, 4069 .ndo_validate_addr = eth_validate_addr, 4070 .ndo_features_check = rtl8152_features_check, 4071 }; 4072 4073 static void r8152b_get_version(struct r8152 *tp) 4074 { 4075 u32 ocp_data; 4076 u16 version; 4077 4078 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 4079 version = (u16)(ocp_data & VERSION_MASK); 4080 4081 switch (version) { 4082 case 0x4c00: 4083 tp->version = RTL_VER_01; 4084 break; 4085 case 0x4c10: 4086 tp->version = RTL_VER_02; 4087 break; 4088 case 0x5c00: 4089 tp->version = RTL_VER_03; 4090 tp->mii.supports_gmii = 1; 4091 break; 4092 case 0x5c10: 4093 tp->version = RTL_VER_04; 4094 tp->mii.supports_gmii = 1; 4095 break; 4096 case 0x5c20: 4097 tp->version = RTL_VER_05; 4098 tp->mii.supports_gmii = 1; 4099 break; 4100 case 0x5c30: 4101 tp->version = RTL_VER_06; 4102 tp->mii.supports_gmii = 1; 4103 break; 4104 default: 4105 netif_info(tp, probe, tp->netdev, 4106 "Unknown version 0x%04x\n", version); 4107 break; 4108 } 4109 } 4110 4111 static void rtl8152_unload(struct r8152 *tp) 4112 { 4113 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4114 return; 4115 4116 if (tp->version != RTL_VER_01) 4117 r8152_power_cut_en(tp, true); 4118 } 4119 4120 static void rtl8153_unload(struct r8152 *tp) 4121 { 4122 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4123 return; 4124 4125 r8153_power_cut_en(tp, false); 4126 } 4127 4128 static int rtl_ops_init(struct r8152 *tp) 4129 { 4130 struct rtl_ops *ops = &tp->rtl_ops; 4131 int ret = 0; 4132 4133 switch (tp->version) { 4134 case RTL_VER_01: 4135 case RTL_VER_02: 4136 ops->init = r8152b_init; 4137 ops->enable = rtl8152_enable; 4138 ops->disable = rtl8152_disable; 4139 ops->up = rtl8152_up; 4140 ops->down = rtl8152_down; 4141 ops->unload = rtl8152_unload; 4142 ops->eee_get = r8152_get_eee; 4143 ops->eee_set = r8152_set_eee; 4144 ops->in_nway = rtl8152_in_nway; 4145 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 4146 break; 4147 4148 case RTL_VER_03: 4149 case RTL_VER_04: 4150 case RTL_VER_05: 4151 case RTL_VER_06: 4152 ops->init = r8153_init; 4153 ops->enable = rtl8153_enable; 4154 ops->disable = rtl8153_disable; 4155 ops->up = rtl8153_up; 4156 ops->down = rtl8153_down; 4157 ops->unload = rtl8153_unload; 4158 ops->eee_get = r8153_get_eee; 4159 ops->eee_set = r8153_set_eee; 4160 ops->in_nway = rtl8153_in_nway; 4161 ops->hw_phy_cfg = r8153_hw_phy_cfg; 4162 break; 4163 4164 default: 4165 ret = -ENODEV; 4166 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 4167 break; 4168 } 4169 4170 return ret; 4171 } 4172 4173 static int rtl8152_probe(struct usb_interface *intf, 4174 const struct usb_device_id *id) 4175 { 4176 struct usb_device *udev = interface_to_usbdev(intf); 4177 struct r8152 *tp; 4178 struct net_device *netdev; 4179 int ret; 4180 4181 if (udev->actconfig->desc.bConfigurationValue != 1) { 4182 usb_driver_set_configuration(udev, 1); 4183 return -ENODEV; 4184 } 4185 4186 usb_reset_device(udev); 4187 netdev = alloc_etherdev(sizeof(struct r8152)); 4188 if (!netdev) { 4189 dev_err(&intf->dev, "Out of memory\n"); 4190 return -ENOMEM; 4191 } 4192 4193 SET_NETDEV_DEV(netdev, &intf->dev); 4194 tp = netdev_priv(netdev); 4195 tp->msg_enable = 0x7FFF; 4196 4197 tp->udev = udev; 4198 tp->netdev = netdev; 4199 tp->intf = intf; 4200 4201 r8152b_get_version(tp); 4202 ret = rtl_ops_init(tp); 4203 if (ret) 4204 goto out; 4205 4206 mutex_init(&tp->control); 4207 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 4208 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 4209 4210 netdev->netdev_ops = &rtl8152_netdev_ops; 4211 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 4212 4213 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4214 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 4215 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 4216 NETIF_F_HW_VLAN_CTAG_TX; 4217 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4218 NETIF_F_TSO | NETIF_F_FRAGLIST | 4219 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 4220 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 4221 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 4222 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 4223 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 4224 4225 netdev->ethtool_ops = &ops; 4226 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 4227 4228 tp->mii.dev = netdev; 4229 tp->mii.mdio_read = read_mii_word; 4230 tp->mii.mdio_write = write_mii_word; 4231 tp->mii.phy_id_mask = 0x3f; 4232 tp->mii.reg_num_mask = 0x1f; 4233 tp->mii.phy_id = R8152_PHY_ID; 4234 4235 switch (udev->speed) { 4236 case USB_SPEED_SUPER: 4237 case USB_SPEED_SUPER_PLUS: 4238 tp->coalesce = COALESCE_SUPER; 4239 break; 4240 case USB_SPEED_HIGH: 4241 tp->coalesce = COALESCE_HIGH; 4242 break; 4243 default: 4244 tp->coalesce = COALESCE_SLOW; 4245 break; 4246 } 4247 4248 tp->autoneg = AUTONEG_ENABLE; 4249 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 4250 tp->duplex = DUPLEX_FULL; 4251 4252 intf->needs_remote_wakeup = 1; 4253 4254 tp->rtl_ops.init(tp); 4255 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4256 set_ethernet_addr(tp); 4257 4258 usb_set_intfdata(intf, tp); 4259 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 4260 4261 ret = register_netdev(netdev); 4262 if (ret != 0) { 4263 netif_err(tp, probe, netdev, "couldn't register the device\n"); 4264 goto out1; 4265 } 4266 4267 if (!rtl_can_wakeup(tp)) 4268 __rtl_set_wol(tp, 0); 4269 4270 tp->saved_wolopts = __rtl_get_wol(tp); 4271 if (tp->saved_wolopts) 4272 device_set_wakeup_enable(&udev->dev, true); 4273 else 4274 device_set_wakeup_enable(&udev->dev, false); 4275 4276 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 4277 4278 return 0; 4279 4280 out1: 4281 netif_napi_del(&tp->napi); 4282 usb_set_intfdata(intf, NULL); 4283 out: 4284 free_netdev(netdev); 4285 return ret; 4286 } 4287 4288 static void rtl8152_disconnect(struct usb_interface *intf) 4289 { 4290 struct r8152 *tp = usb_get_intfdata(intf); 4291 4292 usb_set_intfdata(intf, NULL); 4293 if (tp) { 4294 struct usb_device *udev = tp->udev; 4295 4296 if (udev->state == USB_STATE_NOTATTACHED) 4297 set_bit(RTL8152_UNPLUG, &tp->flags); 4298 4299 netif_napi_del(&tp->napi); 4300 unregister_netdev(tp->netdev); 4301 cancel_delayed_work_sync(&tp->hw_phy_work); 4302 tp->rtl_ops.unload(tp); 4303 free_netdev(tp->netdev); 4304 } 4305 } 4306 4307 #define REALTEK_USB_DEVICE(vend, prod) \ 4308 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4309 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4310 .idVendor = (vend), \ 4311 .idProduct = (prod), \ 4312 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4313 }, \ 4314 { \ 4315 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4316 USB_DEVICE_ID_MATCH_DEVICE, \ 4317 .idVendor = (vend), \ 4318 .idProduct = (prod), \ 4319 .bInterfaceClass = USB_CLASS_COMM, \ 4320 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4321 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4322 4323 /* table of devices that work with this driver */ 4324 static struct usb_device_id rtl8152_table[] = { 4325 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4326 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4327 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4328 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4329 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 4330 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 4331 {} 4332 }; 4333 4334 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4335 4336 static struct usb_driver rtl8152_driver = { 4337 .name = MODULENAME, 4338 .id_table = rtl8152_table, 4339 .probe = rtl8152_probe, 4340 .disconnect = rtl8152_disconnect, 4341 .suspend = rtl8152_suspend, 4342 .resume = rtl8152_resume, 4343 .reset_resume = rtl8152_reset_resume, 4344 .pre_reset = rtl8152_pre_reset, 4345 .post_reset = rtl8152_post_reset, 4346 .supports_autosuspend = 1, 4347 .disable_hub_initiated_lpm = 1, 4348 }; 4349 4350 module_usb_driver(rtl8152_driver); 4351 4352 MODULE_AUTHOR(DRIVER_AUTHOR); 4353 MODULE_DESCRIPTION(DRIVER_DESC); 4354 MODULE_LICENSE("GPL"); 4355