1 /* 2 * ASIX AX8817X based USB 2.0 Ethernet Devices 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 6 * Copyright (c) 2002-2003 TiVo Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include "asix.h" 24 25 #define PHY_MODE_MARVELL 0x0000 26 #define MII_MARVELL_LED_CTRL 0x0018 27 #define MII_MARVELL_STATUS 0x001b 28 #define MII_MARVELL_CTRL 0x0014 29 30 #define MARVELL_LED_MANUAL 0x0019 31 32 #define MARVELL_STATUS_HWCFG 0x0004 33 34 #define MARVELL_CTRL_TXDELAY 0x0002 35 #define MARVELL_CTRL_RXDELAY 0x0080 36 37 #define PHY_MODE_RTL8211CL 0x000C 38 39 struct ax88172_int_data { 40 __le16 res1; 41 u8 link; 42 __le16 res2; 43 u8 status; 44 __le16 res3; 45 } __packed; 46 47 static void asix_status(struct usbnet *dev, struct urb *urb) 48 { 49 struct ax88172_int_data *event; 50 int link; 51 52 if (urb->actual_length < 8) 53 return; 54 55 event = urb->transfer_buffer; 56 link = event->link & 0x01; 57 if (netif_carrier_ok(dev->net) != link) { 58 if (link) { 59 netif_carrier_on(dev->net); 60 usbnet_defer_kevent (dev, EVENT_LINK_RESET ); 61 } else 62 netif_carrier_off(dev->net); 63 netdev_dbg(dev->net, "Link Status is: %d\n", link); 64 } 65 } 66 67 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 68 static u32 asix_get_phyid(struct usbnet *dev) 69 { 70 int phy_reg; 71 u32 phy_id; 72 int i; 73 74 /* Poll for the rare case the FW or phy isn't ready yet. */ 75 for (i = 0; i < 100; i++) { 76 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 77 if (phy_reg != 0 && phy_reg != 0xFFFF) 78 break; 79 mdelay(1); 80 } 81 82 if (phy_reg <= 0 || phy_reg == 0xFFFF) 83 return 0; 84 85 phy_id = (phy_reg & 0xffff) << 16; 86 87 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 88 if (phy_reg < 0) 89 return 0; 90 91 phy_id |= (phy_reg & 0xffff); 92 93 return phy_id; 94 } 95 96 static u32 asix_get_link(struct net_device *net) 97 { 98 struct usbnet *dev = netdev_priv(net); 99 100 return mii_link_ok(&dev->mii); 101 } 102 103 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 104 { 105 struct usbnet *dev = netdev_priv(net); 106 107 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 108 } 109 110 /* We need to override some ethtool_ops so we require our 111 own structure so we don't interfere with other usbnet 112 devices that may be connected at the same time. */ 113 static const struct ethtool_ops ax88172_ethtool_ops = { 114 .get_drvinfo = asix_get_drvinfo, 115 .get_link = asix_get_link, 116 .get_msglevel = usbnet_get_msglevel, 117 .set_msglevel = usbnet_set_msglevel, 118 .get_wol = asix_get_wol, 119 .set_wol = asix_set_wol, 120 .get_eeprom_len = asix_get_eeprom_len, 121 .get_eeprom = asix_get_eeprom, 122 .set_eeprom = asix_set_eeprom, 123 .get_settings = usbnet_get_settings, 124 .set_settings = usbnet_set_settings, 125 .nway_reset = usbnet_nway_reset, 126 }; 127 128 static void ax88172_set_multicast(struct net_device *net) 129 { 130 struct usbnet *dev = netdev_priv(net); 131 struct asix_data *data = (struct asix_data *)&dev->data; 132 u8 rx_ctl = 0x8c; 133 134 if (net->flags & IFF_PROMISC) { 135 rx_ctl |= 0x01; 136 } else if (net->flags & IFF_ALLMULTI || 137 netdev_mc_count(net) > AX_MAX_MCAST) { 138 rx_ctl |= 0x02; 139 } else if (netdev_mc_empty(net)) { 140 /* just broadcast and directed */ 141 } else { 142 /* We use the 20 byte dev->data 143 * for our 8 byte filter buffer 144 * to avoid allocating memory that 145 * is tricky to free later */ 146 struct netdev_hw_addr *ha; 147 u32 crc_bits; 148 149 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 150 151 /* Build the multicast hash filter. */ 152 netdev_for_each_mc_addr(ha, net) { 153 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 154 data->multi_filter[crc_bits >> 3] |= 155 1 << (crc_bits & 7); 156 } 157 158 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 159 AX_MCAST_FILTER_SIZE, data->multi_filter); 160 161 rx_ctl |= 0x10; 162 } 163 164 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 165 } 166 167 static int ax88172_link_reset(struct usbnet *dev) 168 { 169 u8 mode; 170 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 171 172 mii_check_media(&dev->mii, 1, 1); 173 mii_ethtool_gset(&dev->mii, &ecmd); 174 mode = AX88172_MEDIUM_DEFAULT; 175 176 if (ecmd.duplex != DUPLEX_FULL) 177 mode |= ~AX88172_MEDIUM_FD; 178 179 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 180 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 181 182 asix_write_medium_mode(dev, mode); 183 184 return 0; 185 } 186 187 static const struct net_device_ops ax88172_netdev_ops = { 188 .ndo_open = usbnet_open, 189 .ndo_stop = usbnet_stop, 190 .ndo_start_xmit = usbnet_start_xmit, 191 .ndo_tx_timeout = usbnet_tx_timeout, 192 .ndo_change_mtu = usbnet_change_mtu, 193 .ndo_set_mac_address = eth_mac_addr, 194 .ndo_validate_addr = eth_validate_addr, 195 .ndo_do_ioctl = asix_ioctl, 196 .ndo_set_rx_mode = ax88172_set_multicast, 197 }; 198 199 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 200 { 201 int ret = 0; 202 u8 buf[ETH_ALEN]; 203 int i; 204 unsigned long gpio_bits = dev->driver_info->data; 205 206 usbnet_get_endpoints(dev,intf); 207 208 /* Toggle the GPIOs in a manufacturer/model specific way */ 209 for (i = 2; i >= 0; i--) { 210 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 211 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL); 212 if (ret < 0) 213 goto out; 214 msleep(5); 215 } 216 217 ret = asix_write_rx_ctl(dev, 0x80); 218 if (ret < 0) 219 goto out; 220 221 /* Get the MAC address */ 222 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 223 if (ret < 0) { 224 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 225 ret); 226 goto out; 227 } 228 memcpy(dev->net->dev_addr, buf, ETH_ALEN); 229 230 /* Initialize MII structure */ 231 dev->mii.dev = dev->net; 232 dev->mii.mdio_read = asix_mdio_read; 233 dev->mii.mdio_write = asix_mdio_write; 234 dev->mii.phy_id_mask = 0x3f; 235 dev->mii.reg_num_mask = 0x1f; 236 dev->mii.phy_id = asix_get_phy_addr(dev); 237 238 dev->net->netdev_ops = &ax88172_netdev_ops; 239 dev->net->ethtool_ops = &ax88172_ethtool_ops; 240 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 241 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 242 243 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 244 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 245 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 246 mii_nway_restart(&dev->mii); 247 248 return 0; 249 250 out: 251 return ret; 252 } 253 254 static const struct ethtool_ops ax88772_ethtool_ops = { 255 .get_drvinfo = asix_get_drvinfo, 256 .get_link = asix_get_link, 257 .get_msglevel = usbnet_get_msglevel, 258 .set_msglevel = usbnet_set_msglevel, 259 .get_wol = asix_get_wol, 260 .set_wol = asix_set_wol, 261 .get_eeprom_len = asix_get_eeprom_len, 262 .get_eeprom = asix_get_eeprom, 263 .set_eeprom = asix_set_eeprom, 264 .get_settings = usbnet_get_settings, 265 .set_settings = usbnet_set_settings, 266 .nway_reset = usbnet_nway_reset, 267 }; 268 269 static int ax88772_link_reset(struct usbnet *dev) 270 { 271 u16 mode; 272 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 273 274 mii_check_media(&dev->mii, 1, 1); 275 mii_ethtool_gset(&dev->mii, &ecmd); 276 mode = AX88772_MEDIUM_DEFAULT; 277 278 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 279 mode &= ~AX_MEDIUM_PS; 280 281 if (ecmd.duplex != DUPLEX_FULL) 282 mode &= ~AX_MEDIUM_FD; 283 284 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 285 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 286 287 asix_write_medium_mode(dev, mode); 288 289 return 0; 290 } 291 292 static int ax88772_reset(struct usbnet *dev) 293 { 294 struct asix_data *data = (struct asix_data *)&dev->data; 295 int ret, embd_phy; 296 u16 rx_ctl; 297 298 ret = asix_write_gpio(dev, 299 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); 300 if (ret < 0) 301 goto out; 302 303 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 304 305 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 306 if (ret < 0) { 307 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 308 goto out; 309 } 310 311 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); 312 if (ret < 0) 313 goto out; 314 315 msleep(150); 316 317 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); 318 if (ret < 0) 319 goto out; 320 321 msleep(150); 322 323 if (embd_phy) { 324 ret = asix_sw_reset(dev, AX_SWRESET_IPRL); 325 if (ret < 0) 326 goto out; 327 } else { 328 ret = asix_sw_reset(dev, AX_SWRESET_PRTE); 329 if (ret < 0) 330 goto out; 331 } 332 333 msleep(150); 334 rx_ctl = asix_read_rx_ctl(dev); 335 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl); 336 ret = asix_write_rx_ctl(dev, 0x0000); 337 if (ret < 0) 338 goto out; 339 340 rx_ctl = asix_read_rx_ctl(dev); 341 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 342 343 ret = asix_sw_reset(dev, AX_SWRESET_PRL); 344 if (ret < 0) 345 goto out; 346 347 msleep(150); 348 349 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL); 350 if (ret < 0) 351 goto out; 352 353 msleep(150); 354 355 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 356 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 357 ADVERTISE_ALL | ADVERTISE_CSMA); 358 mii_nway_restart(&dev->mii); 359 360 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT); 361 if (ret < 0) 362 goto out; 363 364 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 365 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 366 AX88772_IPG2_DEFAULT, 0, NULL); 367 if (ret < 0) { 368 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 369 goto out; 370 } 371 372 /* Rewrite MAC address */ 373 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 374 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 375 data->mac_addr); 376 if (ret < 0) 377 goto out; 378 379 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 380 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); 381 if (ret < 0) 382 goto out; 383 384 rx_ctl = asix_read_rx_ctl(dev); 385 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 386 rx_ctl); 387 388 rx_ctl = asix_read_medium_status(dev); 389 netdev_dbg(dev->net, 390 "Medium Status is 0x%04x after all initializations\n", 391 rx_ctl); 392 393 return 0; 394 395 out: 396 return ret; 397 398 } 399 400 static const struct net_device_ops ax88772_netdev_ops = { 401 .ndo_open = usbnet_open, 402 .ndo_stop = usbnet_stop, 403 .ndo_start_xmit = usbnet_start_xmit, 404 .ndo_tx_timeout = usbnet_tx_timeout, 405 .ndo_change_mtu = usbnet_change_mtu, 406 .ndo_set_mac_address = asix_set_mac_address, 407 .ndo_validate_addr = eth_validate_addr, 408 .ndo_do_ioctl = asix_ioctl, 409 .ndo_set_rx_mode = asix_set_multicast, 410 }; 411 412 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 413 { 414 int ret, embd_phy; 415 u8 buf[ETH_ALEN]; 416 u32 phyid; 417 418 usbnet_get_endpoints(dev,intf); 419 420 /* Get the MAC address */ 421 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 422 if (ret < 0) { 423 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 424 return ret; 425 } 426 memcpy(dev->net->dev_addr, buf, ETH_ALEN); 427 428 /* Initialize MII structure */ 429 dev->mii.dev = dev->net; 430 dev->mii.mdio_read = asix_mdio_read; 431 dev->mii.mdio_write = asix_mdio_write; 432 dev->mii.phy_id_mask = 0x1f; 433 dev->mii.reg_num_mask = 0x1f; 434 dev->mii.phy_id = asix_get_phy_addr(dev); 435 436 dev->net->netdev_ops = &ax88772_netdev_ops; 437 dev->net->ethtool_ops = &ax88772_ethtool_ops; 438 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 439 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 440 441 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 442 443 /* Reset the PHY to normal operation mode */ 444 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 445 if (ret < 0) { 446 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 447 return ret; 448 } 449 450 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); 451 if (ret < 0) 452 return ret; 453 454 msleep(150); 455 456 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); 457 if (ret < 0) 458 return ret; 459 460 msleep(150); 461 462 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE); 463 464 /* Read PHYID register *AFTER* the PHY was reset properly */ 465 phyid = asix_get_phyid(dev); 466 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 467 468 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 469 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 470 /* hard_mtu is still the default - the device does not support 471 jumbo eth frames */ 472 dev->rx_urb_size = 2048; 473 } 474 475 return 0; 476 } 477 478 static const struct ethtool_ops ax88178_ethtool_ops = { 479 .get_drvinfo = asix_get_drvinfo, 480 .get_link = asix_get_link, 481 .get_msglevel = usbnet_get_msglevel, 482 .set_msglevel = usbnet_set_msglevel, 483 .get_wol = asix_get_wol, 484 .set_wol = asix_set_wol, 485 .get_eeprom_len = asix_get_eeprom_len, 486 .get_eeprom = asix_get_eeprom, 487 .set_eeprom = asix_set_eeprom, 488 .get_settings = usbnet_get_settings, 489 .set_settings = usbnet_set_settings, 490 .nway_reset = usbnet_nway_reset, 491 }; 492 493 static int marvell_phy_init(struct usbnet *dev) 494 { 495 struct asix_data *data = (struct asix_data *)&dev->data; 496 u16 reg; 497 498 netdev_dbg(dev->net, "marvell_phy_init()\n"); 499 500 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 501 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 502 503 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 504 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 505 506 if (data->ledmode) { 507 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 508 MII_MARVELL_LED_CTRL); 509 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 510 511 reg &= 0xf8ff; 512 reg |= (1 + 0x0100); 513 asix_mdio_write(dev->net, dev->mii.phy_id, 514 MII_MARVELL_LED_CTRL, reg); 515 516 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 517 MII_MARVELL_LED_CTRL); 518 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 519 reg &= 0xfc0f; 520 } 521 522 return 0; 523 } 524 525 static int rtl8211cl_phy_init(struct usbnet *dev) 526 { 527 struct asix_data *data = (struct asix_data *)&dev->data; 528 529 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 530 531 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 532 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 533 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 534 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 535 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 536 537 if (data->ledmode == 12) { 538 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 539 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 540 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 541 } 542 543 return 0; 544 } 545 546 static int marvell_led_status(struct usbnet *dev, u16 speed) 547 { 548 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 549 550 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 551 552 /* Clear out the center LED bits - 0x03F0 */ 553 reg &= 0xfc0f; 554 555 switch (speed) { 556 case SPEED_1000: 557 reg |= 0x03e0; 558 break; 559 case SPEED_100: 560 reg |= 0x03b0; 561 break; 562 default: 563 reg |= 0x02f0; 564 } 565 566 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 567 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 568 569 return 0; 570 } 571 572 static int ax88178_reset(struct usbnet *dev) 573 { 574 struct asix_data *data = (struct asix_data *)&dev->data; 575 int ret; 576 __le16 eeprom; 577 u8 status; 578 int gpio0 = 0; 579 u32 phyid; 580 581 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); 582 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 583 584 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); 585 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); 586 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); 587 588 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 589 590 if (eeprom == cpu_to_le16(0xffff)) { 591 data->phymode = PHY_MODE_MARVELL; 592 data->ledmode = 0; 593 gpio0 = 1; 594 } else { 595 data->phymode = le16_to_cpu(eeprom) & 0x7F; 596 data->ledmode = le16_to_cpu(eeprom) >> 8; 597 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 598 } 599 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 600 601 /* Power up external GigaPHY through AX88178 GPIO pin */ 602 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); 603 if ((le16_to_cpu(eeprom) >> 8) != 1) { 604 asix_write_gpio(dev, 0x003c, 30); 605 asix_write_gpio(dev, 0x001c, 300); 606 asix_write_gpio(dev, 0x003c, 30); 607 } else { 608 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 609 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); 610 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); 611 } 612 613 /* Read PHYID register *AFTER* powering up PHY */ 614 phyid = asix_get_phyid(dev); 615 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 616 617 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 618 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL); 619 620 asix_sw_reset(dev, 0); 621 msleep(150); 622 623 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); 624 msleep(150); 625 626 asix_write_rx_ctl(dev, 0); 627 628 if (data->phymode == PHY_MODE_MARVELL) { 629 marvell_phy_init(dev); 630 msleep(60); 631 } else if (data->phymode == PHY_MODE_RTL8211CL) 632 rtl8211cl_phy_init(dev); 633 634 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, 635 BMCR_RESET | BMCR_ANENABLE); 636 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 637 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 638 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 639 ADVERTISE_1000FULL); 640 641 mii_nway_restart(&dev->mii); 642 643 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT); 644 if (ret < 0) 645 return ret; 646 647 /* Rewrite MAC address */ 648 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 649 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 650 data->mac_addr); 651 if (ret < 0) 652 return ret; 653 654 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); 655 if (ret < 0) 656 return ret; 657 658 return 0; 659 } 660 661 static int ax88178_link_reset(struct usbnet *dev) 662 { 663 u16 mode; 664 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 665 struct asix_data *data = (struct asix_data *)&dev->data; 666 u32 speed; 667 668 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 669 670 mii_check_media(&dev->mii, 1, 1); 671 mii_ethtool_gset(&dev->mii, &ecmd); 672 mode = AX88178_MEDIUM_DEFAULT; 673 speed = ethtool_cmd_speed(&ecmd); 674 675 if (speed == SPEED_1000) 676 mode |= AX_MEDIUM_GM; 677 else if (speed == SPEED_100) 678 mode |= AX_MEDIUM_PS; 679 else 680 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 681 682 mode |= AX_MEDIUM_ENCK; 683 684 if (ecmd.duplex == DUPLEX_FULL) 685 mode |= AX_MEDIUM_FD; 686 else 687 mode &= ~AX_MEDIUM_FD; 688 689 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 690 speed, ecmd.duplex, mode); 691 692 asix_write_medium_mode(dev, mode); 693 694 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 695 marvell_led_status(dev, speed); 696 697 return 0; 698 } 699 700 static void ax88178_set_mfb(struct usbnet *dev) 701 { 702 u16 mfb = AX_RX_CTL_MFB_16384; 703 u16 rxctl; 704 u16 medium; 705 int old_rx_urb_size = dev->rx_urb_size; 706 707 if (dev->hard_mtu < 2048) { 708 dev->rx_urb_size = 2048; 709 mfb = AX_RX_CTL_MFB_2048; 710 } else if (dev->hard_mtu < 4096) { 711 dev->rx_urb_size = 4096; 712 mfb = AX_RX_CTL_MFB_4096; 713 } else if (dev->hard_mtu < 8192) { 714 dev->rx_urb_size = 8192; 715 mfb = AX_RX_CTL_MFB_8192; 716 } else if (dev->hard_mtu < 16384) { 717 dev->rx_urb_size = 16384; 718 mfb = AX_RX_CTL_MFB_16384; 719 } 720 721 rxctl = asix_read_rx_ctl(dev); 722 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); 723 724 medium = asix_read_medium_status(dev); 725 if (dev->net->mtu > 1500) 726 medium |= AX_MEDIUM_JFE; 727 else 728 medium &= ~AX_MEDIUM_JFE; 729 asix_write_medium_mode(dev, medium); 730 731 if (dev->rx_urb_size > old_rx_urb_size) 732 usbnet_unlink_rx_urbs(dev); 733 } 734 735 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 736 { 737 struct usbnet *dev = netdev_priv(net); 738 int ll_mtu = new_mtu + net->hard_header_len + 4; 739 740 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 741 742 if (new_mtu <= 0 || ll_mtu > 16384) 743 return -EINVAL; 744 745 if ((ll_mtu % dev->maxpacket) == 0) 746 return -EDOM; 747 748 net->mtu = new_mtu; 749 dev->hard_mtu = net->mtu + net->hard_header_len; 750 ax88178_set_mfb(dev); 751 752 return 0; 753 } 754 755 static const struct net_device_ops ax88178_netdev_ops = { 756 .ndo_open = usbnet_open, 757 .ndo_stop = usbnet_stop, 758 .ndo_start_xmit = usbnet_start_xmit, 759 .ndo_tx_timeout = usbnet_tx_timeout, 760 .ndo_set_mac_address = asix_set_mac_address, 761 .ndo_validate_addr = eth_validate_addr, 762 .ndo_set_rx_mode = asix_set_multicast, 763 .ndo_do_ioctl = asix_ioctl, 764 .ndo_change_mtu = ax88178_change_mtu, 765 }; 766 767 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 768 { 769 int ret; 770 u8 buf[ETH_ALEN]; 771 772 usbnet_get_endpoints(dev,intf); 773 774 /* Get the MAC address */ 775 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 776 if (ret < 0) { 777 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 778 return ret; 779 } 780 memcpy(dev->net->dev_addr, buf, ETH_ALEN); 781 782 /* Initialize MII structure */ 783 dev->mii.dev = dev->net; 784 dev->mii.mdio_read = asix_mdio_read; 785 dev->mii.mdio_write = asix_mdio_write; 786 dev->mii.phy_id_mask = 0x1f; 787 dev->mii.reg_num_mask = 0xff; 788 dev->mii.supports_gmii = 1; 789 dev->mii.phy_id = asix_get_phy_addr(dev); 790 791 dev->net->netdev_ops = &ax88178_netdev_ops; 792 dev->net->ethtool_ops = &ax88178_ethtool_ops; 793 794 /* Blink LEDS so users know driver saw dongle */ 795 asix_sw_reset(dev, 0); 796 msleep(150); 797 798 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); 799 msleep(150); 800 801 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 802 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 803 /* hard_mtu is still the default - the device does not support 804 jumbo eth frames */ 805 dev->rx_urb_size = 2048; 806 } 807 808 return 0; 809 } 810 811 static const struct driver_info ax8817x_info = { 812 .description = "ASIX AX8817x USB 2.0 Ethernet", 813 .bind = ax88172_bind, 814 .status = asix_status, 815 .link_reset = ax88172_link_reset, 816 .reset = ax88172_link_reset, 817 .flags = FLAG_ETHER | FLAG_LINK_INTR, 818 .data = 0x00130103, 819 }; 820 821 static const struct driver_info dlink_dub_e100_info = { 822 .description = "DLink DUB-E100 USB Ethernet", 823 .bind = ax88172_bind, 824 .status = asix_status, 825 .link_reset = ax88172_link_reset, 826 .reset = ax88172_link_reset, 827 .flags = FLAG_ETHER | FLAG_LINK_INTR, 828 .data = 0x009f9d9f, 829 }; 830 831 static const struct driver_info netgear_fa120_info = { 832 .description = "Netgear FA-120 USB Ethernet", 833 .bind = ax88172_bind, 834 .status = asix_status, 835 .link_reset = ax88172_link_reset, 836 .reset = ax88172_link_reset, 837 .flags = FLAG_ETHER | FLAG_LINK_INTR, 838 .data = 0x00130103, 839 }; 840 841 static const struct driver_info hawking_uf200_info = { 842 .description = "Hawking UF200 USB Ethernet", 843 .bind = ax88172_bind, 844 .status = asix_status, 845 .link_reset = ax88172_link_reset, 846 .reset = ax88172_link_reset, 847 .flags = FLAG_ETHER | FLAG_LINK_INTR, 848 .data = 0x001f1d1f, 849 }; 850 851 static const struct driver_info ax88772_info = { 852 .description = "ASIX AX88772 USB 2.0 Ethernet", 853 .bind = ax88772_bind, 854 .status = asix_status, 855 .link_reset = ax88772_link_reset, 856 .reset = ax88772_reset, 857 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 858 .rx_fixup = asix_rx_fixup, 859 .tx_fixup = asix_tx_fixup, 860 }; 861 862 static const struct driver_info ax88178_info = { 863 .description = "ASIX AX88178 USB 2.0 Ethernet", 864 .bind = ax88178_bind, 865 .status = asix_status, 866 .link_reset = ax88178_link_reset, 867 .reset = ax88178_reset, 868 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, 869 .rx_fixup = asix_rx_fixup, 870 .tx_fixup = asix_tx_fixup, 871 }; 872 873 extern const struct driver_info ax88172a_info; 874 875 static const struct usb_device_id products [] = { 876 { 877 // Linksys USB200M 878 USB_DEVICE (0x077b, 0x2226), 879 .driver_info = (unsigned long) &ax8817x_info, 880 }, { 881 // Netgear FA120 882 USB_DEVICE (0x0846, 0x1040), 883 .driver_info = (unsigned long) &netgear_fa120_info, 884 }, { 885 // DLink DUB-E100 886 USB_DEVICE (0x2001, 0x1a00), 887 .driver_info = (unsigned long) &dlink_dub_e100_info, 888 }, { 889 // Intellinet, ST Lab USB Ethernet 890 USB_DEVICE (0x0b95, 0x1720), 891 .driver_info = (unsigned long) &ax8817x_info, 892 }, { 893 // Hawking UF200, TrendNet TU2-ET100 894 USB_DEVICE (0x07b8, 0x420a), 895 .driver_info = (unsigned long) &hawking_uf200_info, 896 }, { 897 // Billionton Systems, USB2AR 898 USB_DEVICE (0x08dd, 0x90ff), 899 .driver_info = (unsigned long) &ax8817x_info, 900 }, { 901 // ATEN UC210T 902 USB_DEVICE (0x0557, 0x2009), 903 .driver_info = (unsigned long) &ax8817x_info, 904 }, { 905 // Buffalo LUA-U2-KTX 906 USB_DEVICE (0x0411, 0x003d), 907 .driver_info = (unsigned long) &ax8817x_info, 908 }, { 909 // Buffalo LUA-U2-GT 10/100/1000 910 USB_DEVICE (0x0411, 0x006e), 911 .driver_info = (unsigned long) &ax88178_info, 912 }, { 913 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 914 USB_DEVICE (0x6189, 0x182d), 915 .driver_info = (unsigned long) &ax8817x_info, 916 }, { 917 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 918 USB_DEVICE (0x0df6, 0x0056), 919 .driver_info = (unsigned long) &ax88178_info, 920 }, { 921 // corega FEther USB2-TX 922 USB_DEVICE (0x07aa, 0x0017), 923 .driver_info = (unsigned long) &ax8817x_info, 924 }, { 925 // Surecom EP-1427X-2 926 USB_DEVICE (0x1189, 0x0893), 927 .driver_info = (unsigned long) &ax8817x_info, 928 }, { 929 // goodway corp usb gwusb2e 930 USB_DEVICE (0x1631, 0x6200), 931 .driver_info = (unsigned long) &ax8817x_info, 932 }, { 933 // JVC MP-PRX1 Port Replicator 934 USB_DEVICE (0x04f1, 0x3008), 935 .driver_info = (unsigned long) &ax8817x_info, 936 }, { 937 // Lenovo U2L100P 10/100 938 USB_DEVICE (0x17ef, 0x7203), 939 .driver_info = (unsigned long) &ax88772_info, 940 }, { 941 // ASIX AX88772B 10/100 942 USB_DEVICE (0x0b95, 0x772b), 943 .driver_info = (unsigned long) &ax88772_info, 944 }, { 945 // ASIX AX88772 10/100 946 USB_DEVICE (0x0b95, 0x7720), 947 .driver_info = (unsigned long) &ax88772_info, 948 }, { 949 // ASIX AX88178 10/100/1000 950 USB_DEVICE (0x0b95, 0x1780), 951 .driver_info = (unsigned long) &ax88178_info, 952 }, { 953 // Logitec LAN-GTJ/U2A 954 USB_DEVICE (0x0789, 0x0160), 955 .driver_info = (unsigned long) &ax88178_info, 956 }, { 957 // Linksys USB200M Rev 2 958 USB_DEVICE (0x13b1, 0x0018), 959 .driver_info = (unsigned long) &ax88772_info, 960 }, { 961 // 0Q0 cable ethernet 962 USB_DEVICE (0x1557, 0x7720), 963 .driver_info = (unsigned long) &ax88772_info, 964 }, { 965 // DLink DUB-E100 H/W Ver B1 966 USB_DEVICE (0x07d1, 0x3c05), 967 .driver_info = (unsigned long) &ax88772_info, 968 }, { 969 // DLink DUB-E100 H/W Ver B1 Alternate 970 USB_DEVICE (0x2001, 0x3c05), 971 .driver_info = (unsigned long) &ax88772_info, 972 }, { 973 // DLink DUB-E100 H/W Ver C1 974 USB_DEVICE (0x2001, 0x1a02), 975 .driver_info = (unsigned long) &ax88772_info, 976 }, { 977 // Linksys USB1000 978 USB_DEVICE (0x1737, 0x0039), 979 .driver_info = (unsigned long) &ax88178_info, 980 }, { 981 // IO-DATA ETG-US2 982 USB_DEVICE (0x04bb, 0x0930), 983 .driver_info = (unsigned long) &ax88178_info, 984 }, { 985 // Belkin F5D5055 986 USB_DEVICE(0x050d, 0x5055), 987 .driver_info = (unsigned long) &ax88178_info, 988 }, { 989 // Apple USB Ethernet Adapter 990 USB_DEVICE(0x05ac, 0x1402), 991 .driver_info = (unsigned long) &ax88772_info, 992 }, { 993 // Cables-to-Go USB Ethernet Adapter 994 USB_DEVICE(0x0b95, 0x772a), 995 .driver_info = (unsigned long) &ax88772_info, 996 }, { 997 // ABOCOM for pci 998 USB_DEVICE(0x14ea, 0xab11), 999 .driver_info = (unsigned long) &ax88178_info, 1000 }, { 1001 // ASIX 88772a 1002 USB_DEVICE(0x0db0, 0xa877), 1003 .driver_info = (unsigned long) &ax88772_info, 1004 }, { 1005 // Asus USB Ethernet Adapter 1006 USB_DEVICE (0x0b95, 0x7e2b), 1007 .driver_info = (unsigned long) &ax88772_info, 1008 }, { 1009 /* ASIX 88172a demo board */ 1010 USB_DEVICE(0x0b95, 0x172a), 1011 .driver_info = (unsigned long) &ax88172a_info, 1012 }, 1013 { }, // END 1014 }; 1015 MODULE_DEVICE_TABLE(usb, products); 1016 1017 static struct usb_driver asix_driver = { 1018 .name = DRIVER_NAME, 1019 .id_table = products, 1020 .probe = usbnet_probe, 1021 .suspend = usbnet_suspend, 1022 .resume = usbnet_resume, 1023 .disconnect = usbnet_disconnect, 1024 .supports_autosuspend = 1, 1025 .disable_hub_initiated_lpm = 1, 1026 }; 1027 1028 module_usb_driver(asix_driver); 1029 1030 MODULE_AUTHOR("David Hollis"); 1031 MODULE_VERSION(DRIVER_VERSION); 1032 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1033 MODULE_LICENSE("GPL"); 1034 1035