1 /* 2 * ASIX AX8817X based USB 2.0 Ethernet Devices 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 6 * Copyright (c) 2002-2003 TiVo Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef _ASIX_H 23 #define _ASIX_H 24 25 // #define DEBUG // error path messages, extra info 26 // #define VERBOSE // more; success messages 27 28 #include <linux/module.h> 29 #include <linux/kmod.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/workqueue.h> 35 #include <linux/mii.h> 36 #include <linux/usb.h> 37 #include <linux/crc32.h> 38 #include <linux/usb/usbnet.h> 39 #include <linux/slab.h> 40 #include <linux/if_vlan.h> 41 42 #define DRIVER_VERSION "22-Dec-2011" 43 #define DRIVER_NAME "asix" 44 45 /* ASIX AX8817X based USB 2.0 Ethernet Devices */ 46 47 #define AX_CMD_SET_SW_MII 0x06 48 #define AX_CMD_READ_MII_REG 0x07 49 #define AX_CMD_WRITE_MII_REG 0x08 50 #define AX_CMD_SET_HW_MII 0x0a 51 #define AX_CMD_READ_EEPROM 0x0b 52 #define AX_CMD_WRITE_EEPROM 0x0c 53 #define AX_CMD_WRITE_ENABLE 0x0d 54 #define AX_CMD_WRITE_DISABLE 0x0e 55 #define AX_CMD_READ_RX_CTL 0x0f 56 #define AX_CMD_WRITE_RX_CTL 0x10 57 #define AX_CMD_READ_IPG012 0x11 58 #define AX_CMD_WRITE_IPG0 0x12 59 #define AX_CMD_WRITE_IPG1 0x13 60 #define AX_CMD_READ_NODE_ID 0x13 61 #define AX_CMD_WRITE_NODE_ID 0x14 62 #define AX_CMD_WRITE_IPG2 0x14 63 #define AX_CMD_WRITE_MULTI_FILTER 0x16 64 #define AX88172_CMD_READ_NODE_ID 0x17 65 #define AX_CMD_READ_PHY_ID 0x19 66 #define AX_CMD_READ_MEDIUM_STATUS 0x1a 67 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 68 #define AX_CMD_READ_MONITOR_MODE 0x1c 69 #define AX_CMD_WRITE_MONITOR_MODE 0x1d 70 #define AX_CMD_READ_GPIOS 0x1e 71 #define AX_CMD_WRITE_GPIOS 0x1f 72 #define AX_CMD_SW_RESET 0x20 73 #define AX_CMD_SW_PHY_STATUS 0x21 74 #define AX_CMD_SW_PHY_SELECT 0x22 75 76 #define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) 77 #define AX_PHY_SELECT_INTERNAL 0 78 #define AX_PHY_SELECT_EXTERNAL BIT(2) 79 80 #define AX_MONITOR_MODE 0x01 81 #define AX_MONITOR_LINK 0x02 82 #define AX_MONITOR_MAGIC 0x04 83 #define AX_MONITOR_HSFS 0x10 84 85 /* AX88172 Medium Status Register values */ 86 #define AX88172_MEDIUM_FD 0x02 87 #define AX88172_MEDIUM_TX 0x04 88 #define AX88172_MEDIUM_FC 0x10 89 #define AX88172_MEDIUM_DEFAULT \ 90 ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) 91 92 #define AX_MCAST_FILTER_SIZE 8 93 #define AX_MAX_MCAST 64 94 95 #define AX_SWRESET_CLEAR 0x00 96 #define AX_SWRESET_RR 0x01 97 #define AX_SWRESET_RT 0x02 98 #define AX_SWRESET_PRTE 0x04 99 #define AX_SWRESET_PRL 0x08 100 #define AX_SWRESET_BZ 0x10 101 #define AX_SWRESET_IPRL 0x20 102 #define AX_SWRESET_IPPD 0x40 103 104 #define AX88772_IPG0_DEFAULT 0x15 105 #define AX88772_IPG1_DEFAULT 0x0c 106 #define AX88772_IPG2_DEFAULT 0x12 107 108 /* AX88772 & AX88178 Medium Mode Register */ 109 #define AX_MEDIUM_PF 0x0080 110 #define AX_MEDIUM_JFE 0x0040 111 #define AX_MEDIUM_TFC 0x0020 112 #define AX_MEDIUM_RFC 0x0010 113 #define AX_MEDIUM_ENCK 0x0008 114 #define AX_MEDIUM_AC 0x0004 115 #define AX_MEDIUM_FD 0x0002 116 #define AX_MEDIUM_GM 0x0001 117 #define AX_MEDIUM_SM 0x1000 118 #define AX_MEDIUM_SBP 0x0800 119 #define AX_MEDIUM_PS 0x0200 120 #define AX_MEDIUM_RE 0x0100 121 122 #define AX88178_MEDIUM_DEFAULT \ 123 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ 124 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ 125 AX_MEDIUM_RE) 126 127 #define AX88772_MEDIUM_DEFAULT \ 128 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ 129 AX_MEDIUM_TFC | AX_MEDIUM_PS | \ 130 AX_MEDIUM_AC | AX_MEDIUM_RE) 131 132 /* AX88772 & AX88178 RX_CTL values */ 133 #define AX_RX_CTL_SO 0x0080 134 #define AX_RX_CTL_AP 0x0020 135 #define AX_RX_CTL_AM 0x0010 136 #define AX_RX_CTL_AB 0x0008 137 #define AX_RX_CTL_SEP 0x0004 138 #define AX_RX_CTL_AMALL 0x0002 139 #define AX_RX_CTL_PRO 0x0001 140 #define AX_RX_CTL_MFB_2048 0x0000 141 #define AX_RX_CTL_MFB_4096 0x0100 142 #define AX_RX_CTL_MFB_8192 0x0200 143 #define AX_RX_CTL_MFB_16384 0x0300 144 145 #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) 146 147 /* GPIO 0 .. 2 toggles */ 148 #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ 149 #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ 150 #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ 151 #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ 152 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ 153 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ 154 #define AX_GPIO_RESERVED 0x40 /* Reserved */ 155 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ 156 157 #define AX_EEPROM_MAGIC 0xdeadbeef 158 #define AX_EEPROM_LEN 0x200 159 160 /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ 161 struct asix_data { 162 u8 multi_filter[AX_MCAST_FILTER_SIZE]; 163 u8 mac_addr[ETH_ALEN]; 164 u8 phymode; 165 u8 ledmode; 166 u8 res; 167 }; 168 169 struct asix_rx_fixup_info { 170 struct sk_buff *ax_skb; 171 u32 header; 172 u16 size; 173 bool split_head; 174 }; 175 176 struct asix_common_private { 177 struct asix_rx_fixup_info rx_fixup_info; 178 }; 179 180 extern const struct driver_info ax88172a_info; 181 182 /* ASIX specific flags */ 183 #define FLAG_EEPROM_MAC (1UL << 0) /* init device MAC from eeprom */ 184 185 int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 186 u16 size, void *data); 187 188 int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 189 u16 size, void *data); 190 191 void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 192 u16 index, u16 size, void *data); 193 194 int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb, 195 struct asix_rx_fixup_info *rx); 196 int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb); 197 198 struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, 199 gfp_t flags); 200 201 int asix_set_sw_mii(struct usbnet *dev); 202 int asix_set_hw_mii(struct usbnet *dev); 203 204 int asix_read_phy_addr(struct usbnet *dev, int internal); 205 int asix_get_phy_addr(struct usbnet *dev); 206 207 int asix_sw_reset(struct usbnet *dev, u8 flags); 208 209 u16 asix_read_rx_ctl(struct usbnet *dev); 210 int asix_write_rx_ctl(struct usbnet *dev, u16 mode); 211 212 u16 asix_read_medium_status(struct usbnet *dev); 213 int asix_write_medium_mode(struct usbnet *dev, u16 mode); 214 215 int asix_write_gpio(struct usbnet *dev, u16 value, int sleep); 216 217 void asix_set_multicast(struct net_device *net); 218 219 int asix_mdio_read(struct net_device *netdev, int phy_id, int loc); 220 void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val); 221 222 void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo); 223 int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo); 224 225 int asix_get_eeprom_len(struct net_device *net); 226 int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 227 u8 *data); 228 int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 229 u8 *data); 230 231 void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info); 232 233 int asix_set_mac_address(struct net_device *net, void *p); 234 235 #endif /* _ASIX_H */ 236