1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/firmware.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pse-pd/pse.h> 17 18 #define TPS23881_MAX_CHANS 8 19 20 #define TPS23881_REG_PW_STATUS 0x10 21 #define TPS23881_REG_OP_MODE 0x12 22 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa 23 #define TPS23881_REG_DIS_EN 0x13 24 #define TPS23881_REG_DET_CLA_EN 0x14 25 #define TPS23881_REG_GEN_MASK 0x17 26 #define TPS23881_REG_NBITACC BIT(5) 27 #define TPS23881_REG_PW_EN 0x19 28 #define TPS23881_REG_2PAIR_POL1 0x1e 29 #define TPS23881_REG_PORT_MAP 0x26 30 #define TPS23881_REG_PORT_POWER 0x29 31 #define TPS23881_REG_4PAIR_POL1 0x2a 32 #define TPS23881_REG_INPUT_V 0x2e 33 #define TPS23881_REG_CHAN1_A 0x30 34 #define TPS23881_REG_CHAN1_V 0x32 35 #define TPS23881_REG_FOLDBACK 0x40 36 #define TPS23881_REG_TPON BIT(0) 37 #define TPS23881_REG_FWREV 0x41 38 #define TPS23881_REG_DEVID 0x43 39 #define TPS23881_REG_DEVID_MASK 0xF0 40 #define TPS23881_DEVICE_ID 0x02 41 #define TPS23881_REG_CHAN1_CLASS 0x4c 42 #define TPS23881_REG_SRAM_CTRL 0x60 43 #define TPS23881_REG_SRAM_DATA 0x61 44 45 #define TPS23881_UV_STEP 3662 46 #define TPS23881_NA_STEP 70190 47 #define TPS23881_MW_STEP 500 48 #define TPS23881_MIN_PI_PW_LIMIT_MW 2000 49 50 struct tps23881_port_desc { 51 u8 chan[2]; 52 bool is_4p; 53 int pw_pol; 54 }; 55 56 struct tps23881_priv { 57 struct i2c_client *client; 58 struct pse_controller_dev pcdev; 59 struct device_node *np; 60 struct tps23881_port_desc port[TPS23881_MAX_CHANS]; 61 }; 62 63 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev) 64 { 65 return container_of(pcdev, struct tps23881_priv, pcdev); 66 } 67 68 /* 69 * Helper to extract a value from a u16 register value, which is made of two 70 * u8 registers. The function calculates the bit offset based on the channel 71 * and extracts the relevant bits using a provided field mask. 72 * 73 * @param reg_val: The u16 register value (composed of two u8 registers). 74 * @param chan: The channel number (0-7). 75 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 76 * @param field_mask: The mask to apply to extract the required bits. 77 * @return: The extracted value for the specific channel. 78 */ 79 static u16 tps23881_calc_val(u16 reg_val, u8 chan, u8 field_offset, 80 u16 field_mask) 81 { 82 if (chan >= 4) 83 reg_val >>= 8; 84 85 return (reg_val >> field_offset) & field_mask; 86 } 87 88 /* 89 * Helper to combine individual channel values into a u16 register value. 90 * The function sets the value for a specific channel in the appropriate 91 * position. 92 * 93 * @param reg_val: The current u16 register value. 94 * @param chan: The channel number (0-7). 95 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 96 * @param field_mask: The mask to apply for the field (e.g., 0x0F). 97 * @param field_val: The value to set for the specific channel (masked by 98 * field_mask). 99 * @return: The updated u16 register value with the channel value set. 100 */ 101 static u16 tps23881_set_val(u16 reg_val, u8 chan, u8 field_offset, 102 u16 field_mask, u16 field_val) 103 { 104 field_val &= field_mask; 105 106 if (chan < 4) { 107 reg_val &= ~(field_mask << field_offset); 108 reg_val |= (field_val << field_offset); 109 } else { 110 reg_val &= ~(field_mask << (field_offset + 8)); 111 reg_val |= (field_val << (field_offset + 8)); 112 } 113 114 return reg_val; 115 } 116 117 static int 118 tps23881_pi_set_pw_pol_limit(struct tps23881_priv *priv, int id, u8 pw_pol, 119 bool is_4p) 120 { 121 struct i2c_client *client = priv->client; 122 int ret, reg; 123 u16 val; 124 u8 chan; 125 126 chan = priv->port[id].chan[0]; 127 if (!is_4p) { 128 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 129 } else { 130 /* One chan is enough to configure the 4p PI power limit */ 131 if ((chan % 4) < 2) 132 reg = TPS23881_REG_4PAIR_POL1; 133 else 134 reg = TPS23881_REG_4PAIR_POL1 + 1; 135 } 136 137 ret = i2c_smbus_read_word_data(client, reg); 138 if (ret < 0) 139 return ret; 140 141 val = tps23881_set_val(ret, chan, 0, 0xff, pw_pol); 142 return i2c_smbus_write_word_data(client, reg, val); 143 } 144 145 static int tps23881_pi_enable_manual_pol(struct tps23881_priv *priv, int id) 146 { 147 struct i2c_client *client = priv->client; 148 int ret; 149 u8 chan; 150 u16 val; 151 152 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FOLDBACK); 153 if (ret < 0) 154 return ret; 155 156 /* No need to test if the chan is PoE4 as setting either bit for a 157 * 4P configured port disables the automatic configuration on both 158 * channels. 159 */ 160 chan = priv->port[id].chan[0]; 161 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 162 return i2c_smbus_write_byte_data(client, TPS23881_REG_FOLDBACK, val); 163 } 164 165 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id) 166 { 167 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 168 struct i2c_client *client = priv->client; 169 u8 chan; 170 u16 val; 171 172 if (id >= TPS23881_MAX_CHANS) 173 return -ERANGE; 174 175 chan = priv->port[id].chan[0]; 176 val = tps23881_set_val(0, chan, 0, BIT(chan % 4), BIT(chan % 4)); 177 178 if (priv->port[id].is_4p) { 179 chan = priv->port[id].chan[1]; 180 val = tps23881_set_val(val, chan, 0, BIT(chan % 4), 181 BIT(chan % 4)); 182 } 183 184 return i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 185 } 186 187 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id) 188 { 189 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 190 struct i2c_client *client = priv->client; 191 u8 chan; 192 u16 val; 193 int ret; 194 195 if (id >= TPS23881_MAX_CHANS) 196 return -ERANGE; 197 198 chan = priv->port[id].chan[0]; 199 val = tps23881_set_val(0, chan, 4, BIT(chan % 4), BIT(chan % 4)); 200 201 if (priv->port[id].is_4p) { 202 chan = priv->port[id].chan[1]; 203 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 204 BIT(chan % 4)); 205 } 206 207 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 208 if (ret) 209 return ret; 210 211 /* PWOFF command resets lots of register which need to be 212 * configured again. According to the datasheet "It may take upwards 213 * of 5ms after PWOFFn command for all register values to be updated" 214 */ 215 mdelay(5); 216 217 /* Enable detection and classification */ 218 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_CLA_EN); 219 if (ret < 0) 220 return ret; 221 222 chan = priv->port[id].chan[0]; 223 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 224 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), BIT(chan % 4)); 225 226 if (priv->port[id].is_4p) { 227 chan = priv->port[id].chan[1]; 228 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), 229 BIT(chan % 4)); 230 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 231 BIT(chan % 4)); 232 } 233 234 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 235 if (ret) 236 return ret; 237 238 /* No power policy */ 239 if (priv->port[id].pw_pol < 0) 240 return 0; 241 242 ret = tps23881_pi_enable_manual_pol(priv, id); 243 if (ret < 0) 244 return ret; 245 246 /* Set power policy */ 247 return tps23881_pi_set_pw_pol_limit(priv, id, priv->port[id].pw_pol, 248 priv->port[id].is_4p); 249 } 250 251 static int 252 tps23881_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 253 struct pse_admin_state *admin_state) 254 { 255 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 256 struct i2c_client *client = priv->client; 257 bool enabled; 258 u8 chan; 259 u16 val; 260 int ret; 261 262 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 263 if (ret < 0) 264 return ret; 265 266 chan = priv->port[id].chan[0]; 267 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 268 enabled = !!(val); 269 270 if (priv->port[id].is_4p) { 271 chan = priv->port[id].chan[1]; 272 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 273 enabled &= !!(val); 274 } 275 276 /* Return enabled status only if both channel are on this state */ 277 if (enabled) 278 admin_state->c33_admin_state = 279 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 280 else 281 admin_state->c33_admin_state = 282 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 283 284 return 0; 285 } 286 287 static int 288 tps23881_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 289 struct pse_pw_status *pw_status) 290 { 291 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 292 struct i2c_client *client = priv->client; 293 bool delivering; 294 u8 chan; 295 u16 val; 296 int ret; 297 298 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 299 if (ret < 0) 300 return ret; 301 302 chan = priv->port[id].chan[0]; 303 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 304 delivering = !!(val); 305 306 if (priv->port[id].is_4p) { 307 chan = priv->port[id].chan[1]; 308 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 309 delivering &= !!(val); 310 } 311 312 /* Return delivering status only if both channel are on this state */ 313 if (delivering) 314 pw_status->c33_pw_status = 315 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 316 else 317 pw_status->c33_pw_status = 318 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 319 320 return 0; 321 } 322 323 static int tps23881_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 324 { 325 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 326 struct i2c_client *client = priv->client; 327 int ret; 328 u64 uV; 329 330 ret = i2c_smbus_read_word_data(client, TPS23881_REG_INPUT_V); 331 if (ret < 0) 332 return ret; 333 334 uV = ret & 0x3fff; 335 uV *= TPS23881_UV_STEP; 336 337 return (int)uV; 338 } 339 340 static int 341 tps23881_pi_get_chan_current(struct tps23881_priv *priv, u8 chan) 342 { 343 struct i2c_client *client = priv->client; 344 int reg, ret; 345 u64 tmp_64; 346 347 /* Registers 0x30 to 0x3d */ 348 reg = TPS23881_REG_CHAN1_A + (chan % 4) * 4 + (chan >= 4); 349 ret = i2c_smbus_read_word_data(client, reg); 350 if (ret < 0) 351 return ret; 352 353 tmp_64 = ret & 0x3fff; 354 tmp_64 *= TPS23881_NA_STEP; 355 /* uA = nA / 1000 */ 356 tmp_64 = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000); 357 return (int)tmp_64; 358 } 359 360 static int tps23881_pi_get_pw_class(struct pse_controller_dev *pcdev, 361 int id) 362 { 363 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 364 struct i2c_client *client = priv->client; 365 int ret, reg; 366 u8 chan; 367 368 chan = priv->port[id].chan[0]; 369 reg = TPS23881_REG_CHAN1_CLASS + (chan % 4); 370 ret = i2c_smbus_read_word_data(client, reg); 371 if (ret < 0) 372 return ret; 373 374 return tps23881_calc_val(ret, chan, 4, 0x0f); 375 } 376 377 static int 378 tps23881_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 379 { 380 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 381 int ret, uV, uA; 382 u64 tmp_64; 383 u8 chan; 384 385 ret = tps23881_pi_get_voltage(&priv->pcdev, id); 386 if (ret < 0) 387 return ret; 388 uV = ret; 389 390 chan = priv->port[id].chan[0]; 391 ret = tps23881_pi_get_chan_current(priv, chan); 392 if (ret < 0) 393 return ret; 394 uA = ret; 395 396 if (priv->port[id].is_4p) { 397 chan = priv->port[id].chan[1]; 398 ret = tps23881_pi_get_chan_current(priv, chan); 399 if (ret < 0) 400 return ret; 401 uA += ret; 402 } 403 404 tmp_64 = uV; 405 tmp_64 *= uA; 406 /* mW = uV * uA / 1000000000 */ 407 return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); 408 } 409 410 static int 411 tps23881_pi_get_pw_limit_chan(struct tps23881_priv *priv, u8 chan) 412 { 413 struct i2c_client *client = priv->client; 414 int ret, reg; 415 u16 val; 416 417 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 418 ret = i2c_smbus_read_word_data(client, reg); 419 if (ret < 0) 420 return ret; 421 422 val = tps23881_calc_val(ret, chan, 0, 0xff); 423 return val * TPS23881_MW_STEP; 424 } 425 426 static int tps23881_pi_get_pw_limit(struct pse_controller_dev *pcdev, int id) 427 { 428 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 429 int ret, mW; 430 u8 chan; 431 432 chan = priv->port[id].chan[0]; 433 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 434 if (ret < 0) 435 return ret; 436 437 mW = ret; 438 if (priv->port[id].is_4p) { 439 chan = priv->port[id].chan[1]; 440 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 441 if (ret < 0) 442 return ret; 443 mW += ret; 444 } 445 446 return mW; 447 } 448 449 static int tps23881_pi_set_pw_limit(struct pse_controller_dev *pcdev, 450 int id, int max_mW) 451 { 452 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 453 u8 pw_pol; 454 int ret; 455 456 if (max_mW < TPS23881_MIN_PI_PW_LIMIT_MW || MAX_PI_PW < max_mW) { 457 dev_err(&priv->client->dev, 458 "power limit %d out of ranges [%d,%d]", 459 max_mW, TPS23881_MIN_PI_PW_LIMIT_MW, MAX_PI_PW); 460 return -ERANGE; 461 } 462 463 ret = tps23881_pi_enable_manual_pol(priv, id); 464 if (ret < 0) 465 return ret; 466 467 pw_pol = DIV_ROUND_CLOSEST_ULL(max_mW, TPS23881_MW_STEP); 468 469 /* Save power policy to reconfigure it after a disabled call */ 470 priv->port[id].pw_pol = pw_pol; 471 return tps23881_pi_set_pw_pol_limit(priv, id, pw_pol, 472 priv->port[id].is_4p); 473 } 474 475 static int 476 tps23881_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 477 struct pse_pw_limit_ranges *pw_limit_ranges) 478 { 479 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 480 481 c33_pw_limit_ranges = kzalloc(sizeof(*c33_pw_limit_ranges), 482 GFP_KERNEL); 483 if (!c33_pw_limit_ranges) 484 return -ENOMEM; 485 486 c33_pw_limit_ranges->min = TPS23881_MIN_PI_PW_LIMIT_MW; 487 c33_pw_limit_ranges->max = MAX_PI_PW; 488 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 489 490 /* Return the number of ranges */ 491 return 1; 492 } 493 494 /* Parse managers subnode into a array of device node */ 495 static int 496 tps23881_get_of_channels(struct tps23881_priv *priv, 497 struct device_node *chan_node[TPS23881_MAX_CHANS]) 498 { 499 struct device_node *channels_node, *node; 500 int i, ret; 501 502 if (!priv->np) 503 return -EINVAL; 504 505 channels_node = of_find_node_by_name(priv->np, "channels"); 506 if (!channels_node) 507 return -EINVAL; 508 509 for_each_child_of_node(channels_node, node) { 510 u32 chan_id; 511 512 if (!of_node_name_eq(node, "channel")) 513 continue; 514 515 ret = of_property_read_u32(node, "reg", &chan_id); 516 if (ret) { 517 ret = -EINVAL; 518 goto out; 519 } 520 521 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) { 522 dev_err(&priv->client->dev, 523 "wrong number of port (%d)\n", chan_id); 524 ret = -EINVAL; 525 goto out; 526 } 527 528 of_node_get(node); 529 chan_node[chan_id] = node; 530 } 531 532 of_node_put(channels_node); 533 return 0; 534 535 out: 536 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 537 of_node_put(chan_node[i]); 538 chan_node[i] = NULL; 539 } 540 541 of_node_put(node); 542 of_node_put(channels_node); 543 return ret; 544 } 545 546 struct tps23881_port_matrix { 547 u8 pi_id; 548 u8 lgcl_chan[2]; 549 u8 hw_chan[2]; 550 bool is_4p; 551 bool exist; 552 }; 553 554 static int 555 tps23881_match_channel(const struct pse_pi_pairset *pairset, 556 struct device_node *chan_node[TPS23881_MAX_CHANS]) 557 { 558 int i; 559 560 /* Look on every channels */ 561 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 562 if (pairset->np == chan_node[i]) 563 return i; 564 } 565 566 return -ENODEV; 567 } 568 569 static bool 570 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 571 int chan) 572 { 573 int i; 574 575 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 576 if (port_matrix[i].exist && 577 (port_matrix[i].hw_chan[0] == chan || 578 port_matrix[i].hw_chan[1] == chan)) 579 return false; 580 } 581 582 return true; 583 } 584 585 /* Fill port matrix with the matching channels */ 586 static int 587 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id, 588 struct device_node *chan_node[TPS23881_MAX_CHANS], 589 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 590 { 591 int ret; 592 593 if (!pi->pairset[0].np) 594 return 0; 595 596 ret = tps23881_match_channel(&pi->pairset[0], chan_node); 597 if (ret < 0) 598 return ret; 599 600 if (!tps23881_is_chan_free(port_matrix, ret)) { 601 pr_err("tps23881: channel %d already used\n", ret); 602 return -ENODEV; 603 } 604 605 port_matrix[pi_id].hw_chan[0] = ret; 606 port_matrix[pi_id].exist = true; 607 608 if (!pi->pairset[1].np) 609 return 0; 610 611 ret = tps23881_match_channel(&pi->pairset[1], chan_node); 612 if (ret < 0) 613 return ret; 614 615 if (!tps23881_is_chan_free(port_matrix, ret)) { 616 pr_err("tps23881: channel %d already used\n", ret); 617 return -ENODEV; 618 } 619 620 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) { 621 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group"); 622 return -ENODEV; 623 } 624 625 port_matrix[pi_id].hw_chan[1] = ret; 626 port_matrix[pi_id].is_4p = true; 627 628 return 0; 629 } 630 631 static int 632 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 633 int port_cnt) 634 { 635 bool used; 636 int i, j; 637 638 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 639 used = false; 640 641 for (j = 0; j < port_cnt; j++) { 642 if (port_matrix[j].hw_chan[0] == i) { 643 used = true; 644 break; 645 } 646 647 if (port_matrix[j].is_4p && 648 port_matrix[j].hw_chan[1] == i) { 649 used = true; 650 break; 651 } 652 } 653 654 if (!used) 655 return i; 656 } 657 658 return -ENODEV; 659 } 660 661 /* Sort the port matrix to following particular hardware ports matrix 662 * specification of the tps23881. The device has two 4-ports groups and 663 * each 4-pair powered device has to be configured to use two consecutive 664 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the 665 * hardware matrix has to be fully configured even with unused chan to be 666 * valid. 667 */ 668 static int 669 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 670 { 671 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0}; 672 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4; 673 674 /* Configure 4p port matrix */ 675 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 676 int *cnt; 677 678 if (!port_matrix[i].exist || !port_matrix[i].is_4p) 679 continue; 680 681 if (port_matrix[i].hw_chan[0] < 4) 682 cnt = &cnt_4ch_grp1; 683 else 684 cnt = &cnt_4ch_grp2; 685 686 tmp_port_matrix[port_cnt].exist = true; 687 tmp_port_matrix[port_cnt].is_4p = true; 688 tmp_port_matrix[port_cnt].pi_id = i; 689 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 690 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1]; 691 692 /* 4-pair ports have to be configured with consecutive 693 * logical channels 0 and 1, 2 and 3. 694 */ 695 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 696 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++; 697 698 port_cnt++; 699 } 700 701 /* Configure 2p port matrix */ 702 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 703 int *cnt; 704 705 if (!port_matrix[i].exist || port_matrix[i].is_4p) 706 continue; 707 708 if (port_matrix[i].hw_chan[0] < 4) 709 cnt = &cnt_4ch_grp1; 710 else 711 cnt = &cnt_4ch_grp2; 712 713 tmp_port_matrix[port_cnt].exist = true; 714 tmp_port_matrix[port_cnt].pi_id = i; 715 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 716 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 717 718 port_cnt++; 719 } 720 721 /* Complete the rest of the first 4 port group matrix even if 722 * channels are unused 723 */ 724 while (cnt_4ch_grp1 < 4) { 725 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 726 if (ret < 0) { 727 pr_err("tps23881: port matrix issue, no chan available\n"); 728 return ret; 729 } 730 731 if (port_cnt >= TPS23881_MAX_CHANS) { 732 pr_err("tps23881: wrong number of channels\n"); 733 return -ENODEV; 734 } 735 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1; 736 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 737 cnt_4ch_grp1++; 738 port_cnt++; 739 } 740 741 /* Complete the rest of the second 4 port group matrix even if 742 * channels are unused 743 */ 744 while (cnt_4ch_grp2 < 8) { 745 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 746 if (ret < 0) { 747 pr_err("tps23881: port matrix issue, no chan available\n"); 748 return -ENODEV; 749 } 750 751 if (port_cnt >= TPS23881_MAX_CHANS) { 752 pr_err("tps23881: wrong number of channels\n"); 753 return -ENODEV; 754 } 755 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2; 756 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 757 cnt_4ch_grp2++; 758 port_cnt++; 759 } 760 761 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix)); 762 763 return port_cnt; 764 } 765 766 /* Write port matrix to the hardware port matrix and the software port 767 * matrix. 768 */ 769 static int 770 tps23881_write_port_matrix(struct tps23881_priv *priv, 771 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 772 int port_cnt) 773 { 774 struct i2c_client *client = priv->client; 775 u8 pi_id, lgcl_chan, hw_chan; 776 u16 val = 0; 777 int i; 778 779 for (i = 0; i < port_cnt; i++) { 780 pi_id = port_matrix[i].pi_id; 781 lgcl_chan = port_matrix[i].lgcl_chan[0]; 782 hw_chan = port_matrix[i].hw_chan[0] % 4; 783 784 /* Set software port matrix for existing ports */ 785 if (port_matrix[i].exist) 786 priv->port[pi_id].chan[0] = lgcl_chan; 787 788 /* Initialize power policy internal value */ 789 priv->port[pi_id].pw_pol = -1; 790 791 /* Set hardware port matrix for all ports */ 792 val |= hw_chan << (lgcl_chan * 2); 793 794 if (!port_matrix[i].is_4p) 795 continue; 796 797 lgcl_chan = port_matrix[i].lgcl_chan[1]; 798 hw_chan = port_matrix[i].hw_chan[1] % 4; 799 800 /* Set software port matrix for existing ports */ 801 if (port_matrix[i].exist) { 802 priv->port[pi_id].is_4p = true; 803 priv->port[pi_id].chan[1] = lgcl_chan; 804 } 805 806 /* Set hardware port matrix for all ports */ 807 val |= hw_chan << (lgcl_chan * 2); 808 } 809 810 /* Write hardware ports matrix */ 811 return i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val); 812 } 813 814 static int 815 tps23881_set_ports_conf(struct tps23881_priv *priv, 816 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 817 { 818 struct i2c_client *client = priv->client; 819 int i, ret; 820 u16 val; 821 822 /* Set operating mode */ 823 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE, 824 TPS23881_OP_MODE_SEMIAUTO); 825 if (ret) 826 return ret; 827 828 /* Disable DC disconnect */ 829 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0); 830 if (ret) 831 return ret; 832 833 /* Set port power allocation */ 834 val = 0; 835 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 836 if (!port_matrix[i].exist) 837 continue; 838 839 if (port_matrix[i].is_4p) 840 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 841 else 842 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 843 } 844 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val); 845 if (ret) 846 return ret; 847 848 /* Enable detection and classification */ 849 val = 0; 850 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 851 if (!port_matrix[i].exist) 852 continue; 853 854 val |= BIT(port_matrix[i].lgcl_chan[0]) | 855 BIT(port_matrix[i].lgcl_chan[0] + 4); 856 if (port_matrix[i].is_4p) 857 val |= BIT(port_matrix[i].lgcl_chan[1]) | 858 BIT(port_matrix[i].lgcl_chan[1] + 4); 859 } 860 return i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 861 } 862 863 static int 864 tps23881_set_ports_matrix(struct tps23881_priv *priv, 865 struct device_node *chan_node[TPS23881_MAX_CHANS]) 866 { 867 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0}; 868 int i, ret; 869 870 /* Update with values for every PSE PIs */ 871 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 872 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i, 873 chan_node, port_matrix); 874 if (ret) 875 return ret; 876 } 877 878 ret = tps23881_sort_port_matrix(port_matrix); 879 if (ret < 0) 880 return ret; 881 882 ret = tps23881_write_port_matrix(priv, port_matrix, ret); 883 if (ret) 884 return ret; 885 886 return tps23881_set_ports_conf(priv, port_matrix); 887 } 888 889 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev) 890 { 891 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL}; 892 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 893 int ret, i; 894 895 ret = tps23881_get_of_channels(priv, chan_node); 896 if (ret < 0) { 897 dev_warn(&priv->client->dev, 898 "Unable to parse port-matrix, default matrix will be used\n"); 899 return 0; 900 } 901 902 ret = tps23881_set_ports_matrix(priv, chan_node); 903 904 for (i = 0; i < TPS23881_MAX_CHANS; i++) 905 of_node_put(chan_node[i]); 906 907 return ret; 908 } 909 910 static const struct pse_controller_ops tps23881_ops = { 911 .setup_pi_matrix = tps23881_setup_pi_matrix, 912 .pi_enable = tps23881_pi_enable, 913 .pi_disable = tps23881_pi_disable, 914 .pi_get_admin_state = tps23881_pi_get_admin_state, 915 .pi_get_pw_status = tps23881_pi_get_pw_status, 916 .pi_get_pw_class = tps23881_pi_get_pw_class, 917 .pi_get_actual_pw = tps23881_pi_get_actual_pw, 918 .pi_get_voltage = tps23881_pi_get_voltage, 919 .pi_get_pw_limit = tps23881_pi_get_pw_limit, 920 .pi_set_pw_limit = tps23881_pi_set_pw_limit, 921 .pi_get_pw_limit_ranges = tps23881_pi_get_pw_limit_ranges, 922 }; 923 924 static const char fw_parity_name[] = "ti/tps23881/tps23881-parity-14.bin"; 925 static const char fw_sram_name[] = "ti/tps23881/tps23881-sram-14.bin"; 926 927 struct tps23881_fw_conf { 928 u8 reg; 929 u8 val; 930 }; 931 932 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = { 933 {.reg = 0x60, .val = 0x01}, 934 {.reg = 0x62, .val = 0x00}, 935 {.reg = 0x63, .val = 0x80}, 936 {.reg = 0x60, .val = 0xC4}, 937 {.reg = 0x1D, .val = 0xBC}, 938 {.reg = 0xD7, .val = 0x02}, 939 {.reg = 0x91, .val = 0x00}, 940 {.reg = 0x90, .val = 0x00}, 941 {.reg = 0xD7, .val = 0x00}, 942 {.reg = 0x1D, .val = 0x00}, 943 { /* sentinel */ } 944 }; 945 946 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = { 947 {.reg = 0x60, .val = 0xC5}, 948 {.reg = 0x62, .val = 0x00}, 949 {.reg = 0x63, .val = 0x80}, 950 {.reg = 0x60, .val = 0xC0}, 951 {.reg = 0x1D, .val = 0xBC}, 952 {.reg = 0xD7, .val = 0x02}, 953 {.reg = 0x91, .val = 0x00}, 954 {.reg = 0x90, .val = 0x00}, 955 {.reg = 0xD7, .val = 0x00}, 956 {.reg = 0x1D, .val = 0x00}, 957 { /* sentinel */ } 958 }; 959 960 static int tps23881_flash_sram_fw_part(struct i2c_client *client, 961 const char *fw_name, 962 const struct tps23881_fw_conf *fw_conf) 963 { 964 const struct firmware *fw = NULL; 965 int i, ret; 966 967 ret = request_firmware(&fw, fw_name, &client->dev); 968 if (ret) 969 return ret; 970 971 dev_dbg(&client->dev, "Flashing %s\n", fw_name); 972 973 /* Prepare device for RAM download */ 974 while (fw_conf->reg) { 975 ret = i2c_smbus_write_byte_data(client, fw_conf->reg, 976 fw_conf->val); 977 if (ret) 978 goto out; 979 980 fw_conf++; 981 } 982 983 /* Flash the firmware file */ 984 for (i = 0; i < fw->size; i++) { 985 ret = i2c_smbus_write_byte_data(client, 986 TPS23881_REG_SRAM_DATA, 987 fw->data[i]); 988 if (ret) 989 goto out; 990 } 991 992 out: 993 release_firmware(fw); 994 return ret; 995 } 996 997 static int tps23881_flash_sram_fw(struct i2c_client *client) 998 { 999 int ret; 1000 1001 ret = tps23881_flash_sram_fw_part(client, fw_parity_name, 1002 tps23881_fw_parity_conf); 1003 if (ret) 1004 return ret; 1005 1006 ret = tps23881_flash_sram_fw_part(client, fw_sram_name, 1007 tps23881_fw_sram_conf); 1008 if (ret) 1009 return ret; 1010 1011 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18); 1012 if (ret) 1013 return ret; 1014 1015 mdelay(12); 1016 1017 return 0; 1018 } 1019 1020 static int tps23881_i2c_probe(struct i2c_client *client) 1021 { 1022 struct device *dev = &client->dev; 1023 struct tps23881_priv *priv; 1024 struct gpio_desc *reset; 1025 int ret; 1026 u8 val; 1027 1028 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1029 dev_err(dev, "i2c check functionality failed\n"); 1030 return -ENXIO; 1031 } 1032 1033 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1034 if (!priv) 1035 return -ENOMEM; 1036 1037 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1038 if (IS_ERR(reset)) 1039 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n"); 1040 1041 if (reset) { 1042 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */ 1043 usleep_range(5, 10); 1044 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */ 1045 1046 /* TPS23880 datasheet indicates the minimum time after power on reset 1047 * should be 20ms, but the document describing how to load SRAM ("How 1048 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E)) 1049 * indicates we should delay that programming by at least 50ms. So 1050 * we'll wait the entire 50ms here to ensure we're safe to go to the 1051 * SRAM loading proceedure. 1052 */ 1053 msleep(50); 1054 } 1055 1056 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID); 1057 if (ret < 0) 1058 return ret; 1059 1060 if (FIELD_GET(TPS23881_REG_DEVID_MASK, ret) != TPS23881_DEVICE_ID) { 1061 dev_err(dev, "Wrong device ID\n"); 1062 return -ENXIO; 1063 } 1064 1065 ret = tps23881_flash_sram_fw(client); 1066 if (ret < 0) 1067 return ret; 1068 1069 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV); 1070 if (ret < 0) 1071 return ret; 1072 1073 dev_info(&client->dev, "Firmware revision 0x%x\n", ret); 1074 1075 /* Set configuration B, 16 bit access on a single device address */ 1076 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK); 1077 if (ret < 0) 1078 return ret; 1079 1080 val = ret | TPS23881_REG_NBITACC; 1081 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val); 1082 if (ret) 1083 return ret; 1084 1085 priv->client = client; 1086 i2c_set_clientdata(client, priv); 1087 priv->np = dev->of_node; 1088 1089 priv->pcdev.owner = THIS_MODULE; 1090 priv->pcdev.ops = &tps23881_ops; 1091 priv->pcdev.dev = dev; 1092 priv->pcdev.types = ETHTOOL_PSE_C33; 1093 priv->pcdev.nr_lines = TPS23881_MAX_CHANS; 1094 ret = devm_pse_controller_register(dev, &priv->pcdev); 1095 if (ret) { 1096 return dev_err_probe(dev, ret, 1097 "failed to register PSE controller\n"); 1098 } 1099 1100 return ret; 1101 } 1102 1103 static const struct i2c_device_id tps23881_id[] = { 1104 { "tps23881" }, 1105 { } 1106 }; 1107 MODULE_DEVICE_TABLE(i2c, tps23881_id); 1108 1109 static const struct of_device_id tps23881_of_match[] = { 1110 { .compatible = "ti,tps23881", }, 1111 { }, 1112 }; 1113 MODULE_DEVICE_TABLE(of, tps23881_of_match); 1114 1115 static struct i2c_driver tps23881_driver = { 1116 .probe = tps23881_i2c_probe, 1117 .id_table = tps23881_id, 1118 .driver = { 1119 .name = "tps23881", 1120 .of_match_table = tps23881_of_match, 1121 }, 1122 }; 1123 module_i2c_driver(tps23881_driver); 1124 1125 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1126 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver"); 1127 MODULE_LICENSE("GPL"); 1128