1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/firmware.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pse-pd/pse.h> 17 18 #define TPS23881_MAX_CHANS 8 19 #define TPS23881_MAX_IRQ_RETRIES 10 20 21 #define TPS23881_REG_IT 0x0 22 #define TPS23881_REG_IT_MASK 0x1 23 #define TPS23881_REG_IT_DISF BIT(2) 24 #define TPS23881_REG_IT_DETC BIT(3) 25 #define TPS23881_REG_IT_CLASC BIT(4) 26 #define TPS23881_REG_IT_IFAULT BIT(5) 27 #define TPS23881_REG_IT_SUPF BIT(7) 28 #define TPS23881_REG_DET_EVENT 0x5 29 #define TPS23881_REG_FAULT 0x7 30 #define TPS23881_REG_SUPF_EVENT 0xb 31 #define TPS23881_REG_TSD BIT(7) 32 #define TPS23881_REG_DISC 0xc 33 #define TPS23881_REG_PW_STATUS 0x10 34 #define TPS23881_REG_OP_MODE 0x12 35 #define TPS23881_REG_DISC_EN 0x13 36 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa 37 #define TPS23881_REG_DIS_EN 0x13 38 #define TPS23881_REG_DET_CLA_EN 0x14 39 #define TPS23881_REG_GEN_MASK 0x17 40 #define TPS23881_REG_CLCHE BIT(2) 41 #define TPS23881_REG_DECHE BIT(3) 42 #define TPS23881_REG_NBITACC BIT(5) 43 #define TPS23881_REG_INTEN BIT(7) 44 #define TPS23881_REG_PW_EN 0x19 45 #define TPS23881_REG_RESET 0x1a 46 #define TPS23881_REG_CLRAIN BIT(7) 47 #define TPS23881_REG_2PAIR_POL1 0x1e 48 #define TPS23881_REG_PORT_MAP 0x26 49 #define TPS23881_REG_PORT_POWER 0x29 50 #define TPS23881_REG_4PAIR_POL1 0x2a 51 #define TPS23881_REG_INPUT_V 0x2e 52 #define TPS23881_REG_CHAN1_A 0x30 53 #define TPS23881_REG_CHAN1_V 0x32 54 #define TPS23881_REG_FOLDBACK 0x40 55 #define TPS23881_REG_TPON BIT(0) 56 #define TPS23881_REG_FWREV 0x41 57 #define TPS23881_REG_DEVID 0x43 58 #define TPS23881_REG_CHAN1_CLASS 0x4c 59 #define TPS23881_REG_SRAM_CTRL 0x60 60 #define TPS23881_REG_SRAM_DATA 0x61 61 62 #define TPS23881_UV_STEP 3662 63 #define TPS23881_NA_STEP 89500 64 #define TPS23881_MW_STEP 500 65 #define TPS23881_MIN_PI_PW_LIMIT_MW 2000 66 67 struct tps23881_port_desc { 68 u8 chan[2]; 69 bool is_4p; 70 int pw_pol; 71 bool exist; 72 }; 73 74 struct tps23881_priv { 75 struct i2c_client *client; 76 struct pse_controller_dev pcdev; 77 struct device_node *np; 78 struct tps23881_port_desc port[TPS23881_MAX_CHANS]; 79 }; 80 81 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev) 82 { 83 return container_of(pcdev, struct tps23881_priv, pcdev); 84 } 85 86 /* 87 * Helper to extract a value from a u16 register value, which is made of two 88 * u8 registers. The function calculates the bit offset based on the channel 89 * and extracts the relevant bits using a provided field mask. 90 * 91 * @param reg_val: The u16 register value (composed of two u8 registers). 92 * @param chan: The channel number (0-7). 93 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 94 * @param field_mask: The mask to apply to extract the required bits. 95 * @return: The extracted value for the specific channel. 96 */ 97 static u16 tps23881_calc_val(u16 reg_val, u8 chan, u8 field_offset, 98 u16 field_mask) 99 { 100 if (chan >= 4) 101 reg_val >>= 8; 102 103 return (reg_val >> field_offset) & field_mask; 104 } 105 106 /* 107 * Helper to combine individual channel values into a u16 register value. 108 * The function sets the value for a specific channel in the appropriate 109 * position. 110 * 111 * @param reg_val: The current u16 register value. 112 * @param chan: The channel number (0-7). 113 * @param field_offset: The base bit offset to apply (e.g., 0 or 4). 114 * @param field_mask: The mask to apply for the field (e.g., 0x0F). 115 * @param field_val: The value to set for the specific channel (masked by 116 * field_mask). 117 * @return: The updated u16 register value with the channel value set. 118 */ 119 static u16 tps23881_set_val(u16 reg_val, u8 chan, u8 field_offset, 120 u16 field_mask, u16 field_val) 121 { 122 field_val &= field_mask; 123 124 if (chan < 4) { 125 reg_val &= ~(field_mask << field_offset); 126 reg_val |= (field_val << field_offset); 127 } else { 128 reg_val &= ~(field_mask << (field_offset + 8)); 129 reg_val |= (field_val << (field_offset + 8)); 130 } 131 132 return reg_val; 133 } 134 135 static int 136 tps23881_pi_set_pw_pol_limit(struct tps23881_priv *priv, int id, u8 pw_pol, 137 bool is_4p) 138 { 139 struct i2c_client *client = priv->client; 140 int ret, reg; 141 u16 val; 142 u8 chan; 143 144 chan = priv->port[id].chan[0]; 145 if (!is_4p) { 146 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 147 } else { 148 /* One chan is enough to configure the 4p PI power limit */ 149 if ((chan % 4) < 2) 150 reg = TPS23881_REG_4PAIR_POL1; 151 else 152 reg = TPS23881_REG_4PAIR_POL1 + 1; 153 } 154 155 ret = i2c_smbus_read_word_data(client, reg); 156 if (ret < 0) 157 return ret; 158 159 val = tps23881_set_val(ret, chan, 0, 0xff, pw_pol); 160 return i2c_smbus_write_word_data(client, reg, val); 161 } 162 163 static int tps23881_pi_enable_manual_pol(struct tps23881_priv *priv, int id) 164 { 165 struct i2c_client *client = priv->client; 166 int ret; 167 u8 chan; 168 u16 val; 169 170 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FOLDBACK); 171 if (ret < 0) 172 return ret; 173 174 /* No need to test if the chan is PoE4 as setting either bit for a 175 * 4P configured port disables the automatic configuration on both 176 * channels. 177 */ 178 chan = priv->port[id].chan[0]; 179 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 180 return i2c_smbus_write_byte_data(client, TPS23881_REG_FOLDBACK, val); 181 } 182 183 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id) 184 { 185 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 186 struct i2c_client *client = priv->client; 187 u8 chan; 188 u16 val; 189 int ret; 190 191 if (id >= TPS23881_MAX_CHANS) 192 return -ERANGE; 193 194 chan = priv->port[id].chan[0]; 195 val = tps23881_set_val(0, chan, 0, BIT(chan % 4), BIT(chan % 4)); 196 197 if (priv->port[id].is_4p) { 198 chan = priv->port[id].chan[1]; 199 val = tps23881_set_val(val, chan, 0, BIT(chan % 4), 200 BIT(chan % 4)); 201 } 202 203 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 204 if (ret) 205 return ret; 206 207 /* Enable DC disconnect*/ 208 chan = priv->port[id].chan[0]; 209 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN); 210 if (ret < 0) 211 return ret; 212 213 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 214 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val); 215 if (ret) 216 return ret; 217 218 return 0; 219 } 220 221 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id) 222 { 223 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 224 struct i2c_client *client = priv->client; 225 u8 chan; 226 u16 val; 227 int ret; 228 229 if (id >= TPS23881_MAX_CHANS) 230 return -ERANGE; 231 232 chan = priv->port[id].chan[0]; 233 val = tps23881_set_val(0, chan, 4, BIT(chan % 4), BIT(chan % 4)); 234 235 if (priv->port[id].is_4p) { 236 chan = priv->port[id].chan[1]; 237 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 238 BIT(chan % 4)); 239 } 240 241 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val); 242 if (ret) 243 return ret; 244 245 /* PWOFF command resets lots of register which need to be 246 * configured again. According to the datasheet "It may take upwards 247 * of 5ms after PWOFFn command for all register values to be updated" 248 */ 249 mdelay(5); 250 251 /* Disable DC disconnect*/ 252 chan = priv->port[id].chan[0]; 253 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DISC_EN); 254 if (ret < 0) 255 return ret; 256 257 val = tps23881_set_val(ret, chan, 0, 0, BIT(chan % 4)); 258 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DISC_EN, val); 259 if (ret) 260 return ret; 261 262 /* Enable detection and classification */ 263 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_CLA_EN); 264 if (ret < 0) 265 return ret; 266 267 chan = priv->port[id].chan[0]; 268 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), BIT(chan % 4)); 269 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), BIT(chan % 4)); 270 271 if (priv->port[id].is_4p) { 272 chan = priv->port[id].chan[1]; 273 val = tps23881_set_val(ret, chan, 0, BIT(chan % 4), 274 BIT(chan % 4)); 275 val = tps23881_set_val(val, chan, 4, BIT(chan % 4), 276 BIT(chan % 4)); 277 } 278 279 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 280 if (ret) 281 return ret; 282 283 /* No power policy */ 284 if (priv->port[id].pw_pol < 0) 285 return 0; 286 287 ret = tps23881_pi_enable_manual_pol(priv, id); 288 if (ret < 0) 289 return ret; 290 291 /* Set power policy */ 292 return tps23881_pi_set_pw_pol_limit(priv, id, priv->port[id].pw_pol, 293 priv->port[id].is_4p); 294 } 295 296 static int 297 tps23881_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 298 struct pse_admin_state *admin_state) 299 { 300 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 301 struct i2c_client *client = priv->client; 302 bool enabled; 303 u8 chan; 304 u16 val; 305 int ret; 306 307 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 308 if (ret < 0) 309 return ret; 310 311 chan = priv->port[id].chan[0]; 312 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 313 enabled = !!(val); 314 315 if (priv->port[id].is_4p) { 316 chan = priv->port[id].chan[1]; 317 val = tps23881_calc_val(ret, chan, 0, BIT(chan % 4)); 318 enabled &= !!(val); 319 } 320 321 /* Return enabled status only if both channel are on this state */ 322 if (enabled) 323 admin_state->c33_admin_state = 324 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 325 else 326 admin_state->c33_admin_state = 327 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 328 329 return 0; 330 } 331 332 static int 333 tps23881_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 334 struct pse_pw_status *pw_status) 335 { 336 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 337 struct i2c_client *client = priv->client; 338 bool delivering; 339 u8 chan; 340 u16 val; 341 int ret; 342 343 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS); 344 if (ret < 0) 345 return ret; 346 347 chan = priv->port[id].chan[0]; 348 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 349 delivering = !!(val); 350 351 if (priv->port[id].is_4p) { 352 chan = priv->port[id].chan[1]; 353 val = tps23881_calc_val(ret, chan, 4, BIT(chan % 4)); 354 delivering &= !!(val); 355 } 356 357 /* Return delivering status only if both channel are on this state */ 358 if (delivering) 359 pw_status->c33_pw_status = 360 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 361 else 362 pw_status->c33_pw_status = 363 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 364 365 return 0; 366 } 367 368 static int tps23881_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 369 { 370 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 371 struct i2c_client *client = priv->client; 372 int ret; 373 u64 uV; 374 375 ret = i2c_smbus_read_word_data(client, TPS23881_REG_INPUT_V); 376 if (ret < 0) 377 return ret; 378 379 uV = ret & 0x3fff; 380 uV *= TPS23881_UV_STEP; 381 382 return (int)uV; 383 } 384 385 static int 386 tps23881_pi_get_chan_current(struct tps23881_priv *priv, u8 chan) 387 { 388 struct i2c_client *client = priv->client; 389 int reg, ret; 390 u64 tmp_64; 391 392 /* Registers 0x30 to 0x3d */ 393 reg = TPS23881_REG_CHAN1_A + (chan % 4) * 4 + (chan >= 4); 394 ret = i2c_smbus_read_word_data(client, reg); 395 if (ret < 0) 396 return ret; 397 398 tmp_64 = ret & 0x3fff; 399 tmp_64 *= TPS23881_NA_STEP; 400 /* uA = nA / 1000 */ 401 tmp_64 = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000); 402 return (int)tmp_64; 403 } 404 405 static int tps23881_pi_get_pw_class(struct pse_controller_dev *pcdev, 406 int id) 407 { 408 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 409 struct i2c_client *client = priv->client; 410 int ret, reg; 411 u8 chan; 412 413 chan = priv->port[id].chan[0]; 414 reg = TPS23881_REG_CHAN1_CLASS + (chan % 4); 415 ret = i2c_smbus_read_word_data(client, reg); 416 if (ret < 0) 417 return ret; 418 419 return tps23881_calc_val(ret, chan, 4, 0x0f); 420 } 421 422 static int 423 tps23881_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 424 { 425 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 426 int ret, uV, uA; 427 u64 tmp_64; 428 u8 chan; 429 430 ret = tps23881_pi_get_voltage(&priv->pcdev, id); 431 if (ret < 0) 432 return ret; 433 uV = ret; 434 435 chan = priv->port[id].chan[0]; 436 ret = tps23881_pi_get_chan_current(priv, chan); 437 if (ret < 0) 438 return ret; 439 uA = ret; 440 441 if (priv->port[id].is_4p) { 442 chan = priv->port[id].chan[1]; 443 ret = tps23881_pi_get_chan_current(priv, chan); 444 if (ret < 0) 445 return ret; 446 uA += ret; 447 } 448 449 tmp_64 = uV; 450 tmp_64 *= uA; 451 /* mW = uV * uA / 1000000000 */ 452 return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); 453 } 454 455 static int 456 tps23881_pi_get_pw_limit_chan(struct tps23881_priv *priv, u8 chan) 457 { 458 struct i2c_client *client = priv->client; 459 int ret, reg; 460 u16 val; 461 462 reg = TPS23881_REG_2PAIR_POL1 + (chan % 4); 463 ret = i2c_smbus_read_word_data(client, reg); 464 if (ret < 0) 465 return ret; 466 467 val = tps23881_calc_val(ret, chan, 0, 0xff); 468 return val * TPS23881_MW_STEP; 469 } 470 471 static int tps23881_pi_get_pw_limit(struct pse_controller_dev *pcdev, int id) 472 { 473 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 474 int ret, mW; 475 u8 chan; 476 477 chan = priv->port[id].chan[0]; 478 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 479 if (ret < 0) 480 return ret; 481 482 mW = ret; 483 if (priv->port[id].is_4p) { 484 chan = priv->port[id].chan[1]; 485 ret = tps23881_pi_get_pw_limit_chan(priv, chan); 486 if (ret < 0) 487 return ret; 488 mW += ret; 489 } 490 491 return mW; 492 } 493 494 static int tps23881_pi_set_pw_limit(struct pse_controller_dev *pcdev, 495 int id, int max_mW) 496 { 497 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 498 u8 pw_pol; 499 int ret; 500 501 if (max_mW < TPS23881_MIN_PI_PW_LIMIT_MW || MAX_PI_PW < max_mW) { 502 dev_err(&priv->client->dev, 503 "power limit %d out of ranges [%d,%d]", 504 max_mW, TPS23881_MIN_PI_PW_LIMIT_MW, MAX_PI_PW); 505 return -ERANGE; 506 } 507 508 ret = tps23881_pi_enable_manual_pol(priv, id); 509 if (ret < 0) 510 return ret; 511 512 pw_pol = DIV_ROUND_CLOSEST_ULL(max_mW, TPS23881_MW_STEP); 513 514 /* Save power policy to reconfigure it after a disabled call */ 515 priv->port[id].pw_pol = pw_pol; 516 return tps23881_pi_set_pw_pol_limit(priv, id, pw_pol, 517 priv->port[id].is_4p); 518 } 519 520 static int 521 tps23881_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 522 struct pse_pw_limit_ranges *pw_limit_ranges) 523 { 524 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 525 526 c33_pw_limit_ranges = kzalloc_obj(*c33_pw_limit_ranges); 527 if (!c33_pw_limit_ranges) 528 return -ENOMEM; 529 530 c33_pw_limit_ranges->min = TPS23881_MIN_PI_PW_LIMIT_MW; 531 c33_pw_limit_ranges->max = MAX_PI_PW; 532 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 533 534 /* Return the number of ranges */ 535 return 1; 536 } 537 538 /* Parse managers subnode into a array of device node */ 539 static int 540 tps23881_get_of_channels(struct tps23881_priv *priv, 541 struct device_node *chan_node[TPS23881_MAX_CHANS]) 542 { 543 struct device_node *channels_node, *node; 544 int i, ret; 545 546 if (!priv->np) 547 return -EINVAL; 548 549 channels_node = of_find_node_by_name(priv->np, "channels"); 550 if (!channels_node) 551 return -EINVAL; 552 553 for_each_child_of_node(channels_node, node) { 554 u32 chan_id; 555 556 if (!of_node_name_eq(node, "channel")) 557 continue; 558 559 ret = of_property_read_u32(node, "reg", &chan_id); 560 if (ret) { 561 ret = -EINVAL; 562 goto out; 563 } 564 565 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) { 566 dev_err(&priv->client->dev, 567 "wrong number of port (%d)\n", chan_id); 568 ret = -EINVAL; 569 goto out; 570 } 571 572 of_node_get(node); 573 chan_node[chan_id] = node; 574 } 575 576 of_node_put(channels_node); 577 return 0; 578 579 out: 580 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 581 of_node_put(chan_node[i]); 582 chan_node[i] = NULL; 583 } 584 585 of_node_put(node); 586 of_node_put(channels_node); 587 return ret; 588 } 589 590 struct tps23881_port_matrix { 591 u8 pi_id; 592 u8 lgcl_chan[2]; 593 u8 hw_chan[2]; 594 bool is_4p; 595 bool exist; 596 }; 597 598 static int 599 tps23881_match_channel(const struct pse_pi_pairset *pairset, 600 struct device_node *chan_node[TPS23881_MAX_CHANS]) 601 { 602 int i; 603 604 /* Look on every channels */ 605 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 606 if (pairset->np == chan_node[i]) 607 return i; 608 } 609 610 return -ENODEV; 611 } 612 613 static bool 614 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 615 int chan) 616 { 617 int i; 618 619 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 620 if (port_matrix[i].exist && 621 (port_matrix[i].hw_chan[0] == chan || 622 port_matrix[i].hw_chan[1] == chan)) 623 return false; 624 } 625 626 return true; 627 } 628 629 /* Fill port matrix with the matching channels */ 630 static int 631 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id, 632 struct device_node *chan_node[TPS23881_MAX_CHANS], 633 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 634 { 635 int ret; 636 637 if (!pi->pairset[0].np) 638 return 0; 639 640 ret = tps23881_match_channel(&pi->pairset[0], chan_node); 641 if (ret < 0) 642 return ret; 643 644 if (!tps23881_is_chan_free(port_matrix, ret)) { 645 pr_err("tps23881: channel %d already used\n", ret); 646 return -ENODEV; 647 } 648 649 port_matrix[pi_id].hw_chan[0] = ret; 650 port_matrix[pi_id].exist = true; 651 652 if (!pi->pairset[1].np) 653 return 0; 654 655 ret = tps23881_match_channel(&pi->pairset[1], chan_node); 656 if (ret < 0) 657 return ret; 658 659 if (!tps23881_is_chan_free(port_matrix, ret)) { 660 pr_err("tps23881: channel %d already used\n", ret); 661 return -ENODEV; 662 } 663 664 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) { 665 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group"); 666 return -ENODEV; 667 } 668 669 port_matrix[pi_id].hw_chan[1] = ret; 670 port_matrix[pi_id].is_4p = true; 671 672 return 0; 673 } 674 675 static int 676 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 677 int port_cnt) 678 { 679 bool used; 680 int i, j; 681 682 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 683 used = false; 684 685 for (j = 0; j < port_cnt; j++) { 686 if (port_matrix[j].hw_chan[0] == i) { 687 used = true; 688 break; 689 } 690 691 if (port_matrix[j].is_4p && 692 port_matrix[j].hw_chan[1] == i) { 693 used = true; 694 break; 695 } 696 } 697 698 if (!used) 699 return i; 700 } 701 702 return -ENODEV; 703 } 704 705 /* Sort the port matrix to following particular hardware ports matrix 706 * specification of the tps23881. The device has two 4-ports groups and 707 * each 4-pair powered device has to be configured to use two consecutive 708 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the 709 * hardware matrix has to be fully configured even with unused chan to be 710 * valid. 711 */ 712 static int 713 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 714 { 715 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0}; 716 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4; 717 718 /* Configure 4p port matrix */ 719 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 720 int *cnt; 721 722 if (!port_matrix[i].exist || !port_matrix[i].is_4p) 723 continue; 724 725 if (port_matrix[i].hw_chan[0] < 4) 726 cnt = &cnt_4ch_grp1; 727 else 728 cnt = &cnt_4ch_grp2; 729 730 tmp_port_matrix[port_cnt].exist = true; 731 tmp_port_matrix[port_cnt].is_4p = true; 732 tmp_port_matrix[port_cnt].pi_id = i; 733 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 734 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1]; 735 736 /* 4-pair ports have to be configured with consecutive 737 * logical channels 0 and 1, 2 and 3. 738 */ 739 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 740 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++; 741 742 port_cnt++; 743 } 744 745 /* Configure 2p port matrix */ 746 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 747 int *cnt; 748 749 if (!port_matrix[i].exist || port_matrix[i].is_4p) 750 continue; 751 752 if (port_matrix[i].hw_chan[0] < 4) 753 cnt = &cnt_4ch_grp1; 754 else 755 cnt = &cnt_4ch_grp2; 756 757 tmp_port_matrix[port_cnt].exist = true; 758 tmp_port_matrix[port_cnt].pi_id = i; 759 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++; 760 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0]; 761 762 port_cnt++; 763 } 764 765 /* Complete the rest of the first 4 port group matrix even if 766 * channels are unused 767 */ 768 while (cnt_4ch_grp1 < 4) { 769 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 770 if (ret < 0) { 771 pr_err("tps23881: port matrix issue, no chan available\n"); 772 return ret; 773 } 774 775 if (port_cnt >= TPS23881_MAX_CHANS) { 776 pr_err("tps23881: wrong number of channels\n"); 777 return -ENODEV; 778 } 779 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1; 780 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 781 cnt_4ch_grp1++; 782 port_cnt++; 783 } 784 785 /* Complete the rest of the second 4 port group matrix even if 786 * channels are unused 787 */ 788 while (cnt_4ch_grp2 < 8) { 789 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt); 790 if (ret < 0) { 791 pr_err("tps23881: port matrix issue, no chan available\n"); 792 return -ENODEV; 793 } 794 795 if (port_cnt >= TPS23881_MAX_CHANS) { 796 pr_err("tps23881: wrong number of channels\n"); 797 return -ENODEV; 798 } 799 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2; 800 tmp_port_matrix[port_cnt].hw_chan[0] = ret; 801 cnt_4ch_grp2++; 802 port_cnt++; 803 } 804 805 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix)); 806 807 return port_cnt; 808 } 809 810 /* Write port matrix to the hardware port matrix and the software port 811 * matrix. 812 */ 813 static int 814 tps23881_write_port_matrix(struct tps23881_priv *priv, 815 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS], 816 int port_cnt) 817 { 818 struct i2c_client *client = priv->client; 819 u8 pi_id, lgcl_chan, hw_chan; 820 u16 val = 0; 821 int i; 822 823 for (i = 0; i < port_cnt; i++) { 824 pi_id = port_matrix[i].pi_id; 825 lgcl_chan = port_matrix[i].lgcl_chan[0]; 826 hw_chan = port_matrix[i].hw_chan[0] % 4; 827 828 /* Set software port matrix for existing ports */ 829 if (port_matrix[i].exist) { 830 priv->port[pi_id].chan[0] = lgcl_chan; 831 priv->port[pi_id].exist = true; 832 } 833 834 /* Initialize power policy internal value */ 835 priv->port[pi_id].pw_pol = -1; 836 837 /* Set hardware port matrix for all ports */ 838 val |= hw_chan << (lgcl_chan * 2); 839 840 if (!port_matrix[i].is_4p) 841 continue; 842 843 lgcl_chan = port_matrix[i].lgcl_chan[1]; 844 hw_chan = port_matrix[i].hw_chan[1] % 4; 845 846 /* Set software port matrix for existing ports */ 847 if (port_matrix[i].exist) { 848 priv->port[pi_id].is_4p = true; 849 priv->port[pi_id].chan[1] = lgcl_chan; 850 } 851 852 /* Set hardware port matrix for all ports */ 853 val |= hw_chan << (lgcl_chan * 2); 854 } 855 856 /* Write hardware ports matrix */ 857 return i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val); 858 } 859 860 static int 861 tps23881_set_ports_conf(struct tps23881_priv *priv, 862 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS]) 863 { 864 struct i2c_client *client = priv->client; 865 int i, ret; 866 u16 val; 867 868 /* Set operating mode */ 869 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE, 870 TPS23881_OP_MODE_SEMIAUTO); 871 if (ret) 872 return ret; 873 874 /* Disable DC disconnect */ 875 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0); 876 if (ret) 877 return ret; 878 879 /* Set port power allocation */ 880 val = 0; 881 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 882 if (!port_matrix[i].exist) 883 continue; 884 885 if (port_matrix[i].is_4p) 886 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 887 else 888 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4); 889 } 890 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val); 891 if (ret) 892 return ret; 893 894 /* Enable detection and classification */ 895 val = 0; 896 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 897 if (!port_matrix[i].exist) 898 continue; 899 900 val |= BIT(port_matrix[i].lgcl_chan[0]) | 901 BIT(port_matrix[i].lgcl_chan[0] + 4); 902 if (port_matrix[i].is_4p) 903 val |= BIT(port_matrix[i].lgcl_chan[1]) | 904 BIT(port_matrix[i].lgcl_chan[1] + 4); 905 } 906 return i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val); 907 } 908 909 static int 910 tps23881_set_ports_matrix(struct tps23881_priv *priv, 911 struct device_node *chan_node[TPS23881_MAX_CHANS]) 912 { 913 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0}; 914 int i, ret; 915 916 /* Update with values for every PSE PIs */ 917 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 918 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i, 919 chan_node, port_matrix); 920 if (ret) 921 return ret; 922 } 923 924 ret = tps23881_sort_port_matrix(port_matrix); 925 if (ret < 0) 926 return ret; 927 928 ret = tps23881_write_port_matrix(priv, port_matrix, ret); 929 if (ret) 930 return ret; 931 932 return tps23881_set_ports_conf(priv, port_matrix); 933 } 934 935 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev) 936 { 937 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL}; 938 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 939 int ret, i; 940 941 ret = tps23881_get_of_channels(priv, chan_node); 942 if (ret < 0) { 943 dev_warn(&priv->client->dev, 944 "Unable to parse port-matrix, default matrix will be used\n"); 945 return 0; 946 } 947 948 ret = tps23881_set_ports_matrix(priv, chan_node); 949 950 for (i = 0; i < TPS23881_MAX_CHANS; i++) 951 of_node_put(chan_node[i]); 952 953 return ret; 954 } 955 956 static int tps23881_power_class_table[] = { 957 -ERANGE, 958 4000, 959 7000, 960 15500, 961 30000, 962 15500, 963 15500, 964 -ERANGE, 965 45000, 966 60000, 967 75000, 968 90000, 969 15500, 970 45000, 971 -ERANGE, 972 -ERANGE, 973 }; 974 975 static int tps23881_pi_get_pw_req(struct pse_controller_dev *pcdev, int id) 976 { 977 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 978 struct i2c_client *client = priv->client; 979 u8 reg, chan; 980 int ret; 981 u16 val; 982 983 /* For a 4-pair the classification need 5ms to be completed */ 984 if (priv->port[id].is_4p) 985 mdelay(5); 986 987 chan = priv->port[id].chan[0]; 988 reg = TPS23881_REG_DISC + (chan % 4); 989 ret = i2c_smbus_read_word_data(client, reg); 990 if (ret < 0) 991 return ret; 992 993 val = tps23881_calc_val(ret, chan, 4, 0xf); 994 return tps23881_power_class_table[val]; 995 } 996 997 static const struct pse_controller_ops tps23881_ops = { 998 .setup_pi_matrix = tps23881_setup_pi_matrix, 999 .pi_enable = tps23881_pi_enable, 1000 .pi_disable = tps23881_pi_disable, 1001 .pi_get_admin_state = tps23881_pi_get_admin_state, 1002 .pi_get_pw_status = tps23881_pi_get_pw_status, 1003 .pi_get_pw_class = tps23881_pi_get_pw_class, 1004 .pi_get_actual_pw = tps23881_pi_get_actual_pw, 1005 .pi_get_voltage = tps23881_pi_get_voltage, 1006 .pi_get_pw_limit = tps23881_pi_get_pw_limit, 1007 .pi_set_pw_limit = tps23881_pi_set_pw_limit, 1008 .pi_get_pw_limit_ranges = tps23881_pi_get_pw_limit_ranges, 1009 .pi_get_pw_req = tps23881_pi_get_pw_req, 1010 }; 1011 1012 struct tps23881_info { 1013 u8 dev_id; /* device ID and silicon revision */ 1014 const char *fw_parity_name; /* parity code firmware file name */ 1015 const char *fw_sram_name; /* SRAM code firmware file name */ 1016 }; 1017 1018 enum tps23881_model { 1019 TPS23881, 1020 TPS23881B, 1021 }; 1022 1023 static const struct tps23881_info tps23881_info[] = { 1024 [TPS23881] = { 1025 .dev_id = 0x22, 1026 .fw_parity_name = "ti/tps23881/tps23881-parity-14.bin", 1027 .fw_sram_name = "ti/tps23881/tps23881-sram-14.bin", 1028 }, 1029 [TPS23881B] = { 1030 .dev_id = 0x24, 1031 /* skip SRAM load, ROM provides Clause 145 hardware-level support */ 1032 }, 1033 }; 1034 1035 struct tps23881_fw_conf { 1036 u8 reg; 1037 u8 val; 1038 }; 1039 1040 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = { 1041 {.reg = 0x60, .val = 0x01}, 1042 {.reg = 0x62, .val = 0x00}, 1043 {.reg = 0x63, .val = 0x80}, 1044 {.reg = 0x60, .val = 0xC4}, 1045 {.reg = 0x1D, .val = 0xBC}, 1046 {.reg = 0xD7, .val = 0x02}, 1047 {.reg = 0x91, .val = 0x00}, 1048 {.reg = 0x90, .val = 0x00}, 1049 {.reg = 0xD7, .val = 0x00}, 1050 {.reg = 0x1D, .val = 0x00}, 1051 { /* sentinel */ } 1052 }; 1053 1054 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = { 1055 {.reg = 0x60, .val = 0xC5}, 1056 {.reg = 0x62, .val = 0x00}, 1057 {.reg = 0x63, .val = 0x80}, 1058 {.reg = 0x60, .val = 0xC0}, 1059 {.reg = 0x1D, .val = 0xBC}, 1060 {.reg = 0xD7, .val = 0x02}, 1061 {.reg = 0x91, .val = 0x00}, 1062 {.reg = 0x90, .val = 0x00}, 1063 {.reg = 0xD7, .val = 0x00}, 1064 {.reg = 0x1D, .val = 0x00}, 1065 { /* sentinel */ } 1066 }; 1067 1068 static int tps23881_flash_sram_fw_part(struct i2c_client *client, 1069 const char *fw_name, 1070 const struct tps23881_fw_conf *fw_conf) 1071 { 1072 const struct firmware *fw = NULL; 1073 int i, ret; 1074 1075 ret = request_firmware(&fw, fw_name, &client->dev); 1076 if (ret) 1077 return ret; 1078 1079 dev_dbg(&client->dev, "Flashing %s\n", fw_name); 1080 1081 /* Prepare device for RAM download */ 1082 while (fw_conf->reg) { 1083 ret = i2c_smbus_write_byte_data(client, fw_conf->reg, 1084 fw_conf->val); 1085 if (ret) 1086 goto out; 1087 1088 fw_conf++; 1089 } 1090 1091 /* Flash the firmware file */ 1092 for (i = 0; i < fw->size; i++) { 1093 ret = i2c_smbus_write_byte_data(client, 1094 TPS23881_REG_SRAM_DATA, 1095 fw->data[i]); 1096 if (ret) 1097 goto out; 1098 } 1099 1100 out: 1101 release_firmware(fw); 1102 return ret; 1103 } 1104 1105 static int tps23881_flash_sram_fw(struct i2c_client *client, 1106 const struct tps23881_info *info) 1107 { 1108 int ret; 1109 1110 ret = tps23881_flash_sram_fw_part(client, info->fw_parity_name, 1111 tps23881_fw_parity_conf); 1112 if (ret) 1113 return ret; 1114 1115 ret = tps23881_flash_sram_fw_part(client, info->fw_sram_name, 1116 tps23881_fw_sram_conf); 1117 if (ret) 1118 return ret; 1119 1120 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18); 1121 if (ret) 1122 return ret; 1123 1124 mdelay(12); 1125 1126 return 0; 1127 } 1128 1129 /* Convert interrupt events to 0xff to be aligned with the chan 1130 * number. 1131 */ 1132 static u8 tps23881_irq_export_chans_helper(u16 reg_val, u8 field_offset) 1133 { 1134 u8 val; 1135 1136 val = (reg_val >> (4 + field_offset) & 0xf0) | 1137 (reg_val >> field_offset & 0x0f); 1138 1139 return val; 1140 } 1141 1142 /* Convert chan number to port number */ 1143 static void tps23881_set_notifs_helper(struct tps23881_priv *priv, 1144 u8 chans, 1145 unsigned long *notifs, 1146 unsigned long *notifs_mask, 1147 enum ethtool_pse_event event) 1148 { 1149 u8 chan; 1150 int i; 1151 1152 if (!chans) 1153 return; 1154 1155 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 1156 if (!priv->port[i].exist) 1157 continue; 1158 /* No need to look at the 2nd channel in case of PoE4 as 1159 * both registers are set. 1160 */ 1161 chan = priv->port[i].chan[0]; 1162 1163 if (BIT(chan) & chans) { 1164 *notifs_mask |= BIT(i); 1165 notifs[i] |= event; 1166 } 1167 } 1168 } 1169 1170 static void tps23881_irq_event_over_temp(struct tps23881_priv *priv, 1171 u16 reg_val, 1172 unsigned long *notifs, 1173 unsigned long *notifs_mask) 1174 { 1175 int i; 1176 1177 if (reg_val & TPS23881_REG_TSD) { 1178 for (i = 0; i < TPS23881_MAX_CHANS; i++) { 1179 if (!priv->port[i].exist) 1180 continue; 1181 1182 *notifs_mask |= BIT(i); 1183 notifs[i] |= ETHTOOL_PSE_EVENT_OVER_TEMP; 1184 } 1185 } 1186 } 1187 1188 static int tps23881_irq_event_over_current(struct tps23881_priv *priv, 1189 u16 reg_val, 1190 unsigned long *notifs, 1191 unsigned long *notifs_mask) 1192 { 1193 int i, ret; 1194 u8 chans; 1195 1196 chans = tps23881_irq_export_chans_helper(reg_val, 0); 1197 if (!chans) 1198 return 0; 1199 1200 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask, 1201 ETHTOOL_PSE_EVENT_OVER_CURRENT | 1202 ETHTOOL_C33_PSE_EVENT_DISCONNECTION); 1203 1204 /* Over Current event resets the power limit registers so we need 1205 * to configured it again. 1206 */ 1207 for_each_set_bit(i, notifs_mask, priv->pcdev.nr_lines) { 1208 if (priv->port[i].pw_pol < 0) 1209 continue; 1210 1211 ret = tps23881_pi_enable_manual_pol(priv, i); 1212 if (ret < 0) 1213 return ret; 1214 1215 /* Set power policy */ 1216 ret = tps23881_pi_set_pw_pol_limit(priv, i, 1217 priv->port[i].pw_pol, 1218 priv->port[i].is_4p); 1219 if (ret < 0) 1220 return ret; 1221 } 1222 1223 return 0; 1224 } 1225 1226 static void tps23881_irq_event_disconnection(struct tps23881_priv *priv, 1227 u16 reg_val, 1228 unsigned long *notifs, 1229 unsigned long *notifs_mask) 1230 { 1231 u8 chans; 1232 1233 chans = tps23881_irq_export_chans_helper(reg_val, 4); 1234 if (chans) 1235 tps23881_set_notifs_helper(priv, chans, notifs, notifs_mask, 1236 ETHTOOL_C33_PSE_EVENT_DISCONNECTION); 1237 } 1238 1239 static int tps23881_irq_event_detection(struct tps23881_priv *priv, 1240 u16 reg_val, 1241 unsigned long *notifs, 1242 unsigned long *notifs_mask) 1243 { 1244 enum ethtool_pse_event event; 1245 int reg, ret, i, val; 1246 unsigned long chans; 1247 1248 chans = tps23881_irq_export_chans_helper(reg_val, 0); 1249 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) { 1250 reg = TPS23881_REG_DISC + (i % 4); 1251 ret = i2c_smbus_read_word_data(priv->client, reg); 1252 if (ret < 0) 1253 return ret; 1254 1255 val = tps23881_calc_val(ret, i, 0, 0xf); 1256 /* If detection valid */ 1257 if (val == 0x4) 1258 event = ETHTOOL_C33_PSE_EVENT_DETECTION; 1259 else 1260 event = ETHTOOL_C33_PSE_EVENT_DISCONNECTION; 1261 1262 tps23881_set_notifs_helper(priv, BIT(i), notifs, 1263 notifs_mask, event); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int tps23881_irq_event_classification(struct tps23881_priv *priv, 1270 u16 reg_val, 1271 unsigned long *notifs, 1272 unsigned long *notifs_mask) 1273 { 1274 int reg, ret, val, i; 1275 unsigned long chans; 1276 1277 chans = tps23881_irq_export_chans_helper(reg_val, 4); 1278 for_each_set_bit(i, &chans, TPS23881_MAX_CHANS) { 1279 reg = TPS23881_REG_DISC + (i % 4); 1280 ret = i2c_smbus_read_word_data(priv->client, reg); 1281 if (ret < 0) 1282 return ret; 1283 1284 val = tps23881_calc_val(ret, i, 4, 0xf); 1285 /* Do not report classification event for unknown class */ 1286 if (!val || val == 0x8 || val == 0xf) 1287 continue; 1288 1289 tps23881_set_notifs_helper(priv, BIT(i), notifs, 1290 notifs_mask, 1291 ETHTOOL_C33_PSE_EVENT_CLASSIFICATION); 1292 } 1293 1294 return 0; 1295 } 1296 1297 static int tps23881_irq_event_handler(struct tps23881_priv *priv, u16 reg, 1298 unsigned long *notifs, 1299 unsigned long *notifs_mask) 1300 { 1301 struct i2c_client *client = priv->client; 1302 int ret, val; 1303 1304 /* The Supply event bit is repeated twice so we only need to read 1305 * the one from the first byte. 1306 */ 1307 if (reg & TPS23881_REG_IT_SUPF) { 1308 ret = i2c_smbus_read_word_data(client, TPS23881_REG_SUPF_EVENT); 1309 if (ret < 0) 1310 return ret; 1311 tps23881_irq_event_over_temp(priv, ret, notifs, notifs_mask); 1312 } 1313 1314 if (reg & (TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_IFAULT << 8 | 1315 TPS23881_REG_IT_DISF | TPS23881_REG_IT_DISF << 8)) { 1316 ret = i2c_smbus_read_word_data(client, TPS23881_REG_FAULT); 1317 if (ret < 0) 1318 return ret; 1319 ret = tps23881_irq_event_over_current(priv, ret, notifs, 1320 notifs_mask); 1321 if (ret) 1322 return ret; 1323 1324 tps23881_irq_event_disconnection(priv, ret, notifs, notifs_mask); 1325 } 1326 1327 if (reg & (TPS23881_REG_IT_DETC | TPS23881_REG_IT_DETC << 8 | 1328 TPS23881_REG_IT_CLASC | TPS23881_REG_IT_CLASC << 8)) { 1329 ret = i2c_smbus_read_word_data(client, TPS23881_REG_DET_EVENT); 1330 if (ret < 0) 1331 return ret; 1332 1333 val = ret; 1334 ret = tps23881_irq_event_detection(priv, val, notifs, 1335 notifs_mask); 1336 if (ret) 1337 return ret; 1338 1339 ret = tps23881_irq_event_classification(priv, val, notifs, 1340 notifs_mask); 1341 if (ret) 1342 return ret; 1343 } 1344 return 0; 1345 } 1346 1347 static int tps23881_irq_handler(int irq, struct pse_controller_dev *pcdev, 1348 unsigned long *notifs, 1349 unsigned long *notifs_mask) 1350 { 1351 struct tps23881_priv *priv = to_tps23881_priv(pcdev); 1352 struct i2c_client *client = priv->client; 1353 int ret, it_mask, retry; 1354 1355 /* Get interruption mask */ 1356 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT_MASK); 1357 if (ret < 0) 1358 return ret; 1359 it_mask = ret; 1360 1361 /* Read interrupt register until it frees the interruption pin. */ 1362 retry = 0; 1363 while (true) { 1364 if (retry > TPS23881_MAX_IRQ_RETRIES) { 1365 dev_err(&client->dev, "interrupt never freed"); 1366 return -ETIMEDOUT; 1367 } 1368 1369 ret = i2c_smbus_read_word_data(client, TPS23881_REG_IT); 1370 if (ret < 0) 1371 return ret; 1372 1373 /* No more relevant interruption */ 1374 if (!(ret & it_mask)) 1375 return 0; 1376 1377 ret = tps23881_irq_event_handler(priv, (u16)ret, notifs, 1378 notifs_mask); 1379 if (ret) 1380 return ret; 1381 1382 retry++; 1383 } 1384 return 0; 1385 } 1386 1387 static int tps23881_setup_irq(struct tps23881_priv *priv, int irq) 1388 { 1389 struct i2c_client *client = priv->client; 1390 struct pse_irq_desc irq_desc = { 1391 .name = "tps23881-irq", 1392 .map_event = tps23881_irq_handler, 1393 }; 1394 int ret; 1395 u16 val; 1396 1397 if (!irq) { 1398 dev_err(&client->dev, "interrupt is missing"); 1399 return -EINVAL; 1400 } 1401 1402 val = TPS23881_REG_IT_IFAULT | TPS23881_REG_IT_SUPF | 1403 TPS23881_REG_IT_DETC | TPS23881_REG_IT_CLASC | 1404 TPS23881_REG_IT_DISF; 1405 val |= val << 8; 1406 ret = i2c_smbus_write_word_data(client, TPS23881_REG_IT_MASK, val); 1407 if (ret) 1408 return ret; 1409 1410 ret = i2c_smbus_read_word_data(client, TPS23881_REG_GEN_MASK); 1411 if (ret < 0) 1412 return ret; 1413 1414 val = TPS23881_REG_INTEN | TPS23881_REG_CLCHE | TPS23881_REG_DECHE; 1415 val |= val << 8; 1416 val |= (u16)ret; 1417 ret = i2c_smbus_write_word_data(client, TPS23881_REG_GEN_MASK, val); 1418 if (ret < 0) 1419 return ret; 1420 1421 /* Reset interrupts registers */ 1422 ret = i2c_smbus_write_word_data(client, TPS23881_REG_RESET, 1423 TPS23881_REG_CLRAIN); 1424 if (ret < 0) 1425 return ret; 1426 1427 return devm_pse_irq_helper(&priv->pcdev, irq, 0, &irq_desc); 1428 } 1429 1430 static int tps23881_i2c_probe(struct i2c_client *client) 1431 { 1432 struct device *dev = &client->dev; 1433 const struct tps23881_info *info; 1434 struct tps23881_priv *priv; 1435 struct gpio_desc *reset; 1436 int ret; 1437 u8 val; 1438 1439 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1440 dev_err(dev, "i2c check functionality failed\n"); 1441 return -ENXIO; 1442 } 1443 1444 info = i2c_get_match_data(client); 1445 if (!info) 1446 return -EINVAL; 1447 1448 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1449 if (!priv) 1450 return -ENOMEM; 1451 1452 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1453 if (IS_ERR(reset)) 1454 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n"); 1455 1456 if (reset) { 1457 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */ 1458 usleep_range(5, 10); 1459 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */ 1460 1461 /* TPS23880 datasheet indicates the minimum time after power on reset 1462 * should be 20ms, but the document describing how to load SRAM ("How 1463 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E)) 1464 * indicates we should delay that programming by at least 50ms. So 1465 * we'll wait the entire 50ms here to ensure we're safe to go to the 1466 * SRAM loading procedure. 1467 */ 1468 msleep(50); 1469 } 1470 1471 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID); 1472 if (ret < 0) 1473 return ret; 1474 1475 if (ret != info->dev_id) { 1476 dev_err(dev, "Wrong device ID\n"); 1477 return -ENXIO; 1478 } 1479 1480 if (info->fw_sram_name) { 1481 ret = tps23881_flash_sram_fw(client, info); 1482 if (ret < 0) 1483 return ret; 1484 } 1485 1486 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV); 1487 if (ret < 0) 1488 return ret; 1489 1490 if (ret == 0xFF) { 1491 dev_err(&client->dev, "Device entered safe mode\n"); 1492 return -ENXIO; 1493 } 1494 dev_info(&client->dev, "Firmware revision 0x%x%s\n", ret, 1495 ret == 0x00 ? " (ROM firmware)" : ""); 1496 1497 /* Set configuration B, 16 bit access on a single device address */ 1498 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK); 1499 if (ret < 0) 1500 return ret; 1501 1502 val = ret | TPS23881_REG_NBITACC; 1503 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val); 1504 if (ret) 1505 return ret; 1506 1507 priv->client = client; 1508 i2c_set_clientdata(client, priv); 1509 priv->np = dev->of_node; 1510 1511 priv->pcdev.owner = THIS_MODULE; 1512 priv->pcdev.ops = &tps23881_ops; 1513 priv->pcdev.dev = dev; 1514 priv->pcdev.types = ETHTOOL_PSE_C33; 1515 priv->pcdev.nr_lines = TPS23881_MAX_CHANS; 1516 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_STATIC; 1517 ret = devm_pse_controller_register(dev, &priv->pcdev); 1518 if (ret) { 1519 return dev_err_probe(dev, ret, 1520 "failed to register PSE controller\n"); 1521 } 1522 1523 ret = tps23881_setup_irq(priv, client->irq); 1524 if (ret) 1525 return ret; 1526 1527 return ret; 1528 } 1529 1530 static const struct i2c_device_id tps23881_id[] = { 1531 { "tps23881", .driver_data = (kernel_ulong_t)&tps23881_info[TPS23881] }, 1532 { "tps23881b", .driver_data = (kernel_ulong_t)&tps23881_info[TPS23881B] }, 1533 { } 1534 }; 1535 MODULE_DEVICE_TABLE(i2c, tps23881_id); 1536 1537 static const struct of_device_id tps23881_of_match[] = { 1538 { 1539 .compatible = "ti,tps23881", 1540 .data = &tps23881_info[TPS23881] 1541 }, 1542 { 1543 .compatible = "ti,tps23881b", 1544 .data = &tps23881_info[TPS23881B] 1545 }, 1546 { }, 1547 }; 1548 MODULE_DEVICE_TABLE(of, tps23881_of_match); 1549 1550 static struct i2c_driver tps23881_driver = { 1551 .probe = tps23881_i2c_probe, 1552 .id_table = tps23881_id, 1553 .driver = { 1554 .name = "tps23881", 1555 .of_match_table = tps23881_of_match, 1556 }, 1557 }; 1558 module_i2c_driver(tps23881_driver); 1559 1560 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1561 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver"); 1562 MODULE_LICENSE("GPL"); 1563