1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for the microcontroller (MCU) fronting PSE silicon on various 4 * Realtek-based managed switches. The MCU speaks a 12-byte fixed-frame 5 * management protocol; this driver covers two generations of the 6 * protocol via a per-dialect opcode table and response parsers. 7 * 8 * Many PoE switch designs put a dedicated microcontroller in front of the 9 * actual PSE silicon: the host CPU talks to the MCU over I2C/SMBus or 10 * UART, and the MCU in turn manages the PSE chips on the board. The MCU 11 * speaks a small message-based protocol. The PSE chips themselves are not 12 * accessed directly; everything goes through MCU commands. 13 * 14 * This driver targets that architecture for the Realtek-family protocol. 15 * Two generations are supported: Gen1 being used on older switches where 16 * the MCU fronts and manages Broadcom PSE silicon; Gen2 being used with 17 * Realtek PSE silicon. The two share frame format and a sum-mod-256 18 * checksum but diverge on opcode numbers and on a few response layouts; 19 * this is handled by the per-dialect opcode table and parser hooks. 20 * 21 * Out of scope: PSE chips that are interfaced directly from the host 22 * without a management MCU, MCU designs that speak an unrelated protocol 23 * family, and "dumb PSE" modes where no host control is wired up at all. 24 * 25 * This core module implements the protocol, decoding/encoding of MCU 26 * responses, and the pse_controller_ops integration. Transport modules 27 * (realtek-pse-mcu-i2c, realtek-pse-mcu-uart) provide the send/recv 28 * callbacks. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/cleanup.h> 33 #include <linux/container_of.h> 34 #include <linux/delay.h> 35 #include <linux/gpio/consumer.h> 36 #include <linux/jiffies.h> 37 #include <linux/minmax.h> 38 #include <linux/module.h> 39 #include <linux/property.h> 40 #include <linux/pse-pd/pse.h> 41 #include <linux/unaligned.h> 42 43 #include "realtek-pse-mcu.h" 44 45 #define RTPSE_MCU_DEVICE_ID_RTL8238B 0x0138 46 #define RTPSE_MCU_DEVICE_ID_RTL8239 0x0039 47 #define RTPSE_MCU_DEVICE_ID_RTL8239C 0x0139 48 #define RTPSE_MCU_DEVICE_ID_BCM59111 0xe111 49 #define RTPSE_MCU_DEVICE_ID_BCM59121 0xe121 50 51 #define RTPSE_MCU_PORT_STS_DISABLED 0x00 52 #define RTPSE_MCU_PORT_STS_SEARCHING 0x01 53 #define RTPSE_MCU_PORT_STS_DELIVERING 0x02 54 #define RTPSE_MCU_PORT_STS_TEST 0x03 /* Gen1-only; reserved on Gen2 */ 55 #define RTPSE_MCU_PORT_STS_FAULT 0x04 56 #define RTPSE_MCU_PORT_STS_OTHER_FAULT 0x05 /* Gen1-only; reserved on Gen2 */ 57 #define RTPSE_MCU_PORT_STS_REQUESTING 0x06 58 59 /* RTPSE_MCU_PORT_SET_POWER_LIMIT_TYPE values */ 60 #define RTPSE_MCU_PORT_PW_LIMIT_TYPE_USER 0x02 61 62 #define RTPSE_MCU_MAX_PORTS 48 63 #define RTPSE_MCU_PORT_MAX_PRIORITY 3 64 65 /* Bounded resends when the MCU replies NOT_READY (busy). */ 66 #define RTPSE_MCU_NOT_READY_RETRIES 3 67 68 /* Nominal PSE rail; 802.3at/bt operating range. */ 69 #define RTPSE_MCU_PSE_VOLTAGE_UV 54000000 70 71 enum rtpse_mcu_cmd { 72 RTPSE_MCU_CMD_SET_GLOBAL_STATE, 73 RTPSE_MCU_CMD_GET_SYSTEM_INFO, 74 RTPSE_MCU_CMD_GET_EXT_CONFIG, 75 76 RTPSE_MCU_CMD_PORT_ENABLE, 77 RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_TYPE, 78 RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT, 79 RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_EXT, 80 RTPSE_MCU_CMD_PORT_SET_PRIORITY, 81 RTPSE_MCU_CMD_PORT_GET_STATUS, 82 RTPSE_MCU_CMD_PORT_GET_POWER_STATS, 83 RTPSE_MCU_CMD_PORT_GET_CONFIG, 84 RTPSE_MCU_CMD_PORT_GET_EXT_CONFIG, 85 86 RTPSE_MCU_NUM_CMDS, 87 }; 88 89 struct rtpse_mcu_opcode { 90 u8 op; 91 bool valid; 92 }; 93 94 /* Shorthand for the designated-initializer entries in dialect opcode tables. */ 95 #define RTPSE_MCU_OP(opc) { .op = (opc), .valid = true } 96 97 /* Parsed MCU response structures (decoded from rtpse_mcu_msg replies) */ 98 99 struct rtpse_mcu_info { 100 u8 max_ports; 101 bool system_enable; 102 u16 device_id; 103 u8 mcu_type; 104 }; 105 106 struct rtpse_mcu_ext_config { 107 u8 num_of_pses; 108 }; 109 110 struct rtpse_mcu_port_status { 111 u8 sts1; 112 u8 sts2; 113 u8 sts3; 114 }; 115 116 struct rtpse_mcu_port_measurement { 117 u16 voltage_raw; /* 64.45mV/LSB */ 118 u16 current_raw; /* 1mA/LSB */ 119 u16 temperature_raw; /* T(mC) = 1250 * (220 - raw) */ 120 u16 power_raw; /* 100mW/LSB */ 121 }; 122 123 struct rtpse_mcu_port_config { 124 bool enable; 125 }; 126 127 struct rtpse_mcu_port_ext_config { 128 u8 max_power; 129 u8 priority; 130 }; 131 132 struct rtpse_mcu_dialect { 133 struct rtpse_mcu_opcode opcode[RTPSE_MCU_NUM_CMDS]; 134 135 /* 136 * Response parsers for the fields that differ between dialects; each 137 * dialect supplies its own. Other responses share one layout and are 138 * decoded directly - a dialect that diverges there must add a hook, 139 * as a mismatched layout cannot be detected (the checksum still passes). 140 */ 141 void (*parse_system_info)(const u8 *payload, struct rtpse_mcu_info *info); 142 int (*parse_port_class)(const struct rtpse_mcu_port_status *status); 143 const char *(*mcu_type_str)(unsigned int mcu_type); 144 }; 145 146 struct rtpse_mcu_chip_info { 147 const char *name; 148 u32 max_mW_per_port; 149 enum rtpse_mcu_cmd pw_set_cmd; /* command used by set_pw_limit */ 150 u32 pw_set_lsb_mW; /* LSB of pw_set_cmd value, in mW */ 151 u32 pw_read_lsb_mW; /* LSB of ext_config.max_power read-back, in mW */ 152 }; 153 154 static const struct rtpse_mcu_chip_info rtl8238b_info = { 155 .max_mW_per_port = 30000, 156 .name = "RTL8238B", 157 .pw_read_lsb_mW = 200, 158 .pw_set_cmd = RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT, 159 .pw_set_lsb_mW = 200, 160 }; 161 162 static const struct rtpse_mcu_chip_info rtl8239_info = { 163 .max_mW_per_port = 90000, 164 .name = "RTL8239", 165 .pw_read_lsb_mW = 400, 166 .pw_set_cmd = RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_EXT, 167 .pw_set_lsb_mW = 400, 168 }; 169 170 static const struct rtpse_mcu_chip_info rtl8239c_info = { 171 .max_mW_per_port = 90000, 172 .name = "RTL8239C", 173 .pw_read_lsb_mW = 400, 174 .pw_set_cmd = RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_EXT, 175 .pw_set_lsb_mW = 400, 176 }; 177 178 static const struct rtpse_mcu_chip_info bcm59111_info = { 179 .max_mW_per_port = 30000, 180 .name = "BCM59111", 181 .pw_read_lsb_mW = 200, 182 .pw_set_cmd = RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT, 183 .pw_set_lsb_mW = 200, 184 }; 185 186 static const struct rtpse_mcu_chip_info bcm59121_info = { 187 /* 188 * BCM59121 is a 60W Type-3 part, but known boards run it at 802.3at 189 * and the Gen1 dialect has only the 8-bit/0.2W set command (<=51W); 190 * cap at the 30W the hardware actually offers. 191 */ 192 .max_mW_per_port = 30000, 193 .name = "BCM59121", 194 .pw_read_lsb_mW = 200, 195 .pw_set_cmd = RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT, 196 .pw_set_lsb_mW = 200, 197 }; 198 199 /* Helpers and basic functions */ 200 201 static struct rtpse_mcu_ctrl *to_rtpse_mcu_ctrl(struct pse_controller_dev *pcdev) 202 { 203 return container_of(pcdev, struct rtpse_mcu_ctrl, pcdev); 204 } 205 206 static void rtpse_mcu_msg_init(struct rtpse_mcu_msg *msg, u8 opcode) 207 { 208 memset(msg, 0xff, sizeof(*msg)); 209 msg->opcode = opcode; 210 } 211 212 static u8 rtpse_mcu_checksum(const u8 *buf, size_t len) 213 { 214 u8 sum = 0; 215 216 while (len--) 217 sum += *buf++; 218 return sum; 219 } 220 221 static int rtpse_mcu_do_xfer(struct rtpse_mcu_ctrl *pse, struct rtpse_mcu_msg *req, 222 struct rtpse_mcu_msg *resp) 223 { 224 unsigned int tries; 225 int ret; 226 227 for (tries = 0; ; tries++) { 228 scoped_guard(mutex, &pse->mutex) { 229 /* Rolling seq_num (skip 0) so a stale/all-zero reply can't match. */ 230 if (++pse->seq == 0) 231 pse->seq = 1; 232 req->seq_num = pse->seq; 233 req->checksum = rtpse_mcu_checksum((u8 *)req, RTPSE_MCU_MSG_SIZE - 1); 234 235 ret = pse->transport->send(pse, req); 236 if (ret) 237 return ret; 238 239 /* Pace the base reply delay; the transport waits its own way. */ 240 msleep(RTPSE_MCU_RESPONSE_MS); 241 242 memset(resp, 0, sizeof(*resp)); 243 ret = pse->transport->recv(pse, req, resp); 244 if (ret) 245 return ret; 246 } 247 248 /* NOT_READY: MCU busy, wants the command resent; bounded retry. */ 249 if (resp->opcode != RTPSE_MCU_OPCODE_NOT_READY || 250 tries >= RTPSE_MCU_NOT_READY_RETRIES) 251 break; 252 msleep(RTPSE_MCU_RESPONSE_MS); 253 } 254 255 /* Explicit MCU error opcodes (Gen1); map to a meaningful errno. */ 256 switch (resp->opcode) { 257 case RTPSE_MCU_OPCODE_INCOMPLETE: 258 return -EBADE; 259 case RTPSE_MCU_OPCODE_BAD_CSUM: 260 return -EBADMSG; 261 case RTPSE_MCU_OPCODE_NOT_READY: 262 return -EAGAIN; 263 } 264 265 if (resp->opcode != req->opcode || 266 resp->seq_num != req->seq_num || 267 resp->checksum != rtpse_mcu_checksum((u8 *)resp, RTPSE_MCU_MSG_SIZE - 1)) 268 return -EBADMSG; 269 270 return 0; 271 } 272 273 static int rtpse_mcu_port_query(struct rtpse_mcu_ctrl *pse, unsigned int port, u8 opcode, 274 struct rtpse_mcu_msg *resp) 275 { 276 struct rtpse_mcu_msg req; 277 int ret; 278 279 rtpse_mcu_msg_init(&req, opcode); 280 req.payload[0] = port; 281 282 ret = rtpse_mcu_do_xfer(pse, &req, resp); 283 if (ret) 284 return ret; 285 286 if (resp->payload[0] != port) 287 return -EIO; 288 289 return 0; 290 } 291 292 static int rtpse_mcu_port_cmd(struct rtpse_mcu_ctrl *pse, unsigned int port, u8 opcode, u8 arg) 293 { 294 struct rtpse_mcu_msg req, resp; 295 int ret; 296 297 rtpse_mcu_msg_init(&req, opcode); 298 req.payload[0] = port; 299 req.payload[1] = arg; 300 301 ret = rtpse_mcu_do_xfer(pse, &req, &resp); 302 if (ret) 303 return ret; 304 305 if (resp.payload[0] != port || resp.payload[1] != 0) 306 return -EIO; 307 308 return 0; 309 } 310 311 /* Global operations */ 312 313 static int rtpse_mcu_get_info(struct rtpse_mcu_ctrl *pse, struct rtpse_mcu_info *info) 314 { 315 struct rtpse_mcu_msg req, resp; 316 const struct rtpse_mcu_opcode *opc; 317 int ret; 318 319 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_GET_SYSTEM_INFO]; 320 if (!opc->valid) 321 return -EOPNOTSUPP; 322 323 rtpse_mcu_msg_init(&req, opc->op); 324 ret = rtpse_mcu_do_xfer(pse, &req, &resp); 325 if (ret) 326 return ret; 327 328 pse->dialect->parse_system_info(resp.payload, info); 329 return 0; 330 } 331 332 static int rtpse_mcu_get_ext_config(struct rtpse_mcu_ctrl *pse, struct rtpse_mcu_ext_config *config) 333 { 334 struct rtpse_mcu_msg req, resp; 335 const struct rtpse_mcu_opcode *opc; 336 int ret; 337 338 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_GET_EXT_CONFIG]; 339 if (!opc->valid) 340 return -EOPNOTSUPP; 341 342 rtpse_mcu_msg_init(&req, opc->op); 343 ret = rtpse_mcu_do_xfer(pse, &req, &resp); 344 if (ret) 345 return ret; 346 347 config->num_of_pses = resp.payload[6]; 348 349 return 0; 350 } 351 352 static int rtpse_mcu_set_global_state(struct rtpse_mcu_ctrl *pse, bool enable) 353 { 354 struct rtpse_mcu_msg req, resp; 355 const struct rtpse_mcu_opcode *opc; 356 int ret; 357 358 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_SET_GLOBAL_STATE]; 359 if (!opc->valid) 360 return -EOPNOTSUPP; 361 362 rtpse_mcu_msg_init(&req, opc->op); 363 req.payload[0] = enable ? 0x1 : 0x0; 364 365 ret = rtpse_mcu_do_xfer(pse, &req, &resp); 366 if (ret) 367 return ret; 368 369 return (resp.payload[0] == 0x0) ? 0 : -EIO; 370 } 371 372 /* Port operations */ 373 374 static int rtpse_mcu_port_get_status(struct rtpse_mcu_ctrl *pse, unsigned int port, 375 struct rtpse_mcu_port_status *status) 376 { 377 const struct rtpse_mcu_opcode *opc; 378 struct rtpse_mcu_msg resp; 379 int ret; 380 381 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_GET_STATUS]; 382 if (!opc->valid) 383 return -EOPNOTSUPP; 384 385 ret = rtpse_mcu_port_query(pse, port, opc->op, &resp); 386 if (ret) 387 return ret; 388 389 status->sts1 = resp.payload[1]; 390 status->sts2 = resp.payload[2]; 391 status->sts3 = resp.payload[3]; 392 393 return 0; 394 } 395 396 static int rtpse_mcu_port_get_measurement(struct rtpse_mcu_ctrl *pse, unsigned int port, 397 struct rtpse_mcu_port_measurement *measurement) 398 { 399 const struct rtpse_mcu_opcode *opc; 400 struct rtpse_mcu_msg resp; 401 int ret; 402 403 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_GET_POWER_STATS]; 404 if (!opc->valid) 405 return -EOPNOTSUPP; 406 407 ret = rtpse_mcu_port_query(pse, port, opc->op, &resp); 408 if (ret) 409 return ret; 410 411 measurement->voltage_raw = get_unaligned_be16(&resp.payload[1]); 412 measurement->current_raw = get_unaligned_be16(&resp.payload[3]); 413 measurement->temperature_raw = get_unaligned_be16(&resp.payload[5]); 414 measurement->power_raw = get_unaligned_be16(&resp.payload[7]); 415 416 return 0; 417 } 418 419 static int rtpse_mcu_port_get_config(struct rtpse_mcu_ctrl *pse, unsigned int port, 420 struct rtpse_mcu_port_config *config) 421 { 422 const struct rtpse_mcu_opcode *opc; 423 struct rtpse_mcu_msg resp; 424 int ret; 425 426 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_GET_CONFIG]; 427 if (!opc->valid) 428 return -EOPNOTSUPP; 429 430 ret = rtpse_mcu_port_query(pse, port, opc->op, &resp); 431 if (ret) 432 return ret; 433 434 config->enable = (resp.payload[1] == 1); 435 436 return 0; 437 } 438 439 static int rtpse_mcu_port_get_ext_config(struct rtpse_mcu_ctrl *pse, unsigned int port, 440 struct rtpse_mcu_port_ext_config *config) 441 { 442 const struct rtpse_mcu_opcode *opc; 443 struct rtpse_mcu_msg resp; 444 int ret; 445 446 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_GET_EXT_CONFIG]; 447 if (!opc->valid) 448 return -EOPNOTSUPP; 449 450 ret = rtpse_mcu_port_query(pse, port, opc->op, &resp); 451 if (ret) 452 return ret; 453 454 config->max_power = resp.payload[3]; 455 config->priority = resp.payload[4]; 456 457 return 0; 458 } 459 460 static int rtpse_mcu_port_set_state(struct rtpse_mcu_ctrl *pse, unsigned int port, bool enable) 461 { 462 const struct rtpse_mcu_opcode *opc; 463 464 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_ENABLE]; 465 if (!opc->valid) 466 return -EOPNOTSUPP; 467 468 return rtpse_mcu_port_cmd(pse, port, opc->op, enable ? 0x1 : 0x0); 469 } 470 471 /* PSE controller ops */ 472 473 static int rtpse_mcu_port_get_admin_state(struct pse_controller_dev *pcdev, int id, 474 struct pse_admin_state *admin_state) 475 { 476 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 477 struct rtpse_mcu_port_config config; 478 int ret; 479 480 ret = rtpse_mcu_port_get_config(pse, id, &config); 481 if (ret) 482 return ret; 483 484 admin_state->c33_admin_state = config.enable ? ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED : 485 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 486 return 0; 487 } 488 489 static int rtpse_mcu_port_get_pw_status(struct pse_controller_dev *pcdev, int id, 490 struct pse_pw_status *pw_status) 491 { 492 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 493 struct rtpse_mcu_port_status status; 494 int ret; 495 496 ret = rtpse_mcu_port_get_status(pse, id, &status); 497 if (ret) 498 return ret; 499 500 switch (status.sts1) { 501 case RTPSE_MCU_PORT_STS_DISABLED: 502 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 503 break; 504 case RTPSE_MCU_PORT_STS_SEARCHING: 505 case RTPSE_MCU_PORT_STS_REQUESTING: 506 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING; 507 break; 508 case RTPSE_MCU_PORT_STS_DELIVERING: 509 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 510 break; 511 case RTPSE_MCU_PORT_STS_TEST: 512 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_TEST; 513 break; 514 case RTPSE_MCU_PORT_STS_FAULT: 515 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_FAULT; 516 break; 517 case RTPSE_MCU_PORT_STS_OTHER_FAULT: 518 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT; 519 break; 520 default: 521 pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN; 522 break; 523 } 524 525 return 0; 526 } 527 528 static int rtpse_mcu_port_get_pw_class(struct pse_controller_dev *pcdev, int id) 529 { 530 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 531 struct rtpse_mcu_port_status status; 532 int ret; 533 534 ret = rtpse_mcu_port_get_status(pse, id, &status); 535 if (ret) 536 return ret; 537 538 /* 539 * As per datasheet, the classification result is only valid when in 540 * one of those operational modes, otherwise not. 541 */ 542 switch (status.sts1) { 543 case RTPSE_MCU_PORT_STS_DISABLED: 544 case RTPSE_MCU_PORT_STS_SEARCHING: 545 case RTPSE_MCU_PORT_STS_DELIVERING: 546 case RTPSE_MCU_PORT_STS_REQUESTING: 547 return pse->dialect->parse_port_class(&status); 548 default: 549 /* 550 * No class to report, return 0 instead. This is indistinguishable 551 * from a real class-0 PD but userspace disambiguates via the 552 * power status. 553 */ 554 return 0; 555 } 556 } 557 558 static int rtpse_mcu_port_get_actual_pw(struct pse_controller_dev *pcdev, int id) 559 { 560 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 561 struct rtpse_mcu_port_measurement measurement; 562 int ret; 563 564 ret = rtpse_mcu_port_get_measurement(pse, id, &measurement); 565 if (ret) 566 return ret; 567 568 /* 100mW per LSB */ 569 return measurement.power_raw * 100U; 570 } 571 572 static int rtpse_mcu_port_get_voltage(struct pse_controller_dev *pcdev, int id) 573 { 574 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 575 struct rtpse_mcu_port_measurement measurement; 576 int ret; 577 u32 uV; 578 579 ret = rtpse_mcu_port_get_measurement(pse, id, &measurement); 580 if (ret) 581 return ret; 582 583 /* 64.45mV per LSB */ 584 uV = measurement.voltage_raw * 64450U; 585 586 /* 587 * Idle ports measure 0V, which the core rejects when turning a power 588 * limit into a current limit. Fall back to the nominal rail so a limit 589 * can be set before a PD is attached. 590 */ 591 if (!uV) 592 return RTPSE_MCU_PSE_VOLTAGE_UV; 593 594 return min_t(u32, uV, INT_MAX); 595 } 596 597 static int rtpse_mcu_port_enable(struct pse_controller_dev *pcdev, int id) 598 { 599 return rtpse_mcu_port_set_state(to_rtpse_mcu_ctrl(pcdev), id, true); 600 } 601 602 static int rtpse_mcu_port_disable(struct pse_controller_dev *pcdev, int id) 603 { 604 return rtpse_mcu_port_set_state(to_rtpse_mcu_ctrl(pcdev), id, false); 605 } 606 607 static int rtpse_mcu_port_get_pw_limit(struct pse_controller_dev *pcdev, int id) 608 { 609 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 610 struct rtpse_mcu_port_ext_config config; 611 int ret; 612 613 ret = rtpse_mcu_port_get_ext_config(pse, id, &config); 614 if (ret) 615 return ret; 616 617 /* 618 * The MCU's raw max_power byte can scale above the chip's rated cap; 619 * clamp to the same bound set_pw_limit() and the advertised range use. 620 */ 621 return min_t(u32, config.max_power * pse->chip->pw_read_lsb_mW, 622 pse->chip->max_mW_per_port); 623 } 624 625 static int rtpse_mcu_port_set_pw_limit(struct pse_controller_dev *pcdev, int id, int max_mW) 626 { 627 const struct rtpse_mcu_opcode *type_opc, *val_opc; 628 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 629 const struct rtpse_mcu_chip_info *chip = pse->chip; 630 u8 prg_val; 631 int ret; 632 633 if (max_mW < 0 || max_mW > chip->max_mW_per_port) 634 return -ERANGE; 635 636 type_opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_TYPE]; 637 val_opc = &pse->dialect->opcode[chip->pw_set_cmd]; 638 /* pw_set_lsb_mW is the divisor below; reject a chip that lacks it. */ 639 if (!type_opc->valid || !val_opc->valid || !chip->pw_set_lsb_mW) 640 return -EOPNOTSUPP; 641 642 /* 643 * Round up so a sub-LSB request maps to one LSB, not silently to 0; 644 * an explicit 0 still yields 0, and LSB-aligned maxima can't overshoot. 645 */ 646 prg_val = min_t(unsigned int, DIV_ROUND_UP(max_mW, chip->pw_set_lsb_mW), U8_MAX); 647 648 /* 649 * Program the value before switching to user-defined mode. The two 650 * commands aren't atomic, but this order never leaves a stale cap: a 651 * failure keeps the previous cap, or (already user mode) the requested. 652 */ 653 ret = rtpse_mcu_port_cmd(pse, id, val_opc->op, prg_val); 654 if (ret) 655 return ret; 656 657 return rtpse_mcu_port_cmd(pse, id, type_opc->op, RTPSE_MCU_PORT_PW_LIMIT_TYPE_USER); 658 } 659 660 static int rtpse_mcu_port_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 661 struct pse_pw_limit_ranges *out) 662 { 663 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 664 struct ethtool_c33_pse_pw_limit_range *range; 665 666 range = kzalloc_obj(*range); 667 if (!range) 668 return -ENOMEM; 669 670 range[0].min = 0; 671 range[0].max = pse->chip->max_mW_per_port; 672 673 out->c33_pw_limit_ranges = range; 674 return 1; 675 } 676 677 static int rtpse_mcu_port_get_prio(struct pse_controller_dev *pcdev, int id) 678 { 679 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 680 struct rtpse_mcu_port_ext_config config; 681 int ret; 682 683 ret = rtpse_mcu_port_get_ext_config(pse, id, &config); 684 if (ret) 685 return ret; 686 687 /* Clamp to the advertised max; set_prio() and pis_prio_max use the same bound. */ 688 return min_t(u8, config.priority, RTPSE_MCU_PORT_MAX_PRIORITY); 689 } 690 691 static int rtpse_mcu_port_set_prio(struct pse_controller_dev *pcdev, int id, unsigned int prio) 692 { 693 struct rtpse_mcu_ctrl *pse = to_rtpse_mcu_ctrl(pcdev); 694 const struct rtpse_mcu_opcode *opc; 695 696 if (prio > RTPSE_MCU_PORT_MAX_PRIORITY) 697 return -ERANGE; 698 699 opc = &pse->dialect->opcode[RTPSE_MCU_CMD_PORT_SET_PRIORITY]; 700 if (!opc->valid) 701 return -EOPNOTSUPP; 702 703 return rtpse_mcu_port_cmd(pse, id, opc->op, prio); 704 } 705 706 static const struct pse_controller_ops rtpse_mcu_ops = { 707 .pi_get_admin_state = rtpse_mcu_port_get_admin_state, 708 .pi_get_pw_status = rtpse_mcu_port_get_pw_status, 709 .pi_get_pw_class = rtpse_mcu_port_get_pw_class, 710 .pi_get_actual_pw = rtpse_mcu_port_get_actual_pw, 711 .pi_enable = rtpse_mcu_port_enable, 712 .pi_disable = rtpse_mcu_port_disable, 713 .pi_get_voltage = rtpse_mcu_port_get_voltage, 714 .pi_get_pw_limit = rtpse_mcu_port_get_pw_limit, 715 .pi_set_pw_limit = rtpse_mcu_port_set_pw_limit, 716 .pi_get_pw_limit_ranges = rtpse_mcu_port_get_pw_limit_ranges, 717 .pi_get_prio = rtpse_mcu_port_get_prio, 718 .pi_set_prio = rtpse_mcu_port_set_prio, 719 }; 720 721 static int rtpse_mcu_discover(struct rtpse_mcu_ctrl *pse, struct rtpse_mcu_info *info) 722 { 723 struct rtpse_mcu_ext_config ext_config; 724 unsigned long deadline; 725 int ret; 726 727 /* 728 * A booting MCU may stay silent (-ETIMEDOUT), not ACK its address 729 * (-ENXIO / -EREMOTEIO), report not-ready (-EAGAIN), or emit a 730 * corrupt/partial frame (-EBADMSG / -EBADE). Retry those within a 731 * bounded window; other errors (e.g. -EOPNOTSUPP) are fatal and fail 732 * immediately. 733 */ 734 deadline = jiffies + msecs_to_jiffies(RTPSE_MCU_BOOT_TIMEOUT_MS); 735 do { 736 ret = rtpse_mcu_get_info(pse, info); 737 if (ret != -ETIMEDOUT && ret != -ENXIO && ret != -EREMOTEIO && 738 ret != -EAGAIN && ret != -EBADMSG && ret != -EBADE) 739 break; 740 msleep(RTPSE_MCU_BOOT_RETRY_MS); 741 } while (time_before(jiffies, deadline)); 742 if (ret) 743 return dev_err_probe(pse->dev, ret, "failed to read MCU info\n"); 744 745 switch (info->device_id) { 746 case RTPSE_MCU_DEVICE_ID_RTL8238B: 747 pse->chip = &rtl8238b_info; 748 break; 749 case RTPSE_MCU_DEVICE_ID_RTL8239: 750 pse->chip = &rtl8239_info; 751 break; 752 case RTPSE_MCU_DEVICE_ID_RTL8239C: 753 pse->chip = &rtl8239c_info; 754 break; 755 case RTPSE_MCU_DEVICE_ID_BCM59111: 756 pse->chip = &bcm59111_info; 757 break; 758 case RTPSE_MCU_DEVICE_ID_BCM59121: 759 pse->chip = &bcm59121_info; 760 break; 761 default: 762 return dev_err_probe(pse->dev, -EINVAL, "unknown PSE id 0x%x\n", 763 info->device_id); 764 } 765 766 if (!info->max_ports || info->max_ports > RTPSE_MCU_MAX_PORTS) 767 return dev_err_probe(pse->dev, -EINVAL, 768 "MCU reports invalid port count %u\n", info->max_ports); 769 770 ret = rtpse_mcu_get_ext_config(pse, &ext_config); 771 if (ret) 772 return dev_err_probe(pse->dev, ret, "failed to read MCU ext config\n"); 773 774 dev_info(pse->dev, "%s MCU, %s (id 0x%04x), %u ports across %u PSE chip(s)\n", 775 pse->dialect->mcu_type_str(info->mcu_type), pse->chip->name, 776 info->device_id, info->max_ports, ext_config.num_of_pses); 777 return 0; 778 } 779 780 static void rtpse_mcu_global_disable(void *data) 781 { 782 struct rtpse_mcu_ctrl *pse = data; 783 784 rtpse_mcu_set_global_state(pse, false); 785 } 786 787 int rtpse_mcu_register(struct rtpse_mcu_ctrl *pse) 788 { 789 const struct rtpse_mcu_match_data *match; 790 struct rtpse_mcu_info info; 791 struct gpio_desc *gpiod; 792 int ret; 793 794 BUILD_BUG_ON(sizeof(struct rtpse_mcu_msg) != RTPSE_MCU_MSG_SIZE); 795 796 ret = devm_mutex_init(pse->dev, &pse->mutex); 797 if (ret) 798 return ret; 799 800 match = device_get_match_data(pse->dev); 801 if (!match) 802 return dev_err_probe(pse->dev, -ENODEV, "missing match data\n"); 803 pse->dialect = match->dialect; 804 805 /* 806 * Catch a dialect that forgot to set one of the required hooks at 807 * probe time, rather than NULL-deref'ing later from a fast path. 808 */ 809 if (!pse->dialect || 810 !pse->dialect->parse_system_info || 811 !pse->dialect->parse_port_class || 812 !pse->dialect->mcu_type_str) 813 return dev_err_probe(pse->dev, -EINVAL, 814 "dialect for chip is incomplete\n"); 815 816 /* 817 * Release the MCU from reset before the first transaction; the 818 * boot-retry loop in discover() waits for it to answer. 819 */ 820 gpiod = devm_gpiod_get_optional(pse->dev, "reset", GPIOD_OUT_LOW); 821 if (IS_ERR(gpiod)) 822 return dev_err_probe(pse->dev, PTR_ERR(gpiod), 823 "failed to get reset gpio\n"); 824 825 ret = rtpse_mcu_discover(pse, &info); 826 if (ret) 827 return ret; 828 829 /* 830 * Some boards gate all ports through a hardware line; deassert it only 831 * after the MCU is confirmed, so a discover failure never ungates the 832 * ports. It is then left to the MCU - not re-gated on unbind or a later 833 * probe error - so a driver reload doesn't black out PoE. 834 */ 835 gpiod = devm_gpiod_get_optional(pse->dev, "disable-ports", GPIOD_OUT_LOW); 836 if (IS_ERR(gpiod)) 837 return dev_err_probe(pse->dev, PTR_ERR(gpiod), 838 "failed to get disable-ports gpio\n"); 839 840 if (!info.system_enable) { 841 ret = rtpse_mcu_set_global_state(pse, true); 842 /* Dialects without a global-state concept (e.g. Gen1) return 843 * -EOPNOTSUPP; treat that as "no separate enable required". 844 */ 845 if (ret && ret != -EOPNOTSUPP) 846 return dev_err_probe(pse->dev, ret, 847 "failed to enable PSE system\n"); 848 if (!ret) { 849 ret = devm_add_action_or_reset(pse->dev, 850 rtpse_mcu_global_disable, pse); 851 if (ret) 852 return ret; 853 } 854 } 855 856 /* 857 * Depending on the MCU firmware configuration (which might be different 858 * for every board), it isn't known whether the PoE subsystem is active or 859 * inactive by default. At this stage, the PSE chips might already deliver 860 * power to PDs without any explicit enable. 861 */ 862 863 /* pcdev.owner is set by the transport, so the registered controller 864 * pins the transport module that owns the live device, not the core. 865 */ 866 pse->pcdev.ops = &rtpse_mcu_ops; 867 pse->pcdev.dev = pse->dev; 868 pse->pcdev.types = ETHTOOL_PSE_C33; 869 pse->pcdev.nr_lines = info.max_ports; 870 pse->pcdev.pis_prio_max = RTPSE_MCU_PORT_MAX_PRIORITY; 871 pse->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC; 872 873 return devm_pse_controller_register(pse->dev, &pse->pcdev); 874 } 875 EXPORT_SYMBOL_GPL(rtpse_mcu_register); 876 877 static void rtpse_mcu_gen2_parse_system_info(const u8 *payload, struct rtpse_mcu_info *info) 878 { 879 info->max_ports = payload[1]; 880 info->system_enable = (payload[2] == 0x1); 881 info->device_id = get_unaligned_be16(&payload[3]); 882 info->mcu_type = payload[6]; 883 } 884 885 static int rtpse_mcu_gen2_parse_port_class(const struct rtpse_mcu_port_status *status) 886 { 887 /* Class lives in the upper nibble of sts2. */ 888 return FIELD_GET(GENMASK(7, 4), status->sts2); 889 } 890 891 static const char *rtpse_mcu_gen2_mcu_type_str(unsigned int mcu_type) 892 { 893 switch (mcu_type) { 894 case 0x00: return "GigaDevice GD32F310"; 895 case 0x01: return "GigaDevice GD32F230"; 896 case 0x02: return "GigaDevice GD32F303"; 897 case 0x03: return "GigaDevice GD32F103"; 898 case 0x04: return "GigaDevice GD32E103"; 899 case 0x10: return "Nuvoton M0516"; 900 case 0x11: return "Nuvoton M0564"; 901 case 0x12: return "Nuvoton NUC029"; 902 default: return "unknown"; 903 } 904 } 905 906 static void rtpse_mcu_gen1_parse_system_info(const u8 *payload, struct rtpse_mcu_info *info) 907 { 908 info->max_ports = payload[1]; 909 /* Gen1 has no explicit system_enable byte; the closest analog is the 910 * "remote enable" bit in the system-status flags at payload[7]. 911 */ 912 info->system_enable = !!(payload[7] & BIT(2)); 913 info->device_id = get_unaligned_be16(&payload[3]); 914 info->mcu_type = payload[6]; 915 } 916 917 static int rtpse_mcu_gen1_parse_port_class(const struct rtpse_mcu_port_status *status) 918 { 919 /* Gen1 puts the detected class in payload[3] (== sts3) directly. 920 * Mask to the low nibble; class is 0..8 and any high bits would be 921 * noise. 922 */ 923 return status->sts3 & 0x0f; 924 } 925 926 static const char *rtpse_mcu_gen1_mcu_type_str(unsigned int mcu_type) 927 { 928 switch (mcu_type) { 929 case 0x00: return "ST Micro ST32F100"; 930 case 0x01: return "Nuvoton M05xx LAN"; 931 case 0x02: return "ST Micro STF030C8"; 932 case 0x03: return "Nuvoton M058SAN"; 933 case 0x04: return "Nuvoton NUC122"; 934 default: return "unknown"; 935 } 936 } 937 938 /* Map each logical command the core issues to its per-dialect opcode. */ 939 static const struct rtpse_mcu_dialect rtpse_mcu_dialect_gen2 = { 940 .parse_system_info = rtpse_mcu_gen2_parse_system_info, 941 .parse_port_class = rtpse_mcu_gen2_parse_port_class, 942 .mcu_type_str = rtpse_mcu_gen2_mcu_type_str, 943 .opcode = { 944 [RTPSE_MCU_CMD_SET_GLOBAL_STATE] = RTPSE_MCU_OP(0x00), 945 [RTPSE_MCU_CMD_GET_SYSTEM_INFO] = RTPSE_MCU_OP(0x40), 946 [RTPSE_MCU_CMD_GET_EXT_CONFIG] = RTPSE_MCU_OP(0x4a), 947 948 [RTPSE_MCU_CMD_PORT_ENABLE] = RTPSE_MCU_OP(0x01), 949 [RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_TYPE] = RTPSE_MCU_OP(0x12), 950 [RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT] = RTPSE_MCU_OP(0x13), 951 [RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_EXT] = RTPSE_MCU_OP(0x14), 952 [RTPSE_MCU_CMD_PORT_SET_PRIORITY] = RTPSE_MCU_OP(0x15), 953 [RTPSE_MCU_CMD_PORT_GET_STATUS] = RTPSE_MCU_OP(0x42), 954 [RTPSE_MCU_CMD_PORT_GET_POWER_STATS] = RTPSE_MCU_OP(0x44), 955 [RTPSE_MCU_CMD_PORT_GET_CONFIG] = RTPSE_MCU_OP(0x48), 956 [RTPSE_MCU_CMD_PORT_GET_EXT_CONFIG] = RTPSE_MCU_OP(0x49), 957 }, 958 }; 959 960 static const struct rtpse_mcu_dialect rtpse_mcu_dialect_gen1 = { 961 .parse_system_info = rtpse_mcu_gen1_parse_system_info, 962 .parse_port_class = rtpse_mcu_gen1_parse_port_class, 963 .mcu_type_str = rtpse_mcu_gen1_mcu_type_str, 964 .opcode = { 965 [RTPSE_MCU_CMD_GET_SYSTEM_INFO] = RTPSE_MCU_OP(0x20), 966 [RTPSE_MCU_CMD_GET_EXT_CONFIG] = RTPSE_MCU_OP(0x2b), 967 968 [RTPSE_MCU_CMD_PORT_ENABLE] = RTPSE_MCU_OP(0x00), 969 [RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT_TYPE] = RTPSE_MCU_OP(0x15), 970 [RTPSE_MCU_CMD_PORT_SET_POWER_LIMIT] = RTPSE_MCU_OP(0x16), 971 [RTPSE_MCU_CMD_PORT_SET_PRIORITY] = RTPSE_MCU_OP(0x1a), 972 [RTPSE_MCU_CMD_PORT_GET_STATUS] = RTPSE_MCU_OP(0x21), 973 [RTPSE_MCU_CMD_PORT_GET_POWER_STATS] = RTPSE_MCU_OP(0x30), 974 [RTPSE_MCU_CMD_PORT_GET_CONFIG] = RTPSE_MCU_OP(0x25), 975 [RTPSE_MCU_CMD_PORT_GET_EXT_CONFIG] = RTPSE_MCU_OP(0x26), 976 }, 977 }; 978 979 const struct rtpse_mcu_match_data rtpse_mcu_gen1_data = { 980 .dialect = &rtpse_mcu_dialect_gen1, 981 }; 982 EXPORT_SYMBOL_GPL(rtpse_mcu_gen1_data); 983 984 const struct rtpse_mcu_match_data rtpse_mcu_gen2_data = { 985 .dialect = &rtpse_mcu_dialect_gen2, 986 }; 987 EXPORT_SYMBOL_GPL(rtpse_mcu_gen2_data); 988 989 /* Same dialect as gen2, but the MCU expects raw-I2C framing. */ 990 const struct rtpse_mcu_match_data rtpse_mcu_gen2_i2c_data = { 991 .dialect = &rtpse_mcu_dialect_gen2, 992 .native_i2c = true, 993 }; 994 EXPORT_SYMBOL_GPL(rtpse_mcu_gen2_i2c_data); 995 996 MODULE_AUTHOR("Jonas Jelonek <jelonek.jonas@gmail.com>"); 997 MODULE_DESCRIPTION("Realtek PSE MCU driver (core)"); 998 MODULE_LICENSE("GPL"); 999