1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Framework for Ethernet Power Sourcing Equipment 4 // 5 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 6 // 7 8 #include <linux/device.h> 9 #include <linux/of.h> 10 #include <linux/pse-pd/pse.h> 11 #include <linux/regulator/driver.h> 12 #include <linux/regulator/machine.h> 13 14 static DEFINE_MUTEX(pse_list_mutex); 15 static LIST_HEAD(pse_controller_list); 16 17 /** 18 * struct pse_control - a PSE control 19 * @pcdev: a pointer to the PSE controller device 20 * this PSE control belongs to 21 * @ps: PSE PI supply of the PSE control 22 * @list: list entry for the pcdev's PSE controller list 23 * @id: ID of the PSE line in the PSE controller device 24 * @refcnt: Number of gets of this pse_control 25 */ 26 struct pse_control { 27 struct pse_controller_dev *pcdev; 28 struct regulator *ps; 29 struct list_head list; 30 unsigned int id; 31 struct kref refcnt; 32 }; 33 34 static int of_load_single_pse_pi_pairset(struct device_node *node, 35 struct pse_pi *pi, 36 int pairset_num) 37 { 38 struct device_node *pairset_np; 39 const char *name; 40 int ret; 41 42 ret = of_property_read_string_index(node, "pairset-names", 43 pairset_num, &name); 44 if (ret) 45 return ret; 46 47 if (!strcmp(name, "alternative-a")) { 48 pi->pairset[pairset_num].pinout = ALTERNATIVE_A; 49 } else if (!strcmp(name, "alternative-b")) { 50 pi->pairset[pairset_num].pinout = ALTERNATIVE_B; 51 } else { 52 pr_err("pse: wrong pairset-names value %s (%pOF)\n", 53 name, node); 54 return -EINVAL; 55 } 56 57 pairset_np = of_parse_phandle(node, "pairsets", pairset_num); 58 if (!pairset_np) 59 return -ENODEV; 60 61 pi->pairset[pairset_num].np = pairset_np; 62 63 return 0; 64 } 65 66 /** 67 * of_load_pse_pi_pairsets - load PSE PI pairsets pinout and polarity 68 * @node: a pointer of the device node 69 * @pi: a pointer of the PSE PI to fill 70 * @npairsets: the number of pairsets (1 or 2) used by the PI 71 * 72 * Return: 0 on success and failure value on error 73 */ 74 static int of_load_pse_pi_pairsets(struct device_node *node, 75 struct pse_pi *pi, 76 int npairsets) 77 { 78 int i, ret; 79 80 ret = of_property_count_strings(node, "pairset-names"); 81 if (ret != npairsets) { 82 pr_err("pse: amount of pairsets and pairset-names is not equal %d != %d (%pOF)\n", 83 npairsets, ret, node); 84 return -EINVAL; 85 } 86 87 for (i = 0; i < npairsets; i++) { 88 ret = of_load_single_pse_pi_pairset(node, pi, i); 89 if (ret) 90 goto out; 91 } 92 93 if (npairsets == 2 && 94 pi->pairset[0].pinout == pi->pairset[1].pinout) { 95 pr_err("pse: two PI pairsets can not have identical pinout (%pOF)", 96 node); 97 ret = -EINVAL; 98 } 99 100 out: 101 /* If an error appears, release all the pairset device node kref */ 102 if (ret) { 103 of_node_put(pi->pairset[0].np); 104 pi->pairset[0].np = NULL; 105 of_node_put(pi->pairset[1].np); 106 pi->pairset[1].np = NULL; 107 } 108 109 return ret; 110 } 111 112 static void pse_release_pis(struct pse_controller_dev *pcdev) 113 { 114 int i; 115 116 for (i = 0; i < pcdev->nr_lines; i++) { 117 of_node_put(pcdev->pi[i].pairset[0].np); 118 of_node_put(pcdev->pi[i].pairset[1].np); 119 of_node_put(pcdev->pi[i].np); 120 } 121 kfree(pcdev->pi); 122 } 123 124 /** 125 * of_load_pse_pis - load all the PSE PIs 126 * @pcdev: a pointer to the PSE controller device 127 * 128 * Return: 0 on success and failure value on error 129 */ 130 static int of_load_pse_pis(struct pse_controller_dev *pcdev) 131 { 132 struct device_node *np = pcdev->dev->of_node; 133 struct device_node *node, *pis; 134 int ret; 135 136 if (!np) 137 return -ENODEV; 138 139 pcdev->pi = kcalloc(pcdev->nr_lines, sizeof(*pcdev->pi), GFP_KERNEL); 140 if (!pcdev->pi) 141 return -ENOMEM; 142 143 pis = of_get_child_by_name(np, "pse-pis"); 144 if (!pis) { 145 /* no description of PSE PIs */ 146 pcdev->no_of_pse_pi = true; 147 return 0; 148 } 149 150 for_each_child_of_node(pis, node) { 151 struct pse_pi pi = {0}; 152 u32 id; 153 154 if (!of_node_name_eq(node, "pse-pi")) 155 continue; 156 157 ret = of_property_read_u32(node, "reg", &id); 158 if (ret) { 159 dev_err(pcdev->dev, 160 "can't get reg property for node '%pOF'", 161 node); 162 goto out; 163 } 164 165 if (id >= pcdev->nr_lines) { 166 dev_err(pcdev->dev, 167 "reg value (%u) is out of range (%u) (%pOF)\n", 168 id, pcdev->nr_lines, node); 169 ret = -EINVAL; 170 goto out; 171 } 172 173 if (pcdev->pi[id].np) { 174 dev_err(pcdev->dev, 175 "other node with same reg value was already registered. %pOF : %pOF\n", 176 pcdev->pi[id].np, node); 177 ret = -EINVAL; 178 goto out; 179 } 180 181 ret = of_count_phandle_with_args(node, "pairsets", NULL); 182 /* npairsets is limited to value one or two */ 183 if (ret == 1 || ret == 2) { 184 ret = of_load_pse_pi_pairsets(node, &pi, ret); 185 if (ret) 186 goto out; 187 } else if (ret != ENOENT) { 188 dev_err(pcdev->dev, 189 "error: wrong number of pairsets. Should be 1 or 2, got %d (%pOF)\n", 190 ret, node); 191 ret = -EINVAL; 192 goto out; 193 } 194 195 of_node_get(node); 196 pi.np = node; 197 memcpy(&pcdev->pi[id], &pi, sizeof(pi)); 198 } 199 200 of_node_put(pis); 201 return 0; 202 203 out: 204 pse_release_pis(pcdev); 205 of_node_put(node); 206 of_node_put(pis); 207 return ret; 208 } 209 210 static int pse_pi_is_enabled(struct regulator_dev *rdev) 211 { 212 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 213 struct pse_admin_state admin_state = {0}; 214 const struct pse_controller_ops *ops; 215 int id, ret; 216 217 ops = pcdev->ops; 218 if (!ops->pi_get_admin_state) 219 return -EOPNOTSUPP; 220 221 id = rdev_get_id(rdev); 222 mutex_lock(&pcdev->lock); 223 ret = ops->pi_get_admin_state(pcdev, id, &admin_state); 224 if (ret) 225 goto out; 226 227 if (admin_state.podl_admin_state == ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED || 228 admin_state.c33_admin_state == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 229 ret = 1; 230 231 out: 232 mutex_unlock(&pcdev->lock); 233 234 return ret; 235 } 236 237 static int pse_pi_enable(struct regulator_dev *rdev) 238 { 239 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 240 const struct pse_controller_ops *ops; 241 int id, ret; 242 243 ops = pcdev->ops; 244 if (!ops->pi_enable) 245 return -EOPNOTSUPP; 246 247 id = rdev_get_id(rdev); 248 mutex_lock(&pcdev->lock); 249 ret = ops->pi_enable(pcdev, id); 250 if (!ret) 251 pcdev->pi[id].admin_state_enabled = 1; 252 mutex_unlock(&pcdev->lock); 253 254 return ret; 255 } 256 257 static int pse_pi_disable(struct regulator_dev *rdev) 258 { 259 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 260 const struct pse_controller_ops *ops; 261 int id, ret; 262 263 ops = pcdev->ops; 264 if (!ops->pi_disable) 265 return -EOPNOTSUPP; 266 267 id = rdev_get_id(rdev); 268 mutex_lock(&pcdev->lock); 269 ret = ops->pi_disable(pcdev, id); 270 if (!ret) 271 pcdev->pi[id].admin_state_enabled = 0; 272 mutex_unlock(&pcdev->lock); 273 274 return ret; 275 } 276 277 static int _pse_pi_get_voltage(struct regulator_dev *rdev) 278 { 279 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 280 const struct pse_controller_ops *ops; 281 int id; 282 283 ops = pcdev->ops; 284 if (!ops->pi_get_voltage) 285 return -EOPNOTSUPP; 286 287 id = rdev_get_id(rdev); 288 return ops->pi_get_voltage(pcdev, id); 289 } 290 291 static int pse_pi_get_voltage(struct regulator_dev *rdev) 292 { 293 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 294 int ret; 295 296 mutex_lock(&pcdev->lock); 297 ret = _pse_pi_get_voltage(rdev); 298 mutex_unlock(&pcdev->lock); 299 300 return ret; 301 } 302 303 static int pse_pi_get_current_limit(struct regulator_dev *rdev) 304 { 305 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 306 const struct pse_controller_ops *ops; 307 int id, uV, mW, ret; 308 s64 tmp_64; 309 310 ops = pcdev->ops; 311 id = rdev_get_id(rdev); 312 if (!ops->pi_get_pw_limit || !ops->pi_get_voltage) 313 return -EOPNOTSUPP; 314 315 mutex_lock(&pcdev->lock); 316 ret = ops->pi_get_pw_limit(pcdev, id); 317 if (ret < 0) 318 goto out; 319 mW = ret; 320 321 ret = pse_pi_get_voltage(rdev); 322 if (!ret) { 323 dev_err(pcdev->dev, "Voltage null\n"); 324 ret = -ERANGE; 325 goto out; 326 } 327 if (ret < 0) 328 goto out; 329 uV = ret; 330 331 tmp_64 = mW; 332 tmp_64 *= 1000000000ull; 333 /* uA = mW * 1000000000 / uV */ 334 ret = DIV_ROUND_CLOSEST_ULL(tmp_64, uV); 335 336 out: 337 mutex_unlock(&pcdev->lock); 338 return ret; 339 } 340 341 static int pse_pi_set_current_limit(struct regulator_dev *rdev, int min_uA, 342 int max_uA) 343 { 344 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 345 const struct pse_controller_ops *ops; 346 int id, mW, ret; 347 s64 tmp_64; 348 349 ops = pcdev->ops; 350 if (!ops->pi_set_pw_limit || !ops->pi_get_voltage) 351 return -EOPNOTSUPP; 352 353 if (max_uA > MAX_PI_CURRENT) 354 return -ERANGE; 355 356 id = rdev_get_id(rdev); 357 mutex_lock(&pcdev->lock); 358 ret = pse_pi_get_voltage(rdev); 359 if (!ret) { 360 dev_err(pcdev->dev, "Voltage null\n"); 361 ret = -ERANGE; 362 goto out; 363 } 364 if (ret < 0) 365 goto out; 366 367 tmp_64 = ret; 368 tmp_64 *= max_uA; 369 /* mW = uA * uV / 1000000000 */ 370 mW = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); 371 ret = ops->pi_set_pw_limit(pcdev, id, mW); 372 out: 373 mutex_unlock(&pcdev->lock); 374 375 return ret; 376 } 377 378 static const struct regulator_ops pse_pi_ops = { 379 .is_enabled = pse_pi_is_enabled, 380 .enable = pse_pi_enable, 381 .disable = pse_pi_disable, 382 .get_voltage = pse_pi_get_voltage, 383 .get_current_limit = pse_pi_get_current_limit, 384 .set_current_limit = pse_pi_set_current_limit, 385 }; 386 387 static int 388 devm_pse_pi_regulator_register(struct pse_controller_dev *pcdev, 389 char *name, int id) 390 { 391 struct regulator_init_data *rinit_data; 392 struct regulator_config rconfig = {0}; 393 struct regulator_desc *rdesc; 394 struct regulator_dev *rdev; 395 396 rinit_data = devm_kzalloc(pcdev->dev, sizeof(*rinit_data), 397 GFP_KERNEL); 398 if (!rinit_data) 399 return -ENOMEM; 400 401 rdesc = devm_kzalloc(pcdev->dev, sizeof(*rdesc), GFP_KERNEL); 402 if (!rdesc) 403 return -ENOMEM; 404 405 /* Regulator descriptor id have to be the same as its associated 406 * PSE PI id for the well functioning of the PSE controls. 407 */ 408 rdesc->id = id; 409 rdesc->name = name; 410 rdesc->type = REGULATOR_VOLTAGE; 411 rdesc->ops = &pse_pi_ops; 412 rdesc->owner = pcdev->owner; 413 414 rinit_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; 415 416 if (pcdev->ops->pi_set_pw_limit) 417 rinit_data->constraints.valid_ops_mask |= 418 REGULATOR_CHANGE_CURRENT; 419 420 rinit_data->supply_regulator = "vpwr"; 421 422 rconfig.dev = pcdev->dev; 423 rconfig.driver_data = pcdev; 424 rconfig.init_data = rinit_data; 425 426 rdev = devm_regulator_register(pcdev->dev, rdesc, &rconfig); 427 if (IS_ERR(rdev)) { 428 dev_err_probe(pcdev->dev, PTR_ERR(rdev), 429 "Failed to register regulator\n"); 430 return PTR_ERR(rdev); 431 } 432 433 pcdev->pi[id].rdev = rdev; 434 435 return 0; 436 } 437 438 /** 439 * pse_controller_register - register a PSE controller device 440 * @pcdev: a pointer to the initialized PSE controller device 441 * 442 * Return: 0 on success and failure value on error 443 */ 444 int pse_controller_register(struct pse_controller_dev *pcdev) 445 { 446 size_t reg_name_len; 447 int ret, i; 448 449 mutex_init(&pcdev->lock); 450 INIT_LIST_HEAD(&pcdev->pse_control_head); 451 452 if (!pcdev->nr_lines) 453 pcdev->nr_lines = 1; 454 455 if (!pcdev->ops->pi_get_admin_state || 456 !pcdev->ops->pi_get_pw_status) { 457 dev_err(pcdev->dev, 458 "Mandatory status report callbacks are missing"); 459 return -EINVAL; 460 } 461 462 ret = of_load_pse_pis(pcdev); 463 if (ret) 464 return ret; 465 466 if (pcdev->ops->setup_pi_matrix) { 467 ret = pcdev->ops->setup_pi_matrix(pcdev); 468 if (ret) 469 return ret; 470 } 471 472 /* Each regulator name len is pcdev dev name + 7 char + 473 * int max digit number (10) + 1 474 */ 475 reg_name_len = strlen(dev_name(pcdev->dev)) + 18; 476 477 /* Register PI regulators */ 478 for (i = 0; i < pcdev->nr_lines; i++) { 479 char *reg_name; 480 481 /* Do not register regulator for PIs not described */ 482 if (!pcdev->no_of_pse_pi && !pcdev->pi[i].np) 483 continue; 484 485 reg_name = devm_kzalloc(pcdev->dev, reg_name_len, GFP_KERNEL); 486 if (!reg_name) 487 return -ENOMEM; 488 489 snprintf(reg_name, reg_name_len, "pse-%s_pi%d", 490 dev_name(pcdev->dev), i); 491 492 ret = devm_pse_pi_regulator_register(pcdev, reg_name, i); 493 if (ret) 494 return ret; 495 } 496 497 mutex_lock(&pse_list_mutex); 498 list_add(&pcdev->list, &pse_controller_list); 499 mutex_unlock(&pse_list_mutex); 500 501 return 0; 502 } 503 EXPORT_SYMBOL_GPL(pse_controller_register); 504 505 /** 506 * pse_controller_unregister - unregister a PSE controller device 507 * @pcdev: a pointer to the PSE controller device 508 */ 509 void pse_controller_unregister(struct pse_controller_dev *pcdev) 510 { 511 pse_release_pis(pcdev); 512 mutex_lock(&pse_list_mutex); 513 list_del(&pcdev->list); 514 mutex_unlock(&pse_list_mutex); 515 } 516 EXPORT_SYMBOL_GPL(pse_controller_unregister); 517 518 static void devm_pse_controller_release(struct device *dev, void *res) 519 { 520 pse_controller_unregister(*(struct pse_controller_dev **)res); 521 } 522 523 /** 524 * devm_pse_controller_register - resource managed pse_controller_register() 525 * @dev: device that is registering this PSE controller 526 * @pcdev: a pointer to the initialized PSE controller device 527 * 528 * Managed pse_controller_register(). For PSE controllers registered by 529 * this function, pse_controller_unregister() is automatically called on 530 * driver detach. See pse_controller_register() for more information. 531 * 532 * Return: 0 on success and failure value on error 533 */ 534 int devm_pse_controller_register(struct device *dev, 535 struct pse_controller_dev *pcdev) 536 { 537 struct pse_controller_dev **pcdevp; 538 int ret; 539 540 pcdevp = devres_alloc(devm_pse_controller_release, sizeof(*pcdevp), 541 GFP_KERNEL); 542 if (!pcdevp) 543 return -ENOMEM; 544 545 ret = pse_controller_register(pcdev); 546 if (ret) { 547 devres_free(pcdevp); 548 return ret; 549 } 550 551 *pcdevp = pcdev; 552 devres_add(dev, pcdevp); 553 554 return 0; 555 } 556 EXPORT_SYMBOL_GPL(devm_pse_controller_register); 557 558 /* PSE control section */ 559 560 static void __pse_control_release(struct kref *kref) 561 { 562 struct pse_control *psec = container_of(kref, struct pse_control, 563 refcnt); 564 565 lockdep_assert_held(&pse_list_mutex); 566 567 if (psec->pcdev->pi[psec->id].admin_state_enabled) 568 regulator_disable(psec->ps); 569 devm_regulator_put(psec->ps); 570 571 module_put(psec->pcdev->owner); 572 573 list_del(&psec->list); 574 kfree(psec); 575 } 576 577 static void __pse_control_put_internal(struct pse_control *psec) 578 { 579 lockdep_assert_held(&pse_list_mutex); 580 581 kref_put(&psec->refcnt, __pse_control_release); 582 } 583 584 /** 585 * pse_control_put - free the PSE control 586 * @psec: PSE control pointer 587 */ 588 void pse_control_put(struct pse_control *psec) 589 { 590 if (IS_ERR_OR_NULL(psec)) 591 return; 592 593 mutex_lock(&pse_list_mutex); 594 __pse_control_put_internal(psec); 595 mutex_unlock(&pse_list_mutex); 596 } 597 EXPORT_SYMBOL_GPL(pse_control_put); 598 599 static struct pse_control * 600 pse_control_get_internal(struct pse_controller_dev *pcdev, unsigned int index) 601 { 602 struct pse_control *psec; 603 int ret; 604 605 lockdep_assert_held(&pse_list_mutex); 606 607 list_for_each_entry(psec, &pcdev->pse_control_head, list) { 608 if (psec->id == index) { 609 kref_get(&psec->refcnt); 610 return psec; 611 } 612 } 613 614 psec = kzalloc(sizeof(*psec), GFP_KERNEL); 615 if (!psec) 616 return ERR_PTR(-ENOMEM); 617 618 if (!try_module_get(pcdev->owner)) { 619 ret = -ENODEV; 620 goto free_psec; 621 } 622 623 psec->ps = devm_regulator_get_exclusive(pcdev->dev, 624 rdev_get_name(pcdev->pi[index].rdev)); 625 if (IS_ERR(psec->ps)) { 626 ret = PTR_ERR(psec->ps); 627 goto put_module; 628 } 629 630 ret = regulator_is_enabled(psec->ps); 631 if (ret < 0) 632 goto regulator_put; 633 634 pcdev->pi[index].admin_state_enabled = ret; 635 636 psec->pcdev = pcdev; 637 list_add(&psec->list, &pcdev->pse_control_head); 638 psec->id = index; 639 kref_init(&psec->refcnt); 640 641 return psec; 642 643 regulator_put: 644 devm_regulator_put(psec->ps); 645 put_module: 646 module_put(pcdev->owner); 647 free_psec: 648 kfree(psec); 649 650 return ERR_PTR(ret); 651 } 652 653 /** 654 * of_pse_match_pi - Find the PSE PI id matching the device node phandle 655 * @pcdev: a pointer to the PSE controller device 656 * @np: a pointer to the device node 657 * 658 * Return: id of the PSE PI, -EINVAL if not found 659 */ 660 static int of_pse_match_pi(struct pse_controller_dev *pcdev, 661 struct device_node *np) 662 { 663 int i; 664 665 for (i = 0; i < pcdev->nr_lines; i++) { 666 if (pcdev->pi[i].np == np) 667 return i; 668 } 669 670 return -EINVAL; 671 } 672 673 /** 674 * psec_id_xlate - translate pse_spec to the PSE line number according 675 * to the number of pse-cells in case of no pse_pi node 676 * @pcdev: a pointer to the PSE controller device 677 * @pse_spec: PSE line specifier as found in the device tree 678 * 679 * Return: 0 if #pse-cells = <0>. Return PSE line number otherwise. 680 */ 681 static int psec_id_xlate(struct pse_controller_dev *pcdev, 682 const struct of_phandle_args *pse_spec) 683 { 684 if (!pcdev->of_pse_n_cells) 685 return 0; 686 687 if (pcdev->of_pse_n_cells > 1 || 688 pse_spec->args[0] >= pcdev->nr_lines) 689 return -EINVAL; 690 691 return pse_spec->args[0]; 692 } 693 694 struct pse_control *of_pse_control_get(struct device_node *node) 695 { 696 struct pse_controller_dev *r, *pcdev; 697 struct of_phandle_args args; 698 struct pse_control *psec; 699 int psec_id; 700 int ret; 701 702 if (!node) 703 return ERR_PTR(-EINVAL); 704 705 ret = of_parse_phandle_with_args(node, "pses", "#pse-cells", 0, &args); 706 if (ret) 707 return ERR_PTR(ret); 708 709 mutex_lock(&pse_list_mutex); 710 pcdev = NULL; 711 list_for_each_entry(r, &pse_controller_list, list) { 712 if (!r->no_of_pse_pi) { 713 ret = of_pse_match_pi(r, args.np); 714 if (ret >= 0) { 715 pcdev = r; 716 psec_id = ret; 717 break; 718 } 719 } else if (args.np == r->dev->of_node) { 720 pcdev = r; 721 break; 722 } 723 } 724 725 if (!pcdev) { 726 psec = ERR_PTR(-EPROBE_DEFER); 727 goto out; 728 } 729 730 if (WARN_ON(args.args_count != pcdev->of_pse_n_cells)) { 731 psec = ERR_PTR(-EINVAL); 732 goto out; 733 } 734 735 if (pcdev->no_of_pse_pi) { 736 psec_id = psec_id_xlate(pcdev, &args); 737 if (psec_id < 0) { 738 psec = ERR_PTR(psec_id); 739 goto out; 740 } 741 } 742 743 /* pse_list_mutex also protects the pcdev's pse_control list */ 744 psec = pse_control_get_internal(pcdev, psec_id); 745 746 out: 747 mutex_unlock(&pse_list_mutex); 748 of_node_put(args.np); 749 750 return psec; 751 } 752 EXPORT_SYMBOL_GPL(of_pse_control_get); 753 754 /** 755 * pse_ethtool_get_status - get status of PSE control 756 * @psec: PSE control pointer 757 * @extack: extack for reporting useful error messages 758 * @status: struct to store PSE status 759 * 760 * Return: 0 on success and failure value on error 761 */ 762 int pse_ethtool_get_status(struct pse_control *psec, 763 struct netlink_ext_ack *extack, 764 struct ethtool_pse_control_status *status) 765 { 766 struct pse_admin_state admin_state = {0}; 767 struct pse_pw_status pw_status = {0}; 768 const struct pse_controller_ops *ops; 769 struct pse_controller_dev *pcdev; 770 int ret; 771 772 pcdev = psec->pcdev; 773 ops = pcdev->ops; 774 mutex_lock(&pcdev->lock); 775 ret = ops->pi_get_admin_state(pcdev, psec->id, &admin_state); 776 if (ret) 777 goto out; 778 status->podl_admin_state = admin_state.podl_admin_state; 779 status->c33_admin_state = admin_state.c33_admin_state; 780 781 ret = ops->pi_get_pw_status(pcdev, psec->id, &pw_status); 782 if (ret) 783 goto out; 784 status->podl_pw_status = pw_status.podl_pw_status; 785 status->c33_pw_status = pw_status.c33_pw_status; 786 787 if (ops->pi_get_ext_state) { 788 struct pse_ext_state_info ext_state_info = {0}; 789 790 ret = ops->pi_get_ext_state(pcdev, psec->id, 791 &ext_state_info); 792 if (ret) 793 goto out; 794 795 memcpy(&status->c33_ext_state_info, 796 &ext_state_info.c33_ext_state_info, 797 sizeof(status->c33_ext_state_info)); 798 } 799 800 if (ops->pi_get_pw_class) { 801 ret = ops->pi_get_pw_class(pcdev, psec->id); 802 if (ret < 0) 803 goto out; 804 805 status->c33_pw_class = ret; 806 } 807 808 if (ops->pi_get_actual_pw) { 809 ret = ops->pi_get_actual_pw(pcdev, psec->id); 810 if (ret < 0) 811 goto out; 812 813 status->c33_actual_pw = ret; 814 } 815 816 if (ops->pi_get_pw_limit) { 817 ret = ops->pi_get_pw_limit(pcdev, psec->id); 818 if (ret < 0) 819 goto out; 820 821 status->c33_avail_pw_limit = ret; 822 } 823 824 if (ops->pi_get_pw_limit_ranges) { 825 struct pse_pw_limit_ranges pw_limit_ranges = {0}; 826 827 ret = ops->pi_get_pw_limit_ranges(pcdev, psec->id, 828 &pw_limit_ranges); 829 if (ret < 0) 830 goto out; 831 832 status->c33_pw_limit_ranges = 833 pw_limit_ranges.c33_pw_limit_ranges; 834 status->c33_pw_limit_nb_ranges = ret; 835 } 836 out: 837 mutex_unlock(&psec->pcdev->lock); 838 return ret; 839 } 840 EXPORT_SYMBOL_GPL(pse_ethtool_get_status); 841 842 static int pse_ethtool_c33_set_config(struct pse_control *psec, 843 const struct pse_control_config *config) 844 { 845 int err = 0; 846 847 /* Look at admin_state_enabled status to not call regulator_enable 848 * or regulator_disable twice creating a regulator counter mismatch 849 */ 850 switch (config->c33_admin_control) { 851 case ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED: 852 /* We could have mismatch between admin_state_enabled and 853 * state reported by regulator_is_enabled. This can occur when 854 * the PI is forcibly turn off by the controller. Call 855 * regulator_disable on that case to fix the counters state. 856 */ 857 if (psec->pcdev->pi[psec->id].admin_state_enabled && 858 !regulator_is_enabled(psec->ps)) { 859 err = regulator_disable(psec->ps); 860 if (err) 861 break; 862 } 863 if (!psec->pcdev->pi[psec->id].admin_state_enabled) 864 err = regulator_enable(psec->ps); 865 break; 866 case ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED: 867 if (psec->pcdev->pi[psec->id].admin_state_enabled) 868 err = regulator_disable(psec->ps); 869 break; 870 default: 871 err = -EOPNOTSUPP; 872 } 873 874 return err; 875 } 876 877 static int pse_ethtool_podl_set_config(struct pse_control *psec, 878 const struct pse_control_config *config) 879 { 880 int err = 0; 881 882 /* Look at admin_state_enabled status to not call regulator_enable 883 * or regulator_disable twice creating a regulator counter mismatch 884 */ 885 switch (config->podl_admin_control) { 886 case ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED: 887 if (!psec->pcdev->pi[psec->id].admin_state_enabled) 888 err = regulator_enable(psec->ps); 889 break; 890 case ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED: 891 if (psec->pcdev->pi[psec->id].admin_state_enabled) 892 err = regulator_disable(psec->ps); 893 break; 894 default: 895 err = -EOPNOTSUPP; 896 } 897 898 return err; 899 } 900 901 /** 902 * pse_ethtool_set_config - set PSE control configuration 903 * @psec: PSE control pointer 904 * @extack: extack for reporting useful error messages 905 * @config: Configuration of the test to run 906 * 907 * Return: 0 on success and failure value on error 908 */ 909 int pse_ethtool_set_config(struct pse_control *psec, 910 struct netlink_ext_ack *extack, 911 const struct pse_control_config *config) 912 { 913 int err = 0; 914 915 if (pse_has_c33(psec) && config->c33_admin_control) { 916 err = pse_ethtool_c33_set_config(psec, config); 917 if (err) 918 return err; 919 } 920 921 if (pse_has_podl(psec) && config->podl_admin_control) 922 err = pse_ethtool_podl_set_config(psec, config); 923 924 return err; 925 } 926 EXPORT_SYMBOL_GPL(pse_ethtool_set_config); 927 928 /** 929 * pse_ethtool_set_pw_limit - set PSE control power limit 930 * @psec: PSE control pointer 931 * @extack: extack for reporting useful error messages 932 * @pw_limit: power limit value in mW 933 * 934 * Return: 0 on success and failure value on error 935 */ 936 int pse_ethtool_set_pw_limit(struct pse_control *psec, 937 struct netlink_ext_ack *extack, 938 const unsigned int pw_limit) 939 { 940 int uV, uA, ret; 941 s64 tmp_64; 942 943 if (pw_limit > MAX_PI_PW) 944 return -ERANGE; 945 946 ret = regulator_get_voltage(psec->ps); 947 if (!ret) { 948 NL_SET_ERR_MSG(extack, 949 "Can't calculate the current, PSE voltage read is 0"); 950 return -ERANGE; 951 } 952 if (ret < 0) { 953 NL_SET_ERR_MSG(extack, 954 "Error reading PSE voltage"); 955 return ret; 956 } 957 uV = ret; 958 959 tmp_64 = pw_limit; 960 tmp_64 *= 1000000000ull; 961 /* uA = mW * 1000000000 / uV */ 962 uA = DIV_ROUND_CLOSEST_ULL(tmp_64, uV); 963 964 return regulator_set_current_limit(psec->ps, 0, uA); 965 } 966 EXPORT_SYMBOL_GPL(pse_ethtool_set_pw_limit); 967 968 bool pse_has_podl(struct pse_control *psec) 969 { 970 return psec->pcdev->types & ETHTOOL_PSE_PODL; 971 } 972 EXPORT_SYMBOL_GPL(pse_has_podl); 973 974 bool pse_has_c33(struct pse_control *psec) 975 { 976 return psec->pcdev->types & ETHTOOL_PSE_C33; 977 } 978 EXPORT_SYMBOL_GPL(pse_has_c33); 979