1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Framework for Ethernet Power Sourcing Equipment 4 // 5 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 6 // 7 8 #include <linux/device.h> 9 #include <linux/of.h> 10 #include <linux/pse-pd/pse.h> 11 #include <linux/regulator/driver.h> 12 #include <linux/regulator/machine.h> 13 14 static DEFINE_MUTEX(pse_list_mutex); 15 static LIST_HEAD(pse_controller_list); 16 17 /** 18 * struct pse_control - a PSE control 19 * @pcdev: a pointer to the PSE controller device 20 * this PSE control belongs to 21 * @ps: PSE PI supply of the PSE control 22 * @list: list entry for the pcdev's PSE controller list 23 * @id: ID of the PSE line in the PSE controller device 24 * @refcnt: Number of gets of this pse_control 25 */ 26 struct pse_control { 27 struct pse_controller_dev *pcdev; 28 struct regulator *ps; 29 struct list_head list; 30 unsigned int id; 31 struct kref refcnt; 32 }; 33 34 static int of_load_single_pse_pi_pairset(struct device_node *node, 35 struct pse_pi *pi, 36 int pairset_num) 37 { 38 struct device_node *pairset_np; 39 const char *name; 40 int ret; 41 42 ret = of_property_read_string_index(node, "pairset-names", 43 pairset_num, &name); 44 if (ret) 45 return ret; 46 47 if (!strcmp(name, "alternative-a")) { 48 pi->pairset[pairset_num].pinout = ALTERNATIVE_A; 49 } else if (!strcmp(name, "alternative-b")) { 50 pi->pairset[pairset_num].pinout = ALTERNATIVE_B; 51 } else { 52 pr_err("pse: wrong pairset-names value %s (%pOF)\n", 53 name, node); 54 return -EINVAL; 55 } 56 57 pairset_np = of_parse_phandle(node, "pairsets", pairset_num); 58 if (!pairset_np) 59 return -ENODEV; 60 61 pi->pairset[pairset_num].np = pairset_np; 62 63 return 0; 64 } 65 66 /** 67 * of_load_pse_pi_pairsets - load PSE PI pairsets pinout and polarity 68 * @node: a pointer of the device node 69 * @pi: a pointer of the PSE PI to fill 70 * @npairsets: the number of pairsets (1 or 2) used by the PI 71 * 72 * Return: 0 on success and failure value on error 73 */ 74 static int of_load_pse_pi_pairsets(struct device_node *node, 75 struct pse_pi *pi, 76 int npairsets) 77 { 78 int i, ret; 79 80 ret = of_property_count_strings(node, "pairset-names"); 81 if (ret != npairsets) { 82 pr_err("pse: amount of pairsets and pairset-names is not equal %d != %d (%pOF)\n", 83 npairsets, ret, node); 84 return -EINVAL; 85 } 86 87 for (i = 0; i < npairsets; i++) { 88 ret = of_load_single_pse_pi_pairset(node, pi, i); 89 if (ret) 90 goto out; 91 } 92 93 if (npairsets == 2 && 94 pi->pairset[0].pinout == pi->pairset[1].pinout) { 95 pr_err("pse: two PI pairsets can not have identical pinout (%pOF)", 96 node); 97 ret = -EINVAL; 98 } 99 100 out: 101 /* If an error appears, release all the pairset device node kref */ 102 if (ret) { 103 of_node_put(pi->pairset[0].np); 104 pi->pairset[0].np = NULL; 105 of_node_put(pi->pairset[1].np); 106 pi->pairset[1].np = NULL; 107 } 108 109 return ret; 110 } 111 112 static void pse_release_pis(struct pse_controller_dev *pcdev) 113 { 114 int i; 115 116 for (i = 0; i < pcdev->nr_lines; i++) { 117 of_node_put(pcdev->pi[i].pairset[0].np); 118 of_node_put(pcdev->pi[i].pairset[1].np); 119 of_node_put(pcdev->pi[i].np); 120 } 121 kfree(pcdev->pi); 122 } 123 124 /** 125 * of_load_pse_pis - load all the PSE PIs 126 * @pcdev: a pointer to the PSE controller device 127 * 128 * Return: 0 on success and failure value on error 129 */ 130 static int of_load_pse_pis(struct pse_controller_dev *pcdev) 131 { 132 struct device_node *np = pcdev->dev->of_node; 133 struct device_node *node, *pis; 134 int ret; 135 136 if (!np) 137 return -ENODEV; 138 139 pcdev->pi = kcalloc(pcdev->nr_lines, sizeof(*pcdev->pi), GFP_KERNEL); 140 if (!pcdev->pi) 141 return -ENOMEM; 142 143 pis = of_get_child_by_name(np, "pse-pis"); 144 if (!pis) { 145 /* no description of PSE PIs */ 146 pcdev->no_of_pse_pi = true; 147 return 0; 148 } 149 150 for_each_child_of_node(pis, node) { 151 struct pse_pi pi = {0}; 152 u32 id; 153 154 if (!of_node_name_eq(node, "pse-pi")) 155 continue; 156 157 ret = of_property_read_u32(node, "reg", &id); 158 if (ret) { 159 dev_err(pcdev->dev, 160 "can't get reg property for node '%pOF'", 161 node); 162 goto out; 163 } 164 165 if (id >= pcdev->nr_lines) { 166 dev_err(pcdev->dev, 167 "reg value (%u) is out of range (%u) (%pOF)\n", 168 id, pcdev->nr_lines, node); 169 ret = -EINVAL; 170 goto out; 171 } 172 173 if (pcdev->pi[id].np) { 174 dev_err(pcdev->dev, 175 "other node with same reg value was already registered. %pOF : %pOF\n", 176 pcdev->pi[id].np, node); 177 ret = -EINVAL; 178 goto out; 179 } 180 181 ret = of_count_phandle_with_args(node, "pairsets", NULL); 182 /* npairsets is limited to value one or two */ 183 if (ret == 1 || ret == 2) { 184 ret = of_load_pse_pi_pairsets(node, &pi, ret); 185 if (ret) 186 goto out; 187 } else if (ret != ENOENT) { 188 dev_err(pcdev->dev, 189 "error: wrong number of pairsets. Should be 1 or 2, got %d (%pOF)\n", 190 ret, node); 191 ret = -EINVAL; 192 goto out; 193 } 194 195 of_node_get(node); 196 pi.np = node; 197 memcpy(&pcdev->pi[id], &pi, sizeof(pi)); 198 } 199 200 of_node_put(pis); 201 return 0; 202 203 out: 204 pse_release_pis(pcdev); 205 of_node_put(node); 206 of_node_put(pis); 207 return ret; 208 } 209 210 static int pse_pi_is_enabled(struct regulator_dev *rdev) 211 { 212 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 213 struct pse_admin_state admin_state = {0}; 214 const struct pse_controller_ops *ops; 215 int id, ret; 216 217 ops = pcdev->ops; 218 if (!ops->pi_get_admin_state) 219 return -EOPNOTSUPP; 220 221 id = rdev_get_id(rdev); 222 mutex_lock(&pcdev->lock); 223 ret = ops->pi_get_admin_state(pcdev, id, &admin_state); 224 if (ret) 225 goto out; 226 227 if (admin_state.podl_admin_state == ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED || 228 admin_state.c33_admin_state == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 229 ret = 1; 230 231 out: 232 mutex_unlock(&pcdev->lock); 233 234 return ret; 235 } 236 237 static int pse_pi_enable(struct regulator_dev *rdev) 238 { 239 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 240 const struct pse_controller_ops *ops; 241 int id, ret; 242 243 ops = pcdev->ops; 244 if (!ops->pi_enable) 245 return -EOPNOTSUPP; 246 247 id = rdev_get_id(rdev); 248 mutex_lock(&pcdev->lock); 249 ret = ops->pi_enable(pcdev, id); 250 if (!ret) 251 pcdev->pi[id].admin_state_enabled = 1; 252 mutex_unlock(&pcdev->lock); 253 254 return ret; 255 } 256 257 static int pse_pi_disable(struct regulator_dev *rdev) 258 { 259 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 260 const struct pse_controller_ops *ops; 261 int id, ret; 262 263 ops = pcdev->ops; 264 if (!ops->pi_disable) 265 return -EOPNOTSUPP; 266 267 id = rdev_get_id(rdev); 268 mutex_lock(&pcdev->lock); 269 ret = ops->pi_disable(pcdev, id); 270 if (!ret) 271 pcdev->pi[id].admin_state_enabled = 0; 272 mutex_unlock(&pcdev->lock); 273 274 return ret; 275 } 276 277 static int _pse_pi_get_voltage(struct regulator_dev *rdev) 278 { 279 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 280 const struct pse_controller_ops *ops; 281 int id; 282 283 ops = pcdev->ops; 284 if (!ops->pi_get_voltage) 285 return -EOPNOTSUPP; 286 287 id = rdev_get_id(rdev); 288 return ops->pi_get_voltage(pcdev, id); 289 } 290 291 static int pse_pi_get_voltage(struct regulator_dev *rdev) 292 { 293 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 294 int ret; 295 296 mutex_lock(&pcdev->lock); 297 ret = _pse_pi_get_voltage(rdev); 298 mutex_unlock(&pcdev->lock); 299 300 return ret; 301 } 302 303 static int pse_pi_get_current_limit(struct regulator_dev *rdev) 304 { 305 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 306 const struct pse_controller_ops *ops; 307 int id, uV, mW, ret; 308 s64 tmp_64; 309 310 ops = pcdev->ops; 311 id = rdev_get_id(rdev); 312 if (!ops->pi_get_pw_limit || !ops->pi_get_voltage) 313 return -EOPNOTSUPP; 314 315 mutex_lock(&pcdev->lock); 316 ret = ops->pi_get_pw_limit(pcdev, id); 317 if (ret < 0) 318 goto out; 319 mW = ret; 320 321 ret = pse_pi_get_voltage(rdev); 322 if (!ret) { 323 dev_err(pcdev->dev, "Voltage null\n"); 324 ret = -ERANGE; 325 goto out; 326 } 327 if (ret < 0) 328 goto out; 329 uV = ret; 330 331 tmp_64 = mW; 332 tmp_64 *= 1000000000ull; 333 /* uA = mW * 1000000000 / uV */ 334 ret = DIV_ROUND_CLOSEST_ULL(tmp_64, uV); 335 336 out: 337 mutex_unlock(&pcdev->lock); 338 return ret; 339 } 340 341 static int pse_pi_set_current_limit(struct regulator_dev *rdev, int min_uA, 342 int max_uA) 343 { 344 struct pse_controller_dev *pcdev = rdev_get_drvdata(rdev); 345 const struct pse_controller_ops *ops; 346 int id, mW, ret; 347 s64 tmp_64; 348 349 ops = pcdev->ops; 350 if (!ops->pi_set_pw_limit || !ops->pi_get_voltage) 351 return -EOPNOTSUPP; 352 353 if (max_uA > MAX_PI_CURRENT) 354 return -ERANGE; 355 356 id = rdev_get_id(rdev); 357 mutex_lock(&pcdev->lock); 358 ret = pse_pi_get_voltage(rdev); 359 if (!ret) { 360 dev_err(pcdev->dev, "Voltage null\n"); 361 ret = -ERANGE; 362 goto out; 363 } 364 if (ret < 0) 365 goto out; 366 367 tmp_64 = ret; 368 tmp_64 *= max_uA; 369 /* mW = uA * uV / 1000000000 */ 370 mW = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000); 371 ret = ops->pi_set_pw_limit(pcdev, id, mW); 372 out: 373 mutex_unlock(&pcdev->lock); 374 375 return ret; 376 } 377 378 static const struct regulator_ops pse_pi_ops = { 379 .is_enabled = pse_pi_is_enabled, 380 .enable = pse_pi_enable, 381 .disable = pse_pi_disable, 382 .get_voltage = pse_pi_get_voltage, 383 .get_current_limit = pse_pi_get_current_limit, 384 .set_current_limit = pse_pi_set_current_limit, 385 }; 386 387 static int 388 devm_pse_pi_regulator_register(struct pse_controller_dev *pcdev, 389 char *name, int id) 390 { 391 struct regulator_init_data *rinit_data; 392 struct regulator_config rconfig = {0}; 393 struct regulator_desc *rdesc; 394 struct regulator_dev *rdev; 395 396 rinit_data = devm_kzalloc(pcdev->dev, sizeof(*rinit_data), 397 GFP_KERNEL); 398 if (!rinit_data) 399 return -ENOMEM; 400 401 rdesc = devm_kzalloc(pcdev->dev, sizeof(*rdesc), GFP_KERNEL); 402 if (!rdesc) 403 return -ENOMEM; 404 405 /* Regulator descriptor id have to be the same as its associated 406 * PSE PI id for the well functioning of the PSE controls. 407 */ 408 rdesc->id = id; 409 rdesc->name = name; 410 rdesc->type = REGULATOR_VOLTAGE; 411 rdesc->ops = &pse_pi_ops; 412 rdesc->owner = pcdev->owner; 413 414 rinit_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; 415 416 if (pcdev->ops->pi_set_pw_limit) 417 rinit_data->constraints.valid_ops_mask |= 418 REGULATOR_CHANGE_CURRENT; 419 420 rinit_data->supply_regulator = "vpwr"; 421 422 rconfig.dev = pcdev->dev; 423 rconfig.driver_data = pcdev; 424 rconfig.init_data = rinit_data; 425 rconfig.of_node = pcdev->pi[id].np; 426 427 rdev = devm_regulator_register(pcdev->dev, rdesc, &rconfig); 428 if (IS_ERR(rdev)) { 429 dev_err_probe(pcdev->dev, PTR_ERR(rdev), 430 "Failed to register regulator\n"); 431 return PTR_ERR(rdev); 432 } 433 434 pcdev->pi[id].rdev = rdev; 435 436 return 0; 437 } 438 439 /** 440 * pse_controller_register - register a PSE controller device 441 * @pcdev: a pointer to the initialized PSE controller device 442 * 443 * Return: 0 on success and failure value on error 444 */ 445 int pse_controller_register(struct pse_controller_dev *pcdev) 446 { 447 size_t reg_name_len; 448 int ret, i; 449 450 mutex_init(&pcdev->lock); 451 INIT_LIST_HEAD(&pcdev->pse_control_head); 452 453 if (!pcdev->nr_lines) 454 pcdev->nr_lines = 1; 455 456 if (!pcdev->ops->pi_get_admin_state || 457 !pcdev->ops->pi_get_pw_status) { 458 dev_err(pcdev->dev, 459 "Mandatory status report callbacks are missing"); 460 return -EINVAL; 461 } 462 463 ret = of_load_pse_pis(pcdev); 464 if (ret) 465 return ret; 466 467 if (pcdev->ops->setup_pi_matrix) { 468 ret = pcdev->ops->setup_pi_matrix(pcdev); 469 if (ret) 470 return ret; 471 } 472 473 /* Each regulator name len is pcdev dev name + 7 char + 474 * int max digit number (10) + 1 475 */ 476 reg_name_len = strlen(dev_name(pcdev->dev)) + 18; 477 478 /* Register PI regulators */ 479 for (i = 0; i < pcdev->nr_lines; i++) { 480 char *reg_name; 481 482 /* Do not register regulator for PIs not described */ 483 if (!pcdev->no_of_pse_pi && !pcdev->pi[i].np) 484 continue; 485 486 reg_name = devm_kzalloc(pcdev->dev, reg_name_len, GFP_KERNEL); 487 if (!reg_name) 488 return -ENOMEM; 489 490 snprintf(reg_name, reg_name_len, "pse-%s_pi%d", 491 dev_name(pcdev->dev), i); 492 493 ret = devm_pse_pi_regulator_register(pcdev, reg_name, i); 494 if (ret) 495 return ret; 496 } 497 498 mutex_lock(&pse_list_mutex); 499 list_add(&pcdev->list, &pse_controller_list); 500 mutex_unlock(&pse_list_mutex); 501 502 return 0; 503 } 504 EXPORT_SYMBOL_GPL(pse_controller_register); 505 506 /** 507 * pse_controller_unregister - unregister a PSE controller device 508 * @pcdev: a pointer to the PSE controller device 509 */ 510 void pse_controller_unregister(struct pse_controller_dev *pcdev) 511 { 512 pse_release_pis(pcdev); 513 mutex_lock(&pse_list_mutex); 514 list_del(&pcdev->list); 515 mutex_unlock(&pse_list_mutex); 516 } 517 EXPORT_SYMBOL_GPL(pse_controller_unregister); 518 519 static void devm_pse_controller_release(struct device *dev, void *res) 520 { 521 pse_controller_unregister(*(struct pse_controller_dev **)res); 522 } 523 524 /** 525 * devm_pse_controller_register - resource managed pse_controller_register() 526 * @dev: device that is registering this PSE controller 527 * @pcdev: a pointer to the initialized PSE controller device 528 * 529 * Managed pse_controller_register(). For PSE controllers registered by 530 * this function, pse_controller_unregister() is automatically called on 531 * driver detach. See pse_controller_register() for more information. 532 * 533 * Return: 0 on success and failure value on error 534 */ 535 int devm_pse_controller_register(struct device *dev, 536 struct pse_controller_dev *pcdev) 537 { 538 struct pse_controller_dev **pcdevp; 539 int ret; 540 541 pcdevp = devres_alloc(devm_pse_controller_release, sizeof(*pcdevp), 542 GFP_KERNEL); 543 if (!pcdevp) 544 return -ENOMEM; 545 546 ret = pse_controller_register(pcdev); 547 if (ret) { 548 devres_free(pcdevp); 549 return ret; 550 } 551 552 *pcdevp = pcdev; 553 devres_add(dev, pcdevp); 554 555 return 0; 556 } 557 EXPORT_SYMBOL_GPL(devm_pse_controller_register); 558 559 /* PSE control section */ 560 561 static void __pse_control_release(struct kref *kref) 562 { 563 struct pse_control *psec = container_of(kref, struct pse_control, 564 refcnt); 565 566 lockdep_assert_held(&pse_list_mutex); 567 568 if (psec->pcdev->pi[psec->id].admin_state_enabled) 569 regulator_disable(psec->ps); 570 devm_regulator_put(psec->ps); 571 572 module_put(psec->pcdev->owner); 573 574 list_del(&psec->list); 575 kfree(psec); 576 } 577 578 static void __pse_control_put_internal(struct pse_control *psec) 579 { 580 lockdep_assert_held(&pse_list_mutex); 581 582 kref_put(&psec->refcnt, __pse_control_release); 583 } 584 585 /** 586 * pse_control_put - free the PSE control 587 * @psec: PSE control pointer 588 */ 589 void pse_control_put(struct pse_control *psec) 590 { 591 if (IS_ERR_OR_NULL(psec)) 592 return; 593 594 mutex_lock(&pse_list_mutex); 595 __pse_control_put_internal(psec); 596 mutex_unlock(&pse_list_mutex); 597 } 598 EXPORT_SYMBOL_GPL(pse_control_put); 599 600 static struct pse_control * 601 pse_control_get_internal(struct pse_controller_dev *pcdev, unsigned int index) 602 { 603 struct pse_control *psec; 604 int ret; 605 606 lockdep_assert_held(&pse_list_mutex); 607 608 list_for_each_entry(psec, &pcdev->pse_control_head, list) { 609 if (psec->id == index) { 610 kref_get(&psec->refcnt); 611 return psec; 612 } 613 } 614 615 psec = kzalloc(sizeof(*psec), GFP_KERNEL); 616 if (!psec) 617 return ERR_PTR(-ENOMEM); 618 619 if (!try_module_get(pcdev->owner)) { 620 ret = -ENODEV; 621 goto free_psec; 622 } 623 624 psec->ps = devm_regulator_get_exclusive(pcdev->dev, 625 rdev_get_name(pcdev->pi[index].rdev)); 626 if (IS_ERR(psec->ps)) { 627 ret = PTR_ERR(psec->ps); 628 goto put_module; 629 } 630 631 ret = regulator_is_enabled(psec->ps); 632 if (ret < 0) 633 goto regulator_put; 634 635 pcdev->pi[index].admin_state_enabled = ret; 636 637 psec->pcdev = pcdev; 638 list_add(&psec->list, &pcdev->pse_control_head); 639 psec->id = index; 640 kref_init(&psec->refcnt); 641 642 return psec; 643 644 regulator_put: 645 devm_regulator_put(psec->ps); 646 put_module: 647 module_put(pcdev->owner); 648 free_psec: 649 kfree(psec); 650 651 return ERR_PTR(ret); 652 } 653 654 /** 655 * of_pse_match_pi - Find the PSE PI id matching the device node phandle 656 * @pcdev: a pointer to the PSE controller device 657 * @np: a pointer to the device node 658 * 659 * Return: id of the PSE PI, -EINVAL if not found 660 */ 661 static int of_pse_match_pi(struct pse_controller_dev *pcdev, 662 struct device_node *np) 663 { 664 int i; 665 666 for (i = 0; i < pcdev->nr_lines; i++) { 667 if (pcdev->pi[i].np == np) 668 return i; 669 } 670 671 return -EINVAL; 672 } 673 674 /** 675 * psec_id_xlate - translate pse_spec to the PSE line number according 676 * to the number of pse-cells in case of no pse_pi node 677 * @pcdev: a pointer to the PSE controller device 678 * @pse_spec: PSE line specifier as found in the device tree 679 * 680 * Return: 0 if #pse-cells = <0>. Return PSE line number otherwise. 681 */ 682 static int psec_id_xlate(struct pse_controller_dev *pcdev, 683 const struct of_phandle_args *pse_spec) 684 { 685 if (!pcdev->of_pse_n_cells) 686 return 0; 687 688 if (pcdev->of_pse_n_cells > 1 || 689 pse_spec->args[0] >= pcdev->nr_lines) 690 return -EINVAL; 691 692 return pse_spec->args[0]; 693 } 694 695 struct pse_control *of_pse_control_get(struct device_node *node) 696 { 697 struct pse_controller_dev *r, *pcdev; 698 struct of_phandle_args args; 699 struct pse_control *psec; 700 int psec_id; 701 int ret; 702 703 if (!node) 704 return ERR_PTR(-EINVAL); 705 706 ret = of_parse_phandle_with_args(node, "pses", "#pse-cells", 0, &args); 707 if (ret) 708 return ERR_PTR(ret); 709 710 mutex_lock(&pse_list_mutex); 711 pcdev = NULL; 712 list_for_each_entry(r, &pse_controller_list, list) { 713 if (!r->no_of_pse_pi) { 714 ret = of_pse_match_pi(r, args.np); 715 if (ret >= 0) { 716 pcdev = r; 717 psec_id = ret; 718 break; 719 } 720 } else if (args.np == r->dev->of_node) { 721 pcdev = r; 722 break; 723 } 724 } 725 726 if (!pcdev) { 727 psec = ERR_PTR(-EPROBE_DEFER); 728 goto out; 729 } 730 731 if (WARN_ON(args.args_count != pcdev->of_pse_n_cells)) { 732 psec = ERR_PTR(-EINVAL); 733 goto out; 734 } 735 736 if (pcdev->no_of_pse_pi) { 737 psec_id = psec_id_xlate(pcdev, &args); 738 if (psec_id < 0) { 739 psec = ERR_PTR(psec_id); 740 goto out; 741 } 742 } 743 744 /* pse_list_mutex also protects the pcdev's pse_control list */ 745 psec = pse_control_get_internal(pcdev, psec_id); 746 747 out: 748 mutex_unlock(&pse_list_mutex); 749 of_node_put(args.np); 750 751 return psec; 752 } 753 EXPORT_SYMBOL_GPL(of_pse_control_get); 754 755 /** 756 * pse_ethtool_get_status - get status of PSE control 757 * @psec: PSE control pointer 758 * @extack: extack for reporting useful error messages 759 * @status: struct to store PSE status 760 * 761 * Return: 0 on success and failure value on error 762 */ 763 int pse_ethtool_get_status(struct pse_control *psec, 764 struct netlink_ext_ack *extack, 765 struct ethtool_pse_control_status *status) 766 { 767 struct pse_admin_state admin_state = {0}; 768 struct pse_pw_status pw_status = {0}; 769 const struct pse_controller_ops *ops; 770 struct pse_controller_dev *pcdev; 771 int ret; 772 773 pcdev = psec->pcdev; 774 ops = pcdev->ops; 775 mutex_lock(&pcdev->lock); 776 ret = ops->pi_get_admin_state(pcdev, psec->id, &admin_state); 777 if (ret) 778 goto out; 779 status->podl_admin_state = admin_state.podl_admin_state; 780 status->c33_admin_state = admin_state.c33_admin_state; 781 782 ret = ops->pi_get_pw_status(pcdev, psec->id, &pw_status); 783 if (ret) 784 goto out; 785 status->podl_pw_status = pw_status.podl_pw_status; 786 status->c33_pw_status = pw_status.c33_pw_status; 787 788 if (ops->pi_get_ext_state) { 789 struct pse_ext_state_info ext_state_info = {0}; 790 791 ret = ops->pi_get_ext_state(pcdev, psec->id, 792 &ext_state_info); 793 if (ret) 794 goto out; 795 796 memcpy(&status->c33_ext_state_info, 797 &ext_state_info.c33_ext_state_info, 798 sizeof(status->c33_ext_state_info)); 799 } 800 801 if (ops->pi_get_pw_class) { 802 ret = ops->pi_get_pw_class(pcdev, psec->id); 803 if (ret < 0) 804 goto out; 805 806 status->c33_pw_class = ret; 807 } 808 809 if (ops->pi_get_actual_pw) { 810 ret = ops->pi_get_actual_pw(pcdev, psec->id); 811 if (ret < 0) 812 goto out; 813 814 status->c33_actual_pw = ret; 815 } 816 817 if (ops->pi_get_pw_limit) { 818 ret = ops->pi_get_pw_limit(pcdev, psec->id); 819 if (ret < 0) 820 goto out; 821 822 status->c33_avail_pw_limit = ret; 823 } 824 825 if (ops->pi_get_pw_limit_ranges) { 826 struct pse_pw_limit_ranges pw_limit_ranges = {0}; 827 828 ret = ops->pi_get_pw_limit_ranges(pcdev, psec->id, 829 &pw_limit_ranges); 830 if (ret < 0) 831 goto out; 832 833 status->c33_pw_limit_ranges = 834 pw_limit_ranges.c33_pw_limit_ranges; 835 status->c33_pw_limit_nb_ranges = ret; 836 } 837 out: 838 mutex_unlock(&psec->pcdev->lock); 839 return ret; 840 } 841 EXPORT_SYMBOL_GPL(pse_ethtool_get_status); 842 843 static int pse_ethtool_c33_set_config(struct pse_control *psec, 844 const struct pse_control_config *config) 845 { 846 int err = 0; 847 848 /* Look at admin_state_enabled status to not call regulator_enable 849 * or regulator_disable twice creating a regulator counter mismatch 850 */ 851 switch (config->c33_admin_control) { 852 case ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED: 853 /* We could have mismatch between admin_state_enabled and 854 * state reported by regulator_is_enabled. This can occur when 855 * the PI is forcibly turn off by the controller. Call 856 * regulator_disable on that case to fix the counters state. 857 */ 858 if (psec->pcdev->pi[psec->id].admin_state_enabled && 859 !regulator_is_enabled(psec->ps)) { 860 err = regulator_disable(psec->ps); 861 if (err) 862 break; 863 } 864 if (!psec->pcdev->pi[psec->id].admin_state_enabled) 865 err = regulator_enable(psec->ps); 866 break; 867 case ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED: 868 if (psec->pcdev->pi[psec->id].admin_state_enabled) 869 err = regulator_disable(psec->ps); 870 break; 871 default: 872 err = -EOPNOTSUPP; 873 } 874 875 return err; 876 } 877 878 static int pse_ethtool_podl_set_config(struct pse_control *psec, 879 const struct pse_control_config *config) 880 { 881 int err = 0; 882 883 /* Look at admin_state_enabled status to not call regulator_enable 884 * or regulator_disable twice creating a regulator counter mismatch 885 */ 886 switch (config->podl_admin_control) { 887 case ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED: 888 if (!psec->pcdev->pi[psec->id].admin_state_enabled) 889 err = regulator_enable(psec->ps); 890 break; 891 case ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED: 892 if (psec->pcdev->pi[psec->id].admin_state_enabled) 893 err = regulator_disable(psec->ps); 894 break; 895 default: 896 err = -EOPNOTSUPP; 897 } 898 899 return err; 900 } 901 902 /** 903 * pse_ethtool_set_config - set PSE control configuration 904 * @psec: PSE control pointer 905 * @extack: extack for reporting useful error messages 906 * @config: Configuration of the test to run 907 * 908 * Return: 0 on success and failure value on error 909 */ 910 int pse_ethtool_set_config(struct pse_control *psec, 911 struct netlink_ext_ack *extack, 912 const struct pse_control_config *config) 913 { 914 int err = 0; 915 916 if (pse_has_c33(psec) && config->c33_admin_control) { 917 err = pse_ethtool_c33_set_config(psec, config); 918 if (err) 919 return err; 920 } 921 922 if (pse_has_podl(psec) && config->podl_admin_control) 923 err = pse_ethtool_podl_set_config(psec, config); 924 925 return err; 926 } 927 EXPORT_SYMBOL_GPL(pse_ethtool_set_config); 928 929 /** 930 * pse_ethtool_set_pw_limit - set PSE control power limit 931 * @psec: PSE control pointer 932 * @extack: extack for reporting useful error messages 933 * @pw_limit: power limit value in mW 934 * 935 * Return: 0 on success and failure value on error 936 */ 937 int pse_ethtool_set_pw_limit(struct pse_control *psec, 938 struct netlink_ext_ack *extack, 939 const unsigned int pw_limit) 940 { 941 int uV, uA, ret; 942 s64 tmp_64; 943 944 if (pw_limit > MAX_PI_PW) 945 return -ERANGE; 946 947 ret = regulator_get_voltage(psec->ps); 948 if (!ret) { 949 NL_SET_ERR_MSG(extack, 950 "Can't calculate the current, PSE voltage read is 0"); 951 return -ERANGE; 952 } 953 if (ret < 0) { 954 NL_SET_ERR_MSG(extack, 955 "Error reading PSE voltage"); 956 return ret; 957 } 958 uV = ret; 959 960 tmp_64 = pw_limit; 961 tmp_64 *= 1000000000ull; 962 /* uA = mW * 1000000000 / uV */ 963 uA = DIV_ROUND_CLOSEST_ULL(tmp_64, uV); 964 965 return regulator_set_current_limit(psec->ps, 0, uA); 966 } 967 EXPORT_SYMBOL_GPL(pse_ethtool_set_pw_limit); 968 969 bool pse_has_podl(struct pse_control *psec) 970 { 971 return psec->pcdev->types & ETHTOOL_PSE_PODL; 972 } 973 EXPORT_SYMBOL_GPL(pse_has_podl); 974 975 bool pse_has_c33(struct pse_control *psec) 976 { 977 return psec->pcdev->types & ETHTOOL_PSE_C33; 978 } 979 EXPORT_SYMBOL_GPL(pse_has_c33); 980