1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pse-pd/pse.h> 15 16 #define PD692X0_PSE_NAME "pd692x0_pse" 17 18 #define PD692X0_MAX_PIS 48 19 #define PD692X0_MAX_MANAGERS 12 20 #define PD692X0_MAX_MANAGER_PORTS 8 21 #define PD692X0_MAX_HW_PORTS (PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS) 22 23 #define PD69200_BT_PROD_VER 24 24 #define PD69210_BT_PROD_VER 26 25 #define PD69220_BT_PROD_VER 29 26 27 #define PD692X0_FW_MAJ_VER 3 28 #define PD692X0_FW_MIN_VER 5 29 #define PD692X0_FW_PATCH_VER 5 30 31 enum pd692x0_fw_state { 32 PD692X0_FW_UNKNOWN, 33 PD692X0_FW_OK, 34 PD692X0_FW_BROKEN, 35 PD692X0_FW_NEED_UPDATE, 36 PD692X0_FW_PREPARE, 37 PD692X0_FW_WRITE, 38 PD692X0_FW_COMPLETE, 39 }; 40 41 struct pd692x0_msg { 42 u8 key; 43 u8 echo; 44 u8 sub[3]; 45 u8 data[8]; 46 __be16 chksum; 47 } __packed; 48 49 struct pd692x0_msg_ver { 50 u8 prod; 51 u8 maj_sw_ver; 52 u8 min_sw_ver; 53 u8 pa_sw_ver; 54 u8 param; 55 u8 build; 56 }; 57 58 enum { 59 PD692X0_KEY_CMD, 60 PD692X0_KEY_PRG, 61 PD692X0_KEY_REQ, 62 PD692X0_KEY_TLM, 63 PD692X0_KEY_TEST, 64 PD692X0_KEY_REPORT = 0x52 65 }; 66 67 enum { 68 PD692X0_MSG_RESET, 69 PD692X0_MSG_GET_SYS_STATUS, 70 PD692X0_MSG_GET_SW_VER, 71 PD692X0_MSG_SET_TMP_PORT_MATRIX, 72 PD692X0_MSG_PRG_PORT_MATRIX, 73 PD692X0_MSG_SET_PORT_PARAM, 74 PD692X0_MSG_GET_PORT_STATUS, 75 PD692X0_MSG_DOWNLOAD_CMD, 76 PD692X0_MSG_GET_PORT_CLASS, 77 PD692X0_MSG_GET_PORT_MEAS, 78 PD692X0_MSG_GET_PORT_PARAM, 79 80 /* add new message above here */ 81 PD692X0_MSG_CNT 82 }; 83 84 struct pd692x0_priv { 85 struct i2c_client *client; 86 struct pse_controller_dev pcdev; 87 struct device_node *np; 88 89 enum pd692x0_fw_state fw_state; 90 struct fw_upload *fwl; 91 bool cancel_request; 92 93 u8 msg_id; 94 bool last_cmd_key; 95 unsigned long last_cmd_key_time; 96 97 enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS]; 98 }; 99 100 /* Template list of communication messages. The non-null bytes defined here 101 * constitute the fixed portion of the messages. The remaining bytes will 102 * be configured later within the functions. Refer to the "PD692x0 BT Serial 103 * Communication Protocol User Guide" for comprehensive details on messages 104 * content. 105 */ 106 static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = { 107 [PD692X0_MSG_RESET] = { 108 .key = PD692X0_KEY_CMD, 109 .sub = {0x07, 0x55, 0x00}, 110 .data = {0x55, 0x00, 0x55, 0x4e, 111 0x4e, 0x4e, 0x4e, 0x4e}, 112 }, 113 [PD692X0_MSG_GET_SYS_STATUS] = { 114 .key = PD692X0_KEY_REQ, 115 .sub = {0x07, 0xd0, 0x4e}, 116 .data = {0x4e, 0x4e, 0x4e, 0x4e, 117 0x4e, 0x4e, 0x4e, 0x4e}, 118 }, 119 [PD692X0_MSG_GET_SW_VER] = { 120 .key = PD692X0_KEY_REQ, 121 .sub = {0x07, 0x1e, 0x21}, 122 .data = {0x4e, 0x4e, 0x4e, 0x4e, 123 0x4e, 0x4e, 0x4e, 0x4e}, 124 }, 125 [PD692X0_MSG_SET_TMP_PORT_MATRIX] = { 126 .key = PD692X0_KEY_CMD, 127 .sub = {0x05, 0x43}, 128 .data = { 0, 0x4e, 0x4e, 0x4e, 129 0x4e, 0x4e, 0x4e, 0x4e}, 130 }, 131 [PD692X0_MSG_PRG_PORT_MATRIX] = { 132 .key = PD692X0_KEY_CMD, 133 .sub = {0x07, 0x43, 0x4e}, 134 .data = {0x4e, 0x4e, 0x4e, 0x4e, 135 0x4e, 0x4e, 0x4e, 0x4e}, 136 }, 137 [PD692X0_MSG_SET_PORT_PARAM] = { 138 .key = PD692X0_KEY_CMD, 139 .sub = {0x05, 0xc0}, 140 .data = { 0xf, 0xff, 0xff, 0xff, 141 0x4e, 0x4e, 0x4e, 0x4e}, 142 }, 143 [PD692X0_MSG_GET_PORT_STATUS] = { 144 .key = PD692X0_KEY_REQ, 145 .sub = {0x05, 0xc1}, 146 .data = {0x4e, 0x4e, 0x4e, 0x4e, 147 0x4e, 0x4e, 0x4e, 0x4e}, 148 }, 149 [PD692X0_MSG_DOWNLOAD_CMD] = { 150 .key = PD692X0_KEY_PRG, 151 .sub = {0xff, 0x99, 0x15}, 152 .data = {0x16, 0x16, 0x99, 0x4e, 153 0x4e, 0x4e, 0x4e, 0x4e}, 154 }, 155 [PD692X0_MSG_GET_PORT_CLASS] = { 156 .key = PD692X0_KEY_REQ, 157 .sub = {0x05, 0xc4}, 158 .data = {0x4e, 0x4e, 0x4e, 0x4e, 159 0x4e, 0x4e, 0x4e, 0x4e}, 160 }, 161 [PD692X0_MSG_GET_PORT_MEAS] = { 162 .key = PD692X0_KEY_REQ, 163 .sub = {0x05, 0xc5}, 164 .data = {0x4e, 0x4e, 0x4e, 0x4e, 165 0x4e, 0x4e, 0x4e, 0x4e}, 166 }, 167 [PD692X0_MSG_GET_PORT_PARAM] = { 168 .key = PD692X0_KEY_REQ, 169 .sub = {0x05, 0xc0}, 170 .data = {0x4e, 0x4e, 0x4e, 0x4e, 171 0x4e, 0x4e, 0x4e, 0x4e}, 172 }, 173 }; 174 175 static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo) 176 { 177 u8 *data = (u8 *)msg; 178 u16 chksum = 0; 179 int i; 180 181 msg->echo = echo++; 182 if (echo == 0xff) 183 echo = 0; 184 185 for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++) 186 chksum += data[i]; 187 188 msg->chksum = cpu_to_be16(chksum); 189 190 return echo; 191 } 192 193 static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg) 194 { 195 const struct i2c_client *client = priv->client; 196 int ret; 197 198 if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) { 199 int cmd_msleep; 200 201 cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time); 202 if (cmd_msleep > 0) 203 msleep(cmd_msleep); 204 } 205 206 /* Add echo and checksum bytes to the message */ 207 priv->msg_id = pd692x0_build_msg(msg, priv->msg_id); 208 209 ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg)); 210 if (ret != sizeof(*msg)) 211 return -EIO; 212 213 return 0; 214 } 215 216 static int pd692x0_reset(struct pd692x0_priv *priv) 217 { 218 const struct i2c_client *client = priv->client; 219 struct pd692x0_msg msg, buf = {0}; 220 int ret; 221 222 msg = pd692x0_msg_template_list[PD692X0_MSG_RESET]; 223 ret = pd692x0_send_msg(priv, &msg); 224 if (ret) { 225 dev_err(&client->dev, 226 "Failed to reset the controller (%pe)\n", ERR_PTR(ret)); 227 return ret; 228 } 229 230 msleep(30); 231 232 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 233 if (ret != sizeof(buf)) 234 return ret < 0 ? ret : -EIO; 235 236 /* Is the reply a successful report message */ 237 if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1]) 238 return -EIO; 239 240 msleep(300); 241 242 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 243 if (ret != sizeof(buf)) 244 return ret < 0 ? ret : -EIO; 245 246 /* Is the boot status without error */ 247 if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) { 248 dev_err(&client->dev, "PSE controller error\n"); 249 return -EIO; 250 } 251 252 return 0; 253 } 254 255 static bool pd692x0_try_recv_msg(const struct i2c_client *client, 256 struct pd692x0_msg *msg, 257 struct pd692x0_msg *buf) 258 { 259 /* Wait 30ms before readback as mandated by the protocol */ 260 msleep(30); 261 262 memset(buf, 0, sizeof(*buf)); 263 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 264 if (buf->key) 265 return 0; 266 267 msleep(100); 268 269 memset(buf, 0, sizeof(*buf)); 270 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 271 if (buf->key) 272 return 0; 273 274 return 1; 275 } 276 277 /* Implementation of I2C communication, specifically addressing scenarios 278 * involving communication loss. Refer to the "Synchronization During 279 * Communication Loss" section in the Communication Protocol document for 280 * further details. 281 */ 282 static int pd692x0_recv_msg(struct pd692x0_priv *priv, 283 struct pd692x0_msg *msg, 284 struct pd692x0_msg *buf) 285 { 286 const struct i2c_client *client = priv->client; 287 int ret; 288 289 ret = pd692x0_try_recv_msg(client, msg, buf); 290 if (!ret) 291 goto out_success; 292 293 dev_warn(&client->dev, 294 "Communication lost, rtnl is locked until communication is back!"); 295 296 ret = pd692x0_send_msg(priv, msg); 297 if (ret) 298 return ret; 299 300 ret = pd692x0_try_recv_msg(client, msg, buf); 301 if (!ret) 302 goto out_success2; 303 304 msleep(10000); 305 306 ret = pd692x0_send_msg(priv, msg); 307 if (ret) 308 return ret; 309 310 ret = pd692x0_try_recv_msg(client, msg, buf); 311 if (!ret) 312 goto out_success2; 313 314 return pd692x0_reset(priv); 315 316 out_success2: 317 dev_warn(&client->dev, "Communication is back, rtnl is unlocked!"); 318 out_success: 319 if (msg->key == PD692X0_KEY_CMD) { 320 priv->last_cmd_key = true; 321 priv->last_cmd_key_time = jiffies; 322 } else { 323 priv->last_cmd_key = false; 324 } 325 326 return 0; 327 } 328 329 static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv, 330 struct pd692x0_msg *msg, 331 struct pd692x0_msg *buf) 332 { 333 struct device *dev = &priv->client->dev; 334 int ret; 335 336 ret = pd692x0_send_msg(priv, msg); 337 if (ret) 338 return ret; 339 340 ret = pd692x0_recv_msg(priv, msg, buf); 341 if (ret) 342 return ret; 343 344 if (msg->echo != buf->echo) { 345 dev_err(dev, 346 "Wrong match in message ID, expect %d received %d.\n", 347 msg->echo, buf->echo); 348 return -EIO; 349 } 350 351 /* If the reply is a report message is it successful */ 352 if (buf->key == PD692X0_KEY_REPORT && 353 (buf->sub[0] || buf->sub[1])) { 354 return -EIO; 355 } 356 357 return 0; 358 } 359 360 static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev) 361 { 362 return container_of(pcdev, struct pd692x0_priv, pcdev); 363 } 364 365 static int pd692x0_fw_unavailable(struct pd692x0_priv *priv) 366 { 367 switch (priv->fw_state) { 368 case PD692X0_FW_OK: 369 return 0; 370 case PD692X0_FW_PREPARE: 371 case PD692X0_FW_WRITE: 372 case PD692X0_FW_COMPLETE: 373 dev_err(&priv->client->dev, "Firmware update in progress!\n"); 374 return -EBUSY; 375 case PD692X0_FW_BROKEN: 376 case PD692X0_FW_NEED_UPDATE: 377 default: 378 dev_err(&priv->client->dev, 379 "Firmware issue. Please update it!\n"); 380 return -EOPNOTSUPP; 381 } 382 } 383 384 static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id) 385 { 386 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 387 struct pd692x0_msg msg, buf = {0}; 388 int ret; 389 390 ret = pd692x0_fw_unavailable(priv); 391 if (ret) 392 return ret; 393 394 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 395 return 0; 396 397 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 398 msg.data[0] = 0x1; 399 msg.sub[2] = id; 400 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 401 if (ret < 0) 402 return ret; 403 404 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 405 406 return 0; 407 } 408 409 static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id) 410 { 411 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 412 struct pd692x0_msg msg, buf = {0}; 413 int ret; 414 415 ret = pd692x0_fw_unavailable(priv); 416 if (ret) 417 return ret; 418 419 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED) 420 return 0; 421 422 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 423 msg.data[0] = 0x0; 424 msg.sub[2] = id; 425 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 426 if (ret < 0) 427 return ret; 428 429 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 430 431 return 0; 432 } 433 434 struct pd692x0_pse_ext_state_mapping { 435 u32 status_code; 436 enum ethtool_c33_pse_ext_state pse_ext_state; 437 u32 pse_ext_substate; 438 }; 439 440 static const struct pd692x0_pse_ext_state_mapping 441 pd692x0_pse_ext_state_map[] = { 442 {0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 443 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE}, 444 {0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 445 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE}, 446 {0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE, 447 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE}, 448 {0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 449 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT}, 450 {0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 451 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT}, 452 {0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 453 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 454 {0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 455 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS}, 456 {0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 457 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 458 {0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 459 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD}, 460 {0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED, 461 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD}, 462 {0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 463 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED}, 464 {0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 465 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 466 {0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 467 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE}, 468 {0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 469 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION}, 470 {0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 471 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 472 {0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED, 473 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION}, 474 {0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 475 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 476 {0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 477 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 478 {0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 479 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 480 {0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 481 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET}, 482 {0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 483 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT}, 484 {0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 485 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT}, 486 {0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 487 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 488 {0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 489 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR}, 490 {0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 491 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN}, 492 { /* sentinel */ } 493 }; 494 495 static int 496 pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id, 497 struct pse_ext_state_info *ext_state_info) 498 { 499 struct ethtool_c33_pse_ext_state_info *c33_ext_state_info; 500 const struct pd692x0_pse_ext_state_mapping *ext_state_map; 501 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 502 struct pd692x0_msg msg, buf = {0}; 503 int ret; 504 505 ret = pd692x0_fw_unavailable(priv); 506 if (ret) 507 return ret; 508 509 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 510 msg.sub[2] = id; 511 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 512 if (ret < 0) 513 return ret; 514 515 c33_ext_state_info = &ext_state_info->c33_ext_state_info; 516 ext_state_map = pd692x0_pse_ext_state_map; 517 while (ext_state_map->status_code) { 518 if (ext_state_map->status_code == buf.sub[0]) { 519 c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state; 520 c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate; 521 return 0; 522 } 523 ext_state_map++; 524 } 525 526 return 0; 527 } 528 529 struct pd692x0_class_pw { 530 int class; 531 int class_cfg_value; 532 int class_pw; 533 int max_added_class_pw; 534 }; 535 536 #define PD692X0_CLASS_PW_TABLE_SIZE 4 537 /* 4/2 pairs class configuration power table in compliance mode. 538 * Need to be arranged in ascending order of power support. 539 */ 540 static const struct pd692x0_class_pw 541 pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = { 542 {.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100}, 543 {.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000}, 544 {.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000}, 545 {.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500}, 546 }; 547 548 static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw) 549 { 550 const struct pd692x0_class_pw *pw_table; 551 int i; 552 553 pw_table = pd692x0_class_pw_table; 554 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 555 if (pw_table->class_cfg_value == op_mode) 556 return pw_table->class_pw + added_pw * 100; 557 } 558 559 return -ERANGE; 560 } 561 562 static int pd692x0_pi_set_pw_from_table(struct device *dev, 563 struct pd692x0_msg *msg, int pw) 564 { 565 const struct pd692x0_class_pw *pw_table; 566 int i; 567 568 pw_table = pd692x0_class_pw_table; 569 if (pw < pw_table->class_pw) { 570 dev_err(dev, 571 "Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n", 572 pw, 573 pw_table->class_pw, 574 pw_table->class_pw + pw_table->max_added_class_pw); 575 return -ERANGE; 576 } 577 578 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 579 if (pw > (pw_table->class_pw + pw_table->max_added_class_pw)) 580 continue; 581 582 if (pw < pw_table->class_pw) { 583 dev_err(dev, 584 "Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n", 585 pw, 586 (pw_table - 1)->class_pw, 587 (pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw, 588 pw_table->class_pw, 589 pw_table->class_pw + pw_table->max_added_class_pw); 590 return -ERANGE; 591 } 592 593 msg->data[2] = pw_table->class_cfg_value; 594 msg->data[3] = (pw - pw_table->class_pw) / 100; 595 return 0; 596 } 597 598 pw_table--; 599 dev_warn(dev, 600 "Power limit %dmW not supported. Set to highest power limit %dmW\n", 601 pw, pw_table->class_pw + pw_table->max_added_class_pw); 602 msg->data[2] = pw_table->class_cfg_value; 603 msg->data[3] = pw_table->max_added_class_pw / 100; 604 return 0; 605 } 606 607 static int 608 pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 609 struct pse_pw_limit_ranges *pw_limit_ranges) 610 { 611 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 612 const struct pd692x0_class_pw *pw_table; 613 int i; 614 615 pw_table = pd692x0_class_pw_table; 616 c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE, 617 sizeof(*c33_pw_limit_ranges), 618 GFP_KERNEL); 619 if (!c33_pw_limit_ranges) 620 return -ENOMEM; 621 622 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 623 c33_pw_limit_ranges[i].min = pw_table->class_pw; 624 c33_pw_limit_ranges[i].max = pw_table->class_pw + 625 pw_table->max_added_class_pw; 626 } 627 628 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 629 return i; 630 } 631 632 static int 633 pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 634 struct pse_admin_state *admin_state) 635 { 636 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 637 struct pd692x0_msg msg, buf = {0}; 638 int ret; 639 640 ret = pd692x0_fw_unavailable(priv); 641 if (ret) 642 return ret; 643 644 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 645 msg.sub[2] = id; 646 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 647 if (ret < 0) 648 return ret; 649 650 if (buf.sub[1]) 651 admin_state->c33_admin_state = 652 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 653 else 654 admin_state->c33_admin_state = 655 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 656 657 priv->admin_state[id] = admin_state->c33_admin_state; 658 659 return 0; 660 } 661 662 static int 663 pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 664 struct pse_pw_status *pw_status) 665 { 666 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 667 struct pd692x0_msg msg, buf = {0}; 668 int ret; 669 670 ret = pd692x0_fw_unavailable(priv); 671 if (ret) 672 return ret; 673 674 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 675 msg.sub[2] = id; 676 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 677 if (ret < 0) 678 return ret; 679 680 /* Compare Port Status (Communication Protocol Document par. 7.1) */ 681 if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90) 682 pw_status->c33_pw_status = 683 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 684 else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22) 685 pw_status->c33_pw_status = 686 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING; 687 else if (buf.sub[0] == 0x12) 688 pw_status->c33_pw_status = 689 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT; 690 else 691 pw_status->c33_pw_status = 692 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 693 694 return 0; 695 } 696 697 static int 698 pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id) 699 { 700 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 701 struct pd692x0_msg msg, buf = {0}; 702 u32 class; 703 int ret; 704 705 ret = pd692x0_fw_unavailable(priv); 706 if (ret) 707 return ret; 708 709 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS]; 710 msg.sub[2] = id; 711 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 712 if (ret < 0) 713 return ret; 714 715 class = buf.data[3] >> 4; 716 if (class <= 8) 717 return class; 718 719 return 0; 720 } 721 722 static int 723 pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 724 { 725 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 726 struct pd692x0_msg msg, buf = {0}; 727 int ret; 728 729 ret = pd692x0_fw_unavailable(priv); 730 if (ret) 731 return ret; 732 733 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 734 msg.sub[2] = id; 735 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 736 if (ret < 0) 737 return ret; 738 739 return (buf.data[0] << 4 | buf.data[1]) * 100; 740 } 741 742 static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv) 743 { 744 struct device *dev = &priv->client->dev; 745 struct pd692x0_msg msg, buf = {0}; 746 struct pd692x0_msg_ver ver = {0}; 747 int ret; 748 749 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER]; 750 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 751 if (ret < 0) { 752 dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret)); 753 return ver; 754 } 755 756 /* Extract version from the message */ 757 ver.prod = buf.sub[2]; 758 ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100; 759 ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10; 760 ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10; 761 ver.param = buf.data[2]; 762 ver.build = buf.data[3]; 763 764 return ver; 765 } 766 767 struct pd692x0_manager { 768 struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS]; 769 int nports; 770 }; 771 772 struct pd692x0_matrix { 773 u8 hw_port_a; 774 u8 hw_port_b; 775 }; 776 777 static int 778 pd692x0_of_get_ports_manager(struct pd692x0_priv *priv, 779 struct pd692x0_manager *manager, 780 struct device_node *np) 781 { 782 struct device_node *node; 783 int ret, nports, i; 784 785 nports = 0; 786 for_each_child_of_node(np, node) { 787 u32 port; 788 789 if (!of_node_name_eq(node, "port")) 790 continue; 791 792 ret = of_property_read_u32(node, "reg", &port); 793 if (ret) 794 goto out; 795 796 if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) { 797 dev_err(&priv->client->dev, 798 "wrong number or order of manager ports (%d)\n", 799 port); 800 ret = -EINVAL; 801 goto out; 802 } 803 804 of_node_get(node); 805 manager->port_node[port] = node; 806 nports++; 807 } 808 809 manager->nports = nports; 810 return 0; 811 812 out: 813 for (i = 0; i < nports; i++) { 814 of_node_put(manager->port_node[i]); 815 manager->port_node[i] = NULL; 816 } 817 of_node_put(node); 818 return ret; 819 } 820 821 static int 822 pd692x0_of_get_managers(struct pd692x0_priv *priv, 823 struct pd692x0_manager manager[PD692X0_MAX_MANAGERS]) 824 { 825 struct device_node *managers_node, *node; 826 int ret, nmanagers, i, j; 827 828 if (!priv->np) 829 return -EINVAL; 830 831 nmanagers = 0; 832 managers_node = of_get_child_by_name(priv->np, "managers"); 833 if (!managers_node) 834 return -EINVAL; 835 836 for_each_child_of_node(managers_node, node) { 837 u32 manager_id; 838 839 if (!of_node_name_eq(node, "manager")) 840 continue; 841 842 ret = of_property_read_u32(node, "reg", &manager_id); 843 if (ret) 844 goto out; 845 846 if (manager_id >= PD692X0_MAX_MANAGERS || 847 manager_id != nmanagers) { 848 dev_err(&priv->client->dev, 849 "wrong number or order of managers (%d)\n", 850 manager_id); 851 ret = -EINVAL; 852 goto out; 853 } 854 855 ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id], 856 node); 857 if (ret) 858 goto out; 859 860 nmanagers++; 861 } 862 863 of_node_put(managers_node); 864 return nmanagers; 865 866 out: 867 for (i = 0; i < nmanagers; i++) { 868 for (j = 0; j < manager[i].nports; j++) { 869 of_node_put(manager[i].port_node[j]); 870 manager[i].port_node[j] = NULL; 871 } 872 } 873 874 of_node_put(node); 875 of_node_put(managers_node); 876 return ret; 877 } 878 879 static int 880 pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset, 881 const struct pd692x0_manager *manager, 882 int nmanagers, struct pd692x0_matrix *port_matrix) 883 { 884 int i, j, port_cnt; 885 bool found = false; 886 887 if (!pairset->np) 888 return 0; 889 890 /* Look on every managers */ 891 port_cnt = 0; 892 for (i = 0; i < nmanagers; i++) { 893 /* Look on every ports of the manager */ 894 for (j = 0; j < manager[i].nports; j++) { 895 if (pairset->np == manager[i].port_node[j]) { 896 found = true; 897 break; 898 } 899 } 900 port_cnt += j; 901 902 if (found) 903 break; 904 } 905 906 if (!found) 907 return -ENODEV; 908 909 if (pairset->pinout == ALTERNATIVE_A) 910 port_matrix->hw_port_a = port_cnt; 911 else if (pairset->pinout == ALTERNATIVE_B) 912 port_matrix->hw_port_b = port_cnt; 913 914 return 0; 915 } 916 917 static int 918 pd692x0_set_ports_matrix(struct pd692x0_priv *priv, 919 const struct pd692x0_manager *manager, 920 int nmanagers, 921 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]) 922 { 923 struct pse_controller_dev *pcdev = &priv->pcdev; 924 int i, ret; 925 926 /* Init Matrix */ 927 for (i = 0; i < PD692X0_MAX_PIS; i++) { 928 port_matrix[i].hw_port_a = 0xff; 929 port_matrix[i].hw_port_b = 0xff; 930 } 931 932 /* Update with values for every PSE PIs */ 933 for (i = 0; i < pcdev->nr_lines; i++) { 934 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0], 935 manager, nmanagers, 936 &port_matrix[i]); 937 if (ret) { 938 dev_err(&priv->client->dev, 939 "unable to configure pi %d pairset 0", i); 940 return ret; 941 } 942 943 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1], 944 manager, nmanagers, 945 &port_matrix[i]); 946 if (ret) { 947 dev_err(&priv->client->dev, 948 "unable to configure pi %d pairset 1", i); 949 return ret; 950 } 951 } 952 953 return 0; 954 } 955 956 static int 957 pd692x0_write_ports_matrix(struct pd692x0_priv *priv, 958 const struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]) 959 { 960 struct pd692x0_msg msg, buf; 961 int ret, i; 962 963 /* Write temporary Matrix */ 964 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX]; 965 for (i = 0; i < PD692X0_MAX_PIS; i++) { 966 msg.sub[2] = i; 967 msg.data[0] = port_matrix[i].hw_port_b; 968 msg.data[1] = port_matrix[i].hw_port_a; 969 970 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 971 if (ret < 0) 972 return ret; 973 } 974 975 /* Program Matrix */ 976 msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX]; 977 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 978 if (ret < 0) 979 return ret; 980 981 return 0; 982 } 983 984 static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev) 985 { 986 struct pd692x0_manager manager[PD692X0_MAX_MANAGERS] = {0}; 987 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 988 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]; 989 int ret, i, j, nmanagers; 990 991 /* Should we flash the port matrix */ 992 if (priv->fw_state != PD692X0_FW_OK && 993 priv->fw_state != PD692X0_FW_COMPLETE) 994 return 0; 995 996 ret = pd692x0_of_get_managers(priv, manager); 997 if (ret < 0) 998 return ret; 999 1000 nmanagers = ret; 1001 ret = pd692x0_set_ports_matrix(priv, manager, nmanagers, port_matrix); 1002 if (ret) 1003 goto out; 1004 1005 ret = pd692x0_write_ports_matrix(priv, port_matrix); 1006 if (ret) 1007 goto out; 1008 1009 out: 1010 for (i = 0; i < nmanagers; i++) { 1011 for (j = 0; j < manager[i].nports; j++) 1012 of_node_put(manager[i].port_node[j]); 1013 } 1014 return ret; 1015 } 1016 1017 static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 1018 { 1019 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1020 struct pd692x0_msg msg, buf = {0}; 1021 int ret; 1022 1023 ret = pd692x0_fw_unavailable(priv); 1024 if (ret) 1025 return ret; 1026 1027 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS]; 1028 msg.sub[2] = id; 1029 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1030 if (ret < 0) 1031 return ret; 1032 1033 /* Convert 0.1V unit to uV */ 1034 return (buf.sub[0] << 8 | buf.sub[1]) * 100000; 1035 } 1036 1037 static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev, 1038 int id) 1039 { 1040 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1041 struct pd692x0_msg msg, buf = {0}; 1042 int ret; 1043 1044 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 1045 msg.sub[2] = id; 1046 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1047 if (ret < 0) 1048 return ret; 1049 1050 return pd692x0_pi_get_pw_from_table(buf.data[2], buf.data[3]); 1051 } 1052 1053 static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev, 1054 int id, int max_mW) 1055 { 1056 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1057 struct device *dev = &priv->client->dev; 1058 struct pd692x0_msg msg, buf = {0}; 1059 int ret; 1060 1061 ret = pd692x0_fw_unavailable(priv); 1062 if (ret) 1063 return ret; 1064 1065 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1066 msg.sub[2] = id; 1067 ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW); 1068 if (ret) 1069 return ret; 1070 1071 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1072 } 1073 1074 static const struct pse_controller_ops pd692x0_ops = { 1075 .setup_pi_matrix = pd692x0_setup_pi_matrix, 1076 .pi_get_admin_state = pd692x0_pi_get_admin_state, 1077 .pi_get_pw_status = pd692x0_pi_get_pw_status, 1078 .pi_get_ext_state = pd692x0_pi_get_ext_state, 1079 .pi_get_pw_class = pd692x0_pi_get_pw_class, 1080 .pi_get_actual_pw = pd692x0_pi_get_actual_pw, 1081 .pi_enable = pd692x0_pi_enable, 1082 .pi_disable = pd692x0_pi_disable, 1083 .pi_get_voltage = pd692x0_pi_get_voltage, 1084 .pi_get_pw_limit = pd692x0_pi_get_pw_limit, 1085 .pi_set_pw_limit = pd692x0_pi_set_pw_limit, 1086 .pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges, 1087 }; 1088 1089 #define PD692X0_FW_LINE_MAX_SZ 0xff 1090 static int pd692x0_fw_get_next_line(const u8 *data, 1091 char *line, size_t size) 1092 { 1093 size_t line_size; 1094 int i; 1095 1096 line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ); 1097 1098 memset(line, 0, PD692X0_FW_LINE_MAX_SZ); 1099 for (i = 0; i < line_size - 1; i++) { 1100 if (*data == '\r' && *(data + 1) == '\n') { 1101 line[i] = '\r'; 1102 line[i + 1] = '\n'; 1103 return i + 2; 1104 } 1105 line[i] = *data; 1106 data++; 1107 } 1108 1109 return -EIO; 1110 } 1111 1112 static enum fw_upload_err 1113 pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout, 1114 const char *msg_ok, unsigned int msg_size) 1115 { 1116 /* Maximum controller response size */ 1117 char fw_msg_buf[5] = {0}; 1118 unsigned long timeout; 1119 int ret; 1120 1121 if (msg_size > sizeof(fw_msg_buf)) 1122 return FW_UPLOAD_ERR_RW_ERROR; 1123 1124 /* Read until we get something */ 1125 timeout = msecs_to_jiffies(ms_timeout) + jiffies; 1126 while (true) { 1127 if (time_is_before_jiffies(timeout)) 1128 return FW_UPLOAD_ERR_TIMEOUT; 1129 1130 ret = i2c_master_recv(client, fw_msg_buf, 1); 1131 if (ret < 0 || *fw_msg_buf == 0) { 1132 usleep_range(1000, 2000); 1133 continue; 1134 } else { 1135 break; 1136 } 1137 } 1138 1139 /* Read remaining characters */ 1140 ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1); 1141 if (strncmp(fw_msg_buf, msg_ok, msg_size)) { 1142 dev_err(&client->dev, 1143 "Wrong FW download process answer (%*pE)\n", 1144 msg_size, fw_msg_buf); 1145 return FW_UPLOAD_ERR_HW_ERROR; 1146 } 1147 1148 return FW_UPLOAD_ERR_NONE; 1149 } 1150 1151 static int pd692x0_fw_write_line(const struct i2c_client *client, 1152 const char line[PD692X0_FW_LINE_MAX_SZ], 1153 const bool last_line) 1154 { 1155 int ret; 1156 1157 while (*line != 0) { 1158 ret = i2c_master_send(client, line, 1); 1159 if (ret < 0) 1160 return FW_UPLOAD_ERR_RW_ERROR; 1161 line++; 1162 } 1163 1164 if (last_line) { 1165 ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n", 1166 sizeof("TP\r\n") - 1); 1167 if (ret) 1168 return ret; 1169 } else { 1170 ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n", 1171 sizeof("T*\r\n") - 1); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 return FW_UPLOAD_ERR_NONE; 1177 } 1178 1179 static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client) 1180 { 1181 const struct pd692x0_msg zero = {0}; 1182 struct pd692x0_msg buf = {0}; 1183 unsigned long timeout; 1184 char cmd[] = "RST"; 1185 int ret; 1186 1187 ret = i2c_master_send(client, cmd, strlen(cmd)); 1188 if (ret < 0) { 1189 dev_err(&client->dev, 1190 "Failed to reset the controller (%pe)\n", 1191 ERR_PTR(ret)); 1192 return ret; 1193 } 1194 1195 timeout = msecs_to_jiffies(10000) + jiffies; 1196 while (true) { 1197 if (time_is_before_jiffies(timeout)) 1198 return FW_UPLOAD_ERR_TIMEOUT; 1199 1200 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1201 if (ret < 0 || 1202 !memcmp(&buf, &zero, sizeof(buf))) 1203 usleep_range(1000, 2000); 1204 else 1205 break; 1206 } 1207 1208 /* Is the reply a successful report message */ 1209 if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff || 1210 buf.sub[0] & 0x01) { 1211 dev_err(&client->dev, "PSE controller error\n"); 1212 return FW_UPLOAD_ERR_HW_ERROR; 1213 } 1214 1215 /* Is the firmware operational */ 1216 if (buf.sub[0] & 0x02) { 1217 dev_err(&client->dev, 1218 "PSE firmware error. Please update it.\n"); 1219 return FW_UPLOAD_ERR_HW_ERROR; 1220 } 1221 1222 return FW_UPLOAD_ERR_NONE; 1223 } 1224 1225 static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl, 1226 const u8 *data, u32 size) 1227 { 1228 struct pd692x0_priv *priv = fwl->dd_handle; 1229 const struct i2c_client *client = priv->client; 1230 enum pd692x0_fw_state last_fw_state; 1231 int ret; 1232 1233 priv->cancel_request = false; 1234 last_fw_state = priv->fw_state; 1235 1236 priv->fw_state = PD692X0_FW_PREPARE; 1237 1238 /* Enter program mode */ 1239 if (last_fw_state == PD692X0_FW_BROKEN) { 1240 const char *msg = "ENTR"; 1241 const char *c; 1242 1243 c = msg; 1244 do { 1245 ret = i2c_master_send(client, c, 1); 1246 if (ret < 0) 1247 return FW_UPLOAD_ERR_RW_ERROR; 1248 if (*(c + 1)) 1249 usleep_range(10000, 20000); 1250 } while (*(++c)); 1251 } else { 1252 struct pd692x0_msg msg, buf; 1253 1254 msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD]; 1255 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1256 if (ret < 0) { 1257 dev_err(&client->dev, 1258 "Failed to enter programming mode (%pe)\n", 1259 ERR_PTR(ret)); 1260 return FW_UPLOAD_ERR_RW_ERROR; 1261 } 1262 } 1263 1264 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1265 if (ret) 1266 goto err_out; 1267 1268 if (priv->cancel_request) { 1269 ret = FW_UPLOAD_ERR_CANCELED; 1270 goto err_out; 1271 } 1272 1273 return FW_UPLOAD_ERR_NONE; 1274 1275 err_out: 1276 pd692x0_fw_reset(priv->client); 1277 priv->fw_state = last_fw_state; 1278 return ret; 1279 } 1280 1281 static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl, 1282 const u8 *data, u32 offset, 1283 u32 size, u32 *written) 1284 { 1285 struct pd692x0_priv *priv = fwl->dd_handle; 1286 char line[PD692X0_FW_LINE_MAX_SZ]; 1287 const struct i2c_client *client; 1288 int ret, i; 1289 char cmd; 1290 1291 client = priv->client; 1292 priv->fw_state = PD692X0_FW_WRITE; 1293 1294 /* Erase */ 1295 cmd = 'E'; 1296 ret = i2c_master_send(client, &cmd, 1); 1297 if (ret < 0) { 1298 dev_err(&client->dev, 1299 "Failed to boot programming mode (%pe)\n", 1300 ERR_PTR(ret)); 1301 return FW_UPLOAD_ERR_RW_ERROR; 1302 } 1303 1304 ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1); 1305 if (ret) 1306 return ret; 1307 1308 ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1); 1309 if (ret) 1310 dev_warn(&client->dev, 1311 "Failed to erase internal memory, however still try to write Firmware\n"); 1312 1313 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1314 if (ret) 1315 dev_warn(&client->dev, 1316 "Failed to erase internal memory, however still try to write Firmware\n"); 1317 1318 if (priv->cancel_request) 1319 return FW_UPLOAD_ERR_CANCELED; 1320 1321 /* Program */ 1322 cmd = 'P'; 1323 ret = i2c_master_send(client, &cmd, sizeof(char)); 1324 if (ret < 0) { 1325 dev_err(&client->dev, 1326 "Failed to boot programming mode (%pe)\n", 1327 ERR_PTR(ret)); 1328 return ret; 1329 } 1330 1331 ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1); 1332 if (ret) 1333 return ret; 1334 1335 i = 0; 1336 while (i < size) { 1337 ret = pd692x0_fw_get_next_line(data, line, size - i); 1338 if (ret < 0) { 1339 ret = FW_UPLOAD_ERR_FW_INVALID; 1340 goto err; 1341 } 1342 1343 i += ret; 1344 data += ret; 1345 if (line[0] == 'S' && line[1] == '0') { 1346 continue; 1347 } else if (line[0] == 'S' && line[1] == '7') { 1348 ret = pd692x0_fw_write_line(client, line, true); 1349 if (ret) 1350 goto err; 1351 } else { 1352 ret = pd692x0_fw_write_line(client, line, false); 1353 if (ret) 1354 goto err; 1355 } 1356 1357 if (priv->cancel_request) { 1358 ret = FW_UPLOAD_ERR_CANCELED; 1359 goto err; 1360 } 1361 } 1362 *written = i; 1363 1364 msleep(400); 1365 1366 return FW_UPLOAD_ERR_NONE; 1367 1368 err: 1369 strscpy_pad(line, "S7\r\n", sizeof(line)); 1370 pd692x0_fw_write_line(client, line, true); 1371 return ret; 1372 } 1373 1374 static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl) 1375 { 1376 struct pd692x0_priv *priv = fwl->dd_handle; 1377 const struct i2c_client *client = priv->client; 1378 struct pd692x0_msg_ver ver; 1379 int ret; 1380 1381 priv->fw_state = PD692X0_FW_COMPLETE; 1382 1383 ret = pd692x0_fw_reset(client); 1384 if (ret) 1385 return ret; 1386 1387 ver = pd692x0_get_sw_version(priv); 1388 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1389 dev_err(&client->dev, 1390 "Too old firmware version. Please update it\n"); 1391 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1392 return FW_UPLOAD_ERR_FW_INVALID; 1393 } 1394 1395 ret = pd692x0_setup_pi_matrix(&priv->pcdev); 1396 if (ret < 0) { 1397 dev_err(&client->dev, "Error configuring ports matrix (%pe)\n", 1398 ERR_PTR(ret)); 1399 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1400 return FW_UPLOAD_ERR_HW_ERROR; 1401 } 1402 1403 priv->fw_state = PD692X0_FW_OK; 1404 return FW_UPLOAD_ERR_NONE; 1405 } 1406 1407 static void pd692x0_fw_cancel(struct fw_upload *fwl) 1408 { 1409 struct pd692x0_priv *priv = fwl->dd_handle; 1410 1411 priv->cancel_request = true; 1412 } 1413 1414 static void pd692x0_fw_cleanup(struct fw_upload *fwl) 1415 { 1416 struct pd692x0_priv *priv = fwl->dd_handle; 1417 1418 switch (priv->fw_state) { 1419 case PD692X0_FW_WRITE: 1420 pd692x0_fw_reset(priv->client); 1421 fallthrough; 1422 case PD692X0_FW_COMPLETE: 1423 priv->fw_state = PD692X0_FW_BROKEN; 1424 break; 1425 default: 1426 break; 1427 } 1428 } 1429 1430 static const struct fw_upload_ops pd692x0_fw_ops = { 1431 .prepare = pd692x0_fw_prepare, 1432 .write = pd692x0_fw_write, 1433 .poll_complete = pd692x0_fw_poll_complete, 1434 .cancel = pd692x0_fw_cancel, 1435 .cleanup = pd692x0_fw_cleanup, 1436 }; 1437 1438 static int pd692x0_i2c_probe(struct i2c_client *client) 1439 { 1440 struct pd692x0_msg msg, buf = {0}, zero = {0}; 1441 struct device *dev = &client->dev; 1442 struct pd692x0_msg_ver ver; 1443 struct pd692x0_priv *priv; 1444 struct fw_upload *fwl; 1445 int ret; 1446 1447 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1448 dev_err(dev, "i2c check functionality failed\n"); 1449 return -ENXIO; 1450 } 1451 1452 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1453 if (!priv) 1454 return -ENOMEM; 1455 1456 priv->client = client; 1457 i2c_set_clientdata(client, priv); 1458 1459 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1460 if (ret != sizeof(buf)) { 1461 dev_err(dev, "Failed to get device status\n"); 1462 return -EIO; 1463 } 1464 1465 /* Probe has been already run and the status dumped */ 1466 if (!memcmp(&buf, &zero, sizeof(buf))) { 1467 /* Ask again the controller status */ 1468 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS]; 1469 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1470 if (ret < 0) { 1471 dev_err(dev, "Failed to get device status\n"); 1472 return ret; 1473 } 1474 } 1475 1476 if (buf.key != 0x03 || buf.sub[0] & 0x01) { 1477 dev_err(dev, "PSE controller error\n"); 1478 return -EIO; 1479 } 1480 if (buf.sub[0] & 0x02) { 1481 dev_err(dev, "PSE firmware error. Please update it.\n"); 1482 priv->fw_state = PD692X0_FW_BROKEN; 1483 } else { 1484 ver = pd692x0_get_sw_version(priv); 1485 dev_info(&client->dev, "Software version %d.%02d.%d.%d\n", 1486 ver.prod, ver.maj_sw_ver, ver.min_sw_ver, 1487 ver.pa_sw_ver); 1488 1489 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1490 dev_err(dev, "Too old firmware version. Please update it\n"); 1491 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1492 } else { 1493 priv->fw_state = PD692X0_FW_OK; 1494 } 1495 } 1496 1497 priv->np = dev->of_node; 1498 priv->pcdev.nr_lines = PD692X0_MAX_PIS; 1499 priv->pcdev.owner = THIS_MODULE; 1500 priv->pcdev.ops = &pd692x0_ops; 1501 priv->pcdev.dev = dev; 1502 priv->pcdev.types = ETHTOOL_PSE_C33; 1503 ret = devm_pse_controller_register(dev, &priv->pcdev); 1504 if (ret) 1505 return dev_err_probe(dev, ret, 1506 "failed to register PSE controller\n"); 1507 1508 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev), 1509 &pd692x0_fw_ops, priv); 1510 if (IS_ERR(fwl)) 1511 return dev_err_probe(dev, PTR_ERR(fwl), 1512 "failed to register to the Firmware Upload API\n"); 1513 priv->fwl = fwl; 1514 1515 return 0; 1516 } 1517 1518 static void pd692x0_i2c_remove(struct i2c_client *client) 1519 { 1520 struct pd692x0_priv *priv = i2c_get_clientdata(client); 1521 1522 firmware_upload_unregister(priv->fwl); 1523 } 1524 1525 static const struct i2c_device_id pd692x0_id[] = { 1526 { PD692X0_PSE_NAME }, 1527 { } 1528 }; 1529 MODULE_DEVICE_TABLE(i2c, pd692x0_id); 1530 1531 static const struct of_device_id pd692x0_of_match[] = { 1532 { .compatible = "microchip,pd69200", }, 1533 { .compatible = "microchip,pd69210", }, 1534 { .compatible = "microchip,pd69220", }, 1535 { }, 1536 }; 1537 MODULE_DEVICE_TABLE(of, pd692x0_of_match); 1538 1539 static struct i2c_driver pd692x0_driver = { 1540 .probe = pd692x0_i2c_probe, 1541 .remove = pd692x0_i2c_remove, 1542 .id_table = pd692x0_id, 1543 .driver = { 1544 .name = PD692X0_PSE_NAME, 1545 .of_match_table = pd692x0_of_match, 1546 }, 1547 }; 1548 module_i2c_driver(pd692x0_driver); 1549 1550 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1551 MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver"); 1552 MODULE_LICENSE("GPL"); 1553