1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pse-pd/pse.h> 15 #include <linux/regulator/driver.h> 16 #include <linux/regulator/machine.h> 17 18 #define PD692X0_PSE_NAME "pd692x0_pse" 19 20 #define PD692X0_MAX_PIS 48 21 #define PD692X0_MAX_MANAGERS 12 22 #define PD692X0_MAX_MANAGER_PORTS 8 23 #define PD692X0_MAX_HW_PORTS (PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS) 24 25 #define PD69200_BT_PROD_VER 24 26 #define PD69210_BT_PROD_VER 26 27 #define PD69220_BT_PROD_VER 29 28 29 #define PD692X0_FW_MAJ_VER 3 30 #define PD692X0_FW_MIN_VER 5 31 #define PD692X0_FW_PATCH_VER 5 32 33 #define PD692X0_USER_BYTE 42 34 35 enum pd692x0_fw_state { 36 PD692X0_FW_UNKNOWN, 37 PD692X0_FW_OK, 38 PD692X0_FW_BROKEN, 39 PD692X0_FW_NEED_UPDATE, 40 PD692X0_FW_PREPARE, 41 PD692X0_FW_WRITE, 42 PD692X0_FW_COMPLETE, 43 }; 44 45 struct pd692x0_msg { 46 u8 key; 47 u8 echo; 48 u8 sub[3]; 49 u8 data[8]; 50 __be16 chksum; 51 } __packed; 52 53 struct pd692x0_msg_ver { 54 u8 prod; 55 u8 maj_sw_ver; 56 u8 min_sw_ver; 57 u8 pa_sw_ver; 58 u8 param; 59 u8 build; 60 }; 61 62 enum { 63 PD692X0_KEY_CMD, 64 PD692X0_KEY_PRG, 65 PD692X0_KEY_REQ, 66 PD692X0_KEY_TLM, 67 PD692X0_KEY_TEST, 68 PD692X0_KEY_REPORT = 0x52 69 }; 70 71 enum { 72 PD692X0_MSG_RESET, 73 PD692X0_MSG_GET_SYS_STATUS, 74 PD692X0_MSG_GET_SW_VER, 75 PD692X0_MSG_SET_TMP_PORT_MATRIX, 76 PD692X0_MSG_PRG_PORT_MATRIX, 77 PD692X0_MSG_SET_PORT_PARAM, 78 PD692X0_MSG_GET_PORT_STATUS, 79 PD692X0_MSG_DOWNLOAD_CMD, 80 PD692X0_MSG_GET_PORT_CLASS, 81 PD692X0_MSG_GET_PORT_MEAS, 82 PD692X0_MSG_GET_PORT_PARAM, 83 PD692X0_MSG_GET_POWER_BANK, 84 PD692X0_MSG_SET_POWER_BANK, 85 PD692X0_MSG_SET_USER_BYTE, 86 87 /* add new message above here */ 88 PD692X0_MSG_CNT 89 }; 90 91 struct pd692x0_matrix { 92 u8 hw_port_a; 93 u8 hw_port_b; 94 }; 95 96 struct pd692x0_priv { 97 struct i2c_client *client; 98 struct pse_controller_dev pcdev; 99 struct device_node *np; 100 101 enum pd692x0_fw_state fw_state; 102 struct fw_upload *fwl; 103 bool cancel_request; 104 105 u8 msg_id; 106 bool last_cmd_key; 107 unsigned long last_cmd_key_time; 108 109 bool cfg_saved; 110 enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS]; 111 struct regulator_dev *manager_reg[PD692X0_MAX_MANAGERS]; 112 int manager_pw_budget[PD692X0_MAX_MANAGERS]; 113 int nmanagers; 114 struct pd692x0_matrix *port_matrix; 115 }; 116 117 /* Template list of communication messages. The non-null bytes defined here 118 * constitute the fixed portion of the messages. The remaining bytes will 119 * be configured later within the functions. Refer to the "PD692x0 BT Serial 120 * Communication Protocol User Guide" for comprehensive details on messages 121 * content. 122 */ 123 static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = { 124 [PD692X0_MSG_RESET] = { 125 .key = PD692X0_KEY_CMD, 126 .sub = {0x07, 0x55, 0x00}, 127 .data = {0x55, 0x00, 0x55, 0x4e, 128 0x4e, 0x4e, 0x4e, 0x4e}, 129 }, 130 [PD692X0_MSG_GET_SYS_STATUS] = { 131 .key = PD692X0_KEY_REQ, 132 .sub = {0x07, 0xd0, 0x4e}, 133 .data = {0x4e, 0x4e, 0x4e, 0x4e, 134 0x4e, 0x4e, 0x4e, 0x4e}, 135 }, 136 [PD692X0_MSG_GET_SW_VER] = { 137 .key = PD692X0_KEY_REQ, 138 .sub = {0x07, 0x1e, 0x21}, 139 .data = {0x4e, 0x4e, 0x4e, 0x4e, 140 0x4e, 0x4e, 0x4e, 0x4e}, 141 }, 142 [PD692X0_MSG_SET_TMP_PORT_MATRIX] = { 143 .key = PD692X0_KEY_CMD, 144 .sub = {0x05, 0x43}, 145 .data = { 0, 0x4e, 0x4e, 0x4e, 146 0x4e, 0x4e, 0x4e, 0x4e}, 147 }, 148 [PD692X0_MSG_PRG_PORT_MATRIX] = { 149 .key = PD692X0_KEY_CMD, 150 .sub = {0x07, 0x43, 0x4e}, 151 .data = {0x4e, 0x4e, 0x4e, 0x4e, 152 0x4e, 0x4e, 0x4e, 0x4e}, 153 }, 154 [PD692X0_MSG_SET_PORT_PARAM] = { 155 .key = PD692X0_KEY_CMD, 156 .sub = {0x05, 0xc0}, 157 .data = { 0xf, 0xff, 0xff, 0xff, 158 0x4e, 0x4e, 0x4e, 0x4e}, 159 }, 160 [PD692X0_MSG_GET_PORT_STATUS] = { 161 .key = PD692X0_KEY_REQ, 162 .sub = {0x05, 0xc1}, 163 .data = {0x4e, 0x4e, 0x4e, 0x4e, 164 0x4e, 0x4e, 0x4e, 0x4e}, 165 }, 166 [PD692X0_MSG_DOWNLOAD_CMD] = { 167 .key = PD692X0_KEY_PRG, 168 .sub = {0xff, 0x99, 0x15}, 169 .data = {0x16, 0x16, 0x99, 0x4e, 170 0x4e, 0x4e, 0x4e, 0x4e}, 171 }, 172 [PD692X0_MSG_GET_PORT_CLASS] = { 173 .key = PD692X0_KEY_REQ, 174 .sub = {0x05, 0xc4}, 175 .data = {0x4e, 0x4e, 0x4e, 0x4e, 176 0x4e, 0x4e, 0x4e, 0x4e}, 177 }, 178 [PD692X0_MSG_GET_PORT_MEAS] = { 179 .key = PD692X0_KEY_REQ, 180 .sub = {0x05, 0xc5}, 181 .data = {0x4e, 0x4e, 0x4e, 0x4e, 182 0x4e, 0x4e, 0x4e, 0x4e}, 183 }, 184 [PD692X0_MSG_GET_PORT_PARAM] = { 185 .key = PD692X0_KEY_REQ, 186 .sub = {0x05, 0xc0}, 187 .data = {0x4e, 0x4e, 0x4e, 0x4e, 188 0x4e, 0x4e, 0x4e, 0x4e}, 189 }, 190 [PD692X0_MSG_GET_POWER_BANK] = { 191 .key = PD692X0_KEY_REQ, 192 .sub = {0x07, 0x0b, 0x57}, 193 .data = { 0, 0x4e, 0x4e, 0x4e, 194 0x4e, 0x4e, 0x4e, 0x4e}, 195 }, 196 [PD692X0_MSG_SET_POWER_BANK] = { 197 .key = PD692X0_KEY_CMD, 198 .sub = {0x07, 0x0b, 0x57}, 199 }, 200 [PD692X0_MSG_SET_USER_BYTE] = { 201 .key = PD692X0_KEY_PRG, 202 .sub = {0x41, PD692X0_USER_BYTE}, 203 .data = {0x4e, 0x4e, 0x4e, 0x4e, 204 0x4e, 0x4e, 0x4e, 0x4e}, 205 }, 206 }; 207 208 static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo) 209 { 210 u8 *data = (u8 *)msg; 211 u16 chksum = 0; 212 int i; 213 214 msg->echo = echo++; 215 if (echo == 0xff) 216 echo = 0; 217 218 for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++) 219 chksum += data[i]; 220 221 msg->chksum = cpu_to_be16(chksum); 222 223 return echo; 224 } 225 226 static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg) 227 { 228 const struct i2c_client *client = priv->client; 229 int ret; 230 231 if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) { 232 int cmd_msleep; 233 234 cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time); 235 if (cmd_msleep > 0) 236 msleep(cmd_msleep); 237 } 238 239 /* Add echo and checksum bytes to the message */ 240 priv->msg_id = pd692x0_build_msg(msg, priv->msg_id); 241 242 ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg)); 243 if (ret != sizeof(*msg)) 244 return -EIO; 245 246 return 0; 247 } 248 249 static int pd692x0_reset(struct pd692x0_priv *priv) 250 { 251 const struct i2c_client *client = priv->client; 252 struct pd692x0_msg msg, buf = {0}; 253 int ret; 254 255 msg = pd692x0_msg_template_list[PD692X0_MSG_RESET]; 256 ret = pd692x0_send_msg(priv, &msg); 257 if (ret) { 258 dev_err(&client->dev, 259 "Failed to reset the controller (%pe)\n", ERR_PTR(ret)); 260 return ret; 261 } 262 263 msleep(30); 264 265 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 266 if (ret != sizeof(buf)) 267 return ret < 0 ? ret : -EIO; 268 269 /* Is the reply a successful report message */ 270 if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1]) 271 return -EIO; 272 273 msleep(300); 274 275 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 276 if (ret != sizeof(buf)) 277 return ret < 0 ? ret : -EIO; 278 279 /* Is the boot status without error */ 280 if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) { 281 dev_err(&client->dev, "PSE controller error\n"); 282 return -EIO; 283 } 284 285 return 0; 286 } 287 288 static bool pd692x0_try_recv_msg(const struct i2c_client *client, 289 struct pd692x0_msg *msg, 290 struct pd692x0_msg *buf) 291 { 292 /* Wait 30ms before readback as mandated by the protocol */ 293 msleep(30); 294 295 memset(buf, 0, sizeof(*buf)); 296 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 297 if (buf->key) 298 return 0; 299 300 msleep(100); 301 302 memset(buf, 0, sizeof(*buf)); 303 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 304 if (buf->key) 305 return 0; 306 307 return 1; 308 } 309 310 /* Implementation of I2C communication, specifically addressing scenarios 311 * involving communication loss. Refer to the "Synchronization During 312 * Communication Loss" section in the Communication Protocol document for 313 * further details. 314 */ 315 static int pd692x0_recv_msg(struct pd692x0_priv *priv, 316 struct pd692x0_msg *msg, 317 struct pd692x0_msg *buf) 318 { 319 const struct i2c_client *client = priv->client; 320 int ret; 321 322 ret = pd692x0_try_recv_msg(client, msg, buf); 323 if (!ret) 324 goto out_success; 325 326 dev_warn(&client->dev, 327 "Communication lost, rtnl is locked until communication is back!"); 328 329 ret = pd692x0_send_msg(priv, msg); 330 if (ret) 331 return ret; 332 333 ret = pd692x0_try_recv_msg(client, msg, buf); 334 if (!ret) 335 goto out_success2; 336 337 msleep(10000); 338 339 ret = pd692x0_send_msg(priv, msg); 340 if (ret) 341 return ret; 342 343 ret = pd692x0_try_recv_msg(client, msg, buf); 344 if (!ret) 345 goto out_success2; 346 347 return pd692x0_reset(priv); 348 349 out_success2: 350 dev_warn(&client->dev, "Communication is back, rtnl is unlocked!"); 351 out_success: 352 if (msg->key == PD692X0_KEY_CMD) { 353 priv->last_cmd_key = true; 354 priv->last_cmd_key_time = jiffies; 355 } else { 356 priv->last_cmd_key = false; 357 } 358 359 return 0; 360 } 361 362 static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv, 363 struct pd692x0_msg *msg, 364 struct pd692x0_msg *buf) 365 { 366 struct device *dev = &priv->client->dev; 367 int ret; 368 369 ret = pd692x0_send_msg(priv, msg); 370 if (ret) 371 return ret; 372 373 ret = pd692x0_recv_msg(priv, msg, buf); 374 if (ret) 375 return ret; 376 377 if (msg->echo != buf->echo) { 378 dev_err(dev, 379 "Wrong match in message ID, expect %d received %d.\n", 380 msg->echo, buf->echo); 381 return -EIO; 382 } 383 384 /* If the reply is a report message is it successful */ 385 if (buf->key == PD692X0_KEY_REPORT && 386 (buf->sub[0] || buf->sub[1])) { 387 return -EIO; 388 } 389 390 return 0; 391 } 392 393 static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev) 394 { 395 return container_of(pcdev, struct pd692x0_priv, pcdev); 396 } 397 398 static int pd692x0_fw_unavailable(struct pd692x0_priv *priv) 399 { 400 switch (priv->fw_state) { 401 case PD692X0_FW_OK: 402 return 0; 403 case PD692X0_FW_PREPARE: 404 case PD692X0_FW_WRITE: 405 case PD692X0_FW_COMPLETE: 406 dev_err(&priv->client->dev, "Firmware update in progress!\n"); 407 return -EBUSY; 408 case PD692X0_FW_BROKEN: 409 case PD692X0_FW_NEED_UPDATE: 410 default: 411 dev_err(&priv->client->dev, 412 "Firmware issue. Please update it!\n"); 413 return -EOPNOTSUPP; 414 } 415 } 416 417 static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id) 418 { 419 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 420 struct pd692x0_msg msg, buf = {0}; 421 int ret; 422 423 ret = pd692x0_fw_unavailable(priv); 424 if (ret) 425 return ret; 426 427 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 428 return 0; 429 430 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 431 msg.data[0] = 0x1; 432 msg.sub[2] = id; 433 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 434 if (ret < 0) 435 return ret; 436 437 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 438 439 return 0; 440 } 441 442 static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id) 443 { 444 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 445 struct pd692x0_msg msg, buf = {0}; 446 int ret; 447 448 ret = pd692x0_fw_unavailable(priv); 449 if (ret) 450 return ret; 451 452 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED) 453 return 0; 454 455 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 456 msg.data[0] = 0x0; 457 msg.sub[2] = id; 458 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 459 if (ret < 0) 460 return ret; 461 462 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 463 464 return 0; 465 } 466 467 struct pd692x0_pse_ext_state_mapping { 468 u32 status_code; 469 enum ethtool_c33_pse_ext_state pse_ext_state; 470 u32 pse_ext_substate; 471 }; 472 473 static const struct pd692x0_pse_ext_state_mapping 474 pd692x0_pse_ext_state_map[] = { 475 {0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 476 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE}, 477 {0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 478 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE}, 479 {0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE, 480 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE}, 481 {0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 482 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT}, 483 {0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 484 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT}, 485 {0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 486 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 487 {0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 488 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS}, 489 {0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 490 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 491 {0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 492 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD}, 493 {0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED, 494 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD}, 495 {0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 496 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED}, 497 {0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 498 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 499 {0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 500 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE}, 501 {0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 502 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION}, 503 {0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 504 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 505 {0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED, 506 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION}, 507 {0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 508 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 509 {0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 510 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 511 {0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 512 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 513 {0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 514 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET}, 515 {0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 516 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT}, 517 {0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 518 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT}, 519 {0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 520 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 521 {0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 522 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR}, 523 {0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 524 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN}, 525 { /* sentinel */ } 526 }; 527 528 static int 529 pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id, 530 struct pse_ext_state_info *ext_state_info) 531 { 532 struct ethtool_c33_pse_ext_state_info *c33_ext_state_info; 533 const struct pd692x0_pse_ext_state_mapping *ext_state_map; 534 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 535 struct pd692x0_msg msg, buf = {0}; 536 int ret; 537 538 ret = pd692x0_fw_unavailable(priv); 539 if (ret) 540 return ret; 541 542 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 543 msg.sub[2] = id; 544 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 545 if (ret < 0) 546 return ret; 547 548 c33_ext_state_info = &ext_state_info->c33_ext_state_info; 549 ext_state_map = pd692x0_pse_ext_state_map; 550 while (ext_state_map->status_code) { 551 if (ext_state_map->status_code == buf.sub[0]) { 552 c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state; 553 c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate; 554 return 0; 555 } 556 ext_state_map++; 557 } 558 559 return 0; 560 } 561 562 struct pd692x0_class_pw { 563 int class; 564 int class_cfg_value; 565 int class_pw; 566 int max_added_class_pw; 567 }; 568 569 #define PD692X0_CLASS_PW_TABLE_SIZE 4 570 /* 4/2 pairs class configuration power table in compliance mode. 571 * Need to be arranged in ascending order of power support. 572 */ 573 static const struct pd692x0_class_pw 574 pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = { 575 {.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100}, 576 {.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000}, 577 {.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000}, 578 {.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500}, 579 }; 580 581 static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw) 582 { 583 const struct pd692x0_class_pw *pw_table; 584 int i; 585 586 pw_table = pd692x0_class_pw_table; 587 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 588 if (pw_table->class_cfg_value == op_mode) 589 return pw_table->class_pw + added_pw * 100; 590 } 591 592 return -ERANGE; 593 } 594 595 static int pd692x0_pi_set_pw_from_table(struct device *dev, 596 struct pd692x0_msg *msg, int pw) 597 { 598 const struct pd692x0_class_pw *pw_table; 599 int i; 600 601 pw_table = pd692x0_class_pw_table; 602 if (pw < pw_table->class_pw) { 603 dev_err(dev, 604 "Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n", 605 pw, 606 pw_table->class_pw, 607 pw_table->class_pw + pw_table->max_added_class_pw); 608 return -ERANGE; 609 } 610 611 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 612 if (pw > (pw_table->class_pw + pw_table->max_added_class_pw)) 613 continue; 614 615 if (pw < pw_table->class_pw) { 616 dev_err(dev, 617 "Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n", 618 pw, 619 (pw_table - 1)->class_pw, 620 (pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw, 621 pw_table->class_pw, 622 pw_table->class_pw + pw_table->max_added_class_pw); 623 return -ERANGE; 624 } 625 626 msg->data[2] = pw_table->class_cfg_value; 627 msg->data[3] = (pw - pw_table->class_pw) / 100; 628 return 0; 629 } 630 631 pw_table--; 632 dev_warn(dev, 633 "Power limit %dmW not supported. Set to highest power limit %dmW\n", 634 pw, pw_table->class_pw + pw_table->max_added_class_pw); 635 msg->data[2] = pw_table->class_cfg_value; 636 msg->data[3] = pw_table->max_added_class_pw / 100; 637 return 0; 638 } 639 640 static int 641 pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 642 struct pse_pw_limit_ranges *pw_limit_ranges) 643 { 644 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 645 const struct pd692x0_class_pw *pw_table; 646 int i; 647 648 pw_table = pd692x0_class_pw_table; 649 c33_pw_limit_ranges = kzalloc_objs(*c33_pw_limit_ranges, 650 PD692X0_CLASS_PW_TABLE_SIZE); 651 if (!c33_pw_limit_ranges) 652 return -ENOMEM; 653 654 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 655 c33_pw_limit_ranges[i].min = pw_table->class_pw; 656 c33_pw_limit_ranges[i].max = pw_table->class_pw + 657 pw_table->max_added_class_pw; 658 } 659 660 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 661 return i; 662 } 663 664 static int 665 pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 666 struct pse_admin_state *admin_state) 667 { 668 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 669 struct pd692x0_msg msg, buf = {0}; 670 int ret; 671 672 ret = pd692x0_fw_unavailable(priv); 673 if (ret) 674 return ret; 675 676 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 677 msg.sub[2] = id; 678 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 679 if (ret < 0) 680 return ret; 681 682 if (buf.sub[1]) 683 admin_state->c33_admin_state = 684 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 685 else 686 admin_state->c33_admin_state = 687 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 688 689 priv->admin_state[id] = admin_state->c33_admin_state; 690 691 return 0; 692 } 693 694 static int 695 pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 696 struct pse_pw_status *pw_status) 697 { 698 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 699 struct pd692x0_msg msg, buf = {0}; 700 int ret; 701 702 ret = pd692x0_fw_unavailable(priv); 703 if (ret) 704 return ret; 705 706 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 707 msg.sub[2] = id; 708 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 709 if (ret < 0) 710 return ret; 711 712 /* Compare Port Status (Communication Protocol Document par. 7.1) */ 713 if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90) 714 pw_status->c33_pw_status = 715 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 716 else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22) 717 pw_status->c33_pw_status = 718 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING; 719 else if (buf.sub[0] == 0x12) 720 pw_status->c33_pw_status = 721 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT; 722 else 723 pw_status->c33_pw_status = 724 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 725 726 return 0; 727 } 728 729 static int 730 pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id) 731 { 732 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 733 struct pd692x0_msg msg, buf = {0}; 734 u32 class; 735 int ret; 736 737 ret = pd692x0_fw_unavailable(priv); 738 if (ret) 739 return ret; 740 741 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS]; 742 msg.sub[2] = id; 743 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 744 if (ret < 0) 745 return ret; 746 747 class = buf.data[3] >> 4; 748 if (class <= 8) 749 return class; 750 751 return 0; 752 } 753 754 static int 755 pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 756 { 757 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 758 struct pd692x0_msg msg, buf = {0}; 759 int ret; 760 761 ret = pd692x0_fw_unavailable(priv); 762 if (ret) 763 return ret; 764 765 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 766 msg.sub[2] = id; 767 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 768 if (ret < 0) 769 return ret; 770 771 return (buf.data[0] << 4 | buf.data[1]) * 100; 772 } 773 774 static int 775 pd692x0_pi_get_prio(struct pse_controller_dev *pcdev, int id) 776 { 777 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 778 struct pd692x0_msg msg, buf = {0}; 779 int ret; 780 781 ret = pd692x0_fw_unavailable(priv); 782 if (ret) 783 return ret; 784 785 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 786 msg.sub[2] = id; 787 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 788 if (ret < 0) 789 return ret; 790 if (!buf.data[2] || buf.data[2] > pcdev->pis_prio_max + 1) 791 return -ERANGE; 792 793 /* PSE core priority start at 0 */ 794 return buf.data[2] - 1; 795 } 796 797 static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv) 798 { 799 struct device *dev = &priv->client->dev; 800 struct pd692x0_msg msg, buf = {0}; 801 struct pd692x0_msg_ver ver = {0}; 802 int ret; 803 804 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER]; 805 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 806 if (ret < 0) { 807 dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret)); 808 return ver; 809 } 810 811 /* Extract version from the message */ 812 ver.prod = buf.sub[2]; 813 ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100; 814 ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10; 815 ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10; 816 ver.param = buf.data[2]; 817 ver.build = buf.data[3]; 818 819 return ver; 820 } 821 822 struct pd692x0_manager { 823 struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS]; 824 struct device_node *node; 825 int nports; 826 }; 827 828 static int 829 pd692x0_of_get_ports_manager(struct pd692x0_priv *priv, 830 struct pd692x0_manager *manager, 831 struct device_node *np) 832 { 833 struct device_node *node; 834 int ret, nports, i; 835 836 nports = 0; 837 for_each_child_of_node(np, node) { 838 u32 port; 839 840 if (!of_node_name_eq(node, "port")) 841 continue; 842 843 ret = of_property_read_u32(node, "reg", &port); 844 if (ret) 845 goto out; 846 847 if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) { 848 dev_err(&priv->client->dev, 849 "wrong number or order of manager ports (%d)\n", 850 port); 851 ret = -EINVAL; 852 goto out; 853 } 854 855 of_node_get(node); 856 manager->port_node[port] = node; 857 nports++; 858 } 859 860 manager->nports = nports; 861 return 0; 862 863 out: 864 for (i = 0; i < nports; i++) { 865 of_node_put(manager->port_node[i]); 866 manager->port_node[i] = NULL; 867 } 868 of_node_put(node); 869 return ret; 870 } 871 872 static int 873 pd692x0_of_get_managers(struct pd692x0_priv *priv, 874 struct pd692x0_manager *manager) 875 { 876 struct device_node *managers_node, *node; 877 int ret, nmanagers, i, j; 878 879 if (!priv->np) 880 return -EINVAL; 881 882 nmanagers = 0; 883 managers_node = of_get_child_by_name(priv->np, "managers"); 884 if (!managers_node) 885 return -EINVAL; 886 887 for_each_child_of_node(managers_node, node) { 888 u32 manager_id; 889 890 if (!of_node_name_eq(node, "manager")) 891 continue; 892 893 ret = of_property_read_u32(node, "reg", &manager_id); 894 if (ret) 895 goto out; 896 897 if (manager_id >= PD692X0_MAX_MANAGERS || 898 manager_id != nmanagers) { 899 dev_err(&priv->client->dev, 900 "wrong number or order of managers (%d)\n", 901 manager_id); 902 ret = -EINVAL; 903 goto out; 904 } 905 906 ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id], 907 node); 908 if (ret) 909 goto out; 910 911 of_node_get(node); 912 manager[manager_id].node = node; 913 nmanagers++; 914 } 915 916 of_node_put(managers_node); 917 priv->nmanagers = nmanagers; 918 return 0; 919 920 out: 921 for (i = 0; i < nmanagers; i++) { 922 for (j = 0; j < manager[i].nports; j++) { 923 of_node_put(manager[i].port_node[j]); 924 manager[i].port_node[j] = NULL; 925 } 926 of_node_put(manager[i].node); 927 manager[i].node = NULL; 928 } 929 930 of_node_put(node); 931 of_node_put(managers_node); 932 return ret; 933 } 934 935 static const struct regulator_ops dummy_ops; 936 937 static struct regulator_dev * 938 pd692x0_register_manager_regulator(struct device *dev, char *reg_name, 939 struct device_node *node) 940 { 941 struct regulator_init_data *rinit_data; 942 struct regulator_config rconfig = {0}; 943 struct regulator_desc *rdesc; 944 struct regulator_dev *rdev; 945 946 rinit_data = devm_kzalloc(dev, sizeof(*rinit_data), 947 GFP_KERNEL); 948 if (!rinit_data) 949 return ERR_PTR(-ENOMEM); 950 951 rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); 952 if (!rdesc) 953 return ERR_PTR(-ENOMEM); 954 955 rdesc->name = reg_name; 956 rdesc->type = REGULATOR_VOLTAGE; 957 rdesc->ops = &dummy_ops; 958 rdesc->owner = THIS_MODULE; 959 960 rinit_data->supply_regulator = "vmain"; 961 962 rconfig.dev = dev; 963 rconfig.init_data = rinit_data; 964 rconfig.of_node = node; 965 966 rdev = devm_regulator_register(dev, rdesc, &rconfig); 967 if (IS_ERR(rdev)) { 968 dev_err_probe(dev, PTR_ERR(rdev), 969 "Failed to register regulator\n"); 970 return rdev; 971 } 972 973 return rdev; 974 } 975 976 static int 977 pd692x0_register_managers_regulator(struct pd692x0_priv *priv, 978 const struct pd692x0_manager *manager) 979 { 980 struct device *dev = &priv->client->dev; 981 size_t reg_name_len; 982 int i; 983 984 /* Each regulator name len is dev name + 12 char + 985 * int max digit number (10) + 1 986 */ 987 reg_name_len = strlen(dev_name(dev)) + 23; 988 989 for (i = 0; i < priv->nmanagers; i++) { 990 static const char * const regulators[] = { "vaux5", "vaux3p3" }; 991 struct regulator_dev *rdev; 992 char *reg_name; 993 int ret; 994 995 reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL); 996 if (!reg_name) 997 return -ENOMEM; 998 snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i); 999 rdev = pd692x0_register_manager_regulator(dev, reg_name, 1000 manager[i].node); 1001 if (IS_ERR(rdev)) 1002 return PTR_ERR(rdev); 1003 1004 /* VMAIN is described as main supply for the manager. 1005 * Add other VAUX power supplies and link them to the 1006 * virtual device rdev->dev. 1007 */ 1008 ret = devm_regulator_bulk_get_enable(&rdev->dev, 1009 ARRAY_SIZE(regulators), 1010 regulators); 1011 if (ret) 1012 return dev_err_probe(&rdev->dev, ret, 1013 "Failed to enable regulators\n"); 1014 1015 priv->manager_reg[i] = rdev; 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int 1022 pd692x0_conf_manager_power_budget(struct pd692x0_priv *priv, int id) 1023 { 1024 struct pd692x0_msg msg, buf; 1025 int ret, pw_mW; 1026 1027 pw_mW = priv->manager_pw_budget[id] / 1000; 1028 if (!pw_mW) 1029 return 0; 1030 1031 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_POWER_BANK]; 1032 msg.data[0] = id; 1033 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1034 if (ret < 0) 1035 return ret; 1036 1037 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_POWER_BANK]; 1038 msg.data[0] = id; 1039 msg.data[1] = pw_mW >> 8; 1040 msg.data[2] = pw_mW & 0xff; 1041 msg.data[3] = buf.sub[2]; 1042 msg.data[4] = buf.data[0]; 1043 msg.data[5] = buf.data[1]; 1044 msg.data[6] = buf.data[2]; 1045 msg.data[7] = buf.data[3]; 1046 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1047 } 1048 1049 static int 1050 pd692x0_req_managers_pw_budget(struct pd692x0_priv *priv) 1051 { 1052 int i, ret; 1053 1054 for (i = 0; i < priv->nmanagers; i++) { 1055 struct regulator *supply = priv->manager_reg[i]->supply; 1056 int pw_budget; 1057 1058 pw_budget = regulator_get_unclaimed_power_budget(supply); 1059 if (!pw_budget) 1060 /* Do nothing if no power budget */ 1061 continue; 1062 1063 /* Max power budget per manager */ 1064 if (pw_budget > 6000000) 1065 pw_budget = 6000000; 1066 ret = regulator_request_power_budget(supply, pw_budget); 1067 if (ret < 0) 1068 return ret; 1069 1070 priv->manager_pw_budget[i] = pw_budget; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int 1077 pd692x0_configure_managers(struct pd692x0_priv *priv) 1078 { 1079 int i, ret; 1080 1081 for (i = 0; i < priv->nmanagers; i++) { 1082 ret = pd692x0_conf_manager_power_budget(priv, i); 1083 if (ret < 0) 1084 return ret; 1085 } 1086 1087 return 0; 1088 } 1089 1090 static int 1091 pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset, 1092 const struct pd692x0_manager *manager, 1093 int nmanagers, struct pd692x0_matrix *port_matrix) 1094 { 1095 int i, j, port_cnt; 1096 bool found = false; 1097 1098 if (!pairset->np) 1099 return 0; 1100 1101 /* Look on every managers */ 1102 port_cnt = 0; 1103 for (i = 0; i < nmanagers; i++) { 1104 /* Look on every ports of the manager */ 1105 for (j = 0; j < manager[i].nports; j++) { 1106 if (pairset->np == manager[i].port_node[j]) { 1107 found = true; 1108 break; 1109 } 1110 } 1111 port_cnt += j; 1112 1113 if (found) 1114 break; 1115 } 1116 1117 if (!found) 1118 return -ENODEV; 1119 1120 if (pairset->pinout == ALTERNATIVE_A) 1121 port_matrix->hw_port_a = port_cnt; 1122 else if (pairset->pinout == ALTERNATIVE_B) 1123 port_matrix->hw_port_b = port_cnt; 1124 1125 return 0; 1126 } 1127 1128 static int 1129 pd692x0_set_ports_matrix(struct pd692x0_priv *priv, 1130 const struct pd692x0_manager *manager) 1131 { 1132 struct pd692x0_matrix *port_matrix = priv->port_matrix; 1133 struct pse_controller_dev *pcdev = &priv->pcdev; 1134 int i, ret; 1135 1136 /* Init Matrix */ 1137 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1138 port_matrix[i].hw_port_a = 0xff; 1139 port_matrix[i].hw_port_b = 0xff; 1140 } 1141 1142 /* Update with values for every PSE PIs */ 1143 for (i = 0; i < pcdev->nr_lines; i++) { 1144 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0], 1145 manager, priv->nmanagers, 1146 &port_matrix[i]); 1147 if (ret) { 1148 dev_err(&priv->client->dev, 1149 "unable to configure pi %d pairset 0", i); 1150 return ret; 1151 } 1152 1153 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1], 1154 manager, priv->nmanagers, 1155 &port_matrix[i]); 1156 if (ret) { 1157 dev_err(&priv->client->dev, 1158 "unable to configure pi %d pairset 1", i); 1159 return ret; 1160 } 1161 } 1162 1163 return 0; 1164 } 1165 1166 static int 1167 pd692x0_write_ports_matrix(struct pd692x0_priv *priv) 1168 { 1169 struct pd692x0_matrix *port_matrix = priv->port_matrix; 1170 struct pd692x0_msg msg, buf; 1171 int ret, i; 1172 1173 /* Write temporary Matrix */ 1174 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX]; 1175 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1176 msg.sub[2] = i; 1177 msg.data[0] = port_matrix[i].hw_port_b; 1178 msg.data[1] = port_matrix[i].hw_port_a; 1179 1180 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1181 if (ret < 0) 1182 return ret; 1183 } 1184 1185 /* Program Matrix */ 1186 msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX]; 1187 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1188 if (ret < 0) 1189 return ret; 1190 1191 return 0; 1192 } 1193 1194 static int pd692x0_hw_conf_init(struct pd692x0_priv *priv) 1195 { 1196 int ret; 1197 1198 /* Is PD692x0 ready to be configured? */ 1199 if (priv->fw_state != PD692X0_FW_OK && 1200 priv->fw_state != PD692X0_FW_COMPLETE) 1201 return 0; 1202 1203 ret = pd692x0_configure_managers(priv); 1204 if (ret) 1205 return ret; 1206 1207 ret = pd692x0_write_ports_matrix(priv); 1208 if (ret) 1209 return ret; 1210 1211 return 0; 1212 } 1213 1214 static void pd692x0_of_put_managers(struct pd692x0_priv *priv, 1215 struct pd692x0_manager *manager) 1216 { 1217 int i, j; 1218 1219 for (i = 0; i < priv->nmanagers; i++) { 1220 for (j = 0; j < manager[i].nports; j++) 1221 of_node_put(manager[i].port_node[j]); 1222 of_node_put(manager[i].node); 1223 } 1224 } 1225 1226 static void pd692x0_managers_free_pw_budget(struct pd692x0_priv *priv) 1227 { 1228 int i; 1229 1230 for (i = 0; i < PD692X0_MAX_MANAGERS; i++) { 1231 struct regulator *supply; 1232 1233 if (!priv->manager_reg[i] || !priv->manager_pw_budget[i]) 1234 continue; 1235 1236 supply = priv->manager_reg[i]->supply; 1237 if (!supply) 1238 continue; 1239 1240 regulator_free_power_budget(supply, 1241 priv->manager_pw_budget[i]); 1242 } 1243 } 1244 1245 static int 1246 pd692x0_save_user_byte(struct pd692x0_priv *priv) 1247 { 1248 struct pd692x0_msg msg, buf; 1249 1250 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_USER_BYTE]; 1251 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1252 } 1253 1254 static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev) 1255 { 1256 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1257 struct pd692x0_matrix *port_matrix; 1258 struct pd692x0_manager *manager; 1259 int ret; 1260 1261 manager = kzalloc_objs(*manager, PD692X0_MAX_MANAGERS); 1262 if (!manager) 1263 return -ENOMEM; 1264 1265 port_matrix = devm_kcalloc(&priv->client->dev, PD692X0_MAX_PIS, 1266 sizeof(*port_matrix), GFP_KERNEL); 1267 if (!port_matrix) { 1268 ret = -ENOMEM; 1269 goto err_free_manager; 1270 } 1271 priv->port_matrix = port_matrix; 1272 1273 ret = pd692x0_of_get_managers(priv, manager); 1274 if (ret < 0) 1275 goto err_free_manager; 1276 1277 ret = pd692x0_register_managers_regulator(priv, manager); 1278 if (ret) 1279 goto err_of_managers; 1280 1281 ret = pd692x0_req_managers_pw_budget(priv); 1282 if (ret) 1283 goto err_of_managers; 1284 1285 ret = pd692x0_set_ports_matrix(priv, manager); 1286 if (ret) 1287 goto err_managers_req_pw; 1288 1289 /* Do not init the conf if it is already saved */ 1290 if (!priv->cfg_saved) { 1291 ret = pd692x0_hw_conf_init(priv); 1292 if (ret) 1293 goto err_managers_req_pw; 1294 1295 ret = pd692x0_save_user_byte(priv); 1296 if (ret) 1297 goto err_managers_req_pw; 1298 } 1299 1300 pd692x0_of_put_managers(priv, manager); 1301 kfree(manager); 1302 return 0; 1303 1304 err_managers_req_pw: 1305 pd692x0_managers_free_pw_budget(priv); 1306 err_of_managers: 1307 pd692x0_of_put_managers(priv, manager); 1308 err_free_manager: 1309 kfree(manager); 1310 return ret; 1311 } 1312 1313 static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 1314 { 1315 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1316 struct pd692x0_msg msg, buf = {0}; 1317 int ret; 1318 1319 ret = pd692x0_fw_unavailable(priv); 1320 if (ret) 1321 return ret; 1322 1323 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS]; 1324 msg.sub[2] = id; 1325 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1326 if (ret < 0) 1327 return ret; 1328 1329 /* Convert 0.1V unit to uV */ 1330 return (buf.sub[0] << 8 | buf.sub[1]) * 100000; 1331 } 1332 1333 static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev, 1334 int id) 1335 { 1336 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1337 struct pd692x0_msg msg, buf = {0}; 1338 int ret; 1339 1340 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 1341 msg.sub[2] = id; 1342 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1343 if (ret < 0) 1344 return ret; 1345 1346 return pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]); 1347 } 1348 1349 static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev, 1350 int id, int max_mW) 1351 { 1352 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1353 struct device *dev = &priv->client->dev; 1354 struct pd692x0_msg msg, buf = {0}; 1355 int ret; 1356 1357 ret = pd692x0_fw_unavailable(priv); 1358 if (ret) 1359 return ret; 1360 1361 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1362 msg.sub[2] = id; 1363 ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW); 1364 if (ret) 1365 return ret; 1366 1367 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1368 } 1369 1370 static int pd692x0_pi_set_prio(struct pse_controller_dev *pcdev, int id, 1371 unsigned int prio) 1372 { 1373 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1374 struct pd692x0_msg msg, buf = {0}; 1375 int ret; 1376 1377 ret = pd692x0_fw_unavailable(priv); 1378 if (ret) 1379 return ret; 1380 1381 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1382 msg.sub[2] = id; 1383 /* Controller priority from 1 to 3 */ 1384 msg.data[4] = prio + 1; 1385 1386 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1387 } 1388 1389 static const struct pse_controller_ops pd692x0_ops = { 1390 .setup_pi_matrix = pd692x0_setup_pi_matrix, 1391 .pi_get_admin_state = pd692x0_pi_get_admin_state, 1392 .pi_get_pw_status = pd692x0_pi_get_pw_status, 1393 .pi_get_ext_state = pd692x0_pi_get_ext_state, 1394 .pi_get_pw_class = pd692x0_pi_get_pw_class, 1395 .pi_get_actual_pw = pd692x0_pi_get_actual_pw, 1396 .pi_enable = pd692x0_pi_enable, 1397 .pi_disable = pd692x0_pi_disable, 1398 .pi_get_voltage = pd692x0_pi_get_voltage, 1399 .pi_get_pw_limit = pd692x0_pi_get_pw_limit, 1400 .pi_set_pw_limit = pd692x0_pi_set_pw_limit, 1401 .pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges, 1402 .pi_get_prio = pd692x0_pi_get_prio, 1403 .pi_set_prio = pd692x0_pi_set_prio, 1404 }; 1405 1406 #define PD692X0_FW_LINE_MAX_SZ 0xff 1407 static int pd692x0_fw_get_next_line(const u8 *data, 1408 char *line, size_t size) 1409 { 1410 size_t line_size; 1411 int i; 1412 1413 line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ); 1414 1415 memset(line, 0, PD692X0_FW_LINE_MAX_SZ); 1416 for (i = 0; i < line_size - 1; i++) { 1417 if (*data == '\r' && *(data + 1) == '\n') { 1418 line[i] = '\r'; 1419 line[i + 1] = '\n'; 1420 return i + 2; 1421 } 1422 line[i] = *data; 1423 data++; 1424 } 1425 1426 return -EIO; 1427 } 1428 1429 static enum fw_upload_err 1430 pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout, 1431 const char *msg_ok, unsigned int msg_size) 1432 { 1433 /* Maximum controller response size */ 1434 char fw_msg_buf[5] = {0}; 1435 unsigned long timeout; 1436 int ret; 1437 1438 if (msg_size > sizeof(fw_msg_buf)) 1439 return FW_UPLOAD_ERR_RW_ERROR; 1440 1441 /* Read until we get something */ 1442 timeout = msecs_to_jiffies(ms_timeout) + jiffies; 1443 while (true) { 1444 if (time_is_before_jiffies(timeout)) 1445 return FW_UPLOAD_ERR_TIMEOUT; 1446 1447 ret = i2c_master_recv(client, fw_msg_buf, 1); 1448 if (ret < 0 || *fw_msg_buf == 0) { 1449 usleep_range(1000, 2000); 1450 continue; 1451 } else { 1452 break; 1453 } 1454 } 1455 1456 /* Read remaining characters */ 1457 ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1); 1458 if (strncmp(fw_msg_buf, msg_ok, msg_size)) { 1459 dev_err(&client->dev, 1460 "Wrong FW download process answer (%*pE)\n", 1461 msg_size, fw_msg_buf); 1462 return FW_UPLOAD_ERR_HW_ERROR; 1463 } 1464 1465 return FW_UPLOAD_ERR_NONE; 1466 } 1467 1468 static int pd692x0_fw_write_line(const struct i2c_client *client, 1469 const char line[PD692X0_FW_LINE_MAX_SZ], 1470 const bool last_line) 1471 { 1472 int ret; 1473 1474 while (*line != 0) { 1475 ret = i2c_master_send(client, line, 1); 1476 if (ret < 0) 1477 return FW_UPLOAD_ERR_RW_ERROR; 1478 line++; 1479 } 1480 1481 if (last_line) { 1482 ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n", 1483 sizeof("TP\r\n") - 1); 1484 if (ret) 1485 return ret; 1486 } else { 1487 ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n", 1488 sizeof("T*\r\n") - 1); 1489 if (ret) 1490 return ret; 1491 } 1492 1493 return FW_UPLOAD_ERR_NONE; 1494 } 1495 1496 static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client) 1497 { 1498 const struct pd692x0_msg zero = {0}; 1499 struct pd692x0_msg buf = {0}; 1500 unsigned long timeout; 1501 char cmd[] = "RST"; 1502 int ret; 1503 1504 ret = i2c_master_send(client, cmd, strlen(cmd)); 1505 if (ret < 0) { 1506 dev_err(&client->dev, 1507 "Failed to reset the controller (%pe)\n", 1508 ERR_PTR(ret)); 1509 return ret; 1510 } 1511 1512 timeout = msecs_to_jiffies(10000) + jiffies; 1513 while (true) { 1514 if (time_is_before_jiffies(timeout)) 1515 return FW_UPLOAD_ERR_TIMEOUT; 1516 1517 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1518 if (ret < 0 || 1519 !memcmp(&buf, &zero, sizeof(buf))) 1520 usleep_range(1000, 2000); 1521 else 1522 break; 1523 } 1524 1525 /* Is the reply a successful report message */ 1526 if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff || 1527 buf.sub[0] & 0x01) { 1528 dev_err(&client->dev, "PSE controller error\n"); 1529 return FW_UPLOAD_ERR_HW_ERROR; 1530 } 1531 1532 /* Is the firmware operational */ 1533 if (buf.sub[0] & 0x02) { 1534 dev_err(&client->dev, 1535 "PSE firmware error. Please update it.\n"); 1536 return FW_UPLOAD_ERR_HW_ERROR; 1537 } 1538 1539 return FW_UPLOAD_ERR_NONE; 1540 } 1541 1542 static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl, 1543 const u8 *data, u32 size) 1544 { 1545 struct pd692x0_priv *priv = fwl->dd_handle; 1546 const struct i2c_client *client = priv->client; 1547 enum pd692x0_fw_state last_fw_state; 1548 int ret; 1549 1550 priv->cancel_request = false; 1551 last_fw_state = priv->fw_state; 1552 1553 priv->fw_state = PD692X0_FW_PREPARE; 1554 1555 /* Enter program mode */ 1556 if (last_fw_state == PD692X0_FW_BROKEN) { 1557 const char *msg = "ENTR"; 1558 const char *c; 1559 1560 c = msg; 1561 do { 1562 ret = i2c_master_send(client, c, 1); 1563 if (ret < 0) 1564 return FW_UPLOAD_ERR_RW_ERROR; 1565 if (*(c + 1)) 1566 usleep_range(10000, 20000); 1567 } while (*(++c)); 1568 } else { 1569 struct pd692x0_msg msg, buf; 1570 1571 msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD]; 1572 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1573 if (ret < 0) { 1574 dev_err(&client->dev, 1575 "Failed to enter programming mode (%pe)\n", 1576 ERR_PTR(ret)); 1577 return FW_UPLOAD_ERR_RW_ERROR; 1578 } 1579 } 1580 1581 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1582 if (ret) 1583 goto err_out; 1584 1585 if (priv->cancel_request) { 1586 ret = FW_UPLOAD_ERR_CANCELED; 1587 goto err_out; 1588 } 1589 1590 return FW_UPLOAD_ERR_NONE; 1591 1592 err_out: 1593 pd692x0_fw_reset(priv->client); 1594 priv->fw_state = last_fw_state; 1595 return ret; 1596 } 1597 1598 static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl, 1599 const u8 *data, u32 offset, 1600 u32 size, u32 *written) 1601 { 1602 struct pd692x0_priv *priv = fwl->dd_handle; 1603 char line[PD692X0_FW_LINE_MAX_SZ]; 1604 const struct i2c_client *client; 1605 int ret, i; 1606 char cmd; 1607 1608 client = priv->client; 1609 priv->fw_state = PD692X0_FW_WRITE; 1610 1611 /* Erase */ 1612 cmd = 'E'; 1613 ret = i2c_master_send(client, &cmd, 1); 1614 if (ret < 0) { 1615 dev_err(&client->dev, 1616 "Failed to boot programming mode (%pe)\n", 1617 ERR_PTR(ret)); 1618 return FW_UPLOAD_ERR_RW_ERROR; 1619 } 1620 1621 ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1); 1622 if (ret) 1623 return ret; 1624 1625 ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1); 1626 if (ret) 1627 dev_warn(&client->dev, 1628 "Failed to erase internal memory, however still try to write Firmware\n"); 1629 1630 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1631 if (ret) 1632 dev_warn(&client->dev, 1633 "Failed to erase internal memory, however still try to write Firmware\n"); 1634 1635 if (priv->cancel_request) 1636 return FW_UPLOAD_ERR_CANCELED; 1637 1638 /* Program */ 1639 cmd = 'P'; 1640 ret = i2c_master_send(client, &cmd, sizeof(char)); 1641 if (ret < 0) { 1642 dev_err(&client->dev, 1643 "Failed to boot programming mode (%pe)\n", 1644 ERR_PTR(ret)); 1645 return ret; 1646 } 1647 1648 ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1); 1649 if (ret) 1650 return ret; 1651 1652 i = 0; 1653 while (i < size) { 1654 ret = pd692x0_fw_get_next_line(data, line, size - i); 1655 if (ret < 0) { 1656 ret = FW_UPLOAD_ERR_FW_INVALID; 1657 goto err; 1658 } 1659 1660 i += ret; 1661 data += ret; 1662 if (line[0] == 'S' && line[1] == '0') { 1663 continue; 1664 } else if (line[0] == 'S' && line[1] == '7') { 1665 ret = pd692x0_fw_write_line(client, line, true); 1666 if (ret) 1667 goto err; 1668 } else { 1669 ret = pd692x0_fw_write_line(client, line, false); 1670 if (ret) 1671 goto err; 1672 } 1673 1674 if (priv->cancel_request) { 1675 ret = FW_UPLOAD_ERR_CANCELED; 1676 goto err; 1677 } 1678 } 1679 *written = i; 1680 1681 msleep(400); 1682 1683 return FW_UPLOAD_ERR_NONE; 1684 1685 err: 1686 strscpy_pad(line, "S7\r\n", sizeof(line)); 1687 pd692x0_fw_write_line(client, line, true); 1688 return ret; 1689 } 1690 1691 static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl) 1692 { 1693 struct pd692x0_priv *priv = fwl->dd_handle; 1694 const struct i2c_client *client = priv->client; 1695 struct pd692x0_msg_ver ver; 1696 int ret; 1697 1698 priv->fw_state = PD692X0_FW_COMPLETE; 1699 1700 ret = pd692x0_fw_reset(client); 1701 if (ret) 1702 return ret; 1703 1704 ver = pd692x0_get_sw_version(priv); 1705 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1706 dev_err(&client->dev, 1707 "Too old firmware version. Please update it\n"); 1708 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1709 return FW_UPLOAD_ERR_FW_INVALID; 1710 } 1711 1712 ret = pd692x0_hw_conf_init(priv); 1713 if (ret < 0) { 1714 dev_err(&client->dev, "Error configuring ports matrix (%pe)\n", 1715 ERR_PTR(ret)); 1716 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1717 return FW_UPLOAD_ERR_HW_ERROR; 1718 } 1719 1720 priv->fw_state = PD692X0_FW_OK; 1721 return FW_UPLOAD_ERR_NONE; 1722 } 1723 1724 static void pd692x0_fw_cancel(struct fw_upload *fwl) 1725 { 1726 struct pd692x0_priv *priv = fwl->dd_handle; 1727 1728 priv->cancel_request = true; 1729 } 1730 1731 static void pd692x0_fw_cleanup(struct fw_upload *fwl) 1732 { 1733 struct pd692x0_priv *priv = fwl->dd_handle; 1734 1735 switch (priv->fw_state) { 1736 case PD692X0_FW_WRITE: 1737 pd692x0_fw_reset(priv->client); 1738 fallthrough; 1739 case PD692X0_FW_COMPLETE: 1740 priv->fw_state = PD692X0_FW_BROKEN; 1741 break; 1742 default: 1743 break; 1744 } 1745 } 1746 1747 static const struct fw_upload_ops pd692x0_fw_ops = { 1748 .prepare = pd692x0_fw_prepare, 1749 .write = pd692x0_fw_write, 1750 .poll_complete = pd692x0_fw_poll_complete, 1751 .cancel = pd692x0_fw_cancel, 1752 .cleanup = pd692x0_fw_cleanup, 1753 }; 1754 1755 static int pd692x0_i2c_probe(struct i2c_client *client) 1756 { 1757 static const char * const regulators[] = { "vdd", "vdda" }; 1758 struct pd692x0_msg msg, buf = {0}, zero = {0}; 1759 struct device *dev = &client->dev; 1760 struct pd692x0_msg_ver ver; 1761 struct pd692x0_priv *priv; 1762 struct fw_upload *fwl; 1763 int ret; 1764 1765 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), 1766 regulators); 1767 if (ret) 1768 return dev_err_probe(dev, ret, 1769 "Failed to enable regulators\n"); 1770 1771 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1772 dev_err(dev, "i2c check functionality failed\n"); 1773 return -ENXIO; 1774 } 1775 1776 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1777 if (!priv) 1778 return -ENOMEM; 1779 1780 priv->client = client; 1781 i2c_set_clientdata(client, priv); 1782 1783 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1784 if (ret != sizeof(buf)) { 1785 dev_err(dev, "Failed to get device status\n"); 1786 return -EIO; 1787 } 1788 1789 /* Probe has been already run and the status dumped */ 1790 if (!memcmp(&buf, &zero, sizeof(buf))) { 1791 /* Ask again the controller status */ 1792 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS]; 1793 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1794 if (ret < 0) { 1795 dev_err(dev, "Failed to get device status\n"); 1796 return ret; 1797 } 1798 } 1799 1800 if (buf.key != 0x03 || buf.sub[0] & 0x01) { 1801 dev_err(dev, "PSE controller error\n"); 1802 return -EIO; 1803 } 1804 if (buf.sub[0] & 0x02) { 1805 dev_err(dev, "PSE firmware error. Please update it.\n"); 1806 priv->fw_state = PD692X0_FW_BROKEN; 1807 } else { 1808 ver = pd692x0_get_sw_version(priv); 1809 dev_info(&client->dev, "Software version %d.%02d.%d.%d\n", 1810 ver.prod, ver.maj_sw_ver, ver.min_sw_ver, 1811 ver.pa_sw_ver); 1812 1813 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1814 dev_err(dev, "Too old firmware version. Please update it\n"); 1815 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1816 } else { 1817 priv->fw_state = PD692X0_FW_OK; 1818 } 1819 } 1820 1821 if (buf.data[2] == PD692X0_USER_BYTE) 1822 priv->cfg_saved = true; 1823 1824 priv->np = dev->of_node; 1825 priv->pcdev.nr_lines = PD692X0_MAX_PIS; 1826 priv->pcdev.owner = THIS_MODULE; 1827 priv->pcdev.ops = &pd692x0_ops; 1828 priv->pcdev.dev = dev; 1829 priv->pcdev.types = ETHTOOL_PSE_C33; 1830 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC; 1831 priv->pcdev.pis_prio_max = 2; 1832 ret = devm_pse_controller_register(dev, &priv->pcdev); 1833 if (ret) 1834 return dev_err_probe(dev, ret, 1835 "failed to register PSE controller\n"); 1836 1837 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev), 1838 &pd692x0_fw_ops, priv); 1839 if (IS_ERR(fwl)) 1840 return dev_err_probe(dev, PTR_ERR(fwl), 1841 "failed to register to the Firmware Upload API\n"); 1842 priv->fwl = fwl; 1843 1844 return 0; 1845 } 1846 1847 static void pd692x0_i2c_remove(struct i2c_client *client) 1848 { 1849 struct pd692x0_priv *priv = i2c_get_clientdata(client); 1850 1851 pd692x0_managers_free_pw_budget(priv); 1852 firmware_upload_unregister(priv->fwl); 1853 } 1854 1855 static const struct i2c_device_id pd692x0_id[] = { 1856 { PD692X0_PSE_NAME }, 1857 { } 1858 }; 1859 MODULE_DEVICE_TABLE(i2c, pd692x0_id); 1860 1861 static const struct of_device_id pd692x0_of_match[] = { 1862 { .compatible = "microchip,pd69200", }, 1863 { .compatible = "microchip,pd69210", }, 1864 { .compatible = "microchip,pd69220", }, 1865 { }, 1866 }; 1867 MODULE_DEVICE_TABLE(of, pd692x0_of_match); 1868 1869 static struct i2c_driver pd692x0_driver = { 1870 .probe = pd692x0_i2c_probe, 1871 .remove = pd692x0_i2c_remove, 1872 .id_table = pd692x0_id, 1873 .driver = { 1874 .name = PD692X0_PSE_NAME, 1875 .of_match_table = pd692x0_of_match, 1876 }, 1877 }; 1878 module_i2c_driver(pd692x0_driver); 1879 1880 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1881 MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver"); 1882 MODULE_LICENSE("GPL"); 1883