1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pse-pd/pse.h> 15 #include <linux/regulator/driver.h> 16 #include <linux/regulator/machine.h> 17 18 #define PD692X0_PSE_NAME "pd692x0_pse" 19 20 #define PD692X0_MAX_PIS 48 21 #define PD692X0_MAX_MANAGERS 12 22 #define PD692X0_MAX_MANAGER_PORTS 8 23 #define PD692X0_MAX_HW_PORTS (PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS) 24 25 #define PD69200_BT_PROD_VER 24 26 #define PD69210_BT_PROD_VER 26 27 #define PD69220_BT_PROD_VER 29 28 29 #define PD692X0_FW_MAJ_VER 3 30 #define PD692X0_FW_MIN_VER 5 31 #define PD692X0_FW_PATCH_VER 5 32 33 enum pd692x0_fw_state { 34 PD692X0_FW_UNKNOWN, 35 PD692X0_FW_OK, 36 PD692X0_FW_BROKEN, 37 PD692X0_FW_NEED_UPDATE, 38 PD692X0_FW_PREPARE, 39 PD692X0_FW_WRITE, 40 PD692X0_FW_COMPLETE, 41 }; 42 43 struct pd692x0_msg { 44 u8 key; 45 u8 echo; 46 u8 sub[3]; 47 u8 data[8]; 48 __be16 chksum; 49 } __packed; 50 51 struct pd692x0_msg_ver { 52 u8 prod; 53 u8 maj_sw_ver; 54 u8 min_sw_ver; 55 u8 pa_sw_ver; 56 u8 param; 57 u8 build; 58 }; 59 60 enum { 61 PD692X0_KEY_CMD, 62 PD692X0_KEY_PRG, 63 PD692X0_KEY_REQ, 64 PD692X0_KEY_TLM, 65 PD692X0_KEY_TEST, 66 PD692X0_KEY_REPORT = 0x52 67 }; 68 69 enum { 70 PD692X0_MSG_RESET, 71 PD692X0_MSG_GET_SYS_STATUS, 72 PD692X0_MSG_GET_SW_VER, 73 PD692X0_MSG_SET_TMP_PORT_MATRIX, 74 PD692X0_MSG_PRG_PORT_MATRIX, 75 PD692X0_MSG_SET_PORT_PARAM, 76 PD692X0_MSG_GET_PORT_STATUS, 77 PD692X0_MSG_DOWNLOAD_CMD, 78 PD692X0_MSG_GET_PORT_CLASS, 79 PD692X0_MSG_GET_PORT_MEAS, 80 PD692X0_MSG_GET_PORT_PARAM, 81 PD692X0_MSG_GET_POWER_BANK, 82 PD692X0_MSG_SET_POWER_BANK, 83 84 /* add new message above here */ 85 PD692X0_MSG_CNT 86 }; 87 88 struct pd692x0_matrix { 89 u8 hw_port_a; 90 u8 hw_port_b; 91 }; 92 93 struct pd692x0_priv { 94 struct i2c_client *client; 95 struct pse_controller_dev pcdev; 96 struct device_node *np; 97 98 enum pd692x0_fw_state fw_state; 99 struct fw_upload *fwl; 100 bool cancel_request; 101 102 u8 msg_id; 103 bool last_cmd_key; 104 unsigned long last_cmd_key_time; 105 106 enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS]; 107 struct regulator_dev *manager_reg[PD692X0_MAX_MANAGERS]; 108 int manager_pw_budget[PD692X0_MAX_MANAGERS]; 109 int nmanagers; 110 struct pd692x0_matrix *port_matrix; 111 }; 112 113 /* Template list of communication messages. The non-null bytes defined here 114 * constitute the fixed portion of the messages. The remaining bytes will 115 * be configured later within the functions. Refer to the "PD692x0 BT Serial 116 * Communication Protocol User Guide" for comprehensive details on messages 117 * content. 118 */ 119 static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = { 120 [PD692X0_MSG_RESET] = { 121 .key = PD692X0_KEY_CMD, 122 .sub = {0x07, 0x55, 0x00}, 123 .data = {0x55, 0x00, 0x55, 0x4e, 124 0x4e, 0x4e, 0x4e, 0x4e}, 125 }, 126 [PD692X0_MSG_GET_SYS_STATUS] = { 127 .key = PD692X0_KEY_REQ, 128 .sub = {0x07, 0xd0, 0x4e}, 129 .data = {0x4e, 0x4e, 0x4e, 0x4e, 130 0x4e, 0x4e, 0x4e, 0x4e}, 131 }, 132 [PD692X0_MSG_GET_SW_VER] = { 133 .key = PD692X0_KEY_REQ, 134 .sub = {0x07, 0x1e, 0x21}, 135 .data = {0x4e, 0x4e, 0x4e, 0x4e, 136 0x4e, 0x4e, 0x4e, 0x4e}, 137 }, 138 [PD692X0_MSG_SET_TMP_PORT_MATRIX] = { 139 .key = PD692X0_KEY_CMD, 140 .sub = {0x05, 0x43}, 141 .data = { 0, 0x4e, 0x4e, 0x4e, 142 0x4e, 0x4e, 0x4e, 0x4e}, 143 }, 144 [PD692X0_MSG_PRG_PORT_MATRIX] = { 145 .key = PD692X0_KEY_CMD, 146 .sub = {0x07, 0x43, 0x4e}, 147 .data = {0x4e, 0x4e, 0x4e, 0x4e, 148 0x4e, 0x4e, 0x4e, 0x4e}, 149 }, 150 [PD692X0_MSG_SET_PORT_PARAM] = { 151 .key = PD692X0_KEY_CMD, 152 .sub = {0x05, 0xc0}, 153 .data = { 0xf, 0xff, 0xff, 0xff, 154 0x4e, 0x4e, 0x4e, 0x4e}, 155 }, 156 [PD692X0_MSG_GET_PORT_STATUS] = { 157 .key = PD692X0_KEY_REQ, 158 .sub = {0x05, 0xc1}, 159 .data = {0x4e, 0x4e, 0x4e, 0x4e, 160 0x4e, 0x4e, 0x4e, 0x4e}, 161 }, 162 [PD692X0_MSG_DOWNLOAD_CMD] = { 163 .key = PD692X0_KEY_PRG, 164 .sub = {0xff, 0x99, 0x15}, 165 .data = {0x16, 0x16, 0x99, 0x4e, 166 0x4e, 0x4e, 0x4e, 0x4e}, 167 }, 168 [PD692X0_MSG_GET_PORT_CLASS] = { 169 .key = PD692X0_KEY_REQ, 170 .sub = {0x05, 0xc4}, 171 .data = {0x4e, 0x4e, 0x4e, 0x4e, 172 0x4e, 0x4e, 0x4e, 0x4e}, 173 }, 174 [PD692X0_MSG_GET_PORT_MEAS] = { 175 .key = PD692X0_KEY_REQ, 176 .sub = {0x05, 0xc5}, 177 .data = {0x4e, 0x4e, 0x4e, 0x4e, 178 0x4e, 0x4e, 0x4e, 0x4e}, 179 }, 180 [PD692X0_MSG_GET_PORT_PARAM] = { 181 .key = PD692X0_KEY_REQ, 182 .sub = {0x05, 0xc0}, 183 .data = {0x4e, 0x4e, 0x4e, 0x4e, 184 0x4e, 0x4e, 0x4e, 0x4e}, 185 }, 186 [PD692X0_MSG_GET_POWER_BANK] = { 187 .key = PD692X0_KEY_REQ, 188 .sub = {0x07, 0x0b, 0x57}, 189 .data = { 0, 0x4e, 0x4e, 0x4e, 190 0x4e, 0x4e, 0x4e, 0x4e}, 191 }, 192 [PD692X0_MSG_SET_POWER_BANK] = { 193 .key = PD692X0_KEY_CMD, 194 .sub = {0x07, 0x0b, 0x57}, 195 }, 196 }; 197 198 static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo) 199 { 200 u8 *data = (u8 *)msg; 201 u16 chksum = 0; 202 int i; 203 204 msg->echo = echo++; 205 if (echo == 0xff) 206 echo = 0; 207 208 for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++) 209 chksum += data[i]; 210 211 msg->chksum = cpu_to_be16(chksum); 212 213 return echo; 214 } 215 216 static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg) 217 { 218 const struct i2c_client *client = priv->client; 219 int ret; 220 221 if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) { 222 int cmd_msleep; 223 224 cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time); 225 if (cmd_msleep > 0) 226 msleep(cmd_msleep); 227 } 228 229 /* Add echo and checksum bytes to the message */ 230 priv->msg_id = pd692x0_build_msg(msg, priv->msg_id); 231 232 ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg)); 233 if (ret != sizeof(*msg)) 234 return -EIO; 235 236 return 0; 237 } 238 239 static int pd692x0_reset(struct pd692x0_priv *priv) 240 { 241 const struct i2c_client *client = priv->client; 242 struct pd692x0_msg msg, buf = {0}; 243 int ret; 244 245 msg = pd692x0_msg_template_list[PD692X0_MSG_RESET]; 246 ret = pd692x0_send_msg(priv, &msg); 247 if (ret) { 248 dev_err(&client->dev, 249 "Failed to reset the controller (%pe)\n", ERR_PTR(ret)); 250 return ret; 251 } 252 253 msleep(30); 254 255 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 256 if (ret != sizeof(buf)) 257 return ret < 0 ? ret : -EIO; 258 259 /* Is the reply a successful report message */ 260 if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1]) 261 return -EIO; 262 263 msleep(300); 264 265 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 266 if (ret != sizeof(buf)) 267 return ret < 0 ? ret : -EIO; 268 269 /* Is the boot status without error */ 270 if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) { 271 dev_err(&client->dev, "PSE controller error\n"); 272 return -EIO; 273 } 274 275 return 0; 276 } 277 278 static bool pd692x0_try_recv_msg(const struct i2c_client *client, 279 struct pd692x0_msg *msg, 280 struct pd692x0_msg *buf) 281 { 282 /* Wait 30ms before readback as mandated by the protocol */ 283 msleep(30); 284 285 memset(buf, 0, sizeof(*buf)); 286 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 287 if (buf->key) 288 return 0; 289 290 msleep(100); 291 292 memset(buf, 0, sizeof(*buf)); 293 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 294 if (buf->key) 295 return 0; 296 297 return 1; 298 } 299 300 /* Implementation of I2C communication, specifically addressing scenarios 301 * involving communication loss. Refer to the "Synchronization During 302 * Communication Loss" section in the Communication Protocol document for 303 * further details. 304 */ 305 static int pd692x0_recv_msg(struct pd692x0_priv *priv, 306 struct pd692x0_msg *msg, 307 struct pd692x0_msg *buf) 308 { 309 const struct i2c_client *client = priv->client; 310 int ret; 311 312 ret = pd692x0_try_recv_msg(client, msg, buf); 313 if (!ret) 314 goto out_success; 315 316 dev_warn(&client->dev, 317 "Communication lost, rtnl is locked until communication is back!"); 318 319 ret = pd692x0_send_msg(priv, msg); 320 if (ret) 321 return ret; 322 323 ret = pd692x0_try_recv_msg(client, msg, buf); 324 if (!ret) 325 goto out_success2; 326 327 msleep(10000); 328 329 ret = pd692x0_send_msg(priv, msg); 330 if (ret) 331 return ret; 332 333 ret = pd692x0_try_recv_msg(client, msg, buf); 334 if (!ret) 335 goto out_success2; 336 337 return pd692x0_reset(priv); 338 339 out_success2: 340 dev_warn(&client->dev, "Communication is back, rtnl is unlocked!"); 341 out_success: 342 if (msg->key == PD692X0_KEY_CMD) { 343 priv->last_cmd_key = true; 344 priv->last_cmd_key_time = jiffies; 345 } else { 346 priv->last_cmd_key = false; 347 } 348 349 return 0; 350 } 351 352 static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv, 353 struct pd692x0_msg *msg, 354 struct pd692x0_msg *buf) 355 { 356 struct device *dev = &priv->client->dev; 357 int ret; 358 359 ret = pd692x0_send_msg(priv, msg); 360 if (ret) 361 return ret; 362 363 ret = pd692x0_recv_msg(priv, msg, buf); 364 if (ret) 365 return ret; 366 367 if (msg->echo != buf->echo) { 368 dev_err(dev, 369 "Wrong match in message ID, expect %d received %d.\n", 370 msg->echo, buf->echo); 371 return -EIO; 372 } 373 374 /* If the reply is a report message is it successful */ 375 if (buf->key == PD692X0_KEY_REPORT && 376 (buf->sub[0] || buf->sub[1])) { 377 return -EIO; 378 } 379 380 return 0; 381 } 382 383 static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev) 384 { 385 return container_of(pcdev, struct pd692x0_priv, pcdev); 386 } 387 388 static int pd692x0_fw_unavailable(struct pd692x0_priv *priv) 389 { 390 switch (priv->fw_state) { 391 case PD692X0_FW_OK: 392 return 0; 393 case PD692X0_FW_PREPARE: 394 case PD692X0_FW_WRITE: 395 case PD692X0_FW_COMPLETE: 396 dev_err(&priv->client->dev, "Firmware update in progress!\n"); 397 return -EBUSY; 398 case PD692X0_FW_BROKEN: 399 case PD692X0_FW_NEED_UPDATE: 400 default: 401 dev_err(&priv->client->dev, 402 "Firmware issue. Please update it!\n"); 403 return -EOPNOTSUPP; 404 } 405 } 406 407 static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id) 408 { 409 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 410 struct pd692x0_msg msg, buf = {0}; 411 int ret; 412 413 ret = pd692x0_fw_unavailable(priv); 414 if (ret) 415 return ret; 416 417 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 418 return 0; 419 420 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 421 msg.data[0] = 0x1; 422 msg.sub[2] = id; 423 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 424 if (ret < 0) 425 return ret; 426 427 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 428 429 return 0; 430 } 431 432 static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id) 433 { 434 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 435 struct pd692x0_msg msg, buf = {0}; 436 int ret; 437 438 ret = pd692x0_fw_unavailable(priv); 439 if (ret) 440 return ret; 441 442 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED) 443 return 0; 444 445 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 446 msg.data[0] = 0x0; 447 msg.sub[2] = id; 448 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 449 if (ret < 0) 450 return ret; 451 452 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 453 454 return 0; 455 } 456 457 struct pd692x0_pse_ext_state_mapping { 458 u32 status_code; 459 enum ethtool_c33_pse_ext_state pse_ext_state; 460 u32 pse_ext_substate; 461 }; 462 463 static const struct pd692x0_pse_ext_state_mapping 464 pd692x0_pse_ext_state_map[] = { 465 {0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 466 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE}, 467 {0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 468 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE}, 469 {0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE, 470 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE}, 471 {0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 472 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT}, 473 {0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 474 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT}, 475 {0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 476 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 477 {0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 478 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS}, 479 {0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 480 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 481 {0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 482 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD}, 483 {0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED, 484 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD}, 485 {0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 486 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED}, 487 {0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 488 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 489 {0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 490 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE}, 491 {0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 492 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION}, 493 {0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 494 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 495 {0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED, 496 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION}, 497 {0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 498 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 499 {0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 500 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 501 {0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 502 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 503 {0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 504 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET}, 505 {0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 506 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT}, 507 {0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 508 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT}, 509 {0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 510 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 511 {0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 512 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR}, 513 {0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 514 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN}, 515 { /* sentinel */ } 516 }; 517 518 static int 519 pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id, 520 struct pse_ext_state_info *ext_state_info) 521 { 522 struct ethtool_c33_pse_ext_state_info *c33_ext_state_info; 523 const struct pd692x0_pse_ext_state_mapping *ext_state_map; 524 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 525 struct pd692x0_msg msg, buf = {0}; 526 int ret; 527 528 ret = pd692x0_fw_unavailable(priv); 529 if (ret) 530 return ret; 531 532 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 533 msg.sub[2] = id; 534 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 535 if (ret < 0) 536 return ret; 537 538 c33_ext_state_info = &ext_state_info->c33_ext_state_info; 539 ext_state_map = pd692x0_pse_ext_state_map; 540 while (ext_state_map->status_code) { 541 if (ext_state_map->status_code == buf.sub[0]) { 542 c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state; 543 c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate; 544 return 0; 545 } 546 ext_state_map++; 547 } 548 549 return 0; 550 } 551 552 struct pd692x0_class_pw { 553 int class; 554 int class_cfg_value; 555 int class_pw; 556 int max_added_class_pw; 557 }; 558 559 #define PD692X0_CLASS_PW_TABLE_SIZE 4 560 /* 4/2 pairs class configuration power table in compliance mode. 561 * Need to be arranged in ascending order of power support. 562 */ 563 static const struct pd692x0_class_pw 564 pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = { 565 {.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100}, 566 {.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000}, 567 {.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000}, 568 {.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500}, 569 }; 570 571 static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw) 572 { 573 const struct pd692x0_class_pw *pw_table; 574 int i; 575 576 pw_table = pd692x0_class_pw_table; 577 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 578 if (pw_table->class_cfg_value == op_mode) 579 return pw_table->class_pw + added_pw * 100; 580 } 581 582 return -ERANGE; 583 } 584 585 static int pd692x0_pi_set_pw_from_table(struct device *dev, 586 struct pd692x0_msg *msg, int pw) 587 { 588 const struct pd692x0_class_pw *pw_table; 589 int i; 590 591 pw_table = pd692x0_class_pw_table; 592 if (pw < pw_table->class_pw) { 593 dev_err(dev, 594 "Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n", 595 pw, 596 pw_table->class_pw, 597 pw_table->class_pw + pw_table->max_added_class_pw); 598 return -ERANGE; 599 } 600 601 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 602 if (pw > (pw_table->class_pw + pw_table->max_added_class_pw)) 603 continue; 604 605 if (pw < pw_table->class_pw) { 606 dev_err(dev, 607 "Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n", 608 pw, 609 (pw_table - 1)->class_pw, 610 (pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw, 611 pw_table->class_pw, 612 pw_table->class_pw + pw_table->max_added_class_pw); 613 return -ERANGE; 614 } 615 616 msg->data[2] = pw_table->class_cfg_value; 617 msg->data[3] = (pw - pw_table->class_pw) / 100; 618 return 0; 619 } 620 621 pw_table--; 622 dev_warn(dev, 623 "Power limit %dmW not supported. Set to highest power limit %dmW\n", 624 pw, pw_table->class_pw + pw_table->max_added_class_pw); 625 msg->data[2] = pw_table->class_cfg_value; 626 msg->data[3] = pw_table->max_added_class_pw / 100; 627 return 0; 628 } 629 630 static int 631 pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 632 struct pse_pw_limit_ranges *pw_limit_ranges) 633 { 634 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 635 const struct pd692x0_class_pw *pw_table; 636 int i; 637 638 pw_table = pd692x0_class_pw_table; 639 c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE, 640 sizeof(*c33_pw_limit_ranges), 641 GFP_KERNEL); 642 if (!c33_pw_limit_ranges) 643 return -ENOMEM; 644 645 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 646 c33_pw_limit_ranges[i].min = pw_table->class_pw; 647 c33_pw_limit_ranges[i].max = pw_table->class_pw + 648 pw_table->max_added_class_pw; 649 } 650 651 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 652 return i; 653 } 654 655 static int 656 pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 657 struct pse_admin_state *admin_state) 658 { 659 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 660 struct pd692x0_msg msg, buf = {0}; 661 int ret; 662 663 ret = pd692x0_fw_unavailable(priv); 664 if (ret) 665 return ret; 666 667 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 668 msg.sub[2] = id; 669 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 670 if (ret < 0) 671 return ret; 672 673 if (buf.sub[1]) 674 admin_state->c33_admin_state = 675 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 676 else 677 admin_state->c33_admin_state = 678 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 679 680 priv->admin_state[id] = admin_state->c33_admin_state; 681 682 return 0; 683 } 684 685 static int 686 pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 687 struct pse_pw_status *pw_status) 688 { 689 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 690 struct pd692x0_msg msg, buf = {0}; 691 int ret; 692 693 ret = pd692x0_fw_unavailable(priv); 694 if (ret) 695 return ret; 696 697 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 698 msg.sub[2] = id; 699 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 700 if (ret < 0) 701 return ret; 702 703 /* Compare Port Status (Communication Protocol Document par. 7.1) */ 704 if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90) 705 pw_status->c33_pw_status = 706 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 707 else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22) 708 pw_status->c33_pw_status = 709 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING; 710 else if (buf.sub[0] == 0x12) 711 pw_status->c33_pw_status = 712 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT; 713 else 714 pw_status->c33_pw_status = 715 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 716 717 return 0; 718 } 719 720 static int 721 pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id) 722 { 723 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 724 struct pd692x0_msg msg, buf = {0}; 725 u32 class; 726 int ret; 727 728 ret = pd692x0_fw_unavailable(priv); 729 if (ret) 730 return ret; 731 732 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS]; 733 msg.sub[2] = id; 734 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 735 if (ret < 0) 736 return ret; 737 738 class = buf.data[3] >> 4; 739 if (class <= 8) 740 return class; 741 742 return 0; 743 } 744 745 static int 746 pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 747 { 748 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 749 struct pd692x0_msg msg, buf = {0}; 750 int ret; 751 752 ret = pd692x0_fw_unavailable(priv); 753 if (ret) 754 return ret; 755 756 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 757 msg.sub[2] = id; 758 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 759 if (ret < 0) 760 return ret; 761 762 return (buf.data[0] << 4 | buf.data[1]) * 100; 763 } 764 765 static int 766 pd692x0_pi_get_prio(struct pse_controller_dev *pcdev, int id) 767 { 768 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 769 struct pd692x0_msg msg, buf = {0}; 770 int ret; 771 772 ret = pd692x0_fw_unavailable(priv); 773 if (ret) 774 return ret; 775 776 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 777 msg.sub[2] = id; 778 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 779 if (ret < 0) 780 return ret; 781 if (!buf.data[2] || buf.data[2] > pcdev->pis_prio_max + 1) 782 return -ERANGE; 783 784 /* PSE core priority start at 0 */ 785 return buf.data[2] - 1; 786 } 787 788 static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv) 789 { 790 struct device *dev = &priv->client->dev; 791 struct pd692x0_msg msg, buf = {0}; 792 struct pd692x0_msg_ver ver = {0}; 793 int ret; 794 795 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER]; 796 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 797 if (ret < 0) { 798 dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret)); 799 return ver; 800 } 801 802 /* Extract version from the message */ 803 ver.prod = buf.sub[2]; 804 ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100; 805 ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10; 806 ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10; 807 ver.param = buf.data[2]; 808 ver.build = buf.data[3]; 809 810 return ver; 811 } 812 813 struct pd692x0_manager { 814 struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS]; 815 struct device_node *node; 816 int nports; 817 }; 818 819 static int 820 pd692x0_of_get_ports_manager(struct pd692x0_priv *priv, 821 struct pd692x0_manager *manager, 822 struct device_node *np) 823 { 824 struct device_node *node; 825 int ret, nports, i; 826 827 nports = 0; 828 for_each_child_of_node(np, node) { 829 u32 port; 830 831 if (!of_node_name_eq(node, "port")) 832 continue; 833 834 ret = of_property_read_u32(node, "reg", &port); 835 if (ret) 836 goto out; 837 838 if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) { 839 dev_err(&priv->client->dev, 840 "wrong number or order of manager ports (%d)\n", 841 port); 842 ret = -EINVAL; 843 goto out; 844 } 845 846 of_node_get(node); 847 manager->port_node[port] = node; 848 nports++; 849 } 850 851 manager->nports = nports; 852 return 0; 853 854 out: 855 for (i = 0; i < nports; i++) { 856 of_node_put(manager->port_node[i]); 857 manager->port_node[i] = NULL; 858 } 859 of_node_put(node); 860 return ret; 861 } 862 863 static int 864 pd692x0_of_get_managers(struct pd692x0_priv *priv, 865 struct pd692x0_manager *manager) 866 { 867 struct device_node *managers_node, *node; 868 int ret, nmanagers, i, j; 869 870 if (!priv->np) 871 return -EINVAL; 872 873 nmanagers = 0; 874 managers_node = of_get_child_by_name(priv->np, "managers"); 875 if (!managers_node) 876 return -EINVAL; 877 878 for_each_child_of_node(managers_node, node) { 879 u32 manager_id; 880 881 if (!of_node_name_eq(node, "manager")) 882 continue; 883 884 ret = of_property_read_u32(node, "reg", &manager_id); 885 if (ret) 886 goto out; 887 888 if (manager_id >= PD692X0_MAX_MANAGERS || 889 manager_id != nmanagers) { 890 dev_err(&priv->client->dev, 891 "wrong number or order of managers (%d)\n", 892 manager_id); 893 ret = -EINVAL; 894 goto out; 895 } 896 897 ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id], 898 node); 899 if (ret) 900 goto out; 901 902 of_node_get(node); 903 manager[manager_id].node = node; 904 nmanagers++; 905 } 906 907 of_node_put(managers_node); 908 priv->nmanagers = nmanagers; 909 return 0; 910 911 out: 912 for (i = 0; i < nmanagers; i++) { 913 for (j = 0; j < manager[i].nports; j++) { 914 of_node_put(manager[i].port_node[j]); 915 manager[i].port_node[j] = NULL; 916 } 917 of_node_put(manager[i].node); 918 manager[i].node = NULL; 919 } 920 921 of_node_put(node); 922 of_node_put(managers_node); 923 return ret; 924 } 925 926 static const struct regulator_ops dummy_ops; 927 928 static struct regulator_dev * 929 pd692x0_register_manager_regulator(struct device *dev, char *reg_name, 930 struct device_node *node) 931 { 932 struct regulator_init_data *rinit_data; 933 struct regulator_config rconfig = {0}; 934 struct regulator_desc *rdesc; 935 struct regulator_dev *rdev; 936 937 rinit_data = devm_kzalloc(dev, sizeof(*rinit_data), 938 GFP_KERNEL); 939 if (!rinit_data) 940 return ERR_PTR(-ENOMEM); 941 942 rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); 943 if (!rdesc) 944 return ERR_PTR(-ENOMEM); 945 946 rdesc->name = reg_name; 947 rdesc->type = REGULATOR_VOLTAGE; 948 rdesc->ops = &dummy_ops; 949 rdesc->owner = THIS_MODULE; 950 951 rinit_data->supply_regulator = "vmain"; 952 953 rconfig.dev = dev; 954 rconfig.init_data = rinit_data; 955 rconfig.of_node = node; 956 957 rdev = devm_regulator_register(dev, rdesc, &rconfig); 958 if (IS_ERR(rdev)) { 959 dev_err_probe(dev, PTR_ERR(rdev), 960 "Failed to register regulator\n"); 961 return rdev; 962 } 963 964 return rdev; 965 } 966 967 static int 968 pd692x0_register_managers_regulator(struct pd692x0_priv *priv, 969 const struct pd692x0_manager *manager) 970 { 971 struct device *dev = &priv->client->dev; 972 size_t reg_name_len; 973 int i; 974 975 /* Each regulator name len is dev name + 12 char + 976 * int max digit number (10) + 1 977 */ 978 reg_name_len = strlen(dev_name(dev)) + 23; 979 980 for (i = 0; i < priv->nmanagers; i++) { 981 static const char * const regulators[] = { "vaux5", "vaux3p3" }; 982 struct regulator_dev *rdev; 983 char *reg_name; 984 int ret; 985 986 reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL); 987 if (!reg_name) 988 return -ENOMEM; 989 snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i); 990 rdev = pd692x0_register_manager_regulator(dev, reg_name, 991 manager[i].node); 992 if (IS_ERR(rdev)) 993 return PTR_ERR(rdev); 994 995 /* VMAIN is described as main supply for the manager. 996 * Add other VAUX power supplies and link them to the 997 * virtual device rdev->dev. 998 */ 999 ret = devm_regulator_bulk_get_enable(&rdev->dev, 1000 ARRAY_SIZE(regulators), 1001 regulators); 1002 if (ret) 1003 return dev_err_probe(&rdev->dev, ret, 1004 "Failed to enable regulators\n"); 1005 1006 priv->manager_reg[i] = rdev; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int 1013 pd692x0_conf_manager_power_budget(struct pd692x0_priv *priv, int id) 1014 { 1015 struct pd692x0_msg msg, buf; 1016 int ret, pw_mW; 1017 1018 pw_mW = priv->manager_pw_budget[id] / 1000; 1019 if (!pw_mW) 1020 return 0; 1021 1022 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_POWER_BANK]; 1023 msg.data[0] = id; 1024 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1025 if (ret < 0) 1026 return ret; 1027 1028 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_POWER_BANK]; 1029 msg.data[0] = id; 1030 msg.data[1] = pw_mW >> 8; 1031 msg.data[2] = pw_mW & 0xff; 1032 msg.data[3] = buf.sub[2]; 1033 msg.data[4] = buf.data[0]; 1034 msg.data[5] = buf.data[1]; 1035 msg.data[6] = buf.data[2]; 1036 msg.data[7] = buf.data[3]; 1037 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1038 } 1039 1040 static int 1041 pd692x0_req_managers_pw_budget(struct pd692x0_priv *priv) 1042 { 1043 int i, ret; 1044 1045 for (i = 0; i < priv->nmanagers; i++) { 1046 struct regulator *supply = priv->manager_reg[i]->supply; 1047 int pw_budget; 1048 1049 pw_budget = regulator_get_unclaimed_power_budget(supply); 1050 if (!pw_budget) 1051 /* Do nothing if no power budget */ 1052 continue; 1053 1054 /* Max power budget per manager */ 1055 if (pw_budget > 6000000) 1056 pw_budget = 6000000; 1057 ret = regulator_request_power_budget(supply, pw_budget); 1058 if (ret < 0) 1059 return ret; 1060 1061 priv->manager_pw_budget[i] = pw_budget; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static int 1068 pd692x0_configure_managers(struct pd692x0_priv *priv) 1069 { 1070 int i, ret; 1071 1072 for (i = 0; i < priv->nmanagers; i++) { 1073 ret = pd692x0_conf_manager_power_budget(priv, i); 1074 if (ret < 0) 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int 1082 pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset, 1083 const struct pd692x0_manager *manager, 1084 int nmanagers, struct pd692x0_matrix *port_matrix) 1085 { 1086 int i, j, port_cnt; 1087 bool found = false; 1088 1089 if (!pairset->np) 1090 return 0; 1091 1092 /* Look on every managers */ 1093 port_cnt = 0; 1094 for (i = 0; i < nmanagers; i++) { 1095 /* Look on every ports of the manager */ 1096 for (j = 0; j < manager[i].nports; j++) { 1097 if (pairset->np == manager[i].port_node[j]) { 1098 found = true; 1099 break; 1100 } 1101 } 1102 port_cnt += j; 1103 1104 if (found) 1105 break; 1106 } 1107 1108 if (!found) 1109 return -ENODEV; 1110 1111 if (pairset->pinout == ALTERNATIVE_A) 1112 port_matrix->hw_port_a = port_cnt; 1113 else if (pairset->pinout == ALTERNATIVE_B) 1114 port_matrix->hw_port_b = port_cnt; 1115 1116 return 0; 1117 } 1118 1119 static int 1120 pd692x0_set_ports_matrix(struct pd692x0_priv *priv, 1121 const struct pd692x0_manager *manager) 1122 { 1123 struct pd692x0_matrix *port_matrix = priv->port_matrix; 1124 struct pse_controller_dev *pcdev = &priv->pcdev; 1125 int i, ret; 1126 1127 /* Init Matrix */ 1128 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1129 port_matrix[i].hw_port_a = 0xff; 1130 port_matrix[i].hw_port_b = 0xff; 1131 } 1132 1133 /* Update with values for every PSE PIs */ 1134 for (i = 0; i < pcdev->nr_lines; i++) { 1135 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0], 1136 manager, priv->nmanagers, 1137 &port_matrix[i]); 1138 if (ret) { 1139 dev_err(&priv->client->dev, 1140 "unable to configure pi %d pairset 0", i); 1141 return ret; 1142 } 1143 1144 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1], 1145 manager, priv->nmanagers, 1146 &port_matrix[i]); 1147 if (ret) { 1148 dev_err(&priv->client->dev, 1149 "unable to configure pi %d pairset 1", i); 1150 return ret; 1151 } 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int 1158 pd692x0_write_ports_matrix(struct pd692x0_priv *priv) 1159 { 1160 struct pd692x0_matrix *port_matrix = priv->port_matrix; 1161 struct pd692x0_msg msg, buf; 1162 int ret, i; 1163 1164 /* Write temporary Matrix */ 1165 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX]; 1166 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1167 msg.sub[2] = i; 1168 msg.data[0] = port_matrix[i].hw_port_b; 1169 msg.data[1] = port_matrix[i].hw_port_a; 1170 1171 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1172 if (ret < 0) 1173 return ret; 1174 } 1175 1176 /* Program Matrix */ 1177 msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX]; 1178 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1179 if (ret < 0) 1180 return ret; 1181 1182 return 0; 1183 } 1184 1185 static int pd692x0_hw_conf_init(struct pd692x0_priv *priv) 1186 { 1187 int ret; 1188 1189 /* Is PD692x0 ready to be configured? */ 1190 if (priv->fw_state != PD692X0_FW_OK && 1191 priv->fw_state != PD692X0_FW_COMPLETE) 1192 return 0; 1193 1194 ret = pd692x0_configure_managers(priv); 1195 if (ret) 1196 return ret; 1197 1198 ret = pd692x0_write_ports_matrix(priv); 1199 if (ret) 1200 return ret; 1201 1202 return 0; 1203 } 1204 1205 static void pd692x0_of_put_managers(struct pd692x0_priv *priv, 1206 struct pd692x0_manager *manager) 1207 { 1208 int i, j; 1209 1210 for (i = 0; i < priv->nmanagers; i++) { 1211 for (j = 0; j < manager[i].nports; j++) 1212 of_node_put(manager[i].port_node[j]); 1213 of_node_put(manager[i].node); 1214 } 1215 } 1216 1217 static void pd692x0_managers_free_pw_budget(struct pd692x0_priv *priv) 1218 { 1219 int i; 1220 1221 for (i = 0; i < PD692X0_MAX_MANAGERS; i++) { 1222 struct regulator *supply; 1223 1224 if (!priv->manager_reg[i] || !priv->manager_pw_budget[i]) 1225 continue; 1226 1227 supply = priv->manager_reg[i]->supply; 1228 if (!supply) 1229 continue; 1230 1231 regulator_free_power_budget(supply, 1232 priv->manager_pw_budget[i]); 1233 } 1234 } 1235 1236 static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev) 1237 { 1238 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1239 struct pd692x0_matrix *port_matrix; 1240 struct pd692x0_manager *manager; 1241 int ret; 1242 1243 manager = kcalloc(PD692X0_MAX_MANAGERS, sizeof(*manager), GFP_KERNEL); 1244 if (!manager) 1245 return -ENOMEM; 1246 1247 port_matrix = devm_kcalloc(&priv->client->dev, PD692X0_MAX_PIS, 1248 sizeof(*port_matrix), GFP_KERNEL); 1249 if (!port_matrix) { 1250 ret = -ENOMEM; 1251 goto err_free_manager; 1252 } 1253 priv->port_matrix = port_matrix; 1254 1255 ret = pd692x0_of_get_managers(priv, manager); 1256 if (ret < 0) 1257 goto err_free_manager; 1258 1259 ret = pd692x0_register_managers_regulator(priv, manager); 1260 if (ret) 1261 goto err_of_managers; 1262 1263 ret = pd692x0_req_managers_pw_budget(priv); 1264 if (ret) 1265 goto err_of_managers; 1266 1267 ret = pd692x0_set_ports_matrix(priv, manager); 1268 if (ret) 1269 goto err_managers_req_pw; 1270 1271 ret = pd692x0_hw_conf_init(priv); 1272 if (ret) 1273 goto err_managers_req_pw; 1274 1275 pd692x0_of_put_managers(priv, manager); 1276 kfree(manager); 1277 return 0; 1278 1279 err_managers_req_pw: 1280 pd692x0_managers_free_pw_budget(priv); 1281 err_of_managers: 1282 pd692x0_of_put_managers(priv, manager); 1283 err_free_manager: 1284 kfree(manager); 1285 return ret; 1286 } 1287 1288 static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 1289 { 1290 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1291 struct pd692x0_msg msg, buf = {0}; 1292 int ret; 1293 1294 ret = pd692x0_fw_unavailable(priv); 1295 if (ret) 1296 return ret; 1297 1298 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS]; 1299 msg.sub[2] = id; 1300 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1301 if (ret < 0) 1302 return ret; 1303 1304 /* Convert 0.1V unit to uV */ 1305 return (buf.sub[0] << 8 | buf.sub[1]) * 100000; 1306 } 1307 1308 static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev, 1309 int id) 1310 { 1311 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1312 struct pd692x0_msg msg, buf = {0}; 1313 int ret; 1314 1315 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 1316 msg.sub[2] = id; 1317 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1318 if (ret < 0) 1319 return ret; 1320 1321 return pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]); 1322 } 1323 1324 static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev, 1325 int id, int max_mW) 1326 { 1327 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1328 struct device *dev = &priv->client->dev; 1329 struct pd692x0_msg msg, buf = {0}; 1330 int ret; 1331 1332 ret = pd692x0_fw_unavailable(priv); 1333 if (ret) 1334 return ret; 1335 1336 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1337 msg.sub[2] = id; 1338 ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW); 1339 if (ret) 1340 return ret; 1341 1342 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1343 } 1344 1345 static int pd692x0_pi_set_prio(struct pse_controller_dev *pcdev, int id, 1346 unsigned int prio) 1347 { 1348 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1349 struct pd692x0_msg msg, buf = {0}; 1350 int ret; 1351 1352 ret = pd692x0_fw_unavailable(priv); 1353 if (ret) 1354 return ret; 1355 1356 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1357 msg.sub[2] = id; 1358 /* Controller priority from 1 to 3 */ 1359 msg.data[4] = prio + 1; 1360 1361 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1362 } 1363 1364 static const struct pse_controller_ops pd692x0_ops = { 1365 .setup_pi_matrix = pd692x0_setup_pi_matrix, 1366 .pi_get_admin_state = pd692x0_pi_get_admin_state, 1367 .pi_get_pw_status = pd692x0_pi_get_pw_status, 1368 .pi_get_ext_state = pd692x0_pi_get_ext_state, 1369 .pi_get_pw_class = pd692x0_pi_get_pw_class, 1370 .pi_get_actual_pw = pd692x0_pi_get_actual_pw, 1371 .pi_enable = pd692x0_pi_enable, 1372 .pi_disable = pd692x0_pi_disable, 1373 .pi_get_voltage = pd692x0_pi_get_voltage, 1374 .pi_get_pw_limit = pd692x0_pi_get_pw_limit, 1375 .pi_set_pw_limit = pd692x0_pi_set_pw_limit, 1376 .pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges, 1377 .pi_get_prio = pd692x0_pi_get_prio, 1378 .pi_set_prio = pd692x0_pi_set_prio, 1379 }; 1380 1381 #define PD692X0_FW_LINE_MAX_SZ 0xff 1382 static int pd692x0_fw_get_next_line(const u8 *data, 1383 char *line, size_t size) 1384 { 1385 size_t line_size; 1386 int i; 1387 1388 line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ); 1389 1390 memset(line, 0, PD692X0_FW_LINE_MAX_SZ); 1391 for (i = 0; i < line_size - 1; i++) { 1392 if (*data == '\r' && *(data + 1) == '\n') { 1393 line[i] = '\r'; 1394 line[i + 1] = '\n'; 1395 return i + 2; 1396 } 1397 line[i] = *data; 1398 data++; 1399 } 1400 1401 return -EIO; 1402 } 1403 1404 static enum fw_upload_err 1405 pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout, 1406 const char *msg_ok, unsigned int msg_size) 1407 { 1408 /* Maximum controller response size */ 1409 char fw_msg_buf[5] = {0}; 1410 unsigned long timeout; 1411 int ret; 1412 1413 if (msg_size > sizeof(fw_msg_buf)) 1414 return FW_UPLOAD_ERR_RW_ERROR; 1415 1416 /* Read until we get something */ 1417 timeout = msecs_to_jiffies(ms_timeout) + jiffies; 1418 while (true) { 1419 if (time_is_before_jiffies(timeout)) 1420 return FW_UPLOAD_ERR_TIMEOUT; 1421 1422 ret = i2c_master_recv(client, fw_msg_buf, 1); 1423 if (ret < 0 || *fw_msg_buf == 0) { 1424 usleep_range(1000, 2000); 1425 continue; 1426 } else { 1427 break; 1428 } 1429 } 1430 1431 /* Read remaining characters */ 1432 ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1); 1433 if (strncmp(fw_msg_buf, msg_ok, msg_size)) { 1434 dev_err(&client->dev, 1435 "Wrong FW download process answer (%*pE)\n", 1436 msg_size, fw_msg_buf); 1437 return FW_UPLOAD_ERR_HW_ERROR; 1438 } 1439 1440 return FW_UPLOAD_ERR_NONE; 1441 } 1442 1443 static int pd692x0_fw_write_line(const struct i2c_client *client, 1444 const char line[PD692X0_FW_LINE_MAX_SZ], 1445 const bool last_line) 1446 { 1447 int ret; 1448 1449 while (*line != 0) { 1450 ret = i2c_master_send(client, line, 1); 1451 if (ret < 0) 1452 return FW_UPLOAD_ERR_RW_ERROR; 1453 line++; 1454 } 1455 1456 if (last_line) { 1457 ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n", 1458 sizeof("TP\r\n") - 1); 1459 if (ret) 1460 return ret; 1461 } else { 1462 ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n", 1463 sizeof("T*\r\n") - 1); 1464 if (ret) 1465 return ret; 1466 } 1467 1468 return FW_UPLOAD_ERR_NONE; 1469 } 1470 1471 static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client) 1472 { 1473 const struct pd692x0_msg zero = {0}; 1474 struct pd692x0_msg buf = {0}; 1475 unsigned long timeout; 1476 char cmd[] = "RST"; 1477 int ret; 1478 1479 ret = i2c_master_send(client, cmd, strlen(cmd)); 1480 if (ret < 0) { 1481 dev_err(&client->dev, 1482 "Failed to reset the controller (%pe)\n", 1483 ERR_PTR(ret)); 1484 return ret; 1485 } 1486 1487 timeout = msecs_to_jiffies(10000) + jiffies; 1488 while (true) { 1489 if (time_is_before_jiffies(timeout)) 1490 return FW_UPLOAD_ERR_TIMEOUT; 1491 1492 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1493 if (ret < 0 || 1494 !memcmp(&buf, &zero, sizeof(buf))) 1495 usleep_range(1000, 2000); 1496 else 1497 break; 1498 } 1499 1500 /* Is the reply a successful report message */ 1501 if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff || 1502 buf.sub[0] & 0x01) { 1503 dev_err(&client->dev, "PSE controller error\n"); 1504 return FW_UPLOAD_ERR_HW_ERROR; 1505 } 1506 1507 /* Is the firmware operational */ 1508 if (buf.sub[0] & 0x02) { 1509 dev_err(&client->dev, 1510 "PSE firmware error. Please update it.\n"); 1511 return FW_UPLOAD_ERR_HW_ERROR; 1512 } 1513 1514 return FW_UPLOAD_ERR_NONE; 1515 } 1516 1517 static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl, 1518 const u8 *data, u32 size) 1519 { 1520 struct pd692x0_priv *priv = fwl->dd_handle; 1521 const struct i2c_client *client = priv->client; 1522 enum pd692x0_fw_state last_fw_state; 1523 int ret; 1524 1525 priv->cancel_request = false; 1526 last_fw_state = priv->fw_state; 1527 1528 priv->fw_state = PD692X0_FW_PREPARE; 1529 1530 /* Enter program mode */ 1531 if (last_fw_state == PD692X0_FW_BROKEN) { 1532 const char *msg = "ENTR"; 1533 const char *c; 1534 1535 c = msg; 1536 do { 1537 ret = i2c_master_send(client, c, 1); 1538 if (ret < 0) 1539 return FW_UPLOAD_ERR_RW_ERROR; 1540 if (*(c + 1)) 1541 usleep_range(10000, 20000); 1542 } while (*(++c)); 1543 } else { 1544 struct pd692x0_msg msg, buf; 1545 1546 msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD]; 1547 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1548 if (ret < 0) { 1549 dev_err(&client->dev, 1550 "Failed to enter programming mode (%pe)\n", 1551 ERR_PTR(ret)); 1552 return FW_UPLOAD_ERR_RW_ERROR; 1553 } 1554 } 1555 1556 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1557 if (ret) 1558 goto err_out; 1559 1560 if (priv->cancel_request) { 1561 ret = FW_UPLOAD_ERR_CANCELED; 1562 goto err_out; 1563 } 1564 1565 return FW_UPLOAD_ERR_NONE; 1566 1567 err_out: 1568 pd692x0_fw_reset(priv->client); 1569 priv->fw_state = last_fw_state; 1570 return ret; 1571 } 1572 1573 static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl, 1574 const u8 *data, u32 offset, 1575 u32 size, u32 *written) 1576 { 1577 struct pd692x0_priv *priv = fwl->dd_handle; 1578 char line[PD692X0_FW_LINE_MAX_SZ]; 1579 const struct i2c_client *client; 1580 int ret, i; 1581 char cmd; 1582 1583 client = priv->client; 1584 priv->fw_state = PD692X0_FW_WRITE; 1585 1586 /* Erase */ 1587 cmd = 'E'; 1588 ret = i2c_master_send(client, &cmd, 1); 1589 if (ret < 0) { 1590 dev_err(&client->dev, 1591 "Failed to boot programming mode (%pe)\n", 1592 ERR_PTR(ret)); 1593 return FW_UPLOAD_ERR_RW_ERROR; 1594 } 1595 1596 ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1); 1597 if (ret) 1598 return ret; 1599 1600 ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1); 1601 if (ret) 1602 dev_warn(&client->dev, 1603 "Failed to erase internal memory, however still try to write Firmware\n"); 1604 1605 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1606 if (ret) 1607 dev_warn(&client->dev, 1608 "Failed to erase internal memory, however still try to write Firmware\n"); 1609 1610 if (priv->cancel_request) 1611 return FW_UPLOAD_ERR_CANCELED; 1612 1613 /* Program */ 1614 cmd = 'P'; 1615 ret = i2c_master_send(client, &cmd, sizeof(char)); 1616 if (ret < 0) { 1617 dev_err(&client->dev, 1618 "Failed to boot programming mode (%pe)\n", 1619 ERR_PTR(ret)); 1620 return ret; 1621 } 1622 1623 ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1); 1624 if (ret) 1625 return ret; 1626 1627 i = 0; 1628 while (i < size) { 1629 ret = pd692x0_fw_get_next_line(data, line, size - i); 1630 if (ret < 0) { 1631 ret = FW_UPLOAD_ERR_FW_INVALID; 1632 goto err; 1633 } 1634 1635 i += ret; 1636 data += ret; 1637 if (line[0] == 'S' && line[1] == '0') { 1638 continue; 1639 } else if (line[0] == 'S' && line[1] == '7') { 1640 ret = pd692x0_fw_write_line(client, line, true); 1641 if (ret) 1642 goto err; 1643 } else { 1644 ret = pd692x0_fw_write_line(client, line, false); 1645 if (ret) 1646 goto err; 1647 } 1648 1649 if (priv->cancel_request) { 1650 ret = FW_UPLOAD_ERR_CANCELED; 1651 goto err; 1652 } 1653 } 1654 *written = i; 1655 1656 msleep(400); 1657 1658 return FW_UPLOAD_ERR_NONE; 1659 1660 err: 1661 strscpy_pad(line, "S7\r\n", sizeof(line)); 1662 pd692x0_fw_write_line(client, line, true); 1663 return ret; 1664 } 1665 1666 static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl) 1667 { 1668 struct pd692x0_priv *priv = fwl->dd_handle; 1669 const struct i2c_client *client = priv->client; 1670 struct pd692x0_msg_ver ver; 1671 int ret; 1672 1673 priv->fw_state = PD692X0_FW_COMPLETE; 1674 1675 ret = pd692x0_fw_reset(client); 1676 if (ret) 1677 return ret; 1678 1679 ver = pd692x0_get_sw_version(priv); 1680 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1681 dev_err(&client->dev, 1682 "Too old firmware version. Please update it\n"); 1683 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1684 return FW_UPLOAD_ERR_FW_INVALID; 1685 } 1686 1687 ret = pd692x0_hw_conf_init(priv); 1688 if (ret < 0) { 1689 dev_err(&client->dev, "Error configuring ports matrix (%pe)\n", 1690 ERR_PTR(ret)); 1691 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1692 return FW_UPLOAD_ERR_HW_ERROR; 1693 } 1694 1695 priv->fw_state = PD692X0_FW_OK; 1696 return FW_UPLOAD_ERR_NONE; 1697 } 1698 1699 static void pd692x0_fw_cancel(struct fw_upload *fwl) 1700 { 1701 struct pd692x0_priv *priv = fwl->dd_handle; 1702 1703 priv->cancel_request = true; 1704 } 1705 1706 static void pd692x0_fw_cleanup(struct fw_upload *fwl) 1707 { 1708 struct pd692x0_priv *priv = fwl->dd_handle; 1709 1710 switch (priv->fw_state) { 1711 case PD692X0_FW_WRITE: 1712 pd692x0_fw_reset(priv->client); 1713 fallthrough; 1714 case PD692X0_FW_COMPLETE: 1715 priv->fw_state = PD692X0_FW_BROKEN; 1716 break; 1717 default: 1718 break; 1719 } 1720 } 1721 1722 static const struct fw_upload_ops pd692x0_fw_ops = { 1723 .prepare = pd692x0_fw_prepare, 1724 .write = pd692x0_fw_write, 1725 .poll_complete = pd692x0_fw_poll_complete, 1726 .cancel = pd692x0_fw_cancel, 1727 .cleanup = pd692x0_fw_cleanup, 1728 }; 1729 1730 static int pd692x0_i2c_probe(struct i2c_client *client) 1731 { 1732 static const char * const regulators[] = { "vdd", "vdda" }; 1733 struct pd692x0_msg msg, buf = {0}, zero = {0}; 1734 struct device *dev = &client->dev; 1735 struct pd692x0_msg_ver ver; 1736 struct pd692x0_priv *priv; 1737 struct fw_upload *fwl; 1738 int ret; 1739 1740 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), 1741 regulators); 1742 if (ret) 1743 return dev_err_probe(dev, ret, 1744 "Failed to enable regulators\n"); 1745 1746 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1747 dev_err(dev, "i2c check functionality failed\n"); 1748 return -ENXIO; 1749 } 1750 1751 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1752 if (!priv) 1753 return -ENOMEM; 1754 1755 priv->client = client; 1756 i2c_set_clientdata(client, priv); 1757 1758 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1759 if (ret != sizeof(buf)) { 1760 dev_err(dev, "Failed to get device status\n"); 1761 return -EIO; 1762 } 1763 1764 /* Probe has been already run and the status dumped */ 1765 if (!memcmp(&buf, &zero, sizeof(buf))) { 1766 /* Ask again the controller status */ 1767 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS]; 1768 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1769 if (ret < 0) { 1770 dev_err(dev, "Failed to get device status\n"); 1771 return ret; 1772 } 1773 } 1774 1775 if (buf.key != 0x03 || buf.sub[0] & 0x01) { 1776 dev_err(dev, "PSE controller error\n"); 1777 return -EIO; 1778 } 1779 if (buf.sub[0] & 0x02) { 1780 dev_err(dev, "PSE firmware error. Please update it.\n"); 1781 priv->fw_state = PD692X0_FW_BROKEN; 1782 } else { 1783 ver = pd692x0_get_sw_version(priv); 1784 dev_info(&client->dev, "Software version %d.%02d.%d.%d\n", 1785 ver.prod, ver.maj_sw_ver, ver.min_sw_ver, 1786 ver.pa_sw_ver); 1787 1788 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1789 dev_err(dev, "Too old firmware version. Please update it\n"); 1790 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1791 } else { 1792 priv->fw_state = PD692X0_FW_OK; 1793 } 1794 } 1795 1796 priv->np = dev->of_node; 1797 priv->pcdev.nr_lines = PD692X0_MAX_PIS; 1798 priv->pcdev.owner = THIS_MODULE; 1799 priv->pcdev.ops = &pd692x0_ops; 1800 priv->pcdev.dev = dev; 1801 priv->pcdev.types = ETHTOOL_PSE_C33; 1802 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC; 1803 priv->pcdev.pis_prio_max = 2; 1804 ret = devm_pse_controller_register(dev, &priv->pcdev); 1805 if (ret) 1806 return dev_err_probe(dev, ret, 1807 "failed to register PSE controller\n"); 1808 1809 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev), 1810 &pd692x0_fw_ops, priv); 1811 if (IS_ERR(fwl)) 1812 return dev_err_probe(dev, PTR_ERR(fwl), 1813 "failed to register to the Firmware Upload API\n"); 1814 priv->fwl = fwl; 1815 1816 return 0; 1817 } 1818 1819 static void pd692x0_i2c_remove(struct i2c_client *client) 1820 { 1821 struct pd692x0_priv *priv = i2c_get_clientdata(client); 1822 1823 pd692x0_managers_free_pw_budget(priv); 1824 firmware_upload_unregister(priv->fwl); 1825 } 1826 1827 static const struct i2c_device_id pd692x0_id[] = { 1828 { PD692X0_PSE_NAME }, 1829 { } 1830 }; 1831 MODULE_DEVICE_TABLE(i2c, pd692x0_id); 1832 1833 static const struct of_device_id pd692x0_of_match[] = { 1834 { .compatible = "microchip,pd69200", }, 1835 { .compatible = "microchip,pd69210", }, 1836 { .compatible = "microchip,pd69220", }, 1837 { }, 1838 }; 1839 MODULE_DEVICE_TABLE(of, pd692x0_of_match); 1840 1841 static struct i2c_driver pd692x0_driver = { 1842 .probe = pd692x0_i2c_probe, 1843 .remove = pd692x0_i2c_remove, 1844 .id_table = pd692x0_id, 1845 .driver = { 1846 .name = PD692X0_PSE_NAME, 1847 .of_match_table = pd692x0_of_match, 1848 }, 1849 }; 1850 module_i2c_driver(pd692x0_driver); 1851 1852 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1853 MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver"); 1854 MODULE_LICENSE("GPL"); 1855