1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus) 4 * 5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/firmware.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pse-pd/pse.h> 15 #include <linux/regulator/driver.h> 16 #include <linux/regulator/machine.h> 17 18 #define PD692X0_PSE_NAME "pd692x0_pse" 19 20 #define PD692X0_MAX_PIS 48 21 #define PD692X0_MAX_MANAGERS 12 22 #define PD692X0_MAX_MANAGER_PORTS 8 23 #define PD692X0_MAX_HW_PORTS (PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS) 24 25 #define PD69200_BT_PROD_VER 24 26 #define PD69210_BT_PROD_VER 26 27 #define PD69220_BT_PROD_VER 29 28 29 #define PD692X0_FW_MAJ_VER 3 30 #define PD692X0_FW_MIN_VER 5 31 #define PD692X0_FW_PATCH_VER 5 32 33 enum pd692x0_fw_state { 34 PD692X0_FW_UNKNOWN, 35 PD692X0_FW_OK, 36 PD692X0_FW_BROKEN, 37 PD692X0_FW_NEED_UPDATE, 38 PD692X0_FW_PREPARE, 39 PD692X0_FW_WRITE, 40 PD692X0_FW_COMPLETE, 41 }; 42 43 struct pd692x0_msg { 44 u8 key; 45 u8 echo; 46 u8 sub[3]; 47 u8 data[8]; 48 __be16 chksum; 49 } __packed; 50 51 struct pd692x0_msg_ver { 52 u8 prod; 53 u8 maj_sw_ver; 54 u8 min_sw_ver; 55 u8 pa_sw_ver; 56 u8 param; 57 u8 build; 58 }; 59 60 enum { 61 PD692X0_KEY_CMD, 62 PD692X0_KEY_PRG, 63 PD692X0_KEY_REQ, 64 PD692X0_KEY_TLM, 65 PD692X0_KEY_TEST, 66 PD692X0_KEY_REPORT = 0x52 67 }; 68 69 enum { 70 PD692X0_MSG_RESET, 71 PD692X0_MSG_GET_SYS_STATUS, 72 PD692X0_MSG_GET_SW_VER, 73 PD692X0_MSG_SET_TMP_PORT_MATRIX, 74 PD692X0_MSG_PRG_PORT_MATRIX, 75 PD692X0_MSG_SET_PORT_PARAM, 76 PD692X0_MSG_GET_PORT_STATUS, 77 PD692X0_MSG_DOWNLOAD_CMD, 78 PD692X0_MSG_GET_PORT_CLASS, 79 PD692X0_MSG_GET_PORT_MEAS, 80 PD692X0_MSG_GET_PORT_PARAM, 81 PD692X0_MSG_GET_POWER_BANK, 82 PD692X0_MSG_SET_POWER_BANK, 83 84 /* add new message above here */ 85 PD692X0_MSG_CNT 86 }; 87 88 struct pd692x0_priv { 89 struct i2c_client *client; 90 struct pse_controller_dev pcdev; 91 struct device_node *np; 92 93 enum pd692x0_fw_state fw_state; 94 struct fw_upload *fwl; 95 bool cancel_request; 96 97 u8 msg_id; 98 bool last_cmd_key; 99 unsigned long last_cmd_key_time; 100 101 enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS]; 102 struct regulator_dev *manager_reg[PD692X0_MAX_MANAGERS]; 103 int manager_pw_budget[PD692X0_MAX_MANAGERS]; 104 }; 105 106 /* Template list of communication messages. The non-null bytes defined here 107 * constitute the fixed portion of the messages. The remaining bytes will 108 * be configured later within the functions. Refer to the "PD692x0 BT Serial 109 * Communication Protocol User Guide" for comprehensive details on messages 110 * content. 111 */ 112 static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = { 113 [PD692X0_MSG_RESET] = { 114 .key = PD692X0_KEY_CMD, 115 .sub = {0x07, 0x55, 0x00}, 116 .data = {0x55, 0x00, 0x55, 0x4e, 117 0x4e, 0x4e, 0x4e, 0x4e}, 118 }, 119 [PD692X0_MSG_GET_SYS_STATUS] = { 120 .key = PD692X0_KEY_REQ, 121 .sub = {0x07, 0xd0, 0x4e}, 122 .data = {0x4e, 0x4e, 0x4e, 0x4e, 123 0x4e, 0x4e, 0x4e, 0x4e}, 124 }, 125 [PD692X0_MSG_GET_SW_VER] = { 126 .key = PD692X0_KEY_REQ, 127 .sub = {0x07, 0x1e, 0x21}, 128 .data = {0x4e, 0x4e, 0x4e, 0x4e, 129 0x4e, 0x4e, 0x4e, 0x4e}, 130 }, 131 [PD692X0_MSG_SET_TMP_PORT_MATRIX] = { 132 .key = PD692X0_KEY_CMD, 133 .sub = {0x05, 0x43}, 134 .data = { 0, 0x4e, 0x4e, 0x4e, 135 0x4e, 0x4e, 0x4e, 0x4e}, 136 }, 137 [PD692X0_MSG_PRG_PORT_MATRIX] = { 138 .key = PD692X0_KEY_CMD, 139 .sub = {0x07, 0x43, 0x4e}, 140 .data = {0x4e, 0x4e, 0x4e, 0x4e, 141 0x4e, 0x4e, 0x4e, 0x4e}, 142 }, 143 [PD692X0_MSG_SET_PORT_PARAM] = { 144 .key = PD692X0_KEY_CMD, 145 .sub = {0x05, 0xc0}, 146 .data = { 0xf, 0xff, 0xff, 0xff, 147 0x4e, 0x4e, 0x4e, 0x4e}, 148 }, 149 [PD692X0_MSG_GET_PORT_STATUS] = { 150 .key = PD692X0_KEY_REQ, 151 .sub = {0x05, 0xc1}, 152 .data = {0x4e, 0x4e, 0x4e, 0x4e, 153 0x4e, 0x4e, 0x4e, 0x4e}, 154 }, 155 [PD692X0_MSG_DOWNLOAD_CMD] = { 156 .key = PD692X0_KEY_PRG, 157 .sub = {0xff, 0x99, 0x15}, 158 .data = {0x16, 0x16, 0x99, 0x4e, 159 0x4e, 0x4e, 0x4e, 0x4e}, 160 }, 161 [PD692X0_MSG_GET_PORT_CLASS] = { 162 .key = PD692X0_KEY_REQ, 163 .sub = {0x05, 0xc4}, 164 .data = {0x4e, 0x4e, 0x4e, 0x4e, 165 0x4e, 0x4e, 0x4e, 0x4e}, 166 }, 167 [PD692X0_MSG_GET_PORT_MEAS] = { 168 .key = PD692X0_KEY_REQ, 169 .sub = {0x05, 0xc5}, 170 .data = {0x4e, 0x4e, 0x4e, 0x4e, 171 0x4e, 0x4e, 0x4e, 0x4e}, 172 }, 173 [PD692X0_MSG_GET_PORT_PARAM] = { 174 .key = PD692X0_KEY_REQ, 175 .sub = {0x05, 0xc0}, 176 .data = {0x4e, 0x4e, 0x4e, 0x4e, 177 0x4e, 0x4e, 0x4e, 0x4e}, 178 }, 179 [PD692X0_MSG_GET_POWER_BANK] = { 180 .key = PD692X0_KEY_REQ, 181 .sub = {0x07, 0x0b, 0x57}, 182 .data = { 0, 0x4e, 0x4e, 0x4e, 183 0x4e, 0x4e, 0x4e, 0x4e}, 184 }, 185 [PD692X0_MSG_SET_POWER_BANK] = { 186 .key = PD692X0_KEY_CMD, 187 .sub = {0x07, 0x0b, 0x57}, 188 }, 189 }; 190 191 static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo) 192 { 193 u8 *data = (u8 *)msg; 194 u16 chksum = 0; 195 int i; 196 197 msg->echo = echo++; 198 if (echo == 0xff) 199 echo = 0; 200 201 for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++) 202 chksum += data[i]; 203 204 msg->chksum = cpu_to_be16(chksum); 205 206 return echo; 207 } 208 209 static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg) 210 { 211 const struct i2c_client *client = priv->client; 212 int ret; 213 214 if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) { 215 int cmd_msleep; 216 217 cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time); 218 if (cmd_msleep > 0) 219 msleep(cmd_msleep); 220 } 221 222 /* Add echo and checksum bytes to the message */ 223 priv->msg_id = pd692x0_build_msg(msg, priv->msg_id); 224 225 ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg)); 226 if (ret != sizeof(*msg)) 227 return -EIO; 228 229 return 0; 230 } 231 232 static int pd692x0_reset(struct pd692x0_priv *priv) 233 { 234 const struct i2c_client *client = priv->client; 235 struct pd692x0_msg msg, buf = {0}; 236 int ret; 237 238 msg = pd692x0_msg_template_list[PD692X0_MSG_RESET]; 239 ret = pd692x0_send_msg(priv, &msg); 240 if (ret) { 241 dev_err(&client->dev, 242 "Failed to reset the controller (%pe)\n", ERR_PTR(ret)); 243 return ret; 244 } 245 246 msleep(30); 247 248 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 249 if (ret != sizeof(buf)) 250 return ret < 0 ? ret : -EIO; 251 252 /* Is the reply a successful report message */ 253 if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1]) 254 return -EIO; 255 256 msleep(300); 257 258 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 259 if (ret != sizeof(buf)) 260 return ret < 0 ? ret : -EIO; 261 262 /* Is the boot status without error */ 263 if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) { 264 dev_err(&client->dev, "PSE controller error\n"); 265 return -EIO; 266 } 267 268 return 0; 269 } 270 271 static bool pd692x0_try_recv_msg(const struct i2c_client *client, 272 struct pd692x0_msg *msg, 273 struct pd692x0_msg *buf) 274 { 275 /* Wait 30ms before readback as mandated by the protocol */ 276 msleep(30); 277 278 memset(buf, 0, sizeof(*buf)); 279 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 280 if (buf->key) 281 return 0; 282 283 msleep(100); 284 285 memset(buf, 0, sizeof(*buf)); 286 i2c_master_recv(client, (u8 *)buf, sizeof(*buf)); 287 if (buf->key) 288 return 0; 289 290 return 1; 291 } 292 293 /* Implementation of I2C communication, specifically addressing scenarios 294 * involving communication loss. Refer to the "Synchronization During 295 * Communication Loss" section in the Communication Protocol document for 296 * further details. 297 */ 298 static int pd692x0_recv_msg(struct pd692x0_priv *priv, 299 struct pd692x0_msg *msg, 300 struct pd692x0_msg *buf) 301 { 302 const struct i2c_client *client = priv->client; 303 int ret; 304 305 ret = pd692x0_try_recv_msg(client, msg, buf); 306 if (!ret) 307 goto out_success; 308 309 dev_warn(&client->dev, 310 "Communication lost, rtnl is locked until communication is back!"); 311 312 ret = pd692x0_send_msg(priv, msg); 313 if (ret) 314 return ret; 315 316 ret = pd692x0_try_recv_msg(client, msg, buf); 317 if (!ret) 318 goto out_success2; 319 320 msleep(10000); 321 322 ret = pd692x0_send_msg(priv, msg); 323 if (ret) 324 return ret; 325 326 ret = pd692x0_try_recv_msg(client, msg, buf); 327 if (!ret) 328 goto out_success2; 329 330 return pd692x0_reset(priv); 331 332 out_success2: 333 dev_warn(&client->dev, "Communication is back, rtnl is unlocked!"); 334 out_success: 335 if (msg->key == PD692X0_KEY_CMD) { 336 priv->last_cmd_key = true; 337 priv->last_cmd_key_time = jiffies; 338 } else { 339 priv->last_cmd_key = false; 340 } 341 342 return 0; 343 } 344 345 static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv, 346 struct pd692x0_msg *msg, 347 struct pd692x0_msg *buf) 348 { 349 struct device *dev = &priv->client->dev; 350 int ret; 351 352 ret = pd692x0_send_msg(priv, msg); 353 if (ret) 354 return ret; 355 356 ret = pd692x0_recv_msg(priv, msg, buf); 357 if (ret) 358 return ret; 359 360 if (msg->echo != buf->echo) { 361 dev_err(dev, 362 "Wrong match in message ID, expect %d received %d.\n", 363 msg->echo, buf->echo); 364 return -EIO; 365 } 366 367 /* If the reply is a report message is it successful */ 368 if (buf->key == PD692X0_KEY_REPORT && 369 (buf->sub[0] || buf->sub[1])) { 370 return -EIO; 371 } 372 373 return 0; 374 } 375 376 static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev) 377 { 378 return container_of(pcdev, struct pd692x0_priv, pcdev); 379 } 380 381 static int pd692x0_fw_unavailable(struct pd692x0_priv *priv) 382 { 383 switch (priv->fw_state) { 384 case PD692X0_FW_OK: 385 return 0; 386 case PD692X0_FW_PREPARE: 387 case PD692X0_FW_WRITE: 388 case PD692X0_FW_COMPLETE: 389 dev_err(&priv->client->dev, "Firmware update in progress!\n"); 390 return -EBUSY; 391 case PD692X0_FW_BROKEN: 392 case PD692X0_FW_NEED_UPDATE: 393 default: 394 dev_err(&priv->client->dev, 395 "Firmware issue. Please update it!\n"); 396 return -EOPNOTSUPP; 397 } 398 } 399 400 static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id) 401 { 402 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 403 struct pd692x0_msg msg, buf = {0}; 404 int ret; 405 406 ret = pd692x0_fw_unavailable(priv); 407 if (ret) 408 return ret; 409 410 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED) 411 return 0; 412 413 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 414 msg.data[0] = 0x1; 415 msg.sub[2] = id; 416 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 417 if (ret < 0) 418 return ret; 419 420 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 421 422 return 0; 423 } 424 425 static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id) 426 { 427 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 428 struct pd692x0_msg msg, buf = {0}; 429 int ret; 430 431 ret = pd692x0_fw_unavailable(priv); 432 if (ret) 433 return ret; 434 435 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED) 436 return 0; 437 438 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 439 msg.data[0] = 0x0; 440 msg.sub[2] = id; 441 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 442 if (ret < 0) 443 return ret; 444 445 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 446 447 return 0; 448 } 449 450 struct pd692x0_pse_ext_state_mapping { 451 u32 status_code; 452 enum ethtool_c33_pse_ext_state pse_ext_state; 453 u32 pse_ext_substate; 454 }; 455 456 static const struct pd692x0_pse_ext_state_mapping 457 pd692x0_pse_ext_state_map[] = { 458 {0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 459 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE}, 460 {0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 461 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE}, 462 {0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE, 463 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE}, 464 {0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 465 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT}, 466 {0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 467 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT}, 468 {0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 469 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 470 {0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 471 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS}, 472 {0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 473 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 474 {0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 475 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD}, 476 {0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED, 477 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD}, 478 {0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 479 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED}, 480 {0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 481 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT}, 482 {0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 483 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE}, 484 {0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 485 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION}, 486 {0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 487 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 488 {0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED, 489 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION}, 490 {0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 491 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 492 {0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 493 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP}, 494 {0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 495 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 496 {0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 497 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET}, 498 {0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 499 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT}, 500 {0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 501 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT}, 502 {0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION, 503 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS}, 504 {0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 505 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR}, 506 {0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 507 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN}, 508 { /* sentinel */ } 509 }; 510 511 static int 512 pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id, 513 struct pse_ext_state_info *ext_state_info) 514 { 515 struct ethtool_c33_pse_ext_state_info *c33_ext_state_info; 516 const struct pd692x0_pse_ext_state_mapping *ext_state_map; 517 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 518 struct pd692x0_msg msg, buf = {0}; 519 int ret; 520 521 ret = pd692x0_fw_unavailable(priv); 522 if (ret) 523 return ret; 524 525 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 526 msg.sub[2] = id; 527 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 528 if (ret < 0) 529 return ret; 530 531 c33_ext_state_info = &ext_state_info->c33_ext_state_info; 532 ext_state_map = pd692x0_pse_ext_state_map; 533 while (ext_state_map->status_code) { 534 if (ext_state_map->status_code == buf.sub[0]) { 535 c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state; 536 c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate; 537 return 0; 538 } 539 ext_state_map++; 540 } 541 542 return 0; 543 } 544 545 struct pd692x0_class_pw { 546 int class; 547 int class_cfg_value; 548 int class_pw; 549 int max_added_class_pw; 550 }; 551 552 #define PD692X0_CLASS_PW_TABLE_SIZE 4 553 /* 4/2 pairs class configuration power table in compliance mode. 554 * Need to be arranged in ascending order of power support. 555 */ 556 static const struct pd692x0_class_pw 557 pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = { 558 {.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100}, 559 {.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000}, 560 {.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000}, 561 {.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500}, 562 }; 563 564 static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw) 565 { 566 const struct pd692x0_class_pw *pw_table; 567 int i; 568 569 pw_table = pd692x0_class_pw_table; 570 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 571 if (pw_table->class_cfg_value == op_mode) 572 return pw_table->class_pw + added_pw * 100; 573 } 574 575 return -ERANGE; 576 } 577 578 static int pd692x0_pi_set_pw_from_table(struct device *dev, 579 struct pd692x0_msg *msg, int pw) 580 { 581 const struct pd692x0_class_pw *pw_table; 582 int i; 583 584 pw_table = pd692x0_class_pw_table; 585 if (pw < pw_table->class_pw) { 586 dev_err(dev, 587 "Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n", 588 pw, 589 pw_table->class_pw, 590 pw_table->class_pw + pw_table->max_added_class_pw); 591 return -ERANGE; 592 } 593 594 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 595 if (pw > (pw_table->class_pw + pw_table->max_added_class_pw)) 596 continue; 597 598 if (pw < pw_table->class_pw) { 599 dev_err(dev, 600 "Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n", 601 pw, 602 (pw_table - 1)->class_pw, 603 (pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw, 604 pw_table->class_pw, 605 pw_table->class_pw + pw_table->max_added_class_pw); 606 return -ERANGE; 607 } 608 609 msg->data[2] = pw_table->class_cfg_value; 610 msg->data[3] = (pw - pw_table->class_pw) / 100; 611 return 0; 612 } 613 614 pw_table--; 615 dev_warn(dev, 616 "Power limit %dmW not supported. Set to highest power limit %dmW\n", 617 pw, pw_table->class_pw + pw_table->max_added_class_pw); 618 msg->data[2] = pw_table->class_cfg_value; 619 msg->data[3] = pw_table->max_added_class_pw / 100; 620 return 0; 621 } 622 623 static int 624 pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id, 625 struct pse_pw_limit_ranges *pw_limit_ranges) 626 { 627 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 628 const struct pd692x0_class_pw *pw_table; 629 int i; 630 631 pw_table = pd692x0_class_pw_table; 632 c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE, 633 sizeof(*c33_pw_limit_ranges), 634 GFP_KERNEL); 635 if (!c33_pw_limit_ranges) 636 return -ENOMEM; 637 638 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) { 639 c33_pw_limit_ranges[i].min = pw_table->class_pw; 640 c33_pw_limit_ranges[i].max = pw_table->class_pw + 641 pw_table->max_added_class_pw; 642 } 643 644 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges; 645 return i; 646 } 647 648 static int 649 pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id, 650 struct pse_admin_state *admin_state) 651 { 652 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 653 struct pd692x0_msg msg, buf = {0}; 654 int ret; 655 656 ret = pd692x0_fw_unavailable(priv); 657 if (ret) 658 return ret; 659 660 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 661 msg.sub[2] = id; 662 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 663 if (ret < 0) 664 return ret; 665 666 if (buf.sub[1]) 667 admin_state->c33_admin_state = 668 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED; 669 else 670 admin_state->c33_admin_state = 671 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED; 672 673 priv->admin_state[id] = admin_state->c33_admin_state; 674 675 return 0; 676 } 677 678 static int 679 pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id, 680 struct pse_pw_status *pw_status) 681 { 682 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 683 struct pd692x0_msg msg, buf = {0}; 684 int ret; 685 686 ret = pd692x0_fw_unavailable(priv); 687 if (ret) 688 return ret; 689 690 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 691 msg.sub[2] = id; 692 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 693 if (ret < 0) 694 return ret; 695 696 /* Compare Port Status (Communication Protocol Document par. 7.1) */ 697 if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90) 698 pw_status->c33_pw_status = 699 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING; 700 else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22) 701 pw_status->c33_pw_status = 702 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING; 703 else if (buf.sub[0] == 0x12) 704 pw_status->c33_pw_status = 705 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT; 706 else 707 pw_status->c33_pw_status = 708 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED; 709 710 return 0; 711 } 712 713 static int 714 pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id) 715 { 716 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 717 struct pd692x0_msg msg, buf = {0}; 718 u32 class; 719 int ret; 720 721 ret = pd692x0_fw_unavailable(priv); 722 if (ret) 723 return ret; 724 725 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS]; 726 msg.sub[2] = id; 727 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 728 if (ret < 0) 729 return ret; 730 731 class = buf.data[3] >> 4; 732 if (class <= 8) 733 return class; 734 735 return 0; 736 } 737 738 static int 739 pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id) 740 { 741 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 742 struct pd692x0_msg msg, buf = {0}; 743 int ret; 744 745 ret = pd692x0_fw_unavailable(priv); 746 if (ret) 747 return ret; 748 749 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS]; 750 msg.sub[2] = id; 751 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 752 if (ret < 0) 753 return ret; 754 755 return (buf.data[0] << 4 | buf.data[1]) * 100; 756 } 757 758 static int 759 pd692x0_pi_get_prio(struct pse_controller_dev *pcdev, int id) 760 { 761 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 762 struct pd692x0_msg msg, buf = {0}; 763 int ret; 764 765 ret = pd692x0_fw_unavailable(priv); 766 if (ret) 767 return ret; 768 769 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 770 msg.sub[2] = id; 771 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 772 if (ret < 0) 773 return ret; 774 if (!buf.data[2] || buf.data[2] > pcdev->pis_prio_max + 1) 775 return -ERANGE; 776 777 /* PSE core priority start at 0 */ 778 return buf.data[2] - 1; 779 } 780 781 static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv) 782 { 783 struct device *dev = &priv->client->dev; 784 struct pd692x0_msg msg, buf = {0}; 785 struct pd692x0_msg_ver ver = {0}; 786 int ret; 787 788 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER]; 789 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 790 if (ret < 0) { 791 dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret)); 792 return ver; 793 } 794 795 /* Extract version from the message */ 796 ver.prod = buf.sub[2]; 797 ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100; 798 ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10; 799 ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10; 800 ver.param = buf.data[2]; 801 ver.build = buf.data[3]; 802 803 return ver; 804 } 805 806 struct pd692x0_manager { 807 struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS]; 808 struct device_node *node; 809 int nports; 810 }; 811 812 struct pd692x0_matrix { 813 u8 hw_port_a; 814 u8 hw_port_b; 815 }; 816 817 static int 818 pd692x0_of_get_ports_manager(struct pd692x0_priv *priv, 819 struct pd692x0_manager *manager, 820 struct device_node *np) 821 { 822 struct device_node *node; 823 int ret, nports, i; 824 825 nports = 0; 826 for_each_child_of_node(np, node) { 827 u32 port; 828 829 if (!of_node_name_eq(node, "port")) 830 continue; 831 832 ret = of_property_read_u32(node, "reg", &port); 833 if (ret) 834 goto out; 835 836 if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) { 837 dev_err(&priv->client->dev, 838 "wrong number or order of manager ports (%d)\n", 839 port); 840 ret = -EINVAL; 841 goto out; 842 } 843 844 of_node_get(node); 845 manager->port_node[port] = node; 846 nports++; 847 } 848 849 manager->nports = nports; 850 return 0; 851 852 out: 853 for (i = 0; i < nports; i++) { 854 of_node_put(manager->port_node[i]); 855 manager->port_node[i] = NULL; 856 } 857 of_node_put(node); 858 return ret; 859 } 860 861 static int 862 pd692x0_of_get_managers(struct pd692x0_priv *priv, 863 struct pd692x0_manager manager[PD692X0_MAX_MANAGERS]) 864 { 865 struct device_node *managers_node, *node; 866 int ret, nmanagers, i, j; 867 868 if (!priv->np) 869 return -EINVAL; 870 871 nmanagers = 0; 872 managers_node = of_get_child_by_name(priv->np, "managers"); 873 if (!managers_node) 874 return -EINVAL; 875 876 for_each_child_of_node(managers_node, node) { 877 u32 manager_id; 878 879 if (!of_node_name_eq(node, "manager")) 880 continue; 881 882 ret = of_property_read_u32(node, "reg", &manager_id); 883 if (ret) 884 goto out; 885 886 if (manager_id >= PD692X0_MAX_MANAGERS || 887 manager_id != nmanagers) { 888 dev_err(&priv->client->dev, 889 "wrong number or order of managers (%d)\n", 890 manager_id); 891 ret = -EINVAL; 892 goto out; 893 } 894 895 ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id], 896 node); 897 if (ret) 898 goto out; 899 900 of_node_get(node); 901 manager[manager_id].node = node; 902 nmanagers++; 903 } 904 905 of_node_put(managers_node); 906 return nmanagers; 907 908 out: 909 for (i = 0; i < nmanagers; i++) { 910 for (j = 0; j < manager[i].nports; j++) { 911 of_node_put(manager[i].port_node[j]); 912 manager[i].port_node[j] = NULL; 913 } 914 of_node_put(manager[i].node); 915 manager[i].node = NULL; 916 } 917 918 of_node_put(node); 919 of_node_put(managers_node); 920 return ret; 921 } 922 923 static const struct regulator_ops dummy_ops; 924 925 static struct regulator_dev * 926 pd692x0_register_manager_regulator(struct device *dev, char *reg_name, 927 struct device_node *node) 928 { 929 struct regulator_init_data *rinit_data; 930 struct regulator_config rconfig = {0}; 931 struct regulator_desc *rdesc; 932 struct regulator_dev *rdev; 933 934 rinit_data = devm_kzalloc(dev, sizeof(*rinit_data), 935 GFP_KERNEL); 936 if (!rinit_data) 937 return ERR_PTR(-ENOMEM); 938 939 rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); 940 if (!rdesc) 941 return ERR_PTR(-ENOMEM); 942 943 rdesc->name = reg_name; 944 rdesc->type = REGULATOR_VOLTAGE; 945 rdesc->ops = &dummy_ops; 946 rdesc->owner = THIS_MODULE; 947 948 rinit_data->supply_regulator = "vmain"; 949 950 rconfig.dev = dev; 951 rconfig.init_data = rinit_data; 952 rconfig.of_node = node; 953 954 rdev = devm_regulator_register(dev, rdesc, &rconfig); 955 if (IS_ERR(rdev)) { 956 dev_err_probe(dev, PTR_ERR(rdev), 957 "Failed to register regulator\n"); 958 return rdev; 959 } 960 961 return rdev; 962 } 963 964 static int 965 pd692x0_register_managers_regulator(struct pd692x0_priv *priv, 966 const struct pd692x0_manager *manager, 967 int nmanagers) 968 { 969 struct device *dev = &priv->client->dev; 970 size_t reg_name_len; 971 int i; 972 973 /* Each regulator name len is dev name + 12 char + 974 * int max digit number (10) + 1 975 */ 976 reg_name_len = strlen(dev_name(dev)) + 23; 977 978 for (i = 0; i < nmanagers; i++) { 979 static const char * const regulators[] = { "vaux5", "vaux3p3" }; 980 struct regulator_dev *rdev; 981 char *reg_name; 982 int ret; 983 984 reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL); 985 if (!reg_name) 986 return -ENOMEM; 987 snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i); 988 rdev = pd692x0_register_manager_regulator(dev, reg_name, 989 manager[i].node); 990 if (IS_ERR(rdev)) 991 return PTR_ERR(rdev); 992 993 /* VMAIN is described as main supply for the manager. 994 * Add other VAUX power supplies and link them to the 995 * virtual device rdev->dev. 996 */ 997 ret = devm_regulator_bulk_get_enable(&rdev->dev, 998 ARRAY_SIZE(regulators), 999 regulators); 1000 if (ret) 1001 return dev_err_probe(&rdev->dev, ret, 1002 "Failed to enable regulators\n"); 1003 1004 priv->manager_reg[i] = rdev; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int 1011 pd692x0_conf_manager_power_budget(struct pd692x0_priv *priv, int id, int pw) 1012 { 1013 struct pd692x0_msg msg, buf; 1014 int ret, pw_mW = pw / 1000; 1015 1016 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_POWER_BANK]; 1017 msg.data[0] = id; 1018 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1019 if (ret < 0) 1020 return ret; 1021 1022 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_POWER_BANK]; 1023 msg.data[0] = id; 1024 msg.data[1] = pw_mW >> 8; 1025 msg.data[2] = pw_mW & 0xff; 1026 msg.data[3] = buf.sub[2]; 1027 msg.data[4] = buf.data[0]; 1028 msg.data[5] = buf.data[1]; 1029 msg.data[6] = buf.data[2]; 1030 msg.data[7] = buf.data[3]; 1031 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1032 } 1033 1034 static int 1035 pd692x0_configure_managers(struct pd692x0_priv *priv, int nmanagers) 1036 { 1037 int i, ret; 1038 1039 for (i = 0; i < nmanagers; i++) { 1040 struct regulator *supply = priv->manager_reg[i]->supply; 1041 int pw_budget; 1042 1043 pw_budget = regulator_get_unclaimed_power_budget(supply); 1044 /* Max power budget per manager */ 1045 if (pw_budget > 6000000) 1046 pw_budget = 6000000; 1047 ret = regulator_request_power_budget(supply, pw_budget); 1048 if (ret < 0) 1049 return ret; 1050 1051 priv->manager_pw_budget[i] = pw_budget; 1052 ret = pd692x0_conf_manager_power_budget(priv, i, pw_budget); 1053 if (ret < 0) 1054 return ret; 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int 1061 pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset, 1062 const struct pd692x0_manager *manager, 1063 int nmanagers, struct pd692x0_matrix *port_matrix) 1064 { 1065 int i, j, port_cnt; 1066 bool found = false; 1067 1068 if (!pairset->np) 1069 return 0; 1070 1071 /* Look on every managers */ 1072 port_cnt = 0; 1073 for (i = 0; i < nmanagers; i++) { 1074 /* Look on every ports of the manager */ 1075 for (j = 0; j < manager[i].nports; j++) { 1076 if (pairset->np == manager[i].port_node[j]) { 1077 found = true; 1078 break; 1079 } 1080 } 1081 port_cnt += j; 1082 1083 if (found) 1084 break; 1085 } 1086 1087 if (!found) 1088 return -ENODEV; 1089 1090 if (pairset->pinout == ALTERNATIVE_A) 1091 port_matrix->hw_port_a = port_cnt; 1092 else if (pairset->pinout == ALTERNATIVE_B) 1093 port_matrix->hw_port_b = port_cnt; 1094 1095 return 0; 1096 } 1097 1098 static int 1099 pd692x0_set_ports_matrix(struct pd692x0_priv *priv, 1100 const struct pd692x0_manager *manager, 1101 int nmanagers, 1102 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]) 1103 { 1104 struct pse_controller_dev *pcdev = &priv->pcdev; 1105 int i, ret; 1106 1107 /* Init Matrix */ 1108 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1109 port_matrix[i].hw_port_a = 0xff; 1110 port_matrix[i].hw_port_b = 0xff; 1111 } 1112 1113 /* Update with values for every PSE PIs */ 1114 for (i = 0; i < pcdev->nr_lines; i++) { 1115 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0], 1116 manager, nmanagers, 1117 &port_matrix[i]); 1118 if (ret) { 1119 dev_err(&priv->client->dev, 1120 "unable to configure pi %d pairset 0", i); 1121 return ret; 1122 } 1123 1124 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1], 1125 manager, nmanagers, 1126 &port_matrix[i]); 1127 if (ret) { 1128 dev_err(&priv->client->dev, 1129 "unable to configure pi %d pairset 1", i); 1130 return ret; 1131 } 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int 1138 pd692x0_write_ports_matrix(struct pd692x0_priv *priv, 1139 const struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]) 1140 { 1141 struct pd692x0_msg msg, buf; 1142 int ret, i; 1143 1144 /* Write temporary Matrix */ 1145 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX]; 1146 for (i = 0; i < PD692X0_MAX_PIS; i++) { 1147 msg.sub[2] = i; 1148 msg.data[0] = port_matrix[i].hw_port_b; 1149 msg.data[1] = port_matrix[i].hw_port_a; 1150 1151 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1152 if (ret < 0) 1153 return ret; 1154 } 1155 1156 /* Program Matrix */ 1157 msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX]; 1158 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1159 if (ret < 0) 1160 return ret; 1161 1162 return 0; 1163 } 1164 1165 static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev) 1166 { 1167 struct pd692x0_manager manager[PD692X0_MAX_MANAGERS] = {0}; 1168 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1169 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS]; 1170 int ret, i, j, nmanagers; 1171 1172 /* Should we flash the port matrix */ 1173 if (priv->fw_state != PD692X0_FW_OK && 1174 priv->fw_state != PD692X0_FW_COMPLETE) 1175 return 0; 1176 1177 ret = pd692x0_of_get_managers(priv, manager); 1178 if (ret < 0) 1179 return ret; 1180 1181 nmanagers = ret; 1182 ret = pd692x0_register_managers_regulator(priv, manager, nmanagers); 1183 if (ret) 1184 goto out; 1185 1186 ret = pd692x0_configure_managers(priv, nmanagers); 1187 if (ret) 1188 goto out; 1189 1190 ret = pd692x0_set_ports_matrix(priv, manager, nmanagers, port_matrix); 1191 if (ret) 1192 goto out; 1193 1194 ret = pd692x0_write_ports_matrix(priv, port_matrix); 1195 if (ret) 1196 goto out; 1197 1198 out: 1199 for (i = 0; i < nmanagers; i++) { 1200 struct regulator *supply = priv->manager_reg[i]->supply; 1201 1202 regulator_free_power_budget(supply, 1203 priv->manager_pw_budget[i]); 1204 1205 for (j = 0; j < manager[i].nports; j++) 1206 of_node_put(manager[i].port_node[j]); 1207 of_node_put(manager[i].node); 1208 } 1209 return ret; 1210 } 1211 1212 static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id) 1213 { 1214 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1215 struct pd692x0_msg msg, buf = {0}; 1216 int ret; 1217 1218 ret = pd692x0_fw_unavailable(priv); 1219 if (ret) 1220 return ret; 1221 1222 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS]; 1223 msg.sub[2] = id; 1224 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1225 if (ret < 0) 1226 return ret; 1227 1228 /* Convert 0.1V unit to uV */ 1229 return (buf.sub[0] << 8 | buf.sub[1]) * 100000; 1230 } 1231 1232 static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev, 1233 int id) 1234 { 1235 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1236 struct pd692x0_msg msg, buf = {0}; 1237 int ret; 1238 1239 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM]; 1240 msg.sub[2] = id; 1241 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1242 if (ret < 0) 1243 return ret; 1244 1245 return pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]); 1246 } 1247 1248 static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev, 1249 int id, int max_mW) 1250 { 1251 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1252 struct device *dev = &priv->client->dev; 1253 struct pd692x0_msg msg, buf = {0}; 1254 int ret; 1255 1256 ret = pd692x0_fw_unavailable(priv); 1257 if (ret) 1258 return ret; 1259 1260 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1261 msg.sub[2] = id; 1262 ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW); 1263 if (ret) 1264 return ret; 1265 1266 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1267 } 1268 1269 static int pd692x0_pi_set_prio(struct pse_controller_dev *pcdev, int id, 1270 unsigned int prio) 1271 { 1272 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev); 1273 struct pd692x0_msg msg, buf = {0}; 1274 int ret; 1275 1276 ret = pd692x0_fw_unavailable(priv); 1277 if (ret) 1278 return ret; 1279 1280 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM]; 1281 msg.sub[2] = id; 1282 /* Controller priority from 1 to 3 */ 1283 msg.data[4] = prio + 1; 1284 1285 return pd692x0_sendrecv_msg(priv, &msg, &buf); 1286 } 1287 1288 static const struct pse_controller_ops pd692x0_ops = { 1289 .setup_pi_matrix = pd692x0_setup_pi_matrix, 1290 .pi_get_admin_state = pd692x0_pi_get_admin_state, 1291 .pi_get_pw_status = pd692x0_pi_get_pw_status, 1292 .pi_get_ext_state = pd692x0_pi_get_ext_state, 1293 .pi_get_pw_class = pd692x0_pi_get_pw_class, 1294 .pi_get_actual_pw = pd692x0_pi_get_actual_pw, 1295 .pi_enable = pd692x0_pi_enable, 1296 .pi_disable = pd692x0_pi_disable, 1297 .pi_get_voltage = pd692x0_pi_get_voltage, 1298 .pi_get_pw_limit = pd692x0_pi_get_pw_limit, 1299 .pi_set_pw_limit = pd692x0_pi_set_pw_limit, 1300 .pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges, 1301 .pi_get_prio = pd692x0_pi_get_prio, 1302 .pi_set_prio = pd692x0_pi_set_prio, 1303 }; 1304 1305 #define PD692X0_FW_LINE_MAX_SZ 0xff 1306 static int pd692x0_fw_get_next_line(const u8 *data, 1307 char *line, size_t size) 1308 { 1309 size_t line_size; 1310 int i; 1311 1312 line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ); 1313 1314 memset(line, 0, PD692X0_FW_LINE_MAX_SZ); 1315 for (i = 0; i < line_size - 1; i++) { 1316 if (*data == '\r' && *(data + 1) == '\n') { 1317 line[i] = '\r'; 1318 line[i + 1] = '\n'; 1319 return i + 2; 1320 } 1321 line[i] = *data; 1322 data++; 1323 } 1324 1325 return -EIO; 1326 } 1327 1328 static enum fw_upload_err 1329 pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout, 1330 const char *msg_ok, unsigned int msg_size) 1331 { 1332 /* Maximum controller response size */ 1333 char fw_msg_buf[5] = {0}; 1334 unsigned long timeout; 1335 int ret; 1336 1337 if (msg_size > sizeof(fw_msg_buf)) 1338 return FW_UPLOAD_ERR_RW_ERROR; 1339 1340 /* Read until we get something */ 1341 timeout = msecs_to_jiffies(ms_timeout) + jiffies; 1342 while (true) { 1343 if (time_is_before_jiffies(timeout)) 1344 return FW_UPLOAD_ERR_TIMEOUT; 1345 1346 ret = i2c_master_recv(client, fw_msg_buf, 1); 1347 if (ret < 0 || *fw_msg_buf == 0) { 1348 usleep_range(1000, 2000); 1349 continue; 1350 } else { 1351 break; 1352 } 1353 } 1354 1355 /* Read remaining characters */ 1356 ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1); 1357 if (strncmp(fw_msg_buf, msg_ok, msg_size)) { 1358 dev_err(&client->dev, 1359 "Wrong FW download process answer (%*pE)\n", 1360 msg_size, fw_msg_buf); 1361 return FW_UPLOAD_ERR_HW_ERROR; 1362 } 1363 1364 return FW_UPLOAD_ERR_NONE; 1365 } 1366 1367 static int pd692x0_fw_write_line(const struct i2c_client *client, 1368 const char line[PD692X0_FW_LINE_MAX_SZ], 1369 const bool last_line) 1370 { 1371 int ret; 1372 1373 while (*line != 0) { 1374 ret = i2c_master_send(client, line, 1); 1375 if (ret < 0) 1376 return FW_UPLOAD_ERR_RW_ERROR; 1377 line++; 1378 } 1379 1380 if (last_line) { 1381 ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n", 1382 sizeof("TP\r\n") - 1); 1383 if (ret) 1384 return ret; 1385 } else { 1386 ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n", 1387 sizeof("T*\r\n") - 1); 1388 if (ret) 1389 return ret; 1390 } 1391 1392 return FW_UPLOAD_ERR_NONE; 1393 } 1394 1395 static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client) 1396 { 1397 const struct pd692x0_msg zero = {0}; 1398 struct pd692x0_msg buf = {0}; 1399 unsigned long timeout; 1400 char cmd[] = "RST"; 1401 int ret; 1402 1403 ret = i2c_master_send(client, cmd, strlen(cmd)); 1404 if (ret < 0) { 1405 dev_err(&client->dev, 1406 "Failed to reset the controller (%pe)\n", 1407 ERR_PTR(ret)); 1408 return ret; 1409 } 1410 1411 timeout = msecs_to_jiffies(10000) + jiffies; 1412 while (true) { 1413 if (time_is_before_jiffies(timeout)) 1414 return FW_UPLOAD_ERR_TIMEOUT; 1415 1416 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1417 if (ret < 0 || 1418 !memcmp(&buf, &zero, sizeof(buf))) 1419 usleep_range(1000, 2000); 1420 else 1421 break; 1422 } 1423 1424 /* Is the reply a successful report message */ 1425 if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff || 1426 buf.sub[0] & 0x01) { 1427 dev_err(&client->dev, "PSE controller error\n"); 1428 return FW_UPLOAD_ERR_HW_ERROR; 1429 } 1430 1431 /* Is the firmware operational */ 1432 if (buf.sub[0] & 0x02) { 1433 dev_err(&client->dev, 1434 "PSE firmware error. Please update it.\n"); 1435 return FW_UPLOAD_ERR_HW_ERROR; 1436 } 1437 1438 return FW_UPLOAD_ERR_NONE; 1439 } 1440 1441 static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl, 1442 const u8 *data, u32 size) 1443 { 1444 struct pd692x0_priv *priv = fwl->dd_handle; 1445 const struct i2c_client *client = priv->client; 1446 enum pd692x0_fw_state last_fw_state; 1447 int ret; 1448 1449 priv->cancel_request = false; 1450 last_fw_state = priv->fw_state; 1451 1452 priv->fw_state = PD692X0_FW_PREPARE; 1453 1454 /* Enter program mode */ 1455 if (last_fw_state == PD692X0_FW_BROKEN) { 1456 const char *msg = "ENTR"; 1457 const char *c; 1458 1459 c = msg; 1460 do { 1461 ret = i2c_master_send(client, c, 1); 1462 if (ret < 0) 1463 return FW_UPLOAD_ERR_RW_ERROR; 1464 if (*(c + 1)) 1465 usleep_range(10000, 20000); 1466 } while (*(++c)); 1467 } else { 1468 struct pd692x0_msg msg, buf; 1469 1470 msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD]; 1471 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1472 if (ret < 0) { 1473 dev_err(&client->dev, 1474 "Failed to enter programming mode (%pe)\n", 1475 ERR_PTR(ret)); 1476 return FW_UPLOAD_ERR_RW_ERROR; 1477 } 1478 } 1479 1480 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1481 if (ret) 1482 goto err_out; 1483 1484 if (priv->cancel_request) { 1485 ret = FW_UPLOAD_ERR_CANCELED; 1486 goto err_out; 1487 } 1488 1489 return FW_UPLOAD_ERR_NONE; 1490 1491 err_out: 1492 pd692x0_fw_reset(priv->client); 1493 priv->fw_state = last_fw_state; 1494 return ret; 1495 } 1496 1497 static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl, 1498 const u8 *data, u32 offset, 1499 u32 size, u32 *written) 1500 { 1501 struct pd692x0_priv *priv = fwl->dd_handle; 1502 char line[PD692X0_FW_LINE_MAX_SZ]; 1503 const struct i2c_client *client; 1504 int ret, i; 1505 char cmd; 1506 1507 client = priv->client; 1508 priv->fw_state = PD692X0_FW_WRITE; 1509 1510 /* Erase */ 1511 cmd = 'E'; 1512 ret = i2c_master_send(client, &cmd, 1); 1513 if (ret < 0) { 1514 dev_err(&client->dev, 1515 "Failed to boot programming mode (%pe)\n", 1516 ERR_PTR(ret)); 1517 return FW_UPLOAD_ERR_RW_ERROR; 1518 } 1519 1520 ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1); 1521 if (ret) 1522 return ret; 1523 1524 ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1); 1525 if (ret) 1526 dev_warn(&client->dev, 1527 "Failed to erase internal memory, however still try to write Firmware\n"); 1528 1529 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1); 1530 if (ret) 1531 dev_warn(&client->dev, 1532 "Failed to erase internal memory, however still try to write Firmware\n"); 1533 1534 if (priv->cancel_request) 1535 return FW_UPLOAD_ERR_CANCELED; 1536 1537 /* Program */ 1538 cmd = 'P'; 1539 ret = i2c_master_send(client, &cmd, sizeof(char)); 1540 if (ret < 0) { 1541 dev_err(&client->dev, 1542 "Failed to boot programming mode (%pe)\n", 1543 ERR_PTR(ret)); 1544 return ret; 1545 } 1546 1547 ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1); 1548 if (ret) 1549 return ret; 1550 1551 i = 0; 1552 while (i < size) { 1553 ret = pd692x0_fw_get_next_line(data, line, size - i); 1554 if (ret < 0) { 1555 ret = FW_UPLOAD_ERR_FW_INVALID; 1556 goto err; 1557 } 1558 1559 i += ret; 1560 data += ret; 1561 if (line[0] == 'S' && line[1] == '0') { 1562 continue; 1563 } else if (line[0] == 'S' && line[1] == '7') { 1564 ret = pd692x0_fw_write_line(client, line, true); 1565 if (ret) 1566 goto err; 1567 } else { 1568 ret = pd692x0_fw_write_line(client, line, false); 1569 if (ret) 1570 goto err; 1571 } 1572 1573 if (priv->cancel_request) { 1574 ret = FW_UPLOAD_ERR_CANCELED; 1575 goto err; 1576 } 1577 } 1578 *written = i; 1579 1580 msleep(400); 1581 1582 return FW_UPLOAD_ERR_NONE; 1583 1584 err: 1585 strscpy_pad(line, "S7\r\n", sizeof(line)); 1586 pd692x0_fw_write_line(client, line, true); 1587 return ret; 1588 } 1589 1590 static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl) 1591 { 1592 struct pd692x0_priv *priv = fwl->dd_handle; 1593 const struct i2c_client *client = priv->client; 1594 struct pd692x0_msg_ver ver; 1595 int ret; 1596 1597 priv->fw_state = PD692X0_FW_COMPLETE; 1598 1599 ret = pd692x0_fw_reset(client); 1600 if (ret) 1601 return ret; 1602 1603 ver = pd692x0_get_sw_version(priv); 1604 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1605 dev_err(&client->dev, 1606 "Too old firmware version. Please update it\n"); 1607 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1608 return FW_UPLOAD_ERR_FW_INVALID; 1609 } 1610 1611 ret = pd692x0_setup_pi_matrix(&priv->pcdev); 1612 if (ret < 0) { 1613 dev_err(&client->dev, "Error configuring ports matrix (%pe)\n", 1614 ERR_PTR(ret)); 1615 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1616 return FW_UPLOAD_ERR_HW_ERROR; 1617 } 1618 1619 priv->fw_state = PD692X0_FW_OK; 1620 return FW_UPLOAD_ERR_NONE; 1621 } 1622 1623 static void pd692x0_fw_cancel(struct fw_upload *fwl) 1624 { 1625 struct pd692x0_priv *priv = fwl->dd_handle; 1626 1627 priv->cancel_request = true; 1628 } 1629 1630 static void pd692x0_fw_cleanup(struct fw_upload *fwl) 1631 { 1632 struct pd692x0_priv *priv = fwl->dd_handle; 1633 1634 switch (priv->fw_state) { 1635 case PD692X0_FW_WRITE: 1636 pd692x0_fw_reset(priv->client); 1637 fallthrough; 1638 case PD692X0_FW_COMPLETE: 1639 priv->fw_state = PD692X0_FW_BROKEN; 1640 break; 1641 default: 1642 break; 1643 } 1644 } 1645 1646 static const struct fw_upload_ops pd692x0_fw_ops = { 1647 .prepare = pd692x0_fw_prepare, 1648 .write = pd692x0_fw_write, 1649 .poll_complete = pd692x0_fw_poll_complete, 1650 .cancel = pd692x0_fw_cancel, 1651 .cleanup = pd692x0_fw_cleanup, 1652 }; 1653 1654 static int pd692x0_i2c_probe(struct i2c_client *client) 1655 { 1656 static const char * const regulators[] = { "vdd", "vdda" }; 1657 struct pd692x0_msg msg, buf = {0}, zero = {0}; 1658 struct device *dev = &client->dev; 1659 struct pd692x0_msg_ver ver; 1660 struct pd692x0_priv *priv; 1661 struct fw_upload *fwl; 1662 int ret; 1663 1664 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), 1665 regulators); 1666 if (ret) 1667 return dev_err_probe(dev, ret, 1668 "Failed to enable regulators\n"); 1669 1670 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1671 dev_err(dev, "i2c check functionality failed\n"); 1672 return -ENXIO; 1673 } 1674 1675 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1676 if (!priv) 1677 return -ENOMEM; 1678 1679 priv->client = client; 1680 i2c_set_clientdata(client, priv); 1681 1682 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf)); 1683 if (ret != sizeof(buf)) { 1684 dev_err(dev, "Failed to get device status\n"); 1685 return -EIO; 1686 } 1687 1688 /* Probe has been already run and the status dumped */ 1689 if (!memcmp(&buf, &zero, sizeof(buf))) { 1690 /* Ask again the controller status */ 1691 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS]; 1692 ret = pd692x0_sendrecv_msg(priv, &msg, &buf); 1693 if (ret < 0) { 1694 dev_err(dev, "Failed to get device status\n"); 1695 return ret; 1696 } 1697 } 1698 1699 if (buf.key != 0x03 || buf.sub[0] & 0x01) { 1700 dev_err(dev, "PSE controller error\n"); 1701 return -EIO; 1702 } 1703 if (buf.sub[0] & 0x02) { 1704 dev_err(dev, "PSE firmware error. Please update it.\n"); 1705 priv->fw_state = PD692X0_FW_BROKEN; 1706 } else { 1707 ver = pd692x0_get_sw_version(priv); 1708 dev_info(&client->dev, "Software version %d.%02d.%d.%d\n", 1709 ver.prod, ver.maj_sw_ver, ver.min_sw_ver, 1710 ver.pa_sw_ver); 1711 1712 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) { 1713 dev_err(dev, "Too old firmware version. Please update it\n"); 1714 priv->fw_state = PD692X0_FW_NEED_UPDATE; 1715 } else { 1716 priv->fw_state = PD692X0_FW_OK; 1717 } 1718 } 1719 1720 priv->np = dev->of_node; 1721 priv->pcdev.nr_lines = PD692X0_MAX_PIS; 1722 priv->pcdev.owner = THIS_MODULE; 1723 priv->pcdev.ops = &pd692x0_ops; 1724 priv->pcdev.dev = dev; 1725 priv->pcdev.types = ETHTOOL_PSE_C33; 1726 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC; 1727 priv->pcdev.pis_prio_max = 2; 1728 ret = devm_pse_controller_register(dev, &priv->pcdev); 1729 if (ret) 1730 return dev_err_probe(dev, ret, 1731 "failed to register PSE controller\n"); 1732 1733 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev), 1734 &pd692x0_fw_ops, priv); 1735 if (IS_ERR(fwl)) 1736 return dev_err_probe(dev, PTR_ERR(fwl), 1737 "failed to register to the Firmware Upload API\n"); 1738 priv->fwl = fwl; 1739 1740 return 0; 1741 } 1742 1743 static void pd692x0_i2c_remove(struct i2c_client *client) 1744 { 1745 struct pd692x0_priv *priv = i2c_get_clientdata(client); 1746 1747 firmware_upload_unregister(priv->fwl); 1748 } 1749 1750 static const struct i2c_device_id pd692x0_id[] = { 1751 { PD692X0_PSE_NAME }, 1752 { } 1753 }; 1754 MODULE_DEVICE_TABLE(i2c, pd692x0_id); 1755 1756 static const struct of_device_id pd692x0_of_match[] = { 1757 { .compatible = "microchip,pd69200", }, 1758 { .compatible = "microchip,pd69210", }, 1759 { .compatible = "microchip,pd69220", }, 1760 { }, 1761 }; 1762 MODULE_DEVICE_TABLE(of, pd692x0_of_match); 1763 1764 static struct i2c_driver pd692x0_driver = { 1765 .probe = pd692x0_i2c_probe, 1766 .remove = pd692x0_i2c_remove, 1767 .id_table = pd692x0_id, 1768 .driver = { 1769 .name = PD692X0_PSE_NAME, 1770 .of_match_table = pd692x0_of_match, 1771 }, 1772 }; 1773 module_i2c_driver(pd692x0_driver); 1774 1775 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>"); 1776 MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver"); 1777 MODULE_LICENSE("GPL"); 1778