1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 #include <net/phy/realtek_phy.h> 21 22 #include "../phylib.h" 23 #include "realtek.h" 24 25 #define RTL8201F_IER_PAGE 0x07 26 #define RTL8201F_IER 0x13 27 #define RTL8201F_IER_LINK BIT(13) 28 #define RTL8201F_IER_DUPLEX BIT(12) 29 #define RTL8201F_IER_ANERR BIT(11) 30 #define RTL8201F_IER_MASK (RTL8201F_IER_ANERR | \ 31 RTL8201F_IER_DUPLEX | \ 32 RTL8201F_IER_LINK) 33 34 #define RTL8201F_ISR 0x1e 35 #define RTL8201F_ISR_ANERR BIT(15) 36 #define RTL8201F_ISR_DUPLEX BIT(13) 37 #define RTL8201F_ISR_LINK BIT(11) 38 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 39 RTL8201F_ISR_DUPLEX | \ 40 RTL8201F_ISR_LINK) 41 42 #define RTL821x_INER 0x12 43 #define RTL8211B_INER_INIT 0x6400 44 #define RTL8211E_INER_LINK_STATUS BIT(10) 45 #define RTL8211F_INER_PME BIT(7) 46 #define RTL8211F_INER_LINK_STATUS BIT(4) 47 48 #define RTL821x_INSR 0x13 49 50 #define RTL821x_EXT_PAGE_SELECT 0x1e 51 52 #define RTL821x_PAGE_SELECT 0x1f 53 #define RTL821x_SET_EXT_PAGE 0x07 54 55 /* RTL8211E extension page 44/0x2c */ 56 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 57 #define RTL8211E_LEDCR1 0x1a 58 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 59 #define RTL8211E_LEDCR1_MASK BIT(4) 60 #define RTL8211E_LEDCR1_SHIFT 1 61 62 #define RTL8211E_LEDCR2 0x1c 63 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 64 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 65 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 66 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 67 #define RTL8211E_LEDCR2_SHIFT 4 68 69 /* RTL8211E extension page 164/0xa4 */ 70 #define RTL8211E_RGMII_EXT_PAGE 0xa4 71 #define RTL8211E_RGMII_DELAY 0x1c 72 #define RTL8211E_CTRL_DELAY BIT(13) 73 #define RTL8211E_TX_DELAY BIT(12) 74 #define RTL8211E_RX_DELAY BIT(11) 75 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 76 77 /* RTL8211F PHY configuration */ 78 #define RTL8211F_PHYCR1 0x18 79 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 80 #define RTL8211F_ALDPS_ENABLE BIT(2) 81 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 82 83 #define RTL8211F_PHYCR2 0x19 84 #define RTL8211F_CLKOUT_EN BIT(0) 85 #define RTL8211F_SYSCLK_SSC_EN BIT(3) 86 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 87 #define RTL8211F_CLKOUT_SSC_EN BIT(7) 88 #define RTL8211F_CLKOUT_SSC_CAP GENMASK(13, 12) 89 90 #define RTL8211F_INSR 0x1d 91 92 /* RTL8211F SSC settings */ 93 #define RTL8211F_SSC_PAGE 0xc44 94 #define RTL8211F_SSC_RXC 0x13 95 #define RTL8211F_SSC_SYSCLK 0x17 96 97 /* RTL8211F LED configuration */ 98 #define RTL8211F_LEDCR_PAGE 0xd04 99 #define RTL8211F_LEDCR 0x10 100 #define RTL8211F_LEDCR_MODE BIT(15) 101 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 102 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 103 #define RTL8211F_LEDCR_LINK_100 BIT(1) 104 #define RTL8211F_LEDCR_LINK_10 BIT(0) 105 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 106 #define RTL8211F_LEDCR_SHIFT 5 107 108 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 109 * to undocumented register pages. The names here do not reflect the datasheet. 110 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 111 */ 112 #define RTL8211FVD_CLKOUT_PAGE 0xd05 113 #define RTL8211FVD_CLKOUT_REG 0x11 114 #define RTL8211FVD_CLKOUT_EN BIT(8) 115 116 /* RTL8211F RGMII configuration */ 117 #define RTL8211F_RGMII_PAGE 0xd08 118 119 #define RTL8211F_TXCR 0x11 120 #define RTL8211F_TX_DELAY BIT(8) 121 122 #define RTL8211F_RXCR 0x15 123 #define RTL8211F_RX_DELAY BIT(3) 124 125 /* RTL8211F WOL settings */ 126 #define RTL8211F_WOL_PAGE 0xd8a 127 #define RTL8211F_WOL_SETTINGS_EVENTS 16 128 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 129 #define RTL8211F_WOL_RST_RMSQ 17 130 #define RTL8211F_WOL_RG_RSTB BIT(15) 131 #define RTL8211F_WOL_RMSQ 0x1fff 132 133 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 134 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 135 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 136 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 137 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 138 139 #define RTL822X_VND1_SERDES_OPTION 0x697a 140 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 141 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 142 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 143 144 #define RTL822X_VND1_SERDES_CTRL3 0x7580 145 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 146 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 147 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 148 149 #define RTL822X_VND1_SERDES_CMD 0x7587 150 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 151 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 152 #define RTL822X_VND1_SERDES_ADDR 0x7588 153 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 154 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 155 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 156 #define RTL822X_VND1_SERDES_DATA 0x7589 157 158 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 159 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 160 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 161 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 162 163 #define RTL8221B_VND2_INER 0xa4d2 164 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 165 166 #define RTL8221B_VND2_INSR 0xa4d4 167 168 #define RTL8224_MII_RTCT 0x11 169 #define RTL8224_MII_RTCT_ENABLE BIT(0) 170 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 171 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 172 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 173 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 174 #define RTL8224_MII_RTCT_DONE BIT(15) 175 176 #define RTL8224_MII_SRAM_ADDR 0x1b 177 #define RTL8224_MII_SRAM_DATA 0x1c 178 179 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 180 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 181 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 182 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 183 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 184 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 185 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 186 187 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 188 189 #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 190 #define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 191 192 #define RTL8366RB_POWER_SAVE 0x15 193 #define RTL8366RB_POWER_SAVE_ON BIT(12) 194 195 #define RTL9000A_GINMR 0x14 196 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 197 198 #define RTL_PHYSR MII_RESV2 199 #define RTL_PHYSR_DUPLEX BIT(3) 200 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 201 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 202 #define RTL_PHYSR_MASTER BIT(11) 203 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 204 205 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 206 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 207 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 208 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 209 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 210 #define RTL_MDIO_PMA_SPEED 0xa616 211 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 212 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 213 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 214 215 #define RTL_GENERIC_PHYID 0x001cc800 216 #define RTL_8211FVD_PHYID 0x001cc878 217 #define RTL_8221B 0x001cc840 218 #define RTL_8221B_VB_CG 0x001cc849 219 #define RTL_8221B_VM_CG 0x001cc84a 220 #define RTL_8251B 0x001cc862 221 #define RTL_8261C 0x001cc890 222 223 /* RTL8211E and RTL8211F support up to three LEDs */ 224 #define RTL8211x_LED_COUNT 3 225 226 MODULE_DESCRIPTION("Realtek PHY driver"); 227 MODULE_AUTHOR("Johnson Leung"); 228 MODULE_LICENSE("GPL"); 229 230 struct rtl821x_priv { 231 bool enable_aldps; 232 bool disable_clk_out; 233 bool enable_clkout_ssc; 234 bool enable_rxc_ssc; 235 bool enable_sysclk_ssc; 236 struct clk *clk; 237 /* rtl8211f */ 238 u16 iner; 239 }; 240 241 static int rtl821x_read_page(struct phy_device *phydev) 242 { 243 return __phy_read(phydev, RTL821x_PAGE_SELECT); 244 } 245 246 static int rtl821x_write_page(struct phy_device *phydev, int page) 247 { 248 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 249 } 250 251 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 252 u32 regnum) 253 { 254 int oldpage, ret = 0; 255 256 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 257 if (oldpage >= 0) { 258 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 259 if (ret == 0) 260 ret = __phy_read(phydev, regnum); 261 } 262 263 return phy_restore_page(phydev, oldpage, ret); 264 } 265 266 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 267 u32 regnum, u16 mask, u16 set) 268 { 269 int oldpage, ret = 0; 270 271 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 272 if (oldpage >= 0) { 273 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 274 if (ret == 0) 275 ret = __phy_modify(phydev, regnum, mask, set); 276 } 277 278 return phy_restore_page(phydev, oldpage, ret); 279 } 280 281 static int rtl821x_probe(struct phy_device *phydev) 282 { 283 struct device *dev = &phydev->mdio.dev; 284 struct rtl821x_priv *priv; 285 286 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 287 if (!priv) 288 return -ENOMEM; 289 290 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 291 if (IS_ERR(priv->clk)) 292 return dev_err_probe(dev, PTR_ERR(priv->clk), 293 "failed to get phy clock\n"); 294 295 priv->enable_aldps = of_property_read_bool(dev->of_node, 296 "realtek,aldps-enable"); 297 priv->disable_clk_out = of_property_read_bool(dev->of_node, 298 "realtek,clkout-disable"); 299 priv->enable_clkout_ssc = of_property_read_bool(dev->of_node, 300 "realtek,clkout-ssc-enable"); 301 priv->enable_rxc_ssc = of_property_read_bool(dev->of_node, 302 "realtek,rxc-ssc-enable"); 303 priv->enable_sysclk_ssc = of_property_read_bool(dev->of_node, 304 "realtek,sysclk-ssc-enable"); 305 306 phydev->priv = priv; 307 308 return 0; 309 } 310 311 static int rtl8211f_probe(struct phy_device *phydev) 312 { 313 struct device *dev = &phydev->mdio.dev; 314 int ret; 315 316 ret = rtl821x_probe(phydev); 317 if (ret < 0) 318 return ret; 319 320 /* Disable all PME events */ 321 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 322 RTL8211F_WOL_SETTINGS_EVENTS, 0); 323 if (ret < 0) 324 return ret; 325 326 /* Mark this PHY as wakeup capable and register the interrupt as a 327 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 328 * and the interrupt is valid. 329 */ 330 if (device_property_read_bool(dev, "wakeup-source") && 331 phy_interrupt_is_valid(phydev)) { 332 device_set_wakeup_capable(dev, true); 333 devm_pm_set_wake_irq(dev, phydev->irq); 334 } 335 336 return ret; 337 } 338 339 static int rtl8201_ack_interrupt(struct phy_device *phydev) 340 { 341 int err; 342 343 err = phy_read(phydev, RTL8201F_ISR); 344 345 return (err < 0) ? err : 0; 346 } 347 348 static int rtl821x_ack_interrupt(struct phy_device *phydev) 349 { 350 int err; 351 352 err = phy_read(phydev, RTL821x_INSR); 353 354 return (err < 0) ? err : 0; 355 } 356 357 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 358 { 359 int err; 360 361 err = phy_read(phydev, RTL8211F_INSR); 362 363 return (err < 0) ? err : 0; 364 } 365 366 static int rtl8201_config_intr(struct phy_device *phydev) 367 { 368 u16 val; 369 int err; 370 371 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 372 err = rtl8201_ack_interrupt(phydev); 373 if (err) 374 return err; 375 376 val = RTL8201F_IER_MASK; 377 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 378 RTL8201F_IER, val); 379 } else { 380 val = 0; 381 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 382 RTL8201F_IER, val); 383 if (err) 384 return err; 385 386 err = rtl8201_ack_interrupt(phydev); 387 } 388 389 return err; 390 } 391 392 static int rtl8211b_config_intr(struct phy_device *phydev) 393 { 394 int err; 395 396 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 397 err = rtl821x_ack_interrupt(phydev); 398 if (err) 399 return err; 400 401 err = phy_write(phydev, RTL821x_INER, 402 RTL8211B_INER_INIT); 403 } else { 404 err = phy_write(phydev, RTL821x_INER, 0); 405 if (err) 406 return err; 407 408 err = rtl821x_ack_interrupt(phydev); 409 } 410 411 return err; 412 } 413 414 static int rtl8211e_config_intr(struct phy_device *phydev) 415 { 416 int err; 417 418 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 419 err = rtl821x_ack_interrupt(phydev); 420 if (err) 421 return err; 422 423 err = phy_write(phydev, RTL821x_INER, 424 RTL8211E_INER_LINK_STATUS); 425 } else { 426 err = phy_write(phydev, RTL821x_INER, 0); 427 if (err) 428 return err; 429 430 err = rtl821x_ack_interrupt(phydev); 431 } 432 433 return err; 434 } 435 436 static int rtl8211f_config_intr(struct phy_device *phydev) 437 { 438 struct rtl821x_priv *priv = phydev->priv; 439 u16 val; 440 int err; 441 442 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 443 err = rtl8211f_ack_interrupt(phydev); 444 if (err) 445 return err; 446 447 val = RTL8211F_INER_LINK_STATUS; 448 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 449 if (err == 0) 450 priv->iner = val; 451 } else { 452 priv->iner = val = 0; 453 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 454 if (err) 455 return err; 456 457 err = rtl8211f_ack_interrupt(phydev); 458 } 459 460 return err; 461 } 462 463 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 464 { 465 int irq_status; 466 467 irq_status = phy_read(phydev, RTL8201F_ISR); 468 if (irq_status < 0) { 469 phy_error(phydev); 470 return IRQ_NONE; 471 } 472 473 if (!(irq_status & RTL8201F_ISR_MASK)) 474 return IRQ_NONE; 475 476 phy_trigger_machine(phydev); 477 478 return IRQ_HANDLED; 479 } 480 481 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 482 { 483 int irq_status, irq_enabled; 484 485 irq_status = phy_read(phydev, RTL821x_INSR); 486 if (irq_status < 0) { 487 phy_error(phydev); 488 return IRQ_NONE; 489 } 490 491 irq_enabled = phy_read(phydev, RTL821x_INER); 492 if (irq_enabled < 0) { 493 phy_error(phydev); 494 return IRQ_NONE; 495 } 496 497 if (!(irq_status & irq_enabled)) 498 return IRQ_NONE; 499 500 phy_trigger_machine(phydev); 501 502 return IRQ_HANDLED; 503 } 504 505 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 506 { 507 int irq_status; 508 509 irq_status = phy_read(phydev, RTL8211F_INSR); 510 if (irq_status < 0) { 511 phy_error(phydev); 512 return IRQ_NONE; 513 } 514 515 if (irq_status & RTL8211F_INER_LINK_STATUS) { 516 phy_trigger_machine(phydev); 517 return IRQ_HANDLED; 518 } 519 520 if (irq_status & RTL8211F_INER_PME) { 521 pm_wakeup_event(&phydev->mdio.dev, 0); 522 return IRQ_HANDLED; 523 } 524 525 return IRQ_NONE; 526 } 527 528 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 529 { 530 int wol_events; 531 532 /* If the PHY is not capable of waking the system, then WoL can not 533 * be supported. 534 */ 535 if (!device_can_wakeup(&dev->mdio.dev)) { 536 wol->supported = 0; 537 return; 538 } 539 540 wol->supported = WAKE_MAGIC; 541 542 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 543 if (wol_events < 0) 544 return; 545 546 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 547 wol->wolopts = WAKE_MAGIC; 548 } 549 550 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 551 { 552 const u8 *mac_addr = dev->attached_dev->dev_addr; 553 int oldpage; 554 555 if (!device_can_wakeup(&dev->mdio.dev)) 556 return -EOPNOTSUPP; 557 558 oldpage = phy_save_page(dev); 559 if (oldpage < 0) 560 goto err; 561 562 if (wol->wolopts & WAKE_MAGIC) { 563 /* Store the device address for the magic packet */ 564 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 565 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 566 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 567 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 568 569 /* Enable magic packet matching */ 570 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 571 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 572 /* Set the maximum packet size, and assert WoL reset */ 573 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 574 } else { 575 /* Disable magic packet matching */ 576 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 577 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 578 579 /* Place WoL in reset */ 580 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 581 RTL8211F_WOL_RG_RSTB); 582 } 583 584 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 585 586 err: 587 return phy_restore_page(dev, oldpage, 0); 588 } 589 590 static int rtl8211_config_aneg(struct phy_device *phydev) 591 { 592 int ret; 593 594 ret = genphy_config_aneg(phydev); 595 if (ret < 0) 596 return ret; 597 598 /* Quirk was copied from vendor driver. Unfortunately it includes no 599 * description of the magic numbers. 600 */ 601 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 602 phy_write(phydev, 0x17, 0x2138); 603 phy_write(phydev, 0x0e, 0x0260); 604 } else { 605 phy_write(phydev, 0x17, 0x2108); 606 phy_write(phydev, 0x0e, 0x0000); 607 } 608 609 return 0; 610 } 611 612 static int rtl8211c_config_init(struct phy_device *phydev) 613 { 614 /* RTL8211C has an issue when operating in Gigabit slave mode */ 615 return phy_set_bits(phydev, MII_CTRL1000, 616 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 617 } 618 619 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 620 { 621 u16 val_txdly, val_rxdly; 622 int ret; 623 624 switch (phydev->interface) { 625 case PHY_INTERFACE_MODE_RGMII: 626 val_txdly = 0; 627 val_rxdly = 0; 628 break; 629 630 case PHY_INTERFACE_MODE_RGMII_RXID: 631 val_txdly = 0; 632 val_rxdly = RTL8211F_RX_DELAY; 633 break; 634 635 case PHY_INTERFACE_MODE_RGMII_TXID: 636 val_txdly = RTL8211F_TX_DELAY; 637 val_rxdly = 0; 638 break; 639 640 case PHY_INTERFACE_MODE_RGMII_ID: 641 val_txdly = RTL8211F_TX_DELAY; 642 val_rxdly = RTL8211F_RX_DELAY; 643 break; 644 645 default: /* the rest of the modes imply leaving delay as is. */ 646 return 0; 647 } 648 649 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 650 RTL8211F_TXCR, RTL8211F_TX_DELAY, 651 val_txdly); 652 if (ret < 0) { 653 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 654 ERR_PTR(ret)); 655 return ret; 656 } else if (ret) { 657 phydev_dbg(phydev, 658 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 659 str_enable_disable(val_txdly)); 660 } else { 661 phydev_dbg(phydev, 662 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 663 str_enabled_disabled(val_txdly)); 664 } 665 666 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 667 RTL8211F_RXCR, RTL8211F_RX_DELAY, 668 val_rxdly); 669 if (ret < 0) { 670 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 671 ERR_PTR(ret)); 672 return ret; 673 } else if (ret) { 674 phydev_dbg(phydev, 675 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 676 str_enable_disable(val_rxdly)); 677 } else { 678 phydev_dbg(phydev, 679 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 680 str_enabled_disabled(val_rxdly)); 681 } 682 683 return 0; 684 } 685 686 static int rtl8211f_config_clk_out(struct phy_device *phydev) 687 { 688 struct rtl821x_priv *priv = phydev->priv; 689 int ret; 690 691 /* The value is preserved if the device tree property is absent */ 692 if (!priv->disable_clk_out) 693 return 0; 694 695 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 696 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 697 RTL8211FVD_CLKOUT_REG, 698 RTL8211FVD_CLKOUT_EN, 0); 699 else 700 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 701 0); 702 if (ret) 703 return ret; 704 705 return genphy_soft_reset(phydev); 706 } 707 708 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 709 * which causes the RXC clock signal to stop for tens to hundreds of 710 * milliseconds. 711 * 712 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 713 * only enabled based on an opt-in device tree property. 714 */ 715 static int rtl8211f_config_aldps(struct phy_device *phydev) 716 { 717 struct rtl821x_priv *priv = phydev->priv; 718 u16 mask = RTL8211F_ALDPS_PLL_OFF | 719 RTL8211F_ALDPS_ENABLE | 720 RTL8211F_ALDPS_XTAL_OFF; 721 722 /* The value is preserved if the device tree property is absent */ 723 if (!priv->enable_aldps) 724 return 0; 725 726 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 727 } 728 729 static int rtl8211f_disable_autonomous_eee(struct phy_device *phydev) 730 { 731 return phy_modify(phydev, RTL8211F_PHYCR2, 732 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 733 } 734 735 static int rtl8211f_config_clkout_ssc(struct phy_device *phydev) 736 { 737 struct rtl821x_priv *priv = phydev->priv; 738 struct device *dev = &phydev->mdio.dev; 739 int ret; 740 741 /* The value is preserved if the device tree property is absent */ 742 if (!priv->enable_clkout_ssc) 743 return 0; 744 745 /* RTL8211FVD has PHYCR2 register, but configuration of CLKOUT SSC 746 * is not currently supported by this driver due to different bit 747 * layout. 748 */ 749 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 750 return 0; 751 752 /* Unnamed registers from EMI improvement parameters application note 1.2 */ 753 ret = phy_write_paged(phydev, 0xd09, 0x10, 0xcf00); 754 if (ret < 0) { 755 dev_err(dev, "CLKOUT SSC initialization failed: %pe\n", ERR_PTR(ret)); 756 return ret; 757 } 758 759 /* Enable CLKOUT SSC and CLKOUT SSC Capability using PHYCR2 760 * bits 7, 12, 13. This matches the register 25 write 0x38C3 761 * from the EMI improvement parameters application note 1.2 762 * section 2.3, without affecting unrelated bits. 763 */ 764 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, 765 RTL8211F_CLKOUT_SSC_CAP | RTL8211F_CLKOUT_SSC_EN); 766 if (ret < 0) { 767 dev_err(dev, "CLKOUT SSC enable failed: %pe\n", ERR_PTR(ret)); 768 return ret; 769 } 770 771 return 0; 772 } 773 774 static int rtl8211f_config_rxc_ssc(struct phy_device *phydev) 775 { 776 struct rtl821x_priv *priv = phydev->priv; 777 struct device *dev = &phydev->mdio.dev; 778 int ret; 779 780 /* The value is preserved if the device tree property is absent */ 781 if (!priv->enable_rxc_ssc) 782 return 0; 783 784 /* RTL8211FVD has PHYCR2 register, but configuration of RXC SSC 785 * is not currently supported by this driver due to different bit 786 * layout. 787 */ 788 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 789 return 0; 790 791 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_RXC, 0x5f00); 792 if (ret < 0) { 793 dev_err(dev, "RXC SSC configuration failed: %pe\n", ERR_PTR(ret)); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static int rtl8211f_config_sysclk_ssc(struct phy_device *phydev) 801 { 802 struct rtl821x_priv *priv = phydev->priv; 803 struct device *dev = &phydev->mdio.dev; 804 int ret; 805 806 /* The value is preserved if the device tree property is absent */ 807 if (!priv->enable_sysclk_ssc) 808 return 0; 809 810 /* RTL8211FVD has PHYCR2 register, but configuration of SYSCLK SSC 811 * is not currently supported by this driver due to different bit 812 * layout. 813 */ 814 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 815 return 0; 816 817 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_SYSCLK, 0x4f00); 818 if (ret < 0) { 819 dev_err(dev, "SYSCLK SSC configuration failed: %pe\n", ERR_PTR(ret)); 820 return ret; 821 } 822 823 /* Enable SSC */ 824 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, RTL8211F_SYSCLK_SSC_EN); 825 if (ret < 0) { 826 dev_err(dev, "SYSCLK SSC enable failed: %pe\n", ERR_PTR(ret)); 827 return ret; 828 } 829 830 return 0; 831 } 832 833 static int rtl8211f_config_init(struct phy_device *phydev) 834 { 835 struct device *dev = &phydev->mdio.dev; 836 int ret; 837 838 ret = rtl8211f_config_aldps(phydev); 839 if (ret) { 840 dev_err(dev, "aldps mode configuration failed: %pe\n", 841 ERR_PTR(ret)); 842 return ret; 843 } 844 845 ret = rtl8211f_config_rgmii_delay(phydev); 846 if (ret) 847 return ret; 848 849 ret = rtl8211f_config_rxc_ssc(phydev); 850 if (ret) 851 return ret; 852 853 ret = rtl8211f_config_sysclk_ssc(phydev); 854 if (ret) 855 return ret; 856 857 ret = rtl8211f_config_clkout_ssc(phydev); 858 if (ret) 859 return ret; 860 861 ret = rtl8211f_config_clk_out(phydev); 862 if (ret) { 863 dev_err(dev, "clkout configuration failed: %pe\n", 864 ERR_PTR(ret)); 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static int rtl821x_suspend(struct phy_device *phydev) 872 { 873 struct rtl821x_priv *priv = phydev->priv; 874 int ret = 0; 875 876 if (!phydev->wol_enabled) { 877 ret = genphy_suspend(phydev); 878 879 if (ret) 880 return ret; 881 882 clk_disable_unprepare(priv->clk); 883 } 884 885 return ret; 886 } 887 888 static int rtl8211f_suspend(struct phy_device *phydev) 889 { 890 u16 wol_rst; 891 int ret; 892 893 ret = rtl821x_suspend(phydev); 894 if (ret < 0) 895 return ret; 896 897 /* If a PME event is enabled, then configure the interrupt for 898 * PME events only, disabling link interrupt. We avoid switching 899 * to PMEB mode as we don't have a status bit for that. 900 */ 901 if (device_may_wakeup(&phydev->mdio.dev)) { 902 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 903 RTL8211F_INER_PME); 904 if (ret < 0) 905 goto err; 906 907 /* Read the INSR to clear any pending interrupt */ 908 phy_read(phydev, RTL8211F_INSR); 909 910 /* Reset the WoL to ensure that an event is picked up. 911 * Unless we do this, even if we receive another packet, 912 * we may not have a PME interrupt raised. 913 */ 914 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 915 RTL8211F_WOL_RST_RMSQ); 916 if (ret < 0) 917 goto err; 918 919 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 920 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 921 RTL8211F_WOL_RST_RMSQ, wol_rst); 922 if (ret < 0) 923 goto err; 924 925 wol_rst |= RTL8211F_WOL_RG_RSTB; 926 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 927 RTL8211F_WOL_RST_RMSQ, wol_rst); 928 } 929 930 err: 931 return ret; 932 } 933 934 static int rtl821x_resume(struct phy_device *phydev) 935 { 936 struct rtl821x_priv *priv = phydev->priv; 937 int ret; 938 939 if (!phydev->wol_enabled) 940 clk_prepare_enable(priv->clk); 941 942 ret = genphy_resume(phydev); 943 if (ret < 0) 944 return ret; 945 946 msleep(20); 947 948 return 0; 949 } 950 951 static int rtl8211f_resume(struct phy_device *phydev) 952 { 953 struct rtl821x_priv *priv = phydev->priv; 954 int ret; 955 956 ret = rtl821x_resume(phydev); 957 if (ret < 0) 958 return ret; 959 960 /* If the device was programmed for a PME event, restore the interrupt 961 * enable so phylib can receive link state interrupts. 962 */ 963 if (device_may_wakeup(&phydev->mdio.dev)) 964 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 965 966 return ret; 967 } 968 969 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 970 unsigned long rules) 971 { 972 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 973 BIT(TRIGGER_NETDEV_LINK_10) | 974 BIT(TRIGGER_NETDEV_LINK_100) | 975 BIT(TRIGGER_NETDEV_LINK_1000) | 976 BIT(TRIGGER_NETDEV_RX) | 977 BIT(TRIGGER_NETDEV_TX); 978 979 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 980 * - Link: Configurable subset of 10/100/1000 link rates 981 * - Active: Blink on activity, RX or TX is not differentiated 982 * The Active option has two modes, A and B: 983 * - A: Link and Active indication at configurable, but matching, 984 * subset of 10/100/1000 link rates 985 * - B: Link indication at configurable subset of 10/100/1000 link 986 * rates and Active indication always at all three 10+100+1000 987 * link rates. 988 * This code currently uses mode B only. 989 * 990 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 991 */ 992 993 if (index >= RTL8211x_LED_COUNT) 994 return -EINVAL; 995 996 /* Filter out any other unsupported triggers. */ 997 if (rules & ~mask) 998 return -EOPNOTSUPP; 999 1000 /* RX and TX are not differentiated, either both are set or not set. */ 1001 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 1002 return -EOPNOTSUPP; 1003 1004 return 0; 1005 } 1006 1007 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 1008 unsigned long *rules) 1009 { 1010 int val; 1011 1012 if (index >= RTL8211x_LED_COUNT) 1013 return -EINVAL; 1014 1015 val = phy_read_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR); 1016 if (val < 0) 1017 return val; 1018 1019 val >>= RTL8211F_LEDCR_SHIFT * index; 1020 val &= RTL8211F_LEDCR_MASK; 1021 1022 if (val & RTL8211F_LEDCR_LINK_10) 1023 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1024 1025 if (val & RTL8211F_LEDCR_LINK_100) 1026 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1027 1028 if (val & RTL8211F_LEDCR_LINK_1000) 1029 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1030 1031 if ((val & RTL8211F_LEDCR_LINK_10) && 1032 (val & RTL8211F_LEDCR_LINK_100) && 1033 (val & RTL8211F_LEDCR_LINK_1000)) { 1034 __set_bit(TRIGGER_NETDEV_LINK, rules); 1035 } 1036 1037 if (val & RTL8211F_LEDCR_ACT_TXRX) { 1038 __set_bit(TRIGGER_NETDEV_RX, rules); 1039 __set_bit(TRIGGER_NETDEV_TX, rules); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 1046 unsigned long rules) 1047 { 1048 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 1049 u16 reg = 0; 1050 1051 if (index >= RTL8211x_LED_COUNT) 1052 return -EINVAL; 1053 1054 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1055 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1056 reg |= RTL8211F_LEDCR_LINK_10; 1057 } 1058 1059 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1060 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1061 reg |= RTL8211F_LEDCR_LINK_100; 1062 } 1063 1064 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1065 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1066 reg |= RTL8211F_LEDCR_LINK_1000; 1067 } 1068 1069 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1070 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1071 reg |= RTL8211F_LEDCR_ACT_TXRX; 1072 } 1073 1074 reg <<= RTL8211F_LEDCR_SHIFT * index; 1075 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 1076 1077 return phy_modify_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR, 1078 mask, reg); 1079 } 1080 1081 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 1082 unsigned long *rules) 1083 { 1084 int ret; 1085 u16 cr1, cr2; 1086 1087 if (index >= RTL8211x_LED_COUNT) 1088 return -EINVAL; 1089 1090 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1091 RTL8211E_LEDCR1); 1092 if (ret < 0) 1093 return ret; 1094 1095 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 1096 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 1097 __set_bit(TRIGGER_NETDEV_RX, rules); 1098 __set_bit(TRIGGER_NETDEV_TX, rules); 1099 } 1100 1101 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1102 RTL8211E_LEDCR2); 1103 if (ret < 0) 1104 return ret; 1105 1106 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 1107 if (cr2 & RTL8211E_LEDCR2_LINK_10) 1108 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1109 1110 if (cr2 & RTL8211E_LEDCR2_LINK_100) 1111 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1112 1113 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 1114 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1115 1116 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 1117 (cr2 & RTL8211E_LEDCR2_LINK_100) && 1118 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 1119 __set_bit(TRIGGER_NETDEV_LINK, rules); 1120 } 1121 1122 return ret; 1123 } 1124 1125 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 1126 unsigned long rules) 1127 { 1128 const u16 cr1mask = 1129 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 1130 const u16 cr2mask = 1131 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 1132 u16 cr1 = 0, cr2 = 0; 1133 int ret; 1134 1135 if (index >= RTL8211x_LED_COUNT) 1136 return -EINVAL; 1137 1138 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1139 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1140 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1141 } 1142 1143 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1144 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1145 RTL8211E_LEDCR1, cr1mask, cr1); 1146 if (ret < 0) 1147 return ret; 1148 1149 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1150 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1151 cr2 |= RTL8211E_LEDCR2_LINK_10; 1152 } 1153 1154 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1155 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1156 cr2 |= RTL8211E_LEDCR2_LINK_100; 1157 } 1158 1159 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1160 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1161 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1162 } 1163 1164 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1165 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1166 RTL8211E_LEDCR2, cr2mask, cr2); 1167 1168 return ret; 1169 } 1170 1171 static int rtl8211e_config_init(struct phy_device *phydev) 1172 { 1173 u16 val; 1174 1175 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1176 switch (phydev->interface) { 1177 case PHY_INTERFACE_MODE_RGMII: 1178 val = RTL8211E_CTRL_DELAY | 0; 1179 break; 1180 case PHY_INTERFACE_MODE_RGMII_ID: 1181 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1182 break; 1183 case PHY_INTERFACE_MODE_RGMII_RXID: 1184 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1185 break; 1186 case PHY_INTERFACE_MODE_RGMII_TXID: 1187 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1188 break; 1189 default: /* the rest of the modes imply leaving delays as is. */ 1190 return 0; 1191 } 1192 1193 /* According to a sample driver there is a 0x1c config register on the 1194 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1195 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1196 * The configuration register definition: 1197 * 14 = reserved 1198 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1199 * 12 = RX Delay, 11 = TX Delay 1200 * 10:0 = Test && debug settings reserved by realtek 1201 */ 1202 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1203 RTL8211E_RGMII_DELAY, 1204 RTL8211E_DELAY_MASK, val); 1205 } 1206 1207 static int rtl8211b_suspend(struct phy_device *phydev) 1208 { 1209 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1210 1211 return genphy_suspend(phydev); 1212 } 1213 1214 static int rtl8211b_resume(struct phy_device *phydev) 1215 { 1216 phy_write(phydev, MII_MMD_DATA, 0); 1217 1218 return genphy_resume(phydev); 1219 } 1220 1221 static int rtl8366rb_config_init(struct phy_device *phydev) 1222 { 1223 int ret; 1224 1225 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1226 RTL8366RB_POWER_SAVE_ON); 1227 if (ret) { 1228 dev_err(&phydev->mdio.dev, 1229 "error enabling power management\n"); 1230 } 1231 1232 return ret; 1233 } 1234 1235 /* get actual speed to cover the downshift case */ 1236 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1237 { 1238 /* bit 3 1239 * 0: Half Duplex 1240 * 1: Full Duplex 1241 */ 1242 if (val & RTL_PHYSR_DUPLEX) 1243 phydev->duplex = DUPLEX_FULL; 1244 else 1245 phydev->duplex = DUPLEX_HALF; 1246 1247 switch (val & RTL_PHYSR_SPEED_MASK) { 1248 case 0x0000: 1249 phydev->speed = SPEED_10; 1250 break; 1251 case 0x0010: 1252 phydev->speed = SPEED_100; 1253 break; 1254 case 0x0020: 1255 phydev->speed = SPEED_1000; 1256 break; 1257 case 0x0200: 1258 phydev->speed = SPEED_10000; 1259 break; 1260 case 0x0210: 1261 phydev->speed = SPEED_2500; 1262 break; 1263 case 0x0220: 1264 phydev->speed = SPEED_5000; 1265 break; 1266 default: 1267 break; 1268 } 1269 1270 /* bit 11 1271 * 0: Slave Mode 1272 * 1: Master Mode 1273 */ 1274 if (phydev->speed >= 1000) { 1275 if (val & RTL_PHYSR_MASTER) 1276 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1277 else 1278 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1279 } else { 1280 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1281 } 1282 } 1283 1284 static int rtlgen_read_status(struct phy_device *phydev) 1285 { 1286 int ret, val; 1287 1288 ret = genphy_read_status(phydev); 1289 if (ret < 0) 1290 return ret; 1291 1292 if (!phydev->link) 1293 return 0; 1294 1295 val = phy_read(phydev, RTL_PHYSR); 1296 if (val < 0) 1297 return val; 1298 1299 rtlgen_decode_physr(phydev, val); 1300 1301 return 0; 1302 } 1303 1304 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1305 { 1306 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1307 } 1308 1309 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1310 { 1311 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1312 val); 1313 } 1314 1315 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1316 { 1317 int ret; 1318 1319 if (devnum == MDIO_MMD_VEND2) 1320 ret = rtlgen_read_vend2(phydev, regnum); 1321 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1322 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1323 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1324 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1325 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1326 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1327 else 1328 ret = -EOPNOTSUPP; 1329 1330 return ret; 1331 } 1332 1333 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1334 u16 val) 1335 { 1336 int ret; 1337 1338 if (devnum == MDIO_MMD_VEND2) 1339 ret = rtlgen_write_vend2(phydev, regnum, val); 1340 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1341 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1342 else 1343 ret = -EOPNOTSUPP; 1344 1345 return ret; 1346 } 1347 1348 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1349 { 1350 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1351 1352 if (ret != -EOPNOTSUPP) 1353 return ret; 1354 1355 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1356 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1357 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1358 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1359 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1360 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1361 1362 return ret; 1363 } 1364 1365 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1366 u16 val) 1367 { 1368 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1369 1370 if (ret != -EOPNOTSUPP) 1371 return ret; 1372 1373 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1374 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1375 1376 return ret; 1377 } 1378 1379 static int rtl822x_probe(struct phy_device *phydev) 1380 { 1381 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1382 phydev->phy_id != RTL_GENERIC_PHYID) 1383 return rtl822x_hwmon_init(phydev); 1384 1385 return 0; 1386 } 1387 1388 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1389 * A mapping to use paged access needs to be used instead. 1390 * All other MMD devices can be accessed as usual. 1391 */ 1392 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1393 { 1394 int oldpage, ret, read_ret; 1395 u16 page; 1396 1397 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1398 * Clause-45 access is available 1399 */ 1400 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1401 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1402 phydev->is_c45, devnum, reg); 1403 1404 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1405 if (reg >= RTL822X_VND2_C22_REG(0) && 1406 reg <= RTL822X_VND2_C22_REG(30)) 1407 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1408 1409 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1410 page = RTL822X_VND2_TO_PAGE(reg); 1411 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1412 if (oldpage < 0) 1413 return oldpage; 1414 1415 if (oldpage != page) { 1416 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1417 if (ret < 0) 1418 return ret; 1419 } 1420 1421 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1422 if (oldpage != page) { 1423 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1424 if (ret < 0) 1425 return ret; 1426 } 1427 1428 return read_ret; 1429 } 1430 1431 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1432 u16 val) 1433 { 1434 int oldpage, ret, write_ret; 1435 u16 page; 1436 1437 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1438 * Clause-45 access is available 1439 */ 1440 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1441 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1442 phydev->is_c45, devnum, reg, val); 1443 1444 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1445 if (reg >= RTL822X_VND2_C22_REG(0) && 1446 reg <= RTL822X_VND2_C22_REG(30)) 1447 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1448 1449 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1450 page = RTL822X_VND2_TO_PAGE(reg); 1451 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1452 if (oldpage < 0) 1453 return oldpage; 1454 1455 if (oldpage != page) { 1456 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1457 if (ret < 0) 1458 return ret; 1459 } 1460 1461 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1462 if (oldpage != page) { 1463 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1464 if (ret < 0) 1465 return ret; 1466 } 1467 1468 return write_ret; 1469 } 1470 1471 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1472 { 1473 bool has_2500, has_sgmii; 1474 u16 mode; 1475 int ret; 1476 1477 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1478 phydev->host_interfaces) || 1479 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1480 1481 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1482 phydev->host_interfaces) || 1483 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1484 1485 /* fill in possible interfaces */ 1486 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1487 has_2500); 1488 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1489 has_sgmii); 1490 1491 if (!has_2500 && !has_sgmii) 1492 return 0; 1493 1494 /* determine SerDes option mode */ 1495 if (has_2500 && !has_sgmii) { 1496 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1497 phydev->rate_matching = RATE_MATCH_PAUSE; 1498 } else { 1499 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1500 phydev->rate_matching = RATE_MATCH_NONE; 1501 } 1502 1503 /* the following sequence with magic numbers sets up the SerDes 1504 * option mode 1505 */ 1506 1507 if (!gen1) { 1508 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1509 if (ret < 0) 1510 return ret; 1511 } 1512 1513 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1514 RTL822X_VND1_SERDES_OPTION, 1515 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1516 mode); 1517 if (gen1 || ret < 0) 1518 return ret; 1519 1520 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1521 if (ret < 0) 1522 return ret; 1523 1524 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1525 if (ret < 0) 1526 return ret; 1527 1528 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1529 } 1530 1531 static int rtl822x_config_init(struct phy_device *phydev) 1532 { 1533 return rtl822x_set_serdes_option_mode(phydev, true); 1534 } 1535 1536 static int rtl822xb_config_init(struct phy_device *phydev) 1537 { 1538 return rtl822x_set_serdes_option_mode(phydev, false); 1539 } 1540 1541 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1542 { 1543 int ret, poll; 1544 1545 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1546 if (ret < 0) 1547 return ret; 1548 1549 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1550 if (ret < 0) 1551 return ret; 1552 1553 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1554 RTL822X_VND1_SERDES_CMD_WRITE | 1555 RTL822X_VND1_SERDES_CMD_BUSY); 1556 if (ret < 0) 1557 return ret; 1558 1559 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1560 RTL822X_VND1_SERDES_CMD, poll, 1561 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1562 500, 100000, false); 1563 } 1564 1565 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1566 { 1567 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1568 (modes != LINK_INBAND_DISABLE) ? 1569 RTL822X_VND1_SERDES_INBAND_ENABLE : 1570 RTL822X_VND1_SERDES_INBAND_DISABLE); 1571 } 1572 1573 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1574 phy_interface_t interface) 1575 { 1576 switch (interface) { 1577 case PHY_INTERFACE_MODE_2500BASEX: 1578 return LINK_INBAND_DISABLE; 1579 case PHY_INTERFACE_MODE_SGMII: 1580 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1581 default: 1582 return 0; 1583 } 1584 } 1585 1586 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1587 phy_interface_t iface) 1588 { 1589 int val; 1590 1591 /* Only rate matching at 2500base-x */ 1592 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1593 return RATE_MATCH_NONE; 1594 1595 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1596 if (val < 0) 1597 return val; 1598 1599 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1600 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1601 return RATE_MATCH_PAUSE; 1602 1603 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1604 return RATE_MATCH_NONE; 1605 } 1606 1607 static int rtl822x_get_features(struct phy_device *phydev) 1608 { 1609 int val; 1610 1611 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1612 if (val < 0) 1613 return val; 1614 1615 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1616 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1617 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1618 phydev->supported, val & MDIO_PMA_SPEED_5G); 1619 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1620 phydev->supported, val & MDIO_SPEED_10G); 1621 1622 return genphy_read_abilities(phydev); 1623 } 1624 1625 static int rtl822x_config_aneg(struct phy_device *phydev) 1626 { 1627 int ret = 0; 1628 1629 if (phydev->autoneg == AUTONEG_ENABLE) { 1630 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1631 1632 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1633 RTL_MDIO_AN_10GBT_CTRL, 1634 MDIO_AN_10GBT_CTRL_ADV2_5G | 1635 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1636 if (ret < 0) 1637 return ret; 1638 } 1639 1640 return __genphy_config_aneg(phydev, ret); 1641 } 1642 1643 static void rtl822xb_update_interface(struct phy_device *phydev) 1644 { 1645 int val; 1646 1647 if (!phydev->link) 1648 return; 1649 1650 /* Change interface according to serdes mode */ 1651 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1652 if (val < 0) 1653 return; 1654 1655 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1656 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1657 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1658 break; 1659 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1660 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1661 break; 1662 } 1663 } 1664 1665 static int rtl822x_read_status(struct phy_device *phydev) 1666 { 1667 int lpadv, ret; 1668 1669 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1670 1671 ret = rtlgen_read_status(phydev); 1672 if (ret < 0) 1673 return ret; 1674 1675 if (phydev->autoneg == AUTONEG_DISABLE || 1676 !phydev->autoneg_complete) 1677 return 0; 1678 1679 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1680 if (lpadv < 0) 1681 return lpadv; 1682 1683 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1684 1685 return 0; 1686 } 1687 1688 static int rtl822xb_read_status(struct phy_device *phydev) 1689 { 1690 int ret; 1691 1692 ret = rtl822x_read_status(phydev); 1693 if (ret < 0) 1694 return ret; 1695 1696 rtl822xb_update_interface(phydev); 1697 1698 return 0; 1699 } 1700 1701 static int rtl822x_c45_get_features(struct phy_device *phydev) 1702 { 1703 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1704 phydev->supported); 1705 1706 return genphy_c45_pma_read_abilities(phydev); 1707 } 1708 1709 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1710 { 1711 bool changed = false; 1712 int ret, val; 1713 1714 if (phydev->autoneg == AUTONEG_DISABLE) 1715 return genphy_c45_pma_setup_forced(phydev); 1716 1717 ret = genphy_c45_an_config_aneg(phydev); 1718 if (ret < 0) 1719 return ret; 1720 if (ret > 0) 1721 changed = true; 1722 1723 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1724 1725 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1726 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1727 RTL822X_VND2_C22_REG(MII_CTRL1000), 1728 ADVERTISE_1000FULL, val); 1729 if (ret < 0) 1730 return ret; 1731 if (ret > 0) 1732 changed = true; 1733 1734 return genphy_c45_check_and_restart_aneg(phydev, changed); 1735 } 1736 1737 static int rtl822x_c45_read_status(struct phy_device *phydev) 1738 { 1739 int ret, val; 1740 1741 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1742 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1743 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1744 RTL822X_VND2_C22_REG(MII_STAT1000)); 1745 if (val < 0) 1746 return val; 1747 } else { 1748 val = 0; 1749 } 1750 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1751 1752 ret = genphy_c45_read_status(phydev); 1753 if (ret < 0) 1754 return ret; 1755 1756 if (!phydev->link) { 1757 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1758 return 0; 1759 } 1760 1761 /* Read actual speed from vendor register. */ 1762 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1763 RTL822X_VND2_C22_REG(RTL_PHYSR)); 1764 if (val < 0) 1765 return val; 1766 1767 rtlgen_decode_physr(phydev, val); 1768 1769 return 0; 1770 } 1771 1772 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1773 { 1774 int ret, val; 1775 1776 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1777 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1778 if (ret < 0) 1779 return ret; 1780 1781 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1782 MDIO_CTRL1, val, 1783 !(val & MDIO_CTRL1_RESET), 1784 5000, 100000, true); 1785 } 1786 1787 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1788 { 1789 int ret; 1790 1791 ret = rtl822x_c45_read_status(phydev); 1792 if (ret < 0) 1793 return ret; 1794 1795 rtl822xb_update_interface(phydev); 1796 1797 return 0; 1798 } 1799 1800 static int rtl8224_cable_test_start(struct phy_device *phydev) 1801 { 1802 u32 val; 1803 int ret; 1804 1805 /* disable auto-negotiation and force 1000/Full */ 1806 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1807 RTL822X_VND2_C22_REG(MII_BMCR), 1808 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1809 BMCR_SPEED1000 | BMCR_FULLDPLX); 1810 if (ret) 1811 return ret; 1812 1813 mdelay(500); 1814 1815 /* trigger cable test */ 1816 val = RTL8224_MII_RTCT_ENABLE; 1817 val |= RTL8224_MII_RTCT_PAIR_A; 1818 val |= RTL8224_MII_RTCT_PAIR_B; 1819 val |= RTL8224_MII_RTCT_PAIR_C; 1820 val |= RTL8224_MII_RTCT_PAIR_D; 1821 1822 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1823 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1824 RTL8224_MII_RTCT_DONE, val); 1825 } 1826 1827 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1828 { 1829 int ret; 1830 1831 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1832 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1833 reg); 1834 if (ret) 1835 return ret; 1836 1837 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1838 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1839 } 1840 1841 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1842 { 1843 int cable_len; 1844 u32 reg_len; 1845 int ret; 1846 u32 cm; 1847 1848 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1849 1850 ret = rtl8224_sram_read(phydev, reg_len); 1851 if (ret < 0) 1852 return ret; 1853 1854 cable_len = ret & 0xff00; 1855 1856 ret = rtl8224_sram_read(phydev, reg_len + 1); 1857 if (ret < 0) 1858 return ret; 1859 1860 cable_len |= (ret & 0xff00) >> 8; 1861 1862 cable_len -= 620; 1863 cable_len = max(cable_len, 0); 1864 1865 cm = cable_len * 100 / 78; 1866 1867 return cm; 1868 } 1869 1870 static int rtl8224_cable_test_result_trans(u32 result) 1871 { 1872 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1873 return -EBUSY; 1874 1875 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1876 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1877 1878 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1879 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1880 1881 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1882 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1883 1884 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1885 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1886 1887 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1888 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1889 1890 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1891 } 1892 1893 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1894 { 1895 int fault_rslt; 1896 int ret; 1897 1898 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1899 if (ret < 0) 1900 return ret; 1901 1902 fault_rslt = rtl8224_cable_test_result_trans(ret); 1903 if (fault_rslt < 0) 1904 return 0; 1905 1906 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1907 if (ret < 0) 1908 return ret; 1909 1910 switch (fault_rslt) { 1911 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1912 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1913 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1914 ret = rtl8224_pair_len_get(phydev, pair); 1915 if (ret < 0) 1916 return ret; 1917 1918 return ethnl_cable_test_fault_length(phydev, pair, ret); 1919 default: 1920 return 0; 1921 } 1922 } 1923 1924 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1925 { 1926 unsigned int pair; 1927 int ret; 1928 1929 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1930 ret = rtl8224_cable_test_report_pair(phydev, pair); 1931 if (ret == -EBUSY) { 1932 *finished = false; 1933 return 0; 1934 } 1935 1936 if (ret < 0) 1937 return ret; 1938 } 1939 1940 return 0; 1941 } 1942 1943 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1944 { 1945 int ret; 1946 1947 *finished = false; 1948 1949 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1950 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1951 if (ret < 0) 1952 return ret; 1953 1954 if (!(ret & RTL8224_MII_RTCT_DONE)) 1955 return 0; 1956 1957 *finished = true; 1958 1959 return rtl8224_cable_test_report(phydev, finished); 1960 } 1961 1962 static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, 1963 u32 regnum, u16 mask, u16 set) 1964 { 1965 int val, ret; 1966 1967 phy_lock_mdio_bus(phydev); 1968 1969 val = __phy_package_read_mmd(phydev, 0, devad, regnum); 1970 if (val < 0) { 1971 ret = val; 1972 goto exit; 1973 } 1974 1975 val &= ~mask; 1976 val |= set; 1977 1978 ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); 1979 1980 exit: 1981 phy_unlock_mdio_bus(phydev); 1982 return ret; 1983 } 1984 1985 static int rtl8224_mdi_config_order(struct phy_device *phydev) 1986 { 1987 struct device_node *np = phydev->mdio.dev.of_node; 1988 u8 port_offset = phydev->mdio.addr & 3; 1989 u32 order = 0; 1990 int ret; 1991 1992 ret = of_property_read_u32(np, "enet-phy-pair-order", &order); 1993 1994 /* Do nothing in case the property is not present */ 1995 if (ret == -EINVAL || ret == -ENOSYS) 1996 return 0; 1997 1998 if (ret) 1999 return ret; 2000 2001 if (order & ~1) 2002 return -EINVAL; 2003 2004 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2005 RTL8224_VND1_MDI_PAIR_SWAP, 2006 BIT(port_offset), 2007 order ? BIT(port_offset) : 0); 2008 } 2009 2010 static int rtl8224_mdi_config_polarity(struct phy_device *phydev) 2011 { 2012 struct device_node *np = phydev->mdio.dev.of_node; 2013 u8 offset = (phydev->mdio.addr & 3) * 4; 2014 u32 polarity = 0; 2015 int ret; 2016 2017 ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity); 2018 2019 /* Do nothing if the property is not present */ 2020 if (ret == -EINVAL || ret == -ENOSYS) 2021 return 0; 2022 2023 if (ret) 2024 return ret; 2025 2026 if (polarity & ~0xf) 2027 return -EINVAL; 2028 2029 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2030 RTL8224_VND1_MDI_POLARITY_SWAP, 2031 0xf << offset, 2032 polarity << offset); 2033 } 2034 2035 static int rtl8224_config_init(struct phy_device *phydev) 2036 { 2037 int ret; 2038 2039 ret = rtl8224_mdi_config_order(phydev); 2040 if (ret) 2041 return ret; 2042 2043 return rtl8224_mdi_config_polarity(phydev); 2044 } 2045 2046 static int rtl8224_probe(struct phy_device *phydev) 2047 { 2048 /* Chip exposes 4 ports, join all of them in the same package */ 2049 return devm_phy_package_join(&phydev->mdio.dev, phydev, 2050 phydev->mdio.addr & ~3, 0); 2051 } 2052 2053 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 2054 { 2055 int val; 2056 2057 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 2058 val = phy_read(phydev, 0x13); 2059 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 2060 2061 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 2062 } 2063 2064 /* On internal PHY's MMD reads over C22 always return 0. 2065 * Check a MMD register which is known to be non-zero. 2066 */ 2067 static bool rtlgen_supports_mmd(struct phy_device *phydev) 2068 { 2069 int val; 2070 2071 phy_lock_mdio_bus(phydev); 2072 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 2073 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 2074 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 2075 val = __phy_read(phydev, MII_MMD_DATA); 2076 phy_unlock_mdio_bus(phydev); 2077 2078 return val > 0; 2079 } 2080 2081 static int rtlgen_match_phy_device(struct phy_device *phydev, 2082 const struct phy_driver *phydrv) 2083 { 2084 return phydev->phy_id == RTL_GENERIC_PHYID && 2085 !rtlgen_supports_2_5gbps(phydev); 2086 } 2087 2088 static int rtl8226_match_phy_device(struct phy_device *phydev, 2089 const struct phy_driver *phydrv) 2090 { 2091 return phydev->phy_id == RTL_GENERIC_PHYID && 2092 rtlgen_supports_2_5gbps(phydev) && 2093 rtlgen_supports_mmd(phydev); 2094 } 2095 2096 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 2097 bool is_c45) 2098 { 2099 if (phydev->is_c45) 2100 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 2101 else 2102 return !is_c45 && (id == phydev->phy_id); 2103 } 2104 2105 static int rtl8221b_match_phy_device(struct phy_device *phydev, 2106 const struct phy_driver *phydrv) 2107 { 2108 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 2109 } 2110 2111 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 2112 const struct phy_driver *phydrv) 2113 { 2114 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 2115 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 2116 } 2117 2118 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 2119 const struct phy_driver *phydrv) 2120 { 2121 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 2122 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 2123 } 2124 2125 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 2126 const struct phy_driver *phydrv) 2127 { 2128 if (phydev->is_c45) 2129 return false; 2130 2131 switch (phydev->phy_id) { 2132 case RTL_GENERIC_PHYID: 2133 case RTL_8221B: 2134 case RTL_8251B: 2135 case RTL_8261C: 2136 case 0x001cc841: 2137 break; 2138 default: 2139 return false; 2140 } 2141 2142 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 2143 } 2144 2145 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 2146 const struct phy_driver *phydrv) 2147 { 2148 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 2149 } 2150 2151 static int rtlgen_resume(struct phy_device *phydev) 2152 { 2153 int ret = genphy_resume(phydev); 2154 2155 /* Internal PHY's from RTL8168h up may not be instantly ready */ 2156 msleep(20); 2157 2158 return ret; 2159 } 2160 2161 static int rtlgen_c45_resume(struct phy_device *phydev) 2162 { 2163 int ret = genphy_c45_pma_resume(phydev); 2164 2165 msleep(20); 2166 2167 return ret; 2168 } 2169 2170 static int rtl9000a_config_init(struct phy_device *phydev) 2171 { 2172 phydev->autoneg = AUTONEG_DISABLE; 2173 phydev->speed = SPEED_100; 2174 phydev->duplex = DUPLEX_FULL; 2175 2176 return 0; 2177 } 2178 2179 static int rtl9000a_config_aneg(struct phy_device *phydev) 2180 { 2181 int ret; 2182 u16 ctl = 0; 2183 2184 switch (phydev->master_slave_set) { 2185 case MASTER_SLAVE_CFG_MASTER_FORCE: 2186 ctl |= CTL1000_AS_MASTER; 2187 break; 2188 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2189 break; 2190 case MASTER_SLAVE_CFG_UNKNOWN: 2191 case MASTER_SLAVE_CFG_UNSUPPORTED: 2192 return 0; 2193 default: 2194 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2195 return -EOPNOTSUPP; 2196 } 2197 2198 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 2199 if (ret == 1) 2200 ret = genphy_soft_reset(phydev); 2201 2202 return ret; 2203 } 2204 2205 static int rtl9000a_read_status(struct phy_device *phydev) 2206 { 2207 int ret; 2208 2209 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 2210 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2211 2212 ret = genphy_update_link(phydev); 2213 if (ret) 2214 return ret; 2215 2216 ret = phy_read(phydev, MII_CTRL1000); 2217 if (ret < 0) 2218 return ret; 2219 if (ret & CTL1000_AS_MASTER) 2220 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 2221 else 2222 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 2223 2224 ret = phy_read(phydev, MII_STAT1000); 2225 if (ret < 0) 2226 return ret; 2227 if (ret & LPA_1000MSRES) 2228 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 2229 else 2230 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2231 2232 return 0; 2233 } 2234 2235 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2236 { 2237 int err; 2238 2239 err = phy_read(phydev, RTL8211F_INSR); 2240 2241 return (err < 0) ? err : 0; 2242 } 2243 2244 static int rtl9000a_config_intr(struct phy_device *phydev) 2245 { 2246 u16 val; 2247 int err; 2248 2249 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2250 err = rtl9000a_ack_interrupt(phydev); 2251 if (err) 2252 return err; 2253 2254 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2255 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2256 } else { 2257 val = ~0; 2258 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2259 if (err) 2260 return err; 2261 2262 err = rtl9000a_ack_interrupt(phydev); 2263 } 2264 2265 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2266 } 2267 2268 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2269 { 2270 int irq_status; 2271 2272 irq_status = phy_read(phydev, RTL8211F_INSR); 2273 if (irq_status < 0) { 2274 phy_error(phydev); 2275 return IRQ_NONE; 2276 } 2277 2278 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2279 return IRQ_NONE; 2280 2281 phy_trigger_machine(phydev); 2282 2283 return IRQ_HANDLED; 2284 } 2285 2286 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2287 { 2288 int err; 2289 2290 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2291 2292 return (err < 0) ? err : 0; 2293 } 2294 2295 static int rtl8221b_config_intr(struct phy_device *phydev) 2296 { 2297 int err; 2298 2299 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2300 err = rtl8221b_ack_interrupt(phydev); 2301 if (err) 2302 return err; 2303 2304 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2305 RTL8221B_VND2_INER_LINK_STATUS); 2306 } else { 2307 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2308 RTL8221B_VND2_INER, 0); 2309 if (err) 2310 return err; 2311 2312 err = rtl8221b_ack_interrupt(phydev); 2313 } 2314 2315 return err; 2316 } 2317 2318 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2319 { 2320 int err; 2321 2322 err = rtl8221b_ack_interrupt(phydev); 2323 if (err) { 2324 phy_error(phydev); 2325 return IRQ_NONE; 2326 } 2327 2328 phy_trigger_machine(phydev); 2329 2330 return IRQ_HANDLED; 2331 } 2332 2333 static int rtlgen_sfp_get_features(struct phy_device *phydev) 2334 { 2335 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2336 phydev->supported); 2337 2338 /* set default mode */ 2339 phydev->speed = SPEED_10000; 2340 phydev->duplex = DUPLEX_FULL; 2341 2342 phydev->port = PORT_FIBRE; 2343 2344 return 0; 2345 } 2346 2347 static int rtlgen_sfp_read_status(struct phy_device *phydev) 2348 { 2349 int val, err; 2350 2351 err = genphy_update_link(phydev); 2352 if (err) 2353 return err; 2354 2355 if (!phydev->link) 2356 return 0; 2357 2358 val = phy_read(phydev, RTL_PHYSR); 2359 if (val < 0) 2360 return val; 2361 2362 rtlgen_decode_physr(phydev, val); 2363 2364 return 0; 2365 } 2366 2367 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 2368 { 2369 return 0; 2370 } 2371 2372 static struct phy_driver realtek_drvs[] = { 2373 { 2374 PHY_ID_MATCH_EXACT(0x00008201), 2375 .name = "RTL8201CP Ethernet", 2376 .read_page = rtl821x_read_page, 2377 .write_page = rtl821x_write_page, 2378 }, { 2379 PHY_ID_MATCH_EXACT(0x001cc816), 2380 .name = "RTL8201F Fast Ethernet", 2381 .config_intr = &rtl8201_config_intr, 2382 .handle_interrupt = rtl8201_handle_interrupt, 2383 .suspend = genphy_suspend, 2384 .resume = genphy_resume, 2385 .read_page = rtl821x_read_page, 2386 .write_page = rtl821x_write_page, 2387 }, { 2388 PHY_ID_MATCH_MODEL(0x001cc880), 2389 .name = "RTL8208 Fast Ethernet", 2390 .read_mmd = genphy_read_mmd_unsupported, 2391 .write_mmd = genphy_write_mmd_unsupported, 2392 .suspend = genphy_suspend, 2393 .resume = genphy_resume, 2394 .read_page = rtl821x_read_page, 2395 .write_page = rtl821x_write_page, 2396 }, { 2397 PHY_ID_MATCH_EXACT(0x001cc910), 2398 .name = "RTL8211 Gigabit Ethernet", 2399 .config_aneg = rtl8211_config_aneg, 2400 .read_mmd = &genphy_read_mmd_unsupported, 2401 .write_mmd = &genphy_write_mmd_unsupported, 2402 .read_page = rtl821x_read_page, 2403 .write_page = rtl821x_write_page, 2404 }, { 2405 PHY_ID_MATCH_EXACT(0x001cc912), 2406 .name = "RTL8211B Gigabit Ethernet", 2407 .config_intr = &rtl8211b_config_intr, 2408 .handle_interrupt = rtl821x_handle_interrupt, 2409 .read_mmd = &genphy_read_mmd_unsupported, 2410 .write_mmd = &genphy_write_mmd_unsupported, 2411 .suspend = rtl8211b_suspend, 2412 .resume = rtl8211b_resume, 2413 .read_page = rtl821x_read_page, 2414 .write_page = rtl821x_write_page, 2415 }, { 2416 PHY_ID_MATCH_EXACT(0x001cc913), 2417 .name = "RTL8211C Gigabit Ethernet", 2418 .config_init = rtl8211c_config_init, 2419 .read_mmd = &genphy_read_mmd_unsupported, 2420 .write_mmd = &genphy_write_mmd_unsupported, 2421 .read_page = rtl821x_read_page, 2422 .write_page = rtl821x_write_page, 2423 }, { 2424 PHY_ID_MATCH_EXACT(0x001cc914), 2425 .name = "RTL8211DN Gigabit Ethernet", 2426 .config_intr = rtl8211e_config_intr, 2427 .handle_interrupt = rtl821x_handle_interrupt, 2428 .suspend = genphy_suspend, 2429 .resume = genphy_resume, 2430 .read_page = rtl821x_read_page, 2431 .write_page = rtl821x_write_page, 2432 }, { 2433 PHY_ID_MATCH_EXACT(0x001cc915), 2434 .name = "RTL8211E Gigabit Ethernet", 2435 .config_init = &rtl8211e_config_init, 2436 .config_intr = &rtl8211e_config_intr, 2437 .handle_interrupt = rtl821x_handle_interrupt, 2438 .suspend = genphy_suspend, 2439 .resume = genphy_resume, 2440 .read_page = rtl821x_read_page, 2441 .write_page = rtl821x_write_page, 2442 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2443 .led_hw_control_get = rtl8211e_led_hw_control_get, 2444 .led_hw_control_set = rtl8211e_led_hw_control_set, 2445 }, { 2446 PHY_ID_MATCH_EXACT(0x001cc916), 2447 .name = "RTL8211F Gigabit Ethernet", 2448 .probe = rtl8211f_probe, 2449 .config_init = &rtl8211f_config_init, 2450 .read_status = rtlgen_read_status, 2451 .config_intr = &rtl8211f_config_intr, 2452 .handle_interrupt = rtl8211f_handle_interrupt, 2453 .set_wol = rtl8211f_set_wol, 2454 .get_wol = rtl8211f_get_wol, 2455 .suspend = rtl8211f_suspend, 2456 .resume = rtl8211f_resume, 2457 .read_page = rtl821x_read_page, 2458 .write_page = rtl821x_write_page, 2459 .flags = PHY_ALWAYS_CALL_SUSPEND, 2460 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2461 .led_hw_control_get = rtl8211f_led_hw_control_get, 2462 .led_hw_control_set = rtl8211f_led_hw_control_set, 2463 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 2464 }, { 2465 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2466 .name = "RTL8211F-VD Gigabit Ethernet", 2467 .probe = rtl821x_probe, 2468 .config_init = &rtl8211f_config_init, 2469 .read_status = rtlgen_read_status, 2470 .config_intr = &rtl8211f_config_intr, 2471 .handle_interrupt = rtl8211f_handle_interrupt, 2472 .suspend = rtl821x_suspend, 2473 .resume = rtl821x_resume, 2474 .read_page = rtl821x_read_page, 2475 .write_page = rtl821x_write_page, 2476 .flags = PHY_ALWAYS_CALL_SUSPEND, 2477 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2478 .led_hw_control_get = rtl8211f_led_hw_control_get, 2479 .led_hw_control_set = rtl8211f_led_hw_control_set, 2480 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 2481 }, { 2482 .name = "Generic FE-GE Realtek PHY", 2483 .match_phy_device = rtlgen_match_phy_device, 2484 .read_status = rtlgen_read_status, 2485 .suspend = genphy_suspend, 2486 .resume = rtlgen_resume, 2487 .read_page = rtl821x_read_page, 2488 .write_page = rtl821x_write_page, 2489 .read_mmd = rtlgen_read_mmd, 2490 .write_mmd = rtlgen_write_mmd, 2491 }, { 2492 .name = "RTL8226 2.5Gbps PHY", 2493 .match_phy_device = rtl8226_match_phy_device, 2494 .get_features = rtl822x_get_features, 2495 .config_aneg = rtl822x_config_aneg, 2496 .read_status = rtl822x_read_status, 2497 .suspend = genphy_suspend, 2498 .resume = rtlgen_resume, 2499 .read_page = rtl821x_read_page, 2500 .write_page = rtl821x_write_page, 2501 .read_mmd = rtl822xb_read_mmd, 2502 .write_mmd = rtl822xb_write_mmd, 2503 }, { 2504 .match_phy_device = rtl8221b_match_phy_device, 2505 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2506 .get_features = rtl822x_get_features, 2507 .config_aneg = rtl822x_config_aneg, 2508 .config_init = rtl822xb_config_init, 2509 .inband_caps = rtl822x_inband_caps, 2510 .config_inband = rtl822x_config_inband, 2511 .get_rate_matching = rtl822xb_get_rate_matching, 2512 .read_status = rtl822xb_read_status, 2513 .suspend = genphy_suspend, 2514 .resume = rtlgen_resume, 2515 .read_page = rtl821x_read_page, 2516 .write_page = rtl821x_write_page, 2517 .read_mmd = rtl822xb_read_mmd, 2518 .write_mmd = rtl822xb_write_mmd, 2519 }, { 2520 PHY_ID_MATCH_EXACT(0x001cc838), 2521 .name = "RTL8226-CG 2.5Gbps PHY", 2522 .soft_reset = rtl822x_c45_soft_reset, 2523 .get_features = rtl822x_c45_get_features, 2524 .config_aneg = rtl822x_c45_config_aneg, 2525 .config_init = rtl822x_config_init, 2526 .inband_caps = rtl822x_inband_caps, 2527 .config_inband = rtl822x_config_inband, 2528 .read_status = rtl822xb_c45_read_status, 2529 .suspend = genphy_c45_pma_suspend, 2530 .resume = rtlgen_c45_resume, 2531 .read_mmd = rtl822xb_read_mmd, 2532 .write_mmd = rtl822xb_write_mmd, 2533 }, { 2534 PHY_ID_MATCH_EXACT(0x001cc848), 2535 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2536 .get_features = rtl822x_get_features, 2537 .config_aneg = rtl822x_config_aneg, 2538 .config_init = rtl822xb_config_init, 2539 .inband_caps = rtl822x_inband_caps, 2540 .config_inband = rtl822x_config_inband, 2541 .get_rate_matching = rtl822xb_get_rate_matching, 2542 .read_status = rtl822xb_read_status, 2543 .suspend = genphy_suspend, 2544 .resume = rtlgen_resume, 2545 .read_page = rtl821x_read_page, 2546 .write_page = rtl821x_write_page, 2547 .read_mmd = rtl822xb_read_mmd, 2548 .write_mmd = rtl822xb_write_mmd, 2549 }, { 2550 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 2551 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 2552 .config_intr = rtl8221b_config_intr, 2553 .handle_interrupt = rtl8221b_handle_interrupt, 2554 .probe = rtl822x_probe, 2555 .config_init = rtl822xb_config_init, 2556 .inband_caps = rtl822x_inband_caps, 2557 .config_inband = rtl822x_config_inband, 2558 .get_rate_matching = rtl822xb_get_rate_matching, 2559 .get_features = rtl822x_c45_get_features, 2560 .config_aneg = rtl822x_c45_config_aneg, 2561 .read_status = rtl822xb_c45_read_status, 2562 .suspend = genphy_c45_pma_suspend, 2563 .resume = rtlgen_c45_resume, 2564 .read_page = rtl821x_read_page, 2565 .write_page = rtl821x_write_page, 2566 .read_mmd = rtl822xb_read_mmd, 2567 .write_mmd = rtl822xb_write_mmd, 2568 }, { 2569 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 2570 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 2571 .config_intr = rtl8221b_config_intr, 2572 .handle_interrupt = rtl8221b_handle_interrupt, 2573 .probe = rtl822x_probe, 2574 .config_init = rtl822xb_config_init, 2575 .inband_caps = rtl822x_inband_caps, 2576 .config_inband = rtl822x_config_inband, 2577 .get_rate_matching = rtl822xb_get_rate_matching, 2578 .get_features = rtl822x_c45_get_features, 2579 .config_aneg = rtl822x_c45_config_aneg, 2580 .read_status = rtl822xb_c45_read_status, 2581 .suspend = genphy_c45_pma_suspend, 2582 .resume = rtlgen_c45_resume, 2583 .read_page = rtl821x_read_page, 2584 .write_page = rtl821x_write_page, 2585 .read_mmd = rtl822xb_read_mmd, 2586 .write_mmd = rtl822xb_write_mmd, 2587 }, { 2588 .match_phy_device = rtl8251b_c45_match_phy_device, 2589 .name = "RTL8251B 5Gbps PHY", 2590 .probe = rtl822x_probe, 2591 .get_features = rtl822x_get_features, 2592 .config_aneg = rtl822x_config_aneg, 2593 .read_status = rtl822x_read_status, 2594 .suspend = genphy_suspend, 2595 .resume = rtlgen_resume, 2596 .read_page = rtl821x_read_page, 2597 .write_page = rtl821x_write_page, 2598 }, { 2599 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2600 .name = "Realtek Internal NBASE-T PHY", 2601 .flags = PHY_IS_INTERNAL, 2602 .probe = rtl822x_probe, 2603 .get_features = rtl822x_get_features, 2604 .config_aneg = rtl822x_config_aneg, 2605 .read_status = rtl822x_read_status, 2606 .suspend = genphy_suspend, 2607 .resume = rtlgen_resume, 2608 .read_page = rtl821x_read_page, 2609 .write_page = rtl821x_write_page, 2610 .read_mmd = rtl822x_read_mmd, 2611 .write_mmd = rtl822x_write_mmd, 2612 }, { 2613 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 2614 .name = "Realtek SFP PHY Mode", 2615 .flags = PHY_IS_INTERNAL, 2616 .probe = rtl822x_probe, 2617 .get_features = rtlgen_sfp_get_features, 2618 .config_aneg = rtlgen_sfp_config_aneg, 2619 .read_status = rtlgen_sfp_read_status, 2620 .suspend = genphy_suspend, 2621 .resume = rtlgen_resume, 2622 .read_page = rtl821x_read_page, 2623 .write_page = rtl821x_write_page, 2624 .read_mmd = rtl822x_read_mmd, 2625 .write_mmd = rtl822x_write_mmd, 2626 }, { 2627 PHY_ID_MATCH_EXACT(0x001ccad0), 2628 .name = "RTL8224 2.5Gbps PHY", 2629 .flags = PHY_POLL_CABLE_TEST, 2630 .probe = rtl8224_probe, 2631 .config_init = rtl8224_config_init, 2632 .get_features = rtl822x_c45_get_features, 2633 .config_aneg = rtl822x_c45_config_aneg, 2634 .read_status = rtl822x_c45_read_status, 2635 .suspend = genphy_c45_pma_suspend, 2636 .resume = rtlgen_c45_resume, 2637 .cable_test_start = rtl8224_cable_test_start, 2638 .cable_test_get_status = rtl8224_cable_test_get_status, 2639 }, { 2640 PHY_ID_MATCH_EXACT(0x001cc961), 2641 .name = "RTL8366RB Gigabit Ethernet", 2642 .config_init = &rtl8366rb_config_init, 2643 /* These interrupts are handled by the irq controller 2644 * embedded inside the RTL8366RB, they get unmasked when the 2645 * irq is requested and ACKed by reading the status register, 2646 * which is done by the irqchip code. 2647 */ 2648 .config_intr = genphy_no_config_intr, 2649 .handle_interrupt = genphy_handle_interrupt_no_ack, 2650 .suspend = genphy_suspend, 2651 .resume = genphy_resume, 2652 }, { 2653 PHY_ID_MATCH_EXACT(0x001ccb00), 2654 .name = "RTL9000AA_RTL9000AN Ethernet", 2655 .features = PHY_BASIC_T1_FEATURES, 2656 .config_init = rtl9000a_config_init, 2657 .config_aneg = rtl9000a_config_aneg, 2658 .read_status = rtl9000a_read_status, 2659 .config_intr = rtl9000a_config_intr, 2660 .handle_interrupt = rtl9000a_handle_interrupt, 2661 .suspend = genphy_suspend, 2662 .resume = genphy_resume, 2663 .read_page = rtl821x_read_page, 2664 .write_page = rtl821x_write_page, 2665 }, { 2666 PHY_ID_MATCH_EXACT(0x001cc942), 2667 .name = "RTL8365MB-VC Gigabit Ethernet", 2668 /* Interrupt handling analogous to RTL8366RB */ 2669 .config_intr = genphy_no_config_intr, 2670 .handle_interrupt = genphy_handle_interrupt_no_ack, 2671 .suspend = genphy_suspend, 2672 .resume = genphy_resume, 2673 }, { 2674 PHY_ID_MATCH_EXACT(0x001cc960), 2675 .name = "RTL8366S Gigabit Ethernet", 2676 .suspend = genphy_suspend, 2677 .resume = genphy_resume, 2678 .read_mmd = genphy_read_mmd_unsupported, 2679 .write_mmd = genphy_write_mmd_unsupported, 2680 }, 2681 }; 2682 2683 module_phy_driver(realtek_drvs); 2684 2685 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2686 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2687 { } 2688 }; 2689 2690 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2691