1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 #include <net/phy/realtek_phy.h> 21 22 #include "../phylib.h" 23 #include "realtek.h" 24 25 #define RTL8201F_IER 0x13 26 27 #define RTL8201F_ISR 0x1e 28 #define RTL8201F_ISR_ANERR BIT(15) 29 #define RTL8201F_ISR_DUPLEX BIT(13) 30 #define RTL8201F_ISR_LINK BIT(11) 31 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 32 RTL8201F_ISR_DUPLEX | \ 33 RTL8201F_ISR_LINK) 34 35 #define RTL821x_INER 0x12 36 #define RTL8211B_INER_INIT 0x6400 37 #define RTL8211E_INER_LINK_STATUS BIT(10) 38 #define RTL8211F_INER_PME BIT(7) 39 #define RTL8211F_INER_LINK_STATUS BIT(4) 40 41 #define RTL821x_INSR 0x13 42 43 #define RTL821x_EXT_PAGE_SELECT 0x1e 44 45 #define RTL821x_PAGE_SELECT 0x1f 46 #define RTL821x_SET_EXT_PAGE 0x07 47 48 /* RTL8211E extension page 44/0x2c */ 49 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 50 #define RTL8211E_LEDCR1 0x1a 51 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 52 #define RTL8211E_LEDCR1_MASK BIT(4) 53 #define RTL8211E_LEDCR1_SHIFT 1 54 55 #define RTL8211E_LEDCR2 0x1c 56 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 57 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 58 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 59 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 60 #define RTL8211E_LEDCR2_SHIFT 4 61 62 /* RTL8211E extension page 164/0xa4 */ 63 #define RTL8211E_RGMII_EXT_PAGE 0xa4 64 #define RTL8211E_RGMII_DELAY 0x1c 65 #define RTL8211E_CTRL_DELAY BIT(13) 66 #define RTL8211E_TX_DELAY BIT(12) 67 #define RTL8211E_RX_DELAY BIT(11) 68 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 69 70 /* RTL8211F PHY configuration */ 71 #define RTL8211F_PHYCR1 0x18 72 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 73 #define RTL8211F_ALDPS_ENABLE BIT(2) 74 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 75 76 #define RTL8211F_PHYCR2 0x19 77 #define RTL8211F_CLKOUT_EN BIT(0) 78 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 79 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 94 * to undocumented register pages. The names here do not reflect the datasheet. 95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 96 */ 97 #define RTL8211FVD_CLKOUT_PAGE 0xd05 98 #define RTL8211FVD_CLKOUT_REG 0x11 99 #define RTL8211FVD_CLKOUT_EN BIT(8) 100 101 /* RTL8211F RGMII configuration */ 102 #define RTL8211F_RGMII_PAGE 0xd08 103 104 #define RTL8211F_TXCR 0x11 105 #define RTL8211F_TX_DELAY BIT(8) 106 107 #define RTL8211F_RXCR 0x15 108 #define RTL8211F_RX_DELAY BIT(3) 109 110 /* RTL8211F WOL settings */ 111 #define RTL8211F_WOL_PAGE 0xd8a 112 #define RTL8211F_WOL_SETTINGS_EVENTS 16 113 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 114 #define RTL8211F_WOL_RST_RMSQ 17 115 #define RTL8211F_WOL_RG_RSTB BIT(15) 116 #define RTL8211F_WOL_RMSQ 0x1fff 117 118 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 119 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 120 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 121 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 122 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 123 124 #define RTL822X_VND1_SERDES_OPTION 0x697a 125 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 126 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 128 129 #define RTL822X_VND1_SERDES_CTRL3 0x7580 130 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 131 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 132 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 133 134 #define RTL822X_VND1_SERDES_CMD 0x7587 135 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 136 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 137 #define RTL822X_VND1_SERDES_ADDR 0x7588 138 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 139 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 140 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 141 #define RTL822X_VND1_SERDES_DATA 0x7589 142 143 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 144 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 145 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 146 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 147 148 #define RTL8221B_VND2_INER 0xa4d2 149 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 150 151 #define RTL8221B_VND2_INSR 0xa4d4 152 153 #define RTL8224_MII_RTCT 0x11 154 #define RTL8224_MII_RTCT_ENABLE BIT(0) 155 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 156 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 157 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 158 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 159 #define RTL8224_MII_RTCT_DONE BIT(15) 160 161 #define RTL8224_MII_SRAM_ADDR 0x1b 162 #define RTL8224_MII_SRAM_DATA 0x1c 163 164 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 165 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 166 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 167 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 168 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 169 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 170 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 171 172 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 173 174 #define RTL8366RB_POWER_SAVE 0x15 175 #define RTL8366RB_POWER_SAVE_ON BIT(12) 176 177 #define RTL9000A_GINMR 0x14 178 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 179 180 #define RTL_PHYSR MII_RESV2 181 #define RTL_PHYSR_DUPLEX BIT(3) 182 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 183 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 184 #define RTL_PHYSR_MASTER BIT(11) 185 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 186 187 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 188 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 189 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 190 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 191 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 192 #define RTL_MDIO_PMA_SPEED 0xa616 193 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 194 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 195 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 196 197 #define RTL_GENERIC_PHYID 0x001cc800 198 #define RTL_8211FVD_PHYID 0x001cc878 199 #define RTL_8221B 0x001cc840 200 #define RTL_8221B_VB_CG 0x001cc849 201 #define RTL_8221B_VM_CG 0x001cc84a 202 #define RTL_8251B 0x001cc862 203 #define RTL_8261C 0x001cc890 204 205 /* RTL8211E and RTL8211F support up to three LEDs */ 206 #define RTL8211x_LED_COUNT 3 207 208 MODULE_DESCRIPTION("Realtek PHY driver"); 209 MODULE_AUTHOR("Johnson Leung"); 210 MODULE_LICENSE("GPL"); 211 212 struct rtl821x_priv { 213 bool enable_aldps; 214 bool disable_clk_out; 215 struct clk *clk; 216 /* rtl8211f */ 217 u16 iner; 218 }; 219 220 static int rtl821x_read_page(struct phy_device *phydev) 221 { 222 return __phy_read(phydev, RTL821x_PAGE_SELECT); 223 } 224 225 static int rtl821x_write_page(struct phy_device *phydev, int page) 226 { 227 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 228 } 229 230 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 231 u32 regnum) 232 { 233 int oldpage, ret = 0; 234 235 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 236 if (oldpage >= 0) { 237 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 238 if (ret == 0) 239 ret = __phy_read(phydev, regnum); 240 } 241 242 return phy_restore_page(phydev, oldpage, ret); 243 } 244 245 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 246 u32 regnum, u16 mask, u16 set) 247 { 248 int oldpage, ret = 0; 249 250 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 251 if (oldpage >= 0) { 252 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 253 if (ret == 0) 254 ret = __phy_modify(phydev, regnum, mask, set); 255 } 256 257 return phy_restore_page(phydev, oldpage, ret); 258 } 259 260 static int rtl821x_probe(struct phy_device *phydev) 261 { 262 struct device *dev = &phydev->mdio.dev; 263 struct rtl821x_priv *priv; 264 265 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 266 if (!priv) 267 return -ENOMEM; 268 269 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 270 if (IS_ERR(priv->clk)) 271 return dev_err_probe(dev, PTR_ERR(priv->clk), 272 "failed to get phy clock\n"); 273 274 priv->enable_aldps = of_property_read_bool(dev->of_node, 275 "realtek,aldps-enable"); 276 priv->disable_clk_out = of_property_read_bool(dev->of_node, 277 "realtek,clkout-disable"); 278 279 phydev->priv = priv; 280 281 return 0; 282 } 283 284 static int rtl8211f_probe(struct phy_device *phydev) 285 { 286 struct device *dev = &phydev->mdio.dev; 287 int ret; 288 289 ret = rtl821x_probe(phydev); 290 if (ret < 0) 291 return ret; 292 293 /* Disable all PME events */ 294 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 295 RTL8211F_WOL_SETTINGS_EVENTS, 0); 296 if (ret < 0) 297 return ret; 298 299 /* Mark this PHY as wakeup capable and register the interrupt as a 300 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 301 * and the interrupt is valid. 302 */ 303 if (device_property_read_bool(dev, "wakeup-source") && 304 phy_interrupt_is_valid(phydev)) { 305 device_set_wakeup_capable(dev, true); 306 devm_pm_set_wake_irq(dev, phydev->irq); 307 } 308 309 return ret; 310 } 311 312 static int rtl8201_ack_interrupt(struct phy_device *phydev) 313 { 314 int err; 315 316 err = phy_read(phydev, RTL8201F_ISR); 317 318 return (err < 0) ? err : 0; 319 } 320 321 static int rtl821x_ack_interrupt(struct phy_device *phydev) 322 { 323 int err; 324 325 err = phy_read(phydev, RTL821x_INSR); 326 327 return (err < 0) ? err : 0; 328 } 329 330 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 331 { 332 int err; 333 334 err = phy_read(phydev, RTL8211F_INSR); 335 336 return (err < 0) ? err : 0; 337 } 338 339 static int rtl8201_config_intr(struct phy_device *phydev) 340 { 341 u16 val; 342 int err; 343 344 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 345 err = rtl8201_ack_interrupt(phydev); 346 if (err) 347 return err; 348 349 val = BIT(13) | BIT(12) | BIT(11); 350 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 351 } else { 352 val = 0; 353 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 354 if (err) 355 return err; 356 357 err = rtl8201_ack_interrupt(phydev); 358 } 359 360 return err; 361 } 362 363 static int rtl8211b_config_intr(struct phy_device *phydev) 364 { 365 int err; 366 367 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 368 err = rtl821x_ack_interrupt(phydev); 369 if (err) 370 return err; 371 372 err = phy_write(phydev, RTL821x_INER, 373 RTL8211B_INER_INIT); 374 } else { 375 err = phy_write(phydev, RTL821x_INER, 0); 376 if (err) 377 return err; 378 379 err = rtl821x_ack_interrupt(phydev); 380 } 381 382 return err; 383 } 384 385 static int rtl8211e_config_intr(struct phy_device *phydev) 386 { 387 int err; 388 389 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 390 err = rtl821x_ack_interrupt(phydev); 391 if (err) 392 return err; 393 394 err = phy_write(phydev, RTL821x_INER, 395 RTL8211E_INER_LINK_STATUS); 396 } else { 397 err = phy_write(phydev, RTL821x_INER, 0); 398 if (err) 399 return err; 400 401 err = rtl821x_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static int rtl8211f_config_intr(struct phy_device *phydev) 408 { 409 struct rtl821x_priv *priv = phydev->priv; 410 u16 val; 411 int err; 412 413 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 414 err = rtl8211f_ack_interrupt(phydev); 415 if (err) 416 return err; 417 418 val = RTL8211F_INER_LINK_STATUS; 419 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 420 if (err == 0) 421 priv->iner = val; 422 } else { 423 priv->iner = val = 0; 424 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 425 if (err) 426 return err; 427 428 err = rtl8211f_ack_interrupt(phydev); 429 } 430 431 return err; 432 } 433 434 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 435 { 436 int irq_status; 437 438 irq_status = phy_read(phydev, RTL8201F_ISR); 439 if (irq_status < 0) { 440 phy_error(phydev); 441 return IRQ_NONE; 442 } 443 444 if (!(irq_status & RTL8201F_ISR_MASK)) 445 return IRQ_NONE; 446 447 phy_trigger_machine(phydev); 448 449 return IRQ_HANDLED; 450 } 451 452 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 453 { 454 int irq_status, irq_enabled; 455 456 irq_status = phy_read(phydev, RTL821x_INSR); 457 if (irq_status < 0) { 458 phy_error(phydev); 459 return IRQ_NONE; 460 } 461 462 irq_enabled = phy_read(phydev, RTL821x_INER); 463 if (irq_enabled < 0) { 464 phy_error(phydev); 465 return IRQ_NONE; 466 } 467 468 if (!(irq_status & irq_enabled)) 469 return IRQ_NONE; 470 471 phy_trigger_machine(phydev); 472 473 return IRQ_HANDLED; 474 } 475 476 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 477 { 478 int irq_status; 479 480 irq_status = phy_read(phydev, RTL8211F_INSR); 481 if (irq_status < 0) { 482 phy_error(phydev); 483 return IRQ_NONE; 484 } 485 486 if (irq_status & RTL8211F_INER_LINK_STATUS) { 487 phy_trigger_machine(phydev); 488 return IRQ_HANDLED; 489 } 490 491 if (irq_status & RTL8211F_INER_PME) { 492 pm_wakeup_event(&phydev->mdio.dev, 0); 493 return IRQ_HANDLED; 494 } 495 496 return IRQ_NONE; 497 } 498 499 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 500 { 501 int wol_events; 502 503 /* If the PHY is not capable of waking the system, then WoL can not 504 * be supported. 505 */ 506 if (!device_can_wakeup(&dev->mdio.dev)) { 507 wol->supported = 0; 508 return; 509 } 510 511 wol->supported = WAKE_MAGIC; 512 513 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 514 if (wol_events < 0) 515 return; 516 517 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 518 wol->wolopts = WAKE_MAGIC; 519 } 520 521 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 522 { 523 const u8 *mac_addr = dev->attached_dev->dev_addr; 524 int oldpage; 525 526 if (!device_can_wakeup(&dev->mdio.dev)) 527 return -EOPNOTSUPP; 528 529 oldpage = phy_save_page(dev); 530 if (oldpage < 0) 531 goto err; 532 533 if (wol->wolopts & WAKE_MAGIC) { 534 /* Store the device address for the magic packet */ 535 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 536 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 537 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 538 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 539 540 /* Enable magic packet matching */ 541 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 542 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 543 /* Set the maximum packet size, and assert WoL reset */ 544 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 545 } else { 546 /* Disable magic packet matching */ 547 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 548 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 549 550 /* Place WoL in reset */ 551 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 552 RTL8211F_WOL_RG_RSTB); 553 } 554 555 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 556 557 err: 558 return phy_restore_page(dev, oldpage, 0); 559 } 560 561 static int rtl8211_config_aneg(struct phy_device *phydev) 562 { 563 int ret; 564 565 ret = genphy_config_aneg(phydev); 566 if (ret < 0) 567 return ret; 568 569 /* Quirk was copied from vendor driver. Unfortunately it includes no 570 * description of the magic numbers. 571 */ 572 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 573 phy_write(phydev, 0x17, 0x2138); 574 phy_write(phydev, 0x0e, 0x0260); 575 } else { 576 phy_write(phydev, 0x17, 0x2108); 577 phy_write(phydev, 0x0e, 0x0000); 578 } 579 580 return 0; 581 } 582 583 static int rtl8211c_config_init(struct phy_device *phydev) 584 { 585 /* RTL8211C has an issue when operating in Gigabit slave mode */ 586 return phy_set_bits(phydev, MII_CTRL1000, 587 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 588 } 589 590 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 591 { 592 u16 val_txdly, val_rxdly; 593 int ret; 594 595 switch (phydev->interface) { 596 case PHY_INTERFACE_MODE_RGMII: 597 val_txdly = 0; 598 val_rxdly = 0; 599 break; 600 601 case PHY_INTERFACE_MODE_RGMII_RXID: 602 val_txdly = 0; 603 val_rxdly = RTL8211F_RX_DELAY; 604 break; 605 606 case PHY_INTERFACE_MODE_RGMII_TXID: 607 val_txdly = RTL8211F_TX_DELAY; 608 val_rxdly = 0; 609 break; 610 611 case PHY_INTERFACE_MODE_RGMII_ID: 612 val_txdly = RTL8211F_TX_DELAY; 613 val_rxdly = RTL8211F_RX_DELAY; 614 break; 615 616 default: /* the rest of the modes imply leaving delay as is. */ 617 return 0; 618 } 619 620 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 621 RTL8211F_TXCR, RTL8211F_TX_DELAY, 622 val_txdly); 623 if (ret < 0) { 624 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 625 ERR_PTR(ret)); 626 return ret; 627 } else if (ret) { 628 phydev_dbg(phydev, 629 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 630 str_enable_disable(val_txdly)); 631 } else { 632 phydev_dbg(phydev, 633 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 634 str_enabled_disabled(val_txdly)); 635 } 636 637 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 638 RTL8211F_RXCR, RTL8211F_RX_DELAY, 639 val_rxdly); 640 if (ret < 0) { 641 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 642 ERR_PTR(ret)); 643 return ret; 644 } else if (ret) { 645 phydev_dbg(phydev, 646 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 647 str_enable_disable(val_rxdly)); 648 } else { 649 phydev_dbg(phydev, 650 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 651 str_enabled_disabled(val_rxdly)); 652 } 653 654 return 0; 655 } 656 657 static int rtl8211f_config_clk_out(struct phy_device *phydev) 658 { 659 struct rtl821x_priv *priv = phydev->priv; 660 int ret; 661 662 /* The value is preserved if the device tree property is absent */ 663 if (!priv->disable_clk_out) 664 return 0; 665 666 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 667 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 668 RTL8211FVD_CLKOUT_REG, 669 RTL8211FVD_CLKOUT_EN, 0); 670 else 671 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 672 0); 673 if (ret) 674 return ret; 675 676 return genphy_soft_reset(phydev); 677 } 678 679 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 680 * which causes the RXC clock signal to stop for tens to hundreds of 681 * milliseconds. 682 * 683 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 684 * only enabled based on an opt-in device tree property. 685 */ 686 static int rtl8211f_config_aldps(struct phy_device *phydev) 687 { 688 struct rtl821x_priv *priv = phydev->priv; 689 u16 mask = RTL8211F_ALDPS_PLL_OFF | 690 RTL8211F_ALDPS_ENABLE | 691 RTL8211F_ALDPS_XTAL_OFF; 692 693 /* The value is preserved if the device tree property is absent */ 694 if (!priv->enable_aldps) 695 return 0; 696 697 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 698 } 699 700 static int rtl8211f_config_phy_eee(struct phy_device *phydev) 701 { 702 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 703 return phy_modify(phydev, RTL8211F_PHYCR2, 704 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 705 } 706 707 static int rtl8211f_config_init(struct phy_device *phydev) 708 { 709 struct device *dev = &phydev->mdio.dev; 710 int ret; 711 712 ret = rtl8211f_config_aldps(phydev); 713 if (ret) { 714 dev_err(dev, "aldps mode configuration failed: %pe\n", 715 ERR_PTR(ret)); 716 return ret; 717 } 718 719 ret = rtl8211f_config_rgmii_delay(phydev); 720 if (ret) 721 return ret; 722 723 ret = rtl8211f_config_clk_out(phydev); 724 if (ret) { 725 dev_err(dev, "clkout configuration failed: %pe\n", 726 ERR_PTR(ret)); 727 return ret; 728 } 729 730 return rtl8211f_config_phy_eee(phydev); 731 } 732 733 static int rtl821x_suspend(struct phy_device *phydev) 734 { 735 struct rtl821x_priv *priv = phydev->priv; 736 int ret = 0; 737 738 if (!phydev->wol_enabled) { 739 ret = genphy_suspend(phydev); 740 741 if (ret) 742 return ret; 743 744 clk_disable_unprepare(priv->clk); 745 } 746 747 return ret; 748 } 749 750 static int rtl8211f_suspend(struct phy_device *phydev) 751 { 752 u16 wol_rst; 753 int ret; 754 755 ret = rtl821x_suspend(phydev); 756 if (ret < 0) 757 return ret; 758 759 /* If a PME event is enabled, then configure the interrupt for 760 * PME events only, disabling link interrupt. We avoid switching 761 * to PMEB mode as we don't have a status bit for that. 762 */ 763 if (device_may_wakeup(&phydev->mdio.dev)) { 764 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 765 RTL8211F_INER_PME); 766 if (ret < 0) 767 goto err; 768 769 /* Read the INSR to clear any pending interrupt */ 770 phy_read(phydev, RTL8211F_INSR); 771 772 /* Reset the WoL to ensure that an event is picked up. 773 * Unless we do this, even if we receive another packet, 774 * we may not have a PME interrupt raised. 775 */ 776 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 777 RTL8211F_WOL_RST_RMSQ); 778 if (ret < 0) 779 goto err; 780 781 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 782 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 783 RTL8211F_WOL_RST_RMSQ, wol_rst); 784 if (ret < 0) 785 goto err; 786 787 wol_rst |= RTL8211F_WOL_RG_RSTB; 788 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 789 RTL8211F_WOL_RST_RMSQ, wol_rst); 790 } 791 792 err: 793 return ret; 794 } 795 796 static int rtl821x_resume(struct phy_device *phydev) 797 { 798 struct rtl821x_priv *priv = phydev->priv; 799 int ret; 800 801 if (!phydev->wol_enabled) 802 clk_prepare_enable(priv->clk); 803 804 ret = genphy_resume(phydev); 805 if (ret < 0) 806 return ret; 807 808 msleep(20); 809 810 return 0; 811 } 812 813 static int rtl8211f_resume(struct phy_device *phydev) 814 { 815 struct rtl821x_priv *priv = phydev->priv; 816 int ret; 817 818 ret = rtl821x_resume(phydev); 819 if (ret < 0) 820 return ret; 821 822 /* If the device was programmed for a PME event, restore the interrupt 823 * enable so phylib can receive link state interrupts. 824 */ 825 if (device_may_wakeup(&phydev->mdio.dev)) 826 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 827 828 return ret; 829 } 830 831 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 832 unsigned long rules) 833 { 834 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 835 BIT(TRIGGER_NETDEV_LINK_10) | 836 BIT(TRIGGER_NETDEV_LINK_100) | 837 BIT(TRIGGER_NETDEV_LINK_1000) | 838 BIT(TRIGGER_NETDEV_RX) | 839 BIT(TRIGGER_NETDEV_TX); 840 841 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 842 * - Link: Configurable subset of 10/100/1000 link rates 843 * - Active: Blink on activity, RX or TX is not differentiated 844 * The Active option has two modes, A and B: 845 * - A: Link and Active indication at configurable, but matching, 846 * subset of 10/100/1000 link rates 847 * - B: Link indication at configurable subset of 10/100/1000 link 848 * rates and Active indication always at all three 10+100+1000 849 * link rates. 850 * This code currently uses mode B only. 851 * 852 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 853 */ 854 855 if (index >= RTL8211x_LED_COUNT) 856 return -EINVAL; 857 858 /* Filter out any other unsupported triggers. */ 859 if (rules & ~mask) 860 return -EOPNOTSUPP; 861 862 /* RX and TX are not differentiated, either both are set or not set. */ 863 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 864 return -EOPNOTSUPP; 865 866 return 0; 867 } 868 869 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 870 unsigned long *rules) 871 { 872 int val; 873 874 if (index >= RTL8211x_LED_COUNT) 875 return -EINVAL; 876 877 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 878 if (val < 0) 879 return val; 880 881 val >>= RTL8211F_LEDCR_SHIFT * index; 882 val &= RTL8211F_LEDCR_MASK; 883 884 if (val & RTL8211F_LEDCR_LINK_10) 885 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 886 887 if (val & RTL8211F_LEDCR_LINK_100) 888 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 889 890 if (val & RTL8211F_LEDCR_LINK_1000) 891 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 892 893 if ((val & RTL8211F_LEDCR_LINK_10) && 894 (val & RTL8211F_LEDCR_LINK_100) && 895 (val & RTL8211F_LEDCR_LINK_1000)) { 896 __set_bit(TRIGGER_NETDEV_LINK, rules); 897 } 898 899 if (val & RTL8211F_LEDCR_ACT_TXRX) { 900 __set_bit(TRIGGER_NETDEV_RX, rules); 901 __set_bit(TRIGGER_NETDEV_TX, rules); 902 } 903 904 return 0; 905 } 906 907 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 908 unsigned long rules) 909 { 910 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 911 u16 reg = 0; 912 913 if (index >= RTL8211x_LED_COUNT) 914 return -EINVAL; 915 916 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 917 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 918 reg |= RTL8211F_LEDCR_LINK_10; 919 } 920 921 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 922 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 923 reg |= RTL8211F_LEDCR_LINK_100; 924 } 925 926 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 927 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 928 reg |= RTL8211F_LEDCR_LINK_1000; 929 } 930 931 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 932 test_bit(TRIGGER_NETDEV_TX, &rules)) { 933 reg |= RTL8211F_LEDCR_ACT_TXRX; 934 } 935 936 reg <<= RTL8211F_LEDCR_SHIFT * index; 937 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 938 939 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 940 } 941 942 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 943 unsigned long *rules) 944 { 945 int ret; 946 u16 cr1, cr2; 947 948 if (index >= RTL8211x_LED_COUNT) 949 return -EINVAL; 950 951 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 952 RTL8211E_LEDCR1); 953 if (ret < 0) 954 return ret; 955 956 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 957 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 958 __set_bit(TRIGGER_NETDEV_RX, rules); 959 __set_bit(TRIGGER_NETDEV_TX, rules); 960 } 961 962 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 963 RTL8211E_LEDCR2); 964 if (ret < 0) 965 return ret; 966 967 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 968 if (cr2 & RTL8211E_LEDCR2_LINK_10) 969 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 970 971 if (cr2 & RTL8211E_LEDCR2_LINK_100) 972 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 973 974 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 975 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 976 977 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 978 (cr2 & RTL8211E_LEDCR2_LINK_100) && 979 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 980 __set_bit(TRIGGER_NETDEV_LINK, rules); 981 } 982 983 return ret; 984 } 985 986 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 987 unsigned long rules) 988 { 989 const u16 cr1mask = 990 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 991 const u16 cr2mask = 992 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 993 u16 cr1 = 0, cr2 = 0; 994 int ret; 995 996 if (index >= RTL8211x_LED_COUNT) 997 return -EINVAL; 998 999 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1000 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1001 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1002 } 1003 1004 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1005 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1006 RTL8211E_LEDCR1, cr1mask, cr1); 1007 if (ret < 0) 1008 return ret; 1009 1010 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1011 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1012 cr2 |= RTL8211E_LEDCR2_LINK_10; 1013 } 1014 1015 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1016 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1017 cr2 |= RTL8211E_LEDCR2_LINK_100; 1018 } 1019 1020 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1021 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1022 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1023 } 1024 1025 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1026 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1027 RTL8211E_LEDCR2, cr2mask, cr2); 1028 1029 return ret; 1030 } 1031 1032 static int rtl8211e_config_init(struct phy_device *phydev) 1033 { 1034 u16 val; 1035 1036 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1037 switch (phydev->interface) { 1038 case PHY_INTERFACE_MODE_RGMII: 1039 val = RTL8211E_CTRL_DELAY | 0; 1040 break; 1041 case PHY_INTERFACE_MODE_RGMII_ID: 1042 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1043 break; 1044 case PHY_INTERFACE_MODE_RGMII_RXID: 1045 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1046 break; 1047 case PHY_INTERFACE_MODE_RGMII_TXID: 1048 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1049 break; 1050 default: /* the rest of the modes imply leaving delays as is. */ 1051 return 0; 1052 } 1053 1054 /* According to a sample driver there is a 0x1c config register on the 1055 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1056 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1057 * The configuration register definition: 1058 * 14 = reserved 1059 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1060 * 12 = RX Delay, 11 = TX Delay 1061 * 10:0 = Test && debug settings reserved by realtek 1062 */ 1063 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1064 RTL8211E_RGMII_DELAY, 1065 RTL8211E_DELAY_MASK, val); 1066 } 1067 1068 static int rtl8211b_suspend(struct phy_device *phydev) 1069 { 1070 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1071 1072 return genphy_suspend(phydev); 1073 } 1074 1075 static int rtl8211b_resume(struct phy_device *phydev) 1076 { 1077 phy_write(phydev, MII_MMD_DATA, 0); 1078 1079 return genphy_resume(phydev); 1080 } 1081 1082 static int rtl8366rb_config_init(struct phy_device *phydev) 1083 { 1084 int ret; 1085 1086 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1087 RTL8366RB_POWER_SAVE_ON); 1088 if (ret) { 1089 dev_err(&phydev->mdio.dev, 1090 "error enabling power management\n"); 1091 } 1092 1093 return ret; 1094 } 1095 1096 /* get actual speed to cover the downshift case */ 1097 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1098 { 1099 /* bit 3 1100 * 0: Half Duplex 1101 * 1: Full Duplex 1102 */ 1103 if (val & RTL_PHYSR_DUPLEX) 1104 phydev->duplex = DUPLEX_FULL; 1105 else 1106 phydev->duplex = DUPLEX_HALF; 1107 1108 switch (val & RTL_PHYSR_SPEED_MASK) { 1109 case 0x0000: 1110 phydev->speed = SPEED_10; 1111 break; 1112 case 0x0010: 1113 phydev->speed = SPEED_100; 1114 break; 1115 case 0x0020: 1116 phydev->speed = SPEED_1000; 1117 break; 1118 case 0x0200: 1119 phydev->speed = SPEED_10000; 1120 break; 1121 case 0x0210: 1122 phydev->speed = SPEED_2500; 1123 break; 1124 case 0x0220: 1125 phydev->speed = SPEED_5000; 1126 break; 1127 default: 1128 break; 1129 } 1130 1131 /* bit 11 1132 * 0: Slave Mode 1133 * 1: Master Mode 1134 */ 1135 if (phydev->speed >= 1000) { 1136 if (val & RTL_PHYSR_MASTER) 1137 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1138 else 1139 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1140 } else { 1141 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1142 } 1143 } 1144 1145 static int rtlgen_read_status(struct phy_device *phydev) 1146 { 1147 int ret, val; 1148 1149 ret = genphy_read_status(phydev); 1150 if (ret < 0) 1151 return ret; 1152 1153 if (!phydev->link) 1154 return 0; 1155 1156 val = phy_read(phydev, RTL_PHYSR); 1157 if (val < 0) 1158 return val; 1159 1160 rtlgen_decode_physr(phydev, val); 1161 1162 return 0; 1163 } 1164 1165 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1166 { 1167 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1168 } 1169 1170 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1171 { 1172 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1173 val); 1174 } 1175 1176 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1177 { 1178 int ret; 1179 1180 if (devnum == MDIO_MMD_VEND2) 1181 ret = rtlgen_read_vend2(phydev, regnum); 1182 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1183 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1184 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1185 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1186 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1187 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1188 else 1189 ret = -EOPNOTSUPP; 1190 1191 return ret; 1192 } 1193 1194 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1195 u16 val) 1196 { 1197 int ret; 1198 1199 if (devnum == MDIO_MMD_VEND2) 1200 ret = rtlgen_write_vend2(phydev, regnum, val); 1201 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1202 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1203 else 1204 ret = -EOPNOTSUPP; 1205 1206 return ret; 1207 } 1208 1209 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1210 { 1211 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1212 1213 if (ret != -EOPNOTSUPP) 1214 return ret; 1215 1216 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1217 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1218 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1219 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1220 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1221 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1222 1223 return ret; 1224 } 1225 1226 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1227 u16 val) 1228 { 1229 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1230 1231 if (ret != -EOPNOTSUPP) 1232 return ret; 1233 1234 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1235 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1236 1237 return ret; 1238 } 1239 1240 static int rtl822x_probe(struct phy_device *phydev) 1241 { 1242 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1243 phydev->phy_id != RTL_GENERIC_PHYID) 1244 return rtl822x_hwmon_init(phydev); 1245 1246 return 0; 1247 } 1248 1249 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1250 * A mapping to use paged access needs to be used instead. 1251 * All other MMD devices can be accessed as usual. 1252 */ 1253 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1254 { 1255 int oldpage, ret, read_ret; 1256 u16 page; 1257 1258 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1259 * Clause-45 access is available 1260 */ 1261 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1262 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1263 phydev->is_c45, devnum, reg); 1264 1265 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1266 if (reg >= RTL822X_VND2_C22_REG(0) && 1267 reg <= RTL822X_VND2_C22_REG(30)) 1268 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1269 1270 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1271 page = RTL822X_VND2_TO_PAGE(reg); 1272 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1273 if (oldpage < 0) 1274 return oldpage; 1275 1276 if (oldpage != page) { 1277 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1278 if (ret < 0) 1279 return ret; 1280 } 1281 1282 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1283 if (oldpage != page) { 1284 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1285 if (ret < 0) 1286 return ret; 1287 } 1288 1289 return read_ret; 1290 } 1291 1292 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1293 u16 val) 1294 { 1295 int oldpage, ret, write_ret; 1296 u16 page; 1297 1298 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1299 * Clause-45 access is available 1300 */ 1301 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1302 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1303 phydev->is_c45, devnum, reg, val); 1304 1305 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1306 if (reg >= RTL822X_VND2_C22_REG(0) && 1307 reg <= RTL822X_VND2_C22_REG(30)) 1308 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1309 1310 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1311 page = RTL822X_VND2_TO_PAGE(reg); 1312 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1313 if (oldpage < 0) 1314 return oldpage; 1315 1316 if (oldpage != page) { 1317 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1318 if (ret < 0) 1319 return ret; 1320 } 1321 1322 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1323 if (oldpage != page) { 1324 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1325 if (ret < 0) 1326 return ret; 1327 } 1328 1329 return write_ret; 1330 } 1331 1332 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1333 { 1334 bool has_2500, has_sgmii; 1335 u16 mode; 1336 int ret; 1337 1338 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1339 phydev->host_interfaces) || 1340 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1341 1342 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1343 phydev->host_interfaces) || 1344 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1345 1346 /* fill in possible interfaces */ 1347 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1348 has_2500); 1349 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1350 has_sgmii); 1351 1352 if (!has_2500 && !has_sgmii) 1353 return 0; 1354 1355 /* determine SerDes option mode */ 1356 if (has_2500 && !has_sgmii) { 1357 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1358 phydev->rate_matching = RATE_MATCH_PAUSE; 1359 } else { 1360 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1361 phydev->rate_matching = RATE_MATCH_NONE; 1362 } 1363 1364 /* the following sequence with magic numbers sets up the SerDes 1365 * option mode 1366 */ 1367 1368 if (!gen1) { 1369 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1370 if (ret < 0) 1371 return ret; 1372 } 1373 1374 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1375 RTL822X_VND1_SERDES_OPTION, 1376 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1377 mode); 1378 if (gen1 || ret < 0) 1379 return ret; 1380 1381 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1382 if (ret < 0) 1383 return ret; 1384 1385 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1386 if (ret < 0) 1387 return ret; 1388 1389 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1390 } 1391 1392 static int rtl822x_config_init(struct phy_device *phydev) 1393 { 1394 return rtl822x_set_serdes_option_mode(phydev, true); 1395 } 1396 1397 static int rtl822xb_config_init(struct phy_device *phydev) 1398 { 1399 return rtl822x_set_serdes_option_mode(phydev, false); 1400 } 1401 1402 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1403 { 1404 int ret, poll; 1405 1406 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1407 if (ret < 0) 1408 return ret; 1409 1410 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1411 if (ret < 0) 1412 return ret; 1413 1414 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1415 RTL822X_VND1_SERDES_CMD_WRITE | 1416 RTL822X_VND1_SERDES_CMD_BUSY); 1417 if (ret < 0) 1418 return ret; 1419 1420 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1421 RTL822X_VND1_SERDES_CMD, poll, 1422 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1423 500, 100000, false); 1424 } 1425 1426 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1427 { 1428 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1429 (modes != LINK_INBAND_DISABLE) ? 1430 RTL822X_VND1_SERDES_INBAND_ENABLE : 1431 RTL822X_VND1_SERDES_INBAND_DISABLE); 1432 } 1433 1434 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1435 phy_interface_t interface) 1436 { 1437 switch (interface) { 1438 case PHY_INTERFACE_MODE_2500BASEX: 1439 return LINK_INBAND_DISABLE; 1440 case PHY_INTERFACE_MODE_SGMII: 1441 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1442 default: 1443 return 0; 1444 } 1445 } 1446 1447 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1448 phy_interface_t iface) 1449 { 1450 int val; 1451 1452 /* Only rate matching at 2500base-x */ 1453 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1454 return RATE_MATCH_NONE; 1455 1456 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1457 if (val < 0) 1458 return val; 1459 1460 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1461 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1462 return RATE_MATCH_PAUSE; 1463 1464 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1465 return RATE_MATCH_NONE; 1466 } 1467 1468 static int rtl822x_get_features(struct phy_device *phydev) 1469 { 1470 int val; 1471 1472 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1473 if (val < 0) 1474 return val; 1475 1476 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1477 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1478 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1479 phydev->supported, val & MDIO_PMA_SPEED_5G); 1480 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1481 phydev->supported, val & MDIO_SPEED_10G); 1482 1483 return genphy_read_abilities(phydev); 1484 } 1485 1486 static int rtl822x_config_aneg(struct phy_device *phydev) 1487 { 1488 int ret = 0; 1489 1490 if (phydev->autoneg == AUTONEG_ENABLE) { 1491 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1492 1493 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1494 RTL_MDIO_AN_10GBT_CTRL, 1495 MDIO_AN_10GBT_CTRL_ADV2_5G | 1496 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1497 if (ret < 0) 1498 return ret; 1499 } 1500 1501 return __genphy_config_aneg(phydev, ret); 1502 } 1503 1504 static void rtl822xb_update_interface(struct phy_device *phydev) 1505 { 1506 int val; 1507 1508 if (!phydev->link) 1509 return; 1510 1511 /* Change interface according to serdes mode */ 1512 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1513 if (val < 0) 1514 return; 1515 1516 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1517 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1518 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1519 break; 1520 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1521 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1522 break; 1523 } 1524 } 1525 1526 static int rtl822x_read_status(struct phy_device *phydev) 1527 { 1528 int lpadv, ret; 1529 1530 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1531 1532 ret = rtlgen_read_status(phydev); 1533 if (ret < 0) 1534 return ret; 1535 1536 if (phydev->autoneg == AUTONEG_DISABLE || 1537 !phydev->autoneg_complete) 1538 return 0; 1539 1540 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1541 if (lpadv < 0) 1542 return lpadv; 1543 1544 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1545 1546 return 0; 1547 } 1548 1549 static int rtl822xb_read_status(struct phy_device *phydev) 1550 { 1551 int ret; 1552 1553 ret = rtl822x_read_status(phydev); 1554 if (ret < 0) 1555 return ret; 1556 1557 rtl822xb_update_interface(phydev); 1558 1559 return 0; 1560 } 1561 1562 static int rtl822x_c45_get_features(struct phy_device *phydev) 1563 { 1564 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1565 phydev->supported); 1566 1567 return genphy_c45_pma_read_abilities(phydev); 1568 } 1569 1570 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1571 { 1572 bool changed = false; 1573 int ret, val; 1574 1575 if (phydev->autoneg == AUTONEG_DISABLE) 1576 return genphy_c45_pma_setup_forced(phydev); 1577 1578 ret = genphy_c45_an_config_aneg(phydev); 1579 if (ret < 0) 1580 return ret; 1581 if (ret > 0) 1582 changed = true; 1583 1584 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1585 1586 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1587 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1588 RTL822X_VND2_C22_REG(MII_CTRL1000), 1589 ADVERTISE_1000FULL, val); 1590 if (ret < 0) 1591 return ret; 1592 if (ret > 0) 1593 changed = true; 1594 1595 return genphy_c45_check_and_restart_aneg(phydev, changed); 1596 } 1597 1598 static int rtl822x_c45_read_status(struct phy_device *phydev) 1599 { 1600 int ret, val; 1601 1602 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1603 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1604 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1605 RTL822X_VND2_C22_REG(MII_STAT1000)); 1606 if (val < 0) 1607 return val; 1608 } else { 1609 val = 0; 1610 } 1611 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1612 1613 ret = genphy_c45_read_status(phydev); 1614 if (ret < 0) 1615 return ret; 1616 1617 if (!phydev->link) { 1618 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1619 return 0; 1620 } 1621 1622 /* Read actual speed from vendor register. */ 1623 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1624 RTL822X_VND2_C22_REG(RTL_PHYSR)); 1625 if (val < 0) 1626 return val; 1627 1628 rtlgen_decode_physr(phydev, val); 1629 1630 return 0; 1631 } 1632 1633 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1634 { 1635 int ret, val; 1636 1637 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1638 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1639 if (ret < 0) 1640 return ret; 1641 1642 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1643 MDIO_CTRL1, val, 1644 !(val & MDIO_CTRL1_RESET), 1645 5000, 100000, true); 1646 } 1647 1648 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1649 { 1650 int ret; 1651 1652 ret = rtl822x_c45_read_status(phydev); 1653 if (ret < 0) 1654 return ret; 1655 1656 rtl822xb_update_interface(phydev); 1657 1658 return 0; 1659 } 1660 1661 static int rtl8224_cable_test_start(struct phy_device *phydev) 1662 { 1663 u32 val; 1664 int ret; 1665 1666 /* disable auto-negotiation and force 1000/Full */ 1667 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1668 RTL822X_VND2_C22_REG(MII_BMCR), 1669 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1670 BMCR_SPEED1000 | BMCR_FULLDPLX); 1671 if (ret) 1672 return ret; 1673 1674 mdelay(500); 1675 1676 /* trigger cable test */ 1677 val = RTL8224_MII_RTCT_ENABLE; 1678 val |= RTL8224_MII_RTCT_PAIR_A; 1679 val |= RTL8224_MII_RTCT_PAIR_B; 1680 val |= RTL8224_MII_RTCT_PAIR_C; 1681 val |= RTL8224_MII_RTCT_PAIR_D; 1682 1683 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1684 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1685 RTL8224_MII_RTCT_DONE, val); 1686 } 1687 1688 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1689 { 1690 int ret; 1691 1692 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1693 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1694 reg); 1695 if (ret) 1696 return ret; 1697 1698 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1699 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1700 } 1701 1702 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1703 { 1704 int cable_len; 1705 u32 reg_len; 1706 int ret; 1707 u32 cm; 1708 1709 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1710 1711 ret = rtl8224_sram_read(phydev, reg_len); 1712 if (ret < 0) 1713 return ret; 1714 1715 cable_len = ret & 0xff00; 1716 1717 ret = rtl8224_sram_read(phydev, reg_len + 1); 1718 if (ret < 0) 1719 return ret; 1720 1721 cable_len |= (ret & 0xff00) >> 8; 1722 1723 cable_len -= 620; 1724 cable_len = max(cable_len, 0); 1725 1726 cm = cable_len * 100 / 78; 1727 1728 return cm; 1729 } 1730 1731 static int rtl8224_cable_test_result_trans(u32 result) 1732 { 1733 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1734 return -EBUSY; 1735 1736 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1737 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1738 1739 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1740 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1741 1742 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1743 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1744 1745 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1746 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1747 1748 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1749 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1750 1751 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1752 } 1753 1754 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1755 { 1756 int fault_rslt; 1757 int ret; 1758 1759 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1760 if (ret < 0) 1761 return ret; 1762 1763 fault_rslt = rtl8224_cable_test_result_trans(ret); 1764 if (fault_rslt < 0) 1765 return 0; 1766 1767 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1768 if (ret < 0) 1769 return ret; 1770 1771 switch (fault_rslt) { 1772 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1773 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1774 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1775 ret = rtl8224_pair_len_get(phydev, pair); 1776 if (ret < 0) 1777 return ret; 1778 1779 return ethnl_cable_test_fault_length(phydev, pair, ret); 1780 default: 1781 return 0; 1782 } 1783 } 1784 1785 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1786 { 1787 unsigned int pair; 1788 int ret; 1789 1790 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1791 ret = rtl8224_cable_test_report_pair(phydev, pair); 1792 if (ret == -EBUSY) { 1793 *finished = false; 1794 return 0; 1795 } 1796 1797 if (ret < 0) 1798 return ret; 1799 } 1800 1801 return 0; 1802 } 1803 1804 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1805 { 1806 int ret; 1807 1808 *finished = false; 1809 1810 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1811 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1812 if (ret < 0) 1813 return ret; 1814 1815 if (!(ret & RTL8224_MII_RTCT_DONE)) 1816 return 0; 1817 1818 *finished = true; 1819 1820 return rtl8224_cable_test_report(phydev, finished); 1821 } 1822 1823 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1824 { 1825 int val; 1826 1827 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1828 val = phy_read(phydev, 0x13); 1829 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1830 1831 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1832 } 1833 1834 /* On internal PHY's MMD reads over C22 always return 0. 1835 * Check a MMD register which is known to be non-zero. 1836 */ 1837 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1838 { 1839 int val; 1840 1841 phy_lock_mdio_bus(phydev); 1842 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1843 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1844 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1845 val = __phy_read(phydev, MII_MMD_DATA); 1846 phy_unlock_mdio_bus(phydev); 1847 1848 return val > 0; 1849 } 1850 1851 static int rtlgen_match_phy_device(struct phy_device *phydev, 1852 const struct phy_driver *phydrv) 1853 { 1854 return phydev->phy_id == RTL_GENERIC_PHYID && 1855 !rtlgen_supports_2_5gbps(phydev); 1856 } 1857 1858 static int rtl8226_match_phy_device(struct phy_device *phydev, 1859 const struct phy_driver *phydrv) 1860 { 1861 return phydev->phy_id == RTL_GENERIC_PHYID && 1862 rtlgen_supports_2_5gbps(phydev) && 1863 rtlgen_supports_mmd(phydev); 1864 } 1865 1866 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1867 bool is_c45) 1868 { 1869 if (phydev->is_c45) 1870 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1871 else 1872 return !is_c45 && (id == phydev->phy_id); 1873 } 1874 1875 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1876 const struct phy_driver *phydrv) 1877 { 1878 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1879 } 1880 1881 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 1882 const struct phy_driver *phydrv) 1883 { 1884 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 1885 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1886 } 1887 1888 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 1889 const struct phy_driver *phydrv) 1890 { 1891 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 1892 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1893 } 1894 1895 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1896 const struct phy_driver *phydrv) 1897 { 1898 if (phydev->is_c45) 1899 return false; 1900 1901 switch (phydev->phy_id) { 1902 case RTL_GENERIC_PHYID: 1903 case RTL_8221B: 1904 case RTL_8251B: 1905 case RTL_8261C: 1906 case 0x001cc841: 1907 break; 1908 default: 1909 return false; 1910 } 1911 1912 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1913 } 1914 1915 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1916 const struct phy_driver *phydrv) 1917 { 1918 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1919 } 1920 1921 static int rtlgen_resume(struct phy_device *phydev) 1922 { 1923 int ret = genphy_resume(phydev); 1924 1925 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1926 msleep(20); 1927 1928 return ret; 1929 } 1930 1931 static int rtlgen_c45_resume(struct phy_device *phydev) 1932 { 1933 int ret = genphy_c45_pma_resume(phydev); 1934 1935 msleep(20); 1936 1937 return ret; 1938 } 1939 1940 static int rtl9000a_config_init(struct phy_device *phydev) 1941 { 1942 phydev->autoneg = AUTONEG_DISABLE; 1943 phydev->speed = SPEED_100; 1944 phydev->duplex = DUPLEX_FULL; 1945 1946 return 0; 1947 } 1948 1949 static int rtl9000a_config_aneg(struct phy_device *phydev) 1950 { 1951 int ret; 1952 u16 ctl = 0; 1953 1954 switch (phydev->master_slave_set) { 1955 case MASTER_SLAVE_CFG_MASTER_FORCE: 1956 ctl |= CTL1000_AS_MASTER; 1957 break; 1958 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1959 break; 1960 case MASTER_SLAVE_CFG_UNKNOWN: 1961 case MASTER_SLAVE_CFG_UNSUPPORTED: 1962 return 0; 1963 default: 1964 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1965 return -EOPNOTSUPP; 1966 } 1967 1968 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1969 if (ret == 1) 1970 ret = genphy_soft_reset(phydev); 1971 1972 return ret; 1973 } 1974 1975 static int rtl9000a_read_status(struct phy_device *phydev) 1976 { 1977 int ret; 1978 1979 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1980 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1981 1982 ret = genphy_update_link(phydev); 1983 if (ret) 1984 return ret; 1985 1986 ret = phy_read(phydev, MII_CTRL1000); 1987 if (ret < 0) 1988 return ret; 1989 if (ret & CTL1000_AS_MASTER) 1990 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1991 else 1992 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1993 1994 ret = phy_read(phydev, MII_STAT1000); 1995 if (ret < 0) 1996 return ret; 1997 if (ret & LPA_1000MSRES) 1998 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1999 else 2000 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2001 2002 return 0; 2003 } 2004 2005 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2006 { 2007 int err; 2008 2009 err = phy_read(phydev, RTL8211F_INSR); 2010 2011 return (err < 0) ? err : 0; 2012 } 2013 2014 static int rtl9000a_config_intr(struct phy_device *phydev) 2015 { 2016 u16 val; 2017 int err; 2018 2019 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2020 err = rtl9000a_ack_interrupt(phydev); 2021 if (err) 2022 return err; 2023 2024 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2025 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2026 } else { 2027 val = ~0; 2028 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2029 if (err) 2030 return err; 2031 2032 err = rtl9000a_ack_interrupt(phydev); 2033 } 2034 2035 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2036 } 2037 2038 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2039 { 2040 int irq_status; 2041 2042 irq_status = phy_read(phydev, RTL8211F_INSR); 2043 if (irq_status < 0) { 2044 phy_error(phydev); 2045 return IRQ_NONE; 2046 } 2047 2048 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2049 return IRQ_NONE; 2050 2051 phy_trigger_machine(phydev); 2052 2053 return IRQ_HANDLED; 2054 } 2055 2056 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2057 { 2058 int err; 2059 2060 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2061 2062 return (err < 0) ? err : 0; 2063 } 2064 2065 static int rtl8221b_config_intr(struct phy_device *phydev) 2066 { 2067 int err; 2068 2069 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2070 err = rtl8221b_ack_interrupt(phydev); 2071 if (err) 2072 return err; 2073 2074 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2075 RTL8221B_VND2_INER_LINK_STATUS); 2076 } else { 2077 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2078 RTL8221B_VND2_INER, 0); 2079 if (err) 2080 return err; 2081 2082 err = rtl8221b_ack_interrupt(phydev); 2083 } 2084 2085 return err; 2086 } 2087 2088 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2089 { 2090 int err; 2091 2092 err = rtl8221b_ack_interrupt(phydev); 2093 if (err) { 2094 phy_error(phydev); 2095 return IRQ_NONE; 2096 } 2097 2098 phy_trigger_machine(phydev); 2099 2100 return IRQ_HANDLED; 2101 } 2102 2103 static int rtlgen_sfp_get_features(struct phy_device *phydev) 2104 { 2105 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2106 phydev->supported); 2107 2108 /* set default mode */ 2109 phydev->speed = SPEED_10000; 2110 phydev->duplex = DUPLEX_FULL; 2111 2112 phydev->port = PORT_FIBRE; 2113 2114 return 0; 2115 } 2116 2117 static int rtlgen_sfp_read_status(struct phy_device *phydev) 2118 { 2119 int val, err; 2120 2121 err = genphy_update_link(phydev); 2122 if (err) 2123 return err; 2124 2125 if (!phydev->link) 2126 return 0; 2127 2128 val = phy_read(phydev, RTL_PHYSR); 2129 if (val < 0) 2130 return val; 2131 2132 rtlgen_decode_physr(phydev, val); 2133 2134 return 0; 2135 } 2136 2137 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 2138 { 2139 return 0; 2140 } 2141 2142 static struct phy_driver realtek_drvs[] = { 2143 { 2144 PHY_ID_MATCH_EXACT(0x00008201), 2145 .name = "RTL8201CP Ethernet", 2146 .read_page = rtl821x_read_page, 2147 .write_page = rtl821x_write_page, 2148 }, { 2149 PHY_ID_MATCH_EXACT(0x001cc816), 2150 .name = "RTL8201F Fast Ethernet", 2151 .config_intr = &rtl8201_config_intr, 2152 .handle_interrupt = rtl8201_handle_interrupt, 2153 .suspend = genphy_suspend, 2154 .resume = genphy_resume, 2155 .read_page = rtl821x_read_page, 2156 .write_page = rtl821x_write_page, 2157 }, { 2158 PHY_ID_MATCH_MODEL(0x001cc880), 2159 .name = "RTL8208 Fast Ethernet", 2160 .read_mmd = genphy_read_mmd_unsupported, 2161 .write_mmd = genphy_write_mmd_unsupported, 2162 .suspend = genphy_suspend, 2163 .resume = genphy_resume, 2164 .read_page = rtl821x_read_page, 2165 .write_page = rtl821x_write_page, 2166 }, { 2167 PHY_ID_MATCH_EXACT(0x001cc910), 2168 .name = "RTL8211 Gigabit Ethernet", 2169 .config_aneg = rtl8211_config_aneg, 2170 .read_mmd = &genphy_read_mmd_unsupported, 2171 .write_mmd = &genphy_write_mmd_unsupported, 2172 .read_page = rtl821x_read_page, 2173 .write_page = rtl821x_write_page, 2174 }, { 2175 PHY_ID_MATCH_EXACT(0x001cc912), 2176 .name = "RTL8211B Gigabit Ethernet", 2177 .config_intr = &rtl8211b_config_intr, 2178 .handle_interrupt = rtl821x_handle_interrupt, 2179 .read_mmd = &genphy_read_mmd_unsupported, 2180 .write_mmd = &genphy_write_mmd_unsupported, 2181 .suspend = rtl8211b_suspend, 2182 .resume = rtl8211b_resume, 2183 .read_page = rtl821x_read_page, 2184 .write_page = rtl821x_write_page, 2185 }, { 2186 PHY_ID_MATCH_EXACT(0x001cc913), 2187 .name = "RTL8211C Gigabit Ethernet", 2188 .config_init = rtl8211c_config_init, 2189 .read_mmd = &genphy_read_mmd_unsupported, 2190 .write_mmd = &genphy_write_mmd_unsupported, 2191 .read_page = rtl821x_read_page, 2192 .write_page = rtl821x_write_page, 2193 }, { 2194 PHY_ID_MATCH_EXACT(0x001cc914), 2195 .name = "RTL8211DN Gigabit Ethernet", 2196 .config_intr = rtl8211e_config_intr, 2197 .handle_interrupt = rtl821x_handle_interrupt, 2198 .suspend = genphy_suspend, 2199 .resume = genphy_resume, 2200 .read_page = rtl821x_read_page, 2201 .write_page = rtl821x_write_page, 2202 }, { 2203 PHY_ID_MATCH_EXACT(0x001cc915), 2204 .name = "RTL8211E Gigabit Ethernet", 2205 .config_init = &rtl8211e_config_init, 2206 .config_intr = &rtl8211e_config_intr, 2207 .handle_interrupt = rtl821x_handle_interrupt, 2208 .suspend = genphy_suspend, 2209 .resume = genphy_resume, 2210 .read_page = rtl821x_read_page, 2211 .write_page = rtl821x_write_page, 2212 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2213 .led_hw_control_get = rtl8211e_led_hw_control_get, 2214 .led_hw_control_set = rtl8211e_led_hw_control_set, 2215 }, { 2216 PHY_ID_MATCH_EXACT(0x001cc916), 2217 .name = "RTL8211F Gigabit Ethernet", 2218 .probe = rtl8211f_probe, 2219 .config_init = &rtl8211f_config_init, 2220 .read_status = rtlgen_read_status, 2221 .config_intr = &rtl8211f_config_intr, 2222 .handle_interrupt = rtl8211f_handle_interrupt, 2223 .set_wol = rtl8211f_set_wol, 2224 .get_wol = rtl8211f_get_wol, 2225 .suspend = rtl8211f_suspend, 2226 .resume = rtl8211f_resume, 2227 .read_page = rtl821x_read_page, 2228 .write_page = rtl821x_write_page, 2229 .flags = PHY_ALWAYS_CALL_SUSPEND, 2230 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2231 .led_hw_control_get = rtl8211f_led_hw_control_get, 2232 .led_hw_control_set = rtl8211f_led_hw_control_set, 2233 }, { 2234 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2235 .name = "RTL8211F-VD Gigabit Ethernet", 2236 .probe = rtl821x_probe, 2237 .config_init = &rtl8211f_config_init, 2238 .read_status = rtlgen_read_status, 2239 .config_intr = &rtl8211f_config_intr, 2240 .handle_interrupt = rtl8211f_handle_interrupt, 2241 .suspend = rtl821x_suspend, 2242 .resume = rtl821x_resume, 2243 .read_page = rtl821x_read_page, 2244 .write_page = rtl821x_write_page, 2245 .flags = PHY_ALWAYS_CALL_SUSPEND, 2246 }, { 2247 .name = "Generic FE-GE Realtek PHY", 2248 .match_phy_device = rtlgen_match_phy_device, 2249 .read_status = rtlgen_read_status, 2250 .suspend = genphy_suspend, 2251 .resume = rtlgen_resume, 2252 .read_page = rtl821x_read_page, 2253 .write_page = rtl821x_write_page, 2254 .read_mmd = rtlgen_read_mmd, 2255 .write_mmd = rtlgen_write_mmd, 2256 }, { 2257 .name = "RTL8226 2.5Gbps PHY", 2258 .match_phy_device = rtl8226_match_phy_device, 2259 .get_features = rtl822x_get_features, 2260 .config_aneg = rtl822x_config_aneg, 2261 .read_status = rtl822x_read_status, 2262 .suspend = genphy_suspend, 2263 .resume = rtlgen_resume, 2264 .read_page = rtl821x_read_page, 2265 .write_page = rtl821x_write_page, 2266 .read_mmd = rtl822xb_read_mmd, 2267 .write_mmd = rtl822xb_write_mmd, 2268 }, { 2269 .match_phy_device = rtl8221b_match_phy_device, 2270 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2271 .get_features = rtl822x_get_features, 2272 .config_aneg = rtl822x_config_aneg, 2273 .config_init = rtl822xb_config_init, 2274 .inband_caps = rtl822x_inband_caps, 2275 .config_inband = rtl822x_config_inband, 2276 .get_rate_matching = rtl822xb_get_rate_matching, 2277 .read_status = rtl822xb_read_status, 2278 .suspend = genphy_suspend, 2279 .resume = rtlgen_resume, 2280 .read_page = rtl821x_read_page, 2281 .write_page = rtl821x_write_page, 2282 .read_mmd = rtl822xb_read_mmd, 2283 .write_mmd = rtl822xb_write_mmd, 2284 }, { 2285 PHY_ID_MATCH_EXACT(0x001cc838), 2286 .name = "RTL8226-CG 2.5Gbps PHY", 2287 .soft_reset = rtl822x_c45_soft_reset, 2288 .get_features = rtl822x_c45_get_features, 2289 .config_aneg = rtl822x_c45_config_aneg, 2290 .config_init = rtl822x_config_init, 2291 .inband_caps = rtl822x_inband_caps, 2292 .config_inband = rtl822x_config_inband, 2293 .read_status = rtl822xb_c45_read_status, 2294 .suspend = genphy_c45_pma_suspend, 2295 .resume = rtlgen_c45_resume, 2296 .read_mmd = rtl822xb_read_mmd, 2297 .write_mmd = rtl822xb_write_mmd, 2298 }, { 2299 PHY_ID_MATCH_EXACT(0x001cc848), 2300 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2301 .get_features = rtl822x_get_features, 2302 .config_aneg = rtl822x_config_aneg, 2303 .config_init = rtl822xb_config_init, 2304 .inband_caps = rtl822x_inband_caps, 2305 .config_inband = rtl822x_config_inband, 2306 .get_rate_matching = rtl822xb_get_rate_matching, 2307 .read_status = rtl822xb_read_status, 2308 .suspend = genphy_suspend, 2309 .resume = rtlgen_resume, 2310 .read_page = rtl821x_read_page, 2311 .write_page = rtl821x_write_page, 2312 .read_mmd = rtl822xb_read_mmd, 2313 .write_mmd = rtl822xb_write_mmd, 2314 }, { 2315 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 2316 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 2317 .config_intr = rtl8221b_config_intr, 2318 .handle_interrupt = rtl8221b_handle_interrupt, 2319 .probe = rtl822x_probe, 2320 .config_init = rtl822xb_config_init, 2321 .inband_caps = rtl822x_inband_caps, 2322 .config_inband = rtl822x_config_inband, 2323 .get_rate_matching = rtl822xb_get_rate_matching, 2324 .get_features = rtl822x_c45_get_features, 2325 .config_aneg = rtl822x_c45_config_aneg, 2326 .read_status = rtl822xb_c45_read_status, 2327 .suspend = genphy_c45_pma_suspend, 2328 .resume = rtlgen_c45_resume, 2329 .read_page = rtl821x_read_page, 2330 .write_page = rtl821x_write_page, 2331 .read_mmd = rtl822xb_read_mmd, 2332 .write_mmd = rtl822xb_write_mmd, 2333 }, { 2334 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 2335 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 2336 .config_intr = rtl8221b_config_intr, 2337 .handle_interrupt = rtl8221b_handle_interrupt, 2338 .probe = rtl822x_probe, 2339 .config_init = rtl822xb_config_init, 2340 .inband_caps = rtl822x_inband_caps, 2341 .config_inband = rtl822x_config_inband, 2342 .get_rate_matching = rtl822xb_get_rate_matching, 2343 .get_features = rtl822x_c45_get_features, 2344 .config_aneg = rtl822x_c45_config_aneg, 2345 .read_status = rtl822xb_c45_read_status, 2346 .suspend = genphy_c45_pma_suspend, 2347 .resume = rtlgen_c45_resume, 2348 .read_page = rtl821x_read_page, 2349 .write_page = rtl821x_write_page, 2350 .read_mmd = rtl822xb_read_mmd, 2351 .write_mmd = rtl822xb_write_mmd, 2352 }, { 2353 .match_phy_device = rtl8251b_c45_match_phy_device, 2354 .name = "RTL8251B 5Gbps PHY", 2355 .probe = rtl822x_probe, 2356 .get_features = rtl822x_get_features, 2357 .config_aneg = rtl822x_config_aneg, 2358 .read_status = rtl822x_read_status, 2359 .suspend = genphy_suspend, 2360 .resume = rtlgen_resume, 2361 .read_page = rtl821x_read_page, 2362 .write_page = rtl821x_write_page, 2363 }, { 2364 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2365 .name = "Realtek Internal NBASE-T PHY", 2366 .flags = PHY_IS_INTERNAL, 2367 .probe = rtl822x_probe, 2368 .get_features = rtl822x_get_features, 2369 .config_aneg = rtl822x_config_aneg, 2370 .read_status = rtl822x_read_status, 2371 .suspend = genphy_suspend, 2372 .resume = rtlgen_resume, 2373 .read_page = rtl821x_read_page, 2374 .write_page = rtl821x_write_page, 2375 .read_mmd = rtl822x_read_mmd, 2376 .write_mmd = rtl822x_write_mmd, 2377 }, { 2378 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 2379 .name = "Realtek SFP PHY Mode", 2380 .flags = PHY_IS_INTERNAL, 2381 .probe = rtl822x_probe, 2382 .get_features = rtlgen_sfp_get_features, 2383 .config_aneg = rtlgen_sfp_config_aneg, 2384 .read_status = rtlgen_sfp_read_status, 2385 .suspend = genphy_suspend, 2386 .resume = rtlgen_resume, 2387 .read_page = rtl821x_read_page, 2388 .write_page = rtl821x_write_page, 2389 .read_mmd = rtl822x_read_mmd, 2390 .write_mmd = rtl822x_write_mmd, 2391 }, { 2392 PHY_ID_MATCH_EXACT(0x001ccad0), 2393 .name = "RTL8224 2.5Gbps PHY", 2394 .flags = PHY_POLL_CABLE_TEST, 2395 .get_features = rtl822x_c45_get_features, 2396 .config_aneg = rtl822x_c45_config_aneg, 2397 .read_status = rtl822x_c45_read_status, 2398 .suspend = genphy_c45_pma_suspend, 2399 .resume = rtlgen_c45_resume, 2400 .cable_test_start = rtl8224_cable_test_start, 2401 .cable_test_get_status = rtl8224_cable_test_get_status, 2402 }, { 2403 PHY_ID_MATCH_EXACT(0x001cc961), 2404 .name = "RTL8366RB Gigabit Ethernet", 2405 .config_init = &rtl8366rb_config_init, 2406 /* These interrupts are handled by the irq controller 2407 * embedded inside the RTL8366RB, they get unmasked when the 2408 * irq is requested and ACKed by reading the status register, 2409 * which is done by the irqchip code. 2410 */ 2411 .config_intr = genphy_no_config_intr, 2412 .handle_interrupt = genphy_handle_interrupt_no_ack, 2413 .suspend = genphy_suspend, 2414 .resume = genphy_resume, 2415 }, { 2416 PHY_ID_MATCH_EXACT(0x001ccb00), 2417 .name = "RTL9000AA_RTL9000AN Ethernet", 2418 .features = PHY_BASIC_T1_FEATURES, 2419 .config_init = rtl9000a_config_init, 2420 .config_aneg = rtl9000a_config_aneg, 2421 .read_status = rtl9000a_read_status, 2422 .config_intr = rtl9000a_config_intr, 2423 .handle_interrupt = rtl9000a_handle_interrupt, 2424 .suspend = genphy_suspend, 2425 .resume = genphy_resume, 2426 .read_page = rtl821x_read_page, 2427 .write_page = rtl821x_write_page, 2428 }, { 2429 PHY_ID_MATCH_EXACT(0x001cc942), 2430 .name = "RTL8365MB-VC Gigabit Ethernet", 2431 /* Interrupt handling analogous to RTL8366RB */ 2432 .config_intr = genphy_no_config_intr, 2433 .handle_interrupt = genphy_handle_interrupt_no_ack, 2434 .suspend = genphy_suspend, 2435 .resume = genphy_resume, 2436 }, { 2437 PHY_ID_MATCH_EXACT(0x001cc960), 2438 .name = "RTL8366S Gigabit Ethernet", 2439 .suspend = genphy_suspend, 2440 .resume = genphy_resume, 2441 .read_mmd = genphy_read_mmd_unsupported, 2442 .write_mmd = genphy_write_mmd_unsupported, 2443 }, 2444 }; 2445 2446 module_phy_driver(realtek_drvs); 2447 2448 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2449 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2450 { } 2451 }; 2452 2453 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2454