1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 21 #include "realtek.h" 22 23 #define RTL8201F_IER 0x13 24 25 #define RTL8201F_ISR 0x1e 26 #define RTL8201F_ISR_ANERR BIT(15) 27 #define RTL8201F_ISR_DUPLEX BIT(13) 28 #define RTL8201F_ISR_LINK BIT(11) 29 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 30 RTL8201F_ISR_DUPLEX | \ 31 RTL8201F_ISR_LINK) 32 33 #define RTL821x_INER 0x12 34 #define RTL8211B_INER_INIT 0x6400 35 #define RTL8211E_INER_LINK_STATUS BIT(10) 36 #define RTL8211F_INER_PME BIT(7) 37 #define RTL8211F_INER_LINK_STATUS BIT(4) 38 39 #define RTL821x_INSR 0x13 40 41 #define RTL821x_EXT_PAGE_SELECT 0x1e 42 43 #define RTL821x_PAGE_SELECT 0x1f 44 #define RTL821x_SET_EXT_PAGE 0x07 45 46 /* RTL8211E extension page 44/0x2c */ 47 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 48 #define RTL8211E_LEDCR1 0x1a 49 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 50 #define RTL8211E_LEDCR1_MASK BIT(4) 51 #define RTL8211E_LEDCR1_SHIFT 1 52 53 #define RTL8211E_LEDCR2 0x1c 54 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 55 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 56 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 57 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 58 #define RTL8211E_LEDCR2_SHIFT 4 59 60 /* RTL8211E extension page 164/0xa4 */ 61 #define RTL8211E_RGMII_EXT_PAGE 0xa4 62 #define RTL8211E_RGMII_DELAY 0x1c 63 #define RTL8211E_CTRL_DELAY BIT(13) 64 #define RTL8211E_TX_DELAY BIT(12) 65 #define RTL8211E_RX_DELAY BIT(11) 66 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 67 68 /* RTL8211F PHY configuration */ 69 #define RTL8211F_PHYCR_PAGE 0xa43 70 #define RTL8211F_PHYCR1 0x18 71 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 72 #define RTL8211F_ALDPS_ENABLE BIT(2) 73 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 74 75 #define RTL8211F_PHYCR2 0x19 76 #define RTL8211F_CLKOUT_EN BIT(0) 77 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 78 79 #define RTL8211F_INSR_PAGE 0xa43 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 94 * to undocumented register pages. The names here do not reflect the datasheet. 95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 96 */ 97 #define RTL8211FVD_CLKOUT_PAGE 0xd05 98 #define RTL8211FVD_CLKOUT_REG 0x11 99 #define RTL8211FVD_CLKOUT_EN BIT(8) 100 101 /* RTL8211F RGMII configuration */ 102 #define RTL8211F_RGMII_PAGE 0xd08 103 104 #define RTL8211F_TXCR 0x11 105 #define RTL8211F_TX_DELAY BIT(8) 106 107 #define RTL8211F_RXCR 0x15 108 #define RTL8211F_RX_DELAY BIT(3) 109 110 /* RTL8211F WOL settings */ 111 #define RTL8211F_WOL_PAGE 0xd8a 112 #define RTL8211F_WOL_SETTINGS_EVENTS 16 113 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 114 #define RTL8211F_WOL_RST_RMSQ 17 115 #define RTL8211F_WOL_RG_RSTB BIT(15) 116 #define RTL8211F_WOL_RMSQ 0x1fff 117 118 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 119 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 120 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 121 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 122 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 123 124 #define RTL822X_VND1_SERDES_OPTION 0x697a 125 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 126 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 128 129 #define RTL822X_VND1_SERDES_CTRL3 0x7580 130 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 131 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 132 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 133 134 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 135 * is set, they cannot be accessed by C45-over-C22. 136 */ 137 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 138 139 #define RTL8221B_VND2_INER 0xa4d2 140 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 141 142 #define RTL8221B_VND2_INSR 0xa4d4 143 144 #define RTL8224_MII_RTCT 0x11 145 #define RTL8224_MII_RTCT_ENABLE BIT(0) 146 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 147 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 148 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 149 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 150 #define RTL8224_MII_RTCT_DONE BIT(15) 151 152 #define RTL8224_MII_SRAM_ADDR 0x1b 153 #define RTL8224_MII_SRAM_DATA 0x1c 154 155 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 156 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 157 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 158 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 159 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 160 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 161 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 162 163 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 164 165 #define RTL8366RB_POWER_SAVE 0x15 166 #define RTL8366RB_POWER_SAVE_ON BIT(12) 167 168 #define RTL9000A_GINMR 0x14 169 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 170 171 #define RTL_VND2_PHYSR 0xa434 172 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 173 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 174 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 175 #define RTL_VND2_PHYSR_MASTER BIT(11) 176 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 177 178 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 179 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 180 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 181 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 182 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 183 #define RTL_MDIO_PMA_SPEED 0xa616 184 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 185 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 186 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 187 188 #define RTL_GENERIC_PHYID 0x001cc800 189 #define RTL_8211FVD_PHYID 0x001cc878 190 #define RTL_8221B 0x001cc840 191 #define RTL_8221B_VB_CG 0x001cc849 192 #define RTL_8221B_VM_CG 0x001cc84a 193 #define RTL_8251B 0x001cc862 194 #define RTL_8261C 0x001cc890 195 196 /* RTL8211E and RTL8211F support up to three LEDs */ 197 #define RTL8211x_LED_COUNT 3 198 199 MODULE_DESCRIPTION("Realtek PHY driver"); 200 MODULE_AUTHOR("Johnson Leung"); 201 MODULE_LICENSE("GPL"); 202 203 struct rtl821x_priv { 204 bool enable_aldps; 205 bool disable_clk_out; 206 struct clk *clk; 207 /* rtl8211f */ 208 u16 iner; 209 }; 210 211 static int rtl821x_read_page(struct phy_device *phydev) 212 { 213 return __phy_read(phydev, RTL821x_PAGE_SELECT); 214 } 215 216 static int rtl821x_write_page(struct phy_device *phydev, int page) 217 { 218 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 219 } 220 221 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 222 u32 regnum) 223 { 224 int oldpage, ret = 0; 225 226 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 227 if (oldpage >= 0) { 228 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 229 if (ret == 0) 230 ret = __phy_read(phydev, regnum); 231 } 232 233 return phy_restore_page(phydev, oldpage, ret); 234 } 235 236 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 237 u32 regnum, u16 mask, u16 set) 238 { 239 int oldpage, ret = 0; 240 241 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 242 if (oldpage >= 0) { 243 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 244 if (ret == 0) 245 ret = __phy_modify(phydev, regnum, mask, set); 246 } 247 248 return phy_restore_page(phydev, oldpage, ret); 249 } 250 251 static int rtl821x_probe(struct phy_device *phydev) 252 { 253 struct device *dev = &phydev->mdio.dev; 254 struct rtl821x_priv *priv; 255 256 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 257 if (!priv) 258 return -ENOMEM; 259 260 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 261 if (IS_ERR(priv->clk)) 262 return dev_err_probe(dev, PTR_ERR(priv->clk), 263 "failed to get phy clock\n"); 264 265 priv->enable_aldps = of_property_read_bool(dev->of_node, 266 "realtek,aldps-enable"); 267 priv->disable_clk_out = of_property_read_bool(dev->of_node, 268 "realtek,clkout-disable"); 269 270 phydev->priv = priv; 271 272 return 0; 273 } 274 275 static int rtl8211f_probe(struct phy_device *phydev) 276 { 277 struct device *dev = &phydev->mdio.dev; 278 int ret; 279 280 ret = rtl821x_probe(phydev); 281 if (ret < 0) 282 return ret; 283 284 /* Disable all PME events */ 285 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 286 RTL8211F_WOL_SETTINGS_EVENTS, 0); 287 if (ret < 0) 288 return ret; 289 290 /* Mark this PHY as wakeup capable and register the interrupt as a 291 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 292 * and the interrupt is valid. 293 */ 294 if (device_property_read_bool(dev, "wakeup-source") && 295 phy_interrupt_is_valid(phydev)) { 296 device_set_wakeup_capable(dev, true); 297 devm_pm_set_wake_irq(dev, phydev->irq); 298 } 299 300 return ret; 301 } 302 303 static int rtl8201_ack_interrupt(struct phy_device *phydev) 304 { 305 int err; 306 307 err = phy_read(phydev, RTL8201F_ISR); 308 309 return (err < 0) ? err : 0; 310 } 311 312 static int rtl821x_ack_interrupt(struct phy_device *phydev) 313 { 314 int err; 315 316 err = phy_read(phydev, RTL821x_INSR); 317 318 return (err < 0) ? err : 0; 319 } 320 321 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 322 { 323 int err; 324 325 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 326 327 return (err < 0) ? err : 0; 328 } 329 330 static int rtl8201_config_intr(struct phy_device *phydev) 331 { 332 u16 val; 333 int err; 334 335 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 336 err = rtl8201_ack_interrupt(phydev); 337 if (err) 338 return err; 339 340 val = BIT(13) | BIT(12) | BIT(11); 341 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 342 } else { 343 val = 0; 344 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 345 if (err) 346 return err; 347 348 err = rtl8201_ack_interrupt(phydev); 349 } 350 351 return err; 352 } 353 354 static int rtl8211b_config_intr(struct phy_device *phydev) 355 { 356 int err; 357 358 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 359 err = rtl821x_ack_interrupt(phydev); 360 if (err) 361 return err; 362 363 err = phy_write(phydev, RTL821x_INER, 364 RTL8211B_INER_INIT); 365 } else { 366 err = phy_write(phydev, RTL821x_INER, 0); 367 if (err) 368 return err; 369 370 err = rtl821x_ack_interrupt(phydev); 371 } 372 373 return err; 374 } 375 376 static int rtl8211e_config_intr(struct phy_device *phydev) 377 { 378 int err; 379 380 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 381 err = rtl821x_ack_interrupt(phydev); 382 if (err) 383 return err; 384 385 err = phy_write(phydev, RTL821x_INER, 386 RTL8211E_INER_LINK_STATUS); 387 } else { 388 err = phy_write(phydev, RTL821x_INER, 0); 389 if (err) 390 return err; 391 392 err = rtl821x_ack_interrupt(phydev); 393 } 394 395 return err; 396 } 397 398 static int rtl8211f_config_intr(struct phy_device *phydev) 399 { 400 struct rtl821x_priv *priv = phydev->priv; 401 u16 val; 402 int err; 403 404 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 405 err = rtl8211f_ack_interrupt(phydev); 406 if (err) 407 return err; 408 409 val = RTL8211F_INER_LINK_STATUS; 410 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 411 if (err == 0) 412 priv->iner = val; 413 } else { 414 priv->iner = val = 0; 415 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 416 if (err) 417 return err; 418 419 err = rtl8211f_ack_interrupt(phydev); 420 } 421 422 return err; 423 } 424 425 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 426 { 427 int irq_status; 428 429 irq_status = phy_read(phydev, RTL8201F_ISR); 430 if (irq_status < 0) { 431 phy_error(phydev); 432 return IRQ_NONE; 433 } 434 435 if (!(irq_status & RTL8201F_ISR_MASK)) 436 return IRQ_NONE; 437 438 phy_trigger_machine(phydev); 439 440 return IRQ_HANDLED; 441 } 442 443 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 444 { 445 int irq_status, irq_enabled; 446 447 irq_status = phy_read(phydev, RTL821x_INSR); 448 if (irq_status < 0) { 449 phy_error(phydev); 450 return IRQ_NONE; 451 } 452 453 irq_enabled = phy_read(phydev, RTL821x_INER); 454 if (irq_enabled < 0) { 455 phy_error(phydev); 456 return IRQ_NONE; 457 } 458 459 if (!(irq_status & irq_enabled)) 460 return IRQ_NONE; 461 462 phy_trigger_machine(phydev); 463 464 return IRQ_HANDLED; 465 } 466 467 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 468 { 469 int irq_status; 470 471 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 472 if (irq_status < 0) { 473 phy_error(phydev); 474 return IRQ_NONE; 475 } 476 477 if (irq_status & RTL8211F_INER_LINK_STATUS) { 478 phy_trigger_machine(phydev); 479 return IRQ_HANDLED; 480 } 481 482 if (irq_status & RTL8211F_INER_PME) { 483 pm_wakeup_event(&phydev->mdio.dev, 0); 484 return IRQ_HANDLED; 485 } 486 487 return IRQ_NONE; 488 } 489 490 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 491 { 492 int wol_events; 493 494 /* If the PHY is not capable of waking the system, then WoL can not 495 * be supported. 496 */ 497 if (!device_can_wakeup(&dev->mdio.dev)) { 498 wol->supported = 0; 499 return; 500 } 501 502 wol->supported = WAKE_MAGIC; 503 504 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 505 if (wol_events < 0) 506 return; 507 508 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 509 wol->wolopts = WAKE_MAGIC; 510 } 511 512 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 513 { 514 const u8 *mac_addr = dev->attached_dev->dev_addr; 515 int oldpage; 516 517 if (!device_can_wakeup(&dev->mdio.dev)) 518 return -EOPNOTSUPP; 519 520 oldpage = phy_save_page(dev); 521 if (oldpage < 0) 522 goto err; 523 524 if (wol->wolopts & WAKE_MAGIC) { 525 /* Store the device address for the magic packet */ 526 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 527 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 528 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 529 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 530 531 /* Enable magic packet matching */ 532 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 533 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 534 /* Set the maximum packet size, and assert WoL reset */ 535 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 536 } else { 537 /* Disable magic packet matching */ 538 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 539 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 540 541 /* Place WoL in reset */ 542 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 543 RTL8211F_WOL_RG_RSTB); 544 } 545 546 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 547 548 err: 549 return phy_restore_page(dev, oldpage, 0); 550 } 551 552 static int rtl8211_config_aneg(struct phy_device *phydev) 553 { 554 int ret; 555 556 ret = genphy_config_aneg(phydev); 557 if (ret < 0) 558 return ret; 559 560 /* Quirk was copied from vendor driver. Unfortunately it includes no 561 * description of the magic numbers. 562 */ 563 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 564 phy_write(phydev, 0x17, 0x2138); 565 phy_write(phydev, 0x0e, 0x0260); 566 } else { 567 phy_write(phydev, 0x17, 0x2108); 568 phy_write(phydev, 0x0e, 0x0000); 569 } 570 571 return 0; 572 } 573 574 static int rtl8211c_config_init(struct phy_device *phydev) 575 { 576 /* RTL8211C has an issue when operating in Gigabit slave mode */ 577 return phy_set_bits(phydev, MII_CTRL1000, 578 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 579 } 580 581 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 582 { 583 u16 val_txdly, val_rxdly; 584 int ret; 585 586 switch (phydev->interface) { 587 case PHY_INTERFACE_MODE_RGMII: 588 val_txdly = 0; 589 val_rxdly = 0; 590 break; 591 592 case PHY_INTERFACE_MODE_RGMII_RXID: 593 val_txdly = 0; 594 val_rxdly = RTL8211F_RX_DELAY; 595 break; 596 597 case PHY_INTERFACE_MODE_RGMII_TXID: 598 val_txdly = RTL8211F_TX_DELAY; 599 val_rxdly = 0; 600 break; 601 602 case PHY_INTERFACE_MODE_RGMII_ID: 603 val_txdly = RTL8211F_TX_DELAY; 604 val_rxdly = RTL8211F_RX_DELAY; 605 break; 606 607 default: /* the rest of the modes imply leaving delay as is. */ 608 return 0; 609 } 610 611 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 612 RTL8211F_TXCR, RTL8211F_TX_DELAY, 613 val_txdly); 614 if (ret < 0) { 615 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 616 ERR_PTR(ret)); 617 return ret; 618 } else if (ret) { 619 phydev_dbg(phydev, 620 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 621 str_enable_disable(val_txdly)); 622 } else { 623 phydev_dbg(phydev, 624 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 625 str_enabled_disabled(val_txdly)); 626 } 627 628 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 629 RTL8211F_RXCR, RTL8211F_RX_DELAY, 630 val_rxdly); 631 if (ret < 0) { 632 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 633 ERR_PTR(ret)); 634 return ret; 635 } else if (ret) { 636 phydev_dbg(phydev, 637 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 638 str_enable_disable(val_rxdly)); 639 } else { 640 phydev_dbg(phydev, 641 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 642 str_enabled_disabled(val_rxdly)); 643 } 644 645 return 0; 646 } 647 648 static int rtl8211f_config_clk_out(struct phy_device *phydev) 649 { 650 struct rtl821x_priv *priv = phydev->priv; 651 int ret; 652 653 /* The value is preserved if the device tree property is absent */ 654 if (!priv->disable_clk_out) 655 return 0; 656 657 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 658 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 659 RTL8211FVD_CLKOUT_REG, 660 RTL8211FVD_CLKOUT_EN, 0); 661 else 662 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 663 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 0); 664 if (ret) 665 return ret; 666 667 return genphy_soft_reset(phydev); 668 } 669 670 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 671 * which causes the RXC clock signal to stop for tens to hundreds of 672 * milliseconds. 673 * 674 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 675 * only enabled based on an opt-in device tree property. 676 */ 677 static int rtl8211f_config_aldps(struct phy_device *phydev) 678 { 679 struct rtl821x_priv *priv = phydev->priv; 680 u16 mask = RTL8211F_ALDPS_PLL_OFF | 681 RTL8211F_ALDPS_ENABLE | 682 RTL8211F_ALDPS_XTAL_OFF; 683 684 /* The value is preserved if the device tree property is absent */ 685 if (!priv->enable_aldps) 686 return 0; 687 688 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 689 mask, mask); 690 } 691 692 static int rtl8211f_config_init(struct phy_device *phydev) 693 { 694 struct device *dev = &phydev->mdio.dev; 695 int ret; 696 697 ret = rtl8211f_config_aldps(phydev); 698 if (ret) { 699 dev_err(dev, "aldps mode configuration failed: %pe\n", 700 ERR_PTR(ret)); 701 return ret; 702 } 703 704 ret = rtl8211f_config_rgmii_delay(phydev); 705 if (ret) 706 return ret; 707 708 ret = rtl8211f_config_clk_out(phydev); 709 if (ret) { 710 dev_err(dev, "clkout configuration failed: %pe\n", 711 ERR_PTR(ret)); 712 return ret; 713 } 714 715 /* RTL8211FVD has no PHYCR2 register */ 716 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 717 return 0; 718 719 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 720 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 721 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 722 if (ret) 723 return ret; 724 725 return 0; 726 } 727 728 static int rtl821x_suspend(struct phy_device *phydev) 729 { 730 struct rtl821x_priv *priv = phydev->priv; 731 int ret = 0; 732 733 if (!phydev->wol_enabled) { 734 ret = genphy_suspend(phydev); 735 736 if (ret) 737 return ret; 738 739 clk_disable_unprepare(priv->clk); 740 } 741 742 return ret; 743 } 744 745 static int rtl8211f_suspend(struct phy_device *phydev) 746 { 747 u16 wol_rst; 748 int ret; 749 750 ret = rtl821x_suspend(phydev); 751 if (ret < 0) 752 return ret; 753 754 /* If a PME event is enabled, then configure the interrupt for 755 * PME events only, disabling link interrupt. We avoid switching 756 * to PMEB mode as we don't have a status bit for that. 757 */ 758 if (device_may_wakeup(&phydev->mdio.dev)) { 759 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 760 RTL8211F_INER_PME); 761 if (ret < 0) 762 goto err; 763 764 /* Read the INSR to clear any pending interrupt */ 765 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 766 767 /* Reset the WoL to ensure that an event is picked up. 768 * Unless we do this, even if we receive another packet, 769 * we may not have a PME interrupt raised. 770 */ 771 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 772 RTL8211F_WOL_RST_RMSQ); 773 if (ret < 0) 774 goto err; 775 776 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 777 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 778 RTL8211F_WOL_RST_RMSQ, wol_rst); 779 if (ret < 0) 780 goto err; 781 782 wol_rst |= RTL8211F_WOL_RG_RSTB; 783 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 784 RTL8211F_WOL_RST_RMSQ, wol_rst); 785 } 786 787 err: 788 return ret; 789 } 790 791 static int rtl821x_resume(struct phy_device *phydev) 792 { 793 struct rtl821x_priv *priv = phydev->priv; 794 int ret; 795 796 if (!phydev->wol_enabled) 797 clk_prepare_enable(priv->clk); 798 799 ret = genphy_resume(phydev); 800 if (ret < 0) 801 return ret; 802 803 msleep(20); 804 805 return 0; 806 } 807 808 static int rtl8211f_resume(struct phy_device *phydev) 809 { 810 struct rtl821x_priv *priv = phydev->priv; 811 int ret; 812 813 ret = rtl821x_resume(phydev); 814 if (ret < 0) 815 return ret; 816 817 /* If the device was programmed for a PME event, restore the interrupt 818 * enable so phylib can receive link state interrupts. 819 */ 820 if (device_may_wakeup(&phydev->mdio.dev)) 821 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 822 823 return ret; 824 } 825 826 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 827 unsigned long rules) 828 { 829 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 830 BIT(TRIGGER_NETDEV_LINK_10) | 831 BIT(TRIGGER_NETDEV_LINK_100) | 832 BIT(TRIGGER_NETDEV_LINK_1000) | 833 BIT(TRIGGER_NETDEV_RX) | 834 BIT(TRIGGER_NETDEV_TX); 835 836 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 837 * - Link: Configurable subset of 10/100/1000 link rates 838 * - Active: Blink on activity, RX or TX is not differentiated 839 * The Active option has two modes, A and B: 840 * - A: Link and Active indication at configurable, but matching, 841 * subset of 10/100/1000 link rates 842 * - B: Link indication at configurable subset of 10/100/1000 link 843 * rates and Active indication always at all three 10+100+1000 844 * link rates. 845 * This code currently uses mode B only. 846 * 847 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 848 */ 849 850 if (index >= RTL8211x_LED_COUNT) 851 return -EINVAL; 852 853 /* Filter out any other unsupported triggers. */ 854 if (rules & ~mask) 855 return -EOPNOTSUPP; 856 857 /* RX and TX are not differentiated, either both are set or not set. */ 858 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 859 return -EOPNOTSUPP; 860 861 return 0; 862 } 863 864 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 865 unsigned long *rules) 866 { 867 int val; 868 869 if (index >= RTL8211x_LED_COUNT) 870 return -EINVAL; 871 872 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 873 if (val < 0) 874 return val; 875 876 val >>= RTL8211F_LEDCR_SHIFT * index; 877 val &= RTL8211F_LEDCR_MASK; 878 879 if (val & RTL8211F_LEDCR_LINK_10) 880 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 881 882 if (val & RTL8211F_LEDCR_LINK_100) 883 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 884 885 if (val & RTL8211F_LEDCR_LINK_1000) 886 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 887 888 if ((val & RTL8211F_LEDCR_LINK_10) && 889 (val & RTL8211F_LEDCR_LINK_100) && 890 (val & RTL8211F_LEDCR_LINK_1000)) { 891 __set_bit(TRIGGER_NETDEV_LINK, rules); 892 } 893 894 if (val & RTL8211F_LEDCR_ACT_TXRX) { 895 __set_bit(TRIGGER_NETDEV_RX, rules); 896 __set_bit(TRIGGER_NETDEV_TX, rules); 897 } 898 899 return 0; 900 } 901 902 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 903 unsigned long rules) 904 { 905 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 906 u16 reg = 0; 907 908 if (index >= RTL8211x_LED_COUNT) 909 return -EINVAL; 910 911 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 912 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 913 reg |= RTL8211F_LEDCR_LINK_10; 914 } 915 916 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 917 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 918 reg |= RTL8211F_LEDCR_LINK_100; 919 } 920 921 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 922 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 923 reg |= RTL8211F_LEDCR_LINK_1000; 924 } 925 926 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 927 test_bit(TRIGGER_NETDEV_TX, &rules)) { 928 reg |= RTL8211F_LEDCR_ACT_TXRX; 929 } 930 931 reg <<= RTL8211F_LEDCR_SHIFT * index; 932 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 933 934 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 935 } 936 937 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 938 unsigned long *rules) 939 { 940 int ret; 941 u16 cr1, cr2; 942 943 if (index >= RTL8211x_LED_COUNT) 944 return -EINVAL; 945 946 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 947 RTL8211E_LEDCR1); 948 if (ret < 0) 949 return ret; 950 951 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 952 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 953 __set_bit(TRIGGER_NETDEV_RX, rules); 954 __set_bit(TRIGGER_NETDEV_TX, rules); 955 } 956 957 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 958 RTL8211E_LEDCR2); 959 if (ret < 0) 960 return ret; 961 962 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 963 if (cr2 & RTL8211E_LEDCR2_LINK_10) 964 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 965 966 if (cr2 & RTL8211E_LEDCR2_LINK_100) 967 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 968 969 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 970 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 971 972 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 973 (cr2 & RTL8211E_LEDCR2_LINK_100) && 974 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 975 __set_bit(TRIGGER_NETDEV_LINK, rules); 976 } 977 978 return ret; 979 } 980 981 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 982 unsigned long rules) 983 { 984 const u16 cr1mask = 985 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 986 const u16 cr2mask = 987 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 988 u16 cr1 = 0, cr2 = 0; 989 int ret; 990 991 if (index >= RTL8211x_LED_COUNT) 992 return -EINVAL; 993 994 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 995 test_bit(TRIGGER_NETDEV_TX, &rules)) { 996 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 997 } 998 999 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1000 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1001 RTL8211E_LEDCR1, cr1mask, cr1); 1002 if (ret < 0) 1003 return ret; 1004 1005 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1006 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1007 cr2 |= RTL8211E_LEDCR2_LINK_10; 1008 } 1009 1010 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1011 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1012 cr2 |= RTL8211E_LEDCR2_LINK_100; 1013 } 1014 1015 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1016 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1017 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1018 } 1019 1020 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1021 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1022 RTL8211E_LEDCR2, cr2mask, cr2); 1023 1024 return ret; 1025 } 1026 1027 static int rtl8211e_config_init(struct phy_device *phydev) 1028 { 1029 u16 val; 1030 1031 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1032 switch (phydev->interface) { 1033 case PHY_INTERFACE_MODE_RGMII: 1034 val = RTL8211E_CTRL_DELAY | 0; 1035 break; 1036 case PHY_INTERFACE_MODE_RGMII_ID: 1037 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1038 break; 1039 case PHY_INTERFACE_MODE_RGMII_RXID: 1040 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1041 break; 1042 case PHY_INTERFACE_MODE_RGMII_TXID: 1043 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1044 break; 1045 default: /* the rest of the modes imply leaving delays as is. */ 1046 return 0; 1047 } 1048 1049 /* According to a sample driver there is a 0x1c config register on the 1050 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1051 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1052 * The configuration register definition: 1053 * 14 = reserved 1054 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1055 * 12 = RX Delay, 11 = TX Delay 1056 * 10:0 = Test && debug settings reserved by realtek 1057 */ 1058 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1059 RTL8211E_RGMII_DELAY, 1060 RTL8211E_DELAY_MASK, val); 1061 } 1062 1063 static int rtl8211b_suspend(struct phy_device *phydev) 1064 { 1065 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1066 1067 return genphy_suspend(phydev); 1068 } 1069 1070 static int rtl8211b_resume(struct phy_device *phydev) 1071 { 1072 phy_write(phydev, MII_MMD_DATA, 0); 1073 1074 return genphy_resume(phydev); 1075 } 1076 1077 static int rtl8366rb_config_init(struct phy_device *phydev) 1078 { 1079 int ret; 1080 1081 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1082 RTL8366RB_POWER_SAVE_ON); 1083 if (ret) { 1084 dev_err(&phydev->mdio.dev, 1085 "error enabling power management\n"); 1086 } 1087 1088 return ret; 1089 } 1090 1091 /* get actual speed to cover the downshift case */ 1092 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1093 { 1094 /* bit 3 1095 * 0: Half Duplex 1096 * 1: Full Duplex 1097 */ 1098 if (val & RTL_VND2_PHYSR_DUPLEX) 1099 phydev->duplex = DUPLEX_FULL; 1100 else 1101 phydev->duplex = DUPLEX_HALF; 1102 1103 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1104 case 0x0000: 1105 phydev->speed = SPEED_10; 1106 break; 1107 case 0x0010: 1108 phydev->speed = SPEED_100; 1109 break; 1110 case 0x0020: 1111 phydev->speed = SPEED_1000; 1112 break; 1113 case 0x0200: 1114 phydev->speed = SPEED_10000; 1115 break; 1116 case 0x0210: 1117 phydev->speed = SPEED_2500; 1118 break; 1119 case 0x0220: 1120 phydev->speed = SPEED_5000; 1121 break; 1122 default: 1123 break; 1124 } 1125 1126 /* bit 11 1127 * 0: Slave Mode 1128 * 1: Master Mode 1129 */ 1130 if (phydev->speed >= 1000) { 1131 if (val & RTL_VND2_PHYSR_MASTER) 1132 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1133 else 1134 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1135 } else { 1136 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1137 } 1138 } 1139 1140 static int rtlgen_read_status(struct phy_device *phydev) 1141 { 1142 int ret, val; 1143 1144 ret = genphy_read_status(phydev); 1145 if (ret < 0) 1146 return ret; 1147 1148 if (!phydev->link) 1149 return 0; 1150 1151 val = phy_read_paged(phydev, 0xa43, 0x12); 1152 if (val < 0) 1153 return val; 1154 1155 rtlgen_decode_physr(phydev, val); 1156 1157 return 0; 1158 } 1159 1160 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1161 { 1162 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1163 } 1164 1165 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1166 { 1167 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1168 val); 1169 } 1170 1171 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1172 { 1173 int ret; 1174 1175 if (devnum == MDIO_MMD_VEND2) 1176 ret = rtlgen_read_vend2(phydev, regnum); 1177 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1178 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1179 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1180 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1181 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1182 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1183 else 1184 ret = -EOPNOTSUPP; 1185 1186 return ret; 1187 } 1188 1189 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1190 u16 val) 1191 { 1192 int ret; 1193 1194 if (devnum == MDIO_MMD_VEND2) 1195 ret = rtlgen_write_vend2(phydev, regnum, val); 1196 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1197 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1198 else 1199 ret = -EOPNOTSUPP; 1200 1201 return ret; 1202 } 1203 1204 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1205 { 1206 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1207 1208 if (ret != -EOPNOTSUPP) 1209 return ret; 1210 1211 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1212 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1213 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1214 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1215 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1216 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1217 1218 return ret; 1219 } 1220 1221 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1222 u16 val) 1223 { 1224 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1225 1226 if (ret != -EOPNOTSUPP) 1227 return ret; 1228 1229 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1230 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1231 1232 return ret; 1233 } 1234 1235 static int rtl822x_probe(struct phy_device *phydev) 1236 { 1237 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1238 phydev->phy_id != RTL_GENERIC_PHYID) 1239 return rtl822x_hwmon_init(phydev); 1240 1241 return 0; 1242 } 1243 1244 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1245 { 1246 bool has_2500, has_sgmii; 1247 u16 mode; 1248 int ret; 1249 1250 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1251 phydev->host_interfaces) || 1252 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1253 1254 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1255 phydev->host_interfaces) || 1256 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1257 1258 /* fill in possible interfaces */ 1259 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1260 has_2500); 1261 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1262 has_sgmii); 1263 1264 if (!has_2500 && !has_sgmii) 1265 return 0; 1266 1267 /* determine SerDes option mode */ 1268 if (has_2500 && !has_sgmii) { 1269 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1270 phydev->rate_matching = RATE_MATCH_PAUSE; 1271 } else { 1272 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1273 phydev->rate_matching = RATE_MATCH_NONE; 1274 } 1275 1276 /* the following sequence with magic numbers sets up the SerDes 1277 * option mode 1278 */ 1279 1280 if (!gen1) { 1281 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1282 if (ret < 0) 1283 return ret; 1284 } 1285 1286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1287 RTL822X_VND1_SERDES_OPTION, 1288 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1289 mode); 1290 if (gen1 || ret < 0) 1291 return ret; 1292 1293 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1294 if (ret < 0) 1295 return ret; 1296 1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1298 if (ret < 0) 1299 return ret; 1300 1301 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1302 } 1303 1304 static int rtl822x_config_init(struct phy_device *phydev) 1305 { 1306 return rtl822x_set_serdes_option_mode(phydev, true); 1307 } 1308 1309 static int rtl822xb_config_init(struct phy_device *phydev) 1310 { 1311 return rtl822x_set_serdes_option_mode(phydev, false); 1312 } 1313 1314 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1315 phy_interface_t iface) 1316 { 1317 int val; 1318 1319 /* Only rate matching at 2500base-x */ 1320 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1321 return RATE_MATCH_NONE; 1322 1323 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1324 if (val < 0) 1325 return val; 1326 1327 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1328 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1329 return RATE_MATCH_PAUSE; 1330 1331 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1332 return RATE_MATCH_NONE; 1333 } 1334 1335 static int rtl822x_get_features(struct phy_device *phydev) 1336 { 1337 int val; 1338 1339 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1340 if (val < 0) 1341 return val; 1342 1343 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1344 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1345 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1346 phydev->supported, val & MDIO_PMA_SPEED_5G); 1347 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1348 phydev->supported, val & MDIO_SPEED_10G); 1349 1350 return genphy_read_abilities(phydev); 1351 } 1352 1353 static int rtl822x_config_aneg(struct phy_device *phydev) 1354 { 1355 int ret = 0; 1356 1357 if (phydev->autoneg == AUTONEG_ENABLE) { 1358 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1359 1360 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1361 RTL_MDIO_AN_10GBT_CTRL, 1362 MDIO_AN_10GBT_CTRL_ADV2_5G | 1363 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1364 if (ret < 0) 1365 return ret; 1366 } 1367 1368 return __genphy_config_aneg(phydev, ret); 1369 } 1370 1371 static void rtl822xb_update_interface(struct phy_device *phydev) 1372 { 1373 int val; 1374 1375 if (!phydev->link) 1376 return; 1377 1378 /* Change interface according to serdes mode */ 1379 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1380 if (val < 0) 1381 return; 1382 1383 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1384 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1385 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1386 break; 1387 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1388 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1389 break; 1390 } 1391 } 1392 1393 static int rtl822x_read_status(struct phy_device *phydev) 1394 { 1395 int lpadv, ret; 1396 1397 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1398 1399 ret = rtlgen_read_status(phydev); 1400 if (ret < 0) 1401 return ret; 1402 1403 if (phydev->autoneg == AUTONEG_DISABLE || 1404 !phydev->autoneg_complete) 1405 return 0; 1406 1407 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1408 if (lpadv < 0) 1409 return lpadv; 1410 1411 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1412 1413 return 0; 1414 } 1415 1416 static int rtl822xb_read_status(struct phy_device *phydev) 1417 { 1418 int ret; 1419 1420 ret = rtl822x_read_status(phydev); 1421 if (ret < 0) 1422 return ret; 1423 1424 rtl822xb_update_interface(phydev); 1425 1426 return 0; 1427 } 1428 1429 static int rtl822x_c45_get_features(struct phy_device *phydev) 1430 { 1431 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1432 phydev->supported); 1433 1434 return genphy_c45_pma_read_abilities(phydev); 1435 } 1436 1437 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1438 { 1439 bool changed = false; 1440 int ret, val; 1441 1442 if (phydev->autoneg == AUTONEG_DISABLE) 1443 return genphy_c45_pma_setup_forced(phydev); 1444 1445 ret = genphy_c45_an_config_aneg(phydev); 1446 if (ret < 0) 1447 return ret; 1448 if (ret > 0) 1449 changed = true; 1450 1451 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1452 1453 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1454 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1455 RTL822X_VND2_C22_REG(MII_CTRL1000), 1456 ADVERTISE_1000FULL, val); 1457 if (ret < 0) 1458 return ret; 1459 if (ret > 0) 1460 changed = true; 1461 1462 return genphy_c45_check_and_restart_aneg(phydev, changed); 1463 } 1464 1465 static int rtl822x_c45_read_status(struct phy_device *phydev) 1466 { 1467 int ret, val; 1468 1469 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1470 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1471 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1472 RTL822X_VND2_C22_REG(MII_STAT1000)); 1473 if (val < 0) 1474 return val; 1475 } else { 1476 val = 0; 1477 } 1478 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1479 1480 ret = genphy_c45_read_status(phydev); 1481 if (ret < 0) 1482 return ret; 1483 1484 if (!phydev->link) { 1485 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1486 return 0; 1487 } 1488 1489 /* Read actual speed from vendor register. */ 1490 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1491 if (val < 0) 1492 return val; 1493 1494 rtlgen_decode_physr(phydev, val); 1495 1496 return 0; 1497 } 1498 1499 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1500 { 1501 int ret, val; 1502 1503 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1504 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1505 if (ret < 0) 1506 return ret; 1507 1508 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1509 MDIO_CTRL1, val, 1510 !(val & MDIO_CTRL1_RESET), 1511 5000, 100000, true); 1512 } 1513 1514 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1515 { 1516 int ret; 1517 1518 ret = rtl822x_c45_read_status(phydev); 1519 if (ret < 0) 1520 return ret; 1521 1522 rtl822xb_update_interface(phydev); 1523 1524 return 0; 1525 } 1526 1527 static int rtl8224_cable_test_start(struct phy_device *phydev) 1528 { 1529 u32 val; 1530 int ret; 1531 1532 /* disable auto-negotiation and force 1000/Full */ 1533 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1534 RTL822X_VND2_C22_REG(MII_BMCR), 1535 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1536 BMCR_SPEED1000 | BMCR_FULLDPLX); 1537 if (ret) 1538 return ret; 1539 1540 mdelay(500); 1541 1542 /* trigger cable test */ 1543 val = RTL8224_MII_RTCT_ENABLE; 1544 val |= RTL8224_MII_RTCT_PAIR_A; 1545 val |= RTL8224_MII_RTCT_PAIR_B; 1546 val |= RTL8224_MII_RTCT_PAIR_C; 1547 val |= RTL8224_MII_RTCT_PAIR_D; 1548 1549 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1550 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1551 RTL8224_MII_RTCT_DONE, val); 1552 } 1553 1554 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1555 { 1556 int ret; 1557 1558 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1559 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1560 reg); 1561 if (ret) 1562 return ret; 1563 1564 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1565 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1566 } 1567 1568 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1569 { 1570 int cable_len; 1571 u32 reg_len; 1572 int ret; 1573 u32 cm; 1574 1575 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1576 1577 ret = rtl8224_sram_read(phydev, reg_len); 1578 if (ret < 0) 1579 return ret; 1580 1581 cable_len = ret & 0xff00; 1582 1583 ret = rtl8224_sram_read(phydev, reg_len + 1); 1584 if (ret < 0) 1585 return ret; 1586 1587 cable_len |= (ret & 0xff00) >> 8; 1588 1589 cable_len -= 620; 1590 cable_len = max(cable_len, 0); 1591 1592 cm = cable_len * 100 / 78; 1593 1594 return cm; 1595 } 1596 1597 static int rtl8224_cable_test_result_trans(u32 result) 1598 { 1599 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1600 return -EBUSY; 1601 1602 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1603 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1604 1605 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1606 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1607 1608 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1609 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1610 1611 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1612 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1613 1614 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1615 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1616 1617 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1618 } 1619 1620 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1621 { 1622 int fault_rslt; 1623 int ret; 1624 1625 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1626 if (ret < 0) 1627 return ret; 1628 1629 fault_rslt = rtl8224_cable_test_result_trans(ret); 1630 if (fault_rslt < 0) 1631 return 0; 1632 1633 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1634 if (ret < 0) 1635 return ret; 1636 1637 switch (fault_rslt) { 1638 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1639 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1640 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1641 ret = rtl8224_pair_len_get(phydev, pair); 1642 if (ret < 0) 1643 return ret; 1644 1645 return ethnl_cable_test_fault_length(phydev, pair, ret); 1646 default: 1647 return 0; 1648 } 1649 } 1650 1651 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1652 { 1653 unsigned int pair; 1654 int ret; 1655 1656 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1657 ret = rtl8224_cable_test_report_pair(phydev, pair); 1658 if (ret == -EBUSY) { 1659 *finished = false; 1660 return 0; 1661 } 1662 1663 if (ret < 0) 1664 return ret; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1671 { 1672 int ret; 1673 1674 *finished = false; 1675 1676 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1677 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1678 if (ret < 0) 1679 return ret; 1680 1681 if (!(ret & RTL8224_MII_RTCT_DONE)) 1682 return 0; 1683 1684 *finished = true; 1685 1686 return rtl8224_cable_test_report(phydev, finished); 1687 } 1688 1689 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1690 { 1691 int val; 1692 1693 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1694 val = phy_read(phydev, 0x13); 1695 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1696 1697 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1698 } 1699 1700 /* On internal PHY's MMD reads over C22 always return 0. 1701 * Check a MMD register which is known to be non-zero. 1702 */ 1703 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1704 { 1705 int val; 1706 1707 phy_lock_mdio_bus(phydev); 1708 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1709 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1710 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1711 val = __phy_read(phydev, MII_MMD_DATA); 1712 phy_unlock_mdio_bus(phydev); 1713 1714 return val > 0; 1715 } 1716 1717 static int rtlgen_match_phy_device(struct phy_device *phydev, 1718 const struct phy_driver *phydrv) 1719 { 1720 return phydev->phy_id == RTL_GENERIC_PHYID && 1721 !rtlgen_supports_2_5gbps(phydev); 1722 } 1723 1724 static int rtl8226_match_phy_device(struct phy_device *phydev, 1725 const struct phy_driver *phydrv) 1726 { 1727 return phydev->phy_id == RTL_GENERIC_PHYID && 1728 rtlgen_supports_2_5gbps(phydev) && 1729 rtlgen_supports_mmd(phydev); 1730 } 1731 1732 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1733 bool is_c45) 1734 { 1735 if (phydev->is_c45) 1736 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1737 else 1738 return !is_c45 && (id == phydev->phy_id); 1739 } 1740 1741 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1742 const struct phy_driver *phydrv) 1743 { 1744 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1745 } 1746 1747 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1748 const struct phy_driver *phydrv) 1749 { 1750 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1751 } 1752 1753 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1754 const struct phy_driver *phydrv) 1755 { 1756 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1757 } 1758 1759 static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev, 1760 const struct phy_driver *phydrv) 1761 { 1762 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1763 } 1764 1765 static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev, 1766 const struct phy_driver *phydrv) 1767 { 1768 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true); 1769 } 1770 1771 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1772 const struct phy_driver *phydrv) 1773 { 1774 if (phydev->is_c45) 1775 return false; 1776 1777 switch (phydev->phy_id) { 1778 case RTL_GENERIC_PHYID: 1779 case RTL_8221B: 1780 case RTL_8251B: 1781 case RTL_8261C: 1782 case 0x001cc841: 1783 break; 1784 default: 1785 return false; 1786 } 1787 1788 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1789 } 1790 1791 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1792 const struct phy_driver *phydrv) 1793 { 1794 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1795 } 1796 1797 static int rtlgen_resume(struct phy_device *phydev) 1798 { 1799 int ret = genphy_resume(phydev); 1800 1801 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1802 msleep(20); 1803 1804 return ret; 1805 } 1806 1807 static int rtlgen_c45_resume(struct phy_device *phydev) 1808 { 1809 int ret = genphy_c45_pma_resume(phydev); 1810 1811 msleep(20); 1812 1813 return ret; 1814 } 1815 1816 static int rtl9000a_config_init(struct phy_device *phydev) 1817 { 1818 phydev->autoneg = AUTONEG_DISABLE; 1819 phydev->speed = SPEED_100; 1820 phydev->duplex = DUPLEX_FULL; 1821 1822 return 0; 1823 } 1824 1825 static int rtl9000a_config_aneg(struct phy_device *phydev) 1826 { 1827 int ret; 1828 u16 ctl = 0; 1829 1830 switch (phydev->master_slave_set) { 1831 case MASTER_SLAVE_CFG_MASTER_FORCE: 1832 ctl |= CTL1000_AS_MASTER; 1833 break; 1834 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1835 break; 1836 case MASTER_SLAVE_CFG_UNKNOWN: 1837 case MASTER_SLAVE_CFG_UNSUPPORTED: 1838 return 0; 1839 default: 1840 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1841 return -EOPNOTSUPP; 1842 } 1843 1844 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1845 if (ret == 1) 1846 ret = genphy_soft_reset(phydev); 1847 1848 return ret; 1849 } 1850 1851 static int rtl9000a_read_status(struct phy_device *phydev) 1852 { 1853 int ret; 1854 1855 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1856 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1857 1858 ret = genphy_update_link(phydev); 1859 if (ret) 1860 return ret; 1861 1862 ret = phy_read(phydev, MII_CTRL1000); 1863 if (ret < 0) 1864 return ret; 1865 if (ret & CTL1000_AS_MASTER) 1866 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1867 else 1868 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1869 1870 ret = phy_read(phydev, MII_STAT1000); 1871 if (ret < 0) 1872 return ret; 1873 if (ret & LPA_1000MSRES) 1874 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1875 else 1876 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1877 1878 return 0; 1879 } 1880 1881 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1882 { 1883 int err; 1884 1885 err = phy_read(phydev, RTL8211F_INSR); 1886 1887 return (err < 0) ? err : 0; 1888 } 1889 1890 static int rtl9000a_config_intr(struct phy_device *phydev) 1891 { 1892 u16 val; 1893 int err; 1894 1895 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1896 err = rtl9000a_ack_interrupt(phydev); 1897 if (err) 1898 return err; 1899 1900 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1901 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1902 } else { 1903 val = ~0; 1904 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1905 if (err) 1906 return err; 1907 1908 err = rtl9000a_ack_interrupt(phydev); 1909 } 1910 1911 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1912 } 1913 1914 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1915 { 1916 int irq_status; 1917 1918 irq_status = phy_read(phydev, RTL8211F_INSR); 1919 if (irq_status < 0) { 1920 phy_error(phydev); 1921 return IRQ_NONE; 1922 } 1923 1924 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1925 return IRQ_NONE; 1926 1927 phy_trigger_machine(phydev); 1928 1929 return IRQ_HANDLED; 1930 } 1931 1932 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 1933 { 1934 int err; 1935 1936 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 1937 1938 return (err < 0) ? err : 0; 1939 } 1940 1941 static int rtl8221b_config_intr(struct phy_device *phydev) 1942 { 1943 int err; 1944 1945 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1946 err = rtl8221b_ack_interrupt(phydev); 1947 if (err) 1948 return err; 1949 1950 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 1951 RTL8221B_VND2_INER_LINK_STATUS); 1952 } else { 1953 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1954 RTL8221B_VND2_INER, 0); 1955 if (err) 1956 return err; 1957 1958 err = rtl8221b_ack_interrupt(phydev); 1959 } 1960 1961 return err; 1962 } 1963 1964 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 1965 { 1966 int err; 1967 1968 err = rtl8221b_ack_interrupt(phydev); 1969 if (err) { 1970 phy_error(phydev); 1971 return IRQ_NONE; 1972 } 1973 1974 phy_trigger_machine(phydev); 1975 1976 return IRQ_HANDLED; 1977 } 1978 1979 static struct phy_driver realtek_drvs[] = { 1980 { 1981 PHY_ID_MATCH_EXACT(0x00008201), 1982 .name = "RTL8201CP Ethernet", 1983 .read_page = rtl821x_read_page, 1984 .write_page = rtl821x_write_page, 1985 }, { 1986 PHY_ID_MATCH_EXACT(0x001cc816), 1987 .name = "RTL8201F Fast Ethernet", 1988 .config_intr = &rtl8201_config_intr, 1989 .handle_interrupt = rtl8201_handle_interrupt, 1990 .suspend = genphy_suspend, 1991 .resume = genphy_resume, 1992 .read_page = rtl821x_read_page, 1993 .write_page = rtl821x_write_page, 1994 }, { 1995 PHY_ID_MATCH_MODEL(0x001cc880), 1996 .name = "RTL8208 Fast Ethernet", 1997 .read_mmd = genphy_read_mmd_unsupported, 1998 .write_mmd = genphy_write_mmd_unsupported, 1999 .suspend = genphy_suspend, 2000 .resume = genphy_resume, 2001 .read_page = rtl821x_read_page, 2002 .write_page = rtl821x_write_page, 2003 }, { 2004 PHY_ID_MATCH_EXACT(0x001cc910), 2005 .name = "RTL8211 Gigabit Ethernet", 2006 .config_aneg = rtl8211_config_aneg, 2007 .read_mmd = &genphy_read_mmd_unsupported, 2008 .write_mmd = &genphy_write_mmd_unsupported, 2009 .read_page = rtl821x_read_page, 2010 .write_page = rtl821x_write_page, 2011 }, { 2012 PHY_ID_MATCH_EXACT(0x001cc912), 2013 .name = "RTL8211B Gigabit Ethernet", 2014 .config_intr = &rtl8211b_config_intr, 2015 .handle_interrupt = rtl821x_handle_interrupt, 2016 .read_mmd = &genphy_read_mmd_unsupported, 2017 .write_mmd = &genphy_write_mmd_unsupported, 2018 .suspend = rtl8211b_suspend, 2019 .resume = rtl8211b_resume, 2020 .read_page = rtl821x_read_page, 2021 .write_page = rtl821x_write_page, 2022 }, { 2023 PHY_ID_MATCH_EXACT(0x001cc913), 2024 .name = "RTL8211C Gigabit Ethernet", 2025 .config_init = rtl8211c_config_init, 2026 .read_mmd = &genphy_read_mmd_unsupported, 2027 .write_mmd = &genphy_write_mmd_unsupported, 2028 .read_page = rtl821x_read_page, 2029 .write_page = rtl821x_write_page, 2030 }, { 2031 PHY_ID_MATCH_EXACT(0x001cc914), 2032 .name = "RTL8211DN Gigabit Ethernet", 2033 .config_intr = rtl8211e_config_intr, 2034 .handle_interrupt = rtl821x_handle_interrupt, 2035 .suspend = genphy_suspend, 2036 .resume = genphy_resume, 2037 .read_page = rtl821x_read_page, 2038 .write_page = rtl821x_write_page, 2039 }, { 2040 PHY_ID_MATCH_EXACT(0x001cc915), 2041 .name = "RTL8211E Gigabit Ethernet", 2042 .config_init = &rtl8211e_config_init, 2043 .config_intr = &rtl8211e_config_intr, 2044 .handle_interrupt = rtl821x_handle_interrupt, 2045 .suspend = genphy_suspend, 2046 .resume = genphy_resume, 2047 .read_page = rtl821x_read_page, 2048 .write_page = rtl821x_write_page, 2049 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2050 .led_hw_control_get = rtl8211e_led_hw_control_get, 2051 .led_hw_control_set = rtl8211e_led_hw_control_set, 2052 }, { 2053 PHY_ID_MATCH_EXACT(0x001cc916), 2054 .name = "RTL8211F Gigabit Ethernet", 2055 .probe = rtl8211f_probe, 2056 .config_init = &rtl8211f_config_init, 2057 .read_status = rtlgen_read_status, 2058 .config_intr = &rtl8211f_config_intr, 2059 .handle_interrupt = rtl8211f_handle_interrupt, 2060 .set_wol = rtl8211f_set_wol, 2061 .get_wol = rtl8211f_get_wol, 2062 .suspend = rtl8211f_suspend, 2063 .resume = rtl8211f_resume, 2064 .read_page = rtl821x_read_page, 2065 .write_page = rtl821x_write_page, 2066 .flags = PHY_ALWAYS_CALL_SUSPEND, 2067 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2068 .led_hw_control_get = rtl8211f_led_hw_control_get, 2069 .led_hw_control_set = rtl8211f_led_hw_control_set, 2070 }, { 2071 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2072 .name = "RTL8211F-VD Gigabit Ethernet", 2073 .probe = rtl821x_probe, 2074 .config_init = &rtl8211f_config_init, 2075 .read_status = rtlgen_read_status, 2076 .config_intr = &rtl8211f_config_intr, 2077 .handle_interrupt = rtl8211f_handle_interrupt, 2078 .suspend = rtl821x_suspend, 2079 .resume = rtl821x_resume, 2080 .read_page = rtl821x_read_page, 2081 .write_page = rtl821x_write_page, 2082 .flags = PHY_ALWAYS_CALL_SUSPEND, 2083 }, { 2084 .name = "Generic FE-GE Realtek PHY", 2085 .match_phy_device = rtlgen_match_phy_device, 2086 .read_status = rtlgen_read_status, 2087 .suspend = genphy_suspend, 2088 .resume = rtlgen_resume, 2089 .read_page = rtl821x_read_page, 2090 .write_page = rtl821x_write_page, 2091 .read_mmd = rtlgen_read_mmd, 2092 .write_mmd = rtlgen_write_mmd, 2093 }, { 2094 .name = "RTL8226 2.5Gbps PHY", 2095 .match_phy_device = rtl8226_match_phy_device, 2096 .get_features = rtl822x_get_features, 2097 .config_aneg = rtl822x_config_aneg, 2098 .read_status = rtl822x_read_status, 2099 .suspend = genphy_suspend, 2100 .resume = rtlgen_resume, 2101 .read_page = rtl821x_read_page, 2102 .write_page = rtl821x_write_page, 2103 }, { 2104 .match_phy_device = rtl8221b_match_phy_device, 2105 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2106 .get_features = rtl822x_get_features, 2107 .config_aneg = rtl822x_config_aneg, 2108 .config_init = rtl822xb_config_init, 2109 .get_rate_matching = rtl822xb_get_rate_matching, 2110 .read_status = rtl822xb_read_status, 2111 .suspend = genphy_suspend, 2112 .resume = rtlgen_resume, 2113 .read_page = rtl821x_read_page, 2114 .write_page = rtl821x_write_page, 2115 }, { 2116 PHY_ID_MATCH_EXACT(0x001cc838), 2117 .name = "RTL8226-CG 2.5Gbps PHY", 2118 .soft_reset = rtl822x_c45_soft_reset, 2119 .get_features = rtl822x_c45_get_features, 2120 .config_aneg = rtl822x_c45_config_aneg, 2121 .config_init = rtl822x_config_init, 2122 .read_status = rtl822xb_c45_read_status, 2123 .suspend = genphy_c45_pma_suspend, 2124 .resume = rtlgen_c45_resume, 2125 }, { 2126 PHY_ID_MATCH_EXACT(0x001cc848), 2127 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2128 .get_features = rtl822x_get_features, 2129 .config_aneg = rtl822x_config_aneg, 2130 .config_init = rtl822xb_config_init, 2131 .get_rate_matching = rtl822xb_get_rate_matching, 2132 .read_status = rtl822xb_read_status, 2133 .suspend = genphy_suspend, 2134 .resume = rtlgen_resume, 2135 .read_page = rtl821x_read_page, 2136 .write_page = rtl821x_write_page, 2137 }, { 2138 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 2139 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 2140 .probe = rtl822x_probe, 2141 .get_features = rtl822x_get_features, 2142 .config_aneg = rtl822x_config_aneg, 2143 .config_init = rtl822xb_config_init, 2144 .get_rate_matching = rtl822xb_get_rate_matching, 2145 .read_status = rtl822xb_read_status, 2146 .suspend = genphy_suspend, 2147 .resume = rtlgen_resume, 2148 .read_page = rtl821x_read_page, 2149 .write_page = rtl821x_write_page, 2150 }, { 2151 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 2152 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 2153 .config_intr = rtl8221b_config_intr, 2154 .handle_interrupt = rtl8221b_handle_interrupt, 2155 .probe = rtl822x_probe, 2156 .config_init = rtl822xb_config_init, 2157 .get_rate_matching = rtl822xb_get_rate_matching, 2158 .get_features = rtl822x_c45_get_features, 2159 .config_aneg = rtl822x_c45_config_aneg, 2160 .read_status = rtl822xb_c45_read_status, 2161 .suspend = genphy_c45_pma_suspend, 2162 .resume = rtlgen_c45_resume, 2163 }, { 2164 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device, 2165 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 2166 .probe = rtl822x_probe, 2167 .get_features = rtl822x_get_features, 2168 .config_aneg = rtl822x_config_aneg, 2169 .config_init = rtl822xb_config_init, 2170 .get_rate_matching = rtl822xb_get_rate_matching, 2171 .read_status = rtl822xb_read_status, 2172 .suspend = genphy_suspend, 2173 .resume = rtlgen_resume, 2174 .read_page = rtl821x_read_page, 2175 .write_page = rtl821x_write_page, 2176 }, { 2177 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device, 2178 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)", 2179 .config_intr = rtl8221b_config_intr, 2180 .handle_interrupt = rtl8221b_handle_interrupt, 2181 .probe = rtl822x_probe, 2182 .config_init = rtl822xb_config_init, 2183 .get_rate_matching = rtl822xb_get_rate_matching, 2184 .get_features = rtl822x_c45_get_features, 2185 .config_aneg = rtl822x_c45_config_aneg, 2186 .read_status = rtl822xb_c45_read_status, 2187 .suspend = genphy_c45_pma_suspend, 2188 .resume = rtlgen_c45_resume, 2189 }, { 2190 .match_phy_device = rtl8251b_c45_match_phy_device, 2191 .name = "RTL8251B 5Gbps PHY", 2192 .probe = rtl822x_probe, 2193 .get_features = rtl822x_get_features, 2194 .config_aneg = rtl822x_config_aneg, 2195 .read_status = rtl822x_read_status, 2196 .suspend = genphy_suspend, 2197 .resume = rtlgen_resume, 2198 .read_page = rtl821x_read_page, 2199 .write_page = rtl821x_write_page, 2200 }, { 2201 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2202 .name = "Realtek Internal NBASE-T PHY", 2203 .flags = PHY_IS_INTERNAL, 2204 .probe = rtl822x_probe, 2205 .get_features = rtl822x_get_features, 2206 .config_aneg = rtl822x_config_aneg, 2207 .read_status = rtl822x_read_status, 2208 .suspend = genphy_suspend, 2209 .resume = rtlgen_resume, 2210 .read_page = rtl821x_read_page, 2211 .write_page = rtl821x_write_page, 2212 .read_mmd = rtl822x_read_mmd, 2213 .write_mmd = rtl822x_write_mmd, 2214 }, { 2215 PHY_ID_MATCH_EXACT(0x001ccad0), 2216 .name = "RTL8224 2.5Gbps PHY", 2217 .flags = PHY_POLL_CABLE_TEST, 2218 .get_features = rtl822x_c45_get_features, 2219 .config_aneg = rtl822x_c45_config_aneg, 2220 .read_status = rtl822x_c45_read_status, 2221 .suspend = genphy_c45_pma_suspend, 2222 .resume = rtlgen_c45_resume, 2223 .cable_test_start = rtl8224_cable_test_start, 2224 .cable_test_get_status = rtl8224_cable_test_get_status, 2225 }, { 2226 PHY_ID_MATCH_EXACT(0x001cc961), 2227 .name = "RTL8366RB Gigabit Ethernet", 2228 .config_init = &rtl8366rb_config_init, 2229 /* These interrupts are handled by the irq controller 2230 * embedded inside the RTL8366RB, they get unmasked when the 2231 * irq is requested and ACKed by reading the status register, 2232 * which is done by the irqchip code. 2233 */ 2234 .config_intr = genphy_no_config_intr, 2235 .handle_interrupt = genphy_handle_interrupt_no_ack, 2236 .suspend = genphy_suspend, 2237 .resume = genphy_resume, 2238 }, { 2239 PHY_ID_MATCH_EXACT(0x001ccb00), 2240 .name = "RTL9000AA_RTL9000AN Ethernet", 2241 .features = PHY_BASIC_T1_FEATURES, 2242 .config_init = rtl9000a_config_init, 2243 .config_aneg = rtl9000a_config_aneg, 2244 .read_status = rtl9000a_read_status, 2245 .config_intr = rtl9000a_config_intr, 2246 .handle_interrupt = rtl9000a_handle_interrupt, 2247 .suspend = genphy_suspend, 2248 .resume = genphy_resume, 2249 .read_page = rtl821x_read_page, 2250 .write_page = rtl821x_write_page, 2251 }, { 2252 PHY_ID_MATCH_EXACT(0x001cc942), 2253 .name = "RTL8365MB-VC Gigabit Ethernet", 2254 /* Interrupt handling analogous to RTL8366RB */ 2255 .config_intr = genphy_no_config_intr, 2256 .handle_interrupt = genphy_handle_interrupt_no_ack, 2257 .suspend = genphy_suspend, 2258 .resume = genphy_resume, 2259 }, { 2260 PHY_ID_MATCH_EXACT(0x001cc960), 2261 .name = "RTL8366S Gigabit Ethernet", 2262 .suspend = genphy_suspend, 2263 .resume = genphy_resume, 2264 .read_mmd = genphy_read_mmd_unsupported, 2265 .write_mmd = genphy_write_mmd_unsupported, 2266 }, 2267 }; 2268 2269 module_phy_driver(realtek_drvs); 2270 2271 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2272 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2273 { } 2274 }; 2275 2276 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2277