1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/pm_wakeirq.h> 14 #include <linux/netdevice.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/clk.h> 18 #include <linux/string_choices.h> 19 20 #include "realtek.h" 21 22 #define RTL8201F_IER 0x13 23 24 #define RTL8201F_ISR 0x1e 25 #define RTL8201F_ISR_ANERR BIT(15) 26 #define RTL8201F_ISR_DUPLEX BIT(13) 27 #define RTL8201F_ISR_LINK BIT(11) 28 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 29 RTL8201F_ISR_DUPLEX | \ 30 RTL8201F_ISR_LINK) 31 32 #define RTL821x_INER 0x12 33 #define RTL8211B_INER_INIT 0x6400 34 #define RTL8211E_INER_LINK_STATUS BIT(10) 35 #define RTL8211F_INER_PME BIT(7) 36 #define RTL8211F_INER_LINK_STATUS BIT(4) 37 38 #define RTL821x_INSR 0x13 39 40 #define RTL821x_EXT_PAGE_SELECT 0x1e 41 42 #define RTL821x_PAGE_SELECT 0x1f 43 #define RTL821x_SET_EXT_PAGE 0x07 44 45 /* RTL8211E extension page 44/0x2c */ 46 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 47 #define RTL8211E_LEDCR1 0x1a 48 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 49 #define RTL8211E_LEDCR1_MASK BIT(4) 50 #define RTL8211E_LEDCR1_SHIFT 1 51 52 #define RTL8211E_LEDCR2 0x1c 53 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 54 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 55 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 56 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 57 #define RTL8211E_LEDCR2_SHIFT 4 58 59 /* RTL8211E extension page 164/0xa4 */ 60 #define RTL8211E_RGMII_EXT_PAGE 0xa4 61 #define RTL8211E_RGMII_DELAY 0x1c 62 #define RTL8211E_CTRL_DELAY BIT(13) 63 #define RTL8211E_TX_DELAY BIT(12) 64 #define RTL8211E_RX_DELAY BIT(11) 65 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 66 67 /* RTL8211F PHY configuration */ 68 #define RTL8211F_PHYCR_PAGE 0xa43 69 #define RTL8211F_PHYCR1 0x18 70 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 71 #define RTL8211F_ALDPS_ENABLE BIT(2) 72 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 73 74 #define RTL8211F_PHYCR2 0x19 75 #define RTL8211F_CLKOUT_EN BIT(0) 76 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 77 78 #define RTL8211F_INSR_PAGE 0xa43 79 #define RTL8211F_INSR 0x1d 80 81 /* RTL8211F LED configuration */ 82 #define RTL8211F_LEDCR_PAGE 0xd04 83 #define RTL8211F_LEDCR 0x10 84 #define RTL8211F_LEDCR_MODE BIT(15) 85 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 86 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 87 #define RTL8211F_LEDCR_LINK_100 BIT(1) 88 #define RTL8211F_LEDCR_LINK_10 BIT(0) 89 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 90 #define RTL8211F_LEDCR_SHIFT 5 91 92 /* RTL8211F RGMII configuration */ 93 #define RTL8211F_RGMII_PAGE 0xd08 94 95 #define RTL8211F_TXCR 0x11 96 #define RTL8211F_TX_DELAY BIT(8) 97 98 #define RTL8211F_RXCR 0x15 99 #define RTL8211F_RX_DELAY BIT(3) 100 101 /* RTL8211F WOL settings */ 102 #define RTL8211F_WOL_PAGE 0xd8a 103 #define RTL8211F_WOL_SETTINGS_EVENTS 16 104 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 105 #define RTL8211F_WOL_RST_RMSQ 17 106 #define RTL8211F_WOL_RG_RSTB BIT(15) 107 #define RTL8211F_WOL_RMSQ 0x1fff 108 109 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 110 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 111 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 112 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 113 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 114 115 #define RTL822X_VND1_SERDES_OPTION 0x697a 116 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 117 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 118 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 119 120 #define RTL822X_VND1_SERDES_CTRL3 0x7580 121 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 122 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 124 125 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 126 * is set, they cannot be accessed by C45-over-C22. 127 */ 128 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 129 130 #define RTL8366RB_POWER_SAVE 0x15 131 #define RTL8366RB_POWER_SAVE_ON BIT(12) 132 133 #define RTL9000A_GINMR 0x14 134 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 135 136 #define RTL_VND2_PHYSR 0xa434 137 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 138 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 139 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 140 #define RTL_VND2_PHYSR_MASTER BIT(11) 141 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 142 143 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 144 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 145 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 146 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 147 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 148 #define RTL_MDIO_PMA_SPEED 0xa616 149 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 150 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 151 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 152 153 #define RTL_GENERIC_PHYID 0x001cc800 154 #define RTL_8211FVD_PHYID 0x001cc878 155 #define RTL_8221B 0x001cc840 156 #define RTL_8221B_VB_CG 0x001cc849 157 #define RTL_8221B_VN_CG 0x001cc84a 158 #define RTL_8251B 0x001cc862 159 #define RTL_8261C 0x001cc890 160 161 /* RTL8211E and RTL8211F support up to three LEDs */ 162 #define RTL8211x_LED_COUNT 3 163 164 MODULE_DESCRIPTION("Realtek PHY driver"); 165 MODULE_AUTHOR("Johnson Leung"); 166 MODULE_LICENSE("GPL"); 167 168 struct rtl821x_priv { 169 u16 phycr1; 170 u16 phycr2; 171 bool has_phycr2; 172 struct clk *clk; 173 /* rtl8211f */ 174 u16 iner; 175 }; 176 177 static int rtl821x_read_page(struct phy_device *phydev) 178 { 179 return __phy_read(phydev, RTL821x_PAGE_SELECT); 180 } 181 182 static int rtl821x_write_page(struct phy_device *phydev, int page) 183 { 184 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 185 } 186 187 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 188 u32 regnum) 189 { 190 int oldpage, ret = 0; 191 192 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 193 if (oldpage >= 0) { 194 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 195 if (ret == 0) 196 ret = __phy_read(phydev, regnum); 197 } 198 199 return phy_restore_page(phydev, oldpage, ret); 200 } 201 202 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 203 u32 regnum, u16 mask, u16 set) 204 { 205 int oldpage, ret = 0; 206 207 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 208 if (oldpage >= 0) { 209 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 210 if (ret == 0) 211 ret = __phy_modify(phydev, regnum, mask, set); 212 } 213 214 return phy_restore_page(phydev, oldpage, ret); 215 } 216 217 static int rtl821x_probe(struct phy_device *phydev) 218 { 219 struct device *dev = &phydev->mdio.dev; 220 struct rtl821x_priv *priv; 221 u32 phy_id = phydev->drv->phy_id; 222 int ret; 223 224 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 225 if (!priv) 226 return -ENOMEM; 227 228 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 229 if (IS_ERR(priv->clk)) 230 return dev_err_probe(dev, PTR_ERR(priv->clk), 231 "failed to get phy clock\n"); 232 233 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 234 if (ret < 0) 235 return ret; 236 237 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 238 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 239 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 240 241 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 242 if (priv->has_phycr2) { 243 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 244 if (ret < 0) 245 return ret; 246 247 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 248 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 249 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 250 } 251 252 phydev->priv = priv; 253 254 return 0; 255 } 256 257 static int rtl8211f_probe(struct phy_device *phydev) 258 { 259 struct device *dev = &phydev->mdio.dev; 260 int ret; 261 262 ret = rtl821x_probe(phydev); 263 if (ret < 0) 264 return ret; 265 266 /* Disable all PME events */ 267 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 268 RTL8211F_WOL_SETTINGS_EVENTS, 0); 269 if (ret < 0) 270 return ret; 271 272 /* Mark this PHY as wakeup capable and register the interrupt as a 273 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 274 * and the interrupt is valid. 275 */ 276 if (device_property_read_bool(dev, "wakeup-source") && 277 phy_interrupt_is_valid(phydev)) { 278 device_set_wakeup_capable(dev, true); 279 devm_pm_set_wake_irq(dev, phydev->irq); 280 } 281 282 return ret; 283 } 284 285 static int rtl8201_ack_interrupt(struct phy_device *phydev) 286 { 287 int err; 288 289 err = phy_read(phydev, RTL8201F_ISR); 290 291 return (err < 0) ? err : 0; 292 } 293 294 static int rtl821x_ack_interrupt(struct phy_device *phydev) 295 { 296 int err; 297 298 err = phy_read(phydev, RTL821x_INSR); 299 300 return (err < 0) ? err : 0; 301 } 302 303 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 304 { 305 int err; 306 307 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 308 309 return (err < 0) ? err : 0; 310 } 311 312 static int rtl8201_config_intr(struct phy_device *phydev) 313 { 314 u16 val; 315 int err; 316 317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 318 err = rtl8201_ack_interrupt(phydev); 319 if (err) 320 return err; 321 322 val = BIT(13) | BIT(12) | BIT(11); 323 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 324 } else { 325 val = 0; 326 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 327 if (err) 328 return err; 329 330 err = rtl8201_ack_interrupt(phydev); 331 } 332 333 return err; 334 } 335 336 static int rtl8211b_config_intr(struct phy_device *phydev) 337 { 338 int err; 339 340 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 341 err = rtl821x_ack_interrupt(phydev); 342 if (err) 343 return err; 344 345 err = phy_write(phydev, RTL821x_INER, 346 RTL8211B_INER_INIT); 347 } else { 348 err = phy_write(phydev, RTL821x_INER, 0); 349 if (err) 350 return err; 351 352 err = rtl821x_ack_interrupt(phydev); 353 } 354 355 return err; 356 } 357 358 static int rtl8211e_config_intr(struct phy_device *phydev) 359 { 360 int err; 361 362 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 363 err = rtl821x_ack_interrupt(phydev); 364 if (err) 365 return err; 366 367 err = phy_write(phydev, RTL821x_INER, 368 RTL8211E_INER_LINK_STATUS); 369 } else { 370 err = phy_write(phydev, RTL821x_INER, 0); 371 if (err) 372 return err; 373 374 err = rtl821x_ack_interrupt(phydev); 375 } 376 377 return err; 378 } 379 380 static int rtl8211f_config_intr(struct phy_device *phydev) 381 { 382 struct rtl821x_priv *priv = phydev->priv; 383 u16 val; 384 int err; 385 386 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 387 err = rtl8211f_ack_interrupt(phydev); 388 if (err) 389 return err; 390 391 val = RTL8211F_INER_LINK_STATUS; 392 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 393 if (err == 0) 394 priv->iner = val; 395 } else { 396 priv->iner = val = 0; 397 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 398 if (err) 399 return err; 400 401 err = rtl8211f_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 408 { 409 int irq_status; 410 411 irq_status = phy_read(phydev, RTL8201F_ISR); 412 if (irq_status < 0) { 413 phy_error(phydev); 414 return IRQ_NONE; 415 } 416 417 if (!(irq_status & RTL8201F_ISR_MASK)) 418 return IRQ_NONE; 419 420 phy_trigger_machine(phydev); 421 422 return IRQ_HANDLED; 423 } 424 425 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 426 { 427 int irq_status, irq_enabled; 428 429 irq_status = phy_read(phydev, RTL821x_INSR); 430 if (irq_status < 0) { 431 phy_error(phydev); 432 return IRQ_NONE; 433 } 434 435 irq_enabled = phy_read(phydev, RTL821x_INER); 436 if (irq_enabled < 0) { 437 phy_error(phydev); 438 return IRQ_NONE; 439 } 440 441 if (!(irq_status & irq_enabled)) 442 return IRQ_NONE; 443 444 phy_trigger_machine(phydev); 445 446 return IRQ_HANDLED; 447 } 448 449 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 450 { 451 int irq_status; 452 453 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 454 if (irq_status < 0) { 455 phy_error(phydev); 456 return IRQ_NONE; 457 } 458 459 if (irq_status & RTL8211F_INER_LINK_STATUS) { 460 phy_trigger_machine(phydev); 461 return IRQ_HANDLED; 462 } 463 464 if (irq_status & RTL8211F_INER_PME) { 465 pm_wakeup_event(&phydev->mdio.dev, 0); 466 return IRQ_HANDLED; 467 } 468 469 return IRQ_NONE; 470 } 471 472 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 473 { 474 int wol_events; 475 476 /* If the PHY is not capable of waking the system, then WoL can not 477 * be supported. 478 */ 479 if (!device_can_wakeup(&dev->mdio.dev)) { 480 wol->supported = 0; 481 return; 482 } 483 484 wol->supported = WAKE_MAGIC; 485 486 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 487 if (wol_events < 0) 488 return; 489 490 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 491 wol->wolopts = WAKE_MAGIC; 492 } 493 494 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 495 { 496 const u8 *mac_addr = dev->attached_dev->dev_addr; 497 int oldpage; 498 499 if (!device_can_wakeup(&dev->mdio.dev)) 500 return -EOPNOTSUPP; 501 502 oldpage = phy_save_page(dev); 503 if (oldpage < 0) 504 goto err; 505 506 if (wol->wolopts & WAKE_MAGIC) { 507 /* Store the device address for the magic packet */ 508 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 509 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 510 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 511 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 512 513 /* Enable magic packet matching */ 514 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 515 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 516 /* Set the maximum packet size, and assert WoL reset */ 517 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 518 } else { 519 /* Disable magic packet matching */ 520 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 521 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 522 523 /* Place WoL in reset */ 524 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 525 RTL8211F_WOL_RG_RSTB); 526 } 527 528 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 529 530 err: 531 return phy_restore_page(dev, oldpage, 0); 532 } 533 534 static int rtl8211_config_aneg(struct phy_device *phydev) 535 { 536 int ret; 537 538 ret = genphy_config_aneg(phydev); 539 if (ret < 0) 540 return ret; 541 542 /* Quirk was copied from vendor driver. Unfortunately it includes no 543 * description of the magic numbers. 544 */ 545 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 546 phy_write(phydev, 0x17, 0x2138); 547 phy_write(phydev, 0x0e, 0x0260); 548 } else { 549 phy_write(phydev, 0x17, 0x2108); 550 phy_write(phydev, 0x0e, 0x0000); 551 } 552 553 return 0; 554 } 555 556 static int rtl8211c_config_init(struct phy_device *phydev) 557 { 558 /* RTL8211C has an issue when operating in Gigabit slave mode */ 559 return phy_set_bits(phydev, MII_CTRL1000, 560 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 561 } 562 563 static int rtl8211f_config_init(struct phy_device *phydev) 564 { 565 struct rtl821x_priv *priv = phydev->priv; 566 struct device *dev = &phydev->mdio.dev; 567 u16 val_txdly, val_rxdly; 568 int ret; 569 570 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 571 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 572 priv->phycr1); 573 if (ret < 0) { 574 dev_err(dev, "aldps mode configuration failed: %pe\n", 575 ERR_PTR(ret)); 576 return ret; 577 } 578 579 switch (phydev->interface) { 580 case PHY_INTERFACE_MODE_RGMII: 581 val_txdly = 0; 582 val_rxdly = 0; 583 break; 584 585 case PHY_INTERFACE_MODE_RGMII_RXID: 586 val_txdly = 0; 587 val_rxdly = RTL8211F_RX_DELAY; 588 break; 589 590 case PHY_INTERFACE_MODE_RGMII_TXID: 591 val_txdly = RTL8211F_TX_DELAY; 592 val_rxdly = 0; 593 break; 594 595 case PHY_INTERFACE_MODE_RGMII_ID: 596 val_txdly = RTL8211F_TX_DELAY; 597 val_rxdly = RTL8211F_RX_DELAY; 598 break; 599 600 default: /* the rest of the modes imply leaving delay as is. */ 601 return 0; 602 } 603 604 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 605 RTL8211F_TXCR, RTL8211F_TX_DELAY, 606 val_txdly); 607 if (ret < 0) { 608 dev_err(dev, "Failed to update the TX delay register\n"); 609 return ret; 610 } else if (ret) { 611 dev_dbg(dev, 612 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 613 str_enable_disable(val_txdly)); 614 } else { 615 dev_dbg(dev, 616 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 617 str_enabled_disabled(val_txdly)); 618 } 619 620 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 621 RTL8211F_RXCR, RTL8211F_RX_DELAY, 622 val_rxdly); 623 if (ret < 0) { 624 dev_err(dev, "Failed to update the RX delay register\n"); 625 return ret; 626 } else if (ret) { 627 dev_dbg(dev, 628 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 629 str_enable_disable(val_rxdly)); 630 } else { 631 dev_dbg(dev, 632 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 633 str_enabled_disabled(val_rxdly)); 634 } 635 636 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 637 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 638 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 639 if (ret) 640 return ret; 641 642 if (priv->has_phycr2) { 643 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 644 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 645 priv->phycr2); 646 if (ret < 0) { 647 dev_err(dev, "clkout configuration failed: %pe\n", 648 ERR_PTR(ret)); 649 return ret; 650 } 651 652 return genphy_soft_reset(phydev); 653 } 654 655 return 0; 656 } 657 658 static int rtl821x_suspend(struct phy_device *phydev) 659 { 660 struct rtl821x_priv *priv = phydev->priv; 661 int ret = 0; 662 663 if (!phydev->wol_enabled) { 664 ret = genphy_suspend(phydev); 665 666 if (ret) 667 return ret; 668 669 clk_disable_unprepare(priv->clk); 670 } 671 672 return ret; 673 } 674 675 static int rtl8211f_suspend(struct phy_device *phydev) 676 { 677 u16 wol_rst; 678 int ret; 679 680 ret = rtl821x_suspend(phydev); 681 if (ret < 0) 682 return ret; 683 684 /* If a PME event is enabled, then configure the interrupt for 685 * PME events only, disabling link interrupt. We avoid switching 686 * to PMEB mode as we don't have a status bit for that. 687 */ 688 if (device_may_wakeup(&phydev->mdio.dev)) { 689 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 690 RTL8211F_INER_PME); 691 if (ret < 0) 692 goto err; 693 694 /* Read the INSR to clear any pending interrupt */ 695 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 696 697 /* Reset the WoL to ensure that an event is picked up. 698 * Unless we do this, even if we receive another packet, 699 * we may not have a PME interrupt raised. 700 */ 701 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 702 RTL8211F_WOL_RST_RMSQ); 703 if (ret < 0) 704 goto err; 705 706 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 707 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 708 RTL8211F_WOL_RST_RMSQ, wol_rst); 709 if (ret < 0) 710 goto err; 711 712 wol_rst |= RTL8211F_WOL_RG_RSTB; 713 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 714 RTL8211F_WOL_RST_RMSQ, wol_rst); 715 } 716 717 err: 718 return ret; 719 } 720 721 static int rtl821x_resume(struct phy_device *phydev) 722 { 723 struct rtl821x_priv *priv = phydev->priv; 724 int ret; 725 726 if (!phydev->wol_enabled) 727 clk_prepare_enable(priv->clk); 728 729 ret = genphy_resume(phydev); 730 if (ret < 0) 731 return ret; 732 733 msleep(20); 734 735 return 0; 736 } 737 738 static int rtl8211f_resume(struct phy_device *phydev) 739 { 740 struct rtl821x_priv *priv = phydev->priv; 741 int ret; 742 743 ret = rtl821x_resume(phydev); 744 if (ret < 0) 745 return ret; 746 747 /* If the device was programmed for a PME event, restore the interrupt 748 * enable so phylib can receive link state interrupts. 749 */ 750 if (device_may_wakeup(&phydev->mdio.dev)) 751 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 752 753 return ret; 754 } 755 756 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 757 unsigned long rules) 758 { 759 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 760 BIT(TRIGGER_NETDEV_LINK_100) | 761 BIT(TRIGGER_NETDEV_LINK_1000) | 762 BIT(TRIGGER_NETDEV_RX) | 763 BIT(TRIGGER_NETDEV_TX); 764 765 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 766 * - Link: Configurable subset of 10/100/1000 link rates 767 * - Active: Blink on activity, RX or TX is not differentiated 768 * The Active option has two modes, A and B: 769 * - A: Link and Active indication at configurable, but matching, 770 * subset of 10/100/1000 link rates 771 * - B: Link indication at configurable subset of 10/100/1000 link 772 * rates and Active indication always at all three 10+100+1000 773 * link rates. 774 * This code currently uses mode B only. 775 * 776 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 777 */ 778 779 if (index >= RTL8211x_LED_COUNT) 780 return -EINVAL; 781 782 /* Filter out any other unsupported triggers. */ 783 if (rules & ~mask) 784 return -EOPNOTSUPP; 785 786 /* RX and TX are not differentiated, either both are set or not set. */ 787 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 788 return -EOPNOTSUPP; 789 790 return 0; 791 } 792 793 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 794 unsigned long *rules) 795 { 796 int val; 797 798 if (index >= RTL8211x_LED_COUNT) 799 return -EINVAL; 800 801 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 802 if (val < 0) 803 return val; 804 805 val >>= RTL8211F_LEDCR_SHIFT * index; 806 val &= RTL8211F_LEDCR_MASK; 807 808 if (val & RTL8211F_LEDCR_LINK_10) 809 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 810 811 if (val & RTL8211F_LEDCR_LINK_100) 812 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 813 814 if (val & RTL8211F_LEDCR_LINK_1000) 815 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 816 817 if (val & RTL8211F_LEDCR_ACT_TXRX) { 818 __set_bit(TRIGGER_NETDEV_RX, rules); 819 __set_bit(TRIGGER_NETDEV_TX, rules); 820 } 821 822 return 0; 823 } 824 825 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 826 unsigned long rules) 827 { 828 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 829 u16 reg = 0; 830 831 if (index >= RTL8211x_LED_COUNT) 832 return -EINVAL; 833 834 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 835 reg |= RTL8211F_LEDCR_LINK_10; 836 837 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 838 reg |= RTL8211F_LEDCR_LINK_100; 839 840 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 841 reg |= RTL8211F_LEDCR_LINK_1000; 842 843 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 844 test_bit(TRIGGER_NETDEV_TX, &rules)) { 845 reg |= RTL8211F_LEDCR_ACT_TXRX; 846 } 847 848 reg <<= RTL8211F_LEDCR_SHIFT * index; 849 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 850 851 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 852 } 853 854 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 855 unsigned long *rules) 856 { 857 int ret; 858 u16 cr1, cr2; 859 860 if (index >= RTL8211x_LED_COUNT) 861 return -EINVAL; 862 863 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 864 RTL8211E_LEDCR1); 865 if (ret < 0) 866 return ret; 867 868 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 869 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 870 __set_bit(TRIGGER_NETDEV_RX, rules); 871 __set_bit(TRIGGER_NETDEV_TX, rules); 872 } 873 874 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 875 RTL8211E_LEDCR2); 876 if (ret < 0) 877 return ret; 878 879 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 880 if (cr2 & RTL8211E_LEDCR2_LINK_10) 881 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 882 883 if (cr2 & RTL8211E_LEDCR2_LINK_100) 884 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 885 886 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 887 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 888 889 return ret; 890 } 891 892 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 893 unsigned long rules) 894 { 895 const u16 cr1mask = 896 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 897 const u16 cr2mask = 898 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 899 u16 cr1 = 0, cr2 = 0; 900 int ret; 901 902 if (index >= RTL8211x_LED_COUNT) 903 return -EINVAL; 904 905 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 906 test_bit(TRIGGER_NETDEV_TX, &rules)) { 907 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 908 } 909 910 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 911 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 912 RTL8211E_LEDCR1, cr1mask, cr1); 913 if (ret < 0) 914 return ret; 915 916 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 917 cr2 |= RTL8211E_LEDCR2_LINK_10; 918 919 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 920 cr2 |= RTL8211E_LEDCR2_LINK_100; 921 922 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 923 cr2 |= RTL8211E_LEDCR2_LINK_1000; 924 925 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 926 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 927 RTL8211E_LEDCR2, cr2mask, cr2); 928 929 return ret; 930 } 931 932 static int rtl8211e_config_init(struct phy_device *phydev) 933 { 934 u16 val; 935 936 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 937 switch (phydev->interface) { 938 case PHY_INTERFACE_MODE_RGMII: 939 val = RTL8211E_CTRL_DELAY | 0; 940 break; 941 case PHY_INTERFACE_MODE_RGMII_ID: 942 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 943 break; 944 case PHY_INTERFACE_MODE_RGMII_RXID: 945 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 946 break; 947 case PHY_INTERFACE_MODE_RGMII_TXID: 948 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 949 break; 950 default: /* the rest of the modes imply leaving delays as is. */ 951 return 0; 952 } 953 954 /* According to a sample driver there is a 0x1c config register on the 955 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 956 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 957 * The configuration register definition: 958 * 14 = reserved 959 * 13 = Force Tx RX Delay controlled by bit12 bit11, 960 * 12 = RX Delay, 11 = TX Delay 961 * 10:0 = Test && debug settings reserved by realtek 962 */ 963 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 964 RTL8211E_RGMII_DELAY, 965 RTL8211E_DELAY_MASK, val); 966 } 967 968 static int rtl8211b_suspend(struct phy_device *phydev) 969 { 970 phy_write(phydev, MII_MMD_DATA, BIT(9)); 971 972 return genphy_suspend(phydev); 973 } 974 975 static int rtl8211b_resume(struct phy_device *phydev) 976 { 977 phy_write(phydev, MII_MMD_DATA, 0); 978 979 return genphy_resume(phydev); 980 } 981 982 static int rtl8366rb_config_init(struct phy_device *phydev) 983 { 984 int ret; 985 986 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 987 RTL8366RB_POWER_SAVE_ON); 988 if (ret) { 989 dev_err(&phydev->mdio.dev, 990 "error enabling power management\n"); 991 } 992 993 return ret; 994 } 995 996 /* get actual speed to cover the downshift case */ 997 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 998 { 999 /* bit 3 1000 * 0: Half Duplex 1001 * 1: Full Duplex 1002 */ 1003 if (val & RTL_VND2_PHYSR_DUPLEX) 1004 phydev->duplex = DUPLEX_FULL; 1005 else 1006 phydev->duplex = DUPLEX_HALF; 1007 1008 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1009 case 0x0000: 1010 phydev->speed = SPEED_10; 1011 break; 1012 case 0x0010: 1013 phydev->speed = SPEED_100; 1014 break; 1015 case 0x0020: 1016 phydev->speed = SPEED_1000; 1017 break; 1018 case 0x0200: 1019 phydev->speed = SPEED_10000; 1020 break; 1021 case 0x0210: 1022 phydev->speed = SPEED_2500; 1023 break; 1024 case 0x0220: 1025 phydev->speed = SPEED_5000; 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 /* bit 11 1032 * 0: Slave Mode 1033 * 1: Master Mode 1034 */ 1035 if (phydev->speed >= 1000) { 1036 if (val & RTL_VND2_PHYSR_MASTER) 1037 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1038 else 1039 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1040 } else { 1041 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1042 } 1043 } 1044 1045 static int rtlgen_read_status(struct phy_device *phydev) 1046 { 1047 int ret, val; 1048 1049 ret = genphy_read_status(phydev); 1050 if (ret < 0) 1051 return ret; 1052 1053 if (!phydev->link) 1054 return 0; 1055 1056 val = phy_read_paged(phydev, 0xa43, 0x12); 1057 if (val < 0) 1058 return val; 1059 1060 rtlgen_decode_physr(phydev, val); 1061 1062 return 0; 1063 } 1064 1065 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1066 { 1067 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1068 } 1069 1070 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1071 { 1072 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1073 val); 1074 } 1075 1076 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1077 { 1078 int ret; 1079 1080 if (devnum == MDIO_MMD_VEND2) 1081 ret = rtlgen_read_vend2(phydev, regnum); 1082 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1083 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1084 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1085 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1086 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1087 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1088 else 1089 ret = -EOPNOTSUPP; 1090 1091 return ret; 1092 } 1093 1094 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1095 u16 val) 1096 { 1097 int ret; 1098 1099 if (devnum == MDIO_MMD_VEND2) 1100 ret = rtlgen_write_vend2(phydev, regnum, val); 1101 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1102 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1103 else 1104 ret = -EOPNOTSUPP; 1105 1106 return ret; 1107 } 1108 1109 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1110 { 1111 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1112 1113 if (ret != -EOPNOTSUPP) 1114 return ret; 1115 1116 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1117 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1118 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1119 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1120 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1121 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1122 1123 return ret; 1124 } 1125 1126 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1127 u16 val) 1128 { 1129 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1130 1131 if (ret != -EOPNOTSUPP) 1132 return ret; 1133 1134 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1135 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1136 1137 return ret; 1138 } 1139 1140 static int rtl822x_probe(struct phy_device *phydev) 1141 { 1142 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1143 phydev->phy_id != RTL_GENERIC_PHYID) 1144 return rtl822x_hwmon_init(phydev); 1145 1146 return 0; 1147 } 1148 1149 static int rtl822xb_config_init(struct phy_device *phydev) 1150 { 1151 bool has_2500, has_sgmii; 1152 u16 mode; 1153 int ret; 1154 1155 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1156 phydev->host_interfaces) || 1157 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1158 1159 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1160 phydev->host_interfaces) || 1161 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1162 1163 /* fill in possible interfaces */ 1164 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1165 has_2500); 1166 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1167 has_sgmii); 1168 1169 if (!has_2500 && !has_sgmii) 1170 return 0; 1171 1172 /* determine SerDes option mode */ 1173 if (has_2500 && !has_sgmii) { 1174 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1175 phydev->rate_matching = RATE_MATCH_PAUSE; 1176 } else { 1177 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1178 phydev->rate_matching = RATE_MATCH_NONE; 1179 } 1180 1181 /* the following sequence with magic numbers sets up the SerDes 1182 * option mode 1183 */ 1184 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1185 if (ret < 0) 1186 return ret; 1187 1188 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1189 RTL822X_VND1_SERDES_OPTION, 1190 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1191 mode); 1192 if (ret < 0) 1193 return ret; 1194 1195 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1196 if (ret < 0) 1197 return ret; 1198 1199 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1200 if (ret < 0) 1201 return ret; 1202 1203 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1204 } 1205 1206 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1207 phy_interface_t iface) 1208 { 1209 int val; 1210 1211 /* Only rate matching at 2500base-x */ 1212 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1213 return RATE_MATCH_NONE; 1214 1215 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1216 if (val < 0) 1217 return val; 1218 1219 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1220 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1221 return RATE_MATCH_PAUSE; 1222 1223 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1224 return RATE_MATCH_NONE; 1225 } 1226 1227 static int rtl822x_get_features(struct phy_device *phydev) 1228 { 1229 int val; 1230 1231 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1232 if (val < 0) 1233 return val; 1234 1235 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1236 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1237 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1238 phydev->supported, val & MDIO_PMA_SPEED_5G); 1239 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1240 phydev->supported, val & MDIO_SPEED_10G); 1241 1242 return genphy_read_abilities(phydev); 1243 } 1244 1245 static int rtl822x_config_aneg(struct phy_device *phydev) 1246 { 1247 int ret = 0; 1248 1249 if (phydev->autoneg == AUTONEG_ENABLE) { 1250 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1251 1252 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1253 RTL_MDIO_AN_10GBT_CTRL, 1254 MDIO_AN_10GBT_CTRL_ADV2_5G | 1255 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1256 if (ret < 0) 1257 return ret; 1258 } 1259 1260 return __genphy_config_aneg(phydev, ret); 1261 } 1262 1263 static void rtl822xb_update_interface(struct phy_device *phydev) 1264 { 1265 int val; 1266 1267 if (!phydev->link) 1268 return; 1269 1270 /* Change interface according to serdes mode */ 1271 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1272 if (val < 0) 1273 return; 1274 1275 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1276 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1277 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1278 break; 1279 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1280 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1281 break; 1282 } 1283 } 1284 1285 static int rtl822x_read_status(struct phy_device *phydev) 1286 { 1287 int lpadv, ret; 1288 1289 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1290 1291 ret = rtlgen_read_status(phydev); 1292 if (ret < 0) 1293 return ret; 1294 1295 if (phydev->autoneg == AUTONEG_DISABLE || 1296 !phydev->autoneg_complete) 1297 return 0; 1298 1299 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1300 if (lpadv < 0) 1301 return lpadv; 1302 1303 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1304 1305 return 0; 1306 } 1307 1308 static int rtl822xb_read_status(struct phy_device *phydev) 1309 { 1310 int ret; 1311 1312 ret = rtl822x_read_status(phydev); 1313 if (ret < 0) 1314 return ret; 1315 1316 rtl822xb_update_interface(phydev); 1317 1318 return 0; 1319 } 1320 1321 static int rtl822x_c45_get_features(struct phy_device *phydev) 1322 { 1323 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1324 phydev->supported); 1325 1326 return genphy_c45_pma_read_abilities(phydev); 1327 } 1328 1329 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1330 { 1331 bool changed = false; 1332 int ret, val; 1333 1334 if (phydev->autoneg == AUTONEG_DISABLE) 1335 return genphy_c45_pma_setup_forced(phydev); 1336 1337 ret = genphy_c45_an_config_aneg(phydev); 1338 if (ret < 0) 1339 return ret; 1340 if (ret > 0) 1341 changed = true; 1342 1343 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1344 1345 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1346 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1347 RTL822X_VND2_C22_REG(MII_CTRL1000), 1348 ADVERTISE_1000FULL, val); 1349 if (ret < 0) 1350 return ret; 1351 if (ret > 0) 1352 changed = true; 1353 1354 return genphy_c45_check_and_restart_aneg(phydev, changed); 1355 } 1356 1357 static int rtl822x_c45_read_status(struct phy_device *phydev) 1358 { 1359 int ret, val; 1360 1361 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1362 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1363 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1364 RTL822X_VND2_C22_REG(MII_STAT1000)); 1365 if (val < 0) 1366 return val; 1367 } else { 1368 val = 0; 1369 } 1370 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1371 1372 ret = genphy_c45_read_status(phydev); 1373 if (ret < 0) 1374 return ret; 1375 1376 if (!phydev->link) { 1377 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1378 return 0; 1379 } 1380 1381 /* Read actual speed from vendor register. */ 1382 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1383 if (val < 0) 1384 return val; 1385 1386 rtlgen_decode_physr(phydev, val); 1387 1388 return 0; 1389 } 1390 1391 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1392 { 1393 int ret, val; 1394 1395 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1396 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1397 if (ret < 0) 1398 return ret; 1399 1400 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1401 MDIO_CTRL1, val, 1402 !(val & MDIO_CTRL1_RESET), 1403 5000, 100000, true); 1404 } 1405 1406 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1407 { 1408 int ret; 1409 1410 ret = rtl822x_c45_read_status(phydev); 1411 if (ret < 0) 1412 return ret; 1413 1414 rtl822xb_update_interface(phydev); 1415 1416 return 0; 1417 } 1418 1419 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1420 { 1421 int val; 1422 1423 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1424 val = phy_read(phydev, 0x13); 1425 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1426 1427 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1428 } 1429 1430 /* On internal PHY's MMD reads over C22 always return 0. 1431 * Check a MMD register which is known to be non-zero. 1432 */ 1433 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1434 { 1435 int val; 1436 1437 phy_lock_mdio_bus(phydev); 1438 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1439 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1440 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1441 val = __phy_read(phydev, MII_MMD_DATA); 1442 phy_unlock_mdio_bus(phydev); 1443 1444 return val > 0; 1445 } 1446 1447 static int rtlgen_match_phy_device(struct phy_device *phydev, 1448 const struct phy_driver *phydrv) 1449 { 1450 return phydev->phy_id == RTL_GENERIC_PHYID && 1451 !rtlgen_supports_2_5gbps(phydev); 1452 } 1453 1454 static int rtl8226_match_phy_device(struct phy_device *phydev, 1455 const struct phy_driver *phydrv) 1456 { 1457 return phydev->phy_id == RTL_GENERIC_PHYID && 1458 rtlgen_supports_2_5gbps(phydev) && 1459 rtlgen_supports_mmd(phydev); 1460 } 1461 1462 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1463 bool is_c45) 1464 { 1465 if (phydev->is_c45) 1466 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1467 else 1468 return !is_c45 && (id == phydev->phy_id); 1469 } 1470 1471 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1472 const struct phy_driver *phydrv) 1473 { 1474 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1475 } 1476 1477 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1478 const struct phy_driver *phydrv) 1479 { 1480 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1481 } 1482 1483 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1484 const struct phy_driver *phydrv) 1485 { 1486 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1487 } 1488 1489 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, 1490 const struct phy_driver *phydrv) 1491 { 1492 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1493 } 1494 1495 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, 1496 const struct phy_driver *phydrv) 1497 { 1498 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1499 } 1500 1501 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1502 const struct phy_driver *phydrv) 1503 { 1504 if (phydev->is_c45) 1505 return false; 1506 1507 switch (phydev->phy_id) { 1508 case RTL_GENERIC_PHYID: 1509 case RTL_8221B: 1510 case RTL_8251B: 1511 case RTL_8261C: 1512 case 0x001cc841: 1513 break; 1514 default: 1515 return false; 1516 } 1517 1518 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1519 } 1520 1521 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1522 const struct phy_driver *phydrv) 1523 { 1524 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1525 } 1526 1527 static int rtlgen_resume(struct phy_device *phydev) 1528 { 1529 int ret = genphy_resume(phydev); 1530 1531 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1532 msleep(20); 1533 1534 return ret; 1535 } 1536 1537 static int rtlgen_c45_resume(struct phy_device *phydev) 1538 { 1539 int ret = genphy_c45_pma_resume(phydev); 1540 1541 msleep(20); 1542 1543 return ret; 1544 } 1545 1546 static int rtl9000a_config_init(struct phy_device *phydev) 1547 { 1548 phydev->autoneg = AUTONEG_DISABLE; 1549 phydev->speed = SPEED_100; 1550 phydev->duplex = DUPLEX_FULL; 1551 1552 return 0; 1553 } 1554 1555 static int rtl9000a_config_aneg(struct phy_device *phydev) 1556 { 1557 int ret; 1558 u16 ctl = 0; 1559 1560 switch (phydev->master_slave_set) { 1561 case MASTER_SLAVE_CFG_MASTER_FORCE: 1562 ctl |= CTL1000_AS_MASTER; 1563 break; 1564 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1565 break; 1566 case MASTER_SLAVE_CFG_UNKNOWN: 1567 case MASTER_SLAVE_CFG_UNSUPPORTED: 1568 return 0; 1569 default: 1570 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1571 return -EOPNOTSUPP; 1572 } 1573 1574 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1575 if (ret == 1) 1576 ret = genphy_soft_reset(phydev); 1577 1578 return ret; 1579 } 1580 1581 static int rtl9000a_read_status(struct phy_device *phydev) 1582 { 1583 int ret; 1584 1585 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1586 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1587 1588 ret = genphy_update_link(phydev); 1589 if (ret) 1590 return ret; 1591 1592 ret = phy_read(phydev, MII_CTRL1000); 1593 if (ret < 0) 1594 return ret; 1595 if (ret & CTL1000_AS_MASTER) 1596 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1597 else 1598 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1599 1600 ret = phy_read(phydev, MII_STAT1000); 1601 if (ret < 0) 1602 return ret; 1603 if (ret & LPA_1000MSRES) 1604 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1605 else 1606 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1607 1608 return 0; 1609 } 1610 1611 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1612 { 1613 int err; 1614 1615 err = phy_read(phydev, RTL8211F_INSR); 1616 1617 return (err < 0) ? err : 0; 1618 } 1619 1620 static int rtl9000a_config_intr(struct phy_device *phydev) 1621 { 1622 u16 val; 1623 int err; 1624 1625 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1626 err = rtl9000a_ack_interrupt(phydev); 1627 if (err) 1628 return err; 1629 1630 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1631 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1632 } else { 1633 val = ~0; 1634 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1635 if (err) 1636 return err; 1637 1638 err = rtl9000a_ack_interrupt(phydev); 1639 } 1640 1641 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1642 } 1643 1644 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1645 { 1646 int irq_status; 1647 1648 irq_status = phy_read(phydev, RTL8211F_INSR); 1649 if (irq_status < 0) { 1650 phy_error(phydev); 1651 return IRQ_NONE; 1652 } 1653 1654 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1655 return IRQ_NONE; 1656 1657 phy_trigger_machine(phydev); 1658 1659 return IRQ_HANDLED; 1660 } 1661 1662 static struct phy_driver realtek_drvs[] = { 1663 { 1664 PHY_ID_MATCH_EXACT(0x00008201), 1665 .name = "RTL8201CP Ethernet", 1666 .read_page = rtl821x_read_page, 1667 .write_page = rtl821x_write_page, 1668 }, { 1669 PHY_ID_MATCH_EXACT(0x001cc816), 1670 .name = "RTL8201F Fast Ethernet", 1671 .config_intr = &rtl8201_config_intr, 1672 .handle_interrupt = rtl8201_handle_interrupt, 1673 .suspend = genphy_suspend, 1674 .resume = genphy_resume, 1675 .read_page = rtl821x_read_page, 1676 .write_page = rtl821x_write_page, 1677 }, { 1678 PHY_ID_MATCH_MODEL(0x001cc880), 1679 .name = "RTL8208 Fast Ethernet", 1680 .read_mmd = genphy_read_mmd_unsupported, 1681 .write_mmd = genphy_write_mmd_unsupported, 1682 .suspend = genphy_suspend, 1683 .resume = genphy_resume, 1684 .read_page = rtl821x_read_page, 1685 .write_page = rtl821x_write_page, 1686 }, { 1687 PHY_ID_MATCH_EXACT(0x001cc910), 1688 .name = "RTL8211 Gigabit Ethernet", 1689 .config_aneg = rtl8211_config_aneg, 1690 .read_mmd = &genphy_read_mmd_unsupported, 1691 .write_mmd = &genphy_write_mmd_unsupported, 1692 .read_page = rtl821x_read_page, 1693 .write_page = rtl821x_write_page, 1694 }, { 1695 PHY_ID_MATCH_EXACT(0x001cc912), 1696 .name = "RTL8211B Gigabit Ethernet", 1697 .config_intr = &rtl8211b_config_intr, 1698 .handle_interrupt = rtl821x_handle_interrupt, 1699 .read_mmd = &genphy_read_mmd_unsupported, 1700 .write_mmd = &genphy_write_mmd_unsupported, 1701 .suspend = rtl8211b_suspend, 1702 .resume = rtl8211b_resume, 1703 .read_page = rtl821x_read_page, 1704 .write_page = rtl821x_write_page, 1705 }, { 1706 PHY_ID_MATCH_EXACT(0x001cc913), 1707 .name = "RTL8211C Gigabit Ethernet", 1708 .config_init = rtl8211c_config_init, 1709 .read_mmd = &genphy_read_mmd_unsupported, 1710 .write_mmd = &genphy_write_mmd_unsupported, 1711 .read_page = rtl821x_read_page, 1712 .write_page = rtl821x_write_page, 1713 }, { 1714 PHY_ID_MATCH_EXACT(0x001cc914), 1715 .name = "RTL8211DN Gigabit Ethernet", 1716 .config_intr = rtl8211e_config_intr, 1717 .handle_interrupt = rtl821x_handle_interrupt, 1718 .suspend = genphy_suspend, 1719 .resume = genphy_resume, 1720 .read_page = rtl821x_read_page, 1721 .write_page = rtl821x_write_page, 1722 }, { 1723 PHY_ID_MATCH_EXACT(0x001cc915), 1724 .name = "RTL8211E Gigabit Ethernet", 1725 .config_init = &rtl8211e_config_init, 1726 .config_intr = &rtl8211e_config_intr, 1727 .handle_interrupt = rtl821x_handle_interrupt, 1728 .suspend = genphy_suspend, 1729 .resume = genphy_resume, 1730 .read_page = rtl821x_read_page, 1731 .write_page = rtl821x_write_page, 1732 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1733 .led_hw_control_get = rtl8211e_led_hw_control_get, 1734 .led_hw_control_set = rtl8211e_led_hw_control_set, 1735 }, { 1736 PHY_ID_MATCH_EXACT(0x001cc916), 1737 .name = "RTL8211F Gigabit Ethernet", 1738 .probe = rtl8211f_probe, 1739 .config_init = &rtl8211f_config_init, 1740 .read_status = rtlgen_read_status, 1741 .config_intr = &rtl8211f_config_intr, 1742 .handle_interrupt = rtl8211f_handle_interrupt, 1743 .set_wol = rtl8211f_set_wol, 1744 .get_wol = rtl8211f_get_wol, 1745 .suspend = rtl8211f_suspend, 1746 .resume = rtl8211f_resume, 1747 .read_page = rtl821x_read_page, 1748 .write_page = rtl821x_write_page, 1749 .flags = PHY_ALWAYS_CALL_SUSPEND, 1750 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1751 .led_hw_control_get = rtl8211f_led_hw_control_get, 1752 .led_hw_control_set = rtl8211f_led_hw_control_set, 1753 }, { 1754 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1755 .name = "RTL8211F-VD Gigabit Ethernet", 1756 .probe = rtl821x_probe, 1757 .config_init = &rtl8211f_config_init, 1758 .read_status = rtlgen_read_status, 1759 .config_intr = &rtl8211f_config_intr, 1760 .handle_interrupt = rtl8211f_handle_interrupt, 1761 .suspend = rtl821x_suspend, 1762 .resume = rtl821x_resume, 1763 .read_page = rtl821x_read_page, 1764 .write_page = rtl821x_write_page, 1765 .flags = PHY_ALWAYS_CALL_SUSPEND, 1766 }, { 1767 .name = "Generic FE-GE Realtek PHY", 1768 .match_phy_device = rtlgen_match_phy_device, 1769 .read_status = rtlgen_read_status, 1770 .suspend = genphy_suspend, 1771 .resume = rtlgen_resume, 1772 .read_page = rtl821x_read_page, 1773 .write_page = rtl821x_write_page, 1774 .read_mmd = rtlgen_read_mmd, 1775 .write_mmd = rtlgen_write_mmd, 1776 }, { 1777 .name = "RTL8226 2.5Gbps PHY", 1778 .match_phy_device = rtl8226_match_phy_device, 1779 .get_features = rtl822x_get_features, 1780 .config_aneg = rtl822x_config_aneg, 1781 .read_status = rtl822x_read_status, 1782 .suspend = genphy_suspend, 1783 .resume = rtlgen_resume, 1784 .read_page = rtl821x_read_page, 1785 .write_page = rtl821x_write_page, 1786 }, { 1787 .match_phy_device = rtl8221b_match_phy_device, 1788 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1789 .get_features = rtl822x_get_features, 1790 .config_aneg = rtl822x_config_aneg, 1791 .config_init = rtl822xb_config_init, 1792 .get_rate_matching = rtl822xb_get_rate_matching, 1793 .read_status = rtl822xb_read_status, 1794 .suspend = genphy_suspend, 1795 .resume = rtlgen_resume, 1796 .read_page = rtl821x_read_page, 1797 .write_page = rtl821x_write_page, 1798 }, { 1799 PHY_ID_MATCH_EXACT(0x001cc838), 1800 .name = "RTL8226-CG 2.5Gbps PHY", 1801 .soft_reset = rtl822x_c45_soft_reset, 1802 .get_features = rtl822x_c45_get_features, 1803 .config_aneg = rtl822x_c45_config_aneg, 1804 .read_status = rtl822x_c45_read_status, 1805 .suspend = genphy_c45_pma_suspend, 1806 .resume = rtlgen_c45_resume, 1807 }, { 1808 PHY_ID_MATCH_EXACT(0x001cc848), 1809 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1810 .get_features = rtl822x_get_features, 1811 .config_aneg = rtl822x_config_aneg, 1812 .config_init = rtl822xb_config_init, 1813 .get_rate_matching = rtl822xb_get_rate_matching, 1814 .read_status = rtl822xb_read_status, 1815 .suspend = genphy_suspend, 1816 .resume = rtlgen_resume, 1817 .read_page = rtl821x_read_page, 1818 .write_page = rtl821x_write_page, 1819 }, { 1820 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1821 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1822 .probe = rtl822x_probe, 1823 .get_features = rtl822x_get_features, 1824 .config_aneg = rtl822x_config_aneg, 1825 .config_init = rtl822xb_config_init, 1826 .get_rate_matching = rtl822xb_get_rate_matching, 1827 .read_status = rtl822xb_read_status, 1828 .suspend = genphy_suspend, 1829 .resume = rtlgen_resume, 1830 .read_page = rtl821x_read_page, 1831 .write_page = rtl821x_write_page, 1832 }, { 1833 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1834 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1835 .probe = rtl822x_probe, 1836 .config_init = rtl822xb_config_init, 1837 .get_rate_matching = rtl822xb_get_rate_matching, 1838 .get_features = rtl822x_c45_get_features, 1839 .config_aneg = rtl822x_c45_config_aneg, 1840 .read_status = rtl822xb_c45_read_status, 1841 .suspend = genphy_c45_pma_suspend, 1842 .resume = rtlgen_c45_resume, 1843 }, { 1844 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1845 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1846 .probe = rtl822x_probe, 1847 .get_features = rtl822x_get_features, 1848 .config_aneg = rtl822x_config_aneg, 1849 .config_init = rtl822xb_config_init, 1850 .get_rate_matching = rtl822xb_get_rate_matching, 1851 .read_status = rtl822xb_read_status, 1852 .suspend = genphy_suspend, 1853 .resume = rtlgen_resume, 1854 .read_page = rtl821x_read_page, 1855 .write_page = rtl821x_write_page, 1856 }, { 1857 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1858 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1859 .probe = rtl822x_probe, 1860 .config_init = rtl822xb_config_init, 1861 .get_rate_matching = rtl822xb_get_rate_matching, 1862 .get_features = rtl822x_c45_get_features, 1863 .config_aneg = rtl822x_c45_config_aneg, 1864 .read_status = rtl822xb_c45_read_status, 1865 .suspend = genphy_c45_pma_suspend, 1866 .resume = rtlgen_c45_resume, 1867 }, { 1868 .match_phy_device = rtl8251b_c45_match_phy_device, 1869 .name = "RTL8251B 5Gbps PHY", 1870 .probe = rtl822x_probe, 1871 .get_features = rtl822x_get_features, 1872 .config_aneg = rtl822x_config_aneg, 1873 .read_status = rtl822x_read_status, 1874 .suspend = genphy_suspend, 1875 .resume = rtlgen_resume, 1876 .read_page = rtl821x_read_page, 1877 .write_page = rtl821x_write_page, 1878 }, { 1879 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1880 .name = "Realtek Internal NBASE-T PHY", 1881 .flags = PHY_IS_INTERNAL, 1882 .probe = rtl822x_probe, 1883 .get_features = rtl822x_get_features, 1884 .config_aneg = rtl822x_config_aneg, 1885 .read_status = rtl822x_read_status, 1886 .suspend = genphy_suspend, 1887 .resume = rtlgen_resume, 1888 .read_page = rtl821x_read_page, 1889 .write_page = rtl821x_write_page, 1890 .read_mmd = rtl822x_read_mmd, 1891 .write_mmd = rtl822x_write_mmd, 1892 }, { 1893 PHY_ID_MATCH_EXACT(0x001ccad0), 1894 .name = "RTL8224 2.5Gbps PHY", 1895 .get_features = rtl822x_c45_get_features, 1896 .config_aneg = rtl822x_c45_config_aneg, 1897 .read_status = rtl822x_c45_read_status, 1898 .suspend = genphy_c45_pma_suspend, 1899 .resume = rtlgen_c45_resume, 1900 }, { 1901 PHY_ID_MATCH_EXACT(0x001cc961), 1902 .name = "RTL8366RB Gigabit Ethernet", 1903 .config_init = &rtl8366rb_config_init, 1904 /* These interrupts are handled by the irq controller 1905 * embedded inside the RTL8366RB, they get unmasked when the 1906 * irq is requested and ACKed by reading the status register, 1907 * which is done by the irqchip code. 1908 */ 1909 .config_intr = genphy_no_config_intr, 1910 .handle_interrupt = genphy_handle_interrupt_no_ack, 1911 .suspend = genphy_suspend, 1912 .resume = genphy_resume, 1913 }, { 1914 PHY_ID_MATCH_EXACT(0x001ccb00), 1915 .name = "RTL9000AA_RTL9000AN Ethernet", 1916 .features = PHY_BASIC_T1_FEATURES, 1917 .config_init = rtl9000a_config_init, 1918 .config_aneg = rtl9000a_config_aneg, 1919 .read_status = rtl9000a_read_status, 1920 .config_intr = rtl9000a_config_intr, 1921 .handle_interrupt = rtl9000a_handle_interrupt, 1922 .suspend = genphy_suspend, 1923 .resume = genphy_resume, 1924 .read_page = rtl821x_read_page, 1925 .write_page = rtl821x_write_page, 1926 }, { 1927 PHY_ID_MATCH_EXACT(0x001cc942), 1928 .name = "RTL8365MB-VC Gigabit Ethernet", 1929 /* Interrupt handling analogous to RTL8366RB */ 1930 .config_intr = genphy_no_config_intr, 1931 .handle_interrupt = genphy_handle_interrupt_no_ack, 1932 .suspend = genphy_suspend, 1933 .resume = genphy_resume, 1934 }, { 1935 PHY_ID_MATCH_EXACT(0x001cc960), 1936 .name = "RTL8366S Gigabit Ethernet", 1937 .suspend = genphy_suspend, 1938 .resume = genphy_resume, 1939 .read_mmd = genphy_read_mmd_unsupported, 1940 .write_mmd = genphy_write_mmd_unsupported, 1941 }, 1942 }; 1943 1944 module_phy_driver(realtek_drvs); 1945 1946 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1947 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1948 { } 1949 }; 1950 1951 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1952