1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/netdevice.h> 14 #include <linux/module.h> 15 #include <linux/delay.h> 16 #include <linux/clk.h> 17 #include <linux/string_choices.h> 18 19 #include "realtek.h" 20 21 #define RTL8201F_IER 0x13 22 23 #define RTL8201F_ISR 0x1e 24 #define RTL8201F_ISR_ANERR BIT(15) 25 #define RTL8201F_ISR_DUPLEX BIT(13) 26 #define RTL8201F_ISR_LINK BIT(11) 27 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 28 RTL8201F_ISR_DUPLEX | \ 29 RTL8201F_ISR_LINK) 30 31 #define RTL821x_INER 0x12 32 #define RTL8211B_INER_INIT 0x6400 33 #define RTL8211E_INER_LINK_STATUS BIT(10) 34 #define RTL8211F_INER_LINK_STATUS BIT(4) 35 36 #define RTL821x_INSR 0x13 37 38 #define RTL821x_EXT_PAGE_SELECT 0x1e 39 40 #define RTL821x_PAGE_SELECT 0x1f 41 #define RTL821x_SET_EXT_PAGE 0x07 42 43 /* RTL8211E extension page 44/0x2c */ 44 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 45 #define RTL8211E_LEDCR1 0x1a 46 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 47 #define RTL8211E_LEDCR1_MASK BIT(4) 48 #define RTL8211E_LEDCR1_SHIFT 1 49 50 #define RTL8211E_LEDCR2 0x1c 51 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 52 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 53 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 54 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 55 #define RTL8211E_LEDCR2_SHIFT 4 56 57 /* RTL8211E extension page 164/0xa4 */ 58 #define RTL8211E_RGMII_EXT_PAGE 0xa4 59 #define RTL8211E_RGMII_DELAY 0x1c 60 #define RTL8211E_CTRL_DELAY BIT(13) 61 #define RTL8211E_TX_DELAY BIT(12) 62 #define RTL8211E_RX_DELAY BIT(11) 63 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 64 65 /* RTL8211F PHY configuration */ 66 #define RTL8211F_PHYCR_PAGE 0xa43 67 #define RTL8211F_PHYCR1 0x18 68 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 69 #define RTL8211F_ALDPS_ENABLE BIT(2) 70 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 71 72 #define RTL8211F_PHYCR2 0x19 73 #define RTL8211F_CLKOUT_EN BIT(0) 74 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 75 76 #define RTL8211F_INSR_PAGE 0xa43 77 #define RTL8211F_INSR 0x1d 78 79 /* RTL8211F LED configuration */ 80 #define RTL8211F_LEDCR_PAGE 0xd04 81 #define RTL8211F_LEDCR 0x10 82 #define RTL8211F_LEDCR_MODE BIT(15) 83 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 84 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 85 #define RTL8211F_LEDCR_LINK_100 BIT(1) 86 #define RTL8211F_LEDCR_LINK_10 BIT(0) 87 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 88 #define RTL8211F_LEDCR_SHIFT 5 89 90 /* RTL8211F RGMII configuration */ 91 #define RTL8211F_RGMII_PAGE 0xd08 92 93 #define RTL8211F_TXCR 0x11 94 #define RTL8211F_TX_DELAY BIT(8) 95 96 #define RTL8211F_RXCR 0x15 97 #define RTL8211F_RX_DELAY BIT(3) 98 99 /* RTL8211F WOL interrupt configuration */ 100 #define RTL8211F_INTBCR_PAGE 0xd40 101 #define RTL8211F_INTBCR 0x16 102 #define RTL8211F_INTBCR_INTB_PMEB BIT(5) 103 104 /* RTL8211F WOL settings */ 105 #define RTL8211F_WOL_SETTINGS_PAGE 0xd8a 106 #define RTL8211F_WOL_SETTINGS_EVENTS 16 107 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 108 #define RTL8211F_WOL_SETTINGS_STATUS 17 109 #define RTL8211F_WOL_STATUS_RESET (BIT(15) | 0x1fff) 110 111 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 112 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 113 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 114 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 115 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 116 117 #define RTL822X_VND1_SERDES_OPTION 0x697a 118 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 119 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 120 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 121 122 #define RTL822X_VND1_SERDES_CTRL3 0x7580 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 124 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 125 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 126 127 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 128 * is set, they cannot be accessed by C45-over-C22. 129 */ 130 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 131 132 #define RTL8366RB_POWER_SAVE 0x15 133 #define RTL8366RB_POWER_SAVE_ON BIT(12) 134 135 #define RTL9000A_GINMR 0x14 136 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 137 138 #define RTL_VND2_PHYSR 0xa434 139 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 140 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 141 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 142 #define RTL_VND2_PHYSR_MASTER BIT(11) 143 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 144 145 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 146 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 147 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 148 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 149 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 150 #define RTL_MDIO_PMA_SPEED 0xa616 151 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 152 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 153 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 154 155 #define RTL_GENERIC_PHYID 0x001cc800 156 #define RTL_8211FVD_PHYID 0x001cc878 157 #define RTL_8221B 0x001cc840 158 #define RTL_8221B_VB_CG 0x001cc849 159 #define RTL_8221B_VN_CG 0x001cc84a 160 #define RTL_8251B 0x001cc862 161 #define RTL_8261C 0x001cc890 162 163 /* RTL8211E and RTL8211F support up to three LEDs */ 164 #define RTL8211x_LED_COUNT 3 165 166 MODULE_DESCRIPTION("Realtek PHY driver"); 167 MODULE_AUTHOR("Johnson Leung"); 168 MODULE_LICENSE("GPL"); 169 170 struct rtl821x_priv { 171 u16 phycr1; 172 u16 phycr2; 173 bool has_phycr2; 174 struct clk *clk; 175 u32 saved_wolopts; 176 }; 177 178 static int rtl821x_read_page(struct phy_device *phydev) 179 { 180 return __phy_read(phydev, RTL821x_PAGE_SELECT); 181 } 182 183 static int rtl821x_write_page(struct phy_device *phydev, int page) 184 { 185 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 186 } 187 188 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 189 u32 regnum) 190 { 191 int oldpage, ret = 0; 192 193 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 194 if (oldpage >= 0) { 195 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 196 if (ret == 0) 197 ret = __phy_read(phydev, regnum); 198 } 199 200 return phy_restore_page(phydev, oldpage, ret); 201 } 202 203 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 204 u32 regnum, u16 mask, u16 set) 205 { 206 int oldpage, ret = 0; 207 208 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 209 if (oldpage >= 0) { 210 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 211 if (ret == 0) 212 ret = __phy_modify(phydev, regnum, mask, set); 213 } 214 215 return phy_restore_page(phydev, oldpage, ret); 216 } 217 218 static int rtl821x_probe(struct phy_device *phydev) 219 { 220 struct device *dev = &phydev->mdio.dev; 221 struct rtl821x_priv *priv; 222 u32 phy_id = phydev->drv->phy_id; 223 int ret; 224 225 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 226 if (!priv) 227 return -ENOMEM; 228 229 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 230 if (IS_ERR(priv->clk)) 231 return dev_err_probe(dev, PTR_ERR(priv->clk), 232 "failed to get phy clock\n"); 233 234 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 235 if (ret < 0) 236 return ret; 237 238 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 239 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 240 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 241 242 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 243 if (priv->has_phycr2) { 244 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 245 if (ret < 0) 246 return ret; 247 248 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 249 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 250 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 251 } 252 253 phydev->priv = priv; 254 255 return 0; 256 } 257 258 static int rtl8201_ack_interrupt(struct phy_device *phydev) 259 { 260 int err; 261 262 err = phy_read(phydev, RTL8201F_ISR); 263 264 return (err < 0) ? err : 0; 265 } 266 267 static int rtl821x_ack_interrupt(struct phy_device *phydev) 268 { 269 int err; 270 271 err = phy_read(phydev, RTL821x_INSR); 272 273 return (err < 0) ? err : 0; 274 } 275 276 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 277 { 278 int err; 279 280 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 281 282 return (err < 0) ? err : 0; 283 } 284 285 static int rtl8201_config_intr(struct phy_device *phydev) 286 { 287 u16 val; 288 int err; 289 290 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 291 err = rtl8201_ack_interrupt(phydev); 292 if (err) 293 return err; 294 295 val = BIT(13) | BIT(12) | BIT(11); 296 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 297 } else { 298 val = 0; 299 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 300 if (err) 301 return err; 302 303 err = rtl8201_ack_interrupt(phydev); 304 } 305 306 return err; 307 } 308 309 static int rtl8211b_config_intr(struct phy_device *phydev) 310 { 311 int err; 312 313 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 314 err = rtl821x_ack_interrupt(phydev); 315 if (err) 316 return err; 317 318 err = phy_write(phydev, RTL821x_INER, 319 RTL8211B_INER_INIT); 320 } else { 321 err = phy_write(phydev, RTL821x_INER, 0); 322 if (err) 323 return err; 324 325 err = rtl821x_ack_interrupt(phydev); 326 } 327 328 return err; 329 } 330 331 static int rtl8211e_config_intr(struct phy_device *phydev) 332 { 333 int err; 334 335 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 336 err = rtl821x_ack_interrupt(phydev); 337 if (err) 338 return err; 339 340 err = phy_write(phydev, RTL821x_INER, 341 RTL8211E_INER_LINK_STATUS); 342 } else { 343 err = phy_write(phydev, RTL821x_INER, 0); 344 if (err) 345 return err; 346 347 err = rtl821x_ack_interrupt(phydev); 348 } 349 350 return err; 351 } 352 353 static int rtl8211f_config_intr(struct phy_device *phydev) 354 { 355 u16 val; 356 int err; 357 358 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 359 err = rtl8211f_ack_interrupt(phydev); 360 if (err) 361 return err; 362 363 val = RTL8211F_INER_LINK_STATUS; 364 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 365 } else { 366 val = 0; 367 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 368 if (err) 369 return err; 370 371 err = rtl8211f_ack_interrupt(phydev); 372 } 373 374 return err; 375 } 376 377 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 378 { 379 int irq_status; 380 381 irq_status = phy_read(phydev, RTL8201F_ISR); 382 if (irq_status < 0) { 383 phy_error(phydev); 384 return IRQ_NONE; 385 } 386 387 if (!(irq_status & RTL8201F_ISR_MASK)) 388 return IRQ_NONE; 389 390 phy_trigger_machine(phydev); 391 392 return IRQ_HANDLED; 393 } 394 395 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 396 { 397 int irq_status, irq_enabled; 398 399 irq_status = phy_read(phydev, RTL821x_INSR); 400 if (irq_status < 0) { 401 phy_error(phydev); 402 return IRQ_NONE; 403 } 404 405 irq_enabled = phy_read(phydev, RTL821x_INER); 406 if (irq_enabled < 0) { 407 phy_error(phydev); 408 return IRQ_NONE; 409 } 410 411 if (!(irq_status & irq_enabled)) 412 return IRQ_NONE; 413 414 phy_trigger_machine(phydev); 415 416 return IRQ_HANDLED; 417 } 418 419 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 420 { 421 int irq_status; 422 423 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 424 if (irq_status < 0) { 425 phy_error(phydev); 426 return IRQ_NONE; 427 } 428 429 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 430 return IRQ_NONE; 431 432 phy_trigger_machine(phydev); 433 434 return IRQ_HANDLED; 435 } 436 437 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 438 { 439 int wol_events; 440 441 wol->supported = WAKE_MAGIC; 442 443 wol_events = phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 444 if (wol_events < 0) 445 return; 446 447 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 448 wol->wolopts = WAKE_MAGIC; 449 } 450 451 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 452 { 453 const u8 *mac_addr = dev->attached_dev->dev_addr; 454 int oldpage; 455 456 oldpage = phy_save_page(dev); 457 if (oldpage < 0) 458 goto err; 459 460 if (wol->wolopts & WAKE_MAGIC) { 461 /* Store the device address for the magic packet */ 462 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 463 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 464 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 465 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 466 467 /* Enable magic packet matching and reset WOL status */ 468 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 469 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 470 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 471 472 /* Enable the WOL interrupt */ 473 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 474 __phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 475 } else { 476 /* Disable the WOL interrupt */ 477 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 478 __phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 479 480 /* Disable magic packet matching and reset WOL status */ 481 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 482 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 483 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 484 } 485 486 err: 487 return phy_restore_page(dev, oldpage, 0); 488 } 489 490 static int rtl8211_config_aneg(struct phy_device *phydev) 491 { 492 int ret; 493 494 ret = genphy_config_aneg(phydev); 495 if (ret < 0) 496 return ret; 497 498 /* Quirk was copied from vendor driver. Unfortunately it includes no 499 * description of the magic numbers. 500 */ 501 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 502 phy_write(phydev, 0x17, 0x2138); 503 phy_write(phydev, 0x0e, 0x0260); 504 } else { 505 phy_write(phydev, 0x17, 0x2108); 506 phy_write(phydev, 0x0e, 0x0000); 507 } 508 509 return 0; 510 } 511 512 static int rtl8211c_config_init(struct phy_device *phydev) 513 { 514 /* RTL8211C has an issue when operating in Gigabit slave mode */ 515 return phy_set_bits(phydev, MII_CTRL1000, 516 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 517 } 518 519 static int rtl8211f_config_init(struct phy_device *phydev) 520 { 521 struct rtl821x_priv *priv = phydev->priv; 522 struct device *dev = &phydev->mdio.dev; 523 u16 val_txdly, val_rxdly; 524 int ret; 525 526 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 527 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 528 priv->phycr1); 529 if (ret < 0) { 530 dev_err(dev, "aldps mode configuration failed: %pe\n", 531 ERR_PTR(ret)); 532 return ret; 533 } 534 535 switch (phydev->interface) { 536 case PHY_INTERFACE_MODE_RGMII: 537 val_txdly = 0; 538 val_rxdly = 0; 539 break; 540 541 case PHY_INTERFACE_MODE_RGMII_RXID: 542 val_txdly = 0; 543 val_rxdly = RTL8211F_RX_DELAY; 544 break; 545 546 case PHY_INTERFACE_MODE_RGMII_TXID: 547 val_txdly = RTL8211F_TX_DELAY; 548 val_rxdly = 0; 549 break; 550 551 case PHY_INTERFACE_MODE_RGMII_ID: 552 val_txdly = RTL8211F_TX_DELAY; 553 val_rxdly = RTL8211F_RX_DELAY; 554 break; 555 556 default: /* the rest of the modes imply leaving delay as is. */ 557 return 0; 558 } 559 560 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 561 RTL8211F_TXCR, RTL8211F_TX_DELAY, 562 val_txdly); 563 if (ret < 0) { 564 dev_err(dev, "Failed to update the TX delay register\n"); 565 return ret; 566 } else if (ret) { 567 dev_dbg(dev, 568 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 569 str_enable_disable(val_txdly)); 570 } else { 571 dev_dbg(dev, 572 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 573 str_enabled_disabled(val_txdly)); 574 } 575 576 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 577 RTL8211F_RXCR, RTL8211F_RX_DELAY, 578 val_rxdly); 579 if (ret < 0) { 580 dev_err(dev, "Failed to update the RX delay register\n"); 581 return ret; 582 } else if (ret) { 583 dev_dbg(dev, 584 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 585 str_enable_disable(val_rxdly)); 586 } else { 587 dev_dbg(dev, 588 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 589 str_enabled_disabled(val_rxdly)); 590 } 591 592 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 593 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 594 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 595 if (ret) 596 return ret; 597 598 if (priv->has_phycr2) { 599 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 600 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 601 priv->phycr2); 602 if (ret < 0) { 603 dev_err(dev, "clkout configuration failed: %pe\n", 604 ERR_PTR(ret)); 605 return ret; 606 } 607 608 return genphy_soft_reset(phydev); 609 } 610 611 return 0; 612 } 613 614 static int rtl821x_suspend(struct phy_device *phydev) 615 { 616 struct rtl821x_priv *priv = phydev->priv; 617 int ret = 0; 618 619 if (!phydev->wol_enabled) { 620 ret = genphy_suspend(phydev); 621 622 if (ret) 623 return ret; 624 625 clk_disable_unprepare(priv->clk); 626 } 627 628 return ret; 629 } 630 631 static int rtl821x_resume(struct phy_device *phydev) 632 { 633 struct rtl821x_priv *priv = phydev->priv; 634 int ret; 635 636 if (!phydev->wol_enabled) 637 clk_prepare_enable(priv->clk); 638 639 ret = genphy_resume(phydev); 640 if (ret < 0) 641 return ret; 642 643 msleep(20); 644 645 return 0; 646 } 647 648 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 649 unsigned long rules) 650 { 651 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 652 BIT(TRIGGER_NETDEV_LINK_100) | 653 BIT(TRIGGER_NETDEV_LINK_1000) | 654 BIT(TRIGGER_NETDEV_RX) | 655 BIT(TRIGGER_NETDEV_TX); 656 657 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 658 * - Link: Configurable subset of 10/100/1000 link rates 659 * - Active: Blink on activity, RX or TX is not differentiated 660 * The Active option has two modes, A and B: 661 * - A: Link and Active indication at configurable, but matching, 662 * subset of 10/100/1000 link rates 663 * - B: Link indication at configurable subset of 10/100/1000 link 664 * rates and Active indication always at all three 10+100+1000 665 * link rates. 666 * This code currently uses mode B only. 667 * 668 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 669 */ 670 671 if (index >= RTL8211x_LED_COUNT) 672 return -EINVAL; 673 674 /* Filter out any other unsupported triggers. */ 675 if (rules & ~mask) 676 return -EOPNOTSUPP; 677 678 /* RX and TX are not differentiated, either both are set or not set. */ 679 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 680 return -EOPNOTSUPP; 681 682 return 0; 683 } 684 685 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 686 unsigned long *rules) 687 { 688 int val; 689 690 if (index >= RTL8211x_LED_COUNT) 691 return -EINVAL; 692 693 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 694 if (val < 0) 695 return val; 696 697 val >>= RTL8211F_LEDCR_SHIFT * index; 698 val &= RTL8211F_LEDCR_MASK; 699 700 if (val & RTL8211F_LEDCR_LINK_10) 701 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 702 703 if (val & RTL8211F_LEDCR_LINK_100) 704 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 705 706 if (val & RTL8211F_LEDCR_LINK_1000) 707 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 708 709 if (val & RTL8211F_LEDCR_ACT_TXRX) { 710 __set_bit(TRIGGER_NETDEV_RX, rules); 711 __set_bit(TRIGGER_NETDEV_TX, rules); 712 } 713 714 return 0; 715 } 716 717 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 718 unsigned long rules) 719 { 720 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 721 u16 reg = 0; 722 723 if (index >= RTL8211x_LED_COUNT) 724 return -EINVAL; 725 726 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 727 reg |= RTL8211F_LEDCR_LINK_10; 728 729 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 730 reg |= RTL8211F_LEDCR_LINK_100; 731 732 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 733 reg |= RTL8211F_LEDCR_LINK_1000; 734 735 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 736 test_bit(TRIGGER_NETDEV_TX, &rules)) { 737 reg |= RTL8211F_LEDCR_ACT_TXRX; 738 } 739 740 reg <<= RTL8211F_LEDCR_SHIFT * index; 741 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 742 743 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 744 } 745 746 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 747 unsigned long *rules) 748 { 749 int ret; 750 u16 cr1, cr2; 751 752 if (index >= RTL8211x_LED_COUNT) 753 return -EINVAL; 754 755 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 756 RTL8211E_LEDCR1); 757 if (ret < 0) 758 return ret; 759 760 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 761 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 762 __set_bit(TRIGGER_NETDEV_RX, rules); 763 __set_bit(TRIGGER_NETDEV_TX, rules); 764 } 765 766 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 767 RTL8211E_LEDCR2); 768 if (ret < 0) 769 return ret; 770 771 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 772 if (cr2 & RTL8211E_LEDCR2_LINK_10) 773 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 774 775 if (cr2 & RTL8211E_LEDCR2_LINK_100) 776 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 777 778 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 779 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 780 781 return ret; 782 } 783 784 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 785 unsigned long rules) 786 { 787 const u16 cr1mask = 788 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 789 const u16 cr2mask = 790 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 791 u16 cr1 = 0, cr2 = 0; 792 int ret; 793 794 if (index >= RTL8211x_LED_COUNT) 795 return -EINVAL; 796 797 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 798 test_bit(TRIGGER_NETDEV_TX, &rules)) { 799 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 800 } 801 802 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 803 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 804 RTL8211E_LEDCR1, cr1mask, cr1); 805 if (ret < 0) 806 return ret; 807 808 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 809 cr2 |= RTL8211E_LEDCR2_LINK_10; 810 811 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 812 cr2 |= RTL8211E_LEDCR2_LINK_100; 813 814 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 815 cr2 |= RTL8211E_LEDCR2_LINK_1000; 816 817 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 818 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 819 RTL8211E_LEDCR2, cr2mask, cr2); 820 821 return ret; 822 } 823 824 static int rtl8211e_config_init(struct phy_device *phydev) 825 { 826 u16 val; 827 828 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 829 switch (phydev->interface) { 830 case PHY_INTERFACE_MODE_RGMII: 831 val = RTL8211E_CTRL_DELAY | 0; 832 break; 833 case PHY_INTERFACE_MODE_RGMII_ID: 834 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 835 break; 836 case PHY_INTERFACE_MODE_RGMII_RXID: 837 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 838 break; 839 case PHY_INTERFACE_MODE_RGMII_TXID: 840 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 841 break; 842 default: /* the rest of the modes imply leaving delays as is. */ 843 return 0; 844 } 845 846 /* According to a sample driver there is a 0x1c config register on the 847 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 848 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 849 * The configuration register definition: 850 * 14 = reserved 851 * 13 = Force Tx RX Delay controlled by bit12 bit11, 852 * 12 = RX Delay, 11 = TX Delay 853 * 10:0 = Test && debug settings reserved by realtek 854 */ 855 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 856 RTL8211E_RGMII_DELAY, 857 RTL8211E_DELAY_MASK, val); 858 } 859 860 static int rtl8211b_suspend(struct phy_device *phydev) 861 { 862 phy_write(phydev, MII_MMD_DATA, BIT(9)); 863 864 return genphy_suspend(phydev); 865 } 866 867 static int rtl8211b_resume(struct phy_device *phydev) 868 { 869 phy_write(phydev, MII_MMD_DATA, 0); 870 871 return genphy_resume(phydev); 872 } 873 874 static int rtl8366rb_config_init(struct phy_device *phydev) 875 { 876 int ret; 877 878 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 879 RTL8366RB_POWER_SAVE_ON); 880 if (ret) { 881 dev_err(&phydev->mdio.dev, 882 "error enabling power management\n"); 883 } 884 885 return ret; 886 } 887 888 /* get actual speed to cover the downshift case */ 889 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 890 { 891 /* bit 3 892 * 0: Half Duplex 893 * 1: Full Duplex 894 */ 895 if (val & RTL_VND2_PHYSR_DUPLEX) 896 phydev->duplex = DUPLEX_FULL; 897 else 898 phydev->duplex = DUPLEX_HALF; 899 900 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 901 case 0x0000: 902 phydev->speed = SPEED_10; 903 break; 904 case 0x0010: 905 phydev->speed = SPEED_100; 906 break; 907 case 0x0020: 908 phydev->speed = SPEED_1000; 909 break; 910 case 0x0200: 911 phydev->speed = SPEED_10000; 912 break; 913 case 0x0210: 914 phydev->speed = SPEED_2500; 915 break; 916 case 0x0220: 917 phydev->speed = SPEED_5000; 918 break; 919 default: 920 break; 921 } 922 923 /* bit 11 924 * 0: Slave Mode 925 * 1: Master Mode 926 */ 927 if (phydev->speed >= 1000) { 928 if (val & RTL_VND2_PHYSR_MASTER) 929 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 930 else 931 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 932 } else { 933 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 934 } 935 } 936 937 static int rtlgen_read_status(struct phy_device *phydev) 938 { 939 int ret, val; 940 941 ret = genphy_read_status(phydev); 942 if (ret < 0) 943 return ret; 944 945 if (!phydev->link) 946 return 0; 947 948 val = phy_read_paged(phydev, 0xa43, 0x12); 949 if (val < 0) 950 return val; 951 952 rtlgen_decode_physr(phydev, val); 953 954 return 0; 955 } 956 957 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 958 { 959 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 960 } 961 962 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 963 { 964 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 965 val); 966 } 967 968 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 969 { 970 int ret; 971 972 if (devnum == MDIO_MMD_VEND2) 973 ret = rtlgen_read_vend2(phydev, regnum); 974 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 975 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 976 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 977 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 978 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 979 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 980 else 981 ret = -EOPNOTSUPP; 982 983 return ret; 984 } 985 986 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 987 u16 val) 988 { 989 int ret; 990 991 if (devnum == MDIO_MMD_VEND2) 992 ret = rtlgen_write_vend2(phydev, regnum, val); 993 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 994 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 995 else 996 ret = -EOPNOTSUPP; 997 998 return ret; 999 } 1000 1001 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1002 { 1003 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1004 1005 if (ret != -EOPNOTSUPP) 1006 return ret; 1007 1008 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1009 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1010 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1011 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1012 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1013 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1014 1015 return ret; 1016 } 1017 1018 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1019 u16 val) 1020 { 1021 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1022 1023 if (ret != -EOPNOTSUPP) 1024 return ret; 1025 1026 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1027 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1028 1029 return ret; 1030 } 1031 1032 static int rtl822x_probe(struct phy_device *phydev) 1033 { 1034 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1035 phydev->phy_id != RTL_GENERIC_PHYID) 1036 return rtl822x_hwmon_init(phydev); 1037 1038 return 0; 1039 } 1040 1041 static int rtl822xb_config_init(struct phy_device *phydev) 1042 { 1043 bool has_2500, has_sgmii; 1044 u16 mode; 1045 int ret; 1046 1047 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1048 phydev->host_interfaces) || 1049 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1050 1051 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1052 phydev->host_interfaces) || 1053 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1054 1055 /* fill in possible interfaces */ 1056 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1057 has_2500); 1058 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1059 has_sgmii); 1060 1061 if (!has_2500 && !has_sgmii) 1062 return 0; 1063 1064 /* determine SerDes option mode */ 1065 if (has_2500 && !has_sgmii) { 1066 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1067 phydev->rate_matching = RATE_MATCH_PAUSE; 1068 } else { 1069 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1070 phydev->rate_matching = RATE_MATCH_NONE; 1071 } 1072 1073 /* the following sequence with magic numbers sets up the SerDes 1074 * option mode 1075 */ 1076 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1077 if (ret < 0) 1078 return ret; 1079 1080 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1081 RTL822X_VND1_SERDES_OPTION, 1082 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1083 mode); 1084 if (ret < 0) 1085 return ret; 1086 1087 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1088 if (ret < 0) 1089 return ret; 1090 1091 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1092 if (ret < 0) 1093 return ret; 1094 1095 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1096 } 1097 1098 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1099 phy_interface_t iface) 1100 { 1101 int val; 1102 1103 /* Only rate matching at 2500base-x */ 1104 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1105 return RATE_MATCH_NONE; 1106 1107 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1108 if (val < 0) 1109 return val; 1110 1111 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1112 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1113 return RATE_MATCH_PAUSE; 1114 1115 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1116 return RATE_MATCH_NONE; 1117 } 1118 1119 static int rtl822x_get_features(struct phy_device *phydev) 1120 { 1121 int val; 1122 1123 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1124 if (val < 0) 1125 return val; 1126 1127 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1128 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1129 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1130 phydev->supported, val & MDIO_PMA_SPEED_5G); 1131 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1132 phydev->supported, val & MDIO_SPEED_10G); 1133 1134 return genphy_read_abilities(phydev); 1135 } 1136 1137 static int rtl822x_config_aneg(struct phy_device *phydev) 1138 { 1139 int ret = 0; 1140 1141 if (phydev->autoneg == AUTONEG_ENABLE) { 1142 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1143 1144 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1145 RTL_MDIO_AN_10GBT_CTRL, 1146 MDIO_AN_10GBT_CTRL_ADV2_5G | 1147 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1148 if (ret < 0) 1149 return ret; 1150 } 1151 1152 return __genphy_config_aneg(phydev, ret); 1153 } 1154 1155 static void rtl822xb_update_interface(struct phy_device *phydev) 1156 { 1157 int val; 1158 1159 if (!phydev->link) 1160 return; 1161 1162 /* Change interface according to serdes mode */ 1163 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1164 if (val < 0) 1165 return; 1166 1167 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1168 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1169 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1170 break; 1171 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1172 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1173 break; 1174 } 1175 } 1176 1177 static int rtl822x_read_status(struct phy_device *phydev) 1178 { 1179 int lpadv, ret; 1180 1181 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1182 1183 ret = rtlgen_read_status(phydev); 1184 if (ret < 0) 1185 return ret; 1186 1187 if (phydev->autoneg == AUTONEG_DISABLE || 1188 !phydev->autoneg_complete) 1189 return 0; 1190 1191 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1192 if (lpadv < 0) 1193 return lpadv; 1194 1195 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1196 1197 return 0; 1198 } 1199 1200 static int rtl822xb_read_status(struct phy_device *phydev) 1201 { 1202 int ret; 1203 1204 ret = rtl822x_read_status(phydev); 1205 if (ret < 0) 1206 return ret; 1207 1208 rtl822xb_update_interface(phydev); 1209 1210 return 0; 1211 } 1212 1213 static int rtl822x_c45_get_features(struct phy_device *phydev) 1214 { 1215 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1216 phydev->supported); 1217 1218 return genphy_c45_pma_read_abilities(phydev); 1219 } 1220 1221 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1222 { 1223 bool changed = false; 1224 int ret, val; 1225 1226 if (phydev->autoneg == AUTONEG_DISABLE) 1227 return genphy_c45_pma_setup_forced(phydev); 1228 1229 ret = genphy_c45_an_config_aneg(phydev); 1230 if (ret < 0) 1231 return ret; 1232 if (ret > 0) 1233 changed = true; 1234 1235 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1236 1237 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1239 RTL822X_VND2_C22_REG(MII_CTRL1000), 1240 ADVERTISE_1000FULL, val); 1241 if (ret < 0) 1242 return ret; 1243 if (ret > 0) 1244 changed = true; 1245 1246 return genphy_c45_check_and_restart_aneg(phydev, changed); 1247 } 1248 1249 static int rtl822x_c45_read_status(struct phy_device *phydev) 1250 { 1251 int ret, val; 1252 1253 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1254 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1255 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1256 RTL822X_VND2_C22_REG(MII_STAT1000)); 1257 if (val < 0) 1258 return val; 1259 } else { 1260 val = 0; 1261 } 1262 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1263 1264 ret = genphy_c45_read_status(phydev); 1265 if (ret < 0) 1266 return ret; 1267 1268 if (!phydev->link) { 1269 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1270 return 0; 1271 } 1272 1273 /* Read actual speed from vendor register. */ 1274 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1275 if (val < 0) 1276 return val; 1277 1278 rtlgen_decode_physr(phydev, val); 1279 1280 return 0; 1281 } 1282 1283 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1284 { 1285 int ret; 1286 1287 ret = rtl822x_c45_read_status(phydev); 1288 if (ret < 0) 1289 return ret; 1290 1291 rtl822xb_update_interface(phydev); 1292 1293 return 0; 1294 } 1295 1296 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1297 { 1298 int val; 1299 1300 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1301 val = phy_read(phydev, 0x13); 1302 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1303 1304 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1305 } 1306 1307 /* On internal PHY's MMD reads over C22 always return 0. 1308 * Check a MMD register which is known to be non-zero. 1309 */ 1310 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1311 { 1312 int val; 1313 1314 phy_lock_mdio_bus(phydev); 1315 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1316 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1317 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1318 val = __phy_read(phydev, MII_MMD_DATA); 1319 phy_unlock_mdio_bus(phydev); 1320 1321 return val > 0; 1322 } 1323 1324 static int rtlgen_match_phy_device(struct phy_device *phydev, 1325 const struct phy_driver *phydrv) 1326 { 1327 return phydev->phy_id == RTL_GENERIC_PHYID && 1328 !rtlgen_supports_2_5gbps(phydev); 1329 } 1330 1331 static int rtl8226_match_phy_device(struct phy_device *phydev, 1332 const struct phy_driver *phydrv) 1333 { 1334 return phydev->phy_id == RTL_GENERIC_PHYID && 1335 rtlgen_supports_2_5gbps(phydev) && 1336 rtlgen_supports_mmd(phydev); 1337 } 1338 1339 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1340 bool is_c45) 1341 { 1342 if (phydev->is_c45) 1343 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1344 else 1345 return !is_c45 && (id == phydev->phy_id); 1346 } 1347 1348 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1349 const struct phy_driver *phydrv) 1350 { 1351 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1352 } 1353 1354 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1355 const struct phy_driver *phydrv) 1356 { 1357 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1358 } 1359 1360 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1361 const struct phy_driver *phydrv) 1362 { 1363 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1364 } 1365 1366 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, 1367 const struct phy_driver *phydrv) 1368 { 1369 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1370 } 1371 1372 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, 1373 const struct phy_driver *phydrv) 1374 { 1375 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1376 } 1377 1378 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1379 const struct phy_driver *phydrv) 1380 { 1381 if (phydev->is_c45) 1382 return false; 1383 1384 switch (phydev->phy_id) { 1385 case RTL_GENERIC_PHYID: 1386 case RTL_8221B: 1387 case RTL_8251B: 1388 case RTL_8261C: 1389 case 0x001cc841: 1390 break; 1391 default: 1392 return false; 1393 } 1394 1395 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1396 } 1397 1398 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1399 const struct phy_driver *phydrv) 1400 { 1401 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1402 } 1403 1404 static int rtlgen_resume(struct phy_device *phydev) 1405 { 1406 int ret = genphy_resume(phydev); 1407 1408 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1409 msleep(20); 1410 1411 return ret; 1412 } 1413 1414 static int rtlgen_c45_resume(struct phy_device *phydev) 1415 { 1416 int ret = genphy_c45_pma_resume(phydev); 1417 1418 msleep(20); 1419 1420 return ret; 1421 } 1422 1423 static int rtl9000a_config_init(struct phy_device *phydev) 1424 { 1425 phydev->autoneg = AUTONEG_DISABLE; 1426 phydev->speed = SPEED_100; 1427 phydev->duplex = DUPLEX_FULL; 1428 1429 return 0; 1430 } 1431 1432 static int rtl9000a_config_aneg(struct phy_device *phydev) 1433 { 1434 int ret; 1435 u16 ctl = 0; 1436 1437 switch (phydev->master_slave_set) { 1438 case MASTER_SLAVE_CFG_MASTER_FORCE: 1439 ctl |= CTL1000_AS_MASTER; 1440 break; 1441 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1442 break; 1443 case MASTER_SLAVE_CFG_UNKNOWN: 1444 case MASTER_SLAVE_CFG_UNSUPPORTED: 1445 return 0; 1446 default: 1447 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1448 return -EOPNOTSUPP; 1449 } 1450 1451 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1452 if (ret == 1) 1453 ret = genphy_soft_reset(phydev); 1454 1455 return ret; 1456 } 1457 1458 static int rtl9000a_read_status(struct phy_device *phydev) 1459 { 1460 int ret; 1461 1462 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1463 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1464 1465 ret = genphy_update_link(phydev); 1466 if (ret) 1467 return ret; 1468 1469 ret = phy_read(phydev, MII_CTRL1000); 1470 if (ret < 0) 1471 return ret; 1472 if (ret & CTL1000_AS_MASTER) 1473 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1474 else 1475 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1476 1477 ret = phy_read(phydev, MII_STAT1000); 1478 if (ret < 0) 1479 return ret; 1480 if (ret & LPA_1000MSRES) 1481 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1482 else 1483 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1484 1485 return 0; 1486 } 1487 1488 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1489 { 1490 int err; 1491 1492 err = phy_read(phydev, RTL8211F_INSR); 1493 1494 return (err < 0) ? err : 0; 1495 } 1496 1497 static int rtl9000a_config_intr(struct phy_device *phydev) 1498 { 1499 u16 val; 1500 int err; 1501 1502 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1503 err = rtl9000a_ack_interrupt(phydev); 1504 if (err) 1505 return err; 1506 1507 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1508 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1509 } else { 1510 val = ~0; 1511 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1512 if (err) 1513 return err; 1514 1515 err = rtl9000a_ack_interrupt(phydev); 1516 } 1517 1518 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1519 } 1520 1521 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1522 { 1523 int irq_status; 1524 1525 irq_status = phy_read(phydev, RTL8211F_INSR); 1526 if (irq_status < 0) { 1527 phy_error(phydev); 1528 return IRQ_NONE; 1529 } 1530 1531 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1532 return IRQ_NONE; 1533 1534 phy_trigger_machine(phydev); 1535 1536 return IRQ_HANDLED; 1537 } 1538 1539 static struct phy_driver realtek_drvs[] = { 1540 { 1541 PHY_ID_MATCH_EXACT(0x00008201), 1542 .name = "RTL8201CP Ethernet", 1543 .read_page = rtl821x_read_page, 1544 .write_page = rtl821x_write_page, 1545 }, { 1546 PHY_ID_MATCH_EXACT(0x001cc816), 1547 .name = "RTL8201F Fast Ethernet", 1548 .config_intr = &rtl8201_config_intr, 1549 .handle_interrupt = rtl8201_handle_interrupt, 1550 .suspend = genphy_suspend, 1551 .resume = genphy_resume, 1552 .read_page = rtl821x_read_page, 1553 .write_page = rtl821x_write_page, 1554 }, { 1555 PHY_ID_MATCH_MODEL(0x001cc880), 1556 .name = "RTL8208 Fast Ethernet", 1557 .read_mmd = genphy_read_mmd_unsupported, 1558 .write_mmd = genphy_write_mmd_unsupported, 1559 .suspend = genphy_suspend, 1560 .resume = genphy_resume, 1561 .read_page = rtl821x_read_page, 1562 .write_page = rtl821x_write_page, 1563 }, { 1564 PHY_ID_MATCH_EXACT(0x001cc910), 1565 .name = "RTL8211 Gigabit Ethernet", 1566 .config_aneg = rtl8211_config_aneg, 1567 .read_mmd = &genphy_read_mmd_unsupported, 1568 .write_mmd = &genphy_write_mmd_unsupported, 1569 .read_page = rtl821x_read_page, 1570 .write_page = rtl821x_write_page, 1571 }, { 1572 PHY_ID_MATCH_EXACT(0x001cc912), 1573 .name = "RTL8211B Gigabit Ethernet", 1574 .config_intr = &rtl8211b_config_intr, 1575 .handle_interrupt = rtl821x_handle_interrupt, 1576 .read_mmd = &genphy_read_mmd_unsupported, 1577 .write_mmd = &genphy_write_mmd_unsupported, 1578 .suspend = rtl8211b_suspend, 1579 .resume = rtl8211b_resume, 1580 .read_page = rtl821x_read_page, 1581 .write_page = rtl821x_write_page, 1582 }, { 1583 PHY_ID_MATCH_EXACT(0x001cc913), 1584 .name = "RTL8211C Gigabit Ethernet", 1585 .config_init = rtl8211c_config_init, 1586 .read_mmd = &genphy_read_mmd_unsupported, 1587 .write_mmd = &genphy_write_mmd_unsupported, 1588 .read_page = rtl821x_read_page, 1589 .write_page = rtl821x_write_page, 1590 }, { 1591 PHY_ID_MATCH_EXACT(0x001cc914), 1592 .name = "RTL8211DN Gigabit Ethernet", 1593 .config_intr = rtl8211e_config_intr, 1594 .handle_interrupt = rtl821x_handle_interrupt, 1595 .suspend = genphy_suspend, 1596 .resume = genphy_resume, 1597 .read_page = rtl821x_read_page, 1598 .write_page = rtl821x_write_page, 1599 }, { 1600 PHY_ID_MATCH_EXACT(0x001cc915), 1601 .name = "RTL8211E Gigabit Ethernet", 1602 .config_init = &rtl8211e_config_init, 1603 .config_intr = &rtl8211e_config_intr, 1604 .handle_interrupt = rtl821x_handle_interrupt, 1605 .suspend = genphy_suspend, 1606 .resume = genphy_resume, 1607 .read_page = rtl821x_read_page, 1608 .write_page = rtl821x_write_page, 1609 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1610 .led_hw_control_get = rtl8211e_led_hw_control_get, 1611 .led_hw_control_set = rtl8211e_led_hw_control_set, 1612 }, { 1613 PHY_ID_MATCH_EXACT(0x001cc916), 1614 .name = "RTL8211F Gigabit Ethernet", 1615 .probe = rtl821x_probe, 1616 .config_init = &rtl8211f_config_init, 1617 .read_status = rtlgen_read_status, 1618 .config_intr = &rtl8211f_config_intr, 1619 .handle_interrupt = rtl8211f_handle_interrupt, 1620 .set_wol = rtl8211f_set_wol, 1621 .get_wol = rtl8211f_get_wol, 1622 .suspend = rtl821x_suspend, 1623 .resume = rtl821x_resume, 1624 .read_page = rtl821x_read_page, 1625 .write_page = rtl821x_write_page, 1626 .flags = PHY_ALWAYS_CALL_SUSPEND, 1627 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1628 .led_hw_control_get = rtl8211f_led_hw_control_get, 1629 .led_hw_control_set = rtl8211f_led_hw_control_set, 1630 }, { 1631 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1632 .name = "RTL8211F-VD Gigabit Ethernet", 1633 .probe = rtl821x_probe, 1634 .config_init = &rtl8211f_config_init, 1635 .read_status = rtlgen_read_status, 1636 .config_intr = &rtl8211f_config_intr, 1637 .handle_interrupt = rtl8211f_handle_interrupt, 1638 .suspend = rtl821x_suspend, 1639 .resume = rtl821x_resume, 1640 .read_page = rtl821x_read_page, 1641 .write_page = rtl821x_write_page, 1642 .flags = PHY_ALWAYS_CALL_SUSPEND, 1643 }, { 1644 .name = "Generic FE-GE Realtek PHY", 1645 .match_phy_device = rtlgen_match_phy_device, 1646 .read_status = rtlgen_read_status, 1647 .suspend = genphy_suspend, 1648 .resume = rtlgen_resume, 1649 .read_page = rtl821x_read_page, 1650 .write_page = rtl821x_write_page, 1651 .read_mmd = rtlgen_read_mmd, 1652 .write_mmd = rtlgen_write_mmd, 1653 }, { 1654 .name = "RTL8226 2.5Gbps PHY", 1655 .match_phy_device = rtl8226_match_phy_device, 1656 .get_features = rtl822x_get_features, 1657 .config_aneg = rtl822x_config_aneg, 1658 .read_status = rtl822x_read_status, 1659 .suspend = genphy_suspend, 1660 .resume = rtlgen_resume, 1661 .read_page = rtl821x_read_page, 1662 .write_page = rtl821x_write_page, 1663 }, { 1664 .match_phy_device = rtl8221b_match_phy_device, 1665 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1666 .get_features = rtl822x_get_features, 1667 .config_aneg = rtl822x_config_aneg, 1668 .config_init = rtl822xb_config_init, 1669 .get_rate_matching = rtl822xb_get_rate_matching, 1670 .read_status = rtl822xb_read_status, 1671 .suspend = genphy_suspend, 1672 .resume = rtlgen_resume, 1673 .read_page = rtl821x_read_page, 1674 .write_page = rtl821x_write_page, 1675 }, { 1676 PHY_ID_MATCH_EXACT(0x001cc838), 1677 .name = "RTL8226-CG 2.5Gbps PHY", 1678 .get_features = rtl822x_get_features, 1679 .config_aneg = rtl822x_config_aneg, 1680 .read_status = rtl822x_read_status, 1681 .suspend = genphy_suspend, 1682 .resume = rtlgen_resume, 1683 .read_page = rtl821x_read_page, 1684 .write_page = rtl821x_write_page, 1685 }, { 1686 PHY_ID_MATCH_EXACT(0x001cc848), 1687 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1688 .get_features = rtl822x_get_features, 1689 .config_aneg = rtl822x_config_aneg, 1690 .config_init = rtl822xb_config_init, 1691 .get_rate_matching = rtl822xb_get_rate_matching, 1692 .read_status = rtl822xb_read_status, 1693 .suspend = genphy_suspend, 1694 .resume = rtlgen_resume, 1695 .read_page = rtl821x_read_page, 1696 .write_page = rtl821x_write_page, 1697 }, { 1698 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1699 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1700 .probe = rtl822x_probe, 1701 .get_features = rtl822x_get_features, 1702 .config_aneg = rtl822x_config_aneg, 1703 .config_init = rtl822xb_config_init, 1704 .get_rate_matching = rtl822xb_get_rate_matching, 1705 .read_status = rtl822xb_read_status, 1706 .suspend = genphy_suspend, 1707 .resume = rtlgen_resume, 1708 .read_page = rtl821x_read_page, 1709 .write_page = rtl821x_write_page, 1710 }, { 1711 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1712 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1713 .probe = rtl822x_probe, 1714 .config_init = rtl822xb_config_init, 1715 .get_rate_matching = rtl822xb_get_rate_matching, 1716 .get_features = rtl822x_c45_get_features, 1717 .config_aneg = rtl822x_c45_config_aneg, 1718 .read_status = rtl822xb_c45_read_status, 1719 .suspend = genphy_c45_pma_suspend, 1720 .resume = rtlgen_c45_resume, 1721 }, { 1722 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1723 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1724 .probe = rtl822x_probe, 1725 .get_features = rtl822x_get_features, 1726 .config_aneg = rtl822x_config_aneg, 1727 .config_init = rtl822xb_config_init, 1728 .get_rate_matching = rtl822xb_get_rate_matching, 1729 .read_status = rtl822xb_read_status, 1730 .suspend = genphy_suspend, 1731 .resume = rtlgen_resume, 1732 .read_page = rtl821x_read_page, 1733 .write_page = rtl821x_write_page, 1734 }, { 1735 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1736 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1737 .probe = rtl822x_probe, 1738 .config_init = rtl822xb_config_init, 1739 .get_rate_matching = rtl822xb_get_rate_matching, 1740 .get_features = rtl822x_c45_get_features, 1741 .config_aneg = rtl822x_c45_config_aneg, 1742 .read_status = rtl822xb_c45_read_status, 1743 .suspend = genphy_c45_pma_suspend, 1744 .resume = rtlgen_c45_resume, 1745 }, { 1746 .match_phy_device = rtl8251b_c45_match_phy_device, 1747 .name = "RTL8251B 5Gbps PHY", 1748 .probe = rtl822x_probe, 1749 .get_features = rtl822x_get_features, 1750 .config_aneg = rtl822x_config_aneg, 1751 .read_status = rtl822x_read_status, 1752 .suspend = genphy_suspend, 1753 .resume = rtlgen_resume, 1754 .read_page = rtl821x_read_page, 1755 .write_page = rtl821x_write_page, 1756 }, { 1757 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1758 .name = "Realtek Internal NBASE-T PHY", 1759 .flags = PHY_IS_INTERNAL, 1760 .probe = rtl822x_probe, 1761 .get_features = rtl822x_get_features, 1762 .config_aneg = rtl822x_config_aneg, 1763 .read_status = rtl822x_read_status, 1764 .suspend = genphy_suspend, 1765 .resume = rtlgen_resume, 1766 .read_page = rtl821x_read_page, 1767 .write_page = rtl821x_write_page, 1768 .read_mmd = rtl822x_read_mmd, 1769 .write_mmd = rtl822x_write_mmd, 1770 }, { 1771 PHY_ID_MATCH_EXACT(0x001ccad0), 1772 .name = "RTL8224 2.5Gbps PHY", 1773 .get_features = rtl822x_c45_get_features, 1774 .config_aneg = rtl822x_c45_config_aneg, 1775 .read_status = rtl822x_c45_read_status, 1776 .suspend = genphy_c45_pma_suspend, 1777 .resume = rtlgen_c45_resume, 1778 }, { 1779 PHY_ID_MATCH_EXACT(0x001cc961), 1780 .name = "RTL8366RB Gigabit Ethernet", 1781 .config_init = &rtl8366rb_config_init, 1782 /* These interrupts are handled by the irq controller 1783 * embedded inside the RTL8366RB, they get unmasked when the 1784 * irq is requested and ACKed by reading the status register, 1785 * which is done by the irqchip code. 1786 */ 1787 .config_intr = genphy_no_config_intr, 1788 .handle_interrupt = genphy_handle_interrupt_no_ack, 1789 .suspend = genphy_suspend, 1790 .resume = genphy_resume, 1791 }, { 1792 PHY_ID_MATCH_EXACT(0x001ccb00), 1793 .name = "RTL9000AA_RTL9000AN Ethernet", 1794 .features = PHY_BASIC_T1_FEATURES, 1795 .config_init = rtl9000a_config_init, 1796 .config_aneg = rtl9000a_config_aneg, 1797 .read_status = rtl9000a_read_status, 1798 .config_intr = rtl9000a_config_intr, 1799 .handle_interrupt = rtl9000a_handle_interrupt, 1800 .suspend = genphy_suspend, 1801 .resume = genphy_resume, 1802 .read_page = rtl821x_read_page, 1803 .write_page = rtl821x_write_page, 1804 }, { 1805 PHY_ID_MATCH_EXACT(0x001cc942), 1806 .name = "RTL8365MB-VC Gigabit Ethernet", 1807 /* Interrupt handling analogous to RTL8366RB */ 1808 .config_intr = genphy_no_config_intr, 1809 .handle_interrupt = genphy_handle_interrupt_no_ack, 1810 .suspend = genphy_suspend, 1811 .resume = genphy_resume, 1812 }, { 1813 PHY_ID_MATCH_EXACT(0x001cc960), 1814 .name = "RTL8366S Gigabit Ethernet", 1815 .suspend = genphy_suspend, 1816 .resume = genphy_resume, 1817 .read_mmd = genphy_read_mmd_unsupported, 1818 .write_mmd = genphy_write_mmd_unsupported, 1819 }, 1820 }; 1821 1822 module_phy_driver(realtek_drvs); 1823 1824 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1825 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1826 { } 1827 }; 1828 1829 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1830