1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 21 #include "realtek.h" 22 23 #define RTL8201F_IER 0x13 24 25 #define RTL8201F_ISR 0x1e 26 #define RTL8201F_ISR_ANERR BIT(15) 27 #define RTL8201F_ISR_DUPLEX BIT(13) 28 #define RTL8201F_ISR_LINK BIT(11) 29 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 30 RTL8201F_ISR_DUPLEX | \ 31 RTL8201F_ISR_LINK) 32 33 #define RTL821x_INER 0x12 34 #define RTL8211B_INER_INIT 0x6400 35 #define RTL8211E_INER_LINK_STATUS BIT(10) 36 #define RTL8211F_INER_PME BIT(7) 37 #define RTL8211F_INER_LINK_STATUS BIT(4) 38 39 #define RTL821x_INSR 0x13 40 41 #define RTL821x_EXT_PAGE_SELECT 0x1e 42 43 #define RTL821x_PAGE_SELECT 0x1f 44 #define RTL821x_SET_EXT_PAGE 0x07 45 46 /* RTL8211E extension page 44/0x2c */ 47 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 48 #define RTL8211E_LEDCR1 0x1a 49 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 50 #define RTL8211E_LEDCR1_MASK BIT(4) 51 #define RTL8211E_LEDCR1_SHIFT 1 52 53 #define RTL8211E_LEDCR2 0x1c 54 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 55 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 56 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 57 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 58 #define RTL8211E_LEDCR2_SHIFT 4 59 60 /* RTL8211E extension page 164/0xa4 */ 61 #define RTL8211E_RGMII_EXT_PAGE 0xa4 62 #define RTL8211E_RGMII_DELAY 0x1c 63 #define RTL8211E_CTRL_DELAY BIT(13) 64 #define RTL8211E_TX_DELAY BIT(12) 65 #define RTL8211E_RX_DELAY BIT(11) 66 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 67 68 /* RTL8211F PHY configuration */ 69 #define RTL8211F_PHYCR_PAGE 0xa43 70 #define RTL8211F_PHYCR1 0x18 71 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 72 #define RTL8211F_ALDPS_ENABLE BIT(2) 73 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 74 75 #define RTL8211F_PHYCR2 0x19 76 #define RTL8211F_CLKOUT_EN BIT(0) 77 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 78 79 #define RTL8211F_INSR_PAGE 0xa43 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F RGMII configuration */ 94 #define RTL8211F_RGMII_PAGE 0xd08 95 96 #define RTL8211F_TXCR 0x11 97 #define RTL8211F_TX_DELAY BIT(8) 98 99 #define RTL8211F_RXCR 0x15 100 #define RTL8211F_RX_DELAY BIT(3) 101 102 /* RTL8211F WOL settings */ 103 #define RTL8211F_WOL_PAGE 0xd8a 104 #define RTL8211F_WOL_SETTINGS_EVENTS 16 105 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 106 #define RTL8211F_WOL_RST_RMSQ 17 107 #define RTL8211F_WOL_RG_RSTB BIT(15) 108 #define RTL8211F_WOL_RMSQ 0x1fff 109 110 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 111 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 112 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 113 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 114 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 115 116 #define RTL822X_VND1_SERDES_OPTION 0x697a 117 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 118 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 119 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 120 121 #define RTL822X_VND1_SERDES_CTRL3 0x7580 122 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 124 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 125 126 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 127 * is set, they cannot be accessed by C45-over-C22. 128 */ 129 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 130 131 #define RTL8221B_VND2_INER 0xa4d2 132 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 133 134 #define RTL8221B_VND2_INSR 0xa4d4 135 136 #define RTL8224_MII_RTCT 0x11 137 #define RTL8224_MII_RTCT_ENABLE BIT(0) 138 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 139 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 140 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 141 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 142 #define RTL8224_MII_RTCT_DONE BIT(15) 143 144 #define RTL8224_MII_SRAM_ADDR 0x1b 145 #define RTL8224_MII_SRAM_DATA 0x1c 146 147 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 148 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 149 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 150 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 151 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 152 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 153 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 154 155 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 156 157 #define RTL8366RB_POWER_SAVE 0x15 158 #define RTL8366RB_POWER_SAVE_ON BIT(12) 159 160 #define RTL9000A_GINMR 0x14 161 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 162 163 #define RTL_VND2_PHYSR 0xa434 164 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 165 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 166 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 167 #define RTL_VND2_PHYSR_MASTER BIT(11) 168 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 169 170 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 171 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 172 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 173 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 174 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 175 #define RTL_MDIO_PMA_SPEED 0xa616 176 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 177 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 178 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 179 180 #define RTL_GENERIC_PHYID 0x001cc800 181 #define RTL_8211FVD_PHYID 0x001cc878 182 #define RTL_8221B 0x001cc840 183 #define RTL_8221B_VB_CG 0x001cc849 184 #define RTL_8221B_VM_CG 0x001cc84a 185 #define RTL_8251B 0x001cc862 186 #define RTL_8261C 0x001cc890 187 188 /* RTL8211E and RTL8211F support up to three LEDs */ 189 #define RTL8211x_LED_COUNT 3 190 191 MODULE_DESCRIPTION("Realtek PHY driver"); 192 MODULE_AUTHOR("Johnson Leung"); 193 MODULE_LICENSE("GPL"); 194 195 struct rtl821x_priv { 196 u16 phycr1; 197 u16 phycr2; 198 bool has_phycr2; 199 struct clk *clk; 200 /* rtl8211f */ 201 u16 iner; 202 }; 203 204 static int rtl821x_read_page(struct phy_device *phydev) 205 { 206 return __phy_read(phydev, RTL821x_PAGE_SELECT); 207 } 208 209 static int rtl821x_write_page(struct phy_device *phydev, int page) 210 { 211 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 212 } 213 214 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 215 u32 regnum) 216 { 217 int oldpage, ret = 0; 218 219 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 220 if (oldpage >= 0) { 221 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 222 if (ret == 0) 223 ret = __phy_read(phydev, regnum); 224 } 225 226 return phy_restore_page(phydev, oldpage, ret); 227 } 228 229 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 230 u32 regnum, u16 mask, u16 set) 231 { 232 int oldpage, ret = 0; 233 234 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 235 if (oldpage >= 0) { 236 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 237 if (ret == 0) 238 ret = __phy_modify(phydev, regnum, mask, set); 239 } 240 241 return phy_restore_page(phydev, oldpage, ret); 242 } 243 244 static int rtl821x_probe(struct phy_device *phydev) 245 { 246 struct device *dev = &phydev->mdio.dev; 247 struct rtl821x_priv *priv; 248 u32 phy_id = phydev->drv->phy_id; 249 int ret; 250 251 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 252 if (!priv) 253 return -ENOMEM; 254 255 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 256 if (IS_ERR(priv->clk)) 257 return dev_err_probe(dev, PTR_ERR(priv->clk), 258 "failed to get phy clock\n"); 259 260 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 261 if (ret < 0) 262 return ret; 263 264 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 265 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 266 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 267 268 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 269 if (priv->has_phycr2) { 270 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 271 if (ret < 0) 272 return ret; 273 274 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 275 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 276 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 277 } 278 279 phydev->priv = priv; 280 281 return 0; 282 } 283 284 static int rtl8211f_probe(struct phy_device *phydev) 285 { 286 struct device *dev = &phydev->mdio.dev; 287 int ret; 288 289 ret = rtl821x_probe(phydev); 290 if (ret < 0) 291 return ret; 292 293 /* Disable all PME events */ 294 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 295 RTL8211F_WOL_SETTINGS_EVENTS, 0); 296 if (ret < 0) 297 return ret; 298 299 /* Mark this PHY as wakeup capable and register the interrupt as a 300 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 301 * and the interrupt is valid. 302 */ 303 if (device_property_read_bool(dev, "wakeup-source") && 304 phy_interrupt_is_valid(phydev)) { 305 device_set_wakeup_capable(dev, true); 306 devm_pm_set_wake_irq(dev, phydev->irq); 307 } 308 309 return ret; 310 } 311 312 static int rtl8201_ack_interrupt(struct phy_device *phydev) 313 { 314 int err; 315 316 err = phy_read(phydev, RTL8201F_ISR); 317 318 return (err < 0) ? err : 0; 319 } 320 321 static int rtl821x_ack_interrupt(struct phy_device *phydev) 322 { 323 int err; 324 325 err = phy_read(phydev, RTL821x_INSR); 326 327 return (err < 0) ? err : 0; 328 } 329 330 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 331 { 332 int err; 333 334 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 335 336 return (err < 0) ? err : 0; 337 } 338 339 static int rtl8201_config_intr(struct phy_device *phydev) 340 { 341 u16 val; 342 int err; 343 344 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 345 err = rtl8201_ack_interrupt(phydev); 346 if (err) 347 return err; 348 349 val = BIT(13) | BIT(12) | BIT(11); 350 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 351 } else { 352 val = 0; 353 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 354 if (err) 355 return err; 356 357 err = rtl8201_ack_interrupt(phydev); 358 } 359 360 return err; 361 } 362 363 static int rtl8211b_config_intr(struct phy_device *phydev) 364 { 365 int err; 366 367 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 368 err = rtl821x_ack_interrupt(phydev); 369 if (err) 370 return err; 371 372 err = phy_write(phydev, RTL821x_INER, 373 RTL8211B_INER_INIT); 374 } else { 375 err = phy_write(phydev, RTL821x_INER, 0); 376 if (err) 377 return err; 378 379 err = rtl821x_ack_interrupt(phydev); 380 } 381 382 return err; 383 } 384 385 static int rtl8211e_config_intr(struct phy_device *phydev) 386 { 387 int err; 388 389 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 390 err = rtl821x_ack_interrupt(phydev); 391 if (err) 392 return err; 393 394 err = phy_write(phydev, RTL821x_INER, 395 RTL8211E_INER_LINK_STATUS); 396 } else { 397 err = phy_write(phydev, RTL821x_INER, 0); 398 if (err) 399 return err; 400 401 err = rtl821x_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static int rtl8211f_config_intr(struct phy_device *phydev) 408 { 409 struct rtl821x_priv *priv = phydev->priv; 410 u16 val; 411 int err; 412 413 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 414 err = rtl8211f_ack_interrupt(phydev); 415 if (err) 416 return err; 417 418 val = RTL8211F_INER_LINK_STATUS; 419 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 420 if (err == 0) 421 priv->iner = val; 422 } else { 423 priv->iner = val = 0; 424 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 425 if (err) 426 return err; 427 428 err = rtl8211f_ack_interrupt(phydev); 429 } 430 431 return err; 432 } 433 434 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 435 { 436 int irq_status; 437 438 irq_status = phy_read(phydev, RTL8201F_ISR); 439 if (irq_status < 0) { 440 phy_error(phydev); 441 return IRQ_NONE; 442 } 443 444 if (!(irq_status & RTL8201F_ISR_MASK)) 445 return IRQ_NONE; 446 447 phy_trigger_machine(phydev); 448 449 return IRQ_HANDLED; 450 } 451 452 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 453 { 454 int irq_status, irq_enabled; 455 456 irq_status = phy_read(phydev, RTL821x_INSR); 457 if (irq_status < 0) { 458 phy_error(phydev); 459 return IRQ_NONE; 460 } 461 462 irq_enabled = phy_read(phydev, RTL821x_INER); 463 if (irq_enabled < 0) { 464 phy_error(phydev); 465 return IRQ_NONE; 466 } 467 468 if (!(irq_status & irq_enabled)) 469 return IRQ_NONE; 470 471 phy_trigger_machine(phydev); 472 473 return IRQ_HANDLED; 474 } 475 476 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 477 { 478 int irq_status; 479 480 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 481 if (irq_status < 0) { 482 phy_error(phydev); 483 return IRQ_NONE; 484 } 485 486 if (irq_status & RTL8211F_INER_LINK_STATUS) { 487 phy_trigger_machine(phydev); 488 return IRQ_HANDLED; 489 } 490 491 if (irq_status & RTL8211F_INER_PME) { 492 pm_wakeup_event(&phydev->mdio.dev, 0); 493 return IRQ_HANDLED; 494 } 495 496 return IRQ_NONE; 497 } 498 499 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 500 { 501 int wol_events; 502 503 /* If the PHY is not capable of waking the system, then WoL can not 504 * be supported. 505 */ 506 if (!device_can_wakeup(&dev->mdio.dev)) { 507 wol->supported = 0; 508 return; 509 } 510 511 wol->supported = WAKE_MAGIC; 512 513 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 514 if (wol_events < 0) 515 return; 516 517 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 518 wol->wolopts = WAKE_MAGIC; 519 } 520 521 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 522 { 523 const u8 *mac_addr = dev->attached_dev->dev_addr; 524 int oldpage; 525 526 if (!device_can_wakeup(&dev->mdio.dev)) 527 return -EOPNOTSUPP; 528 529 oldpage = phy_save_page(dev); 530 if (oldpage < 0) 531 goto err; 532 533 if (wol->wolopts & WAKE_MAGIC) { 534 /* Store the device address for the magic packet */ 535 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 536 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 537 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 538 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 539 540 /* Enable magic packet matching */ 541 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 542 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 543 /* Set the maximum packet size, and assert WoL reset */ 544 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 545 } else { 546 /* Disable magic packet matching */ 547 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 548 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 549 550 /* Place WoL in reset */ 551 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 552 RTL8211F_WOL_RG_RSTB); 553 } 554 555 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 556 557 err: 558 return phy_restore_page(dev, oldpage, 0); 559 } 560 561 static int rtl8211_config_aneg(struct phy_device *phydev) 562 { 563 int ret; 564 565 ret = genphy_config_aneg(phydev); 566 if (ret < 0) 567 return ret; 568 569 /* Quirk was copied from vendor driver. Unfortunately it includes no 570 * description of the magic numbers. 571 */ 572 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 573 phy_write(phydev, 0x17, 0x2138); 574 phy_write(phydev, 0x0e, 0x0260); 575 } else { 576 phy_write(phydev, 0x17, 0x2108); 577 phy_write(phydev, 0x0e, 0x0000); 578 } 579 580 return 0; 581 } 582 583 static int rtl8211c_config_init(struct phy_device *phydev) 584 { 585 /* RTL8211C has an issue when operating in Gigabit slave mode */ 586 return phy_set_bits(phydev, MII_CTRL1000, 587 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 588 } 589 590 static int rtl8211f_config_init(struct phy_device *phydev) 591 { 592 struct rtl821x_priv *priv = phydev->priv; 593 struct device *dev = &phydev->mdio.dev; 594 u16 val_txdly, val_rxdly; 595 int ret; 596 597 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 598 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 599 priv->phycr1); 600 if (ret < 0) { 601 dev_err(dev, "aldps mode configuration failed: %pe\n", 602 ERR_PTR(ret)); 603 return ret; 604 } 605 606 switch (phydev->interface) { 607 case PHY_INTERFACE_MODE_RGMII: 608 val_txdly = 0; 609 val_rxdly = 0; 610 break; 611 612 case PHY_INTERFACE_MODE_RGMII_RXID: 613 val_txdly = 0; 614 val_rxdly = RTL8211F_RX_DELAY; 615 break; 616 617 case PHY_INTERFACE_MODE_RGMII_TXID: 618 val_txdly = RTL8211F_TX_DELAY; 619 val_rxdly = 0; 620 break; 621 622 case PHY_INTERFACE_MODE_RGMII_ID: 623 val_txdly = RTL8211F_TX_DELAY; 624 val_rxdly = RTL8211F_RX_DELAY; 625 break; 626 627 default: /* the rest of the modes imply leaving delay as is. */ 628 return 0; 629 } 630 631 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 632 RTL8211F_TXCR, RTL8211F_TX_DELAY, 633 val_txdly); 634 if (ret < 0) { 635 dev_err(dev, "Failed to update the TX delay register\n"); 636 return ret; 637 } else if (ret) { 638 dev_dbg(dev, 639 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 640 str_enable_disable(val_txdly)); 641 } else { 642 dev_dbg(dev, 643 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 644 str_enabled_disabled(val_txdly)); 645 } 646 647 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 648 RTL8211F_RXCR, RTL8211F_RX_DELAY, 649 val_rxdly); 650 if (ret < 0) { 651 dev_err(dev, "Failed to update the RX delay register\n"); 652 return ret; 653 } else if (ret) { 654 dev_dbg(dev, 655 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 656 str_enable_disable(val_rxdly)); 657 } else { 658 dev_dbg(dev, 659 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 660 str_enabled_disabled(val_rxdly)); 661 } 662 663 if (!priv->has_phycr2) 664 return 0; 665 666 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 667 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 668 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 669 if (ret) 670 return ret; 671 672 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 673 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 674 priv->phycr2); 675 if (ret < 0) { 676 dev_err(dev, "clkout configuration failed: %pe\n", 677 ERR_PTR(ret)); 678 return ret; 679 } 680 681 return genphy_soft_reset(phydev); 682 } 683 684 static int rtl821x_suspend(struct phy_device *phydev) 685 { 686 struct rtl821x_priv *priv = phydev->priv; 687 int ret = 0; 688 689 if (!phydev->wol_enabled) { 690 ret = genphy_suspend(phydev); 691 692 if (ret) 693 return ret; 694 695 clk_disable_unprepare(priv->clk); 696 } 697 698 return ret; 699 } 700 701 static int rtl8211f_suspend(struct phy_device *phydev) 702 { 703 u16 wol_rst; 704 int ret; 705 706 ret = rtl821x_suspend(phydev); 707 if (ret < 0) 708 return ret; 709 710 /* If a PME event is enabled, then configure the interrupt for 711 * PME events only, disabling link interrupt. We avoid switching 712 * to PMEB mode as we don't have a status bit for that. 713 */ 714 if (device_may_wakeup(&phydev->mdio.dev)) { 715 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 716 RTL8211F_INER_PME); 717 if (ret < 0) 718 goto err; 719 720 /* Read the INSR to clear any pending interrupt */ 721 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 722 723 /* Reset the WoL to ensure that an event is picked up. 724 * Unless we do this, even if we receive another packet, 725 * we may not have a PME interrupt raised. 726 */ 727 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 728 RTL8211F_WOL_RST_RMSQ); 729 if (ret < 0) 730 goto err; 731 732 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 733 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 734 RTL8211F_WOL_RST_RMSQ, wol_rst); 735 if (ret < 0) 736 goto err; 737 738 wol_rst |= RTL8211F_WOL_RG_RSTB; 739 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 740 RTL8211F_WOL_RST_RMSQ, wol_rst); 741 } 742 743 err: 744 return ret; 745 } 746 747 static int rtl821x_resume(struct phy_device *phydev) 748 { 749 struct rtl821x_priv *priv = phydev->priv; 750 int ret; 751 752 if (!phydev->wol_enabled) 753 clk_prepare_enable(priv->clk); 754 755 ret = genphy_resume(phydev); 756 if (ret < 0) 757 return ret; 758 759 msleep(20); 760 761 return 0; 762 } 763 764 static int rtl8211f_resume(struct phy_device *phydev) 765 { 766 struct rtl821x_priv *priv = phydev->priv; 767 int ret; 768 769 ret = rtl821x_resume(phydev); 770 if (ret < 0) 771 return ret; 772 773 /* If the device was programmed for a PME event, restore the interrupt 774 * enable so phylib can receive link state interrupts. 775 */ 776 if (device_may_wakeup(&phydev->mdio.dev)) 777 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 778 779 return ret; 780 } 781 782 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 783 unsigned long rules) 784 { 785 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 786 BIT(TRIGGER_NETDEV_LINK_10) | 787 BIT(TRIGGER_NETDEV_LINK_100) | 788 BIT(TRIGGER_NETDEV_LINK_1000) | 789 BIT(TRIGGER_NETDEV_RX) | 790 BIT(TRIGGER_NETDEV_TX); 791 792 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 793 * - Link: Configurable subset of 10/100/1000 link rates 794 * - Active: Blink on activity, RX or TX is not differentiated 795 * The Active option has two modes, A and B: 796 * - A: Link and Active indication at configurable, but matching, 797 * subset of 10/100/1000 link rates 798 * - B: Link indication at configurable subset of 10/100/1000 link 799 * rates and Active indication always at all three 10+100+1000 800 * link rates. 801 * This code currently uses mode B only. 802 * 803 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 804 */ 805 806 if (index >= RTL8211x_LED_COUNT) 807 return -EINVAL; 808 809 /* Filter out any other unsupported triggers. */ 810 if (rules & ~mask) 811 return -EOPNOTSUPP; 812 813 /* RX and TX are not differentiated, either both are set or not set. */ 814 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 815 return -EOPNOTSUPP; 816 817 return 0; 818 } 819 820 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 821 unsigned long *rules) 822 { 823 int val; 824 825 if (index >= RTL8211x_LED_COUNT) 826 return -EINVAL; 827 828 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 829 if (val < 0) 830 return val; 831 832 val >>= RTL8211F_LEDCR_SHIFT * index; 833 val &= RTL8211F_LEDCR_MASK; 834 835 if (val & RTL8211F_LEDCR_LINK_10) 836 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 837 838 if (val & RTL8211F_LEDCR_LINK_100) 839 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 840 841 if (val & RTL8211F_LEDCR_LINK_1000) 842 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 843 844 if ((val & RTL8211F_LEDCR_LINK_10) && 845 (val & RTL8211F_LEDCR_LINK_100) && 846 (val & RTL8211F_LEDCR_LINK_1000)) { 847 __set_bit(TRIGGER_NETDEV_LINK, rules); 848 } 849 850 if (val & RTL8211F_LEDCR_ACT_TXRX) { 851 __set_bit(TRIGGER_NETDEV_RX, rules); 852 __set_bit(TRIGGER_NETDEV_TX, rules); 853 } 854 855 return 0; 856 } 857 858 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 859 unsigned long rules) 860 { 861 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 862 u16 reg = 0; 863 864 if (index >= RTL8211x_LED_COUNT) 865 return -EINVAL; 866 867 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 868 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 869 reg |= RTL8211F_LEDCR_LINK_10; 870 } 871 872 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 873 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 874 reg |= RTL8211F_LEDCR_LINK_100; 875 } 876 877 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 878 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 879 reg |= RTL8211F_LEDCR_LINK_1000; 880 } 881 882 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 883 test_bit(TRIGGER_NETDEV_TX, &rules)) { 884 reg |= RTL8211F_LEDCR_ACT_TXRX; 885 } 886 887 reg <<= RTL8211F_LEDCR_SHIFT * index; 888 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 889 890 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 891 } 892 893 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 894 unsigned long *rules) 895 { 896 int ret; 897 u16 cr1, cr2; 898 899 if (index >= RTL8211x_LED_COUNT) 900 return -EINVAL; 901 902 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 903 RTL8211E_LEDCR1); 904 if (ret < 0) 905 return ret; 906 907 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 908 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 909 __set_bit(TRIGGER_NETDEV_RX, rules); 910 __set_bit(TRIGGER_NETDEV_TX, rules); 911 } 912 913 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 914 RTL8211E_LEDCR2); 915 if (ret < 0) 916 return ret; 917 918 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 919 if (cr2 & RTL8211E_LEDCR2_LINK_10) 920 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 921 922 if (cr2 & RTL8211E_LEDCR2_LINK_100) 923 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 924 925 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 926 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 927 928 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 929 (cr2 & RTL8211E_LEDCR2_LINK_100) && 930 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 931 __set_bit(TRIGGER_NETDEV_LINK, rules); 932 } 933 934 return ret; 935 } 936 937 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 938 unsigned long rules) 939 { 940 const u16 cr1mask = 941 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 942 const u16 cr2mask = 943 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 944 u16 cr1 = 0, cr2 = 0; 945 int ret; 946 947 if (index >= RTL8211x_LED_COUNT) 948 return -EINVAL; 949 950 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 951 test_bit(TRIGGER_NETDEV_TX, &rules)) { 952 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 953 } 954 955 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 956 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 957 RTL8211E_LEDCR1, cr1mask, cr1); 958 if (ret < 0) 959 return ret; 960 961 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 962 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 963 cr2 |= RTL8211E_LEDCR2_LINK_10; 964 } 965 966 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 967 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 968 cr2 |= RTL8211E_LEDCR2_LINK_100; 969 } 970 971 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 972 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 973 cr2 |= RTL8211E_LEDCR2_LINK_1000; 974 } 975 976 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 977 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 978 RTL8211E_LEDCR2, cr2mask, cr2); 979 980 return ret; 981 } 982 983 static int rtl8211e_config_init(struct phy_device *phydev) 984 { 985 u16 val; 986 987 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 988 switch (phydev->interface) { 989 case PHY_INTERFACE_MODE_RGMII: 990 val = RTL8211E_CTRL_DELAY | 0; 991 break; 992 case PHY_INTERFACE_MODE_RGMII_ID: 993 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 994 break; 995 case PHY_INTERFACE_MODE_RGMII_RXID: 996 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 997 break; 998 case PHY_INTERFACE_MODE_RGMII_TXID: 999 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1000 break; 1001 default: /* the rest of the modes imply leaving delays as is. */ 1002 return 0; 1003 } 1004 1005 /* According to a sample driver there is a 0x1c config register on the 1006 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1007 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1008 * The configuration register definition: 1009 * 14 = reserved 1010 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1011 * 12 = RX Delay, 11 = TX Delay 1012 * 10:0 = Test && debug settings reserved by realtek 1013 */ 1014 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1015 RTL8211E_RGMII_DELAY, 1016 RTL8211E_DELAY_MASK, val); 1017 } 1018 1019 static int rtl8211b_suspend(struct phy_device *phydev) 1020 { 1021 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1022 1023 return genphy_suspend(phydev); 1024 } 1025 1026 static int rtl8211b_resume(struct phy_device *phydev) 1027 { 1028 phy_write(phydev, MII_MMD_DATA, 0); 1029 1030 return genphy_resume(phydev); 1031 } 1032 1033 static int rtl8366rb_config_init(struct phy_device *phydev) 1034 { 1035 int ret; 1036 1037 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1038 RTL8366RB_POWER_SAVE_ON); 1039 if (ret) { 1040 dev_err(&phydev->mdio.dev, 1041 "error enabling power management\n"); 1042 } 1043 1044 return ret; 1045 } 1046 1047 /* get actual speed to cover the downshift case */ 1048 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1049 { 1050 /* bit 3 1051 * 0: Half Duplex 1052 * 1: Full Duplex 1053 */ 1054 if (val & RTL_VND2_PHYSR_DUPLEX) 1055 phydev->duplex = DUPLEX_FULL; 1056 else 1057 phydev->duplex = DUPLEX_HALF; 1058 1059 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1060 case 0x0000: 1061 phydev->speed = SPEED_10; 1062 break; 1063 case 0x0010: 1064 phydev->speed = SPEED_100; 1065 break; 1066 case 0x0020: 1067 phydev->speed = SPEED_1000; 1068 break; 1069 case 0x0200: 1070 phydev->speed = SPEED_10000; 1071 break; 1072 case 0x0210: 1073 phydev->speed = SPEED_2500; 1074 break; 1075 case 0x0220: 1076 phydev->speed = SPEED_5000; 1077 break; 1078 default: 1079 break; 1080 } 1081 1082 /* bit 11 1083 * 0: Slave Mode 1084 * 1: Master Mode 1085 */ 1086 if (phydev->speed >= 1000) { 1087 if (val & RTL_VND2_PHYSR_MASTER) 1088 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1089 else 1090 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1091 } else { 1092 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1093 } 1094 } 1095 1096 static int rtlgen_read_status(struct phy_device *phydev) 1097 { 1098 int ret, val; 1099 1100 ret = genphy_read_status(phydev); 1101 if (ret < 0) 1102 return ret; 1103 1104 if (!phydev->link) 1105 return 0; 1106 1107 val = phy_read_paged(phydev, 0xa43, 0x12); 1108 if (val < 0) 1109 return val; 1110 1111 rtlgen_decode_physr(phydev, val); 1112 1113 return 0; 1114 } 1115 1116 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1117 { 1118 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1119 } 1120 1121 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1122 { 1123 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1124 val); 1125 } 1126 1127 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1128 { 1129 int ret; 1130 1131 if (devnum == MDIO_MMD_VEND2) 1132 ret = rtlgen_read_vend2(phydev, regnum); 1133 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1134 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1135 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1136 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1137 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1138 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1139 else 1140 ret = -EOPNOTSUPP; 1141 1142 return ret; 1143 } 1144 1145 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1146 u16 val) 1147 { 1148 int ret; 1149 1150 if (devnum == MDIO_MMD_VEND2) 1151 ret = rtlgen_write_vend2(phydev, regnum, val); 1152 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1153 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1154 else 1155 ret = -EOPNOTSUPP; 1156 1157 return ret; 1158 } 1159 1160 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1161 { 1162 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1163 1164 if (ret != -EOPNOTSUPP) 1165 return ret; 1166 1167 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1168 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1169 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1170 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1171 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1172 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1173 1174 return ret; 1175 } 1176 1177 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1178 u16 val) 1179 { 1180 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1181 1182 if (ret != -EOPNOTSUPP) 1183 return ret; 1184 1185 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1186 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1187 1188 return ret; 1189 } 1190 1191 static int rtl822x_probe(struct phy_device *phydev) 1192 { 1193 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1194 phydev->phy_id != RTL_GENERIC_PHYID) 1195 return rtl822x_hwmon_init(phydev); 1196 1197 return 0; 1198 } 1199 1200 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1201 { 1202 bool has_2500, has_sgmii; 1203 u16 mode; 1204 int ret; 1205 1206 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1207 phydev->host_interfaces) || 1208 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1209 1210 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1211 phydev->host_interfaces) || 1212 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1213 1214 /* fill in possible interfaces */ 1215 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1216 has_2500); 1217 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1218 has_sgmii); 1219 1220 if (!has_2500 && !has_sgmii) 1221 return 0; 1222 1223 /* determine SerDes option mode */ 1224 if (has_2500 && !has_sgmii) { 1225 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1226 phydev->rate_matching = RATE_MATCH_PAUSE; 1227 } else { 1228 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1229 phydev->rate_matching = RATE_MATCH_NONE; 1230 } 1231 1232 /* the following sequence with magic numbers sets up the SerDes 1233 * option mode 1234 */ 1235 1236 if (!gen1) { 1237 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1238 if (ret < 0) 1239 return ret; 1240 } 1241 1242 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1243 RTL822X_VND1_SERDES_OPTION, 1244 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1245 mode); 1246 if (gen1 || ret < 0) 1247 return ret; 1248 1249 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1250 if (ret < 0) 1251 return ret; 1252 1253 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1254 if (ret < 0) 1255 return ret; 1256 1257 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1258 } 1259 1260 static int rtl822x_config_init(struct phy_device *phydev) 1261 { 1262 return rtl822x_set_serdes_option_mode(phydev, true); 1263 } 1264 1265 static int rtl822xb_config_init(struct phy_device *phydev) 1266 { 1267 return rtl822x_set_serdes_option_mode(phydev, false); 1268 } 1269 1270 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1271 phy_interface_t iface) 1272 { 1273 int val; 1274 1275 /* Only rate matching at 2500base-x */ 1276 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1277 return RATE_MATCH_NONE; 1278 1279 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1280 if (val < 0) 1281 return val; 1282 1283 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1284 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1285 return RATE_MATCH_PAUSE; 1286 1287 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1288 return RATE_MATCH_NONE; 1289 } 1290 1291 static int rtl822x_get_features(struct phy_device *phydev) 1292 { 1293 int val; 1294 1295 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1296 if (val < 0) 1297 return val; 1298 1299 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1300 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1301 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1302 phydev->supported, val & MDIO_PMA_SPEED_5G); 1303 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1304 phydev->supported, val & MDIO_SPEED_10G); 1305 1306 return genphy_read_abilities(phydev); 1307 } 1308 1309 static int rtl822x_config_aneg(struct phy_device *phydev) 1310 { 1311 int ret = 0; 1312 1313 if (phydev->autoneg == AUTONEG_ENABLE) { 1314 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1315 1316 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1317 RTL_MDIO_AN_10GBT_CTRL, 1318 MDIO_AN_10GBT_CTRL_ADV2_5G | 1319 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1320 if (ret < 0) 1321 return ret; 1322 } 1323 1324 return __genphy_config_aneg(phydev, ret); 1325 } 1326 1327 static void rtl822xb_update_interface(struct phy_device *phydev) 1328 { 1329 int val; 1330 1331 if (!phydev->link) 1332 return; 1333 1334 /* Change interface according to serdes mode */ 1335 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1336 if (val < 0) 1337 return; 1338 1339 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1340 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1341 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1342 break; 1343 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1344 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1345 break; 1346 } 1347 } 1348 1349 static int rtl822x_read_status(struct phy_device *phydev) 1350 { 1351 int lpadv, ret; 1352 1353 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1354 1355 ret = rtlgen_read_status(phydev); 1356 if (ret < 0) 1357 return ret; 1358 1359 if (phydev->autoneg == AUTONEG_DISABLE || 1360 !phydev->autoneg_complete) 1361 return 0; 1362 1363 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1364 if (lpadv < 0) 1365 return lpadv; 1366 1367 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1368 1369 return 0; 1370 } 1371 1372 static int rtl822xb_read_status(struct phy_device *phydev) 1373 { 1374 int ret; 1375 1376 ret = rtl822x_read_status(phydev); 1377 if (ret < 0) 1378 return ret; 1379 1380 rtl822xb_update_interface(phydev); 1381 1382 return 0; 1383 } 1384 1385 static int rtl822x_c45_get_features(struct phy_device *phydev) 1386 { 1387 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1388 phydev->supported); 1389 1390 return genphy_c45_pma_read_abilities(phydev); 1391 } 1392 1393 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1394 { 1395 bool changed = false; 1396 int ret, val; 1397 1398 if (phydev->autoneg == AUTONEG_DISABLE) 1399 return genphy_c45_pma_setup_forced(phydev); 1400 1401 ret = genphy_c45_an_config_aneg(phydev); 1402 if (ret < 0) 1403 return ret; 1404 if (ret > 0) 1405 changed = true; 1406 1407 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1408 1409 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1410 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1411 RTL822X_VND2_C22_REG(MII_CTRL1000), 1412 ADVERTISE_1000FULL, val); 1413 if (ret < 0) 1414 return ret; 1415 if (ret > 0) 1416 changed = true; 1417 1418 return genphy_c45_check_and_restart_aneg(phydev, changed); 1419 } 1420 1421 static int rtl822x_c45_read_status(struct phy_device *phydev) 1422 { 1423 int ret, val; 1424 1425 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1426 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1427 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1428 RTL822X_VND2_C22_REG(MII_STAT1000)); 1429 if (val < 0) 1430 return val; 1431 } else { 1432 val = 0; 1433 } 1434 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1435 1436 ret = genphy_c45_read_status(phydev); 1437 if (ret < 0) 1438 return ret; 1439 1440 if (!phydev->link) { 1441 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1442 return 0; 1443 } 1444 1445 /* Read actual speed from vendor register. */ 1446 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1447 if (val < 0) 1448 return val; 1449 1450 rtlgen_decode_physr(phydev, val); 1451 1452 return 0; 1453 } 1454 1455 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1456 { 1457 int ret, val; 1458 1459 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1460 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1461 if (ret < 0) 1462 return ret; 1463 1464 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1465 MDIO_CTRL1, val, 1466 !(val & MDIO_CTRL1_RESET), 1467 5000, 100000, true); 1468 } 1469 1470 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1471 { 1472 int ret; 1473 1474 ret = rtl822x_c45_read_status(phydev); 1475 if (ret < 0) 1476 return ret; 1477 1478 rtl822xb_update_interface(phydev); 1479 1480 return 0; 1481 } 1482 1483 static int rtl8224_cable_test_start(struct phy_device *phydev) 1484 { 1485 u32 val; 1486 int ret; 1487 1488 /* disable auto-negotiation and force 1000/Full */ 1489 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1490 RTL822X_VND2_C22_REG(MII_BMCR), 1491 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1492 BMCR_SPEED1000 | BMCR_FULLDPLX); 1493 if (ret) 1494 return ret; 1495 1496 mdelay(500); 1497 1498 /* trigger cable test */ 1499 val = RTL8224_MII_RTCT_ENABLE; 1500 val |= RTL8224_MII_RTCT_PAIR_A; 1501 val |= RTL8224_MII_RTCT_PAIR_B; 1502 val |= RTL8224_MII_RTCT_PAIR_C; 1503 val |= RTL8224_MII_RTCT_PAIR_D; 1504 1505 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1506 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1507 RTL8224_MII_RTCT_DONE, val); 1508 } 1509 1510 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1511 { 1512 int ret; 1513 1514 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1515 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1516 reg); 1517 if (ret) 1518 return ret; 1519 1520 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1521 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1522 } 1523 1524 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1525 { 1526 int cable_len; 1527 u32 reg_len; 1528 int ret; 1529 u32 cm; 1530 1531 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1532 1533 ret = rtl8224_sram_read(phydev, reg_len); 1534 if (ret < 0) 1535 return ret; 1536 1537 cable_len = ret & 0xff00; 1538 1539 ret = rtl8224_sram_read(phydev, reg_len + 1); 1540 if (ret < 0) 1541 return ret; 1542 1543 cable_len |= (ret & 0xff00) >> 8; 1544 1545 cable_len -= 620; 1546 cable_len = max(cable_len, 0); 1547 1548 cm = cable_len * 100 / 78; 1549 1550 return cm; 1551 } 1552 1553 static int rtl8224_cable_test_result_trans(u32 result) 1554 { 1555 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1556 return -EBUSY; 1557 1558 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1559 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1560 1561 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1562 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1563 1564 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1565 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1566 1567 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1568 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1569 1570 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1571 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1572 1573 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1574 } 1575 1576 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1577 { 1578 int fault_rslt; 1579 int ret; 1580 1581 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1582 if (ret < 0) 1583 return ret; 1584 1585 fault_rslt = rtl8224_cable_test_result_trans(ret); 1586 if (fault_rslt < 0) 1587 return 0; 1588 1589 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1590 if (ret < 0) 1591 return ret; 1592 1593 switch (fault_rslt) { 1594 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1595 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1596 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1597 ret = rtl8224_pair_len_get(phydev, pair); 1598 if (ret < 0) 1599 return ret; 1600 1601 return ethnl_cable_test_fault_length(phydev, pair, ret); 1602 default: 1603 return 0; 1604 } 1605 } 1606 1607 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1608 { 1609 unsigned int pair; 1610 int ret; 1611 1612 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1613 ret = rtl8224_cable_test_report_pair(phydev, pair); 1614 if (ret == -EBUSY) { 1615 *finished = false; 1616 return 0; 1617 } 1618 1619 if (ret < 0) 1620 return ret; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1627 { 1628 int ret; 1629 1630 *finished = false; 1631 1632 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1633 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1634 if (ret < 0) 1635 return ret; 1636 1637 if (!(ret & RTL8224_MII_RTCT_DONE)) 1638 return 0; 1639 1640 *finished = true; 1641 1642 return rtl8224_cable_test_report(phydev, finished); 1643 } 1644 1645 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1646 { 1647 int val; 1648 1649 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1650 val = phy_read(phydev, 0x13); 1651 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1652 1653 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1654 } 1655 1656 /* On internal PHY's MMD reads over C22 always return 0. 1657 * Check a MMD register which is known to be non-zero. 1658 */ 1659 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1660 { 1661 int val; 1662 1663 phy_lock_mdio_bus(phydev); 1664 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1665 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1666 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1667 val = __phy_read(phydev, MII_MMD_DATA); 1668 phy_unlock_mdio_bus(phydev); 1669 1670 return val > 0; 1671 } 1672 1673 static int rtlgen_match_phy_device(struct phy_device *phydev, 1674 const struct phy_driver *phydrv) 1675 { 1676 return phydev->phy_id == RTL_GENERIC_PHYID && 1677 !rtlgen_supports_2_5gbps(phydev); 1678 } 1679 1680 static int rtl8226_match_phy_device(struct phy_device *phydev, 1681 const struct phy_driver *phydrv) 1682 { 1683 return phydev->phy_id == RTL_GENERIC_PHYID && 1684 rtlgen_supports_2_5gbps(phydev) && 1685 rtlgen_supports_mmd(phydev); 1686 } 1687 1688 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1689 bool is_c45) 1690 { 1691 if (phydev->is_c45) 1692 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1693 else 1694 return !is_c45 && (id == phydev->phy_id); 1695 } 1696 1697 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1698 const struct phy_driver *phydrv) 1699 { 1700 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1701 } 1702 1703 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1704 const struct phy_driver *phydrv) 1705 { 1706 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1707 } 1708 1709 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1710 const struct phy_driver *phydrv) 1711 { 1712 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1713 } 1714 1715 static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev, 1716 const struct phy_driver *phydrv) 1717 { 1718 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1719 } 1720 1721 static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev, 1722 const struct phy_driver *phydrv) 1723 { 1724 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true); 1725 } 1726 1727 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1728 const struct phy_driver *phydrv) 1729 { 1730 if (phydev->is_c45) 1731 return false; 1732 1733 switch (phydev->phy_id) { 1734 case RTL_GENERIC_PHYID: 1735 case RTL_8221B: 1736 case RTL_8251B: 1737 case RTL_8261C: 1738 case 0x001cc841: 1739 break; 1740 default: 1741 return false; 1742 } 1743 1744 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1745 } 1746 1747 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1748 const struct phy_driver *phydrv) 1749 { 1750 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1751 } 1752 1753 static int rtlgen_resume(struct phy_device *phydev) 1754 { 1755 int ret = genphy_resume(phydev); 1756 1757 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1758 msleep(20); 1759 1760 return ret; 1761 } 1762 1763 static int rtlgen_c45_resume(struct phy_device *phydev) 1764 { 1765 int ret = genphy_c45_pma_resume(phydev); 1766 1767 msleep(20); 1768 1769 return ret; 1770 } 1771 1772 static int rtl9000a_config_init(struct phy_device *phydev) 1773 { 1774 phydev->autoneg = AUTONEG_DISABLE; 1775 phydev->speed = SPEED_100; 1776 phydev->duplex = DUPLEX_FULL; 1777 1778 return 0; 1779 } 1780 1781 static int rtl9000a_config_aneg(struct phy_device *phydev) 1782 { 1783 int ret; 1784 u16 ctl = 0; 1785 1786 switch (phydev->master_slave_set) { 1787 case MASTER_SLAVE_CFG_MASTER_FORCE: 1788 ctl |= CTL1000_AS_MASTER; 1789 break; 1790 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1791 break; 1792 case MASTER_SLAVE_CFG_UNKNOWN: 1793 case MASTER_SLAVE_CFG_UNSUPPORTED: 1794 return 0; 1795 default: 1796 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1797 return -EOPNOTSUPP; 1798 } 1799 1800 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1801 if (ret == 1) 1802 ret = genphy_soft_reset(phydev); 1803 1804 return ret; 1805 } 1806 1807 static int rtl9000a_read_status(struct phy_device *phydev) 1808 { 1809 int ret; 1810 1811 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1812 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1813 1814 ret = genphy_update_link(phydev); 1815 if (ret) 1816 return ret; 1817 1818 ret = phy_read(phydev, MII_CTRL1000); 1819 if (ret < 0) 1820 return ret; 1821 if (ret & CTL1000_AS_MASTER) 1822 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1823 else 1824 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1825 1826 ret = phy_read(phydev, MII_STAT1000); 1827 if (ret < 0) 1828 return ret; 1829 if (ret & LPA_1000MSRES) 1830 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1831 else 1832 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1833 1834 return 0; 1835 } 1836 1837 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1838 { 1839 int err; 1840 1841 err = phy_read(phydev, RTL8211F_INSR); 1842 1843 return (err < 0) ? err : 0; 1844 } 1845 1846 static int rtl9000a_config_intr(struct phy_device *phydev) 1847 { 1848 u16 val; 1849 int err; 1850 1851 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1852 err = rtl9000a_ack_interrupt(phydev); 1853 if (err) 1854 return err; 1855 1856 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1857 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1858 } else { 1859 val = ~0; 1860 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1861 if (err) 1862 return err; 1863 1864 err = rtl9000a_ack_interrupt(phydev); 1865 } 1866 1867 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1868 } 1869 1870 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1871 { 1872 int irq_status; 1873 1874 irq_status = phy_read(phydev, RTL8211F_INSR); 1875 if (irq_status < 0) { 1876 phy_error(phydev); 1877 return IRQ_NONE; 1878 } 1879 1880 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1881 return IRQ_NONE; 1882 1883 phy_trigger_machine(phydev); 1884 1885 return IRQ_HANDLED; 1886 } 1887 1888 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 1889 { 1890 int err; 1891 1892 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 1893 1894 return (err < 0) ? err : 0; 1895 } 1896 1897 static int rtl8221b_config_intr(struct phy_device *phydev) 1898 { 1899 int err; 1900 1901 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1902 err = rtl8221b_ack_interrupt(phydev); 1903 if (err) 1904 return err; 1905 1906 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 1907 RTL8221B_VND2_INER_LINK_STATUS); 1908 } else { 1909 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1910 RTL8221B_VND2_INER, 0); 1911 if (err) 1912 return err; 1913 1914 err = rtl8221b_ack_interrupt(phydev); 1915 } 1916 1917 return err; 1918 } 1919 1920 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 1921 { 1922 int err; 1923 1924 err = rtl8221b_ack_interrupt(phydev); 1925 if (err) { 1926 phy_error(phydev); 1927 return IRQ_NONE; 1928 } 1929 1930 phy_trigger_machine(phydev); 1931 1932 return IRQ_HANDLED; 1933 } 1934 1935 static struct phy_driver realtek_drvs[] = { 1936 { 1937 PHY_ID_MATCH_EXACT(0x00008201), 1938 .name = "RTL8201CP Ethernet", 1939 .read_page = rtl821x_read_page, 1940 .write_page = rtl821x_write_page, 1941 }, { 1942 PHY_ID_MATCH_EXACT(0x001cc816), 1943 .name = "RTL8201F Fast Ethernet", 1944 .config_intr = &rtl8201_config_intr, 1945 .handle_interrupt = rtl8201_handle_interrupt, 1946 .suspend = genphy_suspend, 1947 .resume = genphy_resume, 1948 .read_page = rtl821x_read_page, 1949 .write_page = rtl821x_write_page, 1950 }, { 1951 PHY_ID_MATCH_MODEL(0x001cc880), 1952 .name = "RTL8208 Fast Ethernet", 1953 .read_mmd = genphy_read_mmd_unsupported, 1954 .write_mmd = genphy_write_mmd_unsupported, 1955 .suspend = genphy_suspend, 1956 .resume = genphy_resume, 1957 .read_page = rtl821x_read_page, 1958 .write_page = rtl821x_write_page, 1959 }, { 1960 PHY_ID_MATCH_EXACT(0x001cc910), 1961 .name = "RTL8211 Gigabit Ethernet", 1962 .config_aneg = rtl8211_config_aneg, 1963 .read_mmd = &genphy_read_mmd_unsupported, 1964 .write_mmd = &genphy_write_mmd_unsupported, 1965 .read_page = rtl821x_read_page, 1966 .write_page = rtl821x_write_page, 1967 }, { 1968 PHY_ID_MATCH_EXACT(0x001cc912), 1969 .name = "RTL8211B Gigabit Ethernet", 1970 .config_intr = &rtl8211b_config_intr, 1971 .handle_interrupt = rtl821x_handle_interrupt, 1972 .read_mmd = &genphy_read_mmd_unsupported, 1973 .write_mmd = &genphy_write_mmd_unsupported, 1974 .suspend = rtl8211b_suspend, 1975 .resume = rtl8211b_resume, 1976 .read_page = rtl821x_read_page, 1977 .write_page = rtl821x_write_page, 1978 }, { 1979 PHY_ID_MATCH_EXACT(0x001cc913), 1980 .name = "RTL8211C Gigabit Ethernet", 1981 .config_init = rtl8211c_config_init, 1982 .read_mmd = &genphy_read_mmd_unsupported, 1983 .write_mmd = &genphy_write_mmd_unsupported, 1984 .read_page = rtl821x_read_page, 1985 .write_page = rtl821x_write_page, 1986 }, { 1987 PHY_ID_MATCH_EXACT(0x001cc914), 1988 .name = "RTL8211DN Gigabit Ethernet", 1989 .config_intr = rtl8211e_config_intr, 1990 .handle_interrupt = rtl821x_handle_interrupt, 1991 .suspend = genphy_suspend, 1992 .resume = genphy_resume, 1993 .read_page = rtl821x_read_page, 1994 .write_page = rtl821x_write_page, 1995 }, { 1996 PHY_ID_MATCH_EXACT(0x001cc915), 1997 .name = "RTL8211E Gigabit Ethernet", 1998 .config_init = &rtl8211e_config_init, 1999 .config_intr = &rtl8211e_config_intr, 2000 .handle_interrupt = rtl821x_handle_interrupt, 2001 .suspend = genphy_suspend, 2002 .resume = genphy_resume, 2003 .read_page = rtl821x_read_page, 2004 .write_page = rtl821x_write_page, 2005 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2006 .led_hw_control_get = rtl8211e_led_hw_control_get, 2007 .led_hw_control_set = rtl8211e_led_hw_control_set, 2008 }, { 2009 PHY_ID_MATCH_EXACT(0x001cc916), 2010 .name = "RTL8211F Gigabit Ethernet", 2011 .probe = rtl8211f_probe, 2012 .config_init = &rtl8211f_config_init, 2013 .read_status = rtlgen_read_status, 2014 .config_intr = &rtl8211f_config_intr, 2015 .handle_interrupt = rtl8211f_handle_interrupt, 2016 .set_wol = rtl8211f_set_wol, 2017 .get_wol = rtl8211f_get_wol, 2018 .suspend = rtl8211f_suspend, 2019 .resume = rtl8211f_resume, 2020 .read_page = rtl821x_read_page, 2021 .write_page = rtl821x_write_page, 2022 .flags = PHY_ALWAYS_CALL_SUSPEND, 2023 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2024 .led_hw_control_get = rtl8211f_led_hw_control_get, 2025 .led_hw_control_set = rtl8211f_led_hw_control_set, 2026 }, { 2027 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2028 .name = "RTL8211F-VD Gigabit Ethernet", 2029 .probe = rtl821x_probe, 2030 .config_init = &rtl8211f_config_init, 2031 .read_status = rtlgen_read_status, 2032 .config_intr = &rtl8211f_config_intr, 2033 .handle_interrupt = rtl8211f_handle_interrupt, 2034 .suspend = rtl821x_suspend, 2035 .resume = rtl821x_resume, 2036 .read_page = rtl821x_read_page, 2037 .write_page = rtl821x_write_page, 2038 .flags = PHY_ALWAYS_CALL_SUSPEND, 2039 }, { 2040 .name = "Generic FE-GE Realtek PHY", 2041 .match_phy_device = rtlgen_match_phy_device, 2042 .read_status = rtlgen_read_status, 2043 .suspend = genphy_suspend, 2044 .resume = rtlgen_resume, 2045 .read_page = rtl821x_read_page, 2046 .write_page = rtl821x_write_page, 2047 .read_mmd = rtlgen_read_mmd, 2048 .write_mmd = rtlgen_write_mmd, 2049 }, { 2050 .name = "RTL8226 2.5Gbps PHY", 2051 .match_phy_device = rtl8226_match_phy_device, 2052 .get_features = rtl822x_get_features, 2053 .config_aneg = rtl822x_config_aneg, 2054 .read_status = rtl822x_read_status, 2055 .suspend = genphy_suspend, 2056 .resume = rtlgen_resume, 2057 .read_page = rtl821x_read_page, 2058 .write_page = rtl821x_write_page, 2059 }, { 2060 .match_phy_device = rtl8221b_match_phy_device, 2061 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2062 .get_features = rtl822x_get_features, 2063 .config_aneg = rtl822x_config_aneg, 2064 .config_init = rtl822xb_config_init, 2065 .get_rate_matching = rtl822xb_get_rate_matching, 2066 .read_status = rtl822xb_read_status, 2067 .suspend = genphy_suspend, 2068 .resume = rtlgen_resume, 2069 .read_page = rtl821x_read_page, 2070 .write_page = rtl821x_write_page, 2071 }, { 2072 PHY_ID_MATCH_EXACT(0x001cc838), 2073 .name = "RTL8226-CG 2.5Gbps PHY", 2074 .soft_reset = rtl822x_c45_soft_reset, 2075 .get_features = rtl822x_c45_get_features, 2076 .config_aneg = rtl822x_c45_config_aneg, 2077 .config_init = rtl822x_config_init, 2078 .read_status = rtl822xb_c45_read_status, 2079 .suspend = genphy_c45_pma_suspend, 2080 .resume = rtlgen_c45_resume, 2081 }, { 2082 PHY_ID_MATCH_EXACT(0x001cc848), 2083 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2084 .get_features = rtl822x_get_features, 2085 .config_aneg = rtl822x_config_aneg, 2086 .config_init = rtl822xb_config_init, 2087 .get_rate_matching = rtl822xb_get_rate_matching, 2088 .read_status = rtl822xb_read_status, 2089 .suspend = genphy_suspend, 2090 .resume = rtlgen_resume, 2091 .read_page = rtl821x_read_page, 2092 .write_page = rtl821x_write_page, 2093 }, { 2094 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 2095 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 2096 .probe = rtl822x_probe, 2097 .get_features = rtl822x_get_features, 2098 .config_aneg = rtl822x_config_aneg, 2099 .config_init = rtl822xb_config_init, 2100 .get_rate_matching = rtl822xb_get_rate_matching, 2101 .read_status = rtl822xb_read_status, 2102 .suspend = genphy_suspend, 2103 .resume = rtlgen_resume, 2104 .read_page = rtl821x_read_page, 2105 .write_page = rtl821x_write_page, 2106 }, { 2107 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 2108 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 2109 .config_intr = rtl8221b_config_intr, 2110 .handle_interrupt = rtl8221b_handle_interrupt, 2111 .probe = rtl822x_probe, 2112 .config_init = rtl822xb_config_init, 2113 .get_rate_matching = rtl822xb_get_rate_matching, 2114 .get_features = rtl822x_c45_get_features, 2115 .config_aneg = rtl822x_c45_config_aneg, 2116 .read_status = rtl822xb_c45_read_status, 2117 .suspend = genphy_c45_pma_suspend, 2118 .resume = rtlgen_c45_resume, 2119 }, { 2120 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device, 2121 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 2122 .probe = rtl822x_probe, 2123 .get_features = rtl822x_get_features, 2124 .config_aneg = rtl822x_config_aneg, 2125 .config_init = rtl822xb_config_init, 2126 .get_rate_matching = rtl822xb_get_rate_matching, 2127 .read_status = rtl822xb_read_status, 2128 .suspend = genphy_suspend, 2129 .resume = rtlgen_resume, 2130 .read_page = rtl821x_read_page, 2131 .write_page = rtl821x_write_page, 2132 }, { 2133 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device, 2134 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)", 2135 .config_intr = rtl8221b_config_intr, 2136 .handle_interrupt = rtl8221b_handle_interrupt, 2137 .probe = rtl822x_probe, 2138 .config_init = rtl822xb_config_init, 2139 .get_rate_matching = rtl822xb_get_rate_matching, 2140 .get_features = rtl822x_c45_get_features, 2141 .config_aneg = rtl822x_c45_config_aneg, 2142 .read_status = rtl822xb_c45_read_status, 2143 .suspend = genphy_c45_pma_suspend, 2144 .resume = rtlgen_c45_resume, 2145 }, { 2146 .match_phy_device = rtl8251b_c45_match_phy_device, 2147 .name = "RTL8251B 5Gbps PHY", 2148 .probe = rtl822x_probe, 2149 .get_features = rtl822x_get_features, 2150 .config_aneg = rtl822x_config_aneg, 2151 .read_status = rtl822x_read_status, 2152 .suspend = genphy_suspend, 2153 .resume = rtlgen_resume, 2154 .read_page = rtl821x_read_page, 2155 .write_page = rtl821x_write_page, 2156 }, { 2157 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2158 .name = "Realtek Internal NBASE-T PHY", 2159 .flags = PHY_IS_INTERNAL, 2160 .probe = rtl822x_probe, 2161 .get_features = rtl822x_get_features, 2162 .config_aneg = rtl822x_config_aneg, 2163 .read_status = rtl822x_read_status, 2164 .suspend = genphy_suspend, 2165 .resume = rtlgen_resume, 2166 .read_page = rtl821x_read_page, 2167 .write_page = rtl821x_write_page, 2168 .read_mmd = rtl822x_read_mmd, 2169 .write_mmd = rtl822x_write_mmd, 2170 }, { 2171 PHY_ID_MATCH_EXACT(0x001ccad0), 2172 .name = "RTL8224 2.5Gbps PHY", 2173 .flags = PHY_POLL_CABLE_TEST, 2174 .get_features = rtl822x_c45_get_features, 2175 .config_aneg = rtl822x_c45_config_aneg, 2176 .read_status = rtl822x_c45_read_status, 2177 .suspend = genphy_c45_pma_suspend, 2178 .resume = rtlgen_c45_resume, 2179 .cable_test_start = rtl8224_cable_test_start, 2180 .cable_test_get_status = rtl8224_cable_test_get_status, 2181 }, { 2182 PHY_ID_MATCH_EXACT(0x001cc961), 2183 .name = "RTL8366RB Gigabit Ethernet", 2184 .config_init = &rtl8366rb_config_init, 2185 /* These interrupts are handled by the irq controller 2186 * embedded inside the RTL8366RB, they get unmasked when the 2187 * irq is requested and ACKed by reading the status register, 2188 * which is done by the irqchip code. 2189 */ 2190 .config_intr = genphy_no_config_intr, 2191 .handle_interrupt = genphy_handle_interrupt_no_ack, 2192 .suspend = genphy_suspend, 2193 .resume = genphy_resume, 2194 }, { 2195 PHY_ID_MATCH_EXACT(0x001ccb00), 2196 .name = "RTL9000AA_RTL9000AN Ethernet", 2197 .features = PHY_BASIC_T1_FEATURES, 2198 .config_init = rtl9000a_config_init, 2199 .config_aneg = rtl9000a_config_aneg, 2200 .read_status = rtl9000a_read_status, 2201 .config_intr = rtl9000a_config_intr, 2202 .handle_interrupt = rtl9000a_handle_interrupt, 2203 .suspend = genphy_suspend, 2204 .resume = genphy_resume, 2205 .read_page = rtl821x_read_page, 2206 .write_page = rtl821x_write_page, 2207 }, { 2208 PHY_ID_MATCH_EXACT(0x001cc942), 2209 .name = "RTL8365MB-VC Gigabit Ethernet", 2210 /* Interrupt handling analogous to RTL8366RB */ 2211 .config_intr = genphy_no_config_intr, 2212 .handle_interrupt = genphy_handle_interrupt_no_ack, 2213 .suspend = genphy_suspend, 2214 .resume = genphy_resume, 2215 }, { 2216 PHY_ID_MATCH_EXACT(0x001cc960), 2217 .name = "RTL8366S Gigabit Ethernet", 2218 .suspend = genphy_suspend, 2219 .resume = genphy_resume, 2220 .read_mmd = genphy_read_mmd_unsupported, 2221 .write_mmd = genphy_write_mmd_unsupported, 2222 }, 2223 }; 2224 2225 module_phy_driver(realtek_drvs); 2226 2227 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2228 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2229 { } 2230 }; 2231 2232 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2233