1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/pm_wakeirq.h> 14 #include <linux/netdevice.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/clk.h> 18 #include <linux/string_choices.h> 19 20 #include "realtek.h" 21 22 #define RTL8201F_IER 0x13 23 24 #define RTL8201F_ISR 0x1e 25 #define RTL8201F_ISR_ANERR BIT(15) 26 #define RTL8201F_ISR_DUPLEX BIT(13) 27 #define RTL8201F_ISR_LINK BIT(11) 28 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 29 RTL8201F_ISR_DUPLEX | \ 30 RTL8201F_ISR_LINK) 31 32 #define RTL821x_INER 0x12 33 #define RTL8211B_INER_INIT 0x6400 34 #define RTL8211E_INER_LINK_STATUS BIT(10) 35 #define RTL8211F_INER_PME BIT(7) 36 #define RTL8211F_INER_LINK_STATUS BIT(4) 37 38 #define RTL821x_INSR 0x13 39 40 #define RTL821x_EXT_PAGE_SELECT 0x1e 41 42 #define RTL821x_PAGE_SELECT 0x1f 43 #define RTL821x_SET_EXT_PAGE 0x07 44 45 /* RTL8211E extension page 44/0x2c */ 46 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 47 #define RTL8211E_LEDCR1 0x1a 48 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 49 #define RTL8211E_LEDCR1_MASK BIT(4) 50 #define RTL8211E_LEDCR1_SHIFT 1 51 52 #define RTL8211E_LEDCR2 0x1c 53 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 54 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 55 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 56 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 57 #define RTL8211E_LEDCR2_SHIFT 4 58 59 /* RTL8211E extension page 164/0xa4 */ 60 #define RTL8211E_RGMII_EXT_PAGE 0xa4 61 #define RTL8211E_RGMII_DELAY 0x1c 62 #define RTL8211E_CTRL_DELAY BIT(13) 63 #define RTL8211E_TX_DELAY BIT(12) 64 #define RTL8211E_RX_DELAY BIT(11) 65 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 66 67 /* RTL8211F PHY configuration */ 68 #define RTL8211F_PHYCR_PAGE 0xa43 69 #define RTL8211F_PHYCR1 0x18 70 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 71 #define RTL8211F_ALDPS_ENABLE BIT(2) 72 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 73 74 #define RTL8211F_PHYCR2 0x19 75 #define RTL8211F_CLKOUT_EN BIT(0) 76 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 77 78 #define RTL8211F_INSR_PAGE 0xa43 79 #define RTL8211F_INSR 0x1d 80 81 /* RTL8211F LED configuration */ 82 #define RTL8211F_LEDCR_PAGE 0xd04 83 #define RTL8211F_LEDCR 0x10 84 #define RTL8211F_LEDCR_MODE BIT(15) 85 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 86 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 87 #define RTL8211F_LEDCR_LINK_100 BIT(1) 88 #define RTL8211F_LEDCR_LINK_10 BIT(0) 89 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 90 #define RTL8211F_LEDCR_SHIFT 5 91 92 /* RTL8211F RGMII configuration */ 93 #define RTL8211F_RGMII_PAGE 0xd08 94 95 #define RTL8211F_TXCR 0x11 96 #define RTL8211F_TX_DELAY BIT(8) 97 98 #define RTL8211F_RXCR 0x15 99 #define RTL8211F_RX_DELAY BIT(3) 100 101 /* RTL8211F WOL settings */ 102 #define RTL8211F_WOL_PAGE 0xd8a 103 #define RTL8211F_WOL_SETTINGS_EVENTS 16 104 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 105 #define RTL8211F_WOL_RST_RMSQ 17 106 #define RTL8211F_WOL_RG_RSTB BIT(15) 107 #define RTL8211F_WOL_RMSQ 0x1fff 108 109 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 110 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 111 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 112 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 113 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 114 115 #define RTL822X_VND1_SERDES_OPTION 0x697a 116 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 117 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 118 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 119 120 #define RTL822X_VND1_SERDES_CTRL3 0x7580 121 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 122 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 124 125 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 126 * is set, they cannot be accessed by C45-over-C22. 127 */ 128 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 129 130 #define RTL8366RB_POWER_SAVE 0x15 131 #define RTL8366RB_POWER_SAVE_ON BIT(12) 132 133 #define RTL9000A_GINMR 0x14 134 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 135 136 #define RTL_VND2_PHYSR 0xa434 137 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 138 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 139 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 140 #define RTL_VND2_PHYSR_MASTER BIT(11) 141 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 142 143 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 144 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 145 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 146 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 147 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 148 #define RTL_MDIO_PMA_SPEED 0xa616 149 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 150 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 151 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 152 153 #define RTL_GENERIC_PHYID 0x001cc800 154 #define RTL_8211FVD_PHYID 0x001cc878 155 #define RTL_8221B 0x001cc840 156 #define RTL_8221B_VB_CG 0x001cc849 157 #define RTL_8221B_VN_CG 0x001cc84a 158 #define RTL_8251B 0x001cc862 159 #define RTL_8261C 0x001cc890 160 161 /* RTL8211E and RTL8211F support up to three LEDs */ 162 #define RTL8211x_LED_COUNT 3 163 164 MODULE_DESCRIPTION("Realtek PHY driver"); 165 MODULE_AUTHOR("Johnson Leung"); 166 MODULE_LICENSE("GPL"); 167 168 struct rtl821x_priv { 169 u16 phycr1; 170 u16 phycr2; 171 bool has_phycr2; 172 struct clk *clk; 173 /* rtl8211f */ 174 u16 iner; 175 }; 176 177 static int rtl821x_read_page(struct phy_device *phydev) 178 { 179 return __phy_read(phydev, RTL821x_PAGE_SELECT); 180 } 181 182 static int rtl821x_write_page(struct phy_device *phydev, int page) 183 { 184 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 185 } 186 187 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 188 u32 regnum) 189 { 190 int oldpage, ret = 0; 191 192 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 193 if (oldpage >= 0) { 194 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 195 if (ret == 0) 196 ret = __phy_read(phydev, regnum); 197 } 198 199 return phy_restore_page(phydev, oldpage, ret); 200 } 201 202 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 203 u32 regnum, u16 mask, u16 set) 204 { 205 int oldpage, ret = 0; 206 207 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 208 if (oldpage >= 0) { 209 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 210 if (ret == 0) 211 ret = __phy_modify(phydev, regnum, mask, set); 212 } 213 214 return phy_restore_page(phydev, oldpage, ret); 215 } 216 217 static int rtl821x_probe(struct phy_device *phydev) 218 { 219 struct device *dev = &phydev->mdio.dev; 220 struct rtl821x_priv *priv; 221 u32 phy_id = phydev->drv->phy_id; 222 int ret; 223 224 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 225 if (!priv) 226 return -ENOMEM; 227 228 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 229 if (IS_ERR(priv->clk)) 230 return dev_err_probe(dev, PTR_ERR(priv->clk), 231 "failed to get phy clock\n"); 232 233 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 234 if (ret < 0) 235 return ret; 236 237 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 238 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 239 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 240 241 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 242 if (priv->has_phycr2) { 243 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 244 if (ret < 0) 245 return ret; 246 247 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 248 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 249 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 250 } 251 252 phydev->priv = priv; 253 254 return 0; 255 } 256 257 static int rtl8211f_probe(struct phy_device *phydev) 258 { 259 struct device *dev = &phydev->mdio.dev; 260 int ret; 261 262 ret = rtl821x_probe(phydev); 263 if (ret < 0) 264 return ret; 265 266 /* Disable all PME events */ 267 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 268 RTL8211F_WOL_SETTINGS_EVENTS, 0); 269 if (ret < 0) 270 return ret; 271 272 /* Mark this PHY as wakeup capable and register the interrupt as a 273 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 274 * and the interrupt is valid. 275 */ 276 if (device_property_read_bool(dev, "wakeup-source") && 277 phy_interrupt_is_valid(phydev)) { 278 device_set_wakeup_capable(dev, true); 279 devm_pm_set_wake_irq(dev, phydev->irq); 280 } 281 282 return ret; 283 } 284 285 static int rtl8201_ack_interrupt(struct phy_device *phydev) 286 { 287 int err; 288 289 err = phy_read(phydev, RTL8201F_ISR); 290 291 return (err < 0) ? err : 0; 292 } 293 294 static int rtl821x_ack_interrupt(struct phy_device *phydev) 295 { 296 int err; 297 298 err = phy_read(phydev, RTL821x_INSR); 299 300 return (err < 0) ? err : 0; 301 } 302 303 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 304 { 305 int err; 306 307 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 308 309 return (err < 0) ? err : 0; 310 } 311 312 static int rtl8201_config_intr(struct phy_device *phydev) 313 { 314 u16 val; 315 int err; 316 317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 318 err = rtl8201_ack_interrupt(phydev); 319 if (err) 320 return err; 321 322 val = BIT(13) | BIT(12) | BIT(11); 323 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 324 } else { 325 val = 0; 326 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 327 if (err) 328 return err; 329 330 err = rtl8201_ack_interrupt(phydev); 331 } 332 333 return err; 334 } 335 336 static int rtl8211b_config_intr(struct phy_device *phydev) 337 { 338 int err; 339 340 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 341 err = rtl821x_ack_interrupt(phydev); 342 if (err) 343 return err; 344 345 err = phy_write(phydev, RTL821x_INER, 346 RTL8211B_INER_INIT); 347 } else { 348 err = phy_write(phydev, RTL821x_INER, 0); 349 if (err) 350 return err; 351 352 err = rtl821x_ack_interrupt(phydev); 353 } 354 355 return err; 356 } 357 358 static int rtl8211e_config_intr(struct phy_device *phydev) 359 { 360 int err; 361 362 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 363 err = rtl821x_ack_interrupt(phydev); 364 if (err) 365 return err; 366 367 err = phy_write(phydev, RTL821x_INER, 368 RTL8211E_INER_LINK_STATUS); 369 } else { 370 err = phy_write(phydev, RTL821x_INER, 0); 371 if (err) 372 return err; 373 374 err = rtl821x_ack_interrupt(phydev); 375 } 376 377 return err; 378 } 379 380 static int rtl8211f_config_intr(struct phy_device *phydev) 381 { 382 struct rtl821x_priv *priv = phydev->priv; 383 u16 val; 384 int err; 385 386 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 387 err = rtl8211f_ack_interrupt(phydev); 388 if (err) 389 return err; 390 391 val = RTL8211F_INER_LINK_STATUS; 392 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 393 if (err == 0) 394 priv->iner = val; 395 } else { 396 priv->iner = val = 0; 397 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 398 if (err) 399 return err; 400 401 err = rtl8211f_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 408 { 409 int irq_status; 410 411 irq_status = phy_read(phydev, RTL8201F_ISR); 412 if (irq_status < 0) { 413 phy_error(phydev); 414 return IRQ_NONE; 415 } 416 417 if (!(irq_status & RTL8201F_ISR_MASK)) 418 return IRQ_NONE; 419 420 phy_trigger_machine(phydev); 421 422 return IRQ_HANDLED; 423 } 424 425 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 426 { 427 int irq_status, irq_enabled; 428 429 irq_status = phy_read(phydev, RTL821x_INSR); 430 if (irq_status < 0) { 431 phy_error(phydev); 432 return IRQ_NONE; 433 } 434 435 irq_enabled = phy_read(phydev, RTL821x_INER); 436 if (irq_enabled < 0) { 437 phy_error(phydev); 438 return IRQ_NONE; 439 } 440 441 if (!(irq_status & irq_enabled)) 442 return IRQ_NONE; 443 444 phy_trigger_machine(phydev); 445 446 return IRQ_HANDLED; 447 } 448 449 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 450 { 451 int irq_status; 452 453 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 454 if (irq_status < 0) { 455 phy_error(phydev); 456 return IRQ_NONE; 457 } 458 459 if (irq_status & RTL8211F_INER_LINK_STATUS) { 460 phy_trigger_machine(phydev); 461 return IRQ_HANDLED; 462 } 463 464 if (irq_status & RTL8211F_INER_PME) { 465 pm_wakeup_event(&phydev->mdio.dev, 0); 466 return IRQ_HANDLED; 467 } 468 469 return IRQ_NONE; 470 } 471 472 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 473 { 474 int wol_events; 475 476 /* If the PHY is not capable of waking the system, then WoL can not 477 * be supported. 478 */ 479 if (!device_can_wakeup(&dev->mdio.dev)) { 480 wol->supported = 0; 481 return; 482 } 483 484 wol->supported = WAKE_MAGIC; 485 486 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 487 if (wol_events < 0) 488 return; 489 490 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 491 wol->wolopts = WAKE_MAGIC; 492 } 493 494 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 495 { 496 const u8 *mac_addr = dev->attached_dev->dev_addr; 497 int oldpage; 498 499 if (!device_can_wakeup(&dev->mdio.dev)) 500 return -EOPNOTSUPP; 501 502 oldpage = phy_save_page(dev); 503 if (oldpage < 0) 504 goto err; 505 506 if (wol->wolopts & WAKE_MAGIC) { 507 /* Store the device address for the magic packet */ 508 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 509 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 510 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 511 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 512 513 /* Enable magic packet matching */ 514 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 515 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 516 /* Set the maximum packet size, and assert WoL reset */ 517 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 518 } else { 519 /* Disable magic packet matching */ 520 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 521 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 522 523 /* Place WoL in reset */ 524 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 525 RTL8211F_WOL_RG_RSTB); 526 } 527 528 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 529 530 err: 531 return phy_restore_page(dev, oldpage, 0); 532 } 533 534 static int rtl8211_config_aneg(struct phy_device *phydev) 535 { 536 int ret; 537 538 ret = genphy_config_aneg(phydev); 539 if (ret < 0) 540 return ret; 541 542 /* Quirk was copied from vendor driver. Unfortunately it includes no 543 * description of the magic numbers. 544 */ 545 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 546 phy_write(phydev, 0x17, 0x2138); 547 phy_write(phydev, 0x0e, 0x0260); 548 } else { 549 phy_write(phydev, 0x17, 0x2108); 550 phy_write(phydev, 0x0e, 0x0000); 551 } 552 553 return 0; 554 } 555 556 static int rtl8211c_config_init(struct phy_device *phydev) 557 { 558 /* RTL8211C has an issue when operating in Gigabit slave mode */ 559 return phy_set_bits(phydev, MII_CTRL1000, 560 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 561 } 562 563 static int rtl8211f_config_init(struct phy_device *phydev) 564 { 565 struct rtl821x_priv *priv = phydev->priv; 566 struct device *dev = &phydev->mdio.dev; 567 u16 val_txdly, val_rxdly; 568 int ret; 569 570 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 571 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 572 priv->phycr1); 573 if (ret < 0) { 574 dev_err(dev, "aldps mode configuration failed: %pe\n", 575 ERR_PTR(ret)); 576 return ret; 577 } 578 579 switch (phydev->interface) { 580 case PHY_INTERFACE_MODE_RGMII: 581 val_txdly = 0; 582 val_rxdly = 0; 583 break; 584 585 case PHY_INTERFACE_MODE_RGMII_RXID: 586 val_txdly = 0; 587 val_rxdly = RTL8211F_RX_DELAY; 588 break; 589 590 case PHY_INTERFACE_MODE_RGMII_TXID: 591 val_txdly = RTL8211F_TX_DELAY; 592 val_rxdly = 0; 593 break; 594 595 case PHY_INTERFACE_MODE_RGMII_ID: 596 val_txdly = RTL8211F_TX_DELAY; 597 val_rxdly = RTL8211F_RX_DELAY; 598 break; 599 600 default: /* the rest of the modes imply leaving delay as is. */ 601 return 0; 602 } 603 604 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 605 RTL8211F_TXCR, RTL8211F_TX_DELAY, 606 val_txdly); 607 if (ret < 0) { 608 dev_err(dev, "Failed to update the TX delay register\n"); 609 return ret; 610 } else if (ret) { 611 dev_dbg(dev, 612 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 613 str_enable_disable(val_txdly)); 614 } else { 615 dev_dbg(dev, 616 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 617 str_enabled_disabled(val_txdly)); 618 } 619 620 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 621 RTL8211F_RXCR, RTL8211F_RX_DELAY, 622 val_rxdly); 623 if (ret < 0) { 624 dev_err(dev, "Failed to update the RX delay register\n"); 625 return ret; 626 } else if (ret) { 627 dev_dbg(dev, 628 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 629 str_enable_disable(val_rxdly)); 630 } else { 631 dev_dbg(dev, 632 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 633 str_enabled_disabled(val_rxdly)); 634 } 635 636 if (!priv->has_phycr2) 637 return 0; 638 639 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 640 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 641 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 642 if (ret) 643 return ret; 644 645 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 646 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 647 priv->phycr2); 648 if (ret < 0) { 649 dev_err(dev, "clkout configuration failed: %pe\n", 650 ERR_PTR(ret)); 651 return ret; 652 } 653 654 return genphy_soft_reset(phydev); 655 } 656 657 static int rtl821x_suspend(struct phy_device *phydev) 658 { 659 struct rtl821x_priv *priv = phydev->priv; 660 int ret = 0; 661 662 if (!phydev->wol_enabled) { 663 ret = genphy_suspend(phydev); 664 665 if (ret) 666 return ret; 667 668 clk_disable_unprepare(priv->clk); 669 } 670 671 return ret; 672 } 673 674 static int rtl8211f_suspend(struct phy_device *phydev) 675 { 676 u16 wol_rst; 677 int ret; 678 679 ret = rtl821x_suspend(phydev); 680 if (ret < 0) 681 return ret; 682 683 /* If a PME event is enabled, then configure the interrupt for 684 * PME events only, disabling link interrupt. We avoid switching 685 * to PMEB mode as we don't have a status bit for that. 686 */ 687 if (device_may_wakeup(&phydev->mdio.dev)) { 688 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 689 RTL8211F_INER_PME); 690 if (ret < 0) 691 goto err; 692 693 /* Read the INSR to clear any pending interrupt */ 694 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 695 696 /* Reset the WoL to ensure that an event is picked up. 697 * Unless we do this, even if we receive another packet, 698 * we may not have a PME interrupt raised. 699 */ 700 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 701 RTL8211F_WOL_RST_RMSQ); 702 if (ret < 0) 703 goto err; 704 705 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 706 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 707 RTL8211F_WOL_RST_RMSQ, wol_rst); 708 if (ret < 0) 709 goto err; 710 711 wol_rst |= RTL8211F_WOL_RG_RSTB; 712 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 713 RTL8211F_WOL_RST_RMSQ, wol_rst); 714 } 715 716 err: 717 return ret; 718 } 719 720 static int rtl821x_resume(struct phy_device *phydev) 721 { 722 struct rtl821x_priv *priv = phydev->priv; 723 int ret; 724 725 if (!phydev->wol_enabled) 726 clk_prepare_enable(priv->clk); 727 728 ret = genphy_resume(phydev); 729 if (ret < 0) 730 return ret; 731 732 msleep(20); 733 734 return 0; 735 } 736 737 static int rtl8211f_resume(struct phy_device *phydev) 738 { 739 struct rtl821x_priv *priv = phydev->priv; 740 int ret; 741 742 ret = rtl821x_resume(phydev); 743 if (ret < 0) 744 return ret; 745 746 /* If the device was programmed for a PME event, restore the interrupt 747 * enable so phylib can receive link state interrupts. 748 */ 749 if (device_may_wakeup(&phydev->mdio.dev)) 750 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 751 752 return ret; 753 } 754 755 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 756 unsigned long rules) 757 { 758 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 759 BIT(TRIGGER_NETDEV_LINK_10) | 760 BIT(TRIGGER_NETDEV_LINK_100) | 761 BIT(TRIGGER_NETDEV_LINK_1000) | 762 BIT(TRIGGER_NETDEV_RX) | 763 BIT(TRIGGER_NETDEV_TX); 764 765 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 766 * - Link: Configurable subset of 10/100/1000 link rates 767 * - Active: Blink on activity, RX or TX is not differentiated 768 * The Active option has two modes, A and B: 769 * - A: Link and Active indication at configurable, but matching, 770 * subset of 10/100/1000 link rates 771 * - B: Link indication at configurable subset of 10/100/1000 link 772 * rates and Active indication always at all three 10+100+1000 773 * link rates. 774 * This code currently uses mode B only. 775 * 776 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 777 */ 778 779 if (index >= RTL8211x_LED_COUNT) 780 return -EINVAL; 781 782 /* Filter out any other unsupported triggers. */ 783 if (rules & ~mask) 784 return -EOPNOTSUPP; 785 786 /* RX and TX are not differentiated, either both are set or not set. */ 787 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 788 return -EOPNOTSUPP; 789 790 return 0; 791 } 792 793 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 794 unsigned long *rules) 795 { 796 int val; 797 798 if (index >= RTL8211x_LED_COUNT) 799 return -EINVAL; 800 801 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 802 if (val < 0) 803 return val; 804 805 val >>= RTL8211F_LEDCR_SHIFT * index; 806 val &= RTL8211F_LEDCR_MASK; 807 808 if (val & RTL8211F_LEDCR_LINK_10) 809 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 810 811 if (val & RTL8211F_LEDCR_LINK_100) 812 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 813 814 if (val & RTL8211F_LEDCR_LINK_1000) 815 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 816 817 if ((val & RTL8211F_LEDCR_LINK_10) && 818 (val & RTL8211F_LEDCR_LINK_100) && 819 (val & RTL8211F_LEDCR_LINK_1000)) { 820 __set_bit(TRIGGER_NETDEV_LINK, rules); 821 } 822 823 if (val & RTL8211F_LEDCR_ACT_TXRX) { 824 __set_bit(TRIGGER_NETDEV_RX, rules); 825 __set_bit(TRIGGER_NETDEV_TX, rules); 826 } 827 828 return 0; 829 } 830 831 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 832 unsigned long rules) 833 { 834 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 835 u16 reg = 0; 836 837 if (index >= RTL8211x_LED_COUNT) 838 return -EINVAL; 839 840 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 841 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 842 reg |= RTL8211F_LEDCR_LINK_10; 843 } 844 845 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 846 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 847 reg |= RTL8211F_LEDCR_LINK_100; 848 } 849 850 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 851 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 852 reg |= RTL8211F_LEDCR_LINK_1000; 853 } 854 855 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 856 test_bit(TRIGGER_NETDEV_TX, &rules)) { 857 reg |= RTL8211F_LEDCR_ACT_TXRX; 858 } 859 860 reg <<= RTL8211F_LEDCR_SHIFT * index; 861 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 862 863 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 864 } 865 866 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 867 unsigned long *rules) 868 { 869 int ret; 870 u16 cr1, cr2; 871 872 if (index >= RTL8211x_LED_COUNT) 873 return -EINVAL; 874 875 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 876 RTL8211E_LEDCR1); 877 if (ret < 0) 878 return ret; 879 880 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 881 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 882 __set_bit(TRIGGER_NETDEV_RX, rules); 883 __set_bit(TRIGGER_NETDEV_TX, rules); 884 } 885 886 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 887 RTL8211E_LEDCR2); 888 if (ret < 0) 889 return ret; 890 891 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 892 if (cr2 & RTL8211E_LEDCR2_LINK_10) 893 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 894 895 if (cr2 & RTL8211E_LEDCR2_LINK_100) 896 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 897 898 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 899 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 900 901 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 902 (cr2 & RTL8211E_LEDCR2_LINK_100) && 903 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 904 __set_bit(TRIGGER_NETDEV_LINK, rules); 905 } 906 907 return ret; 908 } 909 910 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 911 unsigned long rules) 912 { 913 const u16 cr1mask = 914 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 915 const u16 cr2mask = 916 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 917 u16 cr1 = 0, cr2 = 0; 918 int ret; 919 920 if (index >= RTL8211x_LED_COUNT) 921 return -EINVAL; 922 923 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 924 test_bit(TRIGGER_NETDEV_TX, &rules)) { 925 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 926 } 927 928 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 929 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 930 RTL8211E_LEDCR1, cr1mask, cr1); 931 if (ret < 0) 932 return ret; 933 934 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 935 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 936 cr2 |= RTL8211E_LEDCR2_LINK_10; 937 } 938 939 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 940 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 941 cr2 |= RTL8211E_LEDCR2_LINK_100; 942 } 943 944 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 945 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 946 cr2 |= RTL8211E_LEDCR2_LINK_1000; 947 } 948 949 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 950 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 951 RTL8211E_LEDCR2, cr2mask, cr2); 952 953 return ret; 954 } 955 956 static int rtl8211e_config_init(struct phy_device *phydev) 957 { 958 u16 val; 959 960 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 961 switch (phydev->interface) { 962 case PHY_INTERFACE_MODE_RGMII: 963 val = RTL8211E_CTRL_DELAY | 0; 964 break; 965 case PHY_INTERFACE_MODE_RGMII_ID: 966 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 967 break; 968 case PHY_INTERFACE_MODE_RGMII_RXID: 969 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 970 break; 971 case PHY_INTERFACE_MODE_RGMII_TXID: 972 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 973 break; 974 default: /* the rest of the modes imply leaving delays as is. */ 975 return 0; 976 } 977 978 /* According to a sample driver there is a 0x1c config register on the 979 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 980 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 981 * The configuration register definition: 982 * 14 = reserved 983 * 13 = Force Tx RX Delay controlled by bit12 bit11, 984 * 12 = RX Delay, 11 = TX Delay 985 * 10:0 = Test && debug settings reserved by realtek 986 */ 987 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 988 RTL8211E_RGMII_DELAY, 989 RTL8211E_DELAY_MASK, val); 990 } 991 992 static int rtl8211b_suspend(struct phy_device *phydev) 993 { 994 phy_write(phydev, MII_MMD_DATA, BIT(9)); 995 996 return genphy_suspend(phydev); 997 } 998 999 static int rtl8211b_resume(struct phy_device *phydev) 1000 { 1001 phy_write(phydev, MII_MMD_DATA, 0); 1002 1003 return genphy_resume(phydev); 1004 } 1005 1006 static int rtl8366rb_config_init(struct phy_device *phydev) 1007 { 1008 int ret; 1009 1010 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1011 RTL8366RB_POWER_SAVE_ON); 1012 if (ret) { 1013 dev_err(&phydev->mdio.dev, 1014 "error enabling power management\n"); 1015 } 1016 1017 return ret; 1018 } 1019 1020 /* get actual speed to cover the downshift case */ 1021 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1022 { 1023 /* bit 3 1024 * 0: Half Duplex 1025 * 1: Full Duplex 1026 */ 1027 if (val & RTL_VND2_PHYSR_DUPLEX) 1028 phydev->duplex = DUPLEX_FULL; 1029 else 1030 phydev->duplex = DUPLEX_HALF; 1031 1032 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1033 case 0x0000: 1034 phydev->speed = SPEED_10; 1035 break; 1036 case 0x0010: 1037 phydev->speed = SPEED_100; 1038 break; 1039 case 0x0020: 1040 phydev->speed = SPEED_1000; 1041 break; 1042 case 0x0200: 1043 phydev->speed = SPEED_10000; 1044 break; 1045 case 0x0210: 1046 phydev->speed = SPEED_2500; 1047 break; 1048 case 0x0220: 1049 phydev->speed = SPEED_5000; 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 /* bit 11 1056 * 0: Slave Mode 1057 * 1: Master Mode 1058 */ 1059 if (phydev->speed >= 1000) { 1060 if (val & RTL_VND2_PHYSR_MASTER) 1061 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1062 else 1063 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1064 } else { 1065 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1066 } 1067 } 1068 1069 static int rtlgen_read_status(struct phy_device *phydev) 1070 { 1071 int ret, val; 1072 1073 ret = genphy_read_status(phydev); 1074 if (ret < 0) 1075 return ret; 1076 1077 if (!phydev->link) 1078 return 0; 1079 1080 val = phy_read_paged(phydev, 0xa43, 0x12); 1081 if (val < 0) 1082 return val; 1083 1084 rtlgen_decode_physr(phydev, val); 1085 1086 return 0; 1087 } 1088 1089 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1090 { 1091 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1092 } 1093 1094 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1095 { 1096 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1097 val); 1098 } 1099 1100 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1101 { 1102 int ret; 1103 1104 if (devnum == MDIO_MMD_VEND2) 1105 ret = rtlgen_read_vend2(phydev, regnum); 1106 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1107 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1108 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1109 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1110 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1111 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1112 else 1113 ret = -EOPNOTSUPP; 1114 1115 return ret; 1116 } 1117 1118 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1119 u16 val) 1120 { 1121 int ret; 1122 1123 if (devnum == MDIO_MMD_VEND2) 1124 ret = rtlgen_write_vend2(phydev, regnum, val); 1125 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1126 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1127 else 1128 ret = -EOPNOTSUPP; 1129 1130 return ret; 1131 } 1132 1133 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1134 { 1135 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1136 1137 if (ret != -EOPNOTSUPP) 1138 return ret; 1139 1140 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1141 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1142 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1143 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1144 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1145 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1146 1147 return ret; 1148 } 1149 1150 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1151 u16 val) 1152 { 1153 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1154 1155 if (ret != -EOPNOTSUPP) 1156 return ret; 1157 1158 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1159 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1160 1161 return ret; 1162 } 1163 1164 static int rtl822x_probe(struct phy_device *phydev) 1165 { 1166 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1167 phydev->phy_id != RTL_GENERIC_PHYID) 1168 return rtl822x_hwmon_init(phydev); 1169 1170 return 0; 1171 } 1172 1173 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1174 { 1175 bool has_2500, has_sgmii; 1176 u16 mode; 1177 int ret; 1178 1179 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1180 phydev->host_interfaces) || 1181 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1182 1183 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1184 phydev->host_interfaces) || 1185 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1186 1187 /* fill in possible interfaces */ 1188 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1189 has_2500); 1190 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1191 has_sgmii); 1192 1193 if (!has_2500 && !has_sgmii) 1194 return 0; 1195 1196 /* determine SerDes option mode */ 1197 if (has_2500 && !has_sgmii) { 1198 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1199 phydev->rate_matching = RATE_MATCH_PAUSE; 1200 } else { 1201 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1202 phydev->rate_matching = RATE_MATCH_NONE; 1203 } 1204 1205 /* the following sequence with magic numbers sets up the SerDes 1206 * option mode 1207 */ 1208 1209 if (!gen1) { 1210 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1211 if (ret < 0) 1212 return ret; 1213 } 1214 1215 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1216 RTL822X_VND1_SERDES_OPTION, 1217 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1218 mode); 1219 if (gen1 || ret < 0) 1220 return ret; 1221 1222 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1223 if (ret < 0) 1224 return ret; 1225 1226 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1227 if (ret < 0) 1228 return ret; 1229 1230 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1231 } 1232 1233 static int rtl822x_config_init(struct phy_device *phydev) 1234 { 1235 return rtl822x_set_serdes_option_mode(phydev, true); 1236 } 1237 1238 static int rtl822xb_config_init(struct phy_device *phydev) 1239 { 1240 return rtl822x_set_serdes_option_mode(phydev, false); 1241 } 1242 1243 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1244 phy_interface_t iface) 1245 { 1246 int val; 1247 1248 /* Only rate matching at 2500base-x */ 1249 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1250 return RATE_MATCH_NONE; 1251 1252 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1253 if (val < 0) 1254 return val; 1255 1256 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1257 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1258 return RATE_MATCH_PAUSE; 1259 1260 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1261 return RATE_MATCH_NONE; 1262 } 1263 1264 static int rtl822x_get_features(struct phy_device *phydev) 1265 { 1266 int val; 1267 1268 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1269 if (val < 0) 1270 return val; 1271 1272 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1273 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1274 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1275 phydev->supported, val & MDIO_PMA_SPEED_5G); 1276 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1277 phydev->supported, val & MDIO_SPEED_10G); 1278 1279 return genphy_read_abilities(phydev); 1280 } 1281 1282 static int rtl822x_config_aneg(struct phy_device *phydev) 1283 { 1284 int ret = 0; 1285 1286 if (phydev->autoneg == AUTONEG_ENABLE) { 1287 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1288 1289 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1290 RTL_MDIO_AN_10GBT_CTRL, 1291 MDIO_AN_10GBT_CTRL_ADV2_5G | 1292 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1293 if (ret < 0) 1294 return ret; 1295 } 1296 1297 return __genphy_config_aneg(phydev, ret); 1298 } 1299 1300 static void rtl822xb_update_interface(struct phy_device *phydev) 1301 { 1302 int val; 1303 1304 if (!phydev->link) 1305 return; 1306 1307 /* Change interface according to serdes mode */ 1308 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1309 if (val < 0) 1310 return; 1311 1312 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1313 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1314 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1315 break; 1316 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1317 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1318 break; 1319 } 1320 } 1321 1322 static int rtl822x_read_status(struct phy_device *phydev) 1323 { 1324 int lpadv, ret; 1325 1326 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1327 1328 ret = rtlgen_read_status(phydev); 1329 if (ret < 0) 1330 return ret; 1331 1332 if (phydev->autoneg == AUTONEG_DISABLE || 1333 !phydev->autoneg_complete) 1334 return 0; 1335 1336 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1337 if (lpadv < 0) 1338 return lpadv; 1339 1340 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1341 1342 return 0; 1343 } 1344 1345 static int rtl822xb_read_status(struct phy_device *phydev) 1346 { 1347 int ret; 1348 1349 ret = rtl822x_read_status(phydev); 1350 if (ret < 0) 1351 return ret; 1352 1353 rtl822xb_update_interface(phydev); 1354 1355 return 0; 1356 } 1357 1358 static int rtl822x_c45_get_features(struct phy_device *phydev) 1359 { 1360 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1361 phydev->supported); 1362 1363 return genphy_c45_pma_read_abilities(phydev); 1364 } 1365 1366 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1367 { 1368 bool changed = false; 1369 int ret, val; 1370 1371 if (phydev->autoneg == AUTONEG_DISABLE) 1372 return genphy_c45_pma_setup_forced(phydev); 1373 1374 ret = genphy_c45_an_config_aneg(phydev); 1375 if (ret < 0) 1376 return ret; 1377 if (ret > 0) 1378 changed = true; 1379 1380 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1381 1382 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1383 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1384 RTL822X_VND2_C22_REG(MII_CTRL1000), 1385 ADVERTISE_1000FULL, val); 1386 if (ret < 0) 1387 return ret; 1388 if (ret > 0) 1389 changed = true; 1390 1391 return genphy_c45_check_and_restart_aneg(phydev, changed); 1392 } 1393 1394 static int rtl822x_c45_read_status(struct phy_device *phydev) 1395 { 1396 int ret, val; 1397 1398 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1399 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1400 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1401 RTL822X_VND2_C22_REG(MII_STAT1000)); 1402 if (val < 0) 1403 return val; 1404 } else { 1405 val = 0; 1406 } 1407 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1408 1409 ret = genphy_c45_read_status(phydev); 1410 if (ret < 0) 1411 return ret; 1412 1413 if (!phydev->link) { 1414 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1415 return 0; 1416 } 1417 1418 /* Read actual speed from vendor register. */ 1419 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1420 if (val < 0) 1421 return val; 1422 1423 rtlgen_decode_physr(phydev, val); 1424 1425 return 0; 1426 } 1427 1428 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1429 { 1430 int ret, val; 1431 1432 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1433 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1434 if (ret < 0) 1435 return ret; 1436 1437 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1438 MDIO_CTRL1, val, 1439 !(val & MDIO_CTRL1_RESET), 1440 5000, 100000, true); 1441 } 1442 1443 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1444 { 1445 int ret; 1446 1447 ret = rtl822x_c45_read_status(phydev); 1448 if (ret < 0) 1449 return ret; 1450 1451 rtl822xb_update_interface(phydev); 1452 1453 return 0; 1454 } 1455 1456 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1457 { 1458 int val; 1459 1460 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1461 val = phy_read(phydev, 0x13); 1462 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1463 1464 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1465 } 1466 1467 /* On internal PHY's MMD reads over C22 always return 0. 1468 * Check a MMD register which is known to be non-zero. 1469 */ 1470 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1471 { 1472 int val; 1473 1474 phy_lock_mdio_bus(phydev); 1475 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1476 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1477 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1478 val = __phy_read(phydev, MII_MMD_DATA); 1479 phy_unlock_mdio_bus(phydev); 1480 1481 return val > 0; 1482 } 1483 1484 static int rtlgen_match_phy_device(struct phy_device *phydev, 1485 const struct phy_driver *phydrv) 1486 { 1487 return phydev->phy_id == RTL_GENERIC_PHYID && 1488 !rtlgen_supports_2_5gbps(phydev); 1489 } 1490 1491 static int rtl8226_match_phy_device(struct phy_device *phydev, 1492 const struct phy_driver *phydrv) 1493 { 1494 return phydev->phy_id == RTL_GENERIC_PHYID && 1495 rtlgen_supports_2_5gbps(phydev) && 1496 rtlgen_supports_mmd(phydev); 1497 } 1498 1499 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1500 bool is_c45) 1501 { 1502 if (phydev->is_c45) 1503 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1504 else 1505 return !is_c45 && (id == phydev->phy_id); 1506 } 1507 1508 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1509 const struct phy_driver *phydrv) 1510 { 1511 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1512 } 1513 1514 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1515 const struct phy_driver *phydrv) 1516 { 1517 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1518 } 1519 1520 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1521 const struct phy_driver *phydrv) 1522 { 1523 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1524 } 1525 1526 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, 1527 const struct phy_driver *phydrv) 1528 { 1529 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1530 } 1531 1532 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, 1533 const struct phy_driver *phydrv) 1534 { 1535 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1536 } 1537 1538 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1539 const struct phy_driver *phydrv) 1540 { 1541 if (phydev->is_c45) 1542 return false; 1543 1544 switch (phydev->phy_id) { 1545 case RTL_GENERIC_PHYID: 1546 case RTL_8221B: 1547 case RTL_8251B: 1548 case RTL_8261C: 1549 case 0x001cc841: 1550 break; 1551 default: 1552 return false; 1553 } 1554 1555 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1556 } 1557 1558 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1559 const struct phy_driver *phydrv) 1560 { 1561 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1562 } 1563 1564 static int rtlgen_resume(struct phy_device *phydev) 1565 { 1566 int ret = genphy_resume(phydev); 1567 1568 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1569 msleep(20); 1570 1571 return ret; 1572 } 1573 1574 static int rtlgen_c45_resume(struct phy_device *phydev) 1575 { 1576 int ret = genphy_c45_pma_resume(phydev); 1577 1578 msleep(20); 1579 1580 return ret; 1581 } 1582 1583 static int rtl9000a_config_init(struct phy_device *phydev) 1584 { 1585 phydev->autoneg = AUTONEG_DISABLE; 1586 phydev->speed = SPEED_100; 1587 phydev->duplex = DUPLEX_FULL; 1588 1589 return 0; 1590 } 1591 1592 static int rtl9000a_config_aneg(struct phy_device *phydev) 1593 { 1594 int ret; 1595 u16 ctl = 0; 1596 1597 switch (phydev->master_slave_set) { 1598 case MASTER_SLAVE_CFG_MASTER_FORCE: 1599 ctl |= CTL1000_AS_MASTER; 1600 break; 1601 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1602 break; 1603 case MASTER_SLAVE_CFG_UNKNOWN: 1604 case MASTER_SLAVE_CFG_UNSUPPORTED: 1605 return 0; 1606 default: 1607 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1608 return -EOPNOTSUPP; 1609 } 1610 1611 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1612 if (ret == 1) 1613 ret = genphy_soft_reset(phydev); 1614 1615 return ret; 1616 } 1617 1618 static int rtl9000a_read_status(struct phy_device *phydev) 1619 { 1620 int ret; 1621 1622 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1623 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1624 1625 ret = genphy_update_link(phydev); 1626 if (ret) 1627 return ret; 1628 1629 ret = phy_read(phydev, MII_CTRL1000); 1630 if (ret < 0) 1631 return ret; 1632 if (ret & CTL1000_AS_MASTER) 1633 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1634 else 1635 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1636 1637 ret = phy_read(phydev, MII_STAT1000); 1638 if (ret < 0) 1639 return ret; 1640 if (ret & LPA_1000MSRES) 1641 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1642 else 1643 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1644 1645 return 0; 1646 } 1647 1648 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1649 { 1650 int err; 1651 1652 err = phy_read(phydev, RTL8211F_INSR); 1653 1654 return (err < 0) ? err : 0; 1655 } 1656 1657 static int rtl9000a_config_intr(struct phy_device *phydev) 1658 { 1659 u16 val; 1660 int err; 1661 1662 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1663 err = rtl9000a_ack_interrupt(phydev); 1664 if (err) 1665 return err; 1666 1667 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1668 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1669 } else { 1670 val = ~0; 1671 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1672 if (err) 1673 return err; 1674 1675 err = rtl9000a_ack_interrupt(phydev); 1676 } 1677 1678 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1679 } 1680 1681 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1682 { 1683 int irq_status; 1684 1685 irq_status = phy_read(phydev, RTL8211F_INSR); 1686 if (irq_status < 0) { 1687 phy_error(phydev); 1688 return IRQ_NONE; 1689 } 1690 1691 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1692 return IRQ_NONE; 1693 1694 phy_trigger_machine(phydev); 1695 1696 return IRQ_HANDLED; 1697 } 1698 1699 static struct phy_driver realtek_drvs[] = { 1700 { 1701 PHY_ID_MATCH_EXACT(0x00008201), 1702 .name = "RTL8201CP Ethernet", 1703 .read_page = rtl821x_read_page, 1704 .write_page = rtl821x_write_page, 1705 }, { 1706 PHY_ID_MATCH_EXACT(0x001cc816), 1707 .name = "RTL8201F Fast Ethernet", 1708 .config_intr = &rtl8201_config_intr, 1709 .handle_interrupt = rtl8201_handle_interrupt, 1710 .suspend = genphy_suspend, 1711 .resume = genphy_resume, 1712 .read_page = rtl821x_read_page, 1713 .write_page = rtl821x_write_page, 1714 }, { 1715 PHY_ID_MATCH_MODEL(0x001cc880), 1716 .name = "RTL8208 Fast Ethernet", 1717 .read_mmd = genphy_read_mmd_unsupported, 1718 .write_mmd = genphy_write_mmd_unsupported, 1719 .suspend = genphy_suspend, 1720 .resume = genphy_resume, 1721 .read_page = rtl821x_read_page, 1722 .write_page = rtl821x_write_page, 1723 }, { 1724 PHY_ID_MATCH_EXACT(0x001cc910), 1725 .name = "RTL8211 Gigabit Ethernet", 1726 .config_aneg = rtl8211_config_aneg, 1727 .read_mmd = &genphy_read_mmd_unsupported, 1728 .write_mmd = &genphy_write_mmd_unsupported, 1729 .read_page = rtl821x_read_page, 1730 .write_page = rtl821x_write_page, 1731 }, { 1732 PHY_ID_MATCH_EXACT(0x001cc912), 1733 .name = "RTL8211B Gigabit Ethernet", 1734 .config_intr = &rtl8211b_config_intr, 1735 .handle_interrupt = rtl821x_handle_interrupt, 1736 .read_mmd = &genphy_read_mmd_unsupported, 1737 .write_mmd = &genphy_write_mmd_unsupported, 1738 .suspend = rtl8211b_suspend, 1739 .resume = rtl8211b_resume, 1740 .read_page = rtl821x_read_page, 1741 .write_page = rtl821x_write_page, 1742 }, { 1743 PHY_ID_MATCH_EXACT(0x001cc913), 1744 .name = "RTL8211C Gigabit Ethernet", 1745 .config_init = rtl8211c_config_init, 1746 .read_mmd = &genphy_read_mmd_unsupported, 1747 .write_mmd = &genphy_write_mmd_unsupported, 1748 .read_page = rtl821x_read_page, 1749 .write_page = rtl821x_write_page, 1750 }, { 1751 PHY_ID_MATCH_EXACT(0x001cc914), 1752 .name = "RTL8211DN Gigabit Ethernet", 1753 .config_intr = rtl8211e_config_intr, 1754 .handle_interrupt = rtl821x_handle_interrupt, 1755 .suspend = genphy_suspend, 1756 .resume = genphy_resume, 1757 .read_page = rtl821x_read_page, 1758 .write_page = rtl821x_write_page, 1759 }, { 1760 PHY_ID_MATCH_EXACT(0x001cc915), 1761 .name = "RTL8211E Gigabit Ethernet", 1762 .config_init = &rtl8211e_config_init, 1763 .config_intr = &rtl8211e_config_intr, 1764 .handle_interrupt = rtl821x_handle_interrupt, 1765 .suspend = genphy_suspend, 1766 .resume = genphy_resume, 1767 .read_page = rtl821x_read_page, 1768 .write_page = rtl821x_write_page, 1769 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1770 .led_hw_control_get = rtl8211e_led_hw_control_get, 1771 .led_hw_control_set = rtl8211e_led_hw_control_set, 1772 }, { 1773 PHY_ID_MATCH_EXACT(0x001cc916), 1774 .name = "RTL8211F Gigabit Ethernet", 1775 .probe = rtl8211f_probe, 1776 .config_init = &rtl8211f_config_init, 1777 .read_status = rtlgen_read_status, 1778 .config_intr = &rtl8211f_config_intr, 1779 .handle_interrupt = rtl8211f_handle_interrupt, 1780 .set_wol = rtl8211f_set_wol, 1781 .get_wol = rtl8211f_get_wol, 1782 .suspend = rtl8211f_suspend, 1783 .resume = rtl8211f_resume, 1784 .read_page = rtl821x_read_page, 1785 .write_page = rtl821x_write_page, 1786 .flags = PHY_ALWAYS_CALL_SUSPEND, 1787 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1788 .led_hw_control_get = rtl8211f_led_hw_control_get, 1789 .led_hw_control_set = rtl8211f_led_hw_control_set, 1790 }, { 1791 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1792 .name = "RTL8211F-VD Gigabit Ethernet", 1793 .probe = rtl821x_probe, 1794 .config_init = &rtl8211f_config_init, 1795 .read_status = rtlgen_read_status, 1796 .config_intr = &rtl8211f_config_intr, 1797 .handle_interrupt = rtl8211f_handle_interrupt, 1798 .suspend = rtl821x_suspend, 1799 .resume = rtl821x_resume, 1800 .read_page = rtl821x_read_page, 1801 .write_page = rtl821x_write_page, 1802 .flags = PHY_ALWAYS_CALL_SUSPEND, 1803 }, { 1804 .name = "Generic FE-GE Realtek PHY", 1805 .match_phy_device = rtlgen_match_phy_device, 1806 .read_status = rtlgen_read_status, 1807 .suspend = genphy_suspend, 1808 .resume = rtlgen_resume, 1809 .read_page = rtl821x_read_page, 1810 .write_page = rtl821x_write_page, 1811 .read_mmd = rtlgen_read_mmd, 1812 .write_mmd = rtlgen_write_mmd, 1813 }, { 1814 .name = "RTL8226 2.5Gbps PHY", 1815 .match_phy_device = rtl8226_match_phy_device, 1816 .get_features = rtl822x_get_features, 1817 .config_aneg = rtl822x_config_aneg, 1818 .read_status = rtl822x_read_status, 1819 .suspend = genphy_suspend, 1820 .resume = rtlgen_resume, 1821 .read_page = rtl821x_read_page, 1822 .write_page = rtl821x_write_page, 1823 }, { 1824 .match_phy_device = rtl8221b_match_phy_device, 1825 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1826 .get_features = rtl822x_get_features, 1827 .config_aneg = rtl822x_config_aneg, 1828 .config_init = rtl822xb_config_init, 1829 .get_rate_matching = rtl822xb_get_rate_matching, 1830 .read_status = rtl822xb_read_status, 1831 .suspend = genphy_suspend, 1832 .resume = rtlgen_resume, 1833 .read_page = rtl821x_read_page, 1834 .write_page = rtl821x_write_page, 1835 }, { 1836 PHY_ID_MATCH_EXACT(0x001cc838), 1837 .name = "RTL8226-CG 2.5Gbps PHY", 1838 .soft_reset = rtl822x_c45_soft_reset, 1839 .get_features = rtl822x_c45_get_features, 1840 .config_aneg = rtl822x_c45_config_aneg, 1841 .config_init = rtl822x_config_init, 1842 .read_status = rtl822xb_c45_read_status, 1843 .suspend = genphy_c45_pma_suspend, 1844 .resume = rtlgen_c45_resume, 1845 }, { 1846 PHY_ID_MATCH_EXACT(0x001cc848), 1847 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1848 .get_features = rtl822x_get_features, 1849 .config_aneg = rtl822x_config_aneg, 1850 .config_init = rtl822xb_config_init, 1851 .get_rate_matching = rtl822xb_get_rate_matching, 1852 .read_status = rtl822xb_read_status, 1853 .suspend = genphy_suspend, 1854 .resume = rtlgen_resume, 1855 .read_page = rtl821x_read_page, 1856 .write_page = rtl821x_write_page, 1857 }, { 1858 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1859 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1860 .probe = rtl822x_probe, 1861 .get_features = rtl822x_get_features, 1862 .config_aneg = rtl822x_config_aneg, 1863 .config_init = rtl822xb_config_init, 1864 .get_rate_matching = rtl822xb_get_rate_matching, 1865 .read_status = rtl822xb_read_status, 1866 .suspend = genphy_suspend, 1867 .resume = rtlgen_resume, 1868 .read_page = rtl821x_read_page, 1869 .write_page = rtl821x_write_page, 1870 }, { 1871 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1872 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1873 .probe = rtl822x_probe, 1874 .config_init = rtl822xb_config_init, 1875 .get_rate_matching = rtl822xb_get_rate_matching, 1876 .get_features = rtl822x_c45_get_features, 1877 .config_aneg = rtl822x_c45_config_aneg, 1878 .read_status = rtl822xb_c45_read_status, 1879 .suspend = genphy_c45_pma_suspend, 1880 .resume = rtlgen_c45_resume, 1881 }, { 1882 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1883 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1884 .probe = rtl822x_probe, 1885 .get_features = rtl822x_get_features, 1886 .config_aneg = rtl822x_config_aneg, 1887 .config_init = rtl822xb_config_init, 1888 .get_rate_matching = rtl822xb_get_rate_matching, 1889 .read_status = rtl822xb_read_status, 1890 .suspend = genphy_suspend, 1891 .resume = rtlgen_resume, 1892 .read_page = rtl821x_read_page, 1893 .write_page = rtl821x_write_page, 1894 }, { 1895 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1896 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1897 .probe = rtl822x_probe, 1898 .config_init = rtl822xb_config_init, 1899 .get_rate_matching = rtl822xb_get_rate_matching, 1900 .get_features = rtl822x_c45_get_features, 1901 .config_aneg = rtl822x_c45_config_aneg, 1902 .read_status = rtl822xb_c45_read_status, 1903 .suspend = genphy_c45_pma_suspend, 1904 .resume = rtlgen_c45_resume, 1905 }, { 1906 .match_phy_device = rtl8251b_c45_match_phy_device, 1907 .name = "RTL8251B 5Gbps PHY", 1908 .probe = rtl822x_probe, 1909 .get_features = rtl822x_get_features, 1910 .config_aneg = rtl822x_config_aneg, 1911 .read_status = rtl822x_read_status, 1912 .suspend = genphy_suspend, 1913 .resume = rtlgen_resume, 1914 .read_page = rtl821x_read_page, 1915 .write_page = rtl821x_write_page, 1916 }, { 1917 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1918 .name = "Realtek Internal NBASE-T PHY", 1919 .flags = PHY_IS_INTERNAL, 1920 .probe = rtl822x_probe, 1921 .get_features = rtl822x_get_features, 1922 .config_aneg = rtl822x_config_aneg, 1923 .read_status = rtl822x_read_status, 1924 .suspend = genphy_suspend, 1925 .resume = rtlgen_resume, 1926 .read_page = rtl821x_read_page, 1927 .write_page = rtl821x_write_page, 1928 .read_mmd = rtl822x_read_mmd, 1929 .write_mmd = rtl822x_write_mmd, 1930 }, { 1931 PHY_ID_MATCH_EXACT(0x001ccad0), 1932 .name = "RTL8224 2.5Gbps PHY", 1933 .get_features = rtl822x_c45_get_features, 1934 .config_aneg = rtl822x_c45_config_aneg, 1935 .read_status = rtl822x_c45_read_status, 1936 .suspend = genphy_c45_pma_suspend, 1937 .resume = rtlgen_c45_resume, 1938 }, { 1939 PHY_ID_MATCH_EXACT(0x001cc961), 1940 .name = "RTL8366RB Gigabit Ethernet", 1941 .config_init = &rtl8366rb_config_init, 1942 /* These interrupts are handled by the irq controller 1943 * embedded inside the RTL8366RB, they get unmasked when the 1944 * irq is requested and ACKed by reading the status register, 1945 * which is done by the irqchip code. 1946 */ 1947 .config_intr = genphy_no_config_intr, 1948 .handle_interrupt = genphy_handle_interrupt_no_ack, 1949 .suspend = genphy_suspend, 1950 .resume = genphy_resume, 1951 }, { 1952 PHY_ID_MATCH_EXACT(0x001ccb00), 1953 .name = "RTL9000AA_RTL9000AN Ethernet", 1954 .features = PHY_BASIC_T1_FEATURES, 1955 .config_init = rtl9000a_config_init, 1956 .config_aneg = rtl9000a_config_aneg, 1957 .read_status = rtl9000a_read_status, 1958 .config_intr = rtl9000a_config_intr, 1959 .handle_interrupt = rtl9000a_handle_interrupt, 1960 .suspend = genphy_suspend, 1961 .resume = genphy_resume, 1962 .read_page = rtl821x_read_page, 1963 .write_page = rtl821x_write_page, 1964 }, { 1965 PHY_ID_MATCH_EXACT(0x001cc942), 1966 .name = "RTL8365MB-VC Gigabit Ethernet", 1967 /* Interrupt handling analogous to RTL8366RB */ 1968 .config_intr = genphy_no_config_intr, 1969 .handle_interrupt = genphy_handle_interrupt_no_ack, 1970 .suspend = genphy_suspend, 1971 .resume = genphy_resume, 1972 }, { 1973 PHY_ID_MATCH_EXACT(0x001cc960), 1974 .name = "RTL8366S Gigabit Ethernet", 1975 .suspend = genphy_suspend, 1976 .resume = genphy_resume, 1977 .read_mmd = genphy_read_mmd_unsupported, 1978 .write_mmd = genphy_write_mmd_unsupported, 1979 }, 1980 }; 1981 1982 module_phy_driver(realtek_drvs); 1983 1984 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1985 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1986 { } 1987 }; 1988 1989 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1990