1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 21 #include "../phylib.h" 22 #include "realtek.h" 23 24 #define RTL8201F_IER 0x13 25 26 #define RTL8201F_ISR 0x1e 27 #define RTL8201F_ISR_ANERR BIT(15) 28 #define RTL8201F_ISR_DUPLEX BIT(13) 29 #define RTL8201F_ISR_LINK BIT(11) 30 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 31 RTL8201F_ISR_DUPLEX | \ 32 RTL8201F_ISR_LINK) 33 34 #define RTL821x_INER 0x12 35 #define RTL8211B_INER_INIT 0x6400 36 #define RTL8211E_INER_LINK_STATUS BIT(10) 37 #define RTL8211F_INER_PME BIT(7) 38 #define RTL8211F_INER_LINK_STATUS BIT(4) 39 40 #define RTL821x_INSR 0x13 41 42 #define RTL821x_EXT_PAGE_SELECT 0x1e 43 44 #define RTL821x_PAGE_SELECT 0x1f 45 #define RTL821x_SET_EXT_PAGE 0x07 46 47 /* RTL8211E extension page 44/0x2c */ 48 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 49 #define RTL8211E_LEDCR1 0x1a 50 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 51 #define RTL8211E_LEDCR1_MASK BIT(4) 52 #define RTL8211E_LEDCR1_SHIFT 1 53 54 #define RTL8211E_LEDCR2 0x1c 55 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 56 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 57 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 58 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 59 #define RTL8211E_LEDCR2_SHIFT 4 60 61 /* RTL8211E extension page 164/0xa4 */ 62 #define RTL8211E_RGMII_EXT_PAGE 0xa4 63 #define RTL8211E_RGMII_DELAY 0x1c 64 #define RTL8211E_CTRL_DELAY BIT(13) 65 #define RTL8211E_TX_DELAY BIT(12) 66 #define RTL8211E_RX_DELAY BIT(11) 67 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 68 69 /* RTL8211F PHY configuration */ 70 #define RTL8211F_PHYCR_PAGE 0xa43 71 #define RTL8211F_PHYCR1 0x18 72 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 73 #define RTL8211F_ALDPS_ENABLE BIT(2) 74 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 75 76 #define RTL8211F_PHYCR2 0x19 77 #define RTL8211F_CLKOUT_EN BIT(0) 78 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 79 80 #define RTL8211F_INSR_PAGE 0xa43 81 #define RTL8211F_INSR 0x1d 82 83 /* RTL8211F LED configuration */ 84 #define RTL8211F_LEDCR_PAGE 0xd04 85 #define RTL8211F_LEDCR 0x10 86 #define RTL8211F_LEDCR_MODE BIT(15) 87 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 88 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 89 #define RTL8211F_LEDCR_LINK_100 BIT(1) 90 #define RTL8211F_LEDCR_LINK_10 BIT(0) 91 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 92 #define RTL8211F_LEDCR_SHIFT 5 93 94 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 95 * to undocumented register pages. The names here do not reflect the datasheet. 96 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 97 */ 98 #define RTL8211FVD_CLKOUT_PAGE 0xd05 99 #define RTL8211FVD_CLKOUT_REG 0x11 100 #define RTL8211FVD_CLKOUT_EN BIT(8) 101 102 /* RTL8211F RGMII configuration */ 103 #define RTL8211F_RGMII_PAGE 0xd08 104 105 #define RTL8211F_TXCR 0x11 106 #define RTL8211F_TX_DELAY BIT(8) 107 108 #define RTL8211F_RXCR 0x15 109 #define RTL8211F_RX_DELAY BIT(3) 110 111 /* RTL8211F WOL settings */ 112 #define RTL8211F_WOL_PAGE 0xd8a 113 #define RTL8211F_WOL_SETTINGS_EVENTS 16 114 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 115 #define RTL8211F_WOL_RST_RMSQ 17 116 #define RTL8211F_WOL_RG_RSTB BIT(15) 117 #define RTL8211F_WOL_RMSQ 0x1fff 118 119 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 120 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 121 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 122 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 123 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 124 125 #define RTL822X_VND1_SERDES_OPTION 0x697a 126 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 128 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 129 130 #define RTL822X_VND1_SERDES_CTRL3 0x7580 131 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 132 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 133 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 134 135 #define RTL822X_VND1_SERDES_CMD 0x7587 136 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 137 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 138 #define RTL822X_VND1_SERDES_ADDR 0x7588 139 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 140 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 141 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 142 #define RTL822X_VND1_SERDES_DATA 0x7589 143 144 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 145 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 146 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 147 148 #define RTL8221B_VND2_INER 0xa4d2 149 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 150 151 #define RTL8221B_VND2_INSR 0xa4d4 152 153 #define RTL8224_MII_RTCT 0x11 154 #define RTL8224_MII_RTCT_ENABLE BIT(0) 155 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 156 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 157 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 158 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 159 #define RTL8224_MII_RTCT_DONE BIT(15) 160 161 #define RTL8224_MII_SRAM_ADDR 0x1b 162 #define RTL8224_MII_SRAM_DATA 0x1c 163 164 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 165 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 166 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 167 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 168 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 169 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 170 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 171 172 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 173 174 #define RTL8366RB_POWER_SAVE 0x15 175 #define RTL8366RB_POWER_SAVE_ON BIT(12) 176 177 #define RTL9000A_GINMR 0x14 178 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 179 180 #define RTL_VND2_PHYSR 0xa434 181 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 182 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 183 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 184 #define RTL_VND2_PHYSR_MASTER BIT(11) 185 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 186 187 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 188 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 189 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 190 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 191 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 192 #define RTL_MDIO_PMA_SPEED 0xa616 193 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 194 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 195 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 196 197 #define RTL_GENERIC_PHYID 0x001cc800 198 #define RTL_8211FVD_PHYID 0x001cc878 199 #define RTL_8221B 0x001cc840 200 #define RTL_8221B_VB_CG 0x001cc849 201 #define RTL_8221B_VM_CG 0x001cc84a 202 #define RTL_8251B 0x001cc862 203 #define RTL_8261C 0x001cc890 204 205 /* RTL8211E and RTL8211F support up to three LEDs */ 206 #define RTL8211x_LED_COUNT 3 207 208 MODULE_DESCRIPTION("Realtek PHY driver"); 209 MODULE_AUTHOR("Johnson Leung"); 210 MODULE_LICENSE("GPL"); 211 212 struct rtl821x_priv { 213 bool enable_aldps; 214 bool disable_clk_out; 215 struct clk *clk; 216 /* rtl8211f */ 217 u16 iner; 218 }; 219 220 static int rtl821x_read_page(struct phy_device *phydev) 221 { 222 return __phy_read(phydev, RTL821x_PAGE_SELECT); 223 } 224 225 static int rtl821x_write_page(struct phy_device *phydev, int page) 226 { 227 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 228 } 229 230 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 231 u32 regnum) 232 { 233 int oldpage, ret = 0; 234 235 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 236 if (oldpage >= 0) { 237 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 238 if (ret == 0) 239 ret = __phy_read(phydev, regnum); 240 } 241 242 return phy_restore_page(phydev, oldpage, ret); 243 } 244 245 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 246 u32 regnum, u16 mask, u16 set) 247 { 248 int oldpage, ret = 0; 249 250 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 251 if (oldpage >= 0) { 252 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 253 if (ret == 0) 254 ret = __phy_modify(phydev, regnum, mask, set); 255 } 256 257 return phy_restore_page(phydev, oldpage, ret); 258 } 259 260 static int rtl821x_probe(struct phy_device *phydev) 261 { 262 struct device *dev = &phydev->mdio.dev; 263 struct rtl821x_priv *priv; 264 265 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 266 if (!priv) 267 return -ENOMEM; 268 269 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 270 if (IS_ERR(priv->clk)) 271 return dev_err_probe(dev, PTR_ERR(priv->clk), 272 "failed to get phy clock\n"); 273 274 priv->enable_aldps = of_property_read_bool(dev->of_node, 275 "realtek,aldps-enable"); 276 priv->disable_clk_out = of_property_read_bool(dev->of_node, 277 "realtek,clkout-disable"); 278 279 phydev->priv = priv; 280 281 return 0; 282 } 283 284 static int rtl8211f_probe(struct phy_device *phydev) 285 { 286 struct device *dev = &phydev->mdio.dev; 287 int ret; 288 289 ret = rtl821x_probe(phydev); 290 if (ret < 0) 291 return ret; 292 293 /* Disable all PME events */ 294 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 295 RTL8211F_WOL_SETTINGS_EVENTS, 0); 296 if (ret < 0) 297 return ret; 298 299 /* Mark this PHY as wakeup capable and register the interrupt as a 300 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 301 * and the interrupt is valid. 302 */ 303 if (device_property_read_bool(dev, "wakeup-source") && 304 phy_interrupt_is_valid(phydev)) { 305 device_set_wakeup_capable(dev, true); 306 devm_pm_set_wake_irq(dev, phydev->irq); 307 } 308 309 return ret; 310 } 311 312 static int rtl8201_ack_interrupt(struct phy_device *phydev) 313 { 314 int err; 315 316 err = phy_read(phydev, RTL8201F_ISR); 317 318 return (err < 0) ? err : 0; 319 } 320 321 static int rtl821x_ack_interrupt(struct phy_device *phydev) 322 { 323 int err; 324 325 err = phy_read(phydev, RTL821x_INSR); 326 327 return (err < 0) ? err : 0; 328 } 329 330 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 331 { 332 int err; 333 334 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 335 336 return (err < 0) ? err : 0; 337 } 338 339 static int rtl8201_config_intr(struct phy_device *phydev) 340 { 341 u16 val; 342 int err; 343 344 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 345 err = rtl8201_ack_interrupt(phydev); 346 if (err) 347 return err; 348 349 val = BIT(13) | BIT(12) | BIT(11); 350 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 351 } else { 352 val = 0; 353 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 354 if (err) 355 return err; 356 357 err = rtl8201_ack_interrupt(phydev); 358 } 359 360 return err; 361 } 362 363 static int rtl8211b_config_intr(struct phy_device *phydev) 364 { 365 int err; 366 367 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 368 err = rtl821x_ack_interrupt(phydev); 369 if (err) 370 return err; 371 372 err = phy_write(phydev, RTL821x_INER, 373 RTL8211B_INER_INIT); 374 } else { 375 err = phy_write(phydev, RTL821x_INER, 0); 376 if (err) 377 return err; 378 379 err = rtl821x_ack_interrupt(phydev); 380 } 381 382 return err; 383 } 384 385 static int rtl8211e_config_intr(struct phy_device *phydev) 386 { 387 int err; 388 389 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 390 err = rtl821x_ack_interrupt(phydev); 391 if (err) 392 return err; 393 394 err = phy_write(phydev, RTL821x_INER, 395 RTL8211E_INER_LINK_STATUS); 396 } else { 397 err = phy_write(phydev, RTL821x_INER, 0); 398 if (err) 399 return err; 400 401 err = rtl821x_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static int rtl8211f_config_intr(struct phy_device *phydev) 408 { 409 struct rtl821x_priv *priv = phydev->priv; 410 u16 val; 411 int err; 412 413 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 414 err = rtl8211f_ack_interrupt(phydev); 415 if (err) 416 return err; 417 418 val = RTL8211F_INER_LINK_STATUS; 419 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 420 if (err == 0) 421 priv->iner = val; 422 } else { 423 priv->iner = val = 0; 424 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 425 if (err) 426 return err; 427 428 err = rtl8211f_ack_interrupt(phydev); 429 } 430 431 return err; 432 } 433 434 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 435 { 436 int irq_status; 437 438 irq_status = phy_read(phydev, RTL8201F_ISR); 439 if (irq_status < 0) { 440 phy_error(phydev); 441 return IRQ_NONE; 442 } 443 444 if (!(irq_status & RTL8201F_ISR_MASK)) 445 return IRQ_NONE; 446 447 phy_trigger_machine(phydev); 448 449 return IRQ_HANDLED; 450 } 451 452 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 453 { 454 int irq_status, irq_enabled; 455 456 irq_status = phy_read(phydev, RTL821x_INSR); 457 if (irq_status < 0) { 458 phy_error(phydev); 459 return IRQ_NONE; 460 } 461 462 irq_enabled = phy_read(phydev, RTL821x_INER); 463 if (irq_enabled < 0) { 464 phy_error(phydev); 465 return IRQ_NONE; 466 } 467 468 if (!(irq_status & irq_enabled)) 469 return IRQ_NONE; 470 471 phy_trigger_machine(phydev); 472 473 return IRQ_HANDLED; 474 } 475 476 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 477 { 478 int irq_status; 479 480 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 481 if (irq_status < 0) { 482 phy_error(phydev); 483 return IRQ_NONE; 484 } 485 486 if (irq_status & RTL8211F_INER_LINK_STATUS) { 487 phy_trigger_machine(phydev); 488 return IRQ_HANDLED; 489 } 490 491 if (irq_status & RTL8211F_INER_PME) { 492 pm_wakeup_event(&phydev->mdio.dev, 0); 493 return IRQ_HANDLED; 494 } 495 496 return IRQ_NONE; 497 } 498 499 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 500 { 501 int wol_events; 502 503 /* If the PHY is not capable of waking the system, then WoL can not 504 * be supported. 505 */ 506 if (!device_can_wakeup(&dev->mdio.dev)) { 507 wol->supported = 0; 508 return; 509 } 510 511 wol->supported = WAKE_MAGIC; 512 513 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 514 if (wol_events < 0) 515 return; 516 517 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 518 wol->wolopts = WAKE_MAGIC; 519 } 520 521 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 522 { 523 const u8 *mac_addr = dev->attached_dev->dev_addr; 524 int oldpage; 525 526 if (!device_can_wakeup(&dev->mdio.dev)) 527 return -EOPNOTSUPP; 528 529 oldpage = phy_save_page(dev); 530 if (oldpage < 0) 531 goto err; 532 533 if (wol->wolopts & WAKE_MAGIC) { 534 /* Store the device address for the magic packet */ 535 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 536 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 537 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 538 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 539 540 /* Enable magic packet matching */ 541 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 542 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 543 /* Set the maximum packet size, and assert WoL reset */ 544 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 545 } else { 546 /* Disable magic packet matching */ 547 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 548 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 549 550 /* Place WoL in reset */ 551 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 552 RTL8211F_WOL_RG_RSTB); 553 } 554 555 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 556 557 err: 558 return phy_restore_page(dev, oldpage, 0); 559 } 560 561 static int rtl8211_config_aneg(struct phy_device *phydev) 562 { 563 int ret; 564 565 ret = genphy_config_aneg(phydev); 566 if (ret < 0) 567 return ret; 568 569 /* Quirk was copied from vendor driver. Unfortunately it includes no 570 * description of the magic numbers. 571 */ 572 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 573 phy_write(phydev, 0x17, 0x2138); 574 phy_write(phydev, 0x0e, 0x0260); 575 } else { 576 phy_write(phydev, 0x17, 0x2108); 577 phy_write(phydev, 0x0e, 0x0000); 578 } 579 580 return 0; 581 } 582 583 static int rtl8211c_config_init(struct phy_device *phydev) 584 { 585 /* RTL8211C has an issue when operating in Gigabit slave mode */ 586 return phy_set_bits(phydev, MII_CTRL1000, 587 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 588 } 589 590 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 591 { 592 u16 val_txdly, val_rxdly; 593 int ret; 594 595 switch (phydev->interface) { 596 case PHY_INTERFACE_MODE_RGMII: 597 val_txdly = 0; 598 val_rxdly = 0; 599 break; 600 601 case PHY_INTERFACE_MODE_RGMII_RXID: 602 val_txdly = 0; 603 val_rxdly = RTL8211F_RX_DELAY; 604 break; 605 606 case PHY_INTERFACE_MODE_RGMII_TXID: 607 val_txdly = RTL8211F_TX_DELAY; 608 val_rxdly = 0; 609 break; 610 611 case PHY_INTERFACE_MODE_RGMII_ID: 612 val_txdly = RTL8211F_TX_DELAY; 613 val_rxdly = RTL8211F_RX_DELAY; 614 break; 615 616 default: /* the rest of the modes imply leaving delay as is. */ 617 return 0; 618 } 619 620 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 621 RTL8211F_TXCR, RTL8211F_TX_DELAY, 622 val_txdly); 623 if (ret < 0) { 624 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 625 ERR_PTR(ret)); 626 return ret; 627 } else if (ret) { 628 phydev_dbg(phydev, 629 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 630 str_enable_disable(val_txdly)); 631 } else { 632 phydev_dbg(phydev, 633 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 634 str_enabled_disabled(val_txdly)); 635 } 636 637 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 638 RTL8211F_RXCR, RTL8211F_RX_DELAY, 639 val_rxdly); 640 if (ret < 0) { 641 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 642 ERR_PTR(ret)); 643 return ret; 644 } else if (ret) { 645 phydev_dbg(phydev, 646 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 647 str_enable_disable(val_rxdly)); 648 } else { 649 phydev_dbg(phydev, 650 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 651 str_enabled_disabled(val_rxdly)); 652 } 653 654 return 0; 655 } 656 657 static int rtl8211f_config_clk_out(struct phy_device *phydev) 658 { 659 struct rtl821x_priv *priv = phydev->priv; 660 int ret; 661 662 /* The value is preserved if the device tree property is absent */ 663 if (!priv->disable_clk_out) 664 return 0; 665 666 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 667 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 668 RTL8211FVD_CLKOUT_REG, 669 RTL8211FVD_CLKOUT_EN, 0); 670 else 671 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 672 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 0); 673 if (ret) 674 return ret; 675 676 return genphy_soft_reset(phydev); 677 } 678 679 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 680 * which causes the RXC clock signal to stop for tens to hundreds of 681 * milliseconds. 682 * 683 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 684 * only enabled based on an opt-in device tree property. 685 */ 686 static int rtl8211f_config_aldps(struct phy_device *phydev) 687 { 688 struct rtl821x_priv *priv = phydev->priv; 689 u16 mask = RTL8211F_ALDPS_PLL_OFF | 690 RTL8211F_ALDPS_ENABLE | 691 RTL8211F_ALDPS_XTAL_OFF; 692 693 /* The value is preserved if the device tree property is absent */ 694 if (!priv->enable_aldps) 695 return 0; 696 697 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 698 mask, mask); 699 } 700 701 static int rtl8211f_config_phy_eee(struct phy_device *phydev) 702 { 703 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 704 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 705 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 706 } 707 708 static int rtl8211f_config_init(struct phy_device *phydev) 709 { 710 struct device *dev = &phydev->mdio.dev; 711 int ret; 712 713 ret = rtl8211f_config_aldps(phydev); 714 if (ret) { 715 dev_err(dev, "aldps mode configuration failed: %pe\n", 716 ERR_PTR(ret)); 717 return ret; 718 } 719 720 ret = rtl8211f_config_rgmii_delay(phydev); 721 if (ret) 722 return ret; 723 724 ret = rtl8211f_config_clk_out(phydev); 725 if (ret) { 726 dev_err(dev, "clkout configuration failed: %pe\n", 727 ERR_PTR(ret)); 728 return ret; 729 } 730 731 return rtl8211f_config_phy_eee(phydev); 732 } 733 734 static int rtl821x_suspend(struct phy_device *phydev) 735 { 736 struct rtl821x_priv *priv = phydev->priv; 737 int ret = 0; 738 739 if (!phydev->wol_enabled) { 740 ret = genphy_suspend(phydev); 741 742 if (ret) 743 return ret; 744 745 clk_disable_unprepare(priv->clk); 746 } 747 748 return ret; 749 } 750 751 static int rtl8211f_suspend(struct phy_device *phydev) 752 { 753 u16 wol_rst; 754 int ret; 755 756 ret = rtl821x_suspend(phydev); 757 if (ret < 0) 758 return ret; 759 760 /* If a PME event is enabled, then configure the interrupt for 761 * PME events only, disabling link interrupt. We avoid switching 762 * to PMEB mode as we don't have a status bit for that. 763 */ 764 if (device_may_wakeup(&phydev->mdio.dev)) { 765 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 766 RTL8211F_INER_PME); 767 if (ret < 0) 768 goto err; 769 770 /* Read the INSR to clear any pending interrupt */ 771 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 772 773 /* Reset the WoL to ensure that an event is picked up. 774 * Unless we do this, even if we receive another packet, 775 * we may not have a PME interrupt raised. 776 */ 777 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 778 RTL8211F_WOL_RST_RMSQ); 779 if (ret < 0) 780 goto err; 781 782 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 783 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 784 RTL8211F_WOL_RST_RMSQ, wol_rst); 785 if (ret < 0) 786 goto err; 787 788 wol_rst |= RTL8211F_WOL_RG_RSTB; 789 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 790 RTL8211F_WOL_RST_RMSQ, wol_rst); 791 } 792 793 err: 794 return ret; 795 } 796 797 static int rtl821x_resume(struct phy_device *phydev) 798 { 799 struct rtl821x_priv *priv = phydev->priv; 800 int ret; 801 802 if (!phydev->wol_enabled) 803 clk_prepare_enable(priv->clk); 804 805 ret = genphy_resume(phydev); 806 if (ret < 0) 807 return ret; 808 809 msleep(20); 810 811 return 0; 812 } 813 814 static int rtl8211f_resume(struct phy_device *phydev) 815 { 816 struct rtl821x_priv *priv = phydev->priv; 817 int ret; 818 819 ret = rtl821x_resume(phydev); 820 if (ret < 0) 821 return ret; 822 823 /* If the device was programmed for a PME event, restore the interrupt 824 * enable so phylib can receive link state interrupts. 825 */ 826 if (device_may_wakeup(&phydev->mdio.dev)) 827 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 828 829 return ret; 830 } 831 832 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 833 unsigned long rules) 834 { 835 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 836 BIT(TRIGGER_NETDEV_LINK_10) | 837 BIT(TRIGGER_NETDEV_LINK_100) | 838 BIT(TRIGGER_NETDEV_LINK_1000) | 839 BIT(TRIGGER_NETDEV_RX) | 840 BIT(TRIGGER_NETDEV_TX); 841 842 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 843 * - Link: Configurable subset of 10/100/1000 link rates 844 * - Active: Blink on activity, RX or TX is not differentiated 845 * The Active option has two modes, A and B: 846 * - A: Link and Active indication at configurable, but matching, 847 * subset of 10/100/1000 link rates 848 * - B: Link indication at configurable subset of 10/100/1000 link 849 * rates and Active indication always at all three 10+100+1000 850 * link rates. 851 * This code currently uses mode B only. 852 * 853 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 854 */ 855 856 if (index >= RTL8211x_LED_COUNT) 857 return -EINVAL; 858 859 /* Filter out any other unsupported triggers. */ 860 if (rules & ~mask) 861 return -EOPNOTSUPP; 862 863 /* RX and TX are not differentiated, either both are set or not set. */ 864 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 865 return -EOPNOTSUPP; 866 867 return 0; 868 } 869 870 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 871 unsigned long *rules) 872 { 873 int val; 874 875 if (index >= RTL8211x_LED_COUNT) 876 return -EINVAL; 877 878 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 879 if (val < 0) 880 return val; 881 882 val >>= RTL8211F_LEDCR_SHIFT * index; 883 val &= RTL8211F_LEDCR_MASK; 884 885 if (val & RTL8211F_LEDCR_LINK_10) 886 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 887 888 if (val & RTL8211F_LEDCR_LINK_100) 889 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 890 891 if (val & RTL8211F_LEDCR_LINK_1000) 892 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 893 894 if ((val & RTL8211F_LEDCR_LINK_10) && 895 (val & RTL8211F_LEDCR_LINK_100) && 896 (val & RTL8211F_LEDCR_LINK_1000)) { 897 __set_bit(TRIGGER_NETDEV_LINK, rules); 898 } 899 900 if (val & RTL8211F_LEDCR_ACT_TXRX) { 901 __set_bit(TRIGGER_NETDEV_RX, rules); 902 __set_bit(TRIGGER_NETDEV_TX, rules); 903 } 904 905 return 0; 906 } 907 908 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 909 unsigned long rules) 910 { 911 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 912 u16 reg = 0; 913 914 if (index >= RTL8211x_LED_COUNT) 915 return -EINVAL; 916 917 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 918 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 919 reg |= RTL8211F_LEDCR_LINK_10; 920 } 921 922 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 923 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 924 reg |= RTL8211F_LEDCR_LINK_100; 925 } 926 927 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 928 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 929 reg |= RTL8211F_LEDCR_LINK_1000; 930 } 931 932 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 933 test_bit(TRIGGER_NETDEV_TX, &rules)) { 934 reg |= RTL8211F_LEDCR_ACT_TXRX; 935 } 936 937 reg <<= RTL8211F_LEDCR_SHIFT * index; 938 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 939 940 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 941 } 942 943 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 944 unsigned long *rules) 945 { 946 int ret; 947 u16 cr1, cr2; 948 949 if (index >= RTL8211x_LED_COUNT) 950 return -EINVAL; 951 952 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 953 RTL8211E_LEDCR1); 954 if (ret < 0) 955 return ret; 956 957 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 958 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 959 __set_bit(TRIGGER_NETDEV_RX, rules); 960 __set_bit(TRIGGER_NETDEV_TX, rules); 961 } 962 963 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 964 RTL8211E_LEDCR2); 965 if (ret < 0) 966 return ret; 967 968 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 969 if (cr2 & RTL8211E_LEDCR2_LINK_10) 970 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 971 972 if (cr2 & RTL8211E_LEDCR2_LINK_100) 973 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 974 975 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 976 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 977 978 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 979 (cr2 & RTL8211E_LEDCR2_LINK_100) && 980 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 981 __set_bit(TRIGGER_NETDEV_LINK, rules); 982 } 983 984 return ret; 985 } 986 987 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 988 unsigned long rules) 989 { 990 const u16 cr1mask = 991 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 992 const u16 cr2mask = 993 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 994 u16 cr1 = 0, cr2 = 0; 995 int ret; 996 997 if (index >= RTL8211x_LED_COUNT) 998 return -EINVAL; 999 1000 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1001 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1002 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1003 } 1004 1005 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1006 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1007 RTL8211E_LEDCR1, cr1mask, cr1); 1008 if (ret < 0) 1009 return ret; 1010 1011 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1012 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1013 cr2 |= RTL8211E_LEDCR2_LINK_10; 1014 } 1015 1016 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1017 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1018 cr2 |= RTL8211E_LEDCR2_LINK_100; 1019 } 1020 1021 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1022 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1023 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1024 } 1025 1026 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1027 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1028 RTL8211E_LEDCR2, cr2mask, cr2); 1029 1030 return ret; 1031 } 1032 1033 static int rtl8211e_config_init(struct phy_device *phydev) 1034 { 1035 u16 val; 1036 1037 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1038 switch (phydev->interface) { 1039 case PHY_INTERFACE_MODE_RGMII: 1040 val = RTL8211E_CTRL_DELAY | 0; 1041 break; 1042 case PHY_INTERFACE_MODE_RGMII_ID: 1043 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1044 break; 1045 case PHY_INTERFACE_MODE_RGMII_RXID: 1046 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1047 break; 1048 case PHY_INTERFACE_MODE_RGMII_TXID: 1049 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1050 break; 1051 default: /* the rest of the modes imply leaving delays as is. */ 1052 return 0; 1053 } 1054 1055 /* According to a sample driver there is a 0x1c config register on the 1056 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1057 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1058 * The configuration register definition: 1059 * 14 = reserved 1060 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1061 * 12 = RX Delay, 11 = TX Delay 1062 * 10:0 = Test && debug settings reserved by realtek 1063 */ 1064 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1065 RTL8211E_RGMII_DELAY, 1066 RTL8211E_DELAY_MASK, val); 1067 } 1068 1069 static int rtl8211b_suspend(struct phy_device *phydev) 1070 { 1071 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1072 1073 return genphy_suspend(phydev); 1074 } 1075 1076 static int rtl8211b_resume(struct phy_device *phydev) 1077 { 1078 phy_write(phydev, MII_MMD_DATA, 0); 1079 1080 return genphy_resume(phydev); 1081 } 1082 1083 static int rtl8366rb_config_init(struct phy_device *phydev) 1084 { 1085 int ret; 1086 1087 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1088 RTL8366RB_POWER_SAVE_ON); 1089 if (ret) { 1090 dev_err(&phydev->mdio.dev, 1091 "error enabling power management\n"); 1092 } 1093 1094 return ret; 1095 } 1096 1097 /* get actual speed to cover the downshift case */ 1098 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1099 { 1100 /* bit 3 1101 * 0: Half Duplex 1102 * 1: Full Duplex 1103 */ 1104 if (val & RTL_VND2_PHYSR_DUPLEX) 1105 phydev->duplex = DUPLEX_FULL; 1106 else 1107 phydev->duplex = DUPLEX_HALF; 1108 1109 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1110 case 0x0000: 1111 phydev->speed = SPEED_10; 1112 break; 1113 case 0x0010: 1114 phydev->speed = SPEED_100; 1115 break; 1116 case 0x0020: 1117 phydev->speed = SPEED_1000; 1118 break; 1119 case 0x0200: 1120 phydev->speed = SPEED_10000; 1121 break; 1122 case 0x0210: 1123 phydev->speed = SPEED_2500; 1124 break; 1125 case 0x0220: 1126 phydev->speed = SPEED_5000; 1127 break; 1128 default: 1129 break; 1130 } 1131 1132 /* bit 11 1133 * 0: Slave Mode 1134 * 1: Master Mode 1135 */ 1136 if (phydev->speed >= 1000) { 1137 if (val & RTL_VND2_PHYSR_MASTER) 1138 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1139 else 1140 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1141 } else { 1142 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1143 } 1144 } 1145 1146 static int rtlgen_read_status(struct phy_device *phydev) 1147 { 1148 int ret, val; 1149 1150 ret = genphy_read_status(phydev); 1151 if (ret < 0) 1152 return ret; 1153 1154 if (!phydev->link) 1155 return 0; 1156 1157 val = phy_read_paged(phydev, RTL822X_VND2_TO_PAGE(RTL_VND2_PHYSR), 1158 RTL822X_VND2_TO_PAGE_REG(RTL_VND2_PHYSR)); 1159 if (val < 0) 1160 return val; 1161 1162 rtlgen_decode_physr(phydev, val); 1163 1164 return 0; 1165 } 1166 1167 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1168 { 1169 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1170 } 1171 1172 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1173 { 1174 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1175 val); 1176 } 1177 1178 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1179 { 1180 int ret; 1181 1182 if (devnum == MDIO_MMD_VEND2) 1183 ret = rtlgen_read_vend2(phydev, regnum); 1184 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1185 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1186 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1187 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1188 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1189 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1190 else 1191 ret = -EOPNOTSUPP; 1192 1193 return ret; 1194 } 1195 1196 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1197 u16 val) 1198 { 1199 int ret; 1200 1201 if (devnum == MDIO_MMD_VEND2) 1202 ret = rtlgen_write_vend2(phydev, regnum, val); 1203 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1204 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1205 else 1206 ret = -EOPNOTSUPP; 1207 1208 return ret; 1209 } 1210 1211 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1212 { 1213 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1214 1215 if (ret != -EOPNOTSUPP) 1216 return ret; 1217 1218 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1219 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1220 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1221 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1222 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1223 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1224 1225 return ret; 1226 } 1227 1228 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1229 u16 val) 1230 { 1231 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1232 1233 if (ret != -EOPNOTSUPP) 1234 return ret; 1235 1236 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1237 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1238 1239 return ret; 1240 } 1241 1242 static int rtl822x_probe(struct phy_device *phydev) 1243 { 1244 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1245 phydev->phy_id != RTL_GENERIC_PHYID) 1246 return rtl822x_hwmon_init(phydev); 1247 1248 return 0; 1249 } 1250 1251 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1252 * A mapping to use paged access needs to be used instead. 1253 * All other MMD devices can be accessed as usual. 1254 */ 1255 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1256 { 1257 int oldpage, ret, read_ret; 1258 u16 page; 1259 1260 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1261 * Clause-45 access is available 1262 */ 1263 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1264 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1265 phydev->is_c45, devnum, reg); 1266 1267 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1268 page = RTL822X_VND2_TO_PAGE(reg); 1269 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1270 if (oldpage < 0) 1271 return oldpage; 1272 1273 if (oldpage != page) { 1274 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1275 if (ret < 0) 1276 return ret; 1277 } 1278 1279 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1280 if (oldpage != page) { 1281 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1282 if (ret < 0) 1283 return ret; 1284 } 1285 1286 return read_ret; 1287 } 1288 1289 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1290 u16 val) 1291 { 1292 int oldpage, ret, write_ret; 1293 u16 page; 1294 1295 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1296 * Clause-45 access is available 1297 */ 1298 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1299 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1300 phydev->is_c45, devnum, reg, val); 1301 1302 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1303 page = RTL822X_VND2_TO_PAGE(reg); 1304 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1305 if (oldpage < 0) 1306 return oldpage; 1307 1308 if (oldpage != page) { 1309 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1310 if (ret < 0) 1311 return ret; 1312 } 1313 1314 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1315 if (oldpage != page) { 1316 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1317 if (ret < 0) 1318 return ret; 1319 } 1320 1321 return write_ret; 1322 } 1323 1324 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1325 { 1326 bool has_2500, has_sgmii; 1327 u16 mode; 1328 int ret; 1329 1330 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1331 phydev->host_interfaces) || 1332 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1333 1334 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1335 phydev->host_interfaces) || 1336 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1337 1338 /* fill in possible interfaces */ 1339 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1340 has_2500); 1341 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1342 has_sgmii); 1343 1344 if (!has_2500 && !has_sgmii) 1345 return 0; 1346 1347 /* determine SerDes option mode */ 1348 if (has_2500 && !has_sgmii) { 1349 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1350 phydev->rate_matching = RATE_MATCH_PAUSE; 1351 } else { 1352 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1353 phydev->rate_matching = RATE_MATCH_NONE; 1354 } 1355 1356 /* the following sequence with magic numbers sets up the SerDes 1357 * option mode 1358 */ 1359 1360 if (!gen1) { 1361 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1362 if (ret < 0) 1363 return ret; 1364 } 1365 1366 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1367 RTL822X_VND1_SERDES_OPTION, 1368 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1369 mode); 1370 if (gen1 || ret < 0) 1371 return ret; 1372 1373 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1374 if (ret < 0) 1375 return ret; 1376 1377 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1378 if (ret < 0) 1379 return ret; 1380 1381 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1382 } 1383 1384 static int rtl822x_config_init(struct phy_device *phydev) 1385 { 1386 return rtl822x_set_serdes_option_mode(phydev, true); 1387 } 1388 1389 static int rtl822xb_config_init(struct phy_device *phydev) 1390 { 1391 return rtl822x_set_serdes_option_mode(phydev, false); 1392 } 1393 1394 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1395 { 1396 int ret, poll; 1397 1398 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1399 if (ret < 0) 1400 return ret; 1401 1402 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1403 if (ret < 0) 1404 return ret; 1405 1406 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1407 RTL822X_VND1_SERDES_CMD_WRITE | 1408 RTL822X_VND1_SERDES_CMD_BUSY); 1409 if (ret < 0) 1410 return ret; 1411 1412 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1413 RTL822X_VND1_SERDES_CMD, poll, 1414 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1415 500, 100000, false); 1416 } 1417 1418 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1419 { 1420 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1421 (modes != LINK_INBAND_DISABLE) ? 1422 RTL822X_VND1_SERDES_INBAND_ENABLE : 1423 RTL822X_VND1_SERDES_INBAND_DISABLE); 1424 } 1425 1426 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1427 phy_interface_t interface) 1428 { 1429 switch (interface) { 1430 case PHY_INTERFACE_MODE_2500BASEX: 1431 case PHY_INTERFACE_MODE_SGMII: 1432 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1433 default: 1434 return 0; 1435 } 1436 } 1437 1438 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1439 phy_interface_t iface) 1440 { 1441 int val; 1442 1443 /* Only rate matching at 2500base-x */ 1444 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1445 return RATE_MATCH_NONE; 1446 1447 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1448 if (val < 0) 1449 return val; 1450 1451 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1452 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1453 return RATE_MATCH_PAUSE; 1454 1455 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1456 return RATE_MATCH_NONE; 1457 } 1458 1459 static int rtl822x_get_features(struct phy_device *phydev) 1460 { 1461 int val; 1462 1463 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1464 if (val < 0) 1465 return val; 1466 1467 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1468 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1469 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1470 phydev->supported, val & MDIO_PMA_SPEED_5G); 1471 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1472 phydev->supported, val & MDIO_SPEED_10G); 1473 1474 return genphy_read_abilities(phydev); 1475 } 1476 1477 static int rtl822x_config_aneg(struct phy_device *phydev) 1478 { 1479 int ret = 0; 1480 1481 if (phydev->autoneg == AUTONEG_ENABLE) { 1482 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1483 1484 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1485 RTL_MDIO_AN_10GBT_CTRL, 1486 MDIO_AN_10GBT_CTRL_ADV2_5G | 1487 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1488 if (ret < 0) 1489 return ret; 1490 } 1491 1492 return __genphy_config_aneg(phydev, ret); 1493 } 1494 1495 static void rtl822xb_update_interface(struct phy_device *phydev) 1496 { 1497 int val; 1498 1499 if (!phydev->link) 1500 return; 1501 1502 /* Change interface according to serdes mode */ 1503 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1504 if (val < 0) 1505 return; 1506 1507 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1508 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1509 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1510 break; 1511 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1512 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1513 break; 1514 } 1515 } 1516 1517 static int rtl822x_read_status(struct phy_device *phydev) 1518 { 1519 int lpadv, ret; 1520 1521 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1522 1523 ret = rtlgen_read_status(phydev); 1524 if (ret < 0) 1525 return ret; 1526 1527 if (phydev->autoneg == AUTONEG_DISABLE || 1528 !phydev->autoneg_complete) 1529 return 0; 1530 1531 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1532 if (lpadv < 0) 1533 return lpadv; 1534 1535 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1536 1537 return 0; 1538 } 1539 1540 static int rtl822xb_read_status(struct phy_device *phydev) 1541 { 1542 int ret; 1543 1544 ret = rtl822x_read_status(phydev); 1545 if (ret < 0) 1546 return ret; 1547 1548 rtl822xb_update_interface(phydev); 1549 1550 return 0; 1551 } 1552 1553 static int rtl822x_c45_get_features(struct phy_device *phydev) 1554 { 1555 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1556 phydev->supported); 1557 1558 return genphy_c45_pma_read_abilities(phydev); 1559 } 1560 1561 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1562 { 1563 bool changed = false; 1564 int ret, val; 1565 1566 if (phydev->autoneg == AUTONEG_DISABLE) 1567 return genphy_c45_pma_setup_forced(phydev); 1568 1569 ret = genphy_c45_an_config_aneg(phydev); 1570 if (ret < 0) 1571 return ret; 1572 if (ret > 0) 1573 changed = true; 1574 1575 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1576 1577 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1578 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1579 RTL822X_VND2_C22_REG(MII_CTRL1000), 1580 ADVERTISE_1000FULL, val); 1581 if (ret < 0) 1582 return ret; 1583 if (ret > 0) 1584 changed = true; 1585 1586 return genphy_c45_check_and_restart_aneg(phydev, changed); 1587 } 1588 1589 static int rtl822x_c45_read_status(struct phy_device *phydev) 1590 { 1591 int ret, val; 1592 1593 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1594 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1595 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1596 RTL822X_VND2_C22_REG(MII_STAT1000)); 1597 if (val < 0) 1598 return val; 1599 } else { 1600 val = 0; 1601 } 1602 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1603 1604 ret = genphy_c45_read_status(phydev); 1605 if (ret < 0) 1606 return ret; 1607 1608 if (!phydev->link) { 1609 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1610 return 0; 1611 } 1612 1613 /* Read actual speed from vendor register. */ 1614 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1615 if (val < 0) 1616 return val; 1617 1618 rtlgen_decode_physr(phydev, val); 1619 1620 return 0; 1621 } 1622 1623 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1624 { 1625 int ret, val; 1626 1627 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1628 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1629 if (ret < 0) 1630 return ret; 1631 1632 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1633 MDIO_CTRL1, val, 1634 !(val & MDIO_CTRL1_RESET), 1635 5000, 100000, true); 1636 } 1637 1638 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1639 { 1640 int ret; 1641 1642 ret = rtl822x_c45_read_status(phydev); 1643 if (ret < 0) 1644 return ret; 1645 1646 rtl822xb_update_interface(phydev); 1647 1648 return 0; 1649 } 1650 1651 static int rtl8224_cable_test_start(struct phy_device *phydev) 1652 { 1653 u32 val; 1654 int ret; 1655 1656 /* disable auto-negotiation and force 1000/Full */ 1657 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1658 RTL822X_VND2_C22_REG(MII_BMCR), 1659 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1660 BMCR_SPEED1000 | BMCR_FULLDPLX); 1661 if (ret) 1662 return ret; 1663 1664 mdelay(500); 1665 1666 /* trigger cable test */ 1667 val = RTL8224_MII_RTCT_ENABLE; 1668 val |= RTL8224_MII_RTCT_PAIR_A; 1669 val |= RTL8224_MII_RTCT_PAIR_B; 1670 val |= RTL8224_MII_RTCT_PAIR_C; 1671 val |= RTL8224_MII_RTCT_PAIR_D; 1672 1673 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1674 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1675 RTL8224_MII_RTCT_DONE, val); 1676 } 1677 1678 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1679 { 1680 int ret; 1681 1682 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1683 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1684 reg); 1685 if (ret) 1686 return ret; 1687 1688 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1689 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1690 } 1691 1692 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1693 { 1694 int cable_len; 1695 u32 reg_len; 1696 int ret; 1697 u32 cm; 1698 1699 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1700 1701 ret = rtl8224_sram_read(phydev, reg_len); 1702 if (ret < 0) 1703 return ret; 1704 1705 cable_len = ret & 0xff00; 1706 1707 ret = rtl8224_sram_read(phydev, reg_len + 1); 1708 if (ret < 0) 1709 return ret; 1710 1711 cable_len |= (ret & 0xff00) >> 8; 1712 1713 cable_len -= 620; 1714 cable_len = max(cable_len, 0); 1715 1716 cm = cable_len * 100 / 78; 1717 1718 return cm; 1719 } 1720 1721 static int rtl8224_cable_test_result_trans(u32 result) 1722 { 1723 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1724 return -EBUSY; 1725 1726 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1727 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1728 1729 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1730 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1731 1732 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1733 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1734 1735 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1736 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1737 1738 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1739 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1740 1741 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1742 } 1743 1744 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1745 { 1746 int fault_rslt; 1747 int ret; 1748 1749 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1750 if (ret < 0) 1751 return ret; 1752 1753 fault_rslt = rtl8224_cable_test_result_trans(ret); 1754 if (fault_rslt < 0) 1755 return 0; 1756 1757 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1758 if (ret < 0) 1759 return ret; 1760 1761 switch (fault_rslt) { 1762 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1763 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1764 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1765 ret = rtl8224_pair_len_get(phydev, pair); 1766 if (ret < 0) 1767 return ret; 1768 1769 return ethnl_cable_test_fault_length(phydev, pair, ret); 1770 default: 1771 return 0; 1772 } 1773 } 1774 1775 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1776 { 1777 unsigned int pair; 1778 int ret; 1779 1780 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1781 ret = rtl8224_cable_test_report_pair(phydev, pair); 1782 if (ret == -EBUSY) { 1783 *finished = false; 1784 return 0; 1785 } 1786 1787 if (ret < 0) 1788 return ret; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1795 { 1796 int ret; 1797 1798 *finished = false; 1799 1800 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1801 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1802 if (ret < 0) 1803 return ret; 1804 1805 if (!(ret & RTL8224_MII_RTCT_DONE)) 1806 return 0; 1807 1808 *finished = true; 1809 1810 return rtl8224_cable_test_report(phydev, finished); 1811 } 1812 1813 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1814 { 1815 int val; 1816 1817 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1818 val = phy_read(phydev, 0x13); 1819 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1820 1821 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1822 } 1823 1824 /* On internal PHY's MMD reads over C22 always return 0. 1825 * Check a MMD register which is known to be non-zero. 1826 */ 1827 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1828 { 1829 int val; 1830 1831 phy_lock_mdio_bus(phydev); 1832 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1833 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1834 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1835 val = __phy_read(phydev, MII_MMD_DATA); 1836 phy_unlock_mdio_bus(phydev); 1837 1838 return val > 0; 1839 } 1840 1841 static int rtlgen_match_phy_device(struct phy_device *phydev, 1842 const struct phy_driver *phydrv) 1843 { 1844 return phydev->phy_id == RTL_GENERIC_PHYID && 1845 !rtlgen_supports_2_5gbps(phydev); 1846 } 1847 1848 static int rtl8226_match_phy_device(struct phy_device *phydev, 1849 const struct phy_driver *phydrv) 1850 { 1851 return phydev->phy_id == RTL_GENERIC_PHYID && 1852 rtlgen_supports_2_5gbps(phydev) && 1853 rtlgen_supports_mmd(phydev); 1854 } 1855 1856 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1857 bool is_c45) 1858 { 1859 if (phydev->is_c45) 1860 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1861 else 1862 return !is_c45 && (id == phydev->phy_id); 1863 } 1864 1865 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1866 const struct phy_driver *phydrv) 1867 { 1868 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1869 } 1870 1871 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1872 const struct phy_driver *phydrv) 1873 { 1874 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1875 } 1876 1877 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1878 const struct phy_driver *phydrv) 1879 { 1880 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1881 } 1882 1883 static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev, 1884 const struct phy_driver *phydrv) 1885 { 1886 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1887 } 1888 1889 static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev, 1890 const struct phy_driver *phydrv) 1891 { 1892 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true); 1893 } 1894 1895 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1896 const struct phy_driver *phydrv) 1897 { 1898 if (phydev->is_c45) 1899 return false; 1900 1901 switch (phydev->phy_id) { 1902 case RTL_GENERIC_PHYID: 1903 case RTL_8221B: 1904 case RTL_8251B: 1905 case RTL_8261C: 1906 case 0x001cc841: 1907 break; 1908 default: 1909 return false; 1910 } 1911 1912 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1913 } 1914 1915 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1916 const struct phy_driver *phydrv) 1917 { 1918 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1919 } 1920 1921 static int rtlgen_resume(struct phy_device *phydev) 1922 { 1923 int ret = genphy_resume(phydev); 1924 1925 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1926 msleep(20); 1927 1928 return ret; 1929 } 1930 1931 static int rtlgen_c45_resume(struct phy_device *phydev) 1932 { 1933 int ret = genphy_c45_pma_resume(phydev); 1934 1935 msleep(20); 1936 1937 return ret; 1938 } 1939 1940 static int rtl9000a_config_init(struct phy_device *phydev) 1941 { 1942 phydev->autoneg = AUTONEG_DISABLE; 1943 phydev->speed = SPEED_100; 1944 phydev->duplex = DUPLEX_FULL; 1945 1946 return 0; 1947 } 1948 1949 static int rtl9000a_config_aneg(struct phy_device *phydev) 1950 { 1951 int ret; 1952 u16 ctl = 0; 1953 1954 switch (phydev->master_slave_set) { 1955 case MASTER_SLAVE_CFG_MASTER_FORCE: 1956 ctl |= CTL1000_AS_MASTER; 1957 break; 1958 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1959 break; 1960 case MASTER_SLAVE_CFG_UNKNOWN: 1961 case MASTER_SLAVE_CFG_UNSUPPORTED: 1962 return 0; 1963 default: 1964 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1965 return -EOPNOTSUPP; 1966 } 1967 1968 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1969 if (ret == 1) 1970 ret = genphy_soft_reset(phydev); 1971 1972 return ret; 1973 } 1974 1975 static int rtl9000a_read_status(struct phy_device *phydev) 1976 { 1977 int ret; 1978 1979 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1980 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1981 1982 ret = genphy_update_link(phydev); 1983 if (ret) 1984 return ret; 1985 1986 ret = phy_read(phydev, MII_CTRL1000); 1987 if (ret < 0) 1988 return ret; 1989 if (ret & CTL1000_AS_MASTER) 1990 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1991 else 1992 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1993 1994 ret = phy_read(phydev, MII_STAT1000); 1995 if (ret < 0) 1996 return ret; 1997 if (ret & LPA_1000MSRES) 1998 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1999 else 2000 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2001 2002 return 0; 2003 } 2004 2005 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2006 { 2007 int err; 2008 2009 err = phy_read(phydev, RTL8211F_INSR); 2010 2011 return (err < 0) ? err : 0; 2012 } 2013 2014 static int rtl9000a_config_intr(struct phy_device *phydev) 2015 { 2016 u16 val; 2017 int err; 2018 2019 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2020 err = rtl9000a_ack_interrupt(phydev); 2021 if (err) 2022 return err; 2023 2024 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2025 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2026 } else { 2027 val = ~0; 2028 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2029 if (err) 2030 return err; 2031 2032 err = rtl9000a_ack_interrupt(phydev); 2033 } 2034 2035 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2036 } 2037 2038 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2039 { 2040 int irq_status; 2041 2042 irq_status = phy_read(phydev, RTL8211F_INSR); 2043 if (irq_status < 0) { 2044 phy_error(phydev); 2045 return IRQ_NONE; 2046 } 2047 2048 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2049 return IRQ_NONE; 2050 2051 phy_trigger_machine(phydev); 2052 2053 return IRQ_HANDLED; 2054 } 2055 2056 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2057 { 2058 int err; 2059 2060 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2061 2062 return (err < 0) ? err : 0; 2063 } 2064 2065 static int rtl8221b_config_intr(struct phy_device *phydev) 2066 { 2067 int err; 2068 2069 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2070 err = rtl8221b_ack_interrupt(phydev); 2071 if (err) 2072 return err; 2073 2074 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2075 RTL8221B_VND2_INER_LINK_STATUS); 2076 } else { 2077 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2078 RTL8221B_VND2_INER, 0); 2079 if (err) 2080 return err; 2081 2082 err = rtl8221b_ack_interrupt(phydev); 2083 } 2084 2085 return err; 2086 } 2087 2088 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2089 { 2090 int err; 2091 2092 err = rtl8221b_ack_interrupt(phydev); 2093 if (err) { 2094 phy_error(phydev); 2095 return IRQ_NONE; 2096 } 2097 2098 phy_trigger_machine(phydev); 2099 2100 return IRQ_HANDLED; 2101 } 2102 2103 static struct phy_driver realtek_drvs[] = { 2104 { 2105 PHY_ID_MATCH_EXACT(0x00008201), 2106 .name = "RTL8201CP Ethernet", 2107 .read_page = rtl821x_read_page, 2108 .write_page = rtl821x_write_page, 2109 }, { 2110 PHY_ID_MATCH_EXACT(0x001cc816), 2111 .name = "RTL8201F Fast Ethernet", 2112 .config_intr = &rtl8201_config_intr, 2113 .handle_interrupt = rtl8201_handle_interrupt, 2114 .suspend = genphy_suspend, 2115 .resume = genphy_resume, 2116 .read_page = rtl821x_read_page, 2117 .write_page = rtl821x_write_page, 2118 }, { 2119 PHY_ID_MATCH_MODEL(0x001cc880), 2120 .name = "RTL8208 Fast Ethernet", 2121 .read_mmd = genphy_read_mmd_unsupported, 2122 .write_mmd = genphy_write_mmd_unsupported, 2123 .suspend = genphy_suspend, 2124 .resume = genphy_resume, 2125 .read_page = rtl821x_read_page, 2126 .write_page = rtl821x_write_page, 2127 }, { 2128 PHY_ID_MATCH_EXACT(0x001cc910), 2129 .name = "RTL8211 Gigabit Ethernet", 2130 .config_aneg = rtl8211_config_aneg, 2131 .read_mmd = &genphy_read_mmd_unsupported, 2132 .write_mmd = &genphy_write_mmd_unsupported, 2133 .read_page = rtl821x_read_page, 2134 .write_page = rtl821x_write_page, 2135 }, { 2136 PHY_ID_MATCH_EXACT(0x001cc912), 2137 .name = "RTL8211B Gigabit Ethernet", 2138 .config_intr = &rtl8211b_config_intr, 2139 .handle_interrupt = rtl821x_handle_interrupt, 2140 .read_mmd = &genphy_read_mmd_unsupported, 2141 .write_mmd = &genphy_write_mmd_unsupported, 2142 .suspend = rtl8211b_suspend, 2143 .resume = rtl8211b_resume, 2144 .read_page = rtl821x_read_page, 2145 .write_page = rtl821x_write_page, 2146 }, { 2147 PHY_ID_MATCH_EXACT(0x001cc913), 2148 .name = "RTL8211C Gigabit Ethernet", 2149 .config_init = rtl8211c_config_init, 2150 .read_mmd = &genphy_read_mmd_unsupported, 2151 .write_mmd = &genphy_write_mmd_unsupported, 2152 .read_page = rtl821x_read_page, 2153 .write_page = rtl821x_write_page, 2154 }, { 2155 PHY_ID_MATCH_EXACT(0x001cc914), 2156 .name = "RTL8211DN Gigabit Ethernet", 2157 .config_intr = rtl8211e_config_intr, 2158 .handle_interrupt = rtl821x_handle_interrupt, 2159 .suspend = genphy_suspend, 2160 .resume = genphy_resume, 2161 .read_page = rtl821x_read_page, 2162 .write_page = rtl821x_write_page, 2163 }, { 2164 PHY_ID_MATCH_EXACT(0x001cc915), 2165 .name = "RTL8211E Gigabit Ethernet", 2166 .config_init = &rtl8211e_config_init, 2167 .config_intr = &rtl8211e_config_intr, 2168 .handle_interrupt = rtl821x_handle_interrupt, 2169 .suspend = genphy_suspend, 2170 .resume = genphy_resume, 2171 .read_page = rtl821x_read_page, 2172 .write_page = rtl821x_write_page, 2173 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2174 .led_hw_control_get = rtl8211e_led_hw_control_get, 2175 .led_hw_control_set = rtl8211e_led_hw_control_set, 2176 }, { 2177 PHY_ID_MATCH_EXACT(0x001cc916), 2178 .name = "RTL8211F Gigabit Ethernet", 2179 .probe = rtl8211f_probe, 2180 .config_init = &rtl8211f_config_init, 2181 .read_status = rtlgen_read_status, 2182 .config_intr = &rtl8211f_config_intr, 2183 .handle_interrupt = rtl8211f_handle_interrupt, 2184 .set_wol = rtl8211f_set_wol, 2185 .get_wol = rtl8211f_get_wol, 2186 .suspend = rtl8211f_suspend, 2187 .resume = rtl8211f_resume, 2188 .read_page = rtl821x_read_page, 2189 .write_page = rtl821x_write_page, 2190 .flags = PHY_ALWAYS_CALL_SUSPEND, 2191 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2192 .led_hw_control_get = rtl8211f_led_hw_control_get, 2193 .led_hw_control_set = rtl8211f_led_hw_control_set, 2194 }, { 2195 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2196 .name = "RTL8211F-VD Gigabit Ethernet", 2197 .probe = rtl821x_probe, 2198 .config_init = &rtl8211f_config_init, 2199 .read_status = rtlgen_read_status, 2200 .config_intr = &rtl8211f_config_intr, 2201 .handle_interrupt = rtl8211f_handle_interrupt, 2202 .suspend = rtl821x_suspend, 2203 .resume = rtl821x_resume, 2204 .read_page = rtl821x_read_page, 2205 .write_page = rtl821x_write_page, 2206 .flags = PHY_ALWAYS_CALL_SUSPEND, 2207 }, { 2208 .name = "Generic FE-GE Realtek PHY", 2209 .match_phy_device = rtlgen_match_phy_device, 2210 .read_status = rtlgen_read_status, 2211 .suspend = genphy_suspend, 2212 .resume = rtlgen_resume, 2213 .read_page = rtl821x_read_page, 2214 .write_page = rtl821x_write_page, 2215 .read_mmd = rtlgen_read_mmd, 2216 .write_mmd = rtlgen_write_mmd, 2217 }, { 2218 .name = "RTL8226 2.5Gbps PHY", 2219 .match_phy_device = rtl8226_match_phy_device, 2220 .get_features = rtl822x_get_features, 2221 .config_aneg = rtl822x_config_aneg, 2222 .read_status = rtl822x_read_status, 2223 .suspend = genphy_suspend, 2224 .resume = rtlgen_resume, 2225 .read_page = rtl821x_read_page, 2226 .write_page = rtl821x_write_page, 2227 .read_mmd = rtl822xb_read_mmd, 2228 .write_mmd = rtl822xb_write_mmd, 2229 }, { 2230 .match_phy_device = rtl8221b_match_phy_device, 2231 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2232 .get_features = rtl822x_get_features, 2233 .config_aneg = rtl822x_config_aneg, 2234 .config_init = rtl822xb_config_init, 2235 .inband_caps = rtl822x_inband_caps, 2236 .config_inband = rtl822x_config_inband, 2237 .get_rate_matching = rtl822xb_get_rate_matching, 2238 .read_status = rtl822xb_read_status, 2239 .suspend = genphy_suspend, 2240 .resume = rtlgen_resume, 2241 .read_page = rtl821x_read_page, 2242 .write_page = rtl821x_write_page, 2243 .read_mmd = rtl822xb_read_mmd, 2244 .write_mmd = rtl822xb_write_mmd, 2245 }, { 2246 PHY_ID_MATCH_EXACT(0x001cc838), 2247 .name = "RTL8226-CG 2.5Gbps PHY", 2248 .soft_reset = rtl822x_c45_soft_reset, 2249 .get_features = rtl822x_c45_get_features, 2250 .config_aneg = rtl822x_c45_config_aneg, 2251 .config_init = rtl822x_config_init, 2252 .inband_caps = rtl822x_inband_caps, 2253 .config_inband = rtl822x_config_inband, 2254 .read_status = rtl822xb_c45_read_status, 2255 .suspend = genphy_c45_pma_suspend, 2256 .resume = rtlgen_c45_resume, 2257 .read_mmd = rtl822xb_read_mmd, 2258 .write_mmd = rtl822xb_write_mmd, 2259 }, { 2260 PHY_ID_MATCH_EXACT(0x001cc848), 2261 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2262 .get_features = rtl822x_get_features, 2263 .config_aneg = rtl822x_config_aneg, 2264 .config_init = rtl822xb_config_init, 2265 .inband_caps = rtl822x_inband_caps, 2266 .config_inband = rtl822x_config_inband, 2267 .get_rate_matching = rtl822xb_get_rate_matching, 2268 .read_status = rtl822xb_read_status, 2269 .suspend = genphy_suspend, 2270 .resume = rtlgen_resume, 2271 .read_page = rtl821x_read_page, 2272 .write_page = rtl821x_write_page, 2273 .read_mmd = rtl822xb_read_mmd, 2274 .write_mmd = rtl822xb_write_mmd, 2275 }, { 2276 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 2277 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 2278 .probe = rtl822x_probe, 2279 .get_features = rtl822x_get_features, 2280 .config_aneg = rtl822x_config_aneg, 2281 .config_init = rtl822xb_config_init, 2282 .inband_caps = rtl822x_inband_caps, 2283 .config_inband = rtl822x_config_inband, 2284 .get_rate_matching = rtl822xb_get_rate_matching, 2285 .read_status = rtl822xb_read_status, 2286 .suspend = genphy_suspend, 2287 .resume = rtlgen_resume, 2288 .read_page = rtl821x_read_page, 2289 .write_page = rtl821x_write_page, 2290 .read_mmd = rtl822xb_read_mmd, 2291 .write_mmd = rtl822xb_write_mmd, 2292 }, { 2293 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 2294 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 2295 .config_intr = rtl8221b_config_intr, 2296 .handle_interrupt = rtl8221b_handle_interrupt, 2297 .probe = rtl822x_probe, 2298 .config_init = rtl822xb_config_init, 2299 .inband_caps = rtl822x_inband_caps, 2300 .config_inband = rtl822x_config_inband, 2301 .get_rate_matching = rtl822xb_get_rate_matching, 2302 .get_features = rtl822x_c45_get_features, 2303 .config_aneg = rtl822x_c45_config_aneg, 2304 .read_status = rtl822xb_c45_read_status, 2305 .suspend = genphy_c45_pma_suspend, 2306 .resume = rtlgen_c45_resume, 2307 }, { 2308 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device, 2309 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 2310 .probe = rtl822x_probe, 2311 .get_features = rtl822x_get_features, 2312 .config_aneg = rtl822x_config_aneg, 2313 .config_init = rtl822xb_config_init, 2314 .inband_caps = rtl822x_inband_caps, 2315 .config_inband = rtl822x_config_inband, 2316 .get_rate_matching = rtl822xb_get_rate_matching, 2317 .read_status = rtl822xb_read_status, 2318 .suspend = genphy_suspend, 2319 .resume = rtlgen_resume, 2320 .read_page = rtl821x_read_page, 2321 .write_page = rtl821x_write_page, 2322 .read_mmd = rtl822xb_read_mmd, 2323 .write_mmd = rtl822xb_write_mmd, 2324 }, { 2325 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device, 2326 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)", 2327 .config_intr = rtl8221b_config_intr, 2328 .handle_interrupt = rtl8221b_handle_interrupt, 2329 .probe = rtl822x_probe, 2330 .config_init = rtl822xb_config_init, 2331 .inband_caps = rtl822x_inband_caps, 2332 .config_inband = rtl822x_config_inband, 2333 .get_rate_matching = rtl822xb_get_rate_matching, 2334 .get_features = rtl822x_c45_get_features, 2335 .config_aneg = rtl822x_c45_config_aneg, 2336 .read_status = rtl822xb_c45_read_status, 2337 .suspend = genphy_c45_pma_suspend, 2338 .resume = rtlgen_c45_resume, 2339 }, { 2340 .match_phy_device = rtl8251b_c45_match_phy_device, 2341 .name = "RTL8251B 5Gbps PHY", 2342 .probe = rtl822x_probe, 2343 .get_features = rtl822x_get_features, 2344 .config_aneg = rtl822x_config_aneg, 2345 .read_status = rtl822x_read_status, 2346 .suspend = genphy_suspend, 2347 .resume = rtlgen_resume, 2348 .read_page = rtl821x_read_page, 2349 .write_page = rtl821x_write_page, 2350 }, { 2351 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2352 .name = "Realtek Internal NBASE-T PHY", 2353 .flags = PHY_IS_INTERNAL, 2354 .probe = rtl822x_probe, 2355 .get_features = rtl822x_get_features, 2356 .config_aneg = rtl822x_config_aneg, 2357 .read_status = rtl822x_read_status, 2358 .suspend = genphy_suspend, 2359 .resume = rtlgen_resume, 2360 .read_page = rtl821x_read_page, 2361 .write_page = rtl821x_write_page, 2362 .read_mmd = rtl822x_read_mmd, 2363 .write_mmd = rtl822x_write_mmd, 2364 }, { 2365 PHY_ID_MATCH_EXACT(0x001ccad0), 2366 .name = "RTL8224 2.5Gbps PHY", 2367 .flags = PHY_POLL_CABLE_TEST, 2368 .get_features = rtl822x_c45_get_features, 2369 .config_aneg = rtl822x_c45_config_aneg, 2370 .read_status = rtl822x_c45_read_status, 2371 .suspend = genphy_c45_pma_suspend, 2372 .resume = rtlgen_c45_resume, 2373 .cable_test_start = rtl8224_cable_test_start, 2374 .cable_test_get_status = rtl8224_cable_test_get_status, 2375 }, { 2376 PHY_ID_MATCH_EXACT(0x001cc961), 2377 .name = "RTL8366RB Gigabit Ethernet", 2378 .config_init = &rtl8366rb_config_init, 2379 /* These interrupts are handled by the irq controller 2380 * embedded inside the RTL8366RB, they get unmasked when the 2381 * irq is requested and ACKed by reading the status register, 2382 * which is done by the irqchip code. 2383 */ 2384 .config_intr = genphy_no_config_intr, 2385 .handle_interrupt = genphy_handle_interrupt_no_ack, 2386 .suspend = genphy_suspend, 2387 .resume = genphy_resume, 2388 }, { 2389 PHY_ID_MATCH_EXACT(0x001ccb00), 2390 .name = "RTL9000AA_RTL9000AN Ethernet", 2391 .features = PHY_BASIC_T1_FEATURES, 2392 .config_init = rtl9000a_config_init, 2393 .config_aneg = rtl9000a_config_aneg, 2394 .read_status = rtl9000a_read_status, 2395 .config_intr = rtl9000a_config_intr, 2396 .handle_interrupt = rtl9000a_handle_interrupt, 2397 .suspend = genphy_suspend, 2398 .resume = genphy_resume, 2399 .read_page = rtl821x_read_page, 2400 .write_page = rtl821x_write_page, 2401 }, { 2402 PHY_ID_MATCH_EXACT(0x001cc942), 2403 .name = "RTL8365MB-VC Gigabit Ethernet", 2404 /* Interrupt handling analogous to RTL8366RB */ 2405 .config_intr = genphy_no_config_intr, 2406 .handle_interrupt = genphy_handle_interrupt_no_ack, 2407 .suspend = genphy_suspend, 2408 .resume = genphy_resume, 2409 }, { 2410 PHY_ID_MATCH_EXACT(0x001cc960), 2411 .name = "RTL8366S Gigabit Ethernet", 2412 .suspend = genphy_suspend, 2413 .resume = genphy_resume, 2414 .read_mmd = genphy_read_mmd_unsupported, 2415 .write_mmd = genphy_write_mmd_unsupported, 2416 }, 2417 }; 2418 2419 module_phy_driver(realtek_drvs); 2420 2421 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2422 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2423 { } 2424 }; 2425 2426 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2427