1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 #include <net/phy/realtek_phy.h> 21 22 #include "../phylib.h" 23 #include "realtek.h" 24 25 #define RTL8201F_IER_PAGE 0x07 26 #define RTL8201F_IER 0x13 27 #define RTL8201F_IER_LINK BIT(13) 28 #define RTL8201F_IER_DUPLEX BIT(12) 29 #define RTL8201F_IER_ANERR BIT(11) 30 #define RTL8201F_IER_MASK (RTL8201F_IER_ANERR | \ 31 RTL8201F_IER_DUPLEX | \ 32 RTL8201F_IER_LINK) 33 34 #define RTL8201F_ISR 0x1e 35 #define RTL8201F_ISR_ANERR BIT(15) 36 #define RTL8201F_ISR_DUPLEX BIT(13) 37 #define RTL8201F_ISR_LINK BIT(11) 38 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 39 RTL8201F_ISR_DUPLEX | \ 40 RTL8201F_ISR_LINK) 41 42 #define RTL821x_INER 0x12 43 #define RTL8211B_INER_SPEED BIT(14) 44 #define RTL8211B_INER_DUPLEX BIT(13) 45 #define RTL8211B_INER_LINK_STATUS BIT(10) 46 #define RTL8211B_INER_INIT (RTL8211B_INER_SPEED | \ 47 RTL8211B_INER_DUPLEX | \ 48 RTL8211B_INER_LINK_STATUS) 49 #define RTL8211E_INER_LINK_STATUS BIT(10) 50 #define RTL8211F_INER_PME BIT(7) 51 #define RTL8211F_INER_LINK_STATUS BIT(4) 52 53 #define RTL821x_INSR 0x13 54 55 #define RTL821x_EXT_PAGE_SELECT 0x1e 56 57 #define RTL821x_PAGE_SELECT 0x1f 58 #define RTL821x_SET_EXT_PAGE 0x07 59 60 /* RTL8211E extension page 44/0x2c */ 61 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 62 #define RTL8211E_LEDCR1 0x1a 63 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 64 #define RTL8211E_LEDCR1_MASK BIT(4) 65 #define RTL8211E_LEDCR1_SHIFT 1 66 67 #define RTL8211E_LEDCR2 0x1c 68 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 69 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 70 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 71 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 72 #define RTL8211E_LEDCR2_SHIFT 4 73 74 /* RTL8211E extension page 164/0xa4 */ 75 #define RTL8211E_RGMII_EXT_PAGE 0xa4 76 #define RTL8211E_RGMII_DELAY 0x1c 77 #define RTL8211E_CTRL_DELAY BIT(13) 78 #define RTL8211E_TX_DELAY BIT(12) 79 #define RTL8211E_RX_DELAY BIT(11) 80 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 81 82 /* RTL8211F PHY configuration */ 83 #define RTL8211F_PHYCR1 0x18 84 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 85 #define RTL8211F_ALDPS_ENABLE BIT(2) 86 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 87 88 #define RTL8211F_PHYCR2 0x19 89 #define RTL8211F_CLKOUT_EN BIT(0) 90 #define RTL8211F_SYSCLK_SSC_EN BIT(3) 91 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 92 #define RTL8211F_CLKOUT_SSC_EN BIT(7) 93 #define RTL8211F_CLKOUT_SSC_CAP GENMASK(13, 12) 94 95 #define RTL8211F_INSR 0x1d 96 97 /* RTL8211F SSC settings */ 98 #define RTL8211F_SSC_PAGE 0xc44 99 #define RTL8211F_SSC_RXC 0x13 100 #define RTL8211F_SSC_SYSCLK 0x17 101 102 /* RTL8211F LED configuration */ 103 #define RTL8211F_LEDCR_PAGE 0xd04 104 #define RTL8211F_LEDCR 0x10 105 #define RTL8211F_LEDCR_MODE BIT(15) 106 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 107 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 108 #define RTL8211F_LEDCR_LINK_100 BIT(1) 109 #define RTL8211F_LEDCR_LINK_10 BIT(0) 110 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 111 #define RTL8211F_LEDCR_SHIFT 5 112 113 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 114 * to undocumented register pages. The names here do not reflect the datasheet. 115 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 116 */ 117 #define RTL8211FVD_CLKOUT_PAGE 0xd05 118 #define RTL8211FVD_CLKOUT_REG 0x11 119 #define RTL8211FVD_CLKOUT_EN BIT(8) 120 121 /* RTL8211F RGMII configuration */ 122 #define RTL8211F_RGMII_PAGE 0xd08 123 124 #define RTL8211F_TXCR 0x11 125 #define RTL8211F_TX_DELAY BIT(8) 126 127 #define RTL8211F_RXCR 0x15 128 #define RTL8211F_RX_DELAY BIT(3) 129 130 /* RTL8211F WOL settings */ 131 #define RTL8211F_WOL_PAGE 0xd8a 132 #define RTL8211F_WOL_SETTINGS_EVENTS 16 133 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 134 #define RTL8211F_WOL_RST_RMSQ 17 135 #define RTL8211F_WOL_RG_RSTB BIT(15) 136 #define RTL8211F_WOL_RMSQ 0x1fff 137 138 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 139 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 140 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 141 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 142 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 143 144 #define RTL822X_VND1_SERDES_OPTION 0x697a 145 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 146 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 147 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 148 149 #define RTL822X_VND1_SERDES_CTRL3 0x7580 150 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 151 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 152 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 153 154 #define RTL822X_VND1_SERDES_CMD 0x7587 155 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 156 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 157 #define RTL822X_VND1_SERDES_ADDR 0x7588 158 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 159 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 160 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 161 #define RTL822X_VND1_SERDES_DATA 0x7589 162 163 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 164 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 165 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 166 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 167 168 #define RTL8221B_VND2_INER 0xa4d2 169 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 170 171 #define RTL8221B_VND2_INSR 0xa4d4 172 173 #define RTL822X_VND2_LED(x) (0xd032 + ((x) * 2)) 174 #define RTL822X_VND2_LCR_LINK_10 BIT(0) 175 #define RTL822X_VND2_LCR_LINK_100 BIT(1) 176 #define RTL822X_VND2_LCR_LINK_1000 BIT(2) 177 #define RTL822X_VND2_LCR_LINK_2500 BIT(5) 178 179 #define RTL822X_VND2_LCR6 0xd040 180 #define RTL822X_VND2_LED_ACT(x) BIT(x) 181 182 #define RTL822X_VND2_LCR7 0xd044 183 #define RTL822X_VND2_LED_POLAR(x) BIT(x) 184 185 #define RTL8224_MII_RTCT 0x11 186 #define RTL8224_MII_RTCT_ENABLE BIT(0) 187 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 188 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 189 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 190 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 191 #define RTL8224_MII_RTCT_DONE BIT(15) 192 193 #define RTL8224_MII_SRAM_ADDR 0x1b 194 #define RTL8224_MII_SRAM_DATA 0x1c 195 196 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 197 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 198 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 199 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 200 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 201 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 202 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 203 204 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 205 206 #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 207 #define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 208 209 #define RTL8226_VND1_UNKNOWN_6A21 0x6a21 210 #define RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN BIT(5) 211 212 #define RTL8226_VND2_UNKNOWN_D068 0xd068 213 #define RTL8226_VND2_UNKNOWN_D068_MDI_SWAP_FLAG BIT(1) 214 #define RTL8226_VND2_UNKNOWN_D068_PAIR_SEL GENMASK(4, 3) 215 #define RTL8226_VND2_ADCCAL_OFFSET 0xd06a 216 217 #define RTL8226_VND2_RG_LPF_CAP_XG_P0_P1 0xbd5a 218 #define RTL8226_VND2_RG_LPF_CAP_XG_P2_P3 0xbd5c 219 #define RTL8226_VND2_RG_LPF_CAP_P0_P1 0xbc18 220 #define RTL8226_VND2_RG_LPF_CAP_P2_P3 0xbc1a 221 #define RTL8226_RG_LPF_CAP_PAIR_A_MASK GENMASK(4, 0) 222 #define RTL8226_RG_LPF_CAP_PAIR_B_MASK GENMASK(12, 8) 223 224 #define RTL8366RB_POWER_SAVE 0x15 225 #define RTL8366RB_POWER_SAVE_ON BIT(12) 226 227 #define RTL9000A_GINMR 0x14 228 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 229 230 #define RTL_PHYSR MII_RESV2 231 #define RTL_PHYSR_DUPLEX BIT(3) 232 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 233 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 234 #define RTL_PHYSR_MASTER BIT(11) 235 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 236 237 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 238 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 239 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 240 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 241 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 242 #define RTL_MDIO_PMA_SPEED 0xa616 243 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 244 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 245 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 246 247 #define RTL_GENERIC_PHYID 0x001cc800 248 #define RTL_8211FVD_PHYID 0x001cc878 249 #define RTL_8221B 0x001cc840 250 #define RTL_8221B_VB_CG 0x001cc849 251 #define RTL_8221B_VM_CG 0x001cc84a 252 #define RTL_8251B 0x001cc862 253 #define RTL_8261C 0x001cc890 254 255 /* RTL8211E and RTL8211F support up to three LEDs */ 256 #define RTL8211x_LED_COUNT 3 257 258 MODULE_DESCRIPTION("Realtek PHY driver"); 259 MODULE_AUTHOR("Johnson Leung"); 260 MODULE_LICENSE("GPL"); 261 262 struct rtl821x_priv { 263 bool enable_aldps; 264 bool disable_clk_out; 265 bool enable_clkout_ssc; 266 bool enable_rxc_ssc; 267 bool enable_sysclk_ssc; 268 struct clk *clk; 269 /* rtl8211f */ 270 u16 iner; 271 }; 272 273 static int rtl821x_read_page(struct phy_device *phydev) 274 { 275 return __phy_read(phydev, RTL821x_PAGE_SELECT); 276 } 277 278 static int rtl821x_write_page(struct phy_device *phydev, int page) 279 { 280 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 281 } 282 283 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 284 u32 regnum) 285 { 286 int oldpage, ret = 0; 287 288 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 289 if (oldpage >= 0) { 290 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 291 if (ret == 0) 292 ret = __phy_read(phydev, regnum); 293 } 294 295 return phy_restore_page(phydev, oldpage, ret); 296 } 297 298 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 299 u32 regnum, u16 mask, u16 set) 300 { 301 int oldpage, ret = 0; 302 303 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 304 if (oldpage >= 0) { 305 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 306 if (ret == 0) 307 ret = __phy_modify(phydev, regnum, mask, set); 308 } 309 310 return phy_restore_page(phydev, oldpage, ret); 311 } 312 313 static int rtl821x_probe(struct phy_device *phydev) 314 { 315 struct device *dev = &phydev->mdio.dev; 316 struct rtl821x_priv *priv; 317 318 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 319 if (!priv) 320 return -ENOMEM; 321 322 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 323 if (IS_ERR(priv->clk)) 324 return dev_err_probe(dev, PTR_ERR(priv->clk), 325 "failed to get phy clock\n"); 326 327 priv->enable_aldps = of_property_read_bool(dev->of_node, 328 "realtek,aldps-enable"); 329 priv->disable_clk_out = of_property_read_bool(dev->of_node, 330 "realtek,clkout-disable"); 331 priv->enable_clkout_ssc = of_property_read_bool(dev->of_node, 332 "realtek,clkout-ssc-enable"); 333 priv->enable_rxc_ssc = of_property_read_bool(dev->of_node, 334 "realtek,rxc-ssc-enable"); 335 priv->enable_sysclk_ssc = of_property_read_bool(dev->of_node, 336 "realtek,sysclk-ssc-enable"); 337 338 phydev->priv = priv; 339 340 return 0; 341 } 342 343 static int rtl8211f_probe(struct phy_device *phydev) 344 { 345 struct device *dev = &phydev->mdio.dev; 346 int ret; 347 348 ret = rtl821x_probe(phydev); 349 if (ret < 0) 350 return ret; 351 352 /* Disable all PME events */ 353 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 354 RTL8211F_WOL_SETTINGS_EVENTS, 0); 355 if (ret < 0) 356 return ret; 357 358 /* Mark this PHY as wakeup capable and register the interrupt as a 359 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 360 * and the interrupt is valid. 361 */ 362 if (device_property_read_bool(dev, "wakeup-source") && 363 phy_interrupt_is_valid(phydev)) { 364 device_set_wakeup_capable(dev, true); 365 devm_pm_set_wake_irq(dev, phydev->irq); 366 } 367 368 return ret; 369 } 370 371 static int rtl8201_ack_interrupt(struct phy_device *phydev) 372 { 373 int err; 374 375 err = phy_read(phydev, RTL8201F_ISR); 376 377 return (err < 0) ? err : 0; 378 } 379 380 static int rtl821x_ack_interrupt(struct phy_device *phydev) 381 { 382 int err; 383 384 err = phy_read(phydev, RTL821x_INSR); 385 386 return (err < 0) ? err : 0; 387 } 388 389 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 390 { 391 int err; 392 393 err = phy_read(phydev, RTL8211F_INSR); 394 395 return (err < 0) ? err : 0; 396 } 397 398 static int rtl8201_config_intr(struct phy_device *phydev) 399 { 400 u16 val; 401 int err; 402 403 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 404 err = rtl8201_ack_interrupt(phydev); 405 if (err) 406 return err; 407 408 val = RTL8201F_IER_MASK; 409 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 410 RTL8201F_IER, val); 411 } else { 412 val = 0; 413 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 414 RTL8201F_IER, val); 415 if (err) 416 return err; 417 418 err = rtl8201_ack_interrupt(phydev); 419 } 420 421 return err; 422 } 423 424 static int rtl8211b_config_intr(struct phy_device *phydev) 425 { 426 int err; 427 428 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 429 err = rtl821x_ack_interrupt(phydev); 430 if (err) 431 return err; 432 433 err = phy_write(phydev, RTL821x_INER, 434 RTL8211B_INER_INIT); 435 } else { 436 err = phy_write(phydev, RTL821x_INER, 0); 437 if (err) 438 return err; 439 440 err = rtl821x_ack_interrupt(phydev); 441 } 442 443 return err; 444 } 445 446 static int rtl8211e_config_intr(struct phy_device *phydev) 447 { 448 int err; 449 450 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 451 err = rtl821x_ack_interrupt(phydev); 452 if (err) 453 return err; 454 455 err = phy_write(phydev, RTL821x_INER, 456 RTL8211E_INER_LINK_STATUS); 457 } else { 458 err = phy_write(phydev, RTL821x_INER, 0); 459 if (err) 460 return err; 461 462 err = rtl821x_ack_interrupt(phydev); 463 } 464 465 return err; 466 } 467 468 static int rtl8211f_config_intr(struct phy_device *phydev) 469 { 470 struct rtl821x_priv *priv = phydev->priv; 471 u16 val; 472 int err; 473 474 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 475 err = rtl8211f_ack_interrupt(phydev); 476 if (err) 477 return err; 478 479 val = RTL8211F_INER_LINK_STATUS; 480 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 481 if (err == 0) 482 priv->iner = val; 483 } else { 484 priv->iner = val = 0; 485 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 486 if (err) 487 return err; 488 489 err = rtl8211f_ack_interrupt(phydev); 490 } 491 492 return err; 493 } 494 495 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 496 { 497 int irq_status; 498 499 irq_status = phy_read(phydev, RTL8201F_ISR); 500 if (irq_status < 0) { 501 phy_error(phydev); 502 return IRQ_NONE; 503 } 504 505 if (!(irq_status & RTL8201F_ISR_MASK)) 506 return IRQ_NONE; 507 508 phy_trigger_machine(phydev); 509 510 return IRQ_HANDLED; 511 } 512 513 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 514 { 515 int irq_status, irq_enabled; 516 517 irq_status = phy_read(phydev, RTL821x_INSR); 518 if (irq_status < 0) { 519 phy_error(phydev); 520 return IRQ_NONE; 521 } 522 523 irq_enabled = phy_read(phydev, RTL821x_INER); 524 if (irq_enabled < 0) { 525 phy_error(phydev); 526 return IRQ_NONE; 527 } 528 529 if (!(irq_status & irq_enabled)) 530 return IRQ_NONE; 531 532 phy_trigger_machine(phydev); 533 534 return IRQ_HANDLED; 535 } 536 537 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 538 { 539 int irq_status; 540 541 irq_status = phy_read(phydev, RTL8211F_INSR); 542 if (irq_status < 0) { 543 phy_error(phydev); 544 return IRQ_NONE; 545 } 546 547 if (irq_status & RTL8211F_INER_LINK_STATUS) { 548 phy_trigger_machine(phydev); 549 return IRQ_HANDLED; 550 } 551 552 if (irq_status & RTL8211F_INER_PME) { 553 pm_wakeup_event(&phydev->mdio.dev, 0); 554 return IRQ_HANDLED; 555 } 556 557 return IRQ_NONE; 558 } 559 560 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 561 { 562 int wol_events; 563 564 /* If the PHY is not capable of waking the system, then WoL can not 565 * be supported. 566 */ 567 if (!device_can_wakeup(&dev->mdio.dev)) { 568 wol->supported = 0; 569 return; 570 } 571 572 wol->supported = WAKE_MAGIC; 573 574 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 575 if (wol_events < 0) 576 return; 577 578 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 579 wol->wolopts = WAKE_MAGIC; 580 } 581 582 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 583 { 584 const u8 *mac_addr = dev->attached_dev->dev_addr; 585 int oldpage; 586 587 if (!device_can_wakeup(&dev->mdio.dev)) 588 return -EOPNOTSUPP; 589 590 oldpage = phy_save_page(dev); 591 if (oldpage < 0) 592 goto err; 593 594 if (wol->wolopts & WAKE_MAGIC) { 595 /* Store the device address for the magic packet */ 596 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 597 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 598 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 599 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 600 601 /* Enable magic packet matching */ 602 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 603 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 604 /* Set the maximum packet size, and assert WoL reset */ 605 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 606 } else { 607 /* Disable magic packet matching */ 608 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 609 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 610 611 /* Place WoL in reset */ 612 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 613 RTL8211F_WOL_RG_RSTB); 614 } 615 616 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 617 618 err: 619 return phy_restore_page(dev, oldpage, 0); 620 } 621 622 static int rtl8211_config_aneg(struct phy_device *phydev) 623 { 624 int ret; 625 626 ret = genphy_config_aneg(phydev); 627 if (ret < 0) 628 return ret; 629 630 /* Quirk was copied from vendor driver. Unfortunately it includes no 631 * description of the magic numbers. 632 */ 633 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 634 phy_write(phydev, 0x17, 0x2138); 635 phy_write(phydev, 0x0e, 0x0260); 636 } else { 637 phy_write(phydev, 0x17, 0x2108); 638 phy_write(phydev, 0x0e, 0x0000); 639 } 640 641 return 0; 642 } 643 644 static int rtl8211c_config_init(struct phy_device *phydev) 645 { 646 /* RTL8211C has an issue when operating in Gigabit slave mode */ 647 return phy_set_bits(phydev, MII_CTRL1000, 648 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 649 } 650 651 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 652 { 653 u16 val_txdly, val_rxdly; 654 int ret; 655 656 switch (phydev->interface) { 657 case PHY_INTERFACE_MODE_RGMII: 658 val_txdly = 0; 659 val_rxdly = 0; 660 break; 661 662 case PHY_INTERFACE_MODE_RGMII_RXID: 663 val_txdly = 0; 664 val_rxdly = RTL8211F_RX_DELAY; 665 break; 666 667 case PHY_INTERFACE_MODE_RGMII_TXID: 668 val_txdly = RTL8211F_TX_DELAY; 669 val_rxdly = 0; 670 break; 671 672 case PHY_INTERFACE_MODE_RGMII_ID: 673 val_txdly = RTL8211F_TX_DELAY; 674 val_rxdly = RTL8211F_RX_DELAY; 675 break; 676 677 default: /* the rest of the modes imply leaving delay as is. */ 678 return 0; 679 } 680 681 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 682 RTL8211F_TXCR, RTL8211F_TX_DELAY, 683 val_txdly); 684 if (ret < 0) { 685 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 686 ERR_PTR(ret)); 687 return ret; 688 } else if (ret) { 689 phydev_dbg(phydev, 690 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 691 str_enable_disable(val_txdly)); 692 } else { 693 phydev_dbg(phydev, 694 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 695 str_enabled_disabled(val_txdly)); 696 } 697 698 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 699 RTL8211F_RXCR, RTL8211F_RX_DELAY, 700 val_rxdly); 701 if (ret < 0) { 702 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 703 ERR_PTR(ret)); 704 return ret; 705 } else if (ret) { 706 phydev_dbg(phydev, 707 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 708 str_enable_disable(val_rxdly)); 709 } else { 710 phydev_dbg(phydev, 711 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 712 str_enabled_disabled(val_rxdly)); 713 } 714 715 return 0; 716 } 717 718 static int rtl8211f_config_clk_out(struct phy_device *phydev) 719 { 720 struct rtl821x_priv *priv = phydev->priv; 721 int ret; 722 723 /* The value is preserved if the device tree property is absent */ 724 if (!priv->disable_clk_out) 725 return 0; 726 727 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 728 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 729 RTL8211FVD_CLKOUT_REG, 730 RTL8211FVD_CLKOUT_EN, 0); 731 else 732 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 733 0); 734 if (ret) 735 return ret; 736 737 return genphy_soft_reset(phydev); 738 } 739 740 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 741 * which causes the RXC clock signal to stop for tens to hundreds of 742 * milliseconds. 743 * 744 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 745 * only enabled based on an opt-in device tree property. 746 */ 747 static int rtl8211f_config_aldps(struct phy_device *phydev) 748 { 749 struct rtl821x_priv *priv = phydev->priv; 750 u16 mask = RTL8211F_ALDPS_PLL_OFF | 751 RTL8211F_ALDPS_ENABLE | 752 RTL8211F_ALDPS_XTAL_OFF; 753 754 /* The value is preserved if the device tree property is absent */ 755 if (!priv->enable_aldps) 756 return 0; 757 758 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 759 } 760 761 static int rtl8211f_disable_autonomous_eee(struct phy_device *phydev) 762 { 763 return phy_modify(phydev, RTL8211F_PHYCR2, 764 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 765 } 766 767 static int rtl8211f_config_clkout_ssc(struct phy_device *phydev) 768 { 769 struct rtl821x_priv *priv = phydev->priv; 770 struct device *dev = &phydev->mdio.dev; 771 int ret; 772 773 /* The value is preserved if the device tree property is absent */ 774 if (!priv->enable_clkout_ssc) 775 return 0; 776 777 /* RTL8211FVD has PHYCR2 register, but configuration of CLKOUT SSC 778 * is not currently supported by this driver due to different bit 779 * layout. 780 */ 781 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 782 return 0; 783 784 /* Unnamed registers from EMI improvement parameters application note 1.2 */ 785 ret = phy_write_paged(phydev, 0xd09, 0x10, 0xcf00); 786 if (ret < 0) { 787 dev_err(dev, "CLKOUT SSC initialization failed: %pe\n", ERR_PTR(ret)); 788 return ret; 789 } 790 791 /* Enable CLKOUT SSC and CLKOUT SSC Capability using PHYCR2 792 * bits 7, 12, 13. This matches the register 25 write 0x38C3 793 * from the EMI improvement parameters application note 1.2 794 * section 2.3, without affecting unrelated bits. 795 */ 796 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, 797 RTL8211F_CLKOUT_SSC_CAP | RTL8211F_CLKOUT_SSC_EN); 798 if (ret < 0) { 799 dev_err(dev, "CLKOUT SSC enable failed: %pe\n", ERR_PTR(ret)); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int rtl8211f_config_rxc_ssc(struct phy_device *phydev) 807 { 808 struct rtl821x_priv *priv = phydev->priv; 809 struct device *dev = &phydev->mdio.dev; 810 int ret; 811 812 /* The value is preserved if the device tree property is absent */ 813 if (!priv->enable_rxc_ssc) 814 return 0; 815 816 /* RTL8211FVD has PHYCR2 register, but configuration of RXC SSC 817 * is not currently supported by this driver due to different bit 818 * layout. 819 */ 820 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 821 return 0; 822 823 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_RXC, 0x5f00); 824 if (ret < 0) { 825 dev_err(dev, "RXC SSC configuration failed: %pe\n", ERR_PTR(ret)); 826 return ret; 827 } 828 829 return 0; 830 } 831 832 static int rtl8211f_config_sysclk_ssc(struct phy_device *phydev) 833 { 834 struct rtl821x_priv *priv = phydev->priv; 835 struct device *dev = &phydev->mdio.dev; 836 int ret; 837 838 /* The value is preserved if the device tree property is absent */ 839 if (!priv->enable_sysclk_ssc) 840 return 0; 841 842 /* RTL8211FVD has PHYCR2 register, but configuration of SYSCLK SSC 843 * is not currently supported by this driver due to different bit 844 * layout. 845 */ 846 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 847 return 0; 848 849 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_SYSCLK, 0x4f00); 850 if (ret < 0) { 851 dev_err(dev, "SYSCLK SSC configuration failed: %pe\n", ERR_PTR(ret)); 852 return ret; 853 } 854 855 /* Enable SSC */ 856 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, RTL8211F_SYSCLK_SSC_EN); 857 if (ret < 0) { 858 dev_err(dev, "SYSCLK SSC enable failed: %pe\n", ERR_PTR(ret)); 859 return ret; 860 } 861 862 return 0; 863 } 864 865 static int rtl8211f_config_init(struct phy_device *phydev) 866 { 867 struct device *dev = &phydev->mdio.dev; 868 int ret; 869 870 ret = rtl8211f_config_aldps(phydev); 871 if (ret) { 872 dev_err(dev, "aldps mode configuration failed: %pe\n", 873 ERR_PTR(ret)); 874 return ret; 875 } 876 877 ret = rtl8211f_config_rgmii_delay(phydev); 878 if (ret) 879 return ret; 880 881 ret = rtl8211f_config_rxc_ssc(phydev); 882 if (ret) 883 return ret; 884 885 ret = rtl8211f_config_sysclk_ssc(phydev); 886 if (ret) 887 return ret; 888 889 ret = rtl8211f_config_clkout_ssc(phydev); 890 if (ret) 891 return ret; 892 893 ret = rtl8211f_config_clk_out(phydev); 894 if (ret) { 895 dev_err(dev, "clkout configuration failed: %pe\n", 896 ERR_PTR(ret)); 897 return ret; 898 } 899 900 return 0; 901 } 902 903 static int rtl821x_suspend(struct phy_device *phydev) 904 { 905 struct rtl821x_priv *priv = phydev->priv; 906 int ret = 0; 907 908 if (!phydev->wol_enabled) { 909 ret = genphy_suspend(phydev); 910 911 if (ret) 912 return ret; 913 914 clk_disable_unprepare(priv->clk); 915 } 916 917 return ret; 918 } 919 920 static int rtl8211f_suspend(struct phy_device *phydev) 921 { 922 u16 wol_rst; 923 int ret; 924 925 ret = rtl821x_suspend(phydev); 926 if (ret < 0) 927 return ret; 928 929 /* If a PME event is enabled, then configure the interrupt for 930 * PME events only, disabling link interrupt. We avoid switching 931 * to PMEB mode as we don't have a status bit for that. 932 */ 933 if (device_may_wakeup(&phydev->mdio.dev)) { 934 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 935 RTL8211F_INER_PME); 936 if (ret < 0) 937 goto err; 938 939 /* Read the INSR to clear any pending interrupt */ 940 phy_read(phydev, RTL8211F_INSR); 941 942 /* Reset the WoL to ensure that an event is picked up. 943 * Unless we do this, even if we receive another packet, 944 * we may not have a PME interrupt raised. 945 */ 946 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 947 RTL8211F_WOL_RST_RMSQ); 948 if (ret < 0) 949 goto err; 950 951 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 952 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 953 RTL8211F_WOL_RST_RMSQ, wol_rst); 954 if (ret < 0) 955 goto err; 956 957 wol_rst |= RTL8211F_WOL_RG_RSTB; 958 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 959 RTL8211F_WOL_RST_RMSQ, wol_rst); 960 } 961 962 err: 963 return ret; 964 } 965 966 static int rtl821x_resume(struct phy_device *phydev) 967 { 968 struct rtl821x_priv *priv = phydev->priv; 969 int ret; 970 971 if (!phydev->wol_enabled) 972 clk_prepare_enable(priv->clk); 973 974 ret = genphy_resume(phydev); 975 if (ret < 0) 976 return ret; 977 978 msleep(20); 979 980 return 0; 981 } 982 983 static int rtl8211f_resume(struct phy_device *phydev) 984 { 985 struct rtl821x_priv *priv = phydev->priv; 986 int ret; 987 988 ret = rtl821x_resume(phydev); 989 if (ret < 0) 990 return ret; 991 992 /* If the device was programmed for a PME event, restore the interrupt 993 * enable so phylib can receive link state interrupts. 994 */ 995 if (device_may_wakeup(&phydev->mdio.dev)) 996 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 997 998 return ret; 999 } 1000 1001 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 1002 unsigned long rules) 1003 { 1004 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 1005 BIT(TRIGGER_NETDEV_LINK_10) | 1006 BIT(TRIGGER_NETDEV_LINK_100) | 1007 BIT(TRIGGER_NETDEV_LINK_1000) | 1008 BIT(TRIGGER_NETDEV_RX) | 1009 BIT(TRIGGER_NETDEV_TX); 1010 1011 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 1012 * - Link: Configurable subset of 10/100/1000 link rates 1013 * - Active: Blink on activity, RX or TX is not differentiated 1014 * The Active option has two modes, A and B: 1015 * - A: Link and Active indication at configurable, but matching, 1016 * subset of 10/100/1000 link rates 1017 * - B: Link indication at configurable subset of 10/100/1000 link 1018 * rates and Active indication always at all three 10+100+1000 1019 * link rates. 1020 * This code currently uses mode B only. 1021 * 1022 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 1023 */ 1024 1025 if (index >= RTL8211x_LED_COUNT) 1026 return -EINVAL; 1027 1028 /* Filter out any other unsupported triggers. */ 1029 if (rules & ~mask) 1030 return -EOPNOTSUPP; 1031 1032 /* RX and TX are not differentiated, either both are set or not set. */ 1033 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 1034 return -EOPNOTSUPP; 1035 1036 return 0; 1037 } 1038 1039 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 1040 unsigned long *rules) 1041 { 1042 int val; 1043 1044 if (index >= RTL8211x_LED_COUNT) 1045 return -EINVAL; 1046 1047 val = phy_read_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR); 1048 if (val < 0) 1049 return val; 1050 1051 val >>= RTL8211F_LEDCR_SHIFT * index; 1052 val &= RTL8211F_LEDCR_MASK; 1053 1054 if (val & RTL8211F_LEDCR_LINK_10) 1055 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1056 1057 if (val & RTL8211F_LEDCR_LINK_100) 1058 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1059 1060 if (val & RTL8211F_LEDCR_LINK_1000) 1061 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1062 1063 if ((val & RTL8211F_LEDCR_LINK_10) && 1064 (val & RTL8211F_LEDCR_LINK_100) && 1065 (val & RTL8211F_LEDCR_LINK_1000)) { 1066 __set_bit(TRIGGER_NETDEV_LINK, rules); 1067 } 1068 1069 if (val & RTL8211F_LEDCR_ACT_TXRX) { 1070 __set_bit(TRIGGER_NETDEV_RX, rules); 1071 __set_bit(TRIGGER_NETDEV_TX, rules); 1072 } 1073 1074 return 0; 1075 } 1076 1077 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 1078 unsigned long rules) 1079 { 1080 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 1081 u16 reg = 0; 1082 1083 if (index >= RTL8211x_LED_COUNT) 1084 return -EINVAL; 1085 1086 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1087 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1088 reg |= RTL8211F_LEDCR_LINK_10; 1089 } 1090 1091 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1092 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1093 reg |= RTL8211F_LEDCR_LINK_100; 1094 } 1095 1096 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1097 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1098 reg |= RTL8211F_LEDCR_LINK_1000; 1099 } 1100 1101 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1102 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1103 reg |= RTL8211F_LEDCR_ACT_TXRX; 1104 } 1105 1106 reg <<= RTL8211F_LEDCR_SHIFT * index; 1107 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 1108 1109 return phy_modify_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR, 1110 mask, reg); 1111 } 1112 1113 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 1114 unsigned long *rules) 1115 { 1116 int ret; 1117 u16 cr1, cr2; 1118 1119 if (index >= RTL8211x_LED_COUNT) 1120 return -EINVAL; 1121 1122 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1123 RTL8211E_LEDCR1); 1124 if (ret < 0) 1125 return ret; 1126 1127 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 1128 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 1129 __set_bit(TRIGGER_NETDEV_RX, rules); 1130 __set_bit(TRIGGER_NETDEV_TX, rules); 1131 } 1132 1133 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1134 RTL8211E_LEDCR2); 1135 if (ret < 0) 1136 return ret; 1137 1138 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 1139 if (cr2 & RTL8211E_LEDCR2_LINK_10) 1140 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1141 1142 if (cr2 & RTL8211E_LEDCR2_LINK_100) 1143 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1144 1145 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 1146 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1147 1148 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 1149 (cr2 & RTL8211E_LEDCR2_LINK_100) && 1150 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 1151 __set_bit(TRIGGER_NETDEV_LINK, rules); 1152 } 1153 1154 return ret; 1155 } 1156 1157 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 1158 unsigned long rules) 1159 { 1160 const u16 cr1mask = 1161 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 1162 const u16 cr2mask = 1163 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 1164 u16 cr1 = 0, cr2 = 0; 1165 int ret; 1166 1167 if (index >= RTL8211x_LED_COUNT) 1168 return -EINVAL; 1169 1170 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1171 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1172 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1173 } 1174 1175 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1176 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1177 RTL8211E_LEDCR1, cr1mask, cr1); 1178 if (ret < 0) 1179 return ret; 1180 1181 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1182 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1183 cr2 |= RTL8211E_LEDCR2_LINK_10; 1184 } 1185 1186 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1187 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1188 cr2 |= RTL8211E_LEDCR2_LINK_100; 1189 } 1190 1191 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1192 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1193 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1194 } 1195 1196 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1197 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1198 RTL8211E_LEDCR2, cr2mask, cr2); 1199 1200 return ret; 1201 } 1202 1203 static int rtl8211e_config_init(struct phy_device *phydev) 1204 { 1205 u16 val; 1206 1207 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1208 switch (phydev->interface) { 1209 case PHY_INTERFACE_MODE_RGMII: 1210 val = RTL8211E_CTRL_DELAY | 0; 1211 break; 1212 case PHY_INTERFACE_MODE_RGMII_ID: 1213 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1214 break; 1215 case PHY_INTERFACE_MODE_RGMII_RXID: 1216 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1217 break; 1218 case PHY_INTERFACE_MODE_RGMII_TXID: 1219 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1220 break; 1221 default: /* the rest of the modes imply leaving delays as is. */ 1222 return 0; 1223 } 1224 1225 /* According to a sample driver there is a 0x1c config register on the 1226 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1227 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1228 * The configuration register definition: 1229 * 14 = reserved 1230 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1231 * 12 = RX Delay, 11 = TX Delay 1232 * 10:0 = Test && debug settings reserved by realtek 1233 */ 1234 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1235 RTL8211E_RGMII_DELAY, 1236 RTL8211E_DELAY_MASK, val); 1237 } 1238 1239 static int rtl8211b_suspend(struct phy_device *phydev) 1240 { 1241 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1242 1243 return genphy_suspend(phydev); 1244 } 1245 1246 static int rtl8211b_resume(struct phy_device *phydev) 1247 { 1248 phy_write(phydev, MII_MMD_DATA, 0); 1249 1250 return genphy_resume(phydev); 1251 } 1252 1253 static int rtl8366rb_config_init(struct phy_device *phydev) 1254 { 1255 int ret; 1256 1257 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1258 RTL8366RB_POWER_SAVE_ON); 1259 if (ret) { 1260 dev_err(&phydev->mdio.dev, 1261 "error enabling power management\n"); 1262 } 1263 1264 return ret; 1265 } 1266 1267 /* get actual speed to cover the downshift case */ 1268 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1269 { 1270 /* bit 3 1271 * 0: Half Duplex 1272 * 1: Full Duplex 1273 */ 1274 if (val & RTL_PHYSR_DUPLEX) 1275 phydev->duplex = DUPLEX_FULL; 1276 else 1277 phydev->duplex = DUPLEX_HALF; 1278 1279 switch (val & RTL_PHYSR_SPEED_MASK) { 1280 case 0x0000: 1281 phydev->speed = SPEED_10; 1282 break; 1283 case 0x0010: 1284 phydev->speed = SPEED_100; 1285 break; 1286 case 0x0020: 1287 phydev->speed = SPEED_1000; 1288 break; 1289 case 0x0200: 1290 phydev->speed = SPEED_10000; 1291 break; 1292 case 0x0210: 1293 phydev->speed = SPEED_2500; 1294 break; 1295 case 0x0220: 1296 phydev->speed = SPEED_5000; 1297 break; 1298 default: 1299 break; 1300 } 1301 1302 /* bit 11 1303 * 0: Slave Mode 1304 * 1: Master Mode 1305 */ 1306 if (phydev->speed >= 1000) { 1307 if (val & RTL_PHYSR_MASTER) 1308 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1309 else 1310 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1311 } else { 1312 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1313 } 1314 } 1315 1316 static int rtlgen_read_status(struct phy_device *phydev) 1317 { 1318 int ret, val; 1319 1320 ret = genphy_read_status(phydev); 1321 if (ret < 0) 1322 return ret; 1323 1324 if (!phydev->link) 1325 return 0; 1326 1327 val = phy_read(phydev, RTL_PHYSR); 1328 if (val < 0) 1329 return val; 1330 1331 rtlgen_decode_physr(phydev, val); 1332 1333 return 0; 1334 } 1335 1336 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1337 { 1338 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1339 } 1340 1341 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1342 { 1343 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1344 val); 1345 } 1346 1347 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1348 { 1349 int ret; 1350 1351 if (devnum == MDIO_MMD_VEND2) 1352 ret = rtlgen_read_vend2(phydev, regnum); 1353 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1354 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1355 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1356 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1357 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1358 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1359 else 1360 ret = -EOPNOTSUPP; 1361 1362 return ret; 1363 } 1364 1365 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1366 u16 val) 1367 { 1368 int ret; 1369 1370 if (devnum == MDIO_MMD_VEND2) 1371 ret = rtlgen_write_vend2(phydev, regnum, val); 1372 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1373 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1374 else 1375 ret = -EOPNOTSUPP; 1376 1377 return ret; 1378 } 1379 1380 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1381 { 1382 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1383 1384 if (ret != -EOPNOTSUPP) 1385 return ret; 1386 1387 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1388 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1389 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1390 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1391 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1392 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1393 1394 return ret; 1395 } 1396 1397 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1398 u16 val) 1399 { 1400 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1401 1402 if (ret != -EOPNOTSUPP) 1403 return ret; 1404 1405 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1406 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1407 1408 return ret; 1409 } 1410 1411 static int rtl822x_probe(struct phy_device *phydev) 1412 { 1413 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1414 phydev->phy_id != RTL_GENERIC_PHYID) 1415 return rtl822x_hwmon_init(phydev); 1416 1417 return 0; 1418 } 1419 1420 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1421 * A mapping to use paged access needs to be used instead. 1422 * All other MMD devices can be accessed as usual. 1423 */ 1424 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1425 { 1426 int oldpage, ret, read_ret; 1427 u16 page; 1428 1429 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1430 * Clause-45 access is available 1431 */ 1432 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1433 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1434 phydev->is_c45, devnum, reg); 1435 1436 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1437 if (reg >= RTL822X_VND2_C22_REG(0) && 1438 reg <= RTL822X_VND2_C22_REG(30)) 1439 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1440 1441 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1442 page = RTL822X_VND2_TO_PAGE(reg); 1443 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1444 if (oldpage < 0) 1445 return oldpage; 1446 1447 if (oldpage != page) { 1448 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1449 if (ret < 0) 1450 return ret; 1451 } 1452 1453 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1454 if (oldpage != page) { 1455 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1456 if (ret < 0) 1457 return ret; 1458 } 1459 1460 return read_ret; 1461 } 1462 1463 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1464 u16 val) 1465 { 1466 int oldpage, ret, write_ret; 1467 u16 page; 1468 1469 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1470 * Clause-45 access is available 1471 */ 1472 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1473 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1474 phydev->is_c45, devnum, reg, val); 1475 1476 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1477 if (reg >= RTL822X_VND2_C22_REG(0) && 1478 reg <= RTL822X_VND2_C22_REG(30)) 1479 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1480 1481 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1482 page = RTL822X_VND2_TO_PAGE(reg); 1483 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1484 if (oldpage < 0) 1485 return oldpage; 1486 1487 if (oldpage != page) { 1488 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1489 if (ret < 0) 1490 return ret; 1491 } 1492 1493 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1494 if (oldpage != page) { 1495 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1496 if (ret < 0) 1497 return ret; 1498 } 1499 1500 return write_ret; 1501 } 1502 1503 static int rtl8226_set_mdi_swap(struct phy_device *phydev, bool swap_enable) 1504 { 1505 u16 val = swap_enable ? RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN : 0; 1506 1507 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8226_VND1_UNKNOWN_6A21, 1508 RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN, val); 1509 } 1510 1511 static int rtl8226_swap_rg_lpf_cap(struct phy_device *phydev, u32 reg_p0_p1, u32 reg_p2_p3) 1512 { 1513 u16 val_p0, val_p1, val_p2, val_p3; 1514 int ret; 1515 1516 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, reg_p0_p1); 1517 if (ret < 0) 1518 return ret; 1519 1520 val_p0 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_A_MASK, ret); 1521 val_p1 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_B_MASK, ret); 1522 1523 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, reg_p2_p3); 1524 if (ret < 0) 1525 return ret; 1526 1527 val_p2 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_A_MASK, ret); 1528 val_p3 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_B_MASK, ret); 1529 1530 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, reg_p0_p1, 1531 RTL8226_RG_LPF_CAP_PAIR_A_MASK | RTL8226_RG_LPF_CAP_PAIR_B_MASK, 1532 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_A_MASK, val_p3) | 1533 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_B_MASK, val_p2)); 1534 if (ret < 0) 1535 return ret; 1536 1537 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, reg_p2_p3, 1538 RTL8226_RG_LPF_CAP_PAIR_A_MASK | RTL8226_RG_LPF_CAP_PAIR_B_MASK, 1539 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_A_MASK, val_p1) | 1540 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_B_MASK, val_p0)); 1541 } 1542 1543 static int rtl8226_patch_mdi_swap(struct phy_device *phydev, bool swap_enable) 1544 { 1545 u16 adccal_offset[4]; 1546 bool is_patched; 1547 int ret; 1548 1549 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068); 1550 if (ret < 0) 1551 return ret; 1552 1553 is_patched = !(ret & RTL8226_VND2_UNKNOWN_D068_MDI_SWAP_FLAG); 1554 1555 if (is_patched == swap_enable) { 1556 /* Nothing to do */ 1557 return 0; 1558 } 1559 1560 if (!swap_enable) { 1561 /* Patching is only implemented one-way, see next comment. */ 1562 phydev_err(phydev, "MDI swapping disabled, but PHY is already patched.\n"); 1563 return -EINVAL; 1564 } 1565 1566 /* The exact meaning of these bits is unknown. We only know that bit 1 1567 * is used as a flag that swapping is already done. 1568 */ 1569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 0x7, 0x1); 1570 if (ret < 0) 1571 return ret; 1572 1573 for (int i = 0; i < 4; i++) { 1574 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 1575 RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, 1576 FIELD_PREP(RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, i)); 1577 if (ret < 0) 1578 return ret; 1579 1580 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_ADCCAL_OFFSET); 1581 if (ret < 0) 1582 return ret; 1583 1584 adccal_offset[i] = ret; 1585 } 1586 1587 for (int i = 0; i < 4; i++) { 1588 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 1589 RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, 1590 FIELD_PREP(RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, i)); 1591 if (ret < 0) 1592 return ret; 1593 1594 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_ADCCAL_OFFSET, 1595 adccal_offset[3 - i]); 1596 if (ret < 0) 1597 return ret; 1598 } 1599 1600 ret = rtl8226_swap_rg_lpf_cap(phydev, RTL8226_VND2_RG_LPF_CAP_XG_P0_P1, 1601 RTL8226_VND2_RG_LPF_CAP_XG_P2_P3); 1602 if (ret < 0) 1603 return ret; 1604 1605 return rtl8226_swap_rg_lpf_cap(phydev, RTL8226_VND2_RG_LPF_CAP_P0_P1, 1606 RTL8226_VND2_RG_LPF_CAP_P2_P3); 1607 } 1608 1609 static int rtl8226_config_mdi_order(struct phy_device *phydev) 1610 { 1611 u32 order; 1612 bool swap_enable; 1613 int ret; 1614 1615 ret = of_property_read_u32(phydev->mdio.dev.of_node, "enet-phy-pair-order", &order); 1616 1617 /* Property not present, nothing to do */ 1618 if (ret == -EINVAL || ret == -ENOSYS) 1619 return 0; 1620 1621 if (ret) 1622 return ret; 1623 1624 if (order & ~1) 1625 return -EINVAL; 1626 1627 swap_enable = !!(order & 1); 1628 1629 ret = rtl8226_set_mdi_swap(phydev, swap_enable); 1630 if (ret) 1631 return ret; 1632 1633 return rtl8226_patch_mdi_swap(phydev, swap_enable); 1634 } 1635 1636 static int rtl8226_probe(struct phy_device *phydev) 1637 { 1638 return rtl8226_config_mdi_order(phydev); 1639 } 1640 1641 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1642 { 1643 bool has_2500, has_sgmii; 1644 u16 mode; 1645 int ret; 1646 1647 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1648 phydev->host_interfaces) || 1649 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1650 1651 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1652 phydev->host_interfaces) || 1653 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1654 1655 /* fill in possible interfaces */ 1656 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1657 has_2500); 1658 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1659 has_sgmii); 1660 1661 if (!has_2500 && !has_sgmii) 1662 return 0; 1663 1664 /* determine SerDes option mode */ 1665 if (has_2500 && !has_sgmii) { 1666 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1667 phydev->rate_matching = RATE_MATCH_PAUSE; 1668 } else { 1669 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1670 phydev->rate_matching = RATE_MATCH_NONE; 1671 } 1672 1673 /* the following sequence with magic numbers sets up the SerDes 1674 * option mode 1675 */ 1676 1677 if (!gen1) { 1678 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1679 if (ret < 0) 1680 return ret; 1681 } 1682 1683 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1684 RTL822X_VND1_SERDES_OPTION, 1685 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1686 mode); 1687 if (gen1 || ret < 0) 1688 return ret; 1689 1690 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1691 if (ret < 0) 1692 return ret; 1693 1694 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1695 if (ret < 0) 1696 return ret; 1697 1698 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1699 } 1700 1701 static int rtl822x_config_init(struct phy_device *phydev) 1702 { 1703 return rtl822x_set_serdes_option_mode(phydev, true); 1704 } 1705 1706 static int rtl822xb_config_init(struct phy_device *phydev) 1707 { 1708 return rtl822x_set_serdes_option_mode(phydev, false); 1709 } 1710 1711 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1712 { 1713 int ret, poll; 1714 1715 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1716 if (ret < 0) 1717 return ret; 1718 1719 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1720 if (ret < 0) 1721 return ret; 1722 1723 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1724 RTL822X_VND1_SERDES_CMD_WRITE | 1725 RTL822X_VND1_SERDES_CMD_BUSY); 1726 if (ret < 0) 1727 return ret; 1728 1729 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1730 RTL822X_VND1_SERDES_CMD, poll, 1731 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1732 500, 100000, false); 1733 } 1734 1735 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1736 { 1737 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1738 (modes != LINK_INBAND_DISABLE) ? 1739 RTL822X_VND1_SERDES_INBAND_ENABLE : 1740 RTL822X_VND1_SERDES_INBAND_DISABLE); 1741 } 1742 1743 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1744 phy_interface_t interface) 1745 { 1746 switch (interface) { 1747 case PHY_INTERFACE_MODE_2500BASEX: 1748 return LINK_INBAND_DISABLE; 1749 case PHY_INTERFACE_MODE_SGMII: 1750 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1751 default: 1752 return 0; 1753 } 1754 } 1755 1756 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1757 phy_interface_t iface) 1758 { 1759 int val; 1760 1761 /* Only rate matching at 2500base-x */ 1762 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1763 return RATE_MATCH_NONE; 1764 1765 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1766 if (val < 0) 1767 return val; 1768 1769 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1770 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1771 return RATE_MATCH_PAUSE; 1772 1773 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1774 return RATE_MATCH_NONE; 1775 } 1776 1777 static int rtl822x_get_features(struct phy_device *phydev) 1778 { 1779 int val; 1780 1781 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1782 if (val < 0) 1783 return val; 1784 1785 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1786 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1787 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1788 phydev->supported, val & MDIO_PMA_SPEED_5G); 1789 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1790 phydev->supported, val & MDIO_SPEED_10G); 1791 1792 return genphy_read_abilities(phydev); 1793 } 1794 1795 static int rtl822x_config_aneg(struct phy_device *phydev) 1796 { 1797 int ret = 0; 1798 1799 if (phydev->autoneg == AUTONEG_ENABLE) { 1800 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1801 1802 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1803 RTL_MDIO_AN_10GBT_CTRL, 1804 MDIO_AN_10GBT_CTRL_ADV2_5G | 1805 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1806 if (ret < 0) 1807 return ret; 1808 } 1809 1810 return __genphy_config_aneg(phydev, ret); 1811 } 1812 1813 static void rtl822xb_update_interface(struct phy_device *phydev) 1814 { 1815 int val; 1816 1817 if (!phydev->link) 1818 return; 1819 1820 /* Change interface according to serdes mode */ 1821 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1822 if (val < 0) 1823 return; 1824 1825 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1826 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1827 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1828 break; 1829 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1830 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1831 break; 1832 } 1833 } 1834 1835 static int rtl822x_read_status(struct phy_device *phydev) 1836 { 1837 int lpadv, ret; 1838 1839 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1840 1841 ret = rtlgen_read_status(phydev); 1842 if (ret < 0) 1843 return ret; 1844 1845 if (phydev->autoneg == AUTONEG_DISABLE || 1846 !phydev->autoneg_complete) 1847 return 0; 1848 1849 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1850 if (lpadv < 0) 1851 return lpadv; 1852 1853 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1854 1855 return 0; 1856 } 1857 1858 static int rtl822xb_read_status(struct phy_device *phydev) 1859 { 1860 int ret; 1861 1862 ret = rtl822x_read_status(phydev); 1863 if (ret < 0) 1864 return ret; 1865 1866 rtl822xb_update_interface(phydev); 1867 1868 return 0; 1869 } 1870 1871 static int rtl822x_c45_get_features(struct phy_device *phydev) 1872 { 1873 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1874 phydev->supported); 1875 1876 return genphy_c45_pma_read_abilities(phydev); 1877 } 1878 1879 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1880 { 1881 bool changed = false; 1882 int ret, val; 1883 1884 if (phydev->autoneg == AUTONEG_DISABLE) 1885 return genphy_c45_pma_setup_forced(phydev); 1886 1887 ret = genphy_c45_an_config_aneg(phydev); 1888 if (ret < 0) 1889 return ret; 1890 if (ret > 0) 1891 changed = true; 1892 1893 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1894 1895 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1896 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1897 RTL822X_VND2_C22_REG(MII_CTRL1000), 1898 ADVERTISE_1000FULL, val); 1899 if (ret < 0) 1900 return ret; 1901 if (ret > 0) 1902 changed = true; 1903 1904 return genphy_c45_check_and_restart_aneg(phydev, changed); 1905 } 1906 1907 static int rtl822x_c45_read_status(struct phy_device *phydev) 1908 { 1909 int ret, val; 1910 1911 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1912 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1913 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1914 RTL822X_VND2_C22_REG(MII_STAT1000)); 1915 if (val < 0) 1916 return val; 1917 } else { 1918 val = 0; 1919 } 1920 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1921 1922 ret = genphy_c45_read_status(phydev); 1923 if (ret < 0) 1924 return ret; 1925 1926 if (!phydev->link) { 1927 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1928 return 0; 1929 } 1930 1931 /* Read actual speed from vendor register. */ 1932 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1933 RTL822X_VND2_C22_REG(RTL_PHYSR)); 1934 if (val < 0) 1935 return val; 1936 1937 rtlgen_decode_physr(phydev, val); 1938 1939 return 0; 1940 } 1941 1942 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1943 { 1944 int ret, val; 1945 1946 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1947 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1948 if (ret < 0) 1949 return ret; 1950 1951 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1952 MDIO_CTRL1, val, 1953 !(val & MDIO_CTRL1_RESET), 1954 5000, 100000, true); 1955 } 1956 1957 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1958 { 1959 int ret; 1960 1961 ret = rtl822x_c45_read_status(phydev); 1962 if (ret < 0) 1963 return ret; 1964 1965 rtl822xb_update_interface(phydev); 1966 1967 return 0; 1968 } 1969 1970 static int rtl822xb_led_brightness_set(struct phy_device *phydev, u8 index, 1971 enum led_brightness value) 1972 { 1973 int ret; 1974 1975 if (index >= RTL8211x_LED_COUNT) 1976 return -EINVAL; 1977 1978 /* clear HW LED setup */ 1979 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1980 RTL822X_VND2_LED(index), 0); 1981 if (ret < 0) 1982 return ret; 1983 1984 /* clear HW LED blink */ 1985 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6, 1986 RTL822X_VND2_LED_ACT(index)); 1987 if (ret < 0) 1988 return ret; 1989 1990 if (value != LED_OFF) 1991 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1992 RTL822X_VND2_LCR7, 1993 RTL822X_VND2_LED_POLAR(index)); 1994 else 1995 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1996 RTL822X_VND2_LCR7, 1997 RTL822X_VND2_LED_POLAR(index)); 1998 } 1999 2000 static int rtl822xb_led_hw_is_supported(struct phy_device *phydev, u8 index, 2001 unsigned long rules) 2002 { 2003 const unsigned long act_mask = BIT(TRIGGER_NETDEV_RX) | 2004 BIT(TRIGGER_NETDEV_TX); 2005 2006 const unsigned long link_mask = BIT(TRIGGER_NETDEV_LINK) | 2007 BIT(TRIGGER_NETDEV_LINK_10) | 2008 BIT(TRIGGER_NETDEV_LINK_100) | 2009 BIT(TRIGGER_NETDEV_LINK_1000) | 2010 BIT(TRIGGER_NETDEV_LINK_2500); 2011 2012 if (index >= RTL8211x_LED_COUNT) 2013 return -EINVAL; 2014 2015 /* Filter out any other unsupported triggers. */ 2016 if (rules & ~(link_mask | act_mask)) 2017 return -EOPNOTSUPP; 2018 2019 /* RX and TX are not differentiated, they are not possible 2020 * without combination with a link trigger. 2021 */ 2022 if ((rules & act_mask) && !(rules & link_mask)) 2023 return -EOPNOTSUPP; 2024 2025 return 0; 2026 } 2027 2028 static int rtl822xb_led_hw_control_get(struct phy_device *phydev, u8 index, 2029 unsigned long *rules) 2030 { 2031 int val; 2032 2033 if (index >= RTL8211x_LED_COUNT) 2034 return -EINVAL; 2035 2036 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LED(index)); 2037 if (val < 0) 2038 return val; 2039 2040 if (val & RTL822X_VND2_LCR_LINK_10) 2041 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 2042 2043 if (val & RTL822X_VND2_LCR_LINK_100) 2044 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 2045 2046 if (val & RTL822X_VND2_LCR_LINK_1000) 2047 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 2048 2049 if (val & RTL822X_VND2_LCR_LINK_2500) 2050 __set_bit(TRIGGER_NETDEV_LINK_2500, rules); 2051 2052 if ((val & RTL822X_VND2_LCR_LINK_10) && 2053 (val & RTL822X_VND2_LCR_LINK_100) && 2054 (val & RTL822X_VND2_LCR_LINK_1000) && 2055 (val & RTL822X_VND2_LCR_LINK_2500)) 2056 __set_bit(TRIGGER_NETDEV_LINK, rules); 2057 2058 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6); 2059 if (val < 0) 2060 return val; 2061 2062 if (val & RTL822X_VND2_LED_ACT(index)) { 2063 __set_bit(TRIGGER_NETDEV_RX, rules); 2064 __set_bit(TRIGGER_NETDEV_TX, rules); 2065 } 2066 2067 return 0; 2068 } 2069 2070 static int rtl822xb_led_hw_control_set(struct phy_device *phydev, u8 index, 2071 unsigned long rules) 2072 { 2073 u16 val = 0; 2074 bool act; 2075 int ret; 2076 2077 if (index >= RTL8211x_LED_COUNT) 2078 return -EINVAL; 2079 2080 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2081 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 2082 val |= RTL822X_VND2_LCR_LINK_10; 2083 2084 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2085 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 2086 val |= RTL822X_VND2_LCR_LINK_100; 2087 2088 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2089 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 2090 val |= RTL822X_VND2_LCR_LINK_1000; 2091 2092 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2093 test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) 2094 val |= RTL822X_VND2_LCR_LINK_2500; 2095 2096 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2097 RTL822X_VND2_LED(index), val); 2098 if (ret < 0) 2099 return ret; 2100 2101 act = test_bit(TRIGGER_NETDEV_RX, &rules) || 2102 test_bit(TRIGGER_NETDEV_TX, &rules); 2103 2104 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6, 2105 RTL822X_VND2_LED_ACT(index), act ? 2106 RTL822X_VND2_LED_ACT(index) : 0); 2107 if (ret < 0) 2108 return ret; 2109 2110 /* Reset polarity to default */ 2111 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR7, 2112 RTL822X_VND2_LED_POLAR(index)); 2113 } 2114 2115 static int rtl8224_cable_test_start(struct phy_device *phydev) 2116 { 2117 u32 val; 2118 int ret; 2119 2120 /* disable auto-negotiation and force 1000/Full */ 2121 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 2122 RTL822X_VND2_C22_REG(MII_BMCR), 2123 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 2124 BMCR_SPEED1000 | BMCR_FULLDPLX); 2125 if (ret) 2126 return ret; 2127 2128 mdelay(500); 2129 2130 /* trigger cable test */ 2131 val = RTL8224_MII_RTCT_ENABLE; 2132 val |= RTL8224_MII_RTCT_PAIR_A; 2133 val |= RTL8224_MII_RTCT_PAIR_B; 2134 val |= RTL8224_MII_RTCT_PAIR_C; 2135 val |= RTL8224_MII_RTCT_PAIR_D; 2136 2137 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 2138 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 2139 RTL8224_MII_RTCT_DONE, val); 2140 } 2141 2142 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 2143 { 2144 int ret; 2145 2146 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2147 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 2148 reg); 2149 if (ret) 2150 return ret; 2151 2152 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 2153 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 2154 } 2155 2156 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 2157 { 2158 int cable_len; 2159 u32 reg_len; 2160 int ret; 2161 u32 cm; 2162 2163 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 2164 2165 ret = rtl8224_sram_read(phydev, reg_len); 2166 if (ret < 0) 2167 return ret; 2168 2169 cable_len = ret & 0xff00; 2170 2171 ret = rtl8224_sram_read(phydev, reg_len + 1); 2172 if (ret < 0) 2173 return ret; 2174 2175 cable_len |= (ret & 0xff00) >> 8; 2176 2177 cable_len -= 620; 2178 cable_len = max(cable_len, 0); 2179 2180 cm = cable_len * 100 / 78; 2181 2182 return cm; 2183 } 2184 2185 static int rtl8224_cable_test_result_trans(u32 result) 2186 { 2187 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 2188 return -EBUSY; 2189 2190 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 2191 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 2192 2193 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 2194 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 2195 2196 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 2197 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 2198 2199 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 2200 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 2201 2202 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 2203 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 2204 2205 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 2206 } 2207 2208 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 2209 { 2210 int fault_rslt; 2211 int ret; 2212 2213 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 2214 if (ret < 0) 2215 return ret; 2216 2217 fault_rslt = rtl8224_cable_test_result_trans(ret); 2218 if (fault_rslt < 0) 2219 return 0; 2220 2221 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 2222 if (ret < 0) 2223 return ret; 2224 2225 switch (fault_rslt) { 2226 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 2227 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 2228 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 2229 ret = rtl8224_pair_len_get(phydev, pair); 2230 if (ret < 0) 2231 return ret; 2232 2233 return ethnl_cable_test_fault_length(phydev, pair, ret); 2234 default: 2235 return 0; 2236 } 2237 } 2238 2239 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 2240 { 2241 unsigned int pair; 2242 int ret; 2243 2244 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 2245 ret = rtl8224_cable_test_report_pair(phydev, pair); 2246 if (ret == -EBUSY) { 2247 *finished = false; 2248 return 0; 2249 } 2250 2251 if (ret < 0) 2252 return ret; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 2259 { 2260 int ret; 2261 2262 *finished = false; 2263 2264 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 2265 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 2266 if (ret < 0) 2267 return ret; 2268 2269 if (!(ret & RTL8224_MII_RTCT_DONE)) 2270 return 0; 2271 2272 *finished = true; 2273 2274 return rtl8224_cable_test_report(phydev, finished); 2275 } 2276 2277 static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, 2278 u32 regnum, u16 mask, u16 set) 2279 { 2280 int val, ret; 2281 2282 phy_lock_mdio_bus(phydev); 2283 2284 val = __phy_package_read_mmd(phydev, 0, devad, regnum); 2285 if (val < 0) { 2286 ret = val; 2287 goto exit; 2288 } 2289 2290 val &= ~mask; 2291 val |= set; 2292 2293 ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); 2294 2295 exit: 2296 phy_unlock_mdio_bus(phydev); 2297 return ret; 2298 } 2299 2300 static int rtl8224_mdi_config_order(struct phy_device *phydev) 2301 { 2302 struct device_node *np = phydev->mdio.dev.of_node; 2303 u8 port_offset = phydev->mdio.addr & 3; 2304 u32 order = 0; 2305 int ret; 2306 2307 ret = of_property_read_u32(np, "enet-phy-pair-order", &order); 2308 2309 /* Do nothing in case the property is not present */ 2310 if (ret == -EINVAL || ret == -ENOSYS) 2311 return 0; 2312 2313 if (ret) 2314 return ret; 2315 2316 if (order & ~1) 2317 return -EINVAL; 2318 2319 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2320 RTL8224_VND1_MDI_PAIR_SWAP, 2321 BIT(port_offset), 2322 order ? BIT(port_offset) : 0); 2323 } 2324 2325 static int rtl8224_mdi_config_polarity(struct phy_device *phydev) 2326 { 2327 struct device_node *np = phydev->mdio.dev.of_node; 2328 u8 offset = (phydev->mdio.addr & 3) * 4; 2329 u32 polarity = 0; 2330 int ret; 2331 2332 ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity); 2333 2334 /* Do nothing if the property is not present */ 2335 if (ret == -EINVAL || ret == -ENOSYS) 2336 return 0; 2337 2338 if (ret) 2339 return ret; 2340 2341 if (polarity & ~0xf) 2342 return -EINVAL; 2343 2344 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2345 RTL8224_VND1_MDI_POLARITY_SWAP, 2346 0xf << offset, 2347 polarity << offset); 2348 } 2349 2350 static int rtl8224_config_init(struct phy_device *phydev) 2351 { 2352 int ret; 2353 2354 ret = rtl8224_mdi_config_order(phydev); 2355 if (ret) 2356 return ret; 2357 2358 return rtl8224_mdi_config_polarity(phydev); 2359 } 2360 2361 static int rtl8224_probe(struct phy_device *phydev) 2362 { 2363 /* Chip exposes 4 ports, join all of them in the same package */ 2364 return devm_phy_package_join(&phydev->mdio.dev, phydev, 2365 phydev->mdio.addr & ~3, 0); 2366 } 2367 2368 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 2369 { 2370 int val; 2371 2372 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 2373 val = phy_read(phydev, 0x13); 2374 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 2375 2376 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 2377 } 2378 2379 /* On internal PHY's MMD reads over C22 always return 0. 2380 * Check a MMD register which is known to be non-zero. 2381 */ 2382 static bool rtlgen_supports_mmd(struct phy_device *phydev) 2383 { 2384 int val; 2385 2386 phy_lock_mdio_bus(phydev); 2387 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 2388 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 2389 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 2390 val = __phy_read(phydev, MII_MMD_DATA); 2391 phy_unlock_mdio_bus(phydev); 2392 2393 return val > 0; 2394 } 2395 2396 static int rtlgen_match_phy_device(struct phy_device *phydev, 2397 const struct phy_driver *phydrv) 2398 { 2399 return phydev->phy_id == RTL_GENERIC_PHYID && 2400 !rtlgen_supports_2_5gbps(phydev); 2401 } 2402 2403 static int rtl8226_match_phy_device(struct phy_device *phydev, 2404 const struct phy_driver *phydrv) 2405 { 2406 return phydev->phy_id == RTL_GENERIC_PHYID && 2407 rtlgen_supports_2_5gbps(phydev) && 2408 rtlgen_supports_mmd(phydev); 2409 } 2410 2411 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 2412 bool is_c45) 2413 { 2414 if (phydev->is_c45) 2415 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 2416 else 2417 return !is_c45 && (id == phydev->phy_id); 2418 } 2419 2420 static int rtl8221b_match_phy_device(struct phy_device *phydev, 2421 const struct phy_driver *phydrv) 2422 { 2423 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 2424 } 2425 2426 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 2427 const struct phy_driver *phydrv) 2428 { 2429 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 2430 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 2431 } 2432 2433 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 2434 const struct phy_driver *phydrv) 2435 { 2436 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 2437 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 2438 } 2439 2440 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 2441 const struct phy_driver *phydrv) 2442 { 2443 if (phydev->is_c45) 2444 return false; 2445 2446 switch (phydev->phy_id) { 2447 case RTL_GENERIC_PHYID: 2448 case RTL_8221B: 2449 case RTL_8251B: 2450 case RTL_8261C: 2451 case 0x001cc841: 2452 break; 2453 default: 2454 return false; 2455 } 2456 2457 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 2458 } 2459 2460 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 2461 const struct phy_driver *phydrv) 2462 { 2463 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 2464 } 2465 2466 static int rtlgen_resume(struct phy_device *phydev) 2467 { 2468 int ret = genphy_resume(phydev); 2469 2470 /* Internal PHY's from RTL8168h up may not be instantly ready */ 2471 msleep(20); 2472 2473 return ret; 2474 } 2475 2476 static int rtlgen_c45_resume(struct phy_device *phydev) 2477 { 2478 int ret = genphy_c45_pma_resume(phydev); 2479 2480 msleep(20); 2481 2482 return ret; 2483 } 2484 2485 static int rtl9000a_config_init(struct phy_device *phydev) 2486 { 2487 phydev->autoneg = AUTONEG_DISABLE; 2488 phydev->speed = SPEED_100; 2489 phydev->duplex = DUPLEX_FULL; 2490 2491 return 0; 2492 } 2493 2494 static int rtl9000a_config_aneg(struct phy_device *phydev) 2495 { 2496 int ret; 2497 u16 ctl = 0; 2498 2499 switch (phydev->master_slave_set) { 2500 case MASTER_SLAVE_CFG_MASTER_FORCE: 2501 ctl |= CTL1000_AS_MASTER; 2502 break; 2503 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2504 break; 2505 case MASTER_SLAVE_CFG_UNKNOWN: 2506 case MASTER_SLAVE_CFG_UNSUPPORTED: 2507 return 0; 2508 default: 2509 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2510 return -EOPNOTSUPP; 2511 } 2512 2513 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 2514 if (ret == 1) 2515 ret = genphy_soft_reset(phydev); 2516 2517 return ret; 2518 } 2519 2520 static int rtl9000a_read_status(struct phy_device *phydev) 2521 { 2522 int ret; 2523 2524 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 2525 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2526 2527 ret = genphy_update_link(phydev); 2528 if (ret) 2529 return ret; 2530 2531 ret = phy_read(phydev, MII_CTRL1000); 2532 if (ret < 0) 2533 return ret; 2534 if (ret & CTL1000_AS_MASTER) 2535 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 2536 else 2537 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 2538 2539 ret = phy_read(phydev, MII_STAT1000); 2540 if (ret < 0) 2541 return ret; 2542 if (ret & LPA_1000MSRES) 2543 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 2544 else 2545 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2546 2547 return 0; 2548 } 2549 2550 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2551 { 2552 int err; 2553 2554 err = phy_read(phydev, RTL8211F_INSR); 2555 2556 return (err < 0) ? err : 0; 2557 } 2558 2559 static int rtl9000a_config_intr(struct phy_device *phydev) 2560 { 2561 u16 val; 2562 int err; 2563 2564 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2565 err = rtl9000a_ack_interrupt(phydev); 2566 if (err) 2567 return err; 2568 2569 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2570 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2571 } else { 2572 val = ~0; 2573 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2574 if (err) 2575 return err; 2576 2577 err = rtl9000a_ack_interrupt(phydev); 2578 } 2579 2580 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2581 } 2582 2583 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2584 { 2585 int irq_status; 2586 2587 irq_status = phy_read(phydev, RTL8211F_INSR); 2588 if (irq_status < 0) { 2589 phy_error(phydev); 2590 return IRQ_NONE; 2591 } 2592 2593 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2594 return IRQ_NONE; 2595 2596 phy_trigger_machine(phydev); 2597 2598 return IRQ_HANDLED; 2599 } 2600 2601 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2602 { 2603 int err; 2604 2605 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2606 2607 return (err < 0) ? err : 0; 2608 } 2609 2610 static int rtl8221b_config_intr(struct phy_device *phydev) 2611 { 2612 int err; 2613 2614 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2615 err = rtl8221b_ack_interrupt(phydev); 2616 if (err) 2617 return err; 2618 2619 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2620 RTL8221B_VND2_INER_LINK_STATUS); 2621 } else { 2622 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2623 RTL8221B_VND2_INER, 0); 2624 if (err) 2625 return err; 2626 2627 err = rtl8221b_ack_interrupt(phydev); 2628 } 2629 2630 return err; 2631 } 2632 2633 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2634 { 2635 int err; 2636 2637 err = rtl8221b_ack_interrupt(phydev); 2638 if (err) { 2639 phy_error(phydev); 2640 return IRQ_NONE; 2641 } 2642 2643 phy_trigger_machine(phydev); 2644 2645 return IRQ_HANDLED; 2646 } 2647 2648 static int rtlgen_sfp_get_features(struct phy_device *phydev) 2649 { 2650 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2651 phydev->supported); 2652 2653 /* set default mode */ 2654 phydev->speed = SPEED_10000; 2655 phydev->duplex = DUPLEX_FULL; 2656 2657 phydev->port = PORT_FIBRE; 2658 2659 return 0; 2660 } 2661 2662 static int rtlgen_sfp_read_status(struct phy_device *phydev) 2663 { 2664 int val, err; 2665 2666 err = genphy_update_link(phydev); 2667 if (err) 2668 return err; 2669 2670 if (!phydev->link) 2671 return 0; 2672 2673 val = phy_read(phydev, RTL_PHYSR); 2674 if (val < 0) 2675 return val; 2676 2677 rtlgen_decode_physr(phydev, val); 2678 2679 return 0; 2680 } 2681 2682 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 2683 { 2684 return 0; 2685 } 2686 2687 static struct phy_driver realtek_drvs[] = { 2688 { 2689 PHY_ID_MATCH_EXACT(0x00008201), 2690 .name = "RTL8201CP Ethernet", 2691 .read_page = rtl821x_read_page, 2692 .write_page = rtl821x_write_page, 2693 }, { 2694 PHY_ID_MATCH_EXACT(0x001cc816), 2695 .name = "RTL8201F Fast Ethernet", 2696 .config_intr = &rtl8201_config_intr, 2697 .handle_interrupt = rtl8201_handle_interrupt, 2698 .suspend = genphy_suspend, 2699 .resume = genphy_resume, 2700 .read_page = rtl821x_read_page, 2701 .write_page = rtl821x_write_page, 2702 }, { 2703 PHY_ID_MATCH_MODEL(0x001cc880), 2704 .name = "RTL8208 Fast Ethernet", 2705 .read_mmd = genphy_read_mmd_unsupported, 2706 .write_mmd = genphy_write_mmd_unsupported, 2707 .suspend = genphy_suspend, 2708 .resume = genphy_resume, 2709 .read_page = rtl821x_read_page, 2710 .write_page = rtl821x_write_page, 2711 }, { 2712 PHY_ID_MATCH_EXACT(0x001cc910), 2713 .name = "RTL8211 Gigabit Ethernet", 2714 .config_aneg = rtl8211_config_aneg, 2715 .read_mmd = &genphy_read_mmd_unsupported, 2716 .write_mmd = &genphy_write_mmd_unsupported, 2717 .read_page = rtl821x_read_page, 2718 .write_page = rtl821x_write_page, 2719 }, { 2720 PHY_ID_MATCH_EXACT(0x001cc912), 2721 .name = "RTL8211B Gigabit Ethernet", 2722 .config_intr = &rtl8211b_config_intr, 2723 .handle_interrupt = rtl821x_handle_interrupt, 2724 .read_mmd = &genphy_read_mmd_unsupported, 2725 .write_mmd = &genphy_write_mmd_unsupported, 2726 .suspend = rtl8211b_suspend, 2727 .resume = rtl8211b_resume, 2728 .read_page = rtl821x_read_page, 2729 .write_page = rtl821x_write_page, 2730 }, { 2731 PHY_ID_MATCH_EXACT(0x001cc913), 2732 .name = "RTL8211C Gigabit Ethernet", 2733 .config_init = rtl8211c_config_init, 2734 .read_mmd = &genphy_read_mmd_unsupported, 2735 .write_mmd = &genphy_write_mmd_unsupported, 2736 .read_page = rtl821x_read_page, 2737 .write_page = rtl821x_write_page, 2738 }, { 2739 PHY_ID_MATCH_EXACT(0x001cc914), 2740 .name = "RTL8211DN Gigabit Ethernet", 2741 .config_intr = rtl8211e_config_intr, 2742 .handle_interrupt = rtl821x_handle_interrupt, 2743 .suspend = genphy_suspend, 2744 .resume = genphy_resume, 2745 .read_page = rtl821x_read_page, 2746 .write_page = rtl821x_write_page, 2747 }, { 2748 PHY_ID_MATCH_EXACT(0x001cc915), 2749 .name = "RTL8211E Gigabit Ethernet", 2750 .config_init = &rtl8211e_config_init, 2751 .config_intr = &rtl8211e_config_intr, 2752 .handle_interrupt = rtl821x_handle_interrupt, 2753 .suspend = genphy_suspend, 2754 .resume = genphy_resume, 2755 .read_page = rtl821x_read_page, 2756 .write_page = rtl821x_write_page, 2757 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2758 .led_hw_control_get = rtl8211e_led_hw_control_get, 2759 .led_hw_control_set = rtl8211e_led_hw_control_set, 2760 }, { 2761 PHY_ID_MATCH_EXACT(0x001cc916), 2762 .name = "RTL8211F Gigabit Ethernet", 2763 .probe = rtl8211f_probe, 2764 .config_init = &rtl8211f_config_init, 2765 .read_status = rtlgen_read_status, 2766 .config_intr = &rtl8211f_config_intr, 2767 .handle_interrupt = rtl8211f_handle_interrupt, 2768 .set_wol = rtl8211f_set_wol, 2769 .get_wol = rtl8211f_get_wol, 2770 .suspend = rtl8211f_suspend, 2771 .resume = rtl8211f_resume, 2772 .read_page = rtl821x_read_page, 2773 .write_page = rtl821x_write_page, 2774 .flags = PHY_ALWAYS_CALL_SUSPEND, 2775 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2776 .led_hw_control_get = rtl8211f_led_hw_control_get, 2777 .led_hw_control_set = rtl8211f_led_hw_control_set, 2778 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 2779 }, { 2780 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2781 .name = "RTL8211F-VD Gigabit Ethernet", 2782 .probe = rtl821x_probe, 2783 .config_init = &rtl8211f_config_init, 2784 .read_status = rtlgen_read_status, 2785 .config_intr = &rtl8211f_config_intr, 2786 .handle_interrupt = rtl8211f_handle_interrupt, 2787 .suspend = rtl821x_suspend, 2788 .resume = rtl821x_resume, 2789 .read_page = rtl821x_read_page, 2790 .write_page = rtl821x_write_page, 2791 .flags = PHY_ALWAYS_CALL_SUSPEND, 2792 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2793 .led_hw_control_get = rtl8211f_led_hw_control_get, 2794 .led_hw_control_set = rtl8211f_led_hw_control_set, 2795 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 2796 }, { 2797 .name = "Generic FE-GE Realtek PHY", 2798 .match_phy_device = rtlgen_match_phy_device, 2799 .read_status = rtlgen_read_status, 2800 .suspend = genphy_suspend, 2801 .resume = rtlgen_resume, 2802 .read_page = rtl821x_read_page, 2803 .write_page = rtl821x_write_page, 2804 .read_mmd = rtlgen_read_mmd, 2805 .write_mmd = rtlgen_write_mmd, 2806 }, { 2807 .name = "RTL8226 2.5Gbps PHY", 2808 .match_phy_device = rtl8226_match_phy_device, 2809 .get_features = rtl822x_get_features, 2810 .config_aneg = rtl822x_config_aneg, 2811 .read_status = rtl822x_read_status, 2812 .suspend = genphy_suspend, 2813 .resume = rtlgen_resume, 2814 .read_page = rtl821x_read_page, 2815 .write_page = rtl821x_write_page, 2816 .read_mmd = rtl822xb_read_mmd, 2817 .write_mmd = rtl822xb_write_mmd, 2818 }, { 2819 .match_phy_device = rtl8221b_match_phy_device, 2820 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2821 .get_features = rtl822x_get_features, 2822 .config_aneg = rtl822x_config_aneg, 2823 .config_init = rtl822xb_config_init, 2824 .inband_caps = rtl822x_inband_caps, 2825 .config_inband = rtl822x_config_inband, 2826 .get_rate_matching = rtl822xb_get_rate_matching, 2827 .read_status = rtl822xb_read_status, 2828 .suspend = genphy_suspend, 2829 .resume = rtlgen_resume, 2830 .read_page = rtl821x_read_page, 2831 .write_page = rtl821x_write_page, 2832 .read_mmd = rtl822xb_read_mmd, 2833 .write_mmd = rtl822xb_write_mmd, 2834 }, { 2835 PHY_ID_MATCH_EXACT(0x001cc838), 2836 .name = "RTL8226-CG 2.5Gbps PHY", 2837 .soft_reset = rtl822x_c45_soft_reset, 2838 .get_features = rtl822x_c45_get_features, 2839 .config_aneg = rtl822x_c45_config_aneg, 2840 .probe = rtl8226_probe, 2841 .config_init = rtl822x_config_init, 2842 .inband_caps = rtl822x_inband_caps, 2843 .config_inband = rtl822x_config_inband, 2844 .read_status = rtl822xb_c45_read_status, 2845 .suspend = genphy_c45_pma_suspend, 2846 .resume = rtlgen_c45_resume, 2847 .read_mmd = rtl822xb_read_mmd, 2848 .write_mmd = rtl822xb_write_mmd, 2849 }, { 2850 PHY_ID_MATCH_EXACT(0x001cc848), 2851 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2852 .get_features = rtl822x_get_features, 2853 .config_aneg = rtl822x_config_aneg, 2854 .config_init = rtl822xb_config_init, 2855 .inband_caps = rtl822x_inband_caps, 2856 .config_inband = rtl822x_config_inband, 2857 .get_rate_matching = rtl822xb_get_rate_matching, 2858 .read_status = rtl822xb_read_status, 2859 .suspend = genphy_suspend, 2860 .resume = rtlgen_resume, 2861 .read_page = rtl821x_read_page, 2862 .write_page = rtl821x_write_page, 2863 .read_mmd = rtl822xb_read_mmd, 2864 .write_mmd = rtl822xb_write_mmd, 2865 }, { 2866 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 2867 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 2868 .config_intr = rtl8221b_config_intr, 2869 .handle_interrupt = rtl8221b_handle_interrupt, 2870 .probe = rtl822x_probe, 2871 .config_init = rtl822xb_config_init, 2872 .inband_caps = rtl822x_inband_caps, 2873 .config_inband = rtl822x_config_inband, 2874 .get_rate_matching = rtl822xb_get_rate_matching, 2875 .get_features = rtl822x_c45_get_features, 2876 .config_aneg = rtl822x_c45_config_aneg, 2877 .read_status = rtl822xb_c45_read_status, 2878 .suspend = genphy_c45_pma_suspend, 2879 .resume = rtlgen_c45_resume, 2880 .read_page = rtl821x_read_page, 2881 .write_page = rtl821x_write_page, 2882 .read_mmd = rtl822xb_read_mmd, 2883 .write_mmd = rtl822xb_write_mmd, 2884 .led_brightness_set = rtl822xb_led_brightness_set, 2885 .led_hw_is_supported = rtl822xb_led_hw_is_supported, 2886 .led_hw_control_get = rtl822xb_led_hw_control_get, 2887 .led_hw_control_set = rtl822xb_led_hw_control_set, 2888 }, { 2889 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 2890 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 2891 .config_intr = rtl8221b_config_intr, 2892 .handle_interrupt = rtl8221b_handle_interrupt, 2893 .probe = rtl822x_probe, 2894 .config_init = rtl822xb_config_init, 2895 .inband_caps = rtl822x_inband_caps, 2896 .config_inband = rtl822x_config_inband, 2897 .get_rate_matching = rtl822xb_get_rate_matching, 2898 .get_features = rtl822x_c45_get_features, 2899 .config_aneg = rtl822x_c45_config_aneg, 2900 .read_status = rtl822xb_c45_read_status, 2901 .suspend = genphy_c45_pma_suspend, 2902 .resume = rtlgen_c45_resume, 2903 .read_page = rtl821x_read_page, 2904 .write_page = rtl821x_write_page, 2905 .read_mmd = rtl822xb_read_mmd, 2906 .write_mmd = rtl822xb_write_mmd, 2907 .led_brightness_set = rtl822xb_led_brightness_set, 2908 .led_hw_is_supported = rtl822xb_led_hw_is_supported, 2909 .led_hw_control_get = rtl822xb_led_hw_control_get, 2910 .led_hw_control_set = rtl822xb_led_hw_control_set, 2911 }, { 2912 .match_phy_device = rtl8251b_c45_match_phy_device, 2913 .name = "RTL8251B 5Gbps PHY", 2914 .probe = rtl822x_probe, 2915 .get_features = rtl822x_get_features, 2916 .config_aneg = rtl822x_config_aneg, 2917 .read_status = rtl822x_read_status, 2918 .suspend = genphy_suspend, 2919 .resume = rtlgen_resume, 2920 .read_page = rtl821x_read_page, 2921 .write_page = rtl821x_write_page, 2922 }, { 2923 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2924 .name = "Realtek Internal NBASE-T PHY", 2925 .flags = PHY_IS_INTERNAL, 2926 .probe = rtl822x_probe, 2927 .get_features = rtl822x_get_features, 2928 .config_aneg = rtl822x_config_aneg, 2929 .read_status = rtl822x_read_status, 2930 .suspend = genphy_suspend, 2931 .resume = rtlgen_resume, 2932 .read_page = rtl821x_read_page, 2933 .write_page = rtl821x_write_page, 2934 .read_mmd = rtl822x_read_mmd, 2935 .write_mmd = rtl822x_write_mmd, 2936 }, { 2937 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 2938 .name = "Realtek SFP PHY Mode", 2939 .flags = PHY_IS_INTERNAL, 2940 .probe = rtl822x_probe, 2941 .get_features = rtlgen_sfp_get_features, 2942 .config_aneg = rtlgen_sfp_config_aneg, 2943 .read_status = rtlgen_sfp_read_status, 2944 .suspend = genphy_suspend, 2945 .resume = rtlgen_resume, 2946 .read_page = rtl821x_read_page, 2947 .write_page = rtl821x_write_page, 2948 .read_mmd = rtl822x_read_mmd, 2949 .write_mmd = rtl822x_write_mmd, 2950 }, { 2951 PHY_ID_MATCH_EXACT(0x001ccad0), 2952 .name = "RTL8224 2.5Gbps PHY", 2953 .flags = PHY_POLL_CABLE_TEST, 2954 .probe = rtl8224_probe, 2955 .config_init = rtl8224_config_init, 2956 .get_features = rtl822x_c45_get_features, 2957 .config_aneg = rtl822x_c45_config_aneg, 2958 .read_status = rtl822x_c45_read_status, 2959 .suspend = genphy_c45_pma_suspend, 2960 .resume = rtlgen_c45_resume, 2961 .cable_test_start = rtl8224_cable_test_start, 2962 .cable_test_get_status = rtl8224_cable_test_get_status, 2963 }, { 2964 PHY_ID_MATCH_EXACT(0x001cc961), 2965 .name = "RTL8366RB Gigabit Ethernet", 2966 .config_init = &rtl8366rb_config_init, 2967 /* These interrupts are handled by the irq controller 2968 * embedded inside the RTL8366RB, they get unmasked when the 2969 * irq is requested and ACKed by reading the status register, 2970 * which is done by the irqchip code. 2971 */ 2972 .config_intr = genphy_no_config_intr, 2973 .handle_interrupt = genphy_handle_interrupt_no_ack, 2974 .suspend = genphy_suspend, 2975 .resume = genphy_resume, 2976 }, { 2977 PHY_ID_MATCH_EXACT(0x001ccb00), 2978 .name = "RTL9000AA_RTL9000AN Ethernet", 2979 .features = PHY_BASIC_T1_FEATURES, 2980 .config_init = rtl9000a_config_init, 2981 .config_aneg = rtl9000a_config_aneg, 2982 .read_status = rtl9000a_read_status, 2983 .config_intr = rtl9000a_config_intr, 2984 .handle_interrupt = rtl9000a_handle_interrupt, 2985 .suspend = genphy_suspend, 2986 .resume = genphy_resume, 2987 .read_page = rtl821x_read_page, 2988 .write_page = rtl821x_write_page, 2989 }, { 2990 PHY_ID_MATCH_EXACT(0x001cc942), 2991 .name = "RTL8365MB-VC Gigabit Ethernet", 2992 /* Interrupt handling analogous to RTL8366RB */ 2993 .config_intr = genphy_no_config_intr, 2994 .handle_interrupt = genphy_handle_interrupt_no_ack, 2995 .suspend = genphy_suspend, 2996 .resume = genphy_resume, 2997 }, { 2998 PHY_ID_MATCH_EXACT(0x001cc960), 2999 .name = "RTL8366S Gigabit Ethernet", 3000 .suspend = genphy_suspend, 3001 .resume = genphy_resume, 3002 .read_mmd = genphy_read_mmd_unsupported, 3003 .write_mmd = genphy_write_mmd_unsupported, 3004 }, 3005 }; 3006 3007 module_phy_driver(realtek_drvs); 3008 3009 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 3010 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 3011 { } 3012 }; 3013 3014 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 3015