1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/netdevice.h> 14 #include <linux/module.h> 15 #include <linux/delay.h> 16 #include <linux/clk.h> 17 #include <linux/string_choices.h> 18 19 #include "realtek.h" 20 21 #define RTL8201F_IER 0x13 22 23 #define RTL8201F_ISR 0x1e 24 #define RTL8201F_ISR_ANERR BIT(15) 25 #define RTL8201F_ISR_DUPLEX BIT(13) 26 #define RTL8201F_ISR_LINK BIT(11) 27 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 28 RTL8201F_ISR_DUPLEX | \ 29 RTL8201F_ISR_LINK) 30 31 #define RTL821x_INER 0x12 32 #define RTL8211B_INER_INIT 0x6400 33 #define RTL8211E_INER_LINK_STATUS BIT(10) 34 #define RTL8211F_INER_LINK_STATUS BIT(4) 35 36 #define RTL821x_INSR 0x13 37 38 #define RTL821x_EXT_PAGE_SELECT 0x1e 39 40 #define RTL821x_PAGE_SELECT 0x1f 41 #define RTL821x_SET_EXT_PAGE 0x07 42 43 /* RTL8211E extension page 44/0x2c */ 44 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 45 #define RTL8211E_LEDCR1 0x1a 46 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 47 #define RTL8211E_LEDCR1_MASK BIT(4) 48 #define RTL8211E_LEDCR1_SHIFT 1 49 50 #define RTL8211E_LEDCR2 0x1c 51 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 52 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 53 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 54 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 55 #define RTL8211E_LEDCR2_SHIFT 4 56 57 /* RTL8211E extension page 164/0xa4 */ 58 #define RTL8211E_RGMII_EXT_PAGE 0xa4 59 #define RTL8211E_RGMII_DELAY 0x1c 60 #define RTL8211E_CTRL_DELAY BIT(13) 61 #define RTL8211E_TX_DELAY BIT(12) 62 #define RTL8211E_RX_DELAY BIT(11) 63 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 64 65 /* RTL8211F PHY configuration */ 66 #define RTL8211F_PHYCR_PAGE 0xa43 67 #define RTL8211F_PHYCR1 0x18 68 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 69 #define RTL8211F_ALDPS_ENABLE BIT(2) 70 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 71 72 #define RTL8211F_PHYCR2 0x19 73 #define RTL8211F_CLKOUT_EN BIT(0) 74 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 75 76 #define RTL8211F_INSR_PAGE 0xa43 77 #define RTL8211F_INSR 0x1d 78 79 /* RTL8211F LED configuration */ 80 #define RTL8211F_LEDCR_PAGE 0xd04 81 #define RTL8211F_LEDCR 0x10 82 #define RTL8211F_LEDCR_MODE BIT(15) 83 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 84 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 85 #define RTL8211F_LEDCR_LINK_100 BIT(1) 86 #define RTL8211F_LEDCR_LINK_10 BIT(0) 87 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 88 #define RTL8211F_LEDCR_SHIFT 5 89 90 /* RTL8211F RGMII configuration */ 91 #define RTL8211F_RGMII_PAGE 0xd08 92 93 #define RTL8211F_TXCR 0x11 94 #define RTL8211F_TX_DELAY BIT(8) 95 96 #define RTL8211F_RXCR 0x15 97 #define RTL8211F_RX_DELAY BIT(3) 98 99 /* RTL8211F WOL interrupt configuration */ 100 #define RTL8211F_INTBCR_PAGE 0xd40 101 #define RTL8211F_INTBCR 0x16 102 #define RTL8211F_INTBCR_INTB_PMEB BIT(5) 103 104 /* RTL8211F WOL settings */ 105 #define RTL8211F_WOL_SETTINGS_PAGE 0xd8a 106 #define RTL8211F_WOL_SETTINGS_EVENTS 16 107 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 108 #define RTL8211F_WOL_SETTINGS_STATUS 17 109 #define RTL8211F_WOL_STATUS_RESET (BIT(15) | 0x1fff) 110 111 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 112 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 113 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 114 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 115 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 116 117 #define RTL822X_VND1_SERDES_OPTION 0x697a 118 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 119 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 120 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 121 122 #define RTL822X_VND1_SERDES_CTRL3 0x7580 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 124 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 125 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 126 127 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 128 * is set, they cannot be accessed by C45-over-C22. 129 */ 130 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 131 132 #define RTL8366RB_POWER_SAVE 0x15 133 #define RTL8366RB_POWER_SAVE_ON BIT(12) 134 135 #define RTL9000A_GINMR 0x14 136 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 137 138 #define RTL_VND2_PHYSR 0xa434 139 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 140 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 141 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 142 #define RTL_VND2_PHYSR_MASTER BIT(11) 143 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 144 145 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 146 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 147 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 148 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 149 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 150 #define RTL_MDIO_PMA_SPEED 0xa616 151 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 152 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 153 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 154 155 #define RTL_GENERIC_PHYID 0x001cc800 156 #define RTL_8211FVD_PHYID 0x001cc878 157 #define RTL_8221B 0x001cc840 158 #define RTL_8221B_VB_CG 0x001cc849 159 #define RTL_8221B_VN_CG 0x001cc84a 160 #define RTL_8251B 0x001cc862 161 162 /* RTL8211E and RTL8211F support up to three LEDs */ 163 #define RTL8211x_LED_COUNT 3 164 165 MODULE_DESCRIPTION("Realtek PHY driver"); 166 MODULE_AUTHOR("Johnson Leung"); 167 MODULE_LICENSE("GPL"); 168 169 struct rtl821x_priv { 170 u16 phycr1; 171 u16 phycr2; 172 bool has_phycr2; 173 struct clk *clk; 174 u32 saved_wolopts; 175 }; 176 177 static int rtl821x_read_page(struct phy_device *phydev) 178 { 179 return __phy_read(phydev, RTL821x_PAGE_SELECT); 180 } 181 182 static int rtl821x_write_page(struct phy_device *phydev, int page) 183 { 184 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 185 } 186 187 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 188 u32 regnum) 189 { 190 int oldpage, ret = 0; 191 192 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 193 if (oldpage >= 0) { 194 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 195 if (ret == 0) 196 ret = __phy_read(phydev, regnum); 197 } 198 199 return phy_restore_page(phydev, oldpage, ret); 200 } 201 202 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 203 u32 regnum, u16 mask, u16 set) 204 { 205 int oldpage, ret = 0; 206 207 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 208 if (oldpage >= 0) { 209 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 210 if (ret == 0) 211 ret = __phy_modify(phydev, regnum, mask, set); 212 } 213 214 return phy_restore_page(phydev, oldpage, ret); 215 } 216 217 static int rtl821x_probe(struct phy_device *phydev) 218 { 219 struct device *dev = &phydev->mdio.dev; 220 struct rtl821x_priv *priv; 221 u32 phy_id = phydev->drv->phy_id; 222 int ret; 223 224 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 225 if (!priv) 226 return -ENOMEM; 227 228 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 229 if (IS_ERR(priv->clk)) 230 return dev_err_probe(dev, PTR_ERR(priv->clk), 231 "failed to get phy clock\n"); 232 233 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 234 if (ret < 0) 235 return ret; 236 237 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 238 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 239 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 240 241 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 242 if (priv->has_phycr2) { 243 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 244 if (ret < 0) 245 return ret; 246 247 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 248 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 249 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 250 } 251 252 phydev->priv = priv; 253 254 return 0; 255 } 256 257 static int rtl8201_ack_interrupt(struct phy_device *phydev) 258 { 259 int err; 260 261 err = phy_read(phydev, RTL8201F_ISR); 262 263 return (err < 0) ? err : 0; 264 } 265 266 static int rtl821x_ack_interrupt(struct phy_device *phydev) 267 { 268 int err; 269 270 err = phy_read(phydev, RTL821x_INSR); 271 272 return (err < 0) ? err : 0; 273 } 274 275 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 276 { 277 int err; 278 279 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 280 281 return (err < 0) ? err : 0; 282 } 283 284 static int rtl8201_config_intr(struct phy_device *phydev) 285 { 286 u16 val; 287 int err; 288 289 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 290 err = rtl8201_ack_interrupt(phydev); 291 if (err) 292 return err; 293 294 val = BIT(13) | BIT(12) | BIT(11); 295 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 296 } else { 297 val = 0; 298 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 299 if (err) 300 return err; 301 302 err = rtl8201_ack_interrupt(phydev); 303 } 304 305 return err; 306 } 307 308 static int rtl8211b_config_intr(struct phy_device *phydev) 309 { 310 int err; 311 312 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 313 err = rtl821x_ack_interrupt(phydev); 314 if (err) 315 return err; 316 317 err = phy_write(phydev, RTL821x_INER, 318 RTL8211B_INER_INIT); 319 } else { 320 err = phy_write(phydev, RTL821x_INER, 0); 321 if (err) 322 return err; 323 324 err = rtl821x_ack_interrupt(phydev); 325 } 326 327 return err; 328 } 329 330 static int rtl8211e_config_intr(struct phy_device *phydev) 331 { 332 int err; 333 334 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 335 err = rtl821x_ack_interrupt(phydev); 336 if (err) 337 return err; 338 339 err = phy_write(phydev, RTL821x_INER, 340 RTL8211E_INER_LINK_STATUS); 341 } else { 342 err = phy_write(phydev, RTL821x_INER, 0); 343 if (err) 344 return err; 345 346 err = rtl821x_ack_interrupt(phydev); 347 } 348 349 return err; 350 } 351 352 static int rtl8211f_config_intr(struct phy_device *phydev) 353 { 354 u16 val; 355 int err; 356 357 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 358 err = rtl8211f_ack_interrupt(phydev); 359 if (err) 360 return err; 361 362 val = RTL8211F_INER_LINK_STATUS; 363 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 364 } else { 365 val = 0; 366 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 367 if (err) 368 return err; 369 370 err = rtl8211f_ack_interrupt(phydev); 371 } 372 373 return err; 374 } 375 376 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 377 { 378 int irq_status; 379 380 irq_status = phy_read(phydev, RTL8201F_ISR); 381 if (irq_status < 0) { 382 phy_error(phydev); 383 return IRQ_NONE; 384 } 385 386 if (!(irq_status & RTL8201F_ISR_MASK)) 387 return IRQ_NONE; 388 389 phy_trigger_machine(phydev); 390 391 return IRQ_HANDLED; 392 } 393 394 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 395 { 396 int irq_status, irq_enabled; 397 398 irq_status = phy_read(phydev, RTL821x_INSR); 399 if (irq_status < 0) { 400 phy_error(phydev); 401 return IRQ_NONE; 402 } 403 404 irq_enabled = phy_read(phydev, RTL821x_INER); 405 if (irq_enabled < 0) { 406 phy_error(phydev); 407 return IRQ_NONE; 408 } 409 410 if (!(irq_status & irq_enabled)) 411 return IRQ_NONE; 412 413 phy_trigger_machine(phydev); 414 415 return IRQ_HANDLED; 416 } 417 418 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 419 { 420 int irq_status; 421 422 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 423 if (irq_status < 0) { 424 phy_error(phydev); 425 return IRQ_NONE; 426 } 427 428 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 429 return IRQ_NONE; 430 431 phy_trigger_machine(phydev); 432 433 return IRQ_HANDLED; 434 } 435 436 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 437 { 438 wol->supported = WAKE_MAGIC; 439 if (phy_read_paged(dev, RTL8211F_WOL_SETTINGS_PAGE, RTL8211F_WOL_SETTINGS_EVENTS) 440 & RTL8211F_WOL_EVENT_MAGIC) 441 wol->wolopts = WAKE_MAGIC; 442 } 443 444 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 445 { 446 const u8 *mac_addr = dev->attached_dev->dev_addr; 447 int oldpage; 448 449 oldpage = phy_save_page(dev); 450 if (oldpage < 0) 451 goto err; 452 453 if (wol->wolopts & WAKE_MAGIC) { 454 /* Store the device address for the magic packet */ 455 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 456 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 457 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 458 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 459 460 /* Enable magic packet matching and reset WOL status */ 461 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 462 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 463 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 464 465 /* Enable the WOL interrupt */ 466 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 467 __phy_set_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 468 } else { 469 /* Disable the WOL interrupt */ 470 rtl821x_write_page(dev, RTL8211F_INTBCR_PAGE); 471 __phy_clear_bits(dev, RTL8211F_INTBCR, RTL8211F_INTBCR_INTB_PMEB); 472 473 /* Disable magic packet matching and reset WOL status */ 474 rtl821x_write_page(dev, RTL8211F_WOL_SETTINGS_PAGE); 475 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 476 __phy_write(dev, RTL8211F_WOL_SETTINGS_STATUS, RTL8211F_WOL_STATUS_RESET); 477 } 478 479 err: 480 return phy_restore_page(dev, oldpage, 0); 481 } 482 483 static int rtl8211_config_aneg(struct phy_device *phydev) 484 { 485 int ret; 486 487 ret = genphy_config_aneg(phydev); 488 if (ret < 0) 489 return ret; 490 491 /* Quirk was copied from vendor driver. Unfortunately it includes no 492 * description of the magic numbers. 493 */ 494 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 495 phy_write(phydev, 0x17, 0x2138); 496 phy_write(phydev, 0x0e, 0x0260); 497 } else { 498 phy_write(phydev, 0x17, 0x2108); 499 phy_write(phydev, 0x0e, 0x0000); 500 } 501 502 return 0; 503 } 504 505 static int rtl8211c_config_init(struct phy_device *phydev) 506 { 507 /* RTL8211C has an issue when operating in Gigabit slave mode */ 508 return phy_set_bits(phydev, MII_CTRL1000, 509 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 510 } 511 512 static int rtl8211f_config_init(struct phy_device *phydev) 513 { 514 struct rtl821x_priv *priv = phydev->priv; 515 struct device *dev = &phydev->mdio.dev; 516 u16 val_txdly, val_rxdly; 517 int ret; 518 519 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 520 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 521 priv->phycr1); 522 if (ret < 0) { 523 dev_err(dev, "aldps mode configuration failed: %pe\n", 524 ERR_PTR(ret)); 525 return ret; 526 } 527 528 switch (phydev->interface) { 529 case PHY_INTERFACE_MODE_RGMII: 530 val_txdly = 0; 531 val_rxdly = 0; 532 break; 533 534 case PHY_INTERFACE_MODE_RGMII_RXID: 535 val_txdly = 0; 536 val_rxdly = RTL8211F_RX_DELAY; 537 break; 538 539 case PHY_INTERFACE_MODE_RGMII_TXID: 540 val_txdly = RTL8211F_TX_DELAY; 541 val_rxdly = 0; 542 break; 543 544 case PHY_INTERFACE_MODE_RGMII_ID: 545 val_txdly = RTL8211F_TX_DELAY; 546 val_rxdly = RTL8211F_RX_DELAY; 547 break; 548 549 default: /* the rest of the modes imply leaving delay as is. */ 550 return 0; 551 } 552 553 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 554 RTL8211F_TXCR, RTL8211F_TX_DELAY, 555 val_txdly); 556 if (ret < 0) { 557 dev_err(dev, "Failed to update the TX delay register\n"); 558 return ret; 559 } else if (ret) { 560 dev_dbg(dev, 561 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 562 str_enable_disable(val_txdly)); 563 } else { 564 dev_dbg(dev, 565 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 566 str_enabled_disabled(val_txdly)); 567 } 568 569 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 570 RTL8211F_RXCR, RTL8211F_RX_DELAY, 571 val_rxdly); 572 if (ret < 0) { 573 dev_err(dev, "Failed to update the RX delay register\n"); 574 return ret; 575 } else if (ret) { 576 dev_dbg(dev, 577 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 578 str_enable_disable(val_rxdly)); 579 } else { 580 dev_dbg(dev, 581 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 582 str_enabled_disabled(val_rxdly)); 583 } 584 585 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 586 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 587 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 588 if (ret) 589 return ret; 590 591 if (priv->has_phycr2) { 592 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 593 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 594 priv->phycr2); 595 if (ret < 0) { 596 dev_err(dev, "clkout configuration failed: %pe\n", 597 ERR_PTR(ret)); 598 return ret; 599 } 600 601 return genphy_soft_reset(phydev); 602 } 603 604 return 0; 605 } 606 607 static int rtl821x_suspend(struct phy_device *phydev) 608 { 609 struct rtl821x_priv *priv = phydev->priv; 610 int ret = 0; 611 612 if (!phydev->wol_enabled) { 613 ret = genphy_suspend(phydev); 614 615 if (ret) 616 return ret; 617 618 clk_disable_unprepare(priv->clk); 619 } 620 621 return ret; 622 } 623 624 static int rtl821x_resume(struct phy_device *phydev) 625 { 626 struct rtl821x_priv *priv = phydev->priv; 627 int ret; 628 629 if (!phydev->wol_enabled) 630 clk_prepare_enable(priv->clk); 631 632 ret = genphy_resume(phydev); 633 if (ret < 0) 634 return ret; 635 636 msleep(20); 637 638 return 0; 639 } 640 641 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 642 unsigned long rules) 643 { 644 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 645 BIT(TRIGGER_NETDEV_LINK_100) | 646 BIT(TRIGGER_NETDEV_LINK_1000) | 647 BIT(TRIGGER_NETDEV_RX) | 648 BIT(TRIGGER_NETDEV_TX); 649 650 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 651 * - Link: Configurable subset of 10/100/1000 link rates 652 * - Active: Blink on activity, RX or TX is not differentiated 653 * The Active option has two modes, A and B: 654 * - A: Link and Active indication at configurable, but matching, 655 * subset of 10/100/1000 link rates 656 * - B: Link indication at configurable subset of 10/100/1000 link 657 * rates and Active indication always at all three 10+100+1000 658 * link rates. 659 * This code currently uses mode B only. 660 * 661 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 662 */ 663 664 if (index >= RTL8211x_LED_COUNT) 665 return -EINVAL; 666 667 /* Filter out any other unsupported triggers. */ 668 if (rules & ~mask) 669 return -EOPNOTSUPP; 670 671 /* RX and TX are not differentiated, either both are set or not set. */ 672 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 673 return -EOPNOTSUPP; 674 675 return 0; 676 } 677 678 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 679 unsigned long *rules) 680 { 681 int val; 682 683 if (index >= RTL8211x_LED_COUNT) 684 return -EINVAL; 685 686 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 687 if (val < 0) 688 return val; 689 690 val >>= RTL8211F_LEDCR_SHIFT * index; 691 val &= RTL8211F_LEDCR_MASK; 692 693 if (val & RTL8211F_LEDCR_LINK_10) 694 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 695 696 if (val & RTL8211F_LEDCR_LINK_100) 697 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 698 699 if (val & RTL8211F_LEDCR_LINK_1000) 700 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 701 702 if (val & RTL8211F_LEDCR_ACT_TXRX) { 703 __set_bit(TRIGGER_NETDEV_RX, rules); 704 __set_bit(TRIGGER_NETDEV_TX, rules); 705 } 706 707 return 0; 708 } 709 710 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 711 unsigned long rules) 712 { 713 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 714 u16 reg = 0; 715 716 if (index >= RTL8211x_LED_COUNT) 717 return -EINVAL; 718 719 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 720 reg |= RTL8211F_LEDCR_LINK_10; 721 722 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 723 reg |= RTL8211F_LEDCR_LINK_100; 724 725 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 726 reg |= RTL8211F_LEDCR_LINK_1000; 727 728 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 729 test_bit(TRIGGER_NETDEV_TX, &rules)) { 730 reg |= RTL8211F_LEDCR_ACT_TXRX; 731 } 732 733 reg <<= RTL8211F_LEDCR_SHIFT * index; 734 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 735 736 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 737 } 738 739 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 740 unsigned long *rules) 741 { 742 int ret; 743 u16 cr1, cr2; 744 745 if (index >= RTL8211x_LED_COUNT) 746 return -EINVAL; 747 748 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 749 RTL8211E_LEDCR1); 750 if (ret < 0) 751 return ret; 752 753 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 754 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 755 __set_bit(TRIGGER_NETDEV_RX, rules); 756 __set_bit(TRIGGER_NETDEV_TX, rules); 757 } 758 759 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 760 RTL8211E_LEDCR2); 761 if (ret < 0) 762 return ret; 763 764 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 765 if (cr2 & RTL8211E_LEDCR2_LINK_10) 766 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 767 768 if (cr2 & RTL8211E_LEDCR2_LINK_100) 769 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 770 771 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 772 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 773 774 return ret; 775 } 776 777 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 778 unsigned long rules) 779 { 780 const u16 cr1mask = 781 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 782 const u16 cr2mask = 783 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 784 u16 cr1 = 0, cr2 = 0; 785 int ret; 786 787 if (index >= RTL8211x_LED_COUNT) 788 return -EINVAL; 789 790 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 791 test_bit(TRIGGER_NETDEV_TX, &rules)) { 792 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 793 } 794 795 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 796 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 797 RTL8211E_LEDCR1, cr1mask, cr1); 798 if (ret < 0) 799 return ret; 800 801 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 802 cr2 |= RTL8211E_LEDCR2_LINK_10; 803 804 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 805 cr2 |= RTL8211E_LEDCR2_LINK_100; 806 807 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 808 cr2 |= RTL8211E_LEDCR2_LINK_1000; 809 810 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 811 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 812 RTL8211E_LEDCR2, cr2mask, cr2); 813 814 return ret; 815 } 816 817 static int rtl8211e_config_init(struct phy_device *phydev) 818 { 819 u16 val; 820 821 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 822 switch (phydev->interface) { 823 case PHY_INTERFACE_MODE_RGMII: 824 val = RTL8211E_CTRL_DELAY | 0; 825 break; 826 case PHY_INTERFACE_MODE_RGMII_ID: 827 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 828 break; 829 case PHY_INTERFACE_MODE_RGMII_RXID: 830 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 831 break; 832 case PHY_INTERFACE_MODE_RGMII_TXID: 833 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 834 break; 835 default: /* the rest of the modes imply leaving delays as is. */ 836 return 0; 837 } 838 839 /* According to a sample driver there is a 0x1c config register on the 840 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 841 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 842 * The configuration register definition: 843 * 14 = reserved 844 * 13 = Force Tx RX Delay controlled by bit12 bit11, 845 * 12 = RX Delay, 11 = TX Delay 846 * 10:0 = Test && debug settings reserved by realtek 847 */ 848 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 849 RTL8211E_RGMII_DELAY, 850 RTL8211E_DELAY_MASK, val); 851 } 852 853 static int rtl8211b_suspend(struct phy_device *phydev) 854 { 855 phy_write(phydev, MII_MMD_DATA, BIT(9)); 856 857 return genphy_suspend(phydev); 858 } 859 860 static int rtl8211b_resume(struct phy_device *phydev) 861 { 862 phy_write(phydev, MII_MMD_DATA, 0); 863 864 return genphy_resume(phydev); 865 } 866 867 static int rtl8366rb_config_init(struct phy_device *phydev) 868 { 869 int ret; 870 871 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 872 RTL8366RB_POWER_SAVE_ON); 873 if (ret) { 874 dev_err(&phydev->mdio.dev, 875 "error enabling power management\n"); 876 } 877 878 return ret; 879 } 880 881 /* get actual speed to cover the downshift case */ 882 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 883 { 884 /* bit 3 885 * 0: Half Duplex 886 * 1: Full Duplex 887 */ 888 if (val & RTL_VND2_PHYSR_DUPLEX) 889 phydev->duplex = DUPLEX_FULL; 890 else 891 phydev->duplex = DUPLEX_HALF; 892 893 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 894 case 0x0000: 895 phydev->speed = SPEED_10; 896 break; 897 case 0x0010: 898 phydev->speed = SPEED_100; 899 break; 900 case 0x0020: 901 phydev->speed = SPEED_1000; 902 break; 903 case 0x0200: 904 phydev->speed = SPEED_10000; 905 break; 906 case 0x0210: 907 phydev->speed = SPEED_2500; 908 break; 909 case 0x0220: 910 phydev->speed = SPEED_5000; 911 break; 912 default: 913 break; 914 } 915 916 /* bit 11 917 * 0: Slave Mode 918 * 1: Master Mode 919 */ 920 if (phydev->speed >= 1000) { 921 if (val & RTL_VND2_PHYSR_MASTER) 922 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 923 else 924 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 925 } else { 926 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 927 } 928 } 929 930 static int rtlgen_read_status(struct phy_device *phydev) 931 { 932 int ret, val; 933 934 ret = genphy_read_status(phydev); 935 if (ret < 0) 936 return ret; 937 938 if (!phydev->link) 939 return 0; 940 941 val = phy_read_paged(phydev, 0xa43, 0x12); 942 if (val < 0) 943 return val; 944 945 rtlgen_decode_physr(phydev, val); 946 947 return 0; 948 } 949 950 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 951 { 952 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 953 } 954 955 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 956 { 957 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 958 val); 959 } 960 961 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 962 { 963 int ret; 964 965 if (devnum == MDIO_MMD_VEND2) 966 ret = rtlgen_read_vend2(phydev, regnum); 967 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 968 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 969 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 970 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 971 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 972 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 973 else 974 ret = -EOPNOTSUPP; 975 976 return ret; 977 } 978 979 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 980 u16 val) 981 { 982 int ret; 983 984 if (devnum == MDIO_MMD_VEND2) 985 ret = rtlgen_write_vend2(phydev, regnum, val); 986 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 987 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 988 else 989 ret = -EOPNOTSUPP; 990 991 return ret; 992 } 993 994 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 995 { 996 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 997 998 if (ret != -EOPNOTSUPP) 999 return ret; 1000 1001 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1002 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1003 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1004 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1005 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1006 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1007 1008 return ret; 1009 } 1010 1011 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1012 u16 val) 1013 { 1014 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1015 1016 if (ret != -EOPNOTSUPP) 1017 return ret; 1018 1019 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1020 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1021 1022 return ret; 1023 } 1024 1025 static int rtl822x_probe(struct phy_device *phydev) 1026 { 1027 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1028 phydev->phy_id != RTL_GENERIC_PHYID) 1029 return rtl822x_hwmon_init(phydev); 1030 1031 return 0; 1032 } 1033 1034 static int rtl822xb_config_init(struct phy_device *phydev) 1035 { 1036 bool has_2500, has_sgmii; 1037 u16 mode; 1038 int ret; 1039 1040 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1041 phydev->host_interfaces) || 1042 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1043 1044 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1045 phydev->host_interfaces) || 1046 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1047 1048 /* fill in possible interfaces */ 1049 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1050 has_2500); 1051 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1052 has_sgmii); 1053 1054 if (!has_2500 && !has_sgmii) 1055 return 0; 1056 1057 /* determine SerDes option mode */ 1058 if (has_2500 && !has_sgmii) { 1059 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1060 phydev->rate_matching = RATE_MATCH_PAUSE; 1061 } else { 1062 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1063 phydev->rate_matching = RATE_MATCH_NONE; 1064 } 1065 1066 /* the following sequence with magic numbers sets up the SerDes 1067 * option mode 1068 */ 1069 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1070 if (ret < 0) 1071 return ret; 1072 1073 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1074 RTL822X_VND1_SERDES_OPTION, 1075 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1076 mode); 1077 if (ret < 0) 1078 return ret; 1079 1080 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1081 if (ret < 0) 1082 return ret; 1083 1084 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1085 if (ret < 0) 1086 return ret; 1087 1088 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1089 } 1090 1091 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1092 phy_interface_t iface) 1093 { 1094 int val; 1095 1096 /* Only rate matching at 2500base-x */ 1097 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1098 return RATE_MATCH_NONE; 1099 1100 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1101 if (val < 0) 1102 return val; 1103 1104 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1105 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1106 return RATE_MATCH_PAUSE; 1107 1108 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1109 return RATE_MATCH_NONE; 1110 } 1111 1112 static int rtl822x_get_features(struct phy_device *phydev) 1113 { 1114 int val; 1115 1116 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1117 if (val < 0) 1118 return val; 1119 1120 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1121 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1122 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1123 phydev->supported, val & MDIO_PMA_SPEED_5G); 1124 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1125 phydev->supported, val & MDIO_SPEED_10G); 1126 1127 return genphy_read_abilities(phydev); 1128 } 1129 1130 static int rtl822x_config_aneg(struct phy_device *phydev) 1131 { 1132 int ret = 0; 1133 1134 if (phydev->autoneg == AUTONEG_ENABLE) { 1135 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1136 1137 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1138 RTL_MDIO_AN_10GBT_CTRL, 1139 MDIO_AN_10GBT_CTRL_ADV2_5G | 1140 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1141 if (ret < 0) 1142 return ret; 1143 } 1144 1145 return __genphy_config_aneg(phydev, ret); 1146 } 1147 1148 static void rtl822xb_update_interface(struct phy_device *phydev) 1149 { 1150 int val; 1151 1152 if (!phydev->link) 1153 return; 1154 1155 /* Change interface according to serdes mode */ 1156 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1157 if (val < 0) 1158 return; 1159 1160 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1161 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1162 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1163 break; 1164 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1165 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1166 break; 1167 } 1168 } 1169 1170 static int rtl822x_read_status(struct phy_device *phydev) 1171 { 1172 int lpadv, ret; 1173 1174 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1175 1176 ret = rtlgen_read_status(phydev); 1177 if (ret < 0) 1178 return ret; 1179 1180 if (phydev->autoneg == AUTONEG_DISABLE || 1181 !phydev->autoneg_complete) 1182 return 0; 1183 1184 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1185 if (lpadv < 0) 1186 return lpadv; 1187 1188 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1189 1190 return 0; 1191 } 1192 1193 static int rtl822xb_read_status(struct phy_device *phydev) 1194 { 1195 int ret; 1196 1197 ret = rtl822x_read_status(phydev); 1198 if (ret < 0) 1199 return ret; 1200 1201 rtl822xb_update_interface(phydev); 1202 1203 return 0; 1204 } 1205 1206 static int rtl822x_c45_get_features(struct phy_device *phydev) 1207 { 1208 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1209 phydev->supported); 1210 1211 return genphy_c45_pma_read_abilities(phydev); 1212 } 1213 1214 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1215 { 1216 bool changed = false; 1217 int ret, val; 1218 1219 if (phydev->autoneg == AUTONEG_DISABLE) 1220 return genphy_c45_pma_setup_forced(phydev); 1221 1222 ret = genphy_c45_an_config_aneg(phydev); 1223 if (ret < 0) 1224 return ret; 1225 if (ret > 0) 1226 changed = true; 1227 1228 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1229 1230 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1231 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1232 RTL822X_VND2_C22_REG(MII_CTRL1000), 1233 ADVERTISE_1000FULL, val); 1234 if (ret < 0) 1235 return ret; 1236 if (ret > 0) 1237 changed = true; 1238 1239 return genphy_c45_check_and_restart_aneg(phydev, changed); 1240 } 1241 1242 static int rtl822x_c45_read_status(struct phy_device *phydev) 1243 { 1244 int ret, val; 1245 1246 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1247 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1248 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1249 RTL822X_VND2_C22_REG(MII_STAT1000)); 1250 if (val < 0) 1251 return val; 1252 } else { 1253 val = 0; 1254 } 1255 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1256 1257 ret = genphy_c45_read_status(phydev); 1258 if (ret < 0) 1259 return ret; 1260 1261 if (!phydev->link) { 1262 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1263 return 0; 1264 } 1265 1266 /* Read actual speed from vendor register. */ 1267 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1268 if (val < 0) 1269 return val; 1270 1271 rtlgen_decode_physr(phydev, val); 1272 1273 return 0; 1274 } 1275 1276 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1277 { 1278 int ret; 1279 1280 ret = rtl822x_c45_read_status(phydev); 1281 if (ret < 0) 1282 return ret; 1283 1284 rtl822xb_update_interface(phydev); 1285 1286 return 0; 1287 } 1288 1289 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1290 { 1291 int val; 1292 1293 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1294 val = phy_read(phydev, 0x13); 1295 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1296 1297 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1298 } 1299 1300 /* On internal PHY's MMD reads over C22 always return 0. 1301 * Check a MMD register which is known to be non-zero. 1302 */ 1303 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1304 { 1305 int val; 1306 1307 phy_lock_mdio_bus(phydev); 1308 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1309 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1310 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1311 val = __phy_read(phydev, MII_MMD_DATA); 1312 phy_unlock_mdio_bus(phydev); 1313 1314 return val > 0; 1315 } 1316 1317 static int rtlgen_match_phy_device(struct phy_device *phydev) 1318 { 1319 return phydev->phy_id == RTL_GENERIC_PHYID && 1320 !rtlgen_supports_2_5gbps(phydev); 1321 } 1322 1323 static int rtl8226_match_phy_device(struct phy_device *phydev) 1324 { 1325 return phydev->phy_id == RTL_GENERIC_PHYID && 1326 rtlgen_supports_2_5gbps(phydev) && 1327 rtlgen_supports_mmd(phydev); 1328 } 1329 1330 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1331 bool is_c45) 1332 { 1333 if (phydev->is_c45) 1334 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1335 else 1336 return !is_c45 && (id == phydev->phy_id); 1337 } 1338 1339 static int rtl8221b_match_phy_device(struct phy_device *phydev) 1340 { 1341 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1342 } 1343 1344 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) 1345 { 1346 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1347 } 1348 1349 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) 1350 { 1351 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1352 } 1353 1354 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) 1355 { 1356 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1357 } 1358 1359 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) 1360 { 1361 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1362 } 1363 1364 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) 1365 { 1366 if (phydev->is_c45) 1367 return false; 1368 1369 switch (phydev->phy_id) { 1370 case RTL_GENERIC_PHYID: 1371 case RTL_8221B: 1372 case RTL_8251B: 1373 case 0x001cc841: 1374 break; 1375 default: 1376 return false; 1377 } 1378 1379 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1380 } 1381 1382 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) 1383 { 1384 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1385 } 1386 1387 static int rtlgen_resume(struct phy_device *phydev) 1388 { 1389 int ret = genphy_resume(phydev); 1390 1391 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1392 msleep(20); 1393 1394 return ret; 1395 } 1396 1397 static int rtlgen_c45_resume(struct phy_device *phydev) 1398 { 1399 int ret = genphy_c45_pma_resume(phydev); 1400 1401 msleep(20); 1402 1403 return ret; 1404 } 1405 1406 static int rtl9000a_config_init(struct phy_device *phydev) 1407 { 1408 phydev->autoneg = AUTONEG_DISABLE; 1409 phydev->speed = SPEED_100; 1410 phydev->duplex = DUPLEX_FULL; 1411 1412 return 0; 1413 } 1414 1415 static int rtl9000a_config_aneg(struct phy_device *phydev) 1416 { 1417 int ret; 1418 u16 ctl = 0; 1419 1420 switch (phydev->master_slave_set) { 1421 case MASTER_SLAVE_CFG_MASTER_FORCE: 1422 ctl |= CTL1000_AS_MASTER; 1423 break; 1424 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1425 break; 1426 case MASTER_SLAVE_CFG_UNKNOWN: 1427 case MASTER_SLAVE_CFG_UNSUPPORTED: 1428 return 0; 1429 default: 1430 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1431 return -EOPNOTSUPP; 1432 } 1433 1434 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1435 if (ret == 1) 1436 ret = genphy_soft_reset(phydev); 1437 1438 return ret; 1439 } 1440 1441 static int rtl9000a_read_status(struct phy_device *phydev) 1442 { 1443 int ret; 1444 1445 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1446 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1447 1448 ret = genphy_update_link(phydev); 1449 if (ret) 1450 return ret; 1451 1452 ret = phy_read(phydev, MII_CTRL1000); 1453 if (ret < 0) 1454 return ret; 1455 if (ret & CTL1000_AS_MASTER) 1456 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1457 else 1458 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1459 1460 ret = phy_read(phydev, MII_STAT1000); 1461 if (ret < 0) 1462 return ret; 1463 if (ret & LPA_1000MSRES) 1464 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1465 else 1466 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1467 1468 return 0; 1469 } 1470 1471 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1472 { 1473 int err; 1474 1475 err = phy_read(phydev, RTL8211F_INSR); 1476 1477 return (err < 0) ? err : 0; 1478 } 1479 1480 static int rtl9000a_config_intr(struct phy_device *phydev) 1481 { 1482 u16 val; 1483 int err; 1484 1485 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1486 err = rtl9000a_ack_interrupt(phydev); 1487 if (err) 1488 return err; 1489 1490 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1491 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1492 } else { 1493 val = ~0; 1494 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1495 if (err) 1496 return err; 1497 1498 err = rtl9000a_ack_interrupt(phydev); 1499 } 1500 1501 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1502 } 1503 1504 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1505 { 1506 int irq_status; 1507 1508 irq_status = phy_read(phydev, RTL8211F_INSR); 1509 if (irq_status < 0) { 1510 phy_error(phydev); 1511 return IRQ_NONE; 1512 } 1513 1514 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1515 return IRQ_NONE; 1516 1517 phy_trigger_machine(phydev); 1518 1519 return IRQ_HANDLED; 1520 } 1521 1522 static struct phy_driver realtek_drvs[] = { 1523 { 1524 PHY_ID_MATCH_EXACT(0x00008201), 1525 .name = "RTL8201CP Ethernet", 1526 .read_page = rtl821x_read_page, 1527 .write_page = rtl821x_write_page, 1528 }, { 1529 PHY_ID_MATCH_EXACT(0x001cc816), 1530 .name = "RTL8201F Fast Ethernet", 1531 .config_intr = &rtl8201_config_intr, 1532 .handle_interrupt = rtl8201_handle_interrupt, 1533 .suspend = genphy_suspend, 1534 .resume = genphy_resume, 1535 .read_page = rtl821x_read_page, 1536 .write_page = rtl821x_write_page, 1537 }, { 1538 PHY_ID_MATCH_MODEL(0x001cc880), 1539 .name = "RTL8208 Fast Ethernet", 1540 .read_mmd = genphy_read_mmd_unsupported, 1541 .write_mmd = genphy_write_mmd_unsupported, 1542 .suspend = genphy_suspend, 1543 .resume = genphy_resume, 1544 .read_page = rtl821x_read_page, 1545 .write_page = rtl821x_write_page, 1546 }, { 1547 PHY_ID_MATCH_EXACT(0x001cc910), 1548 .name = "RTL8211 Gigabit Ethernet", 1549 .config_aneg = rtl8211_config_aneg, 1550 .read_mmd = &genphy_read_mmd_unsupported, 1551 .write_mmd = &genphy_write_mmd_unsupported, 1552 .read_page = rtl821x_read_page, 1553 .write_page = rtl821x_write_page, 1554 }, { 1555 PHY_ID_MATCH_EXACT(0x001cc912), 1556 .name = "RTL8211B Gigabit Ethernet", 1557 .config_intr = &rtl8211b_config_intr, 1558 .handle_interrupt = rtl821x_handle_interrupt, 1559 .read_mmd = &genphy_read_mmd_unsupported, 1560 .write_mmd = &genphy_write_mmd_unsupported, 1561 .suspend = rtl8211b_suspend, 1562 .resume = rtl8211b_resume, 1563 .read_page = rtl821x_read_page, 1564 .write_page = rtl821x_write_page, 1565 }, { 1566 PHY_ID_MATCH_EXACT(0x001cc913), 1567 .name = "RTL8211C Gigabit Ethernet", 1568 .config_init = rtl8211c_config_init, 1569 .read_mmd = &genphy_read_mmd_unsupported, 1570 .write_mmd = &genphy_write_mmd_unsupported, 1571 .read_page = rtl821x_read_page, 1572 .write_page = rtl821x_write_page, 1573 }, { 1574 PHY_ID_MATCH_EXACT(0x001cc914), 1575 .name = "RTL8211DN Gigabit Ethernet", 1576 .config_intr = rtl8211e_config_intr, 1577 .handle_interrupt = rtl821x_handle_interrupt, 1578 .suspend = genphy_suspend, 1579 .resume = genphy_resume, 1580 .read_page = rtl821x_read_page, 1581 .write_page = rtl821x_write_page, 1582 }, { 1583 PHY_ID_MATCH_EXACT(0x001cc915), 1584 .name = "RTL8211E Gigabit Ethernet", 1585 .config_init = &rtl8211e_config_init, 1586 .config_intr = &rtl8211e_config_intr, 1587 .handle_interrupt = rtl821x_handle_interrupt, 1588 .suspend = genphy_suspend, 1589 .resume = genphy_resume, 1590 .read_page = rtl821x_read_page, 1591 .write_page = rtl821x_write_page, 1592 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1593 .led_hw_control_get = rtl8211e_led_hw_control_get, 1594 .led_hw_control_set = rtl8211e_led_hw_control_set, 1595 }, { 1596 PHY_ID_MATCH_EXACT(0x001cc916), 1597 .name = "RTL8211F Gigabit Ethernet", 1598 .probe = rtl821x_probe, 1599 .config_init = &rtl8211f_config_init, 1600 .read_status = rtlgen_read_status, 1601 .config_intr = &rtl8211f_config_intr, 1602 .handle_interrupt = rtl8211f_handle_interrupt, 1603 .set_wol = rtl8211f_set_wol, 1604 .get_wol = rtl8211f_get_wol, 1605 .suspend = rtl821x_suspend, 1606 .resume = rtl821x_resume, 1607 .read_page = rtl821x_read_page, 1608 .write_page = rtl821x_write_page, 1609 .flags = PHY_ALWAYS_CALL_SUSPEND, 1610 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1611 .led_hw_control_get = rtl8211f_led_hw_control_get, 1612 .led_hw_control_set = rtl8211f_led_hw_control_set, 1613 }, { 1614 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1615 .name = "RTL8211F-VD Gigabit Ethernet", 1616 .probe = rtl821x_probe, 1617 .config_init = &rtl8211f_config_init, 1618 .read_status = rtlgen_read_status, 1619 .config_intr = &rtl8211f_config_intr, 1620 .handle_interrupt = rtl8211f_handle_interrupt, 1621 .suspend = rtl821x_suspend, 1622 .resume = rtl821x_resume, 1623 .read_page = rtl821x_read_page, 1624 .write_page = rtl821x_write_page, 1625 .flags = PHY_ALWAYS_CALL_SUSPEND, 1626 }, { 1627 .name = "Generic FE-GE Realtek PHY", 1628 .match_phy_device = rtlgen_match_phy_device, 1629 .read_status = rtlgen_read_status, 1630 .suspend = genphy_suspend, 1631 .resume = rtlgen_resume, 1632 .read_page = rtl821x_read_page, 1633 .write_page = rtl821x_write_page, 1634 .read_mmd = rtlgen_read_mmd, 1635 .write_mmd = rtlgen_write_mmd, 1636 }, { 1637 .name = "RTL8226 2.5Gbps PHY", 1638 .match_phy_device = rtl8226_match_phy_device, 1639 .get_features = rtl822x_get_features, 1640 .config_aneg = rtl822x_config_aneg, 1641 .read_status = rtl822x_read_status, 1642 .suspend = genphy_suspend, 1643 .resume = rtlgen_resume, 1644 .read_page = rtl821x_read_page, 1645 .write_page = rtl821x_write_page, 1646 }, { 1647 .match_phy_device = rtl8221b_match_phy_device, 1648 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1649 .get_features = rtl822x_get_features, 1650 .config_aneg = rtl822x_config_aneg, 1651 .config_init = rtl822xb_config_init, 1652 .get_rate_matching = rtl822xb_get_rate_matching, 1653 .read_status = rtl822xb_read_status, 1654 .suspend = genphy_suspend, 1655 .resume = rtlgen_resume, 1656 .read_page = rtl821x_read_page, 1657 .write_page = rtl821x_write_page, 1658 }, { 1659 PHY_ID_MATCH_EXACT(0x001cc838), 1660 .name = "RTL8226-CG 2.5Gbps PHY", 1661 .get_features = rtl822x_get_features, 1662 .config_aneg = rtl822x_config_aneg, 1663 .read_status = rtl822x_read_status, 1664 .suspend = genphy_suspend, 1665 .resume = rtlgen_resume, 1666 .read_page = rtl821x_read_page, 1667 .write_page = rtl821x_write_page, 1668 }, { 1669 PHY_ID_MATCH_EXACT(0x001cc848), 1670 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1671 .get_features = rtl822x_get_features, 1672 .config_aneg = rtl822x_config_aneg, 1673 .config_init = rtl822xb_config_init, 1674 .get_rate_matching = rtl822xb_get_rate_matching, 1675 .read_status = rtl822xb_read_status, 1676 .suspend = genphy_suspend, 1677 .resume = rtlgen_resume, 1678 .read_page = rtl821x_read_page, 1679 .write_page = rtl821x_write_page, 1680 }, { 1681 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1682 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1683 .probe = rtl822x_probe, 1684 .get_features = rtl822x_get_features, 1685 .config_aneg = rtl822x_config_aneg, 1686 .config_init = rtl822xb_config_init, 1687 .get_rate_matching = rtl822xb_get_rate_matching, 1688 .read_status = rtl822xb_read_status, 1689 .suspend = genphy_suspend, 1690 .resume = rtlgen_resume, 1691 .read_page = rtl821x_read_page, 1692 .write_page = rtl821x_write_page, 1693 }, { 1694 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1695 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1696 .probe = rtl822x_probe, 1697 .config_init = rtl822xb_config_init, 1698 .get_rate_matching = rtl822xb_get_rate_matching, 1699 .get_features = rtl822x_c45_get_features, 1700 .config_aneg = rtl822x_c45_config_aneg, 1701 .read_status = rtl822xb_c45_read_status, 1702 .suspend = genphy_c45_pma_suspend, 1703 .resume = rtlgen_c45_resume, 1704 }, { 1705 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1706 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1707 .probe = rtl822x_probe, 1708 .get_features = rtl822x_get_features, 1709 .config_aneg = rtl822x_config_aneg, 1710 .config_init = rtl822xb_config_init, 1711 .get_rate_matching = rtl822xb_get_rate_matching, 1712 .read_status = rtl822xb_read_status, 1713 .suspend = genphy_suspend, 1714 .resume = rtlgen_resume, 1715 .read_page = rtl821x_read_page, 1716 .write_page = rtl821x_write_page, 1717 }, { 1718 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1719 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1720 .probe = rtl822x_probe, 1721 .config_init = rtl822xb_config_init, 1722 .get_rate_matching = rtl822xb_get_rate_matching, 1723 .get_features = rtl822x_c45_get_features, 1724 .config_aneg = rtl822x_c45_config_aneg, 1725 .read_status = rtl822xb_c45_read_status, 1726 .suspend = genphy_c45_pma_suspend, 1727 .resume = rtlgen_c45_resume, 1728 }, { 1729 .match_phy_device = rtl8251b_c45_match_phy_device, 1730 .name = "RTL8251B 5Gbps PHY", 1731 .probe = rtl822x_probe, 1732 .get_features = rtl822x_get_features, 1733 .config_aneg = rtl822x_config_aneg, 1734 .read_status = rtl822x_read_status, 1735 .suspend = genphy_suspend, 1736 .resume = rtlgen_resume, 1737 .read_page = rtl821x_read_page, 1738 .write_page = rtl821x_write_page, 1739 }, { 1740 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1741 .name = "Realtek Internal NBASE-T PHY", 1742 .flags = PHY_IS_INTERNAL, 1743 .probe = rtl822x_probe, 1744 .get_features = rtl822x_get_features, 1745 .config_aneg = rtl822x_config_aneg, 1746 .read_status = rtl822x_read_status, 1747 .suspend = genphy_suspend, 1748 .resume = rtlgen_resume, 1749 .read_page = rtl821x_read_page, 1750 .write_page = rtl821x_write_page, 1751 .read_mmd = rtl822x_read_mmd, 1752 .write_mmd = rtl822x_write_mmd, 1753 }, { 1754 PHY_ID_MATCH_EXACT(0x001ccad0), 1755 .name = "RTL8224 2.5Gbps PHY", 1756 .get_features = rtl822x_c45_get_features, 1757 .config_aneg = rtl822x_c45_config_aneg, 1758 .read_status = rtl822x_c45_read_status, 1759 .suspend = genphy_c45_pma_suspend, 1760 .resume = rtlgen_c45_resume, 1761 }, { 1762 PHY_ID_MATCH_EXACT(0x001cc961), 1763 .name = "RTL8366RB Gigabit Ethernet", 1764 .config_init = &rtl8366rb_config_init, 1765 /* These interrupts are handled by the irq controller 1766 * embedded inside the RTL8366RB, they get unmasked when the 1767 * irq is requested and ACKed by reading the status register, 1768 * which is done by the irqchip code. 1769 */ 1770 .config_intr = genphy_no_config_intr, 1771 .handle_interrupt = genphy_handle_interrupt_no_ack, 1772 .suspend = genphy_suspend, 1773 .resume = genphy_resume, 1774 }, { 1775 PHY_ID_MATCH_EXACT(0x001ccb00), 1776 .name = "RTL9000AA_RTL9000AN Ethernet", 1777 .features = PHY_BASIC_T1_FEATURES, 1778 .config_init = rtl9000a_config_init, 1779 .config_aneg = rtl9000a_config_aneg, 1780 .read_status = rtl9000a_read_status, 1781 .config_intr = rtl9000a_config_intr, 1782 .handle_interrupt = rtl9000a_handle_interrupt, 1783 .suspend = genphy_suspend, 1784 .resume = genphy_resume, 1785 .read_page = rtl821x_read_page, 1786 .write_page = rtl821x_write_page, 1787 }, { 1788 PHY_ID_MATCH_EXACT(0x001cc942), 1789 .name = "RTL8365MB-VC Gigabit Ethernet", 1790 /* Interrupt handling analogous to RTL8366RB */ 1791 .config_intr = genphy_no_config_intr, 1792 .handle_interrupt = genphy_handle_interrupt_no_ack, 1793 .suspend = genphy_suspend, 1794 .resume = genphy_resume, 1795 }, { 1796 PHY_ID_MATCH_EXACT(0x001cc960), 1797 .name = "RTL8366S Gigabit Ethernet", 1798 .suspend = genphy_suspend, 1799 .resume = genphy_resume, 1800 .read_mmd = genphy_read_mmd_unsupported, 1801 .write_mmd = genphy_write_mmd_unsupported, 1802 }, 1803 }; 1804 1805 module_phy_driver(realtek_drvs); 1806 1807 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1808 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1809 { } 1810 }; 1811 1812 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1813