1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/pm_wakeirq.h> 14 #include <linux/netdevice.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/clk.h> 18 #include <linux/string_choices.h> 19 20 #include "realtek.h" 21 22 #define RTL8201F_IER 0x13 23 24 #define RTL8201F_ISR 0x1e 25 #define RTL8201F_ISR_ANERR BIT(15) 26 #define RTL8201F_ISR_DUPLEX BIT(13) 27 #define RTL8201F_ISR_LINK BIT(11) 28 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 29 RTL8201F_ISR_DUPLEX | \ 30 RTL8201F_ISR_LINK) 31 32 #define RTL821x_INER 0x12 33 #define RTL8211B_INER_INIT 0x6400 34 #define RTL8211E_INER_LINK_STATUS BIT(10) 35 #define RTL8211F_INER_PME BIT(7) 36 #define RTL8211F_INER_LINK_STATUS BIT(4) 37 38 #define RTL821x_INSR 0x13 39 40 #define RTL821x_EXT_PAGE_SELECT 0x1e 41 42 #define RTL821x_PAGE_SELECT 0x1f 43 #define RTL821x_SET_EXT_PAGE 0x07 44 45 /* RTL8211E extension page 44/0x2c */ 46 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 47 #define RTL8211E_LEDCR1 0x1a 48 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 49 #define RTL8211E_LEDCR1_MASK BIT(4) 50 #define RTL8211E_LEDCR1_SHIFT 1 51 52 #define RTL8211E_LEDCR2 0x1c 53 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 54 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 55 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 56 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 57 #define RTL8211E_LEDCR2_SHIFT 4 58 59 /* RTL8211E extension page 164/0xa4 */ 60 #define RTL8211E_RGMII_EXT_PAGE 0xa4 61 #define RTL8211E_RGMII_DELAY 0x1c 62 #define RTL8211E_CTRL_DELAY BIT(13) 63 #define RTL8211E_TX_DELAY BIT(12) 64 #define RTL8211E_RX_DELAY BIT(11) 65 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 66 67 /* RTL8211F PHY configuration */ 68 #define RTL8211F_PHYCR_PAGE 0xa43 69 #define RTL8211F_PHYCR1 0x18 70 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 71 #define RTL8211F_ALDPS_ENABLE BIT(2) 72 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 73 74 #define RTL8211F_PHYCR2 0x19 75 #define RTL8211F_CLKOUT_EN BIT(0) 76 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 77 78 #define RTL8211F_INSR_PAGE 0xa43 79 #define RTL8211F_INSR 0x1d 80 81 /* RTL8211F LED configuration */ 82 #define RTL8211F_LEDCR_PAGE 0xd04 83 #define RTL8211F_LEDCR 0x10 84 #define RTL8211F_LEDCR_MODE BIT(15) 85 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 86 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 87 #define RTL8211F_LEDCR_LINK_100 BIT(1) 88 #define RTL8211F_LEDCR_LINK_10 BIT(0) 89 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 90 #define RTL8211F_LEDCR_SHIFT 5 91 92 /* RTL8211F RGMII configuration */ 93 #define RTL8211F_RGMII_PAGE 0xd08 94 95 #define RTL8211F_TXCR 0x11 96 #define RTL8211F_TX_DELAY BIT(8) 97 98 #define RTL8211F_RXCR 0x15 99 #define RTL8211F_RX_DELAY BIT(3) 100 101 /* RTL8211F WOL settings */ 102 #define RTL8211F_WOL_PAGE 0xd8a 103 #define RTL8211F_WOL_SETTINGS_EVENTS 16 104 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 105 #define RTL8211F_WOL_RST_RMSQ 17 106 #define RTL8211F_WOL_RG_RSTB BIT(15) 107 #define RTL8211F_WOL_RMSQ 0x1fff 108 109 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 110 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 111 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 112 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 113 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 114 115 #define RTL822X_VND1_SERDES_OPTION 0x697a 116 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 117 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 118 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 119 120 #define RTL822X_VND1_SERDES_CTRL3 0x7580 121 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 122 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 124 125 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 126 * is set, they cannot be accessed by C45-over-C22. 127 */ 128 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 129 130 #define RTL8366RB_POWER_SAVE 0x15 131 #define RTL8366RB_POWER_SAVE_ON BIT(12) 132 133 #define RTL9000A_GINMR 0x14 134 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 135 136 #define RTL_VND2_PHYSR 0xa434 137 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 138 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 139 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 140 #define RTL_VND2_PHYSR_MASTER BIT(11) 141 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 142 143 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 144 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 145 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 146 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 147 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 148 #define RTL_MDIO_PMA_SPEED 0xa616 149 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 150 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 151 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 152 153 #define RTL_GENERIC_PHYID 0x001cc800 154 #define RTL_8211FVD_PHYID 0x001cc878 155 #define RTL_8221B 0x001cc840 156 #define RTL_8221B_VB_CG 0x001cc849 157 #define RTL_8221B_VN_CG 0x001cc84a 158 #define RTL_8251B 0x001cc862 159 #define RTL_8261C 0x001cc890 160 161 /* RTL8211E and RTL8211F support up to three LEDs */ 162 #define RTL8211x_LED_COUNT 3 163 164 MODULE_DESCRIPTION("Realtek PHY driver"); 165 MODULE_AUTHOR("Johnson Leung"); 166 MODULE_LICENSE("GPL"); 167 168 struct rtl821x_priv { 169 u16 phycr1; 170 u16 phycr2; 171 bool has_phycr2; 172 struct clk *clk; 173 /* rtl8211f */ 174 u16 iner; 175 }; 176 177 static int rtl821x_read_page(struct phy_device *phydev) 178 { 179 return __phy_read(phydev, RTL821x_PAGE_SELECT); 180 } 181 182 static int rtl821x_write_page(struct phy_device *phydev, int page) 183 { 184 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 185 } 186 187 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 188 u32 regnum) 189 { 190 int oldpage, ret = 0; 191 192 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 193 if (oldpage >= 0) { 194 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 195 if (ret == 0) 196 ret = __phy_read(phydev, regnum); 197 } 198 199 return phy_restore_page(phydev, oldpage, ret); 200 } 201 202 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 203 u32 regnum, u16 mask, u16 set) 204 { 205 int oldpage, ret = 0; 206 207 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 208 if (oldpage >= 0) { 209 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 210 if (ret == 0) 211 ret = __phy_modify(phydev, regnum, mask, set); 212 } 213 214 return phy_restore_page(phydev, oldpage, ret); 215 } 216 217 static int rtl821x_probe(struct phy_device *phydev) 218 { 219 struct device *dev = &phydev->mdio.dev; 220 struct rtl821x_priv *priv; 221 u32 phy_id = phydev->drv->phy_id; 222 int ret; 223 224 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 225 if (!priv) 226 return -ENOMEM; 227 228 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 229 if (IS_ERR(priv->clk)) 230 return dev_err_probe(dev, PTR_ERR(priv->clk), 231 "failed to get phy clock\n"); 232 233 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 234 if (ret < 0) 235 return ret; 236 237 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 238 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 239 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 240 241 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 242 if (priv->has_phycr2) { 243 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 244 if (ret < 0) 245 return ret; 246 247 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 248 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 249 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 250 } 251 252 phydev->priv = priv; 253 254 return 0; 255 } 256 257 static int rtl8211f_probe(struct phy_device *phydev) 258 { 259 struct device *dev = &phydev->mdio.dev; 260 int ret; 261 262 ret = rtl821x_probe(phydev); 263 if (ret < 0) 264 return ret; 265 266 /* Disable all PME events */ 267 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 268 RTL8211F_WOL_SETTINGS_EVENTS, 0); 269 if (ret < 0) 270 return ret; 271 272 /* Mark this PHY as wakeup capable and register the interrupt as a 273 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 274 * and the interrupt is valid. 275 */ 276 if (device_property_read_bool(dev, "wakeup-source") && 277 phy_interrupt_is_valid(phydev)) { 278 device_set_wakeup_capable(dev, true); 279 devm_pm_set_wake_irq(dev, phydev->irq); 280 } 281 282 return ret; 283 } 284 285 static int rtl8201_ack_interrupt(struct phy_device *phydev) 286 { 287 int err; 288 289 err = phy_read(phydev, RTL8201F_ISR); 290 291 return (err < 0) ? err : 0; 292 } 293 294 static int rtl821x_ack_interrupt(struct phy_device *phydev) 295 { 296 int err; 297 298 err = phy_read(phydev, RTL821x_INSR); 299 300 return (err < 0) ? err : 0; 301 } 302 303 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 304 { 305 int err; 306 307 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 308 309 return (err < 0) ? err : 0; 310 } 311 312 static int rtl8201_config_intr(struct phy_device *phydev) 313 { 314 u16 val; 315 int err; 316 317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 318 err = rtl8201_ack_interrupt(phydev); 319 if (err) 320 return err; 321 322 val = BIT(13) | BIT(12) | BIT(11); 323 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 324 } else { 325 val = 0; 326 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 327 if (err) 328 return err; 329 330 err = rtl8201_ack_interrupt(phydev); 331 } 332 333 return err; 334 } 335 336 static int rtl8211b_config_intr(struct phy_device *phydev) 337 { 338 int err; 339 340 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 341 err = rtl821x_ack_interrupt(phydev); 342 if (err) 343 return err; 344 345 err = phy_write(phydev, RTL821x_INER, 346 RTL8211B_INER_INIT); 347 } else { 348 err = phy_write(phydev, RTL821x_INER, 0); 349 if (err) 350 return err; 351 352 err = rtl821x_ack_interrupt(phydev); 353 } 354 355 return err; 356 } 357 358 static int rtl8211e_config_intr(struct phy_device *phydev) 359 { 360 int err; 361 362 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 363 err = rtl821x_ack_interrupt(phydev); 364 if (err) 365 return err; 366 367 err = phy_write(phydev, RTL821x_INER, 368 RTL8211E_INER_LINK_STATUS); 369 } else { 370 err = phy_write(phydev, RTL821x_INER, 0); 371 if (err) 372 return err; 373 374 err = rtl821x_ack_interrupt(phydev); 375 } 376 377 return err; 378 } 379 380 static int rtl8211f_config_intr(struct phy_device *phydev) 381 { 382 struct rtl821x_priv *priv = phydev->priv; 383 u16 val; 384 int err; 385 386 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 387 err = rtl8211f_ack_interrupt(phydev); 388 if (err) 389 return err; 390 391 val = RTL8211F_INER_LINK_STATUS; 392 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 393 if (err == 0) 394 priv->iner = val; 395 } else { 396 priv->iner = val = 0; 397 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 398 if (err) 399 return err; 400 401 err = rtl8211f_ack_interrupt(phydev); 402 } 403 404 return err; 405 } 406 407 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 408 { 409 int irq_status; 410 411 irq_status = phy_read(phydev, RTL8201F_ISR); 412 if (irq_status < 0) { 413 phy_error(phydev); 414 return IRQ_NONE; 415 } 416 417 if (!(irq_status & RTL8201F_ISR_MASK)) 418 return IRQ_NONE; 419 420 phy_trigger_machine(phydev); 421 422 return IRQ_HANDLED; 423 } 424 425 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 426 { 427 int irq_status, irq_enabled; 428 429 irq_status = phy_read(phydev, RTL821x_INSR); 430 if (irq_status < 0) { 431 phy_error(phydev); 432 return IRQ_NONE; 433 } 434 435 irq_enabled = phy_read(phydev, RTL821x_INER); 436 if (irq_enabled < 0) { 437 phy_error(phydev); 438 return IRQ_NONE; 439 } 440 441 if (!(irq_status & irq_enabled)) 442 return IRQ_NONE; 443 444 phy_trigger_machine(phydev); 445 446 return IRQ_HANDLED; 447 } 448 449 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 450 { 451 int irq_status; 452 453 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 454 if (irq_status < 0) { 455 phy_error(phydev); 456 return IRQ_NONE; 457 } 458 459 if (irq_status & RTL8211F_INER_LINK_STATUS) { 460 phy_trigger_machine(phydev); 461 return IRQ_HANDLED; 462 } 463 464 if (irq_status & RTL8211F_INER_PME) { 465 pm_wakeup_event(&phydev->mdio.dev, 0); 466 return IRQ_HANDLED; 467 } 468 469 return IRQ_NONE; 470 } 471 472 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 473 { 474 int wol_events; 475 476 /* If the PHY is not capable of waking the system, then WoL can not 477 * be supported. 478 */ 479 if (!device_can_wakeup(&dev->mdio.dev)) { 480 wol->supported = 0; 481 return; 482 } 483 484 wol->supported = WAKE_MAGIC; 485 486 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 487 if (wol_events < 0) 488 return; 489 490 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 491 wol->wolopts = WAKE_MAGIC; 492 } 493 494 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 495 { 496 const u8 *mac_addr = dev->attached_dev->dev_addr; 497 int oldpage; 498 499 if (!device_can_wakeup(&dev->mdio.dev)) 500 return -EOPNOTSUPP; 501 502 oldpage = phy_save_page(dev); 503 if (oldpage < 0) 504 goto err; 505 506 if (wol->wolopts & WAKE_MAGIC) { 507 /* Store the device address for the magic packet */ 508 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 509 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 510 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 511 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 512 513 /* Enable magic packet matching */ 514 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 515 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 516 /* Set the maximum packet size, and assert WoL reset */ 517 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 518 } else { 519 /* Disable magic packet matching */ 520 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 521 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 522 523 /* Place WoL in reset */ 524 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 525 RTL8211F_WOL_RG_RSTB); 526 } 527 528 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 529 530 err: 531 return phy_restore_page(dev, oldpage, 0); 532 } 533 534 static int rtl8211_config_aneg(struct phy_device *phydev) 535 { 536 int ret; 537 538 ret = genphy_config_aneg(phydev); 539 if (ret < 0) 540 return ret; 541 542 /* Quirk was copied from vendor driver. Unfortunately it includes no 543 * description of the magic numbers. 544 */ 545 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 546 phy_write(phydev, 0x17, 0x2138); 547 phy_write(phydev, 0x0e, 0x0260); 548 } else { 549 phy_write(phydev, 0x17, 0x2108); 550 phy_write(phydev, 0x0e, 0x0000); 551 } 552 553 return 0; 554 } 555 556 static int rtl8211c_config_init(struct phy_device *phydev) 557 { 558 /* RTL8211C has an issue when operating in Gigabit slave mode */ 559 return phy_set_bits(phydev, MII_CTRL1000, 560 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 561 } 562 563 static int rtl8211f_config_init(struct phy_device *phydev) 564 { 565 struct rtl821x_priv *priv = phydev->priv; 566 struct device *dev = &phydev->mdio.dev; 567 u16 val_txdly, val_rxdly; 568 int ret; 569 570 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 571 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 572 priv->phycr1); 573 if (ret < 0) { 574 dev_err(dev, "aldps mode configuration failed: %pe\n", 575 ERR_PTR(ret)); 576 return ret; 577 } 578 579 switch (phydev->interface) { 580 case PHY_INTERFACE_MODE_RGMII: 581 val_txdly = 0; 582 val_rxdly = 0; 583 break; 584 585 case PHY_INTERFACE_MODE_RGMII_RXID: 586 val_txdly = 0; 587 val_rxdly = RTL8211F_RX_DELAY; 588 break; 589 590 case PHY_INTERFACE_MODE_RGMII_TXID: 591 val_txdly = RTL8211F_TX_DELAY; 592 val_rxdly = 0; 593 break; 594 595 case PHY_INTERFACE_MODE_RGMII_ID: 596 val_txdly = RTL8211F_TX_DELAY; 597 val_rxdly = RTL8211F_RX_DELAY; 598 break; 599 600 default: /* the rest of the modes imply leaving delay as is. */ 601 return 0; 602 } 603 604 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 605 RTL8211F_TXCR, RTL8211F_TX_DELAY, 606 val_txdly); 607 if (ret < 0) { 608 dev_err(dev, "Failed to update the TX delay register\n"); 609 return ret; 610 } else if (ret) { 611 dev_dbg(dev, 612 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 613 str_enable_disable(val_txdly)); 614 } else { 615 dev_dbg(dev, 616 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 617 str_enabled_disabled(val_txdly)); 618 } 619 620 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 621 RTL8211F_RXCR, RTL8211F_RX_DELAY, 622 val_rxdly); 623 if (ret < 0) { 624 dev_err(dev, "Failed to update the RX delay register\n"); 625 return ret; 626 } else if (ret) { 627 dev_dbg(dev, 628 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 629 str_enable_disable(val_rxdly)); 630 } else { 631 dev_dbg(dev, 632 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 633 str_enabled_disabled(val_rxdly)); 634 } 635 636 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 637 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 638 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 639 if (ret) 640 return ret; 641 642 if (priv->has_phycr2) { 643 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 644 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 645 priv->phycr2); 646 if (ret < 0) { 647 dev_err(dev, "clkout configuration failed: %pe\n", 648 ERR_PTR(ret)); 649 return ret; 650 } 651 652 return genphy_soft_reset(phydev); 653 } 654 655 return 0; 656 } 657 658 static int rtl821x_suspend(struct phy_device *phydev) 659 { 660 struct rtl821x_priv *priv = phydev->priv; 661 int ret = 0; 662 663 if (!phydev->wol_enabled) { 664 ret = genphy_suspend(phydev); 665 666 if (ret) 667 return ret; 668 669 clk_disable_unprepare(priv->clk); 670 } 671 672 return ret; 673 } 674 675 static int rtl8211f_suspend(struct phy_device *phydev) 676 { 677 u16 wol_rst; 678 int ret; 679 680 ret = rtl821x_suspend(phydev); 681 if (ret < 0) 682 return ret; 683 684 /* If a PME event is enabled, then configure the interrupt for 685 * PME events only, disabling link interrupt. We avoid switching 686 * to PMEB mode as we don't have a status bit for that. 687 */ 688 if (device_may_wakeup(&phydev->mdio.dev)) { 689 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 690 RTL8211F_INER_PME); 691 if (ret < 0) 692 goto err; 693 694 /* Read the INSR to clear any pending interrupt */ 695 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 696 697 /* Reset the WoL to ensure that an event is picked up. 698 * Unless we do this, even if we receive another packet, 699 * we may not have a PME interrupt raised. 700 */ 701 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 702 RTL8211F_WOL_RST_RMSQ); 703 if (ret < 0) 704 goto err; 705 706 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 707 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 708 RTL8211F_WOL_RST_RMSQ, wol_rst); 709 if (ret < 0) 710 goto err; 711 712 wol_rst |= RTL8211F_WOL_RG_RSTB; 713 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 714 RTL8211F_WOL_RST_RMSQ, wol_rst); 715 } 716 717 err: 718 return ret; 719 } 720 721 static int rtl821x_resume(struct phy_device *phydev) 722 { 723 struct rtl821x_priv *priv = phydev->priv; 724 int ret; 725 726 if (!phydev->wol_enabled) 727 clk_prepare_enable(priv->clk); 728 729 ret = genphy_resume(phydev); 730 if (ret < 0) 731 return ret; 732 733 msleep(20); 734 735 return 0; 736 } 737 738 static int rtl8211f_resume(struct phy_device *phydev) 739 { 740 struct rtl821x_priv *priv = phydev->priv; 741 int ret; 742 743 ret = rtl821x_resume(phydev); 744 if (ret < 0) 745 return ret; 746 747 /* If the device was programmed for a PME event, restore the interrupt 748 * enable so phylib can receive link state interrupts. 749 */ 750 if (device_may_wakeup(&phydev->mdio.dev)) 751 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 752 753 return ret; 754 } 755 756 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 757 unsigned long rules) 758 { 759 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 760 BIT(TRIGGER_NETDEV_LINK_100) | 761 BIT(TRIGGER_NETDEV_LINK_1000) | 762 BIT(TRIGGER_NETDEV_RX) | 763 BIT(TRIGGER_NETDEV_TX); 764 765 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 766 * - Link: Configurable subset of 10/100/1000 link rates 767 * - Active: Blink on activity, RX or TX is not differentiated 768 * The Active option has two modes, A and B: 769 * - A: Link and Active indication at configurable, but matching, 770 * subset of 10/100/1000 link rates 771 * - B: Link indication at configurable subset of 10/100/1000 link 772 * rates and Active indication always at all three 10+100+1000 773 * link rates. 774 * This code currently uses mode B only. 775 * 776 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 777 */ 778 779 if (index >= RTL8211x_LED_COUNT) 780 return -EINVAL; 781 782 /* Filter out any other unsupported triggers. */ 783 if (rules & ~mask) 784 return -EOPNOTSUPP; 785 786 /* RX and TX are not differentiated, either both are set or not set. */ 787 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 788 return -EOPNOTSUPP; 789 790 return 0; 791 } 792 793 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 794 unsigned long *rules) 795 { 796 int val; 797 798 if (index >= RTL8211x_LED_COUNT) 799 return -EINVAL; 800 801 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 802 if (val < 0) 803 return val; 804 805 val >>= RTL8211F_LEDCR_SHIFT * index; 806 val &= RTL8211F_LEDCR_MASK; 807 808 if (val & RTL8211F_LEDCR_LINK_10) 809 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 810 811 if (val & RTL8211F_LEDCR_LINK_100) 812 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 813 814 if (val & RTL8211F_LEDCR_LINK_1000) 815 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 816 817 if (val & RTL8211F_LEDCR_ACT_TXRX) { 818 __set_bit(TRIGGER_NETDEV_RX, rules); 819 __set_bit(TRIGGER_NETDEV_TX, rules); 820 } 821 822 return 0; 823 } 824 825 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 826 unsigned long rules) 827 { 828 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 829 u16 reg = 0; 830 831 if (index >= RTL8211x_LED_COUNT) 832 return -EINVAL; 833 834 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 835 reg |= RTL8211F_LEDCR_LINK_10; 836 837 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 838 reg |= RTL8211F_LEDCR_LINK_100; 839 840 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 841 reg |= RTL8211F_LEDCR_LINK_1000; 842 843 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 844 test_bit(TRIGGER_NETDEV_TX, &rules)) { 845 reg |= RTL8211F_LEDCR_ACT_TXRX; 846 } 847 848 reg <<= RTL8211F_LEDCR_SHIFT * index; 849 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 850 851 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 852 } 853 854 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 855 unsigned long *rules) 856 { 857 int ret; 858 u16 cr1, cr2; 859 860 if (index >= RTL8211x_LED_COUNT) 861 return -EINVAL; 862 863 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 864 RTL8211E_LEDCR1); 865 if (ret < 0) 866 return ret; 867 868 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 869 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 870 __set_bit(TRIGGER_NETDEV_RX, rules); 871 __set_bit(TRIGGER_NETDEV_TX, rules); 872 } 873 874 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 875 RTL8211E_LEDCR2); 876 if (ret < 0) 877 return ret; 878 879 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 880 if (cr2 & RTL8211E_LEDCR2_LINK_10) 881 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 882 883 if (cr2 & RTL8211E_LEDCR2_LINK_100) 884 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 885 886 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 887 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 888 889 return ret; 890 } 891 892 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 893 unsigned long rules) 894 { 895 const u16 cr1mask = 896 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 897 const u16 cr2mask = 898 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 899 u16 cr1 = 0, cr2 = 0; 900 int ret; 901 902 if (index >= RTL8211x_LED_COUNT) 903 return -EINVAL; 904 905 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 906 test_bit(TRIGGER_NETDEV_TX, &rules)) { 907 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 908 } 909 910 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 911 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 912 RTL8211E_LEDCR1, cr1mask, cr1); 913 if (ret < 0) 914 return ret; 915 916 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 917 cr2 |= RTL8211E_LEDCR2_LINK_10; 918 919 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 920 cr2 |= RTL8211E_LEDCR2_LINK_100; 921 922 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 923 cr2 |= RTL8211E_LEDCR2_LINK_1000; 924 925 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 926 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 927 RTL8211E_LEDCR2, cr2mask, cr2); 928 929 return ret; 930 } 931 932 static int rtl8211e_config_init(struct phy_device *phydev) 933 { 934 u16 val; 935 936 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 937 switch (phydev->interface) { 938 case PHY_INTERFACE_MODE_RGMII: 939 val = RTL8211E_CTRL_DELAY | 0; 940 break; 941 case PHY_INTERFACE_MODE_RGMII_ID: 942 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 943 break; 944 case PHY_INTERFACE_MODE_RGMII_RXID: 945 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 946 break; 947 case PHY_INTERFACE_MODE_RGMII_TXID: 948 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 949 break; 950 default: /* the rest of the modes imply leaving delays as is. */ 951 return 0; 952 } 953 954 /* According to a sample driver there is a 0x1c config register on the 955 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 956 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 957 * The configuration register definition: 958 * 14 = reserved 959 * 13 = Force Tx RX Delay controlled by bit12 bit11, 960 * 12 = RX Delay, 11 = TX Delay 961 * 10:0 = Test && debug settings reserved by realtek 962 */ 963 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 964 RTL8211E_RGMII_DELAY, 965 RTL8211E_DELAY_MASK, val); 966 } 967 968 static int rtl8211b_suspend(struct phy_device *phydev) 969 { 970 phy_write(phydev, MII_MMD_DATA, BIT(9)); 971 972 return genphy_suspend(phydev); 973 } 974 975 static int rtl8211b_resume(struct phy_device *phydev) 976 { 977 phy_write(phydev, MII_MMD_DATA, 0); 978 979 return genphy_resume(phydev); 980 } 981 982 static int rtl8366rb_config_init(struct phy_device *phydev) 983 { 984 int ret; 985 986 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 987 RTL8366RB_POWER_SAVE_ON); 988 if (ret) { 989 dev_err(&phydev->mdio.dev, 990 "error enabling power management\n"); 991 } 992 993 return ret; 994 } 995 996 /* get actual speed to cover the downshift case */ 997 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 998 { 999 /* bit 3 1000 * 0: Half Duplex 1001 * 1: Full Duplex 1002 */ 1003 if (val & RTL_VND2_PHYSR_DUPLEX) 1004 phydev->duplex = DUPLEX_FULL; 1005 else 1006 phydev->duplex = DUPLEX_HALF; 1007 1008 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1009 case 0x0000: 1010 phydev->speed = SPEED_10; 1011 break; 1012 case 0x0010: 1013 phydev->speed = SPEED_100; 1014 break; 1015 case 0x0020: 1016 phydev->speed = SPEED_1000; 1017 break; 1018 case 0x0200: 1019 phydev->speed = SPEED_10000; 1020 break; 1021 case 0x0210: 1022 phydev->speed = SPEED_2500; 1023 break; 1024 case 0x0220: 1025 phydev->speed = SPEED_5000; 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 /* bit 11 1032 * 0: Slave Mode 1033 * 1: Master Mode 1034 */ 1035 if (phydev->speed >= 1000) { 1036 if (val & RTL_VND2_PHYSR_MASTER) 1037 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1038 else 1039 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1040 } else { 1041 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1042 } 1043 } 1044 1045 static int rtlgen_read_status(struct phy_device *phydev) 1046 { 1047 int ret, val; 1048 1049 ret = genphy_read_status(phydev); 1050 if (ret < 0) 1051 return ret; 1052 1053 if (!phydev->link) 1054 return 0; 1055 1056 val = phy_read_paged(phydev, 0xa43, 0x12); 1057 if (val < 0) 1058 return val; 1059 1060 rtlgen_decode_physr(phydev, val); 1061 1062 return 0; 1063 } 1064 1065 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1066 { 1067 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1068 } 1069 1070 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1071 { 1072 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1073 val); 1074 } 1075 1076 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1077 { 1078 int ret; 1079 1080 if (devnum == MDIO_MMD_VEND2) 1081 ret = rtlgen_read_vend2(phydev, regnum); 1082 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1083 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1084 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1085 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1086 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1087 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1088 else 1089 ret = -EOPNOTSUPP; 1090 1091 return ret; 1092 } 1093 1094 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1095 u16 val) 1096 { 1097 int ret; 1098 1099 if (devnum == MDIO_MMD_VEND2) 1100 ret = rtlgen_write_vend2(phydev, regnum, val); 1101 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1102 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1103 else 1104 ret = -EOPNOTSUPP; 1105 1106 return ret; 1107 } 1108 1109 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1110 { 1111 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1112 1113 if (ret != -EOPNOTSUPP) 1114 return ret; 1115 1116 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1117 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1118 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1119 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1120 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1121 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1122 1123 return ret; 1124 } 1125 1126 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1127 u16 val) 1128 { 1129 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1130 1131 if (ret != -EOPNOTSUPP) 1132 return ret; 1133 1134 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1135 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1136 1137 return ret; 1138 } 1139 1140 static int rtl822x_probe(struct phy_device *phydev) 1141 { 1142 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1143 phydev->phy_id != RTL_GENERIC_PHYID) 1144 return rtl822x_hwmon_init(phydev); 1145 1146 return 0; 1147 } 1148 1149 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1150 { 1151 bool has_2500, has_sgmii; 1152 u16 mode; 1153 int ret; 1154 1155 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1156 phydev->host_interfaces) || 1157 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1158 1159 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1160 phydev->host_interfaces) || 1161 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1162 1163 /* fill in possible interfaces */ 1164 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1165 has_2500); 1166 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1167 has_sgmii); 1168 1169 if (!has_2500 && !has_sgmii) 1170 return 0; 1171 1172 /* determine SerDes option mode */ 1173 if (has_2500 && !has_sgmii) { 1174 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1175 phydev->rate_matching = RATE_MATCH_PAUSE; 1176 } else { 1177 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1178 phydev->rate_matching = RATE_MATCH_NONE; 1179 } 1180 1181 /* the following sequence with magic numbers sets up the SerDes 1182 * option mode 1183 */ 1184 1185 if (!gen1) { 1186 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1187 if (ret < 0) 1188 return ret; 1189 } 1190 1191 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1192 RTL822X_VND1_SERDES_OPTION, 1193 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1194 mode); 1195 if (gen1 || ret < 0) 1196 return ret; 1197 1198 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1199 if (ret < 0) 1200 return ret; 1201 1202 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1203 if (ret < 0) 1204 return ret; 1205 1206 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1207 } 1208 1209 static int rtl822x_config_init(struct phy_device *phydev) 1210 { 1211 return rtl822x_set_serdes_option_mode(phydev, true); 1212 } 1213 1214 static int rtl822xb_config_init(struct phy_device *phydev) 1215 { 1216 return rtl822x_set_serdes_option_mode(phydev, false); 1217 } 1218 1219 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1220 phy_interface_t iface) 1221 { 1222 int val; 1223 1224 /* Only rate matching at 2500base-x */ 1225 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1226 return RATE_MATCH_NONE; 1227 1228 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1229 if (val < 0) 1230 return val; 1231 1232 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1233 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1234 return RATE_MATCH_PAUSE; 1235 1236 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1237 return RATE_MATCH_NONE; 1238 } 1239 1240 static int rtl822x_get_features(struct phy_device *phydev) 1241 { 1242 int val; 1243 1244 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1245 if (val < 0) 1246 return val; 1247 1248 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1249 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1250 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1251 phydev->supported, val & MDIO_PMA_SPEED_5G); 1252 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1253 phydev->supported, val & MDIO_SPEED_10G); 1254 1255 return genphy_read_abilities(phydev); 1256 } 1257 1258 static int rtl822x_config_aneg(struct phy_device *phydev) 1259 { 1260 int ret = 0; 1261 1262 if (phydev->autoneg == AUTONEG_ENABLE) { 1263 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1264 1265 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1266 RTL_MDIO_AN_10GBT_CTRL, 1267 MDIO_AN_10GBT_CTRL_ADV2_5G | 1268 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1269 if (ret < 0) 1270 return ret; 1271 } 1272 1273 return __genphy_config_aneg(phydev, ret); 1274 } 1275 1276 static void rtl822xb_update_interface(struct phy_device *phydev) 1277 { 1278 int val; 1279 1280 if (!phydev->link) 1281 return; 1282 1283 /* Change interface according to serdes mode */ 1284 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1285 if (val < 0) 1286 return; 1287 1288 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1289 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1290 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1291 break; 1292 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1293 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1294 break; 1295 } 1296 } 1297 1298 static int rtl822x_read_status(struct phy_device *phydev) 1299 { 1300 int lpadv, ret; 1301 1302 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1303 1304 ret = rtlgen_read_status(phydev); 1305 if (ret < 0) 1306 return ret; 1307 1308 if (phydev->autoneg == AUTONEG_DISABLE || 1309 !phydev->autoneg_complete) 1310 return 0; 1311 1312 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1313 if (lpadv < 0) 1314 return lpadv; 1315 1316 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1317 1318 return 0; 1319 } 1320 1321 static int rtl822xb_read_status(struct phy_device *phydev) 1322 { 1323 int ret; 1324 1325 ret = rtl822x_read_status(phydev); 1326 if (ret < 0) 1327 return ret; 1328 1329 rtl822xb_update_interface(phydev); 1330 1331 return 0; 1332 } 1333 1334 static int rtl822x_c45_get_features(struct phy_device *phydev) 1335 { 1336 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1337 phydev->supported); 1338 1339 return genphy_c45_pma_read_abilities(phydev); 1340 } 1341 1342 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1343 { 1344 bool changed = false; 1345 int ret, val; 1346 1347 if (phydev->autoneg == AUTONEG_DISABLE) 1348 return genphy_c45_pma_setup_forced(phydev); 1349 1350 ret = genphy_c45_an_config_aneg(phydev); 1351 if (ret < 0) 1352 return ret; 1353 if (ret > 0) 1354 changed = true; 1355 1356 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1357 1358 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1359 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1360 RTL822X_VND2_C22_REG(MII_CTRL1000), 1361 ADVERTISE_1000FULL, val); 1362 if (ret < 0) 1363 return ret; 1364 if (ret > 0) 1365 changed = true; 1366 1367 return genphy_c45_check_and_restart_aneg(phydev, changed); 1368 } 1369 1370 static int rtl822x_c45_read_status(struct phy_device *phydev) 1371 { 1372 int ret, val; 1373 1374 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1375 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1376 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1377 RTL822X_VND2_C22_REG(MII_STAT1000)); 1378 if (val < 0) 1379 return val; 1380 } else { 1381 val = 0; 1382 } 1383 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1384 1385 ret = genphy_c45_read_status(phydev); 1386 if (ret < 0) 1387 return ret; 1388 1389 if (!phydev->link) { 1390 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1391 return 0; 1392 } 1393 1394 /* Read actual speed from vendor register. */ 1395 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1396 if (val < 0) 1397 return val; 1398 1399 rtlgen_decode_physr(phydev, val); 1400 1401 return 0; 1402 } 1403 1404 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1405 { 1406 int ret, val; 1407 1408 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1409 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1410 if (ret < 0) 1411 return ret; 1412 1413 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1414 MDIO_CTRL1, val, 1415 !(val & MDIO_CTRL1_RESET), 1416 5000, 100000, true); 1417 } 1418 1419 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1420 { 1421 int ret; 1422 1423 ret = rtl822x_c45_read_status(phydev); 1424 if (ret < 0) 1425 return ret; 1426 1427 rtl822xb_update_interface(phydev); 1428 1429 return 0; 1430 } 1431 1432 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1433 { 1434 int val; 1435 1436 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1437 val = phy_read(phydev, 0x13); 1438 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1439 1440 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1441 } 1442 1443 /* On internal PHY's MMD reads over C22 always return 0. 1444 * Check a MMD register which is known to be non-zero. 1445 */ 1446 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1447 { 1448 int val; 1449 1450 phy_lock_mdio_bus(phydev); 1451 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1452 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1453 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1454 val = __phy_read(phydev, MII_MMD_DATA); 1455 phy_unlock_mdio_bus(phydev); 1456 1457 return val > 0; 1458 } 1459 1460 static int rtlgen_match_phy_device(struct phy_device *phydev, 1461 const struct phy_driver *phydrv) 1462 { 1463 return phydev->phy_id == RTL_GENERIC_PHYID && 1464 !rtlgen_supports_2_5gbps(phydev); 1465 } 1466 1467 static int rtl8226_match_phy_device(struct phy_device *phydev, 1468 const struct phy_driver *phydrv) 1469 { 1470 return phydev->phy_id == RTL_GENERIC_PHYID && 1471 rtlgen_supports_2_5gbps(phydev) && 1472 rtlgen_supports_mmd(phydev); 1473 } 1474 1475 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1476 bool is_c45) 1477 { 1478 if (phydev->is_c45) 1479 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1480 else 1481 return !is_c45 && (id == phydev->phy_id); 1482 } 1483 1484 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1485 const struct phy_driver *phydrv) 1486 { 1487 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1488 } 1489 1490 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1491 const struct phy_driver *phydrv) 1492 { 1493 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1494 } 1495 1496 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1497 const struct phy_driver *phydrv) 1498 { 1499 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1500 } 1501 1502 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev, 1503 const struct phy_driver *phydrv) 1504 { 1505 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1506 } 1507 1508 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev, 1509 const struct phy_driver *phydrv) 1510 { 1511 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1512 } 1513 1514 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1515 const struct phy_driver *phydrv) 1516 { 1517 if (phydev->is_c45) 1518 return false; 1519 1520 switch (phydev->phy_id) { 1521 case RTL_GENERIC_PHYID: 1522 case RTL_8221B: 1523 case RTL_8251B: 1524 case RTL_8261C: 1525 case 0x001cc841: 1526 break; 1527 default: 1528 return false; 1529 } 1530 1531 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1532 } 1533 1534 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1535 const struct phy_driver *phydrv) 1536 { 1537 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1538 } 1539 1540 static int rtlgen_resume(struct phy_device *phydev) 1541 { 1542 int ret = genphy_resume(phydev); 1543 1544 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1545 msleep(20); 1546 1547 return ret; 1548 } 1549 1550 static int rtlgen_c45_resume(struct phy_device *phydev) 1551 { 1552 int ret = genphy_c45_pma_resume(phydev); 1553 1554 msleep(20); 1555 1556 return ret; 1557 } 1558 1559 static int rtl9000a_config_init(struct phy_device *phydev) 1560 { 1561 phydev->autoneg = AUTONEG_DISABLE; 1562 phydev->speed = SPEED_100; 1563 phydev->duplex = DUPLEX_FULL; 1564 1565 return 0; 1566 } 1567 1568 static int rtl9000a_config_aneg(struct phy_device *phydev) 1569 { 1570 int ret; 1571 u16 ctl = 0; 1572 1573 switch (phydev->master_slave_set) { 1574 case MASTER_SLAVE_CFG_MASTER_FORCE: 1575 ctl |= CTL1000_AS_MASTER; 1576 break; 1577 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1578 break; 1579 case MASTER_SLAVE_CFG_UNKNOWN: 1580 case MASTER_SLAVE_CFG_UNSUPPORTED: 1581 return 0; 1582 default: 1583 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1584 return -EOPNOTSUPP; 1585 } 1586 1587 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1588 if (ret == 1) 1589 ret = genphy_soft_reset(phydev); 1590 1591 return ret; 1592 } 1593 1594 static int rtl9000a_read_status(struct phy_device *phydev) 1595 { 1596 int ret; 1597 1598 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1599 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1600 1601 ret = genphy_update_link(phydev); 1602 if (ret) 1603 return ret; 1604 1605 ret = phy_read(phydev, MII_CTRL1000); 1606 if (ret < 0) 1607 return ret; 1608 if (ret & CTL1000_AS_MASTER) 1609 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1610 else 1611 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1612 1613 ret = phy_read(phydev, MII_STAT1000); 1614 if (ret < 0) 1615 return ret; 1616 if (ret & LPA_1000MSRES) 1617 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1618 else 1619 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1620 1621 return 0; 1622 } 1623 1624 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1625 { 1626 int err; 1627 1628 err = phy_read(phydev, RTL8211F_INSR); 1629 1630 return (err < 0) ? err : 0; 1631 } 1632 1633 static int rtl9000a_config_intr(struct phy_device *phydev) 1634 { 1635 u16 val; 1636 int err; 1637 1638 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1639 err = rtl9000a_ack_interrupt(phydev); 1640 if (err) 1641 return err; 1642 1643 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1644 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1645 } else { 1646 val = ~0; 1647 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1648 if (err) 1649 return err; 1650 1651 err = rtl9000a_ack_interrupt(phydev); 1652 } 1653 1654 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1655 } 1656 1657 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1658 { 1659 int irq_status; 1660 1661 irq_status = phy_read(phydev, RTL8211F_INSR); 1662 if (irq_status < 0) { 1663 phy_error(phydev); 1664 return IRQ_NONE; 1665 } 1666 1667 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1668 return IRQ_NONE; 1669 1670 phy_trigger_machine(phydev); 1671 1672 return IRQ_HANDLED; 1673 } 1674 1675 static struct phy_driver realtek_drvs[] = { 1676 { 1677 PHY_ID_MATCH_EXACT(0x00008201), 1678 .name = "RTL8201CP Ethernet", 1679 .read_page = rtl821x_read_page, 1680 .write_page = rtl821x_write_page, 1681 }, { 1682 PHY_ID_MATCH_EXACT(0x001cc816), 1683 .name = "RTL8201F Fast Ethernet", 1684 .config_intr = &rtl8201_config_intr, 1685 .handle_interrupt = rtl8201_handle_interrupt, 1686 .suspend = genphy_suspend, 1687 .resume = genphy_resume, 1688 .read_page = rtl821x_read_page, 1689 .write_page = rtl821x_write_page, 1690 }, { 1691 PHY_ID_MATCH_MODEL(0x001cc880), 1692 .name = "RTL8208 Fast Ethernet", 1693 .read_mmd = genphy_read_mmd_unsupported, 1694 .write_mmd = genphy_write_mmd_unsupported, 1695 .suspend = genphy_suspend, 1696 .resume = genphy_resume, 1697 .read_page = rtl821x_read_page, 1698 .write_page = rtl821x_write_page, 1699 }, { 1700 PHY_ID_MATCH_EXACT(0x001cc910), 1701 .name = "RTL8211 Gigabit Ethernet", 1702 .config_aneg = rtl8211_config_aneg, 1703 .read_mmd = &genphy_read_mmd_unsupported, 1704 .write_mmd = &genphy_write_mmd_unsupported, 1705 .read_page = rtl821x_read_page, 1706 .write_page = rtl821x_write_page, 1707 }, { 1708 PHY_ID_MATCH_EXACT(0x001cc912), 1709 .name = "RTL8211B Gigabit Ethernet", 1710 .config_intr = &rtl8211b_config_intr, 1711 .handle_interrupt = rtl821x_handle_interrupt, 1712 .read_mmd = &genphy_read_mmd_unsupported, 1713 .write_mmd = &genphy_write_mmd_unsupported, 1714 .suspend = rtl8211b_suspend, 1715 .resume = rtl8211b_resume, 1716 .read_page = rtl821x_read_page, 1717 .write_page = rtl821x_write_page, 1718 }, { 1719 PHY_ID_MATCH_EXACT(0x001cc913), 1720 .name = "RTL8211C Gigabit Ethernet", 1721 .config_init = rtl8211c_config_init, 1722 .read_mmd = &genphy_read_mmd_unsupported, 1723 .write_mmd = &genphy_write_mmd_unsupported, 1724 .read_page = rtl821x_read_page, 1725 .write_page = rtl821x_write_page, 1726 }, { 1727 PHY_ID_MATCH_EXACT(0x001cc914), 1728 .name = "RTL8211DN Gigabit Ethernet", 1729 .config_intr = rtl8211e_config_intr, 1730 .handle_interrupt = rtl821x_handle_interrupt, 1731 .suspend = genphy_suspend, 1732 .resume = genphy_resume, 1733 .read_page = rtl821x_read_page, 1734 .write_page = rtl821x_write_page, 1735 }, { 1736 PHY_ID_MATCH_EXACT(0x001cc915), 1737 .name = "RTL8211E Gigabit Ethernet", 1738 .config_init = &rtl8211e_config_init, 1739 .config_intr = &rtl8211e_config_intr, 1740 .handle_interrupt = rtl821x_handle_interrupt, 1741 .suspend = genphy_suspend, 1742 .resume = genphy_resume, 1743 .read_page = rtl821x_read_page, 1744 .write_page = rtl821x_write_page, 1745 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1746 .led_hw_control_get = rtl8211e_led_hw_control_get, 1747 .led_hw_control_set = rtl8211e_led_hw_control_set, 1748 }, { 1749 PHY_ID_MATCH_EXACT(0x001cc916), 1750 .name = "RTL8211F Gigabit Ethernet", 1751 .probe = rtl8211f_probe, 1752 .config_init = &rtl8211f_config_init, 1753 .read_status = rtlgen_read_status, 1754 .config_intr = &rtl8211f_config_intr, 1755 .handle_interrupt = rtl8211f_handle_interrupt, 1756 .set_wol = rtl8211f_set_wol, 1757 .get_wol = rtl8211f_get_wol, 1758 .suspend = rtl8211f_suspend, 1759 .resume = rtl8211f_resume, 1760 .read_page = rtl821x_read_page, 1761 .write_page = rtl821x_write_page, 1762 .flags = PHY_ALWAYS_CALL_SUSPEND, 1763 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1764 .led_hw_control_get = rtl8211f_led_hw_control_get, 1765 .led_hw_control_set = rtl8211f_led_hw_control_set, 1766 }, { 1767 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1768 .name = "RTL8211F-VD Gigabit Ethernet", 1769 .probe = rtl821x_probe, 1770 .config_init = &rtl8211f_config_init, 1771 .read_status = rtlgen_read_status, 1772 .config_intr = &rtl8211f_config_intr, 1773 .handle_interrupt = rtl8211f_handle_interrupt, 1774 .suspend = rtl821x_suspend, 1775 .resume = rtl821x_resume, 1776 .read_page = rtl821x_read_page, 1777 .write_page = rtl821x_write_page, 1778 .flags = PHY_ALWAYS_CALL_SUSPEND, 1779 }, { 1780 .name = "Generic FE-GE Realtek PHY", 1781 .match_phy_device = rtlgen_match_phy_device, 1782 .read_status = rtlgen_read_status, 1783 .suspend = genphy_suspend, 1784 .resume = rtlgen_resume, 1785 .read_page = rtl821x_read_page, 1786 .write_page = rtl821x_write_page, 1787 .read_mmd = rtlgen_read_mmd, 1788 .write_mmd = rtlgen_write_mmd, 1789 }, { 1790 .name = "RTL8226 2.5Gbps PHY", 1791 .match_phy_device = rtl8226_match_phy_device, 1792 .get_features = rtl822x_get_features, 1793 .config_aneg = rtl822x_config_aneg, 1794 .read_status = rtl822x_read_status, 1795 .suspend = genphy_suspend, 1796 .resume = rtlgen_resume, 1797 .read_page = rtl821x_read_page, 1798 .write_page = rtl821x_write_page, 1799 }, { 1800 .match_phy_device = rtl8221b_match_phy_device, 1801 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1802 .get_features = rtl822x_get_features, 1803 .config_aneg = rtl822x_config_aneg, 1804 .config_init = rtl822xb_config_init, 1805 .get_rate_matching = rtl822xb_get_rate_matching, 1806 .read_status = rtl822xb_read_status, 1807 .suspend = genphy_suspend, 1808 .resume = rtlgen_resume, 1809 .read_page = rtl821x_read_page, 1810 .write_page = rtl821x_write_page, 1811 }, { 1812 PHY_ID_MATCH_EXACT(0x001cc838), 1813 .name = "RTL8226-CG 2.5Gbps PHY", 1814 .soft_reset = rtl822x_c45_soft_reset, 1815 .get_features = rtl822x_c45_get_features, 1816 .config_aneg = rtl822x_c45_config_aneg, 1817 .config_init = rtl822x_config_init, 1818 .read_status = rtl822xb_c45_read_status, 1819 .suspend = genphy_c45_pma_suspend, 1820 .resume = rtlgen_c45_resume, 1821 }, { 1822 PHY_ID_MATCH_EXACT(0x001cc848), 1823 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1824 .get_features = rtl822x_get_features, 1825 .config_aneg = rtl822x_config_aneg, 1826 .config_init = rtl822xb_config_init, 1827 .get_rate_matching = rtl822xb_get_rate_matching, 1828 .read_status = rtl822xb_read_status, 1829 .suspend = genphy_suspend, 1830 .resume = rtlgen_resume, 1831 .read_page = rtl821x_read_page, 1832 .write_page = rtl821x_write_page, 1833 }, { 1834 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1835 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1836 .probe = rtl822x_probe, 1837 .get_features = rtl822x_get_features, 1838 .config_aneg = rtl822x_config_aneg, 1839 .config_init = rtl822xb_config_init, 1840 .get_rate_matching = rtl822xb_get_rate_matching, 1841 .read_status = rtl822xb_read_status, 1842 .suspend = genphy_suspend, 1843 .resume = rtlgen_resume, 1844 .read_page = rtl821x_read_page, 1845 .write_page = rtl821x_write_page, 1846 }, { 1847 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1848 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1849 .probe = rtl822x_probe, 1850 .config_init = rtl822xb_config_init, 1851 .get_rate_matching = rtl822xb_get_rate_matching, 1852 .get_features = rtl822x_c45_get_features, 1853 .config_aneg = rtl822x_c45_config_aneg, 1854 .read_status = rtl822xb_c45_read_status, 1855 .suspend = genphy_c45_pma_suspend, 1856 .resume = rtlgen_c45_resume, 1857 }, { 1858 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1859 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1860 .probe = rtl822x_probe, 1861 .get_features = rtl822x_get_features, 1862 .config_aneg = rtl822x_config_aneg, 1863 .config_init = rtl822xb_config_init, 1864 .get_rate_matching = rtl822xb_get_rate_matching, 1865 .read_status = rtl822xb_read_status, 1866 .suspend = genphy_suspend, 1867 .resume = rtlgen_resume, 1868 .read_page = rtl821x_read_page, 1869 .write_page = rtl821x_write_page, 1870 }, { 1871 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1872 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1873 .probe = rtl822x_probe, 1874 .config_init = rtl822xb_config_init, 1875 .get_rate_matching = rtl822xb_get_rate_matching, 1876 .get_features = rtl822x_c45_get_features, 1877 .config_aneg = rtl822x_c45_config_aneg, 1878 .read_status = rtl822xb_c45_read_status, 1879 .suspend = genphy_c45_pma_suspend, 1880 .resume = rtlgen_c45_resume, 1881 }, { 1882 .match_phy_device = rtl8251b_c45_match_phy_device, 1883 .name = "RTL8251B 5Gbps PHY", 1884 .probe = rtl822x_probe, 1885 .get_features = rtl822x_get_features, 1886 .config_aneg = rtl822x_config_aneg, 1887 .read_status = rtl822x_read_status, 1888 .suspend = genphy_suspend, 1889 .resume = rtlgen_resume, 1890 .read_page = rtl821x_read_page, 1891 .write_page = rtl821x_write_page, 1892 }, { 1893 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1894 .name = "Realtek Internal NBASE-T PHY", 1895 .flags = PHY_IS_INTERNAL, 1896 .probe = rtl822x_probe, 1897 .get_features = rtl822x_get_features, 1898 .config_aneg = rtl822x_config_aneg, 1899 .read_status = rtl822x_read_status, 1900 .suspend = genphy_suspend, 1901 .resume = rtlgen_resume, 1902 .read_page = rtl821x_read_page, 1903 .write_page = rtl821x_write_page, 1904 .read_mmd = rtl822x_read_mmd, 1905 .write_mmd = rtl822x_write_mmd, 1906 }, { 1907 PHY_ID_MATCH_EXACT(0x001ccad0), 1908 .name = "RTL8224 2.5Gbps PHY", 1909 .get_features = rtl822x_c45_get_features, 1910 .config_aneg = rtl822x_c45_config_aneg, 1911 .read_status = rtl822x_c45_read_status, 1912 .suspend = genphy_c45_pma_suspend, 1913 .resume = rtlgen_c45_resume, 1914 }, { 1915 PHY_ID_MATCH_EXACT(0x001cc961), 1916 .name = "RTL8366RB Gigabit Ethernet", 1917 .config_init = &rtl8366rb_config_init, 1918 /* These interrupts are handled by the irq controller 1919 * embedded inside the RTL8366RB, they get unmasked when the 1920 * irq is requested and ACKed by reading the status register, 1921 * which is done by the irqchip code. 1922 */ 1923 .config_intr = genphy_no_config_intr, 1924 .handle_interrupt = genphy_handle_interrupt_no_ack, 1925 .suspend = genphy_suspend, 1926 .resume = genphy_resume, 1927 }, { 1928 PHY_ID_MATCH_EXACT(0x001ccb00), 1929 .name = "RTL9000AA_RTL9000AN Ethernet", 1930 .features = PHY_BASIC_T1_FEATURES, 1931 .config_init = rtl9000a_config_init, 1932 .config_aneg = rtl9000a_config_aneg, 1933 .read_status = rtl9000a_read_status, 1934 .config_intr = rtl9000a_config_intr, 1935 .handle_interrupt = rtl9000a_handle_interrupt, 1936 .suspend = genphy_suspend, 1937 .resume = genphy_resume, 1938 .read_page = rtl821x_read_page, 1939 .write_page = rtl821x_write_page, 1940 }, { 1941 PHY_ID_MATCH_EXACT(0x001cc942), 1942 .name = "RTL8365MB-VC Gigabit Ethernet", 1943 /* Interrupt handling analogous to RTL8366RB */ 1944 .config_intr = genphy_no_config_intr, 1945 .handle_interrupt = genphy_handle_interrupt_no_ack, 1946 .suspend = genphy_suspend, 1947 .resume = genphy_resume, 1948 }, { 1949 PHY_ID_MATCH_EXACT(0x001cc960), 1950 .name = "RTL8366S Gigabit Ethernet", 1951 .suspend = genphy_suspend, 1952 .resume = genphy_resume, 1953 .read_mmd = genphy_read_mmd_unsupported, 1954 .write_mmd = genphy_write_mmd_unsupported, 1955 }, 1956 }; 1957 1958 module_phy_driver(realtek_drvs); 1959 1960 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1961 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1962 { } 1963 }; 1964 1965 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1966