1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 21 #include "realtek.h" 22 23 #define RTL8201F_IER 0x13 24 25 #define RTL8201F_ISR 0x1e 26 #define RTL8201F_ISR_ANERR BIT(15) 27 #define RTL8201F_ISR_DUPLEX BIT(13) 28 #define RTL8201F_ISR_LINK BIT(11) 29 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 30 RTL8201F_ISR_DUPLEX | \ 31 RTL8201F_ISR_LINK) 32 33 #define RTL821x_INER 0x12 34 #define RTL8211B_INER_INIT 0x6400 35 #define RTL8211E_INER_LINK_STATUS BIT(10) 36 #define RTL8211F_INER_PME BIT(7) 37 #define RTL8211F_INER_LINK_STATUS BIT(4) 38 39 #define RTL821x_INSR 0x13 40 41 #define RTL821x_EXT_PAGE_SELECT 0x1e 42 43 #define RTL821x_PAGE_SELECT 0x1f 44 #define RTL821x_SET_EXT_PAGE 0x07 45 46 /* RTL8211E extension page 44/0x2c */ 47 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 48 #define RTL8211E_LEDCR1 0x1a 49 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 50 #define RTL8211E_LEDCR1_MASK BIT(4) 51 #define RTL8211E_LEDCR1_SHIFT 1 52 53 #define RTL8211E_LEDCR2 0x1c 54 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 55 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 56 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 57 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 58 #define RTL8211E_LEDCR2_SHIFT 4 59 60 /* RTL8211E extension page 164/0xa4 */ 61 #define RTL8211E_RGMII_EXT_PAGE 0xa4 62 #define RTL8211E_RGMII_DELAY 0x1c 63 #define RTL8211E_CTRL_DELAY BIT(13) 64 #define RTL8211E_TX_DELAY BIT(12) 65 #define RTL8211E_RX_DELAY BIT(11) 66 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 67 68 /* RTL8211F PHY configuration */ 69 #define RTL8211F_PHYCR_PAGE 0xa43 70 #define RTL8211F_PHYCR1 0x18 71 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 72 #define RTL8211F_ALDPS_ENABLE BIT(2) 73 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 74 75 #define RTL8211F_PHYCR2 0x19 76 #define RTL8211F_CLKOUT_EN BIT(0) 77 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 78 79 #define RTL8211F_INSR_PAGE 0xa43 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F RGMII configuration */ 94 #define RTL8211F_RGMII_PAGE 0xd08 95 96 #define RTL8211F_TXCR 0x11 97 #define RTL8211F_TX_DELAY BIT(8) 98 99 #define RTL8211F_RXCR 0x15 100 #define RTL8211F_RX_DELAY BIT(3) 101 102 /* RTL8211F WOL settings */ 103 #define RTL8211F_WOL_PAGE 0xd8a 104 #define RTL8211F_WOL_SETTINGS_EVENTS 16 105 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 106 #define RTL8211F_WOL_RST_RMSQ 17 107 #define RTL8211F_WOL_RG_RSTB BIT(15) 108 #define RTL8211F_WOL_RMSQ 0x1fff 109 110 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 111 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 112 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 113 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 114 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 115 116 #define RTL822X_VND1_SERDES_OPTION 0x697a 117 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 118 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 119 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 120 121 #define RTL822X_VND1_SERDES_CTRL3 0x7580 122 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 123 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 124 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 125 126 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 127 * is set, they cannot be accessed by C45-over-C22. 128 */ 129 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 130 131 #define RTL8224_MII_RTCT 0x11 132 #define RTL8224_MII_RTCT_ENABLE BIT(0) 133 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 134 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 135 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 136 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 137 #define RTL8224_MII_RTCT_DONE BIT(15) 138 139 #define RTL8224_MII_SRAM_ADDR 0x1b 140 #define RTL8224_MII_SRAM_DATA 0x1c 141 142 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 143 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 144 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 145 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 146 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 147 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 148 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 149 150 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 151 152 #define RTL8366RB_POWER_SAVE 0x15 153 #define RTL8366RB_POWER_SAVE_ON BIT(12) 154 155 #define RTL9000A_GINMR 0x14 156 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 157 158 #define RTL_VND2_PHYSR 0xa434 159 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 160 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 161 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 162 #define RTL_VND2_PHYSR_MASTER BIT(11) 163 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 164 165 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 166 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 167 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 168 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 169 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 170 #define RTL_MDIO_PMA_SPEED 0xa616 171 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 172 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 173 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 174 175 #define RTL_GENERIC_PHYID 0x001cc800 176 #define RTL_8211FVD_PHYID 0x001cc878 177 #define RTL_8221B 0x001cc840 178 #define RTL_8221B_VB_CG 0x001cc849 179 #define RTL_8221B_VM_CG 0x001cc84a 180 #define RTL_8251B 0x001cc862 181 #define RTL_8261C 0x001cc890 182 183 /* RTL8211E and RTL8211F support up to three LEDs */ 184 #define RTL8211x_LED_COUNT 3 185 186 MODULE_DESCRIPTION("Realtek PHY driver"); 187 MODULE_AUTHOR("Johnson Leung"); 188 MODULE_LICENSE("GPL"); 189 190 struct rtl821x_priv { 191 u16 phycr1; 192 u16 phycr2; 193 bool has_phycr2; 194 struct clk *clk; 195 /* rtl8211f */ 196 u16 iner; 197 }; 198 199 static int rtl821x_read_page(struct phy_device *phydev) 200 { 201 return __phy_read(phydev, RTL821x_PAGE_SELECT); 202 } 203 204 static int rtl821x_write_page(struct phy_device *phydev, int page) 205 { 206 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 207 } 208 209 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 210 u32 regnum) 211 { 212 int oldpage, ret = 0; 213 214 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 215 if (oldpage >= 0) { 216 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 217 if (ret == 0) 218 ret = __phy_read(phydev, regnum); 219 } 220 221 return phy_restore_page(phydev, oldpage, ret); 222 } 223 224 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 225 u32 regnum, u16 mask, u16 set) 226 { 227 int oldpage, ret = 0; 228 229 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 230 if (oldpage >= 0) { 231 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 232 if (ret == 0) 233 ret = __phy_modify(phydev, regnum, mask, set); 234 } 235 236 return phy_restore_page(phydev, oldpage, ret); 237 } 238 239 static int rtl821x_probe(struct phy_device *phydev) 240 { 241 struct device *dev = &phydev->mdio.dev; 242 struct rtl821x_priv *priv; 243 u32 phy_id = phydev->drv->phy_id; 244 int ret; 245 246 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 247 if (!priv) 248 return -ENOMEM; 249 250 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 251 if (IS_ERR(priv->clk)) 252 return dev_err_probe(dev, PTR_ERR(priv->clk), 253 "failed to get phy clock\n"); 254 255 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1); 256 if (ret < 0) 257 return ret; 258 259 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 260 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 261 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 262 263 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 264 if (priv->has_phycr2) { 265 ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2); 266 if (ret < 0) 267 return ret; 268 269 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 270 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 271 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 272 } 273 274 phydev->priv = priv; 275 276 return 0; 277 } 278 279 static int rtl8211f_probe(struct phy_device *phydev) 280 { 281 struct device *dev = &phydev->mdio.dev; 282 int ret; 283 284 ret = rtl821x_probe(phydev); 285 if (ret < 0) 286 return ret; 287 288 /* Disable all PME events */ 289 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 290 RTL8211F_WOL_SETTINGS_EVENTS, 0); 291 if (ret < 0) 292 return ret; 293 294 /* Mark this PHY as wakeup capable and register the interrupt as a 295 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 296 * and the interrupt is valid. 297 */ 298 if (device_property_read_bool(dev, "wakeup-source") && 299 phy_interrupt_is_valid(phydev)) { 300 device_set_wakeup_capable(dev, true); 301 devm_pm_set_wake_irq(dev, phydev->irq); 302 } 303 304 return ret; 305 } 306 307 static int rtl8201_ack_interrupt(struct phy_device *phydev) 308 { 309 int err; 310 311 err = phy_read(phydev, RTL8201F_ISR); 312 313 return (err < 0) ? err : 0; 314 } 315 316 static int rtl821x_ack_interrupt(struct phy_device *phydev) 317 { 318 int err; 319 320 err = phy_read(phydev, RTL821x_INSR); 321 322 return (err < 0) ? err : 0; 323 } 324 325 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 326 { 327 int err; 328 329 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 330 331 return (err < 0) ? err : 0; 332 } 333 334 static int rtl8201_config_intr(struct phy_device *phydev) 335 { 336 u16 val; 337 int err; 338 339 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 340 err = rtl8201_ack_interrupt(phydev); 341 if (err) 342 return err; 343 344 val = BIT(13) | BIT(12) | BIT(11); 345 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 346 } else { 347 val = 0; 348 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 349 if (err) 350 return err; 351 352 err = rtl8201_ack_interrupt(phydev); 353 } 354 355 return err; 356 } 357 358 static int rtl8211b_config_intr(struct phy_device *phydev) 359 { 360 int err; 361 362 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 363 err = rtl821x_ack_interrupt(phydev); 364 if (err) 365 return err; 366 367 err = phy_write(phydev, RTL821x_INER, 368 RTL8211B_INER_INIT); 369 } else { 370 err = phy_write(phydev, RTL821x_INER, 0); 371 if (err) 372 return err; 373 374 err = rtl821x_ack_interrupt(phydev); 375 } 376 377 return err; 378 } 379 380 static int rtl8211e_config_intr(struct phy_device *phydev) 381 { 382 int err; 383 384 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 385 err = rtl821x_ack_interrupt(phydev); 386 if (err) 387 return err; 388 389 err = phy_write(phydev, RTL821x_INER, 390 RTL8211E_INER_LINK_STATUS); 391 } else { 392 err = phy_write(phydev, RTL821x_INER, 0); 393 if (err) 394 return err; 395 396 err = rtl821x_ack_interrupt(phydev); 397 } 398 399 return err; 400 } 401 402 static int rtl8211f_config_intr(struct phy_device *phydev) 403 { 404 struct rtl821x_priv *priv = phydev->priv; 405 u16 val; 406 int err; 407 408 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 409 err = rtl8211f_ack_interrupt(phydev); 410 if (err) 411 return err; 412 413 val = RTL8211F_INER_LINK_STATUS; 414 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 415 if (err == 0) 416 priv->iner = val; 417 } else { 418 priv->iner = val = 0; 419 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 420 if (err) 421 return err; 422 423 err = rtl8211f_ack_interrupt(phydev); 424 } 425 426 return err; 427 } 428 429 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 430 { 431 int irq_status; 432 433 irq_status = phy_read(phydev, RTL8201F_ISR); 434 if (irq_status < 0) { 435 phy_error(phydev); 436 return IRQ_NONE; 437 } 438 439 if (!(irq_status & RTL8201F_ISR_MASK)) 440 return IRQ_NONE; 441 442 phy_trigger_machine(phydev); 443 444 return IRQ_HANDLED; 445 } 446 447 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 448 { 449 int irq_status, irq_enabled; 450 451 irq_status = phy_read(phydev, RTL821x_INSR); 452 if (irq_status < 0) { 453 phy_error(phydev); 454 return IRQ_NONE; 455 } 456 457 irq_enabled = phy_read(phydev, RTL821x_INER); 458 if (irq_enabled < 0) { 459 phy_error(phydev); 460 return IRQ_NONE; 461 } 462 463 if (!(irq_status & irq_enabled)) 464 return IRQ_NONE; 465 466 phy_trigger_machine(phydev); 467 468 return IRQ_HANDLED; 469 } 470 471 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 472 { 473 int irq_status; 474 475 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 476 if (irq_status < 0) { 477 phy_error(phydev); 478 return IRQ_NONE; 479 } 480 481 if (irq_status & RTL8211F_INER_LINK_STATUS) { 482 phy_trigger_machine(phydev); 483 return IRQ_HANDLED; 484 } 485 486 if (irq_status & RTL8211F_INER_PME) { 487 pm_wakeup_event(&phydev->mdio.dev, 0); 488 return IRQ_HANDLED; 489 } 490 491 return IRQ_NONE; 492 } 493 494 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 495 { 496 int wol_events; 497 498 /* If the PHY is not capable of waking the system, then WoL can not 499 * be supported. 500 */ 501 if (!device_can_wakeup(&dev->mdio.dev)) { 502 wol->supported = 0; 503 return; 504 } 505 506 wol->supported = WAKE_MAGIC; 507 508 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 509 if (wol_events < 0) 510 return; 511 512 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 513 wol->wolopts = WAKE_MAGIC; 514 } 515 516 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 517 { 518 const u8 *mac_addr = dev->attached_dev->dev_addr; 519 int oldpage; 520 521 if (!device_can_wakeup(&dev->mdio.dev)) 522 return -EOPNOTSUPP; 523 524 oldpage = phy_save_page(dev); 525 if (oldpage < 0) 526 goto err; 527 528 if (wol->wolopts & WAKE_MAGIC) { 529 /* Store the device address for the magic packet */ 530 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 531 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 532 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 533 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 534 535 /* Enable magic packet matching */ 536 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 537 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 538 /* Set the maximum packet size, and assert WoL reset */ 539 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 540 } else { 541 /* Disable magic packet matching */ 542 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 543 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 544 545 /* Place WoL in reset */ 546 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 547 RTL8211F_WOL_RG_RSTB); 548 } 549 550 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 551 552 err: 553 return phy_restore_page(dev, oldpage, 0); 554 } 555 556 static int rtl8211_config_aneg(struct phy_device *phydev) 557 { 558 int ret; 559 560 ret = genphy_config_aneg(phydev); 561 if (ret < 0) 562 return ret; 563 564 /* Quirk was copied from vendor driver. Unfortunately it includes no 565 * description of the magic numbers. 566 */ 567 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 568 phy_write(phydev, 0x17, 0x2138); 569 phy_write(phydev, 0x0e, 0x0260); 570 } else { 571 phy_write(phydev, 0x17, 0x2108); 572 phy_write(phydev, 0x0e, 0x0000); 573 } 574 575 return 0; 576 } 577 578 static int rtl8211c_config_init(struct phy_device *phydev) 579 { 580 /* RTL8211C has an issue when operating in Gigabit slave mode */ 581 return phy_set_bits(phydev, MII_CTRL1000, 582 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 583 } 584 585 static int rtl8211f_config_init(struct phy_device *phydev) 586 { 587 struct rtl821x_priv *priv = phydev->priv; 588 struct device *dev = &phydev->mdio.dev; 589 u16 val_txdly, val_rxdly; 590 int ret; 591 592 ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1, 593 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 594 priv->phycr1); 595 if (ret < 0) { 596 dev_err(dev, "aldps mode configuration failed: %pe\n", 597 ERR_PTR(ret)); 598 return ret; 599 } 600 601 switch (phydev->interface) { 602 case PHY_INTERFACE_MODE_RGMII: 603 val_txdly = 0; 604 val_rxdly = 0; 605 break; 606 607 case PHY_INTERFACE_MODE_RGMII_RXID: 608 val_txdly = 0; 609 val_rxdly = RTL8211F_RX_DELAY; 610 break; 611 612 case PHY_INTERFACE_MODE_RGMII_TXID: 613 val_txdly = RTL8211F_TX_DELAY; 614 val_rxdly = 0; 615 break; 616 617 case PHY_INTERFACE_MODE_RGMII_ID: 618 val_txdly = RTL8211F_TX_DELAY; 619 val_rxdly = RTL8211F_RX_DELAY; 620 break; 621 622 default: /* the rest of the modes imply leaving delay as is. */ 623 return 0; 624 } 625 626 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 627 RTL8211F_TXCR, RTL8211F_TX_DELAY, 628 val_txdly); 629 if (ret < 0) { 630 dev_err(dev, "Failed to update the TX delay register\n"); 631 return ret; 632 } else if (ret) { 633 dev_dbg(dev, 634 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 635 str_enable_disable(val_txdly)); 636 } else { 637 dev_dbg(dev, 638 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 639 str_enabled_disabled(val_txdly)); 640 } 641 642 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 643 RTL8211F_RXCR, RTL8211F_RX_DELAY, 644 val_rxdly); 645 if (ret < 0) { 646 dev_err(dev, "Failed to update the RX delay register\n"); 647 return ret; 648 } else if (ret) { 649 dev_dbg(dev, 650 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 651 str_enable_disable(val_rxdly)); 652 } else { 653 dev_dbg(dev, 654 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 655 str_enabled_disabled(val_rxdly)); 656 } 657 658 if (!priv->has_phycr2) 659 return 0; 660 661 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 662 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2, 663 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 664 if (ret) 665 return ret; 666 667 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, 668 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 669 priv->phycr2); 670 if (ret < 0) { 671 dev_err(dev, "clkout configuration failed: %pe\n", 672 ERR_PTR(ret)); 673 return ret; 674 } 675 676 return genphy_soft_reset(phydev); 677 } 678 679 static int rtl821x_suspend(struct phy_device *phydev) 680 { 681 struct rtl821x_priv *priv = phydev->priv; 682 int ret = 0; 683 684 if (!phydev->wol_enabled) { 685 ret = genphy_suspend(phydev); 686 687 if (ret) 688 return ret; 689 690 clk_disable_unprepare(priv->clk); 691 } 692 693 return ret; 694 } 695 696 static int rtl8211f_suspend(struct phy_device *phydev) 697 { 698 u16 wol_rst; 699 int ret; 700 701 ret = rtl821x_suspend(phydev); 702 if (ret < 0) 703 return ret; 704 705 /* If a PME event is enabled, then configure the interrupt for 706 * PME events only, disabling link interrupt. We avoid switching 707 * to PMEB mode as we don't have a status bit for that. 708 */ 709 if (device_may_wakeup(&phydev->mdio.dev)) { 710 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 711 RTL8211F_INER_PME); 712 if (ret < 0) 713 goto err; 714 715 /* Read the INSR to clear any pending interrupt */ 716 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR); 717 718 /* Reset the WoL to ensure that an event is picked up. 719 * Unless we do this, even if we receive another packet, 720 * we may not have a PME interrupt raised. 721 */ 722 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 723 RTL8211F_WOL_RST_RMSQ); 724 if (ret < 0) 725 goto err; 726 727 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 728 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 729 RTL8211F_WOL_RST_RMSQ, wol_rst); 730 if (ret < 0) 731 goto err; 732 733 wol_rst |= RTL8211F_WOL_RG_RSTB; 734 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 735 RTL8211F_WOL_RST_RMSQ, wol_rst); 736 } 737 738 err: 739 return ret; 740 } 741 742 static int rtl821x_resume(struct phy_device *phydev) 743 { 744 struct rtl821x_priv *priv = phydev->priv; 745 int ret; 746 747 if (!phydev->wol_enabled) 748 clk_prepare_enable(priv->clk); 749 750 ret = genphy_resume(phydev); 751 if (ret < 0) 752 return ret; 753 754 msleep(20); 755 756 return 0; 757 } 758 759 static int rtl8211f_resume(struct phy_device *phydev) 760 { 761 struct rtl821x_priv *priv = phydev->priv; 762 int ret; 763 764 ret = rtl821x_resume(phydev); 765 if (ret < 0) 766 return ret; 767 768 /* If the device was programmed for a PME event, restore the interrupt 769 * enable so phylib can receive link state interrupts. 770 */ 771 if (device_may_wakeup(&phydev->mdio.dev)) 772 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 773 774 return ret; 775 } 776 777 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 778 unsigned long rules) 779 { 780 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 781 BIT(TRIGGER_NETDEV_LINK_10) | 782 BIT(TRIGGER_NETDEV_LINK_100) | 783 BIT(TRIGGER_NETDEV_LINK_1000) | 784 BIT(TRIGGER_NETDEV_RX) | 785 BIT(TRIGGER_NETDEV_TX); 786 787 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 788 * - Link: Configurable subset of 10/100/1000 link rates 789 * - Active: Blink on activity, RX or TX is not differentiated 790 * The Active option has two modes, A and B: 791 * - A: Link and Active indication at configurable, but matching, 792 * subset of 10/100/1000 link rates 793 * - B: Link indication at configurable subset of 10/100/1000 link 794 * rates and Active indication always at all three 10+100+1000 795 * link rates. 796 * This code currently uses mode B only. 797 * 798 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 799 */ 800 801 if (index >= RTL8211x_LED_COUNT) 802 return -EINVAL; 803 804 /* Filter out any other unsupported triggers. */ 805 if (rules & ~mask) 806 return -EOPNOTSUPP; 807 808 /* RX and TX are not differentiated, either both are set or not set. */ 809 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 810 return -EOPNOTSUPP; 811 812 return 0; 813 } 814 815 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 816 unsigned long *rules) 817 { 818 int val; 819 820 if (index >= RTL8211x_LED_COUNT) 821 return -EINVAL; 822 823 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 824 if (val < 0) 825 return val; 826 827 val >>= RTL8211F_LEDCR_SHIFT * index; 828 val &= RTL8211F_LEDCR_MASK; 829 830 if (val & RTL8211F_LEDCR_LINK_10) 831 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 832 833 if (val & RTL8211F_LEDCR_LINK_100) 834 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 835 836 if (val & RTL8211F_LEDCR_LINK_1000) 837 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 838 839 if ((val & RTL8211F_LEDCR_LINK_10) && 840 (val & RTL8211F_LEDCR_LINK_100) && 841 (val & RTL8211F_LEDCR_LINK_1000)) { 842 __set_bit(TRIGGER_NETDEV_LINK, rules); 843 } 844 845 if (val & RTL8211F_LEDCR_ACT_TXRX) { 846 __set_bit(TRIGGER_NETDEV_RX, rules); 847 __set_bit(TRIGGER_NETDEV_TX, rules); 848 } 849 850 return 0; 851 } 852 853 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 854 unsigned long rules) 855 { 856 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 857 u16 reg = 0; 858 859 if (index >= RTL8211x_LED_COUNT) 860 return -EINVAL; 861 862 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 863 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 864 reg |= RTL8211F_LEDCR_LINK_10; 865 } 866 867 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 868 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 869 reg |= RTL8211F_LEDCR_LINK_100; 870 } 871 872 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 873 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 874 reg |= RTL8211F_LEDCR_LINK_1000; 875 } 876 877 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 878 test_bit(TRIGGER_NETDEV_TX, &rules)) { 879 reg |= RTL8211F_LEDCR_ACT_TXRX; 880 } 881 882 reg <<= RTL8211F_LEDCR_SHIFT * index; 883 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 884 885 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 886 } 887 888 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 889 unsigned long *rules) 890 { 891 int ret; 892 u16 cr1, cr2; 893 894 if (index >= RTL8211x_LED_COUNT) 895 return -EINVAL; 896 897 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 898 RTL8211E_LEDCR1); 899 if (ret < 0) 900 return ret; 901 902 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 903 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 904 __set_bit(TRIGGER_NETDEV_RX, rules); 905 __set_bit(TRIGGER_NETDEV_TX, rules); 906 } 907 908 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 909 RTL8211E_LEDCR2); 910 if (ret < 0) 911 return ret; 912 913 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 914 if (cr2 & RTL8211E_LEDCR2_LINK_10) 915 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 916 917 if (cr2 & RTL8211E_LEDCR2_LINK_100) 918 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 919 920 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 921 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 922 923 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 924 (cr2 & RTL8211E_LEDCR2_LINK_100) && 925 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 926 __set_bit(TRIGGER_NETDEV_LINK, rules); 927 } 928 929 return ret; 930 } 931 932 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 933 unsigned long rules) 934 { 935 const u16 cr1mask = 936 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 937 const u16 cr2mask = 938 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 939 u16 cr1 = 0, cr2 = 0; 940 int ret; 941 942 if (index >= RTL8211x_LED_COUNT) 943 return -EINVAL; 944 945 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 946 test_bit(TRIGGER_NETDEV_TX, &rules)) { 947 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 948 } 949 950 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 951 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 952 RTL8211E_LEDCR1, cr1mask, cr1); 953 if (ret < 0) 954 return ret; 955 956 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 957 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 958 cr2 |= RTL8211E_LEDCR2_LINK_10; 959 } 960 961 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 962 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 963 cr2 |= RTL8211E_LEDCR2_LINK_100; 964 } 965 966 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 967 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 968 cr2 |= RTL8211E_LEDCR2_LINK_1000; 969 } 970 971 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 972 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 973 RTL8211E_LEDCR2, cr2mask, cr2); 974 975 return ret; 976 } 977 978 static int rtl8211e_config_init(struct phy_device *phydev) 979 { 980 u16 val; 981 982 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 983 switch (phydev->interface) { 984 case PHY_INTERFACE_MODE_RGMII: 985 val = RTL8211E_CTRL_DELAY | 0; 986 break; 987 case PHY_INTERFACE_MODE_RGMII_ID: 988 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 989 break; 990 case PHY_INTERFACE_MODE_RGMII_RXID: 991 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 992 break; 993 case PHY_INTERFACE_MODE_RGMII_TXID: 994 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 995 break; 996 default: /* the rest of the modes imply leaving delays as is. */ 997 return 0; 998 } 999 1000 /* According to a sample driver there is a 0x1c config register on the 1001 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1002 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1003 * The configuration register definition: 1004 * 14 = reserved 1005 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1006 * 12 = RX Delay, 11 = TX Delay 1007 * 10:0 = Test && debug settings reserved by realtek 1008 */ 1009 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1010 RTL8211E_RGMII_DELAY, 1011 RTL8211E_DELAY_MASK, val); 1012 } 1013 1014 static int rtl8211b_suspend(struct phy_device *phydev) 1015 { 1016 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1017 1018 return genphy_suspend(phydev); 1019 } 1020 1021 static int rtl8211b_resume(struct phy_device *phydev) 1022 { 1023 phy_write(phydev, MII_MMD_DATA, 0); 1024 1025 return genphy_resume(phydev); 1026 } 1027 1028 static int rtl8366rb_config_init(struct phy_device *phydev) 1029 { 1030 int ret; 1031 1032 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1033 RTL8366RB_POWER_SAVE_ON); 1034 if (ret) { 1035 dev_err(&phydev->mdio.dev, 1036 "error enabling power management\n"); 1037 } 1038 1039 return ret; 1040 } 1041 1042 /* get actual speed to cover the downshift case */ 1043 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1044 { 1045 /* bit 3 1046 * 0: Half Duplex 1047 * 1: Full Duplex 1048 */ 1049 if (val & RTL_VND2_PHYSR_DUPLEX) 1050 phydev->duplex = DUPLEX_FULL; 1051 else 1052 phydev->duplex = DUPLEX_HALF; 1053 1054 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 1055 case 0x0000: 1056 phydev->speed = SPEED_10; 1057 break; 1058 case 0x0010: 1059 phydev->speed = SPEED_100; 1060 break; 1061 case 0x0020: 1062 phydev->speed = SPEED_1000; 1063 break; 1064 case 0x0200: 1065 phydev->speed = SPEED_10000; 1066 break; 1067 case 0x0210: 1068 phydev->speed = SPEED_2500; 1069 break; 1070 case 0x0220: 1071 phydev->speed = SPEED_5000; 1072 break; 1073 default: 1074 break; 1075 } 1076 1077 /* bit 11 1078 * 0: Slave Mode 1079 * 1: Master Mode 1080 */ 1081 if (phydev->speed >= 1000) { 1082 if (val & RTL_VND2_PHYSR_MASTER) 1083 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1084 else 1085 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1086 } else { 1087 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1088 } 1089 } 1090 1091 static int rtlgen_read_status(struct phy_device *phydev) 1092 { 1093 int ret, val; 1094 1095 ret = genphy_read_status(phydev); 1096 if (ret < 0) 1097 return ret; 1098 1099 if (!phydev->link) 1100 return 0; 1101 1102 val = phy_read_paged(phydev, 0xa43, 0x12); 1103 if (val < 0) 1104 return val; 1105 1106 rtlgen_decode_physr(phydev, val); 1107 1108 return 0; 1109 } 1110 1111 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1112 { 1113 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1114 } 1115 1116 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1117 { 1118 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1119 val); 1120 } 1121 1122 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1123 { 1124 int ret; 1125 1126 if (devnum == MDIO_MMD_VEND2) 1127 ret = rtlgen_read_vend2(phydev, regnum); 1128 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1129 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1130 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1131 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1132 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1133 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1134 else 1135 ret = -EOPNOTSUPP; 1136 1137 return ret; 1138 } 1139 1140 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1141 u16 val) 1142 { 1143 int ret; 1144 1145 if (devnum == MDIO_MMD_VEND2) 1146 ret = rtlgen_write_vend2(phydev, regnum, val); 1147 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1148 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1149 else 1150 ret = -EOPNOTSUPP; 1151 1152 return ret; 1153 } 1154 1155 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1156 { 1157 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1158 1159 if (ret != -EOPNOTSUPP) 1160 return ret; 1161 1162 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1163 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1164 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1165 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1166 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1167 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1168 1169 return ret; 1170 } 1171 1172 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1173 u16 val) 1174 { 1175 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1176 1177 if (ret != -EOPNOTSUPP) 1178 return ret; 1179 1180 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1181 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1182 1183 return ret; 1184 } 1185 1186 static int rtl822x_probe(struct phy_device *phydev) 1187 { 1188 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1189 phydev->phy_id != RTL_GENERIC_PHYID) 1190 return rtl822x_hwmon_init(phydev); 1191 1192 return 0; 1193 } 1194 1195 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1196 { 1197 bool has_2500, has_sgmii; 1198 u16 mode; 1199 int ret; 1200 1201 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1202 phydev->host_interfaces) || 1203 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1204 1205 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1206 phydev->host_interfaces) || 1207 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1208 1209 /* fill in possible interfaces */ 1210 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1211 has_2500); 1212 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1213 has_sgmii); 1214 1215 if (!has_2500 && !has_sgmii) 1216 return 0; 1217 1218 /* determine SerDes option mode */ 1219 if (has_2500 && !has_sgmii) { 1220 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1221 phydev->rate_matching = RATE_MATCH_PAUSE; 1222 } else { 1223 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1224 phydev->rate_matching = RATE_MATCH_NONE; 1225 } 1226 1227 /* the following sequence with magic numbers sets up the SerDes 1228 * option mode 1229 */ 1230 1231 if (!gen1) { 1232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1233 if (ret < 0) 1234 return ret; 1235 } 1236 1237 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1238 RTL822X_VND1_SERDES_OPTION, 1239 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1240 mode); 1241 if (gen1 || ret < 0) 1242 return ret; 1243 1244 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1245 if (ret < 0) 1246 return ret; 1247 1248 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1249 if (ret < 0) 1250 return ret; 1251 1252 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1253 } 1254 1255 static int rtl822x_config_init(struct phy_device *phydev) 1256 { 1257 return rtl822x_set_serdes_option_mode(phydev, true); 1258 } 1259 1260 static int rtl822xb_config_init(struct phy_device *phydev) 1261 { 1262 return rtl822x_set_serdes_option_mode(phydev, false); 1263 } 1264 1265 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1266 phy_interface_t iface) 1267 { 1268 int val; 1269 1270 /* Only rate matching at 2500base-x */ 1271 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1272 return RATE_MATCH_NONE; 1273 1274 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1275 if (val < 0) 1276 return val; 1277 1278 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1279 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1280 return RATE_MATCH_PAUSE; 1281 1282 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1283 return RATE_MATCH_NONE; 1284 } 1285 1286 static int rtl822x_get_features(struct phy_device *phydev) 1287 { 1288 int val; 1289 1290 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1291 if (val < 0) 1292 return val; 1293 1294 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1295 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1296 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1297 phydev->supported, val & MDIO_PMA_SPEED_5G); 1298 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1299 phydev->supported, val & MDIO_SPEED_10G); 1300 1301 return genphy_read_abilities(phydev); 1302 } 1303 1304 static int rtl822x_config_aneg(struct phy_device *phydev) 1305 { 1306 int ret = 0; 1307 1308 if (phydev->autoneg == AUTONEG_ENABLE) { 1309 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1310 1311 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1312 RTL_MDIO_AN_10GBT_CTRL, 1313 MDIO_AN_10GBT_CTRL_ADV2_5G | 1314 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1315 if (ret < 0) 1316 return ret; 1317 } 1318 1319 return __genphy_config_aneg(phydev, ret); 1320 } 1321 1322 static void rtl822xb_update_interface(struct phy_device *phydev) 1323 { 1324 int val; 1325 1326 if (!phydev->link) 1327 return; 1328 1329 /* Change interface according to serdes mode */ 1330 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1331 if (val < 0) 1332 return; 1333 1334 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1335 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1336 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1337 break; 1338 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1339 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1340 break; 1341 } 1342 } 1343 1344 static int rtl822x_read_status(struct phy_device *phydev) 1345 { 1346 int lpadv, ret; 1347 1348 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1349 1350 ret = rtlgen_read_status(phydev); 1351 if (ret < 0) 1352 return ret; 1353 1354 if (phydev->autoneg == AUTONEG_DISABLE || 1355 !phydev->autoneg_complete) 1356 return 0; 1357 1358 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1359 if (lpadv < 0) 1360 return lpadv; 1361 1362 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1363 1364 return 0; 1365 } 1366 1367 static int rtl822xb_read_status(struct phy_device *phydev) 1368 { 1369 int ret; 1370 1371 ret = rtl822x_read_status(phydev); 1372 if (ret < 0) 1373 return ret; 1374 1375 rtl822xb_update_interface(phydev); 1376 1377 return 0; 1378 } 1379 1380 static int rtl822x_c45_get_features(struct phy_device *phydev) 1381 { 1382 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1383 phydev->supported); 1384 1385 return genphy_c45_pma_read_abilities(phydev); 1386 } 1387 1388 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1389 { 1390 bool changed = false; 1391 int ret, val; 1392 1393 if (phydev->autoneg == AUTONEG_DISABLE) 1394 return genphy_c45_pma_setup_forced(phydev); 1395 1396 ret = genphy_c45_an_config_aneg(phydev); 1397 if (ret < 0) 1398 return ret; 1399 if (ret > 0) 1400 changed = true; 1401 1402 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1403 1404 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1405 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1406 RTL822X_VND2_C22_REG(MII_CTRL1000), 1407 ADVERTISE_1000FULL, val); 1408 if (ret < 0) 1409 return ret; 1410 if (ret > 0) 1411 changed = true; 1412 1413 return genphy_c45_check_and_restart_aneg(phydev, changed); 1414 } 1415 1416 static int rtl822x_c45_read_status(struct phy_device *phydev) 1417 { 1418 int ret, val; 1419 1420 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1421 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1422 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1423 RTL822X_VND2_C22_REG(MII_STAT1000)); 1424 if (val < 0) 1425 return val; 1426 } else { 1427 val = 0; 1428 } 1429 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1430 1431 ret = genphy_c45_read_status(phydev); 1432 if (ret < 0) 1433 return ret; 1434 1435 if (!phydev->link) { 1436 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1437 return 0; 1438 } 1439 1440 /* Read actual speed from vendor register. */ 1441 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1442 if (val < 0) 1443 return val; 1444 1445 rtlgen_decode_physr(phydev, val); 1446 1447 return 0; 1448 } 1449 1450 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1451 { 1452 int ret, val; 1453 1454 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1455 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1456 if (ret < 0) 1457 return ret; 1458 1459 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1460 MDIO_CTRL1, val, 1461 !(val & MDIO_CTRL1_RESET), 1462 5000, 100000, true); 1463 } 1464 1465 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1466 { 1467 int ret; 1468 1469 ret = rtl822x_c45_read_status(phydev); 1470 if (ret < 0) 1471 return ret; 1472 1473 rtl822xb_update_interface(phydev); 1474 1475 return 0; 1476 } 1477 1478 static int rtl8224_cable_test_start(struct phy_device *phydev) 1479 { 1480 u32 val; 1481 int ret; 1482 1483 /* disable auto-negotiation and force 1000/Full */ 1484 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1485 RTL822X_VND2_C22_REG(MII_BMCR), 1486 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1487 BMCR_SPEED1000 | BMCR_FULLDPLX); 1488 if (ret) 1489 return ret; 1490 1491 mdelay(500); 1492 1493 /* trigger cable test */ 1494 val = RTL8224_MII_RTCT_ENABLE; 1495 val |= RTL8224_MII_RTCT_PAIR_A; 1496 val |= RTL8224_MII_RTCT_PAIR_B; 1497 val |= RTL8224_MII_RTCT_PAIR_C; 1498 val |= RTL8224_MII_RTCT_PAIR_D; 1499 1500 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1501 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1502 RTL8224_MII_RTCT_DONE, val); 1503 } 1504 1505 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1506 { 1507 int ret; 1508 1509 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1510 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1511 reg); 1512 if (ret) 1513 return ret; 1514 1515 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1516 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1517 } 1518 1519 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1520 { 1521 int cable_len; 1522 u32 reg_len; 1523 int ret; 1524 u32 cm; 1525 1526 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1527 1528 ret = rtl8224_sram_read(phydev, reg_len); 1529 if (ret < 0) 1530 return ret; 1531 1532 cable_len = ret & 0xff00; 1533 1534 ret = rtl8224_sram_read(phydev, reg_len + 1); 1535 if (ret < 0) 1536 return ret; 1537 1538 cable_len |= (ret & 0xff00) >> 8; 1539 1540 cable_len -= 620; 1541 cable_len = max(cable_len, 0); 1542 1543 cm = cable_len * 100 / 78; 1544 1545 return cm; 1546 } 1547 1548 static int rtl8224_cable_test_result_trans(u32 result) 1549 { 1550 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1551 return -EBUSY; 1552 1553 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1554 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1555 1556 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1557 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1558 1559 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1560 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1561 1562 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1563 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1564 1565 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1566 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1567 1568 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1569 } 1570 1571 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1572 { 1573 int fault_rslt; 1574 int ret; 1575 1576 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1577 if (ret < 0) 1578 return ret; 1579 1580 fault_rslt = rtl8224_cable_test_result_trans(ret); 1581 if (fault_rslt < 0) 1582 return 0; 1583 1584 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1585 if (ret < 0) 1586 return ret; 1587 1588 switch (fault_rslt) { 1589 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1590 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1591 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1592 ret = rtl8224_pair_len_get(phydev, pair); 1593 if (ret < 0) 1594 return ret; 1595 1596 return ethnl_cable_test_fault_length(phydev, pair, ret); 1597 default: 1598 return 0; 1599 } 1600 } 1601 1602 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1603 { 1604 unsigned int pair; 1605 int ret; 1606 1607 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1608 ret = rtl8224_cable_test_report_pair(phydev, pair); 1609 if (ret == -EBUSY) { 1610 *finished = false; 1611 return 0; 1612 } 1613 1614 if (ret < 0) 1615 return ret; 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1622 { 1623 int ret; 1624 1625 *finished = false; 1626 1627 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1628 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1629 if (ret < 0) 1630 return ret; 1631 1632 if (!(ret & RTL8224_MII_RTCT_DONE)) 1633 return 0; 1634 1635 *finished = true; 1636 1637 return rtl8224_cable_test_report(phydev, finished); 1638 } 1639 1640 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1641 { 1642 int val; 1643 1644 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1645 val = phy_read(phydev, 0x13); 1646 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1647 1648 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1649 } 1650 1651 /* On internal PHY's MMD reads over C22 always return 0. 1652 * Check a MMD register which is known to be non-zero. 1653 */ 1654 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1655 { 1656 int val; 1657 1658 phy_lock_mdio_bus(phydev); 1659 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1660 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1661 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1662 val = __phy_read(phydev, MII_MMD_DATA); 1663 phy_unlock_mdio_bus(phydev); 1664 1665 return val > 0; 1666 } 1667 1668 static int rtlgen_match_phy_device(struct phy_device *phydev, 1669 const struct phy_driver *phydrv) 1670 { 1671 return phydev->phy_id == RTL_GENERIC_PHYID && 1672 !rtlgen_supports_2_5gbps(phydev); 1673 } 1674 1675 static int rtl8226_match_phy_device(struct phy_device *phydev, 1676 const struct phy_driver *phydrv) 1677 { 1678 return phydev->phy_id == RTL_GENERIC_PHYID && 1679 rtlgen_supports_2_5gbps(phydev) && 1680 rtlgen_supports_mmd(phydev); 1681 } 1682 1683 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1684 bool is_c45) 1685 { 1686 if (phydev->is_c45) 1687 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1688 else 1689 return !is_c45 && (id == phydev->phy_id); 1690 } 1691 1692 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1693 const struct phy_driver *phydrv) 1694 { 1695 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1696 } 1697 1698 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev, 1699 const struct phy_driver *phydrv) 1700 { 1701 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1702 } 1703 1704 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev, 1705 const struct phy_driver *phydrv) 1706 { 1707 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1708 } 1709 1710 static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev, 1711 const struct phy_driver *phydrv) 1712 { 1713 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1714 } 1715 1716 static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev, 1717 const struct phy_driver *phydrv) 1718 { 1719 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true); 1720 } 1721 1722 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1723 const struct phy_driver *phydrv) 1724 { 1725 if (phydev->is_c45) 1726 return false; 1727 1728 switch (phydev->phy_id) { 1729 case RTL_GENERIC_PHYID: 1730 case RTL_8221B: 1731 case RTL_8251B: 1732 case RTL_8261C: 1733 case 0x001cc841: 1734 break; 1735 default: 1736 return false; 1737 } 1738 1739 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1740 } 1741 1742 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1743 const struct phy_driver *phydrv) 1744 { 1745 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1746 } 1747 1748 static int rtlgen_resume(struct phy_device *phydev) 1749 { 1750 int ret = genphy_resume(phydev); 1751 1752 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1753 msleep(20); 1754 1755 return ret; 1756 } 1757 1758 static int rtlgen_c45_resume(struct phy_device *phydev) 1759 { 1760 int ret = genphy_c45_pma_resume(phydev); 1761 1762 msleep(20); 1763 1764 return ret; 1765 } 1766 1767 static int rtl9000a_config_init(struct phy_device *phydev) 1768 { 1769 phydev->autoneg = AUTONEG_DISABLE; 1770 phydev->speed = SPEED_100; 1771 phydev->duplex = DUPLEX_FULL; 1772 1773 return 0; 1774 } 1775 1776 static int rtl9000a_config_aneg(struct phy_device *phydev) 1777 { 1778 int ret; 1779 u16 ctl = 0; 1780 1781 switch (phydev->master_slave_set) { 1782 case MASTER_SLAVE_CFG_MASTER_FORCE: 1783 ctl |= CTL1000_AS_MASTER; 1784 break; 1785 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1786 break; 1787 case MASTER_SLAVE_CFG_UNKNOWN: 1788 case MASTER_SLAVE_CFG_UNSUPPORTED: 1789 return 0; 1790 default: 1791 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1792 return -EOPNOTSUPP; 1793 } 1794 1795 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1796 if (ret == 1) 1797 ret = genphy_soft_reset(phydev); 1798 1799 return ret; 1800 } 1801 1802 static int rtl9000a_read_status(struct phy_device *phydev) 1803 { 1804 int ret; 1805 1806 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1807 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1808 1809 ret = genphy_update_link(phydev); 1810 if (ret) 1811 return ret; 1812 1813 ret = phy_read(phydev, MII_CTRL1000); 1814 if (ret < 0) 1815 return ret; 1816 if (ret & CTL1000_AS_MASTER) 1817 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1818 else 1819 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1820 1821 ret = phy_read(phydev, MII_STAT1000); 1822 if (ret < 0) 1823 return ret; 1824 if (ret & LPA_1000MSRES) 1825 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1826 else 1827 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1828 1829 return 0; 1830 } 1831 1832 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1833 { 1834 int err; 1835 1836 err = phy_read(phydev, RTL8211F_INSR); 1837 1838 return (err < 0) ? err : 0; 1839 } 1840 1841 static int rtl9000a_config_intr(struct phy_device *phydev) 1842 { 1843 u16 val; 1844 int err; 1845 1846 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1847 err = rtl9000a_ack_interrupt(phydev); 1848 if (err) 1849 return err; 1850 1851 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1852 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1853 } else { 1854 val = ~0; 1855 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1856 if (err) 1857 return err; 1858 1859 err = rtl9000a_ack_interrupt(phydev); 1860 } 1861 1862 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1863 } 1864 1865 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1866 { 1867 int irq_status; 1868 1869 irq_status = phy_read(phydev, RTL8211F_INSR); 1870 if (irq_status < 0) { 1871 phy_error(phydev); 1872 return IRQ_NONE; 1873 } 1874 1875 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1876 return IRQ_NONE; 1877 1878 phy_trigger_machine(phydev); 1879 1880 return IRQ_HANDLED; 1881 } 1882 1883 static struct phy_driver realtek_drvs[] = { 1884 { 1885 PHY_ID_MATCH_EXACT(0x00008201), 1886 .name = "RTL8201CP Ethernet", 1887 .read_page = rtl821x_read_page, 1888 .write_page = rtl821x_write_page, 1889 }, { 1890 PHY_ID_MATCH_EXACT(0x001cc816), 1891 .name = "RTL8201F Fast Ethernet", 1892 .config_intr = &rtl8201_config_intr, 1893 .handle_interrupt = rtl8201_handle_interrupt, 1894 .suspend = genphy_suspend, 1895 .resume = genphy_resume, 1896 .read_page = rtl821x_read_page, 1897 .write_page = rtl821x_write_page, 1898 }, { 1899 PHY_ID_MATCH_MODEL(0x001cc880), 1900 .name = "RTL8208 Fast Ethernet", 1901 .read_mmd = genphy_read_mmd_unsupported, 1902 .write_mmd = genphy_write_mmd_unsupported, 1903 .suspend = genphy_suspend, 1904 .resume = genphy_resume, 1905 .read_page = rtl821x_read_page, 1906 .write_page = rtl821x_write_page, 1907 }, { 1908 PHY_ID_MATCH_EXACT(0x001cc910), 1909 .name = "RTL8211 Gigabit Ethernet", 1910 .config_aneg = rtl8211_config_aneg, 1911 .read_mmd = &genphy_read_mmd_unsupported, 1912 .write_mmd = &genphy_write_mmd_unsupported, 1913 .read_page = rtl821x_read_page, 1914 .write_page = rtl821x_write_page, 1915 }, { 1916 PHY_ID_MATCH_EXACT(0x001cc912), 1917 .name = "RTL8211B Gigabit Ethernet", 1918 .config_intr = &rtl8211b_config_intr, 1919 .handle_interrupt = rtl821x_handle_interrupt, 1920 .read_mmd = &genphy_read_mmd_unsupported, 1921 .write_mmd = &genphy_write_mmd_unsupported, 1922 .suspend = rtl8211b_suspend, 1923 .resume = rtl8211b_resume, 1924 .read_page = rtl821x_read_page, 1925 .write_page = rtl821x_write_page, 1926 }, { 1927 PHY_ID_MATCH_EXACT(0x001cc913), 1928 .name = "RTL8211C Gigabit Ethernet", 1929 .config_init = rtl8211c_config_init, 1930 .read_mmd = &genphy_read_mmd_unsupported, 1931 .write_mmd = &genphy_write_mmd_unsupported, 1932 .read_page = rtl821x_read_page, 1933 .write_page = rtl821x_write_page, 1934 }, { 1935 PHY_ID_MATCH_EXACT(0x001cc914), 1936 .name = "RTL8211DN Gigabit Ethernet", 1937 .config_intr = rtl8211e_config_intr, 1938 .handle_interrupt = rtl821x_handle_interrupt, 1939 .suspend = genphy_suspend, 1940 .resume = genphy_resume, 1941 .read_page = rtl821x_read_page, 1942 .write_page = rtl821x_write_page, 1943 }, { 1944 PHY_ID_MATCH_EXACT(0x001cc915), 1945 .name = "RTL8211E Gigabit Ethernet", 1946 .config_init = &rtl8211e_config_init, 1947 .config_intr = &rtl8211e_config_intr, 1948 .handle_interrupt = rtl821x_handle_interrupt, 1949 .suspend = genphy_suspend, 1950 .resume = genphy_resume, 1951 .read_page = rtl821x_read_page, 1952 .write_page = rtl821x_write_page, 1953 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1954 .led_hw_control_get = rtl8211e_led_hw_control_get, 1955 .led_hw_control_set = rtl8211e_led_hw_control_set, 1956 }, { 1957 PHY_ID_MATCH_EXACT(0x001cc916), 1958 .name = "RTL8211F Gigabit Ethernet", 1959 .probe = rtl8211f_probe, 1960 .config_init = &rtl8211f_config_init, 1961 .read_status = rtlgen_read_status, 1962 .config_intr = &rtl8211f_config_intr, 1963 .handle_interrupt = rtl8211f_handle_interrupt, 1964 .set_wol = rtl8211f_set_wol, 1965 .get_wol = rtl8211f_get_wol, 1966 .suspend = rtl8211f_suspend, 1967 .resume = rtl8211f_resume, 1968 .read_page = rtl821x_read_page, 1969 .write_page = rtl821x_write_page, 1970 .flags = PHY_ALWAYS_CALL_SUSPEND, 1971 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 1972 .led_hw_control_get = rtl8211f_led_hw_control_get, 1973 .led_hw_control_set = rtl8211f_led_hw_control_set, 1974 }, { 1975 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1976 .name = "RTL8211F-VD Gigabit Ethernet", 1977 .probe = rtl821x_probe, 1978 .config_init = &rtl8211f_config_init, 1979 .read_status = rtlgen_read_status, 1980 .config_intr = &rtl8211f_config_intr, 1981 .handle_interrupt = rtl8211f_handle_interrupt, 1982 .suspend = rtl821x_suspend, 1983 .resume = rtl821x_resume, 1984 .read_page = rtl821x_read_page, 1985 .write_page = rtl821x_write_page, 1986 .flags = PHY_ALWAYS_CALL_SUSPEND, 1987 }, { 1988 .name = "Generic FE-GE Realtek PHY", 1989 .match_phy_device = rtlgen_match_phy_device, 1990 .read_status = rtlgen_read_status, 1991 .suspend = genphy_suspend, 1992 .resume = rtlgen_resume, 1993 .read_page = rtl821x_read_page, 1994 .write_page = rtl821x_write_page, 1995 .read_mmd = rtlgen_read_mmd, 1996 .write_mmd = rtlgen_write_mmd, 1997 }, { 1998 .name = "RTL8226 2.5Gbps PHY", 1999 .match_phy_device = rtl8226_match_phy_device, 2000 .get_features = rtl822x_get_features, 2001 .config_aneg = rtl822x_config_aneg, 2002 .read_status = rtl822x_read_status, 2003 .suspend = genphy_suspend, 2004 .resume = rtlgen_resume, 2005 .read_page = rtl821x_read_page, 2006 .write_page = rtl821x_write_page, 2007 }, { 2008 .match_phy_device = rtl8221b_match_phy_device, 2009 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2010 .get_features = rtl822x_get_features, 2011 .config_aneg = rtl822x_config_aneg, 2012 .config_init = rtl822xb_config_init, 2013 .get_rate_matching = rtl822xb_get_rate_matching, 2014 .read_status = rtl822xb_read_status, 2015 .suspend = genphy_suspend, 2016 .resume = rtlgen_resume, 2017 .read_page = rtl821x_read_page, 2018 .write_page = rtl821x_write_page, 2019 }, { 2020 PHY_ID_MATCH_EXACT(0x001cc838), 2021 .name = "RTL8226-CG 2.5Gbps PHY", 2022 .soft_reset = rtl822x_c45_soft_reset, 2023 .get_features = rtl822x_c45_get_features, 2024 .config_aneg = rtl822x_c45_config_aneg, 2025 .config_init = rtl822x_config_init, 2026 .read_status = rtl822xb_c45_read_status, 2027 .suspend = genphy_c45_pma_suspend, 2028 .resume = rtlgen_c45_resume, 2029 }, { 2030 PHY_ID_MATCH_EXACT(0x001cc848), 2031 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2032 .get_features = rtl822x_get_features, 2033 .config_aneg = rtl822x_config_aneg, 2034 .config_init = rtl822xb_config_init, 2035 .get_rate_matching = rtl822xb_get_rate_matching, 2036 .read_status = rtl822xb_read_status, 2037 .suspend = genphy_suspend, 2038 .resume = rtlgen_resume, 2039 .read_page = rtl821x_read_page, 2040 .write_page = rtl821x_write_page, 2041 }, { 2042 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 2043 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 2044 .probe = rtl822x_probe, 2045 .get_features = rtl822x_get_features, 2046 .config_aneg = rtl822x_config_aneg, 2047 .config_init = rtl822xb_config_init, 2048 .get_rate_matching = rtl822xb_get_rate_matching, 2049 .read_status = rtl822xb_read_status, 2050 .suspend = genphy_suspend, 2051 .resume = rtlgen_resume, 2052 .read_page = rtl821x_read_page, 2053 .write_page = rtl821x_write_page, 2054 }, { 2055 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 2056 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 2057 .probe = rtl822x_probe, 2058 .config_init = rtl822xb_config_init, 2059 .get_rate_matching = rtl822xb_get_rate_matching, 2060 .get_features = rtl822x_c45_get_features, 2061 .config_aneg = rtl822x_c45_config_aneg, 2062 .read_status = rtl822xb_c45_read_status, 2063 .suspend = genphy_c45_pma_suspend, 2064 .resume = rtlgen_c45_resume, 2065 }, { 2066 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device, 2067 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 2068 .probe = rtl822x_probe, 2069 .get_features = rtl822x_get_features, 2070 .config_aneg = rtl822x_config_aneg, 2071 .config_init = rtl822xb_config_init, 2072 .get_rate_matching = rtl822xb_get_rate_matching, 2073 .read_status = rtl822xb_read_status, 2074 .suspend = genphy_suspend, 2075 .resume = rtlgen_resume, 2076 .read_page = rtl821x_read_page, 2077 .write_page = rtl821x_write_page, 2078 }, { 2079 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device, 2080 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)", 2081 .probe = rtl822x_probe, 2082 .config_init = rtl822xb_config_init, 2083 .get_rate_matching = rtl822xb_get_rate_matching, 2084 .get_features = rtl822x_c45_get_features, 2085 .config_aneg = rtl822x_c45_config_aneg, 2086 .read_status = rtl822xb_c45_read_status, 2087 .suspend = genphy_c45_pma_suspend, 2088 .resume = rtlgen_c45_resume, 2089 }, { 2090 .match_phy_device = rtl8251b_c45_match_phy_device, 2091 .name = "RTL8251B 5Gbps PHY", 2092 .probe = rtl822x_probe, 2093 .get_features = rtl822x_get_features, 2094 .config_aneg = rtl822x_config_aneg, 2095 .read_status = rtl822x_read_status, 2096 .suspend = genphy_suspend, 2097 .resume = rtlgen_resume, 2098 .read_page = rtl821x_read_page, 2099 .write_page = rtl821x_write_page, 2100 }, { 2101 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2102 .name = "Realtek Internal NBASE-T PHY", 2103 .flags = PHY_IS_INTERNAL, 2104 .probe = rtl822x_probe, 2105 .get_features = rtl822x_get_features, 2106 .config_aneg = rtl822x_config_aneg, 2107 .read_status = rtl822x_read_status, 2108 .suspend = genphy_suspend, 2109 .resume = rtlgen_resume, 2110 .read_page = rtl821x_read_page, 2111 .write_page = rtl821x_write_page, 2112 .read_mmd = rtl822x_read_mmd, 2113 .write_mmd = rtl822x_write_mmd, 2114 }, { 2115 PHY_ID_MATCH_EXACT(0x001ccad0), 2116 .name = "RTL8224 2.5Gbps PHY", 2117 .flags = PHY_POLL_CABLE_TEST, 2118 .get_features = rtl822x_c45_get_features, 2119 .config_aneg = rtl822x_c45_config_aneg, 2120 .read_status = rtl822x_c45_read_status, 2121 .suspend = genphy_c45_pma_suspend, 2122 .resume = rtlgen_c45_resume, 2123 .cable_test_start = rtl8224_cable_test_start, 2124 .cable_test_get_status = rtl8224_cable_test_get_status, 2125 }, { 2126 PHY_ID_MATCH_EXACT(0x001cc961), 2127 .name = "RTL8366RB Gigabit Ethernet", 2128 .config_init = &rtl8366rb_config_init, 2129 /* These interrupts are handled by the irq controller 2130 * embedded inside the RTL8366RB, they get unmasked when the 2131 * irq is requested and ACKed by reading the status register, 2132 * which is done by the irqchip code. 2133 */ 2134 .config_intr = genphy_no_config_intr, 2135 .handle_interrupt = genphy_handle_interrupt_no_ack, 2136 .suspend = genphy_suspend, 2137 .resume = genphy_resume, 2138 }, { 2139 PHY_ID_MATCH_EXACT(0x001ccb00), 2140 .name = "RTL9000AA_RTL9000AN Ethernet", 2141 .features = PHY_BASIC_T1_FEATURES, 2142 .config_init = rtl9000a_config_init, 2143 .config_aneg = rtl9000a_config_aneg, 2144 .read_status = rtl9000a_read_status, 2145 .config_intr = rtl9000a_config_intr, 2146 .handle_interrupt = rtl9000a_handle_interrupt, 2147 .suspend = genphy_suspend, 2148 .resume = genphy_resume, 2149 .read_page = rtl821x_read_page, 2150 .write_page = rtl821x_write_page, 2151 }, { 2152 PHY_ID_MATCH_EXACT(0x001cc942), 2153 .name = "RTL8365MB-VC Gigabit Ethernet", 2154 /* Interrupt handling analogous to RTL8366RB */ 2155 .config_intr = genphy_no_config_intr, 2156 .handle_interrupt = genphy_handle_interrupt_no_ack, 2157 .suspend = genphy_suspend, 2158 .resume = genphy_resume, 2159 }, { 2160 PHY_ID_MATCH_EXACT(0x001cc960), 2161 .name = "RTL8366S Gigabit Ethernet", 2162 .suspend = genphy_suspend, 2163 .resume = genphy_resume, 2164 .read_mmd = genphy_read_mmd_unsupported, 2165 .write_mmd = genphy_write_mmd_unsupported, 2166 }, 2167 }; 2168 2169 module_phy_driver(realtek_drvs); 2170 2171 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2172 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2173 { } 2174 }; 2175 2176 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2177