1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 #include <net/phy/realtek_phy.h> 21 22 #include "../phylib.h" 23 #include "realtek.h" 24 25 #define RTL8201F_IER 0x13 26 27 #define RTL8201F_ISR 0x1e 28 #define RTL8201F_ISR_ANERR BIT(15) 29 #define RTL8201F_ISR_DUPLEX BIT(13) 30 #define RTL8201F_ISR_LINK BIT(11) 31 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 32 RTL8201F_ISR_DUPLEX | \ 33 RTL8201F_ISR_LINK) 34 35 #define RTL821x_INER 0x12 36 #define RTL8211B_INER_INIT 0x6400 37 #define RTL8211E_INER_LINK_STATUS BIT(10) 38 #define RTL8211F_INER_PME BIT(7) 39 #define RTL8211F_INER_LINK_STATUS BIT(4) 40 41 #define RTL821x_INSR 0x13 42 43 #define RTL821x_EXT_PAGE_SELECT 0x1e 44 45 #define RTL821x_PAGE_SELECT 0x1f 46 #define RTL821x_SET_EXT_PAGE 0x07 47 48 /* RTL8211E extension page 44/0x2c */ 49 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 50 #define RTL8211E_LEDCR1 0x1a 51 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 52 #define RTL8211E_LEDCR1_MASK BIT(4) 53 #define RTL8211E_LEDCR1_SHIFT 1 54 55 #define RTL8211E_LEDCR2 0x1c 56 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 57 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 58 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 59 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 60 #define RTL8211E_LEDCR2_SHIFT 4 61 62 /* RTL8211E extension page 164/0xa4 */ 63 #define RTL8211E_RGMII_EXT_PAGE 0xa4 64 #define RTL8211E_RGMII_DELAY 0x1c 65 #define RTL8211E_CTRL_DELAY BIT(13) 66 #define RTL8211E_TX_DELAY BIT(12) 67 #define RTL8211E_RX_DELAY BIT(11) 68 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 69 70 /* RTL8211F PHY configuration */ 71 #define RTL8211F_PHYCR1 0x18 72 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 73 #define RTL8211F_ALDPS_ENABLE BIT(2) 74 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 75 76 #define RTL8211F_PHYCR2 0x19 77 #define RTL8211F_CLKOUT_EN BIT(0) 78 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 79 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 94 * to undocumented register pages. The names here do not reflect the datasheet. 95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 96 */ 97 #define RTL8211FVD_CLKOUT_PAGE 0xd05 98 #define RTL8211FVD_CLKOUT_REG 0x11 99 #define RTL8211FVD_CLKOUT_EN BIT(8) 100 101 /* RTL8211F RGMII configuration */ 102 #define RTL8211F_RGMII_PAGE 0xd08 103 104 #define RTL8211F_TXCR 0x11 105 #define RTL8211F_TX_DELAY BIT(8) 106 107 #define RTL8211F_RXCR 0x15 108 #define RTL8211F_RX_DELAY BIT(3) 109 110 /* RTL8211F WOL settings */ 111 #define RTL8211F_WOL_PAGE 0xd8a 112 #define RTL8211F_WOL_SETTINGS_EVENTS 16 113 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 114 #define RTL8211F_WOL_RST_RMSQ 17 115 #define RTL8211F_WOL_RG_RSTB BIT(15) 116 #define RTL8211F_WOL_RMSQ 0x1fff 117 118 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 119 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 120 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 121 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 122 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 123 124 #define RTL822X_VND1_SERDES_OPTION 0x697a 125 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 126 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 128 129 #define RTL822X_VND1_SERDES_CTRL3 0x7580 130 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 131 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 132 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 133 134 #define RTL822X_VND1_SERDES_CMD 0x7587 135 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 136 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 137 #define RTL822X_VND1_SERDES_ADDR 0x7588 138 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 139 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 140 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 141 #define RTL822X_VND1_SERDES_DATA 0x7589 142 143 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 144 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 145 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 146 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 147 148 #define RTL8221B_VND2_INER 0xa4d2 149 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 150 151 #define RTL8221B_VND2_INSR 0xa4d4 152 153 #define RTL8224_MII_RTCT 0x11 154 #define RTL8224_MII_RTCT_ENABLE BIT(0) 155 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 156 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 157 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 158 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 159 #define RTL8224_MII_RTCT_DONE BIT(15) 160 161 #define RTL8224_MII_SRAM_ADDR 0x1b 162 #define RTL8224_MII_SRAM_DATA 0x1c 163 164 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 165 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 166 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 167 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 168 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 169 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 170 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 171 172 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 173 174 #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 175 #define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 176 177 #define RTL8366RB_POWER_SAVE 0x15 178 #define RTL8366RB_POWER_SAVE_ON BIT(12) 179 180 #define RTL9000A_GINMR 0x14 181 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 182 183 #define RTL_PHYSR MII_RESV2 184 #define RTL_PHYSR_DUPLEX BIT(3) 185 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 186 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 187 #define RTL_PHYSR_MASTER BIT(11) 188 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 189 190 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 191 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 192 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 193 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 194 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 195 #define RTL_MDIO_PMA_SPEED 0xa616 196 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 197 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 198 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 199 200 #define RTL_GENERIC_PHYID 0x001cc800 201 #define RTL_8211FVD_PHYID 0x001cc878 202 #define RTL_8221B 0x001cc840 203 #define RTL_8221B_VB_CG 0x001cc849 204 #define RTL_8221B_VM_CG 0x001cc84a 205 #define RTL_8251B 0x001cc862 206 #define RTL_8261C 0x001cc890 207 208 /* RTL8211E and RTL8211F support up to three LEDs */ 209 #define RTL8211x_LED_COUNT 3 210 211 MODULE_DESCRIPTION("Realtek PHY driver"); 212 MODULE_AUTHOR("Johnson Leung"); 213 MODULE_LICENSE("GPL"); 214 215 struct rtl821x_priv { 216 bool enable_aldps; 217 bool disable_clk_out; 218 struct clk *clk; 219 /* rtl8211f */ 220 u16 iner; 221 }; 222 223 static int rtl821x_read_page(struct phy_device *phydev) 224 { 225 return __phy_read(phydev, RTL821x_PAGE_SELECT); 226 } 227 228 static int rtl821x_write_page(struct phy_device *phydev, int page) 229 { 230 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 231 } 232 233 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 234 u32 regnum) 235 { 236 int oldpage, ret = 0; 237 238 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 239 if (oldpage >= 0) { 240 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 241 if (ret == 0) 242 ret = __phy_read(phydev, regnum); 243 } 244 245 return phy_restore_page(phydev, oldpage, ret); 246 } 247 248 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 249 u32 regnum, u16 mask, u16 set) 250 { 251 int oldpage, ret = 0; 252 253 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 254 if (oldpage >= 0) { 255 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 256 if (ret == 0) 257 ret = __phy_modify(phydev, regnum, mask, set); 258 } 259 260 return phy_restore_page(phydev, oldpage, ret); 261 } 262 263 static int rtl821x_probe(struct phy_device *phydev) 264 { 265 struct device *dev = &phydev->mdio.dev; 266 struct rtl821x_priv *priv; 267 268 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 269 if (!priv) 270 return -ENOMEM; 271 272 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 273 if (IS_ERR(priv->clk)) 274 return dev_err_probe(dev, PTR_ERR(priv->clk), 275 "failed to get phy clock\n"); 276 277 priv->enable_aldps = of_property_read_bool(dev->of_node, 278 "realtek,aldps-enable"); 279 priv->disable_clk_out = of_property_read_bool(dev->of_node, 280 "realtek,clkout-disable"); 281 282 phydev->priv = priv; 283 284 return 0; 285 } 286 287 static int rtl8211f_probe(struct phy_device *phydev) 288 { 289 struct device *dev = &phydev->mdio.dev; 290 int ret; 291 292 ret = rtl821x_probe(phydev); 293 if (ret < 0) 294 return ret; 295 296 /* Disable all PME events */ 297 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 298 RTL8211F_WOL_SETTINGS_EVENTS, 0); 299 if (ret < 0) 300 return ret; 301 302 /* Mark this PHY as wakeup capable and register the interrupt as a 303 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 304 * and the interrupt is valid. 305 */ 306 if (device_property_read_bool(dev, "wakeup-source") && 307 phy_interrupt_is_valid(phydev)) { 308 device_set_wakeup_capable(dev, true); 309 devm_pm_set_wake_irq(dev, phydev->irq); 310 } 311 312 return ret; 313 } 314 315 static int rtl8201_ack_interrupt(struct phy_device *phydev) 316 { 317 int err; 318 319 err = phy_read(phydev, RTL8201F_ISR); 320 321 return (err < 0) ? err : 0; 322 } 323 324 static int rtl821x_ack_interrupt(struct phy_device *phydev) 325 { 326 int err; 327 328 err = phy_read(phydev, RTL821x_INSR); 329 330 return (err < 0) ? err : 0; 331 } 332 333 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 334 { 335 int err; 336 337 err = phy_read(phydev, RTL8211F_INSR); 338 339 return (err < 0) ? err : 0; 340 } 341 342 static int rtl8201_config_intr(struct phy_device *phydev) 343 { 344 u16 val; 345 int err; 346 347 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 348 err = rtl8201_ack_interrupt(phydev); 349 if (err) 350 return err; 351 352 val = BIT(13) | BIT(12) | BIT(11); 353 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 354 } else { 355 val = 0; 356 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 357 if (err) 358 return err; 359 360 err = rtl8201_ack_interrupt(phydev); 361 } 362 363 return err; 364 } 365 366 static int rtl8211b_config_intr(struct phy_device *phydev) 367 { 368 int err; 369 370 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 371 err = rtl821x_ack_interrupt(phydev); 372 if (err) 373 return err; 374 375 err = phy_write(phydev, RTL821x_INER, 376 RTL8211B_INER_INIT); 377 } else { 378 err = phy_write(phydev, RTL821x_INER, 0); 379 if (err) 380 return err; 381 382 err = rtl821x_ack_interrupt(phydev); 383 } 384 385 return err; 386 } 387 388 static int rtl8211e_config_intr(struct phy_device *phydev) 389 { 390 int err; 391 392 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 393 err = rtl821x_ack_interrupt(phydev); 394 if (err) 395 return err; 396 397 err = phy_write(phydev, RTL821x_INER, 398 RTL8211E_INER_LINK_STATUS); 399 } else { 400 err = phy_write(phydev, RTL821x_INER, 0); 401 if (err) 402 return err; 403 404 err = rtl821x_ack_interrupt(phydev); 405 } 406 407 return err; 408 } 409 410 static int rtl8211f_config_intr(struct phy_device *phydev) 411 { 412 struct rtl821x_priv *priv = phydev->priv; 413 u16 val; 414 int err; 415 416 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 417 err = rtl8211f_ack_interrupt(phydev); 418 if (err) 419 return err; 420 421 val = RTL8211F_INER_LINK_STATUS; 422 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 423 if (err == 0) 424 priv->iner = val; 425 } else { 426 priv->iner = val = 0; 427 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 428 if (err) 429 return err; 430 431 err = rtl8211f_ack_interrupt(phydev); 432 } 433 434 return err; 435 } 436 437 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 438 { 439 int irq_status; 440 441 irq_status = phy_read(phydev, RTL8201F_ISR); 442 if (irq_status < 0) { 443 phy_error(phydev); 444 return IRQ_NONE; 445 } 446 447 if (!(irq_status & RTL8201F_ISR_MASK)) 448 return IRQ_NONE; 449 450 phy_trigger_machine(phydev); 451 452 return IRQ_HANDLED; 453 } 454 455 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 456 { 457 int irq_status, irq_enabled; 458 459 irq_status = phy_read(phydev, RTL821x_INSR); 460 if (irq_status < 0) { 461 phy_error(phydev); 462 return IRQ_NONE; 463 } 464 465 irq_enabled = phy_read(phydev, RTL821x_INER); 466 if (irq_enabled < 0) { 467 phy_error(phydev); 468 return IRQ_NONE; 469 } 470 471 if (!(irq_status & irq_enabled)) 472 return IRQ_NONE; 473 474 phy_trigger_machine(phydev); 475 476 return IRQ_HANDLED; 477 } 478 479 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 480 { 481 int irq_status; 482 483 irq_status = phy_read(phydev, RTL8211F_INSR); 484 if (irq_status < 0) { 485 phy_error(phydev); 486 return IRQ_NONE; 487 } 488 489 if (irq_status & RTL8211F_INER_LINK_STATUS) { 490 phy_trigger_machine(phydev); 491 return IRQ_HANDLED; 492 } 493 494 if (irq_status & RTL8211F_INER_PME) { 495 pm_wakeup_event(&phydev->mdio.dev, 0); 496 return IRQ_HANDLED; 497 } 498 499 return IRQ_NONE; 500 } 501 502 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 503 { 504 int wol_events; 505 506 /* If the PHY is not capable of waking the system, then WoL can not 507 * be supported. 508 */ 509 if (!device_can_wakeup(&dev->mdio.dev)) { 510 wol->supported = 0; 511 return; 512 } 513 514 wol->supported = WAKE_MAGIC; 515 516 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 517 if (wol_events < 0) 518 return; 519 520 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 521 wol->wolopts = WAKE_MAGIC; 522 } 523 524 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 525 { 526 const u8 *mac_addr = dev->attached_dev->dev_addr; 527 int oldpage; 528 529 if (!device_can_wakeup(&dev->mdio.dev)) 530 return -EOPNOTSUPP; 531 532 oldpage = phy_save_page(dev); 533 if (oldpage < 0) 534 goto err; 535 536 if (wol->wolopts & WAKE_MAGIC) { 537 /* Store the device address for the magic packet */ 538 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 539 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 540 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 541 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 542 543 /* Enable magic packet matching */ 544 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 545 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 546 /* Set the maximum packet size, and assert WoL reset */ 547 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 548 } else { 549 /* Disable magic packet matching */ 550 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 551 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 552 553 /* Place WoL in reset */ 554 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 555 RTL8211F_WOL_RG_RSTB); 556 } 557 558 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 559 560 err: 561 return phy_restore_page(dev, oldpage, 0); 562 } 563 564 static int rtl8211_config_aneg(struct phy_device *phydev) 565 { 566 int ret; 567 568 ret = genphy_config_aneg(phydev); 569 if (ret < 0) 570 return ret; 571 572 /* Quirk was copied from vendor driver. Unfortunately it includes no 573 * description of the magic numbers. 574 */ 575 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 576 phy_write(phydev, 0x17, 0x2138); 577 phy_write(phydev, 0x0e, 0x0260); 578 } else { 579 phy_write(phydev, 0x17, 0x2108); 580 phy_write(phydev, 0x0e, 0x0000); 581 } 582 583 return 0; 584 } 585 586 static int rtl8211c_config_init(struct phy_device *phydev) 587 { 588 /* RTL8211C has an issue when operating in Gigabit slave mode */ 589 return phy_set_bits(phydev, MII_CTRL1000, 590 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 591 } 592 593 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 594 { 595 u16 val_txdly, val_rxdly; 596 int ret; 597 598 switch (phydev->interface) { 599 case PHY_INTERFACE_MODE_RGMII: 600 val_txdly = 0; 601 val_rxdly = 0; 602 break; 603 604 case PHY_INTERFACE_MODE_RGMII_RXID: 605 val_txdly = 0; 606 val_rxdly = RTL8211F_RX_DELAY; 607 break; 608 609 case PHY_INTERFACE_MODE_RGMII_TXID: 610 val_txdly = RTL8211F_TX_DELAY; 611 val_rxdly = 0; 612 break; 613 614 case PHY_INTERFACE_MODE_RGMII_ID: 615 val_txdly = RTL8211F_TX_DELAY; 616 val_rxdly = RTL8211F_RX_DELAY; 617 break; 618 619 default: /* the rest of the modes imply leaving delay as is. */ 620 return 0; 621 } 622 623 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 624 RTL8211F_TXCR, RTL8211F_TX_DELAY, 625 val_txdly); 626 if (ret < 0) { 627 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 628 ERR_PTR(ret)); 629 return ret; 630 } else if (ret) { 631 phydev_dbg(phydev, 632 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 633 str_enable_disable(val_txdly)); 634 } else { 635 phydev_dbg(phydev, 636 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 637 str_enabled_disabled(val_txdly)); 638 } 639 640 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 641 RTL8211F_RXCR, RTL8211F_RX_DELAY, 642 val_rxdly); 643 if (ret < 0) { 644 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 645 ERR_PTR(ret)); 646 return ret; 647 } else if (ret) { 648 phydev_dbg(phydev, 649 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 650 str_enable_disable(val_rxdly)); 651 } else { 652 phydev_dbg(phydev, 653 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 654 str_enabled_disabled(val_rxdly)); 655 } 656 657 return 0; 658 } 659 660 static int rtl8211f_config_clk_out(struct phy_device *phydev) 661 { 662 struct rtl821x_priv *priv = phydev->priv; 663 int ret; 664 665 /* The value is preserved if the device tree property is absent */ 666 if (!priv->disable_clk_out) 667 return 0; 668 669 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 670 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 671 RTL8211FVD_CLKOUT_REG, 672 RTL8211FVD_CLKOUT_EN, 0); 673 else 674 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 675 0); 676 if (ret) 677 return ret; 678 679 return genphy_soft_reset(phydev); 680 } 681 682 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 683 * which causes the RXC clock signal to stop for tens to hundreds of 684 * milliseconds. 685 * 686 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 687 * only enabled based on an opt-in device tree property. 688 */ 689 static int rtl8211f_config_aldps(struct phy_device *phydev) 690 { 691 struct rtl821x_priv *priv = phydev->priv; 692 u16 mask = RTL8211F_ALDPS_PLL_OFF | 693 RTL8211F_ALDPS_ENABLE | 694 RTL8211F_ALDPS_XTAL_OFF; 695 696 /* The value is preserved if the device tree property is absent */ 697 if (!priv->enable_aldps) 698 return 0; 699 700 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 701 } 702 703 static int rtl8211f_config_phy_eee(struct phy_device *phydev) 704 { 705 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 706 return phy_modify(phydev, RTL8211F_PHYCR2, 707 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 708 } 709 710 static int rtl8211f_config_init(struct phy_device *phydev) 711 { 712 struct device *dev = &phydev->mdio.dev; 713 int ret; 714 715 ret = rtl8211f_config_aldps(phydev); 716 if (ret) { 717 dev_err(dev, "aldps mode configuration failed: %pe\n", 718 ERR_PTR(ret)); 719 return ret; 720 } 721 722 ret = rtl8211f_config_rgmii_delay(phydev); 723 if (ret) 724 return ret; 725 726 ret = rtl8211f_config_clk_out(phydev); 727 if (ret) { 728 dev_err(dev, "clkout configuration failed: %pe\n", 729 ERR_PTR(ret)); 730 return ret; 731 } 732 733 return rtl8211f_config_phy_eee(phydev); 734 } 735 736 static int rtl821x_suspend(struct phy_device *phydev) 737 { 738 struct rtl821x_priv *priv = phydev->priv; 739 int ret = 0; 740 741 if (!phydev->wol_enabled) { 742 ret = genphy_suspend(phydev); 743 744 if (ret) 745 return ret; 746 747 clk_disable_unprepare(priv->clk); 748 } 749 750 return ret; 751 } 752 753 static int rtl8211f_suspend(struct phy_device *phydev) 754 { 755 u16 wol_rst; 756 int ret; 757 758 ret = rtl821x_suspend(phydev); 759 if (ret < 0) 760 return ret; 761 762 /* If a PME event is enabled, then configure the interrupt for 763 * PME events only, disabling link interrupt. We avoid switching 764 * to PMEB mode as we don't have a status bit for that. 765 */ 766 if (device_may_wakeup(&phydev->mdio.dev)) { 767 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 768 RTL8211F_INER_PME); 769 if (ret < 0) 770 goto err; 771 772 /* Read the INSR to clear any pending interrupt */ 773 phy_read(phydev, RTL8211F_INSR); 774 775 /* Reset the WoL to ensure that an event is picked up. 776 * Unless we do this, even if we receive another packet, 777 * we may not have a PME interrupt raised. 778 */ 779 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 780 RTL8211F_WOL_RST_RMSQ); 781 if (ret < 0) 782 goto err; 783 784 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 785 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 786 RTL8211F_WOL_RST_RMSQ, wol_rst); 787 if (ret < 0) 788 goto err; 789 790 wol_rst |= RTL8211F_WOL_RG_RSTB; 791 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 792 RTL8211F_WOL_RST_RMSQ, wol_rst); 793 } 794 795 err: 796 return ret; 797 } 798 799 static int rtl821x_resume(struct phy_device *phydev) 800 { 801 struct rtl821x_priv *priv = phydev->priv; 802 int ret; 803 804 if (!phydev->wol_enabled) 805 clk_prepare_enable(priv->clk); 806 807 ret = genphy_resume(phydev); 808 if (ret < 0) 809 return ret; 810 811 msleep(20); 812 813 return 0; 814 } 815 816 static int rtl8211f_resume(struct phy_device *phydev) 817 { 818 struct rtl821x_priv *priv = phydev->priv; 819 int ret; 820 821 ret = rtl821x_resume(phydev); 822 if (ret < 0) 823 return ret; 824 825 /* If the device was programmed for a PME event, restore the interrupt 826 * enable so phylib can receive link state interrupts. 827 */ 828 if (device_may_wakeup(&phydev->mdio.dev)) 829 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 830 831 return ret; 832 } 833 834 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 835 unsigned long rules) 836 { 837 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 838 BIT(TRIGGER_NETDEV_LINK_10) | 839 BIT(TRIGGER_NETDEV_LINK_100) | 840 BIT(TRIGGER_NETDEV_LINK_1000) | 841 BIT(TRIGGER_NETDEV_RX) | 842 BIT(TRIGGER_NETDEV_TX); 843 844 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 845 * - Link: Configurable subset of 10/100/1000 link rates 846 * - Active: Blink on activity, RX or TX is not differentiated 847 * The Active option has two modes, A and B: 848 * - A: Link and Active indication at configurable, but matching, 849 * subset of 10/100/1000 link rates 850 * - B: Link indication at configurable subset of 10/100/1000 link 851 * rates and Active indication always at all three 10+100+1000 852 * link rates. 853 * This code currently uses mode B only. 854 * 855 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 856 */ 857 858 if (index >= RTL8211x_LED_COUNT) 859 return -EINVAL; 860 861 /* Filter out any other unsupported triggers. */ 862 if (rules & ~mask) 863 return -EOPNOTSUPP; 864 865 /* RX and TX are not differentiated, either both are set or not set. */ 866 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 867 return -EOPNOTSUPP; 868 869 return 0; 870 } 871 872 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 873 unsigned long *rules) 874 { 875 int val; 876 877 if (index >= RTL8211x_LED_COUNT) 878 return -EINVAL; 879 880 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 881 if (val < 0) 882 return val; 883 884 val >>= RTL8211F_LEDCR_SHIFT * index; 885 val &= RTL8211F_LEDCR_MASK; 886 887 if (val & RTL8211F_LEDCR_LINK_10) 888 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 889 890 if (val & RTL8211F_LEDCR_LINK_100) 891 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 892 893 if (val & RTL8211F_LEDCR_LINK_1000) 894 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 895 896 if ((val & RTL8211F_LEDCR_LINK_10) && 897 (val & RTL8211F_LEDCR_LINK_100) && 898 (val & RTL8211F_LEDCR_LINK_1000)) { 899 __set_bit(TRIGGER_NETDEV_LINK, rules); 900 } 901 902 if (val & RTL8211F_LEDCR_ACT_TXRX) { 903 __set_bit(TRIGGER_NETDEV_RX, rules); 904 __set_bit(TRIGGER_NETDEV_TX, rules); 905 } 906 907 return 0; 908 } 909 910 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 911 unsigned long rules) 912 { 913 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 914 u16 reg = 0; 915 916 if (index >= RTL8211x_LED_COUNT) 917 return -EINVAL; 918 919 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 920 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 921 reg |= RTL8211F_LEDCR_LINK_10; 922 } 923 924 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 925 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 926 reg |= RTL8211F_LEDCR_LINK_100; 927 } 928 929 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 930 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 931 reg |= RTL8211F_LEDCR_LINK_1000; 932 } 933 934 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 935 test_bit(TRIGGER_NETDEV_TX, &rules)) { 936 reg |= RTL8211F_LEDCR_ACT_TXRX; 937 } 938 939 reg <<= RTL8211F_LEDCR_SHIFT * index; 940 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 941 942 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 943 } 944 945 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 946 unsigned long *rules) 947 { 948 int ret; 949 u16 cr1, cr2; 950 951 if (index >= RTL8211x_LED_COUNT) 952 return -EINVAL; 953 954 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 955 RTL8211E_LEDCR1); 956 if (ret < 0) 957 return ret; 958 959 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 960 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 961 __set_bit(TRIGGER_NETDEV_RX, rules); 962 __set_bit(TRIGGER_NETDEV_TX, rules); 963 } 964 965 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 966 RTL8211E_LEDCR2); 967 if (ret < 0) 968 return ret; 969 970 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 971 if (cr2 & RTL8211E_LEDCR2_LINK_10) 972 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 973 974 if (cr2 & RTL8211E_LEDCR2_LINK_100) 975 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 976 977 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 978 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 979 980 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 981 (cr2 & RTL8211E_LEDCR2_LINK_100) && 982 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 983 __set_bit(TRIGGER_NETDEV_LINK, rules); 984 } 985 986 return ret; 987 } 988 989 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 990 unsigned long rules) 991 { 992 const u16 cr1mask = 993 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 994 const u16 cr2mask = 995 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 996 u16 cr1 = 0, cr2 = 0; 997 int ret; 998 999 if (index >= RTL8211x_LED_COUNT) 1000 return -EINVAL; 1001 1002 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1003 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1004 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1005 } 1006 1007 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1008 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1009 RTL8211E_LEDCR1, cr1mask, cr1); 1010 if (ret < 0) 1011 return ret; 1012 1013 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1014 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1015 cr2 |= RTL8211E_LEDCR2_LINK_10; 1016 } 1017 1018 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1019 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1020 cr2 |= RTL8211E_LEDCR2_LINK_100; 1021 } 1022 1023 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1024 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1025 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1026 } 1027 1028 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1029 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1030 RTL8211E_LEDCR2, cr2mask, cr2); 1031 1032 return ret; 1033 } 1034 1035 static int rtl8211e_config_init(struct phy_device *phydev) 1036 { 1037 u16 val; 1038 1039 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1040 switch (phydev->interface) { 1041 case PHY_INTERFACE_MODE_RGMII: 1042 val = RTL8211E_CTRL_DELAY | 0; 1043 break; 1044 case PHY_INTERFACE_MODE_RGMII_ID: 1045 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1046 break; 1047 case PHY_INTERFACE_MODE_RGMII_RXID: 1048 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1049 break; 1050 case PHY_INTERFACE_MODE_RGMII_TXID: 1051 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1052 break; 1053 default: /* the rest of the modes imply leaving delays as is. */ 1054 return 0; 1055 } 1056 1057 /* According to a sample driver there is a 0x1c config register on the 1058 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1059 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1060 * The configuration register definition: 1061 * 14 = reserved 1062 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1063 * 12 = RX Delay, 11 = TX Delay 1064 * 10:0 = Test && debug settings reserved by realtek 1065 */ 1066 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1067 RTL8211E_RGMII_DELAY, 1068 RTL8211E_DELAY_MASK, val); 1069 } 1070 1071 static int rtl8211b_suspend(struct phy_device *phydev) 1072 { 1073 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1074 1075 return genphy_suspend(phydev); 1076 } 1077 1078 static int rtl8211b_resume(struct phy_device *phydev) 1079 { 1080 phy_write(phydev, MII_MMD_DATA, 0); 1081 1082 return genphy_resume(phydev); 1083 } 1084 1085 static int rtl8366rb_config_init(struct phy_device *phydev) 1086 { 1087 int ret; 1088 1089 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1090 RTL8366RB_POWER_SAVE_ON); 1091 if (ret) { 1092 dev_err(&phydev->mdio.dev, 1093 "error enabling power management\n"); 1094 } 1095 1096 return ret; 1097 } 1098 1099 /* get actual speed to cover the downshift case */ 1100 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1101 { 1102 /* bit 3 1103 * 0: Half Duplex 1104 * 1: Full Duplex 1105 */ 1106 if (val & RTL_PHYSR_DUPLEX) 1107 phydev->duplex = DUPLEX_FULL; 1108 else 1109 phydev->duplex = DUPLEX_HALF; 1110 1111 switch (val & RTL_PHYSR_SPEED_MASK) { 1112 case 0x0000: 1113 phydev->speed = SPEED_10; 1114 break; 1115 case 0x0010: 1116 phydev->speed = SPEED_100; 1117 break; 1118 case 0x0020: 1119 phydev->speed = SPEED_1000; 1120 break; 1121 case 0x0200: 1122 phydev->speed = SPEED_10000; 1123 break; 1124 case 0x0210: 1125 phydev->speed = SPEED_2500; 1126 break; 1127 case 0x0220: 1128 phydev->speed = SPEED_5000; 1129 break; 1130 default: 1131 break; 1132 } 1133 1134 /* bit 11 1135 * 0: Slave Mode 1136 * 1: Master Mode 1137 */ 1138 if (phydev->speed >= 1000) { 1139 if (val & RTL_PHYSR_MASTER) 1140 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1141 else 1142 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1143 } else { 1144 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1145 } 1146 } 1147 1148 static int rtlgen_read_status(struct phy_device *phydev) 1149 { 1150 int ret, val; 1151 1152 ret = genphy_read_status(phydev); 1153 if (ret < 0) 1154 return ret; 1155 1156 if (!phydev->link) 1157 return 0; 1158 1159 val = phy_read(phydev, RTL_PHYSR); 1160 if (val < 0) 1161 return val; 1162 1163 rtlgen_decode_physr(phydev, val); 1164 1165 return 0; 1166 } 1167 1168 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1169 { 1170 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1171 } 1172 1173 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1174 { 1175 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1176 val); 1177 } 1178 1179 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1180 { 1181 int ret; 1182 1183 if (devnum == MDIO_MMD_VEND2) 1184 ret = rtlgen_read_vend2(phydev, regnum); 1185 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1186 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1187 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1188 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1189 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1190 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1191 else 1192 ret = -EOPNOTSUPP; 1193 1194 return ret; 1195 } 1196 1197 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1198 u16 val) 1199 { 1200 int ret; 1201 1202 if (devnum == MDIO_MMD_VEND2) 1203 ret = rtlgen_write_vend2(phydev, regnum, val); 1204 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1205 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1206 else 1207 ret = -EOPNOTSUPP; 1208 1209 return ret; 1210 } 1211 1212 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1213 { 1214 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1215 1216 if (ret != -EOPNOTSUPP) 1217 return ret; 1218 1219 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1220 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1221 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1222 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1223 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1224 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1225 1226 return ret; 1227 } 1228 1229 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1230 u16 val) 1231 { 1232 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1233 1234 if (ret != -EOPNOTSUPP) 1235 return ret; 1236 1237 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1238 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1239 1240 return ret; 1241 } 1242 1243 static int rtl822x_probe(struct phy_device *phydev) 1244 { 1245 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1246 phydev->phy_id != RTL_GENERIC_PHYID) 1247 return rtl822x_hwmon_init(phydev); 1248 1249 return 0; 1250 } 1251 1252 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1253 * A mapping to use paged access needs to be used instead. 1254 * All other MMD devices can be accessed as usual. 1255 */ 1256 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1257 { 1258 int oldpage, ret, read_ret; 1259 u16 page; 1260 1261 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1262 * Clause-45 access is available 1263 */ 1264 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1265 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1266 phydev->is_c45, devnum, reg); 1267 1268 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1269 if (reg >= RTL822X_VND2_C22_REG(0) && 1270 reg <= RTL822X_VND2_C22_REG(30)) 1271 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1272 1273 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1274 page = RTL822X_VND2_TO_PAGE(reg); 1275 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1276 if (oldpage < 0) 1277 return oldpage; 1278 1279 if (oldpage != page) { 1280 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1281 if (ret < 0) 1282 return ret; 1283 } 1284 1285 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1286 if (oldpage != page) { 1287 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1288 if (ret < 0) 1289 return ret; 1290 } 1291 1292 return read_ret; 1293 } 1294 1295 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1296 u16 val) 1297 { 1298 int oldpage, ret, write_ret; 1299 u16 page; 1300 1301 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1302 * Clause-45 access is available 1303 */ 1304 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1305 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1306 phydev->is_c45, devnum, reg, val); 1307 1308 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1309 if (reg >= RTL822X_VND2_C22_REG(0) && 1310 reg <= RTL822X_VND2_C22_REG(30)) 1311 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1312 1313 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1314 page = RTL822X_VND2_TO_PAGE(reg); 1315 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1316 if (oldpage < 0) 1317 return oldpage; 1318 1319 if (oldpage != page) { 1320 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1321 if (ret < 0) 1322 return ret; 1323 } 1324 1325 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1326 if (oldpage != page) { 1327 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1328 if (ret < 0) 1329 return ret; 1330 } 1331 1332 return write_ret; 1333 } 1334 1335 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1336 { 1337 bool has_2500, has_sgmii; 1338 u16 mode; 1339 int ret; 1340 1341 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1342 phydev->host_interfaces) || 1343 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1344 1345 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1346 phydev->host_interfaces) || 1347 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1348 1349 /* fill in possible interfaces */ 1350 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1351 has_2500); 1352 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1353 has_sgmii); 1354 1355 if (!has_2500 && !has_sgmii) 1356 return 0; 1357 1358 /* determine SerDes option mode */ 1359 if (has_2500 && !has_sgmii) { 1360 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1361 phydev->rate_matching = RATE_MATCH_PAUSE; 1362 } else { 1363 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1364 phydev->rate_matching = RATE_MATCH_NONE; 1365 } 1366 1367 /* the following sequence with magic numbers sets up the SerDes 1368 * option mode 1369 */ 1370 1371 if (!gen1) { 1372 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1373 if (ret < 0) 1374 return ret; 1375 } 1376 1377 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1378 RTL822X_VND1_SERDES_OPTION, 1379 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1380 mode); 1381 if (gen1 || ret < 0) 1382 return ret; 1383 1384 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1385 if (ret < 0) 1386 return ret; 1387 1388 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1389 if (ret < 0) 1390 return ret; 1391 1392 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1393 } 1394 1395 static int rtl822x_config_init(struct phy_device *phydev) 1396 { 1397 return rtl822x_set_serdes_option_mode(phydev, true); 1398 } 1399 1400 static int rtl822xb_config_init(struct phy_device *phydev) 1401 { 1402 return rtl822x_set_serdes_option_mode(phydev, false); 1403 } 1404 1405 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1406 { 1407 int ret, poll; 1408 1409 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1410 if (ret < 0) 1411 return ret; 1412 1413 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1414 if (ret < 0) 1415 return ret; 1416 1417 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1418 RTL822X_VND1_SERDES_CMD_WRITE | 1419 RTL822X_VND1_SERDES_CMD_BUSY); 1420 if (ret < 0) 1421 return ret; 1422 1423 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1424 RTL822X_VND1_SERDES_CMD, poll, 1425 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1426 500, 100000, false); 1427 } 1428 1429 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1430 { 1431 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1432 (modes != LINK_INBAND_DISABLE) ? 1433 RTL822X_VND1_SERDES_INBAND_ENABLE : 1434 RTL822X_VND1_SERDES_INBAND_DISABLE); 1435 } 1436 1437 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1438 phy_interface_t interface) 1439 { 1440 switch (interface) { 1441 case PHY_INTERFACE_MODE_2500BASEX: 1442 return LINK_INBAND_DISABLE; 1443 case PHY_INTERFACE_MODE_SGMII: 1444 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1445 default: 1446 return 0; 1447 } 1448 } 1449 1450 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1451 phy_interface_t iface) 1452 { 1453 int val; 1454 1455 /* Only rate matching at 2500base-x */ 1456 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1457 return RATE_MATCH_NONE; 1458 1459 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1460 if (val < 0) 1461 return val; 1462 1463 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1464 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1465 return RATE_MATCH_PAUSE; 1466 1467 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1468 return RATE_MATCH_NONE; 1469 } 1470 1471 static int rtl822x_get_features(struct phy_device *phydev) 1472 { 1473 int val; 1474 1475 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1476 if (val < 0) 1477 return val; 1478 1479 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1480 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1481 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1482 phydev->supported, val & MDIO_PMA_SPEED_5G); 1483 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1484 phydev->supported, val & MDIO_SPEED_10G); 1485 1486 return genphy_read_abilities(phydev); 1487 } 1488 1489 static int rtl822x_config_aneg(struct phy_device *phydev) 1490 { 1491 int ret = 0; 1492 1493 if (phydev->autoneg == AUTONEG_ENABLE) { 1494 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1495 1496 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1497 RTL_MDIO_AN_10GBT_CTRL, 1498 MDIO_AN_10GBT_CTRL_ADV2_5G | 1499 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1500 if (ret < 0) 1501 return ret; 1502 } 1503 1504 return __genphy_config_aneg(phydev, ret); 1505 } 1506 1507 static void rtl822xb_update_interface(struct phy_device *phydev) 1508 { 1509 int val; 1510 1511 if (!phydev->link) 1512 return; 1513 1514 /* Change interface according to serdes mode */ 1515 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1516 if (val < 0) 1517 return; 1518 1519 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1520 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1521 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1522 break; 1523 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1524 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1525 break; 1526 } 1527 } 1528 1529 static int rtl822x_read_status(struct phy_device *phydev) 1530 { 1531 int lpadv, ret; 1532 1533 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1534 1535 ret = rtlgen_read_status(phydev); 1536 if (ret < 0) 1537 return ret; 1538 1539 if (phydev->autoneg == AUTONEG_DISABLE || 1540 !phydev->autoneg_complete) 1541 return 0; 1542 1543 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1544 if (lpadv < 0) 1545 return lpadv; 1546 1547 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1548 1549 return 0; 1550 } 1551 1552 static int rtl822xb_read_status(struct phy_device *phydev) 1553 { 1554 int ret; 1555 1556 ret = rtl822x_read_status(phydev); 1557 if (ret < 0) 1558 return ret; 1559 1560 rtl822xb_update_interface(phydev); 1561 1562 return 0; 1563 } 1564 1565 static int rtl822x_c45_get_features(struct phy_device *phydev) 1566 { 1567 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1568 phydev->supported); 1569 1570 return genphy_c45_pma_read_abilities(phydev); 1571 } 1572 1573 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1574 { 1575 bool changed = false; 1576 int ret, val; 1577 1578 if (phydev->autoneg == AUTONEG_DISABLE) 1579 return genphy_c45_pma_setup_forced(phydev); 1580 1581 ret = genphy_c45_an_config_aneg(phydev); 1582 if (ret < 0) 1583 return ret; 1584 if (ret > 0) 1585 changed = true; 1586 1587 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1588 1589 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1590 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1591 RTL822X_VND2_C22_REG(MII_CTRL1000), 1592 ADVERTISE_1000FULL, val); 1593 if (ret < 0) 1594 return ret; 1595 if (ret > 0) 1596 changed = true; 1597 1598 return genphy_c45_check_and_restart_aneg(phydev, changed); 1599 } 1600 1601 static int rtl822x_c45_read_status(struct phy_device *phydev) 1602 { 1603 int ret, val; 1604 1605 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1606 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1607 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1608 RTL822X_VND2_C22_REG(MII_STAT1000)); 1609 if (val < 0) 1610 return val; 1611 } else { 1612 val = 0; 1613 } 1614 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1615 1616 ret = genphy_c45_read_status(phydev); 1617 if (ret < 0) 1618 return ret; 1619 1620 if (!phydev->link) { 1621 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1622 return 0; 1623 } 1624 1625 /* Read actual speed from vendor register. */ 1626 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1627 RTL822X_VND2_C22_REG(RTL_PHYSR)); 1628 if (val < 0) 1629 return val; 1630 1631 rtlgen_decode_physr(phydev, val); 1632 1633 return 0; 1634 } 1635 1636 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1637 { 1638 int ret, val; 1639 1640 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1641 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1642 if (ret < 0) 1643 return ret; 1644 1645 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1646 MDIO_CTRL1, val, 1647 !(val & MDIO_CTRL1_RESET), 1648 5000, 100000, true); 1649 } 1650 1651 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1652 { 1653 int ret; 1654 1655 ret = rtl822x_c45_read_status(phydev); 1656 if (ret < 0) 1657 return ret; 1658 1659 rtl822xb_update_interface(phydev); 1660 1661 return 0; 1662 } 1663 1664 static int rtl8224_cable_test_start(struct phy_device *phydev) 1665 { 1666 u32 val; 1667 int ret; 1668 1669 /* disable auto-negotiation and force 1000/Full */ 1670 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1671 RTL822X_VND2_C22_REG(MII_BMCR), 1672 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1673 BMCR_SPEED1000 | BMCR_FULLDPLX); 1674 if (ret) 1675 return ret; 1676 1677 mdelay(500); 1678 1679 /* trigger cable test */ 1680 val = RTL8224_MII_RTCT_ENABLE; 1681 val |= RTL8224_MII_RTCT_PAIR_A; 1682 val |= RTL8224_MII_RTCT_PAIR_B; 1683 val |= RTL8224_MII_RTCT_PAIR_C; 1684 val |= RTL8224_MII_RTCT_PAIR_D; 1685 1686 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1687 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1688 RTL8224_MII_RTCT_DONE, val); 1689 } 1690 1691 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1692 { 1693 int ret; 1694 1695 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1696 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1697 reg); 1698 if (ret) 1699 return ret; 1700 1701 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1702 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1703 } 1704 1705 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1706 { 1707 int cable_len; 1708 u32 reg_len; 1709 int ret; 1710 u32 cm; 1711 1712 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1713 1714 ret = rtl8224_sram_read(phydev, reg_len); 1715 if (ret < 0) 1716 return ret; 1717 1718 cable_len = ret & 0xff00; 1719 1720 ret = rtl8224_sram_read(phydev, reg_len + 1); 1721 if (ret < 0) 1722 return ret; 1723 1724 cable_len |= (ret & 0xff00) >> 8; 1725 1726 cable_len -= 620; 1727 cable_len = max(cable_len, 0); 1728 1729 cm = cable_len * 100 / 78; 1730 1731 return cm; 1732 } 1733 1734 static int rtl8224_cable_test_result_trans(u32 result) 1735 { 1736 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1737 return -EBUSY; 1738 1739 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1740 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1741 1742 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1743 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1744 1745 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1746 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1747 1748 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1749 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1750 1751 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1752 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1753 1754 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1755 } 1756 1757 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1758 { 1759 int fault_rslt; 1760 int ret; 1761 1762 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1763 if (ret < 0) 1764 return ret; 1765 1766 fault_rslt = rtl8224_cable_test_result_trans(ret); 1767 if (fault_rslt < 0) 1768 return 0; 1769 1770 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1771 if (ret < 0) 1772 return ret; 1773 1774 switch (fault_rslt) { 1775 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1776 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1777 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1778 ret = rtl8224_pair_len_get(phydev, pair); 1779 if (ret < 0) 1780 return ret; 1781 1782 return ethnl_cable_test_fault_length(phydev, pair, ret); 1783 default: 1784 return 0; 1785 } 1786 } 1787 1788 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1789 { 1790 unsigned int pair; 1791 int ret; 1792 1793 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1794 ret = rtl8224_cable_test_report_pair(phydev, pair); 1795 if (ret == -EBUSY) { 1796 *finished = false; 1797 return 0; 1798 } 1799 1800 if (ret < 0) 1801 return ret; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1808 { 1809 int ret; 1810 1811 *finished = false; 1812 1813 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1814 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1815 if (ret < 0) 1816 return ret; 1817 1818 if (!(ret & RTL8224_MII_RTCT_DONE)) 1819 return 0; 1820 1821 *finished = true; 1822 1823 return rtl8224_cable_test_report(phydev, finished); 1824 } 1825 1826 static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, 1827 u32 regnum, u16 mask, u16 set) 1828 { 1829 int val, ret; 1830 1831 phy_lock_mdio_bus(phydev); 1832 1833 val = __phy_package_read_mmd(phydev, 0, devad, regnum); 1834 if (val < 0) { 1835 ret = val; 1836 goto exit; 1837 } 1838 1839 val &= ~mask; 1840 val |= set; 1841 1842 ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); 1843 1844 exit: 1845 phy_unlock_mdio_bus(phydev); 1846 return ret; 1847 } 1848 1849 static int rtl8224_mdi_config_order(struct phy_device *phydev) 1850 { 1851 struct device_node *np = phydev->mdio.dev.of_node; 1852 u8 port_offset = phydev->mdio.addr & 3; 1853 u32 order = 0; 1854 int ret; 1855 1856 ret = of_property_read_u32(np, "enet-phy-pair-order", &order); 1857 1858 /* Do nothing in case the property is not present */ 1859 if (ret == -EINVAL || ret == -ENOSYS) 1860 return 0; 1861 1862 if (ret) 1863 return ret; 1864 1865 if (order & ~1) 1866 return -EINVAL; 1867 1868 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 1869 RTL8224_VND1_MDI_PAIR_SWAP, 1870 BIT(port_offset), 1871 order ? BIT(port_offset) : 0); 1872 } 1873 1874 static int rtl8224_mdi_config_polarity(struct phy_device *phydev) 1875 { 1876 struct device_node *np = phydev->mdio.dev.of_node; 1877 u8 offset = (phydev->mdio.addr & 3) * 4; 1878 u32 polarity = 0; 1879 int ret; 1880 1881 ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity); 1882 1883 /* Do nothing if the property is not present */ 1884 if (ret == -EINVAL || ret == -ENOSYS) 1885 return 0; 1886 1887 if (ret) 1888 return ret; 1889 1890 if (polarity & ~0xf) 1891 return -EINVAL; 1892 1893 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 1894 RTL8224_VND1_MDI_POLARITY_SWAP, 1895 0xf << offset, 1896 polarity << offset); 1897 } 1898 1899 static int rtl8224_config_init(struct phy_device *phydev) 1900 { 1901 int ret; 1902 1903 ret = rtl8224_mdi_config_order(phydev); 1904 if (ret) 1905 return ret; 1906 1907 return rtl8224_mdi_config_polarity(phydev); 1908 } 1909 1910 static int rtl8224_probe(struct phy_device *phydev) 1911 { 1912 /* Chip exposes 4 ports, join all of them in the same package */ 1913 return devm_phy_package_join(&phydev->mdio.dev, phydev, 1914 phydev->mdio.addr & ~3, 0); 1915 } 1916 1917 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1918 { 1919 int val; 1920 1921 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1922 val = phy_read(phydev, 0x13); 1923 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1924 1925 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1926 } 1927 1928 /* On internal PHY's MMD reads over C22 always return 0. 1929 * Check a MMD register which is known to be non-zero. 1930 */ 1931 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1932 { 1933 int val; 1934 1935 phy_lock_mdio_bus(phydev); 1936 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1937 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1938 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1939 val = __phy_read(phydev, MII_MMD_DATA); 1940 phy_unlock_mdio_bus(phydev); 1941 1942 return val > 0; 1943 } 1944 1945 static int rtlgen_match_phy_device(struct phy_device *phydev, 1946 const struct phy_driver *phydrv) 1947 { 1948 return phydev->phy_id == RTL_GENERIC_PHYID && 1949 !rtlgen_supports_2_5gbps(phydev); 1950 } 1951 1952 static int rtl8226_match_phy_device(struct phy_device *phydev, 1953 const struct phy_driver *phydrv) 1954 { 1955 return phydev->phy_id == RTL_GENERIC_PHYID && 1956 rtlgen_supports_2_5gbps(phydev) && 1957 rtlgen_supports_mmd(phydev); 1958 } 1959 1960 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1961 bool is_c45) 1962 { 1963 if (phydev->is_c45) 1964 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1965 else 1966 return !is_c45 && (id == phydev->phy_id); 1967 } 1968 1969 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1970 const struct phy_driver *phydrv) 1971 { 1972 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1973 } 1974 1975 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 1976 const struct phy_driver *phydrv) 1977 { 1978 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 1979 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1980 } 1981 1982 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 1983 const struct phy_driver *phydrv) 1984 { 1985 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 1986 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1987 } 1988 1989 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1990 const struct phy_driver *phydrv) 1991 { 1992 if (phydev->is_c45) 1993 return false; 1994 1995 switch (phydev->phy_id) { 1996 case RTL_GENERIC_PHYID: 1997 case RTL_8221B: 1998 case RTL_8251B: 1999 case RTL_8261C: 2000 case 0x001cc841: 2001 break; 2002 default: 2003 return false; 2004 } 2005 2006 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 2007 } 2008 2009 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 2010 const struct phy_driver *phydrv) 2011 { 2012 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 2013 } 2014 2015 static int rtlgen_resume(struct phy_device *phydev) 2016 { 2017 int ret = genphy_resume(phydev); 2018 2019 /* Internal PHY's from RTL8168h up may not be instantly ready */ 2020 msleep(20); 2021 2022 return ret; 2023 } 2024 2025 static int rtlgen_c45_resume(struct phy_device *phydev) 2026 { 2027 int ret = genphy_c45_pma_resume(phydev); 2028 2029 msleep(20); 2030 2031 return ret; 2032 } 2033 2034 static int rtl9000a_config_init(struct phy_device *phydev) 2035 { 2036 phydev->autoneg = AUTONEG_DISABLE; 2037 phydev->speed = SPEED_100; 2038 phydev->duplex = DUPLEX_FULL; 2039 2040 return 0; 2041 } 2042 2043 static int rtl9000a_config_aneg(struct phy_device *phydev) 2044 { 2045 int ret; 2046 u16 ctl = 0; 2047 2048 switch (phydev->master_slave_set) { 2049 case MASTER_SLAVE_CFG_MASTER_FORCE: 2050 ctl |= CTL1000_AS_MASTER; 2051 break; 2052 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2053 break; 2054 case MASTER_SLAVE_CFG_UNKNOWN: 2055 case MASTER_SLAVE_CFG_UNSUPPORTED: 2056 return 0; 2057 default: 2058 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2059 return -EOPNOTSUPP; 2060 } 2061 2062 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 2063 if (ret == 1) 2064 ret = genphy_soft_reset(phydev); 2065 2066 return ret; 2067 } 2068 2069 static int rtl9000a_read_status(struct phy_device *phydev) 2070 { 2071 int ret; 2072 2073 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 2074 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2075 2076 ret = genphy_update_link(phydev); 2077 if (ret) 2078 return ret; 2079 2080 ret = phy_read(phydev, MII_CTRL1000); 2081 if (ret < 0) 2082 return ret; 2083 if (ret & CTL1000_AS_MASTER) 2084 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 2085 else 2086 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 2087 2088 ret = phy_read(phydev, MII_STAT1000); 2089 if (ret < 0) 2090 return ret; 2091 if (ret & LPA_1000MSRES) 2092 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 2093 else 2094 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2095 2096 return 0; 2097 } 2098 2099 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2100 { 2101 int err; 2102 2103 err = phy_read(phydev, RTL8211F_INSR); 2104 2105 return (err < 0) ? err : 0; 2106 } 2107 2108 static int rtl9000a_config_intr(struct phy_device *phydev) 2109 { 2110 u16 val; 2111 int err; 2112 2113 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2114 err = rtl9000a_ack_interrupt(phydev); 2115 if (err) 2116 return err; 2117 2118 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2119 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2120 } else { 2121 val = ~0; 2122 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2123 if (err) 2124 return err; 2125 2126 err = rtl9000a_ack_interrupt(phydev); 2127 } 2128 2129 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2130 } 2131 2132 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2133 { 2134 int irq_status; 2135 2136 irq_status = phy_read(phydev, RTL8211F_INSR); 2137 if (irq_status < 0) { 2138 phy_error(phydev); 2139 return IRQ_NONE; 2140 } 2141 2142 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2143 return IRQ_NONE; 2144 2145 phy_trigger_machine(phydev); 2146 2147 return IRQ_HANDLED; 2148 } 2149 2150 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2151 { 2152 int err; 2153 2154 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2155 2156 return (err < 0) ? err : 0; 2157 } 2158 2159 static int rtl8221b_config_intr(struct phy_device *phydev) 2160 { 2161 int err; 2162 2163 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2164 err = rtl8221b_ack_interrupt(phydev); 2165 if (err) 2166 return err; 2167 2168 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2169 RTL8221B_VND2_INER_LINK_STATUS); 2170 } else { 2171 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2172 RTL8221B_VND2_INER, 0); 2173 if (err) 2174 return err; 2175 2176 err = rtl8221b_ack_interrupt(phydev); 2177 } 2178 2179 return err; 2180 } 2181 2182 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2183 { 2184 int err; 2185 2186 err = rtl8221b_ack_interrupt(phydev); 2187 if (err) { 2188 phy_error(phydev); 2189 return IRQ_NONE; 2190 } 2191 2192 phy_trigger_machine(phydev); 2193 2194 return IRQ_HANDLED; 2195 } 2196 2197 static int rtlgen_sfp_get_features(struct phy_device *phydev) 2198 { 2199 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2200 phydev->supported); 2201 2202 /* set default mode */ 2203 phydev->speed = SPEED_10000; 2204 phydev->duplex = DUPLEX_FULL; 2205 2206 phydev->port = PORT_FIBRE; 2207 2208 return 0; 2209 } 2210 2211 static int rtlgen_sfp_read_status(struct phy_device *phydev) 2212 { 2213 int val, err; 2214 2215 err = genphy_update_link(phydev); 2216 if (err) 2217 return err; 2218 2219 if (!phydev->link) 2220 return 0; 2221 2222 val = phy_read(phydev, RTL_PHYSR); 2223 if (val < 0) 2224 return val; 2225 2226 rtlgen_decode_physr(phydev, val); 2227 2228 return 0; 2229 } 2230 2231 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 2232 { 2233 return 0; 2234 } 2235 2236 static struct phy_driver realtek_drvs[] = { 2237 { 2238 PHY_ID_MATCH_EXACT(0x00008201), 2239 .name = "RTL8201CP Ethernet", 2240 .read_page = rtl821x_read_page, 2241 .write_page = rtl821x_write_page, 2242 }, { 2243 PHY_ID_MATCH_EXACT(0x001cc816), 2244 .name = "RTL8201F Fast Ethernet", 2245 .config_intr = &rtl8201_config_intr, 2246 .handle_interrupt = rtl8201_handle_interrupt, 2247 .suspend = genphy_suspend, 2248 .resume = genphy_resume, 2249 .read_page = rtl821x_read_page, 2250 .write_page = rtl821x_write_page, 2251 }, { 2252 PHY_ID_MATCH_MODEL(0x001cc880), 2253 .name = "RTL8208 Fast Ethernet", 2254 .read_mmd = genphy_read_mmd_unsupported, 2255 .write_mmd = genphy_write_mmd_unsupported, 2256 .suspend = genphy_suspend, 2257 .resume = genphy_resume, 2258 .read_page = rtl821x_read_page, 2259 .write_page = rtl821x_write_page, 2260 }, { 2261 PHY_ID_MATCH_EXACT(0x001cc910), 2262 .name = "RTL8211 Gigabit Ethernet", 2263 .config_aneg = rtl8211_config_aneg, 2264 .read_mmd = &genphy_read_mmd_unsupported, 2265 .write_mmd = &genphy_write_mmd_unsupported, 2266 .read_page = rtl821x_read_page, 2267 .write_page = rtl821x_write_page, 2268 }, { 2269 PHY_ID_MATCH_EXACT(0x001cc912), 2270 .name = "RTL8211B Gigabit Ethernet", 2271 .config_intr = &rtl8211b_config_intr, 2272 .handle_interrupt = rtl821x_handle_interrupt, 2273 .read_mmd = &genphy_read_mmd_unsupported, 2274 .write_mmd = &genphy_write_mmd_unsupported, 2275 .suspend = rtl8211b_suspend, 2276 .resume = rtl8211b_resume, 2277 .read_page = rtl821x_read_page, 2278 .write_page = rtl821x_write_page, 2279 }, { 2280 PHY_ID_MATCH_EXACT(0x001cc913), 2281 .name = "RTL8211C Gigabit Ethernet", 2282 .config_init = rtl8211c_config_init, 2283 .read_mmd = &genphy_read_mmd_unsupported, 2284 .write_mmd = &genphy_write_mmd_unsupported, 2285 .read_page = rtl821x_read_page, 2286 .write_page = rtl821x_write_page, 2287 }, { 2288 PHY_ID_MATCH_EXACT(0x001cc914), 2289 .name = "RTL8211DN Gigabit Ethernet", 2290 .config_intr = rtl8211e_config_intr, 2291 .handle_interrupt = rtl821x_handle_interrupt, 2292 .suspend = genphy_suspend, 2293 .resume = genphy_resume, 2294 .read_page = rtl821x_read_page, 2295 .write_page = rtl821x_write_page, 2296 }, { 2297 PHY_ID_MATCH_EXACT(0x001cc915), 2298 .name = "RTL8211E Gigabit Ethernet", 2299 .config_init = &rtl8211e_config_init, 2300 .config_intr = &rtl8211e_config_intr, 2301 .handle_interrupt = rtl821x_handle_interrupt, 2302 .suspend = genphy_suspend, 2303 .resume = genphy_resume, 2304 .read_page = rtl821x_read_page, 2305 .write_page = rtl821x_write_page, 2306 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2307 .led_hw_control_get = rtl8211e_led_hw_control_get, 2308 .led_hw_control_set = rtl8211e_led_hw_control_set, 2309 }, { 2310 PHY_ID_MATCH_EXACT(0x001cc916), 2311 .name = "RTL8211F Gigabit Ethernet", 2312 .probe = rtl8211f_probe, 2313 .config_init = &rtl8211f_config_init, 2314 .read_status = rtlgen_read_status, 2315 .config_intr = &rtl8211f_config_intr, 2316 .handle_interrupt = rtl8211f_handle_interrupt, 2317 .set_wol = rtl8211f_set_wol, 2318 .get_wol = rtl8211f_get_wol, 2319 .suspend = rtl8211f_suspend, 2320 .resume = rtl8211f_resume, 2321 .read_page = rtl821x_read_page, 2322 .write_page = rtl821x_write_page, 2323 .flags = PHY_ALWAYS_CALL_SUSPEND, 2324 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2325 .led_hw_control_get = rtl8211f_led_hw_control_get, 2326 .led_hw_control_set = rtl8211f_led_hw_control_set, 2327 }, { 2328 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2329 .name = "RTL8211F-VD Gigabit Ethernet", 2330 .probe = rtl821x_probe, 2331 .config_init = &rtl8211f_config_init, 2332 .read_status = rtlgen_read_status, 2333 .config_intr = &rtl8211f_config_intr, 2334 .handle_interrupt = rtl8211f_handle_interrupt, 2335 .suspend = rtl821x_suspend, 2336 .resume = rtl821x_resume, 2337 .read_page = rtl821x_read_page, 2338 .write_page = rtl821x_write_page, 2339 .flags = PHY_ALWAYS_CALL_SUSPEND, 2340 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2341 .led_hw_control_get = rtl8211f_led_hw_control_get, 2342 .led_hw_control_set = rtl8211f_led_hw_control_set, 2343 }, { 2344 .name = "Generic FE-GE Realtek PHY", 2345 .match_phy_device = rtlgen_match_phy_device, 2346 .read_status = rtlgen_read_status, 2347 .suspend = genphy_suspend, 2348 .resume = rtlgen_resume, 2349 .read_page = rtl821x_read_page, 2350 .write_page = rtl821x_write_page, 2351 .read_mmd = rtlgen_read_mmd, 2352 .write_mmd = rtlgen_write_mmd, 2353 }, { 2354 .name = "RTL8226 2.5Gbps PHY", 2355 .match_phy_device = rtl8226_match_phy_device, 2356 .get_features = rtl822x_get_features, 2357 .config_aneg = rtl822x_config_aneg, 2358 .read_status = rtl822x_read_status, 2359 .suspend = genphy_suspend, 2360 .resume = rtlgen_resume, 2361 .read_page = rtl821x_read_page, 2362 .write_page = rtl821x_write_page, 2363 .read_mmd = rtl822xb_read_mmd, 2364 .write_mmd = rtl822xb_write_mmd, 2365 }, { 2366 .match_phy_device = rtl8221b_match_phy_device, 2367 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2368 .get_features = rtl822x_get_features, 2369 .config_aneg = rtl822x_config_aneg, 2370 .config_init = rtl822xb_config_init, 2371 .inband_caps = rtl822x_inband_caps, 2372 .config_inband = rtl822x_config_inband, 2373 .get_rate_matching = rtl822xb_get_rate_matching, 2374 .read_status = rtl822xb_read_status, 2375 .suspend = genphy_suspend, 2376 .resume = rtlgen_resume, 2377 .read_page = rtl821x_read_page, 2378 .write_page = rtl821x_write_page, 2379 .read_mmd = rtl822xb_read_mmd, 2380 .write_mmd = rtl822xb_write_mmd, 2381 }, { 2382 PHY_ID_MATCH_EXACT(0x001cc838), 2383 .name = "RTL8226-CG 2.5Gbps PHY", 2384 .soft_reset = rtl822x_c45_soft_reset, 2385 .get_features = rtl822x_c45_get_features, 2386 .config_aneg = rtl822x_c45_config_aneg, 2387 .config_init = rtl822x_config_init, 2388 .inband_caps = rtl822x_inband_caps, 2389 .config_inband = rtl822x_config_inband, 2390 .read_status = rtl822xb_c45_read_status, 2391 .suspend = genphy_c45_pma_suspend, 2392 .resume = rtlgen_c45_resume, 2393 .read_mmd = rtl822xb_read_mmd, 2394 .write_mmd = rtl822xb_write_mmd, 2395 }, { 2396 PHY_ID_MATCH_EXACT(0x001cc848), 2397 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2398 .get_features = rtl822x_get_features, 2399 .config_aneg = rtl822x_config_aneg, 2400 .config_init = rtl822xb_config_init, 2401 .inband_caps = rtl822x_inband_caps, 2402 .config_inband = rtl822x_config_inband, 2403 .get_rate_matching = rtl822xb_get_rate_matching, 2404 .read_status = rtl822xb_read_status, 2405 .suspend = genphy_suspend, 2406 .resume = rtlgen_resume, 2407 .read_page = rtl821x_read_page, 2408 .write_page = rtl821x_write_page, 2409 .read_mmd = rtl822xb_read_mmd, 2410 .write_mmd = rtl822xb_write_mmd, 2411 }, { 2412 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 2413 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 2414 .config_intr = rtl8221b_config_intr, 2415 .handle_interrupt = rtl8221b_handle_interrupt, 2416 .probe = rtl822x_probe, 2417 .config_init = rtl822xb_config_init, 2418 .inband_caps = rtl822x_inband_caps, 2419 .config_inband = rtl822x_config_inband, 2420 .get_rate_matching = rtl822xb_get_rate_matching, 2421 .get_features = rtl822x_c45_get_features, 2422 .config_aneg = rtl822x_c45_config_aneg, 2423 .read_status = rtl822xb_c45_read_status, 2424 .suspend = genphy_c45_pma_suspend, 2425 .resume = rtlgen_c45_resume, 2426 .read_page = rtl821x_read_page, 2427 .write_page = rtl821x_write_page, 2428 .read_mmd = rtl822xb_read_mmd, 2429 .write_mmd = rtl822xb_write_mmd, 2430 }, { 2431 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 2432 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 2433 .config_intr = rtl8221b_config_intr, 2434 .handle_interrupt = rtl8221b_handle_interrupt, 2435 .probe = rtl822x_probe, 2436 .config_init = rtl822xb_config_init, 2437 .inband_caps = rtl822x_inband_caps, 2438 .config_inband = rtl822x_config_inband, 2439 .get_rate_matching = rtl822xb_get_rate_matching, 2440 .get_features = rtl822x_c45_get_features, 2441 .config_aneg = rtl822x_c45_config_aneg, 2442 .read_status = rtl822xb_c45_read_status, 2443 .suspend = genphy_c45_pma_suspend, 2444 .resume = rtlgen_c45_resume, 2445 .read_page = rtl821x_read_page, 2446 .write_page = rtl821x_write_page, 2447 .read_mmd = rtl822xb_read_mmd, 2448 .write_mmd = rtl822xb_write_mmd, 2449 }, { 2450 .match_phy_device = rtl8251b_c45_match_phy_device, 2451 .name = "RTL8251B 5Gbps PHY", 2452 .probe = rtl822x_probe, 2453 .get_features = rtl822x_get_features, 2454 .config_aneg = rtl822x_config_aneg, 2455 .read_status = rtl822x_read_status, 2456 .suspend = genphy_suspend, 2457 .resume = rtlgen_resume, 2458 .read_page = rtl821x_read_page, 2459 .write_page = rtl821x_write_page, 2460 }, { 2461 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2462 .name = "Realtek Internal NBASE-T PHY", 2463 .flags = PHY_IS_INTERNAL, 2464 .probe = rtl822x_probe, 2465 .get_features = rtl822x_get_features, 2466 .config_aneg = rtl822x_config_aneg, 2467 .read_status = rtl822x_read_status, 2468 .suspend = genphy_suspend, 2469 .resume = rtlgen_resume, 2470 .read_page = rtl821x_read_page, 2471 .write_page = rtl821x_write_page, 2472 .read_mmd = rtl822x_read_mmd, 2473 .write_mmd = rtl822x_write_mmd, 2474 }, { 2475 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 2476 .name = "Realtek SFP PHY Mode", 2477 .flags = PHY_IS_INTERNAL, 2478 .probe = rtl822x_probe, 2479 .get_features = rtlgen_sfp_get_features, 2480 .config_aneg = rtlgen_sfp_config_aneg, 2481 .read_status = rtlgen_sfp_read_status, 2482 .suspend = genphy_suspend, 2483 .resume = rtlgen_resume, 2484 .read_page = rtl821x_read_page, 2485 .write_page = rtl821x_write_page, 2486 .read_mmd = rtl822x_read_mmd, 2487 .write_mmd = rtl822x_write_mmd, 2488 }, { 2489 PHY_ID_MATCH_EXACT(0x001ccad0), 2490 .name = "RTL8224 2.5Gbps PHY", 2491 .flags = PHY_POLL_CABLE_TEST, 2492 .probe = rtl8224_probe, 2493 .config_init = rtl8224_config_init, 2494 .get_features = rtl822x_c45_get_features, 2495 .config_aneg = rtl822x_c45_config_aneg, 2496 .read_status = rtl822x_c45_read_status, 2497 .suspend = genphy_c45_pma_suspend, 2498 .resume = rtlgen_c45_resume, 2499 .cable_test_start = rtl8224_cable_test_start, 2500 .cable_test_get_status = rtl8224_cable_test_get_status, 2501 }, { 2502 PHY_ID_MATCH_EXACT(0x001cc961), 2503 .name = "RTL8366RB Gigabit Ethernet", 2504 .config_init = &rtl8366rb_config_init, 2505 /* These interrupts are handled by the irq controller 2506 * embedded inside the RTL8366RB, they get unmasked when the 2507 * irq is requested and ACKed by reading the status register, 2508 * which is done by the irqchip code. 2509 */ 2510 .config_intr = genphy_no_config_intr, 2511 .handle_interrupt = genphy_handle_interrupt_no_ack, 2512 .suspend = genphy_suspend, 2513 .resume = genphy_resume, 2514 }, { 2515 PHY_ID_MATCH_EXACT(0x001ccb00), 2516 .name = "RTL9000AA_RTL9000AN Ethernet", 2517 .features = PHY_BASIC_T1_FEATURES, 2518 .config_init = rtl9000a_config_init, 2519 .config_aneg = rtl9000a_config_aneg, 2520 .read_status = rtl9000a_read_status, 2521 .config_intr = rtl9000a_config_intr, 2522 .handle_interrupt = rtl9000a_handle_interrupt, 2523 .suspend = genphy_suspend, 2524 .resume = genphy_resume, 2525 .read_page = rtl821x_read_page, 2526 .write_page = rtl821x_write_page, 2527 }, { 2528 PHY_ID_MATCH_EXACT(0x001cc942), 2529 .name = "RTL8365MB-VC Gigabit Ethernet", 2530 /* Interrupt handling analogous to RTL8366RB */ 2531 .config_intr = genphy_no_config_intr, 2532 .handle_interrupt = genphy_handle_interrupt_no_ack, 2533 .suspend = genphy_suspend, 2534 .resume = genphy_resume, 2535 }, { 2536 PHY_ID_MATCH_EXACT(0x001cc960), 2537 .name = "RTL8366S Gigabit Ethernet", 2538 .suspend = genphy_suspend, 2539 .resume = genphy_resume, 2540 .read_mmd = genphy_read_mmd_unsupported, 2541 .write_mmd = genphy_write_mmd_unsupported, 2542 }, 2543 }; 2544 2545 module_phy_driver(realtek_drvs); 2546 2547 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2548 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2549 { } 2550 }; 2551 2552 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2553