1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/netdevice.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/string_choices.h> 20 #include <net/phy/realtek_phy.h> 21 22 #include "../phylib.h" 23 #include "realtek.h" 24 25 #define RTL8201F_IER 0x13 26 27 #define RTL8201F_ISR 0x1e 28 #define RTL8201F_ISR_ANERR BIT(15) 29 #define RTL8201F_ISR_DUPLEX BIT(13) 30 #define RTL8201F_ISR_LINK BIT(11) 31 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 32 RTL8201F_ISR_DUPLEX | \ 33 RTL8201F_ISR_LINK) 34 35 #define RTL821x_INER 0x12 36 #define RTL8211B_INER_INIT 0x6400 37 #define RTL8211E_INER_LINK_STATUS BIT(10) 38 #define RTL8211F_INER_PME BIT(7) 39 #define RTL8211F_INER_LINK_STATUS BIT(4) 40 41 #define RTL821x_INSR 0x13 42 43 #define RTL821x_EXT_PAGE_SELECT 0x1e 44 45 #define RTL821x_PAGE_SELECT 0x1f 46 #define RTL821x_SET_EXT_PAGE 0x07 47 48 /* RTL8211E extension page 44/0x2c */ 49 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 50 #define RTL8211E_LEDCR1 0x1a 51 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 52 #define RTL8211E_LEDCR1_MASK BIT(4) 53 #define RTL8211E_LEDCR1_SHIFT 1 54 55 #define RTL8211E_LEDCR2 0x1c 56 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 57 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 58 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 59 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 60 #define RTL8211E_LEDCR2_SHIFT 4 61 62 /* RTL8211E extension page 164/0xa4 */ 63 #define RTL8211E_RGMII_EXT_PAGE 0xa4 64 #define RTL8211E_RGMII_DELAY 0x1c 65 #define RTL8211E_CTRL_DELAY BIT(13) 66 #define RTL8211E_TX_DELAY BIT(12) 67 #define RTL8211E_RX_DELAY BIT(11) 68 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 69 70 /* RTL8211F PHY configuration */ 71 #define RTL8211F_PHYCR1 0x18 72 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 73 #define RTL8211F_ALDPS_ENABLE BIT(2) 74 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 75 76 #define RTL8211F_PHYCR2 0x19 77 #define RTL8211F_CLKOUT_EN BIT(0) 78 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 79 80 #define RTL8211F_INSR 0x1d 81 82 /* RTL8211F LED configuration */ 83 #define RTL8211F_LEDCR_PAGE 0xd04 84 #define RTL8211F_LEDCR 0x10 85 #define RTL8211F_LEDCR_MODE BIT(15) 86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 87 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 88 #define RTL8211F_LEDCR_LINK_100 BIT(1) 89 #define RTL8211F_LEDCR_LINK_10 BIT(0) 90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 91 #define RTL8211F_LEDCR_SHIFT 5 92 93 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 94 * to undocumented register pages. The names here do not reflect the datasheet. 95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 96 */ 97 #define RTL8211FVD_CLKOUT_PAGE 0xd05 98 #define RTL8211FVD_CLKOUT_REG 0x11 99 #define RTL8211FVD_CLKOUT_EN BIT(8) 100 101 /* RTL8211F RGMII configuration */ 102 #define RTL8211F_RGMII_PAGE 0xd08 103 104 #define RTL8211F_TXCR 0x11 105 #define RTL8211F_TX_DELAY BIT(8) 106 107 #define RTL8211F_RXCR 0x15 108 #define RTL8211F_RX_DELAY BIT(3) 109 110 /* RTL8211F WOL settings */ 111 #define RTL8211F_WOL_PAGE 0xd8a 112 #define RTL8211F_WOL_SETTINGS_EVENTS 16 113 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 114 #define RTL8211F_WOL_RST_RMSQ 17 115 #define RTL8211F_WOL_RG_RSTB BIT(15) 116 #define RTL8211F_WOL_RMSQ 0x1fff 117 118 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 119 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 120 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 121 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 122 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 123 124 #define RTL822X_VND1_SERDES_OPTION 0x697a 125 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 126 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 128 129 #define RTL822X_VND1_SERDES_CTRL3 0x7580 130 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 131 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 132 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 133 134 #define RTL822X_VND1_SERDES_CMD 0x7587 135 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 136 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 137 #define RTL822X_VND1_SERDES_ADDR 0x7588 138 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 139 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 140 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 141 #define RTL822X_VND1_SERDES_DATA 0x7589 142 143 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 144 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 145 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 146 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 147 148 #define RTL8221B_VND2_INER 0xa4d2 149 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 150 151 #define RTL8221B_VND2_INSR 0xa4d4 152 153 #define RTL8224_MII_RTCT 0x11 154 #define RTL8224_MII_RTCT_ENABLE BIT(0) 155 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 156 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 157 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 158 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 159 #define RTL8224_MII_RTCT_DONE BIT(15) 160 161 #define RTL8224_MII_SRAM_ADDR 0x1b 162 #define RTL8224_MII_SRAM_DATA 0x1c 163 164 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 165 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 166 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 167 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 168 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 169 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 170 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 171 172 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 173 174 #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 175 176 #define RTL8366RB_POWER_SAVE 0x15 177 #define RTL8366RB_POWER_SAVE_ON BIT(12) 178 179 #define RTL9000A_GINMR 0x14 180 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 181 182 #define RTL_PHYSR MII_RESV2 183 #define RTL_PHYSR_DUPLEX BIT(3) 184 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 185 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 186 #define RTL_PHYSR_MASTER BIT(11) 187 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 188 189 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 190 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 191 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 192 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 193 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 194 #define RTL_MDIO_PMA_SPEED 0xa616 195 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 196 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 197 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 198 199 #define RTL_GENERIC_PHYID 0x001cc800 200 #define RTL_8211FVD_PHYID 0x001cc878 201 #define RTL_8221B 0x001cc840 202 #define RTL_8221B_VB_CG 0x001cc849 203 #define RTL_8221B_VM_CG 0x001cc84a 204 #define RTL_8251B 0x001cc862 205 #define RTL_8261C 0x001cc890 206 207 /* RTL8211E and RTL8211F support up to three LEDs */ 208 #define RTL8211x_LED_COUNT 3 209 210 MODULE_DESCRIPTION("Realtek PHY driver"); 211 MODULE_AUTHOR("Johnson Leung"); 212 MODULE_LICENSE("GPL"); 213 214 struct rtl821x_priv { 215 bool enable_aldps; 216 bool disable_clk_out; 217 struct clk *clk; 218 /* rtl8211f */ 219 u16 iner; 220 }; 221 222 static int rtl821x_read_page(struct phy_device *phydev) 223 { 224 return __phy_read(phydev, RTL821x_PAGE_SELECT); 225 } 226 227 static int rtl821x_write_page(struct phy_device *phydev, int page) 228 { 229 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 230 } 231 232 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 233 u32 regnum) 234 { 235 int oldpage, ret = 0; 236 237 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 238 if (oldpage >= 0) { 239 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 240 if (ret == 0) 241 ret = __phy_read(phydev, regnum); 242 } 243 244 return phy_restore_page(phydev, oldpage, ret); 245 } 246 247 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 248 u32 regnum, u16 mask, u16 set) 249 { 250 int oldpage, ret = 0; 251 252 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 253 if (oldpage >= 0) { 254 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 255 if (ret == 0) 256 ret = __phy_modify(phydev, regnum, mask, set); 257 } 258 259 return phy_restore_page(phydev, oldpage, ret); 260 } 261 262 static int rtl821x_probe(struct phy_device *phydev) 263 { 264 struct device *dev = &phydev->mdio.dev; 265 struct rtl821x_priv *priv; 266 267 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 268 if (!priv) 269 return -ENOMEM; 270 271 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 272 if (IS_ERR(priv->clk)) 273 return dev_err_probe(dev, PTR_ERR(priv->clk), 274 "failed to get phy clock\n"); 275 276 priv->enable_aldps = of_property_read_bool(dev->of_node, 277 "realtek,aldps-enable"); 278 priv->disable_clk_out = of_property_read_bool(dev->of_node, 279 "realtek,clkout-disable"); 280 281 phydev->priv = priv; 282 283 return 0; 284 } 285 286 static int rtl8211f_probe(struct phy_device *phydev) 287 { 288 struct device *dev = &phydev->mdio.dev; 289 int ret; 290 291 ret = rtl821x_probe(phydev); 292 if (ret < 0) 293 return ret; 294 295 /* Disable all PME events */ 296 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 297 RTL8211F_WOL_SETTINGS_EVENTS, 0); 298 if (ret < 0) 299 return ret; 300 301 /* Mark this PHY as wakeup capable and register the interrupt as a 302 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 303 * and the interrupt is valid. 304 */ 305 if (device_property_read_bool(dev, "wakeup-source") && 306 phy_interrupt_is_valid(phydev)) { 307 device_set_wakeup_capable(dev, true); 308 devm_pm_set_wake_irq(dev, phydev->irq); 309 } 310 311 return ret; 312 } 313 314 static int rtl8201_ack_interrupt(struct phy_device *phydev) 315 { 316 int err; 317 318 err = phy_read(phydev, RTL8201F_ISR); 319 320 return (err < 0) ? err : 0; 321 } 322 323 static int rtl821x_ack_interrupt(struct phy_device *phydev) 324 { 325 int err; 326 327 err = phy_read(phydev, RTL821x_INSR); 328 329 return (err < 0) ? err : 0; 330 } 331 332 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 333 { 334 int err; 335 336 err = phy_read(phydev, RTL8211F_INSR); 337 338 return (err < 0) ? err : 0; 339 } 340 341 static int rtl8201_config_intr(struct phy_device *phydev) 342 { 343 u16 val; 344 int err; 345 346 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 347 err = rtl8201_ack_interrupt(phydev); 348 if (err) 349 return err; 350 351 val = BIT(13) | BIT(12) | BIT(11); 352 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 353 } else { 354 val = 0; 355 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 356 if (err) 357 return err; 358 359 err = rtl8201_ack_interrupt(phydev); 360 } 361 362 return err; 363 } 364 365 static int rtl8211b_config_intr(struct phy_device *phydev) 366 { 367 int err; 368 369 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 370 err = rtl821x_ack_interrupt(phydev); 371 if (err) 372 return err; 373 374 err = phy_write(phydev, RTL821x_INER, 375 RTL8211B_INER_INIT); 376 } else { 377 err = phy_write(phydev, RTL821x_INER, 0); 378 if (err) 379 return err; 380 381 err = rtl821x_ack_interrupt(phydev); 382 } 383 384 return err; 385 } 386 387 static int rtl8211e_config_intr(struct phy_device *phydev) 388 { 389 int err; 390 391 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 392 err = rtl821x_ack_interrupt(phydev); 393 if (err) 394 return err; 395 396 err = phy_write(phydev, RTL821x_INER, 397 RTL8211E_INER_LINK_STATUS); 398 } else { 399 err = phy_write(phydev, RTL821x_INER, 0); 400 if (err) 401 return err; 402 403 err = rtl821x_ack_interrupt(phydev); 404 } 405 406 return err; 407 } 408 409 static int rtl8211f_config_intr(struct phy_device *phydev) 410 { 411 struct rtl821x_priv *priv = phydev->priv; 412 u16 val; 413 int err; 414 415 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 416 err = rtl8211f_ack_interrupt(phydev); 417 if (err) 418 return err; 419 420 val = RTL8211F_INER_LINK_STATUS; 421 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 422 if (err == 0) 423 priv->iner = val; 424 } else { 425 priv->iner = val = 0; 426 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 427 if (err) 428 return err; 429 430 err = rtl8211f_ack_interrupt(phydev); 431 } 432 433 return err; 434 } 435 436 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 437 { 438 int irq_status; 439 440 irq_status = phy_read(phydev, RTL8201F_ISR); 441 if (irq_status < 0) { 442 phy_error(phydev); 443 return IRQ_NONE; 444 } 445 446 if (!(irq_status & RTL8201F_ISR_MASK)) 447 return IRQ_NONE; 448 449 phy_trigger_machine(phydev); 450 451 return IRQ_HANDLED; 452 } 453 454 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 455 { 456 int irq_status, irq_enabled; 457 458 irq_status = phy_read(phydev, RTL821x_INSR); 459 if (irq_status < 0) { 460 phy_error(phydev); 461 return IRQ_NONE; 462 } 463 464 irq_enabled = phy_read(phydev, RTL821x_INER); 465 if (irq_enabled < 0) { 466 phy_error(phydev); 467 return IRQ_NONE; 468 } 469 470 if (!(irq_status & irq_enabled)) 471 return IRQ_NONE; 472 473 phy_trigger_machine(phydev); 474 475 return IRQ_HANDLED; 476 } 477 478 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 479 { 480 int irq_status; 481 482 irq_status = phy_read(phydev, RTL8211F_INSR); 483 if (irq_status < 0) { 484 phy_error(phydev); 485 return IRQ_NONE; 486 } 487 488 if (irq_status & RTL8211F_INER_LINK_STATUS) { 489 phy_trigger_machine(phydev); 490 return IRQ_HANDLED; 491 } 492 493 if (irq_status & RTL8211F_INER_PME) { 494 pm_wakeup_event(&phydev->mdio.dev, 0); 495 return IRQ_HANDLED; 496 } 497 498 return IRQ_NONE; 499 } 500 501 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 502 { 503 int wol_events; 504 505 /* If the PHY is not capable of waking the system, then WoL can not 506 * be supported. 507 */ 508 if (!device_can_wakeup(&dev->mdio.dev)) { 509 wol->supported = 0; 510 return; 511 } 512 513 wol->supported = WAKE_MAGIC; 514 515 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 516 if (wol_events < 0) 517 return; 518 519 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 520 wol->wolopts = WAKE_MAGIC; 521 } 522 523 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 524 { 525 const u8 *mac_addr = dev->attached_dev->dev_addr; 526 int oldpage; 527 528 if (!device_can_wakeup(&dev->mdio.dev)) 529 return -EOPNOTSUPP; 530 531 oldpage = phy_save_page(dev); 532 if (oldpage < 0) 533 goto err; 534 535 if (wol->wolopts & WAKE_MAGIC) { 536 /* Store the device address for the magic packet */ 537 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 538 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 539 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 540 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 541 542 /* Enable magic packet matching */ 543 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 544 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 545 /* Set the maximum packet size, and assert WoL reset */ 546 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 547 } else { 548 /* Disable magic packet matching */ 549 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 550 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 551 552 /* Place WoL in reset */ 553 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 554 RTL8211F_WOL_RG_RSTB); 555 } 556 557 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 558 559 err: 560 return phy_restore_page(dev, oldpage, 0); 561 } 562 563 static int rtl8211_config_aneg(struct phy_device *phydev) 564 { 565 int ret; 566 567 ret = genphy_config_aneg(phydev); 568 if (ret < 0) 569 return ret; 570 571 /* Quirk was copied from vendor driver. Unfortunately it includes no 572 * description of the magic numbers. 573 */ 574 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 575 phy_write(phydev, 0x17, 0x2138); 576 phy_write(phydev, 0x0e, 0x0260); 577 } else { 578 phy_write(phydev, 0x17, 0x2108); 579 phy_write(phydev, 0x0e, 0x0000); 580 } 581 582 return 0; 583 } 584 585 static int rtl8211c_config_init(struct phy_device *phydev) 586 { 587 /* RTL8211C has an issue when operating in Gigabit slave mode */ 588 return phy_set_bits(phydev, MII_CTRL1000, 589 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 590 } 591 592 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 593 { 594 u16 val_txdly, val_rxdly; 595 int ret; 596 597 switch (phydev->interface) { 598 case PHY_INTERFACE_MODE_RGMII: 599 val_txdly = 0; 600 val_rxdly = 0; 601 break; 602 603 case PHY_INTERFACE_MODE_RGMII_RXID: 604 val_txdly = 0; 605 val_rxdly = RTL8211F_RX_DELAY; 606 break; 607 608 case PHY_INTERFACE_MODE_RGMII_TXID: 609 val_txdly = RTL8211F_TX_DELAY; 610 val_rxdly = 0; 611 break; 612 613 case PHY_INTERFACE_MODE_RGMII_ID: 614 val_txdly = RTL8211F_TX_DELAY; 615 val_rxdly = RTL8211F_RX_DELAY; 616 break; 617 618 default: /* the rest of the modes imply leaving delay as is. */ 619 return 0; 620 } 621 622 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 623 RTL8211F_TXCR, RTL8211F_TX_DELAY, 624 val_txdly); 625 if (ret < 0) { 626 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 627 ERR_PTR(ret)); 628 return ret; 629 } else if (ret) { 630 phydev_dbg(phydev, 631 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 632 str_enable_disable(val_txdly)); 633 } else { 634 phydev_dbg(phydev, 635 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 636 str_enabled_disabled(val_txdly)); 637 } 638 639 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 640 RTL8211F_RXCR, RTL8211F_RX_DELAY, 641 val_rxdly); 642 if (ret < 0) { 643 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 644 ERR_PTR(ret)); 645 return ret; 646 } else if (ret) { 647 phydev_dbg(phydev, 648 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 649 str_enable_disable(val_rxdly)); 650 } else { 651 phydev_dbg(phydev, 652 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 653 str_enabled_disabled(val_rxdly)); 654 } 655 656 return 0; 657 } 658 659 static int rtl8211f_config_clk_out(struct phy_device *phydev) 660 { 661 struct rtl821x_priv *priv = phydev->priv; 662 int ret; 663 664 /* The value is preserved if the device tree property is absent */ 665 if (!priv->disable_clk_out) 666 return 0; 667 668 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 669 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 670 RTL8211FVD_CLKOUT_REG, 671 RTL8211FVD_CLKOUT_EN, 0); 672 else 673 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 674 0); 675 if (ret) 676 return ret; 677 678 return genphy_soft_reset(phydev); 679 } 680 681 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 682 * which causes the RXC clock signal to stop for tens to hundreds of 683 * milliseconds. 684 * 685 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 686 * only enabled based on an opt-in device tree property. 687 */ 688 static int rtl8211f_config_aldps(struct phy_device *phydev) 689 { 690 struct rtl821x_priv *priv = phydev->priv; 691 u16 mask = RTL8211F_ALDPS_PLL_OFF | 692 RTL8211F_ALDPS_ENABLE | 693 RTL8211F_ALDPS_XTAL_OFF; 694 695 /* The value is preserved if the device tree property is absent */ 696 if (!priv->enable_aldps) 697 return 0; 698 699 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 700 } 701 702 static int rtl8211f_config_phy_eee(struct phy_device *phydev) 703 { 704 /* Disable PHY-mode EEE so LPI is passed to the MAC */ 705 return phy_modify(phydev, RTL8211F_PHYCR2, 706 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 707 } 708 709 static int rtl8211f_config_init(struct phy_device *phydev) 710 { 711 struct device *dev = &phydev->mdio.dev; 712 int ret; 713 714 ret = rtl8211f_config_aldps(phydev); 715 if (ret) { 716 dev_err(dev, "aldps mode configuration failed: %pe\n", 717 ERR_PTR(ret)); 718 return ret; 719 } 720 721 ret = rtl8211f_config_rgmii_delay(phydev); 722 if (ret) 723 return ret; 724 725 ret = rtl8211f_config_clk_out(phydev); 726 if (ret) { 727 dev_err(dev, "clkout configuration failed: %pe\n", 728 ERR_PTR(ret)); 729 return ret; 730 } 731 732 return rtl8211f_config_phy_eee(phydev); 733 } 734 735 static int rtl821x_suspend(struct phy_device *phydev) 736 { 737 struct rtl821x_priv *priv = phydev->priv; 738 int ret = 0; 739 740 if (!phydev->wol_enabled) { 741 ret = genphy_suspend(phydev); 742 743 if (ret) 744 return ret; 745 746 clk_disable_unprepare(priv->clk); 747 } 748 749 return ret; 750 } 751 752 static int rtl8211f_suspend(struct phy_device *phydev) 753 { 754 u16 wol_rst; 755 int ret; 756 757 ret = rtl821x_suspend(phydev); 758 if (ret < 0) 759 return ret; 760 761 /* If a PME event is enabled, then configure the interrupt for 762 * PME events only, disabling link interrupt. We avoid switching 763 * to PMEB mode as we don't have a status bit for that. 764 */ 765 if (device_may_wakeup(&phydev->mdio.dev)) { 766 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 767 RTL8211F_INER_PME); 768 if (ret < 0) 769 goto err; 770 771 /* Read the INSR to clear any pending interrupt */ 772 phy_read(phydev, RTL8211F_INSR); 773 774 /* Reset the WoL to ensure that an event is picked up. 775 * Unless we do this, even if we receive another packet, 776 * we may not have a PME interrupt raised. 777 */ 778 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 779 RTL8211F_WOL_RST_RMSQ); 780 if (ret < 0) 781 goto err; 782 783 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 784 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 785 RTL8211F_WOL_RST_RMSQ, wol_rst); 786 if (ret < 0) 787 goto err; 788 789 wol_rst |= RTL8211F_WOL_RG_RSTB; 790 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 791 RTL8211F_WOL_RST_RMSQ, wol_rst); 792 } 793 794 err: 795 return ret; 796 } 797 798 static int rtl821x_resume(struct phy_device *phydev) 799 { 800 struct rtl821x_priv *priv = phydev->priv; 801 int ret; 802 803 if (!phydev->wol_enabled) 804 clk_prepare_enable(priv->clk); 805 806 ret = genphy_resume(phydev); 807 if (ret < 0) 808 return ret; 809 810 msleep(20); 811 812 return 0; 813 } 814 815 static int rtl8211f_resume(struct phy_device *phydev) 816 { 817 struct rtl821x_priv *priv = phydev->priv; 818 int ret; 819 820 ret = rtl821x_resume(phydev); 821 if (ret < 0) 822 return ret; 823 824 /* If the device was programmed for a PME event, restore the interrupt 825 * enable so phylib can receive link state interrupts. 826 */ 827 if (device_may_wakeup(&phydev->mdio.dev)) 828 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 829 830 return ret; 831 } 832 833 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 834 unsigned long rules) 835 { 836 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 837 BIT(TRIGGER_NETDEV_LINK_10) | 838 BIT(TRIGGER_NETDEV_LINK_100) | 839 BIT(TRIGGER_NETDEV_LINK_1000) | 840 BIT(TRIGGER_NETDEV_RX) | 841 BIT(TRIGGER_NETDEV_TX); 842 843 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 844 * - Link: Configurable subset of 10/100/1000 link rates 845 * - Active: Blink on activity, RX or TX is not differentiated 846 * The Active option has two modes, A and B: 847 * - A: Link and Active indication at configurable, but matching, 848 * subset of 10/100/1000 link rates 849 * - B: Link indication at configurable subset of 10/100/1000 link 850 * rates and Active indication always at all three 10+100+1000 851 * link rates. 852 * This code currently uses mode B only. 853 * 854 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 855 */ 856 857 if (index >= RTL8211x_LED_COUNT) 858 return -EINVAL; 859 860 /* Filter out any other unsupported triggers. */ 861 if (rules & ~mask) 862 return -EOPNOTSUPP; 863 864 /* RX and TX are not differentiated, either both are set or not set. */ 865 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 866 return -EOPNOTSUPP; 867 868 return 0; 869 } 870 871 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 872 unsigned long *rules) 873 { 874 int val; 875 876 if (index >= RTL8211x_LED_COUNT) 877 return -EINVAL; 878 879 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 880 if (val < 0) 881 return val; 882 883 val >>= RTL8211F_LEDCR_SHIFT * index; 884 val &= RTL8211F_LEDCR_MASK; 885 886 if (val & RTL8211F_LEDCR_LINK_10) 887 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 888 889 if (val & RTL8211F_LEDCR_LINK_100) 890 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 891 892 if (val & RTL8211F_LEDCR_LINK_1000) 893 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 894 895 if ((val & RTL8211F_LEDCR_LINK_10) && 896 (val & RTL8211F_LEDCR_LINK_100) && 897 (val & RTL8211F_LEDCR_LINK_1000)) { 898 __set_bit(TRIGGER_NETDEV_LINK, rules); 899 } 900 901 if (val & RTL8211F_LEDCR_ACT_TXRX) { 902 __set_bit(TRIGGER_NETDEV_RX, rules); 903 __set_bit(TRIGGER_NETDEV_TX, rules); 904 } 905 906 return 0; 907 } 908 909 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 910 unsigned long rules) 911 { 912 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 913 u16 reg = 0; 914 915 if (index >= RTL8211x_LED_COUNT) 916 return -EINVAL; 917 918 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 919 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 920 reg |= RTL8211F_LEDCR_LINK_10; 921 } 922 923 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 924 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 925 reg |= RTL8211F_LEDCR_LINK_100; 926 } 927 928 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 929 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 930 reg |= RTL8211F_LEDCR_LINK_1000; 931 } 932 933 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 934 test_bit(TRIGGER_NETDEV_TX, &rules)) { 935 reg |= RTL8211F_LEDCR_ACT_TXRX; 936 } 937 938 reg <<= RTL8211F_LEDCR_SHIFT * index; 939 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 940 941 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 942 } 943 944 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 945 unsigned long *rules) 946 { 947 int ret; 948 u16 cr1, cr2; 949 950 if (index >= RTL8211x_LED_COUNT) 951 return -EINVAL; 952 953 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 954 RTL8211E_LEDCR1); 955 if (ret < 0) 956 return ret; 957 958 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 959 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 960 __set_bit(TRIGGER_NETDEV_RX, rules); 961 __set_bit(TRIGGER_NETDEV_TX, rules); 962 } 963 964 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 965 RTL8211E_LEDCR2); 966 if (ret < 0) 967 return ret; 968 969 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 970 if (cr2 & RTL8211E_LEDCR2_LINK_10) 971 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 972 973 if (cr2 & RTL8211E_LEDCR2_LINK_100) 974 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 975 976 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 977 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 978 979 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 980 (cr2 & RTL8211E_LEDCR2_LINK_100) && 981 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 982 __set_bit(TRIGGER_NETDEV_LINK, rules); 983 } 984 985 return ret; 986 } 987 988 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 989 unsigned long rules) 990 { 991 const u16 cr1mask = 992 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 993 const u16 cr2mask = 994 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 995 u16 cr1 = 0, cr2 = 0; 996 int ret; 997 998 if (index >= RTL8211x_LED_COUNT) 999 return -EINVAL; 1000 1001 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1002 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1003 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1004 } 1005 1006 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1007 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1008 RTL8211E_LEDCR1, cr1mask, cr1); 1009 if (ret < 0) 1010 return ret; 1011 1012 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1013 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1014 cr2 |= RTL8211E_LEDCR2_LINK_10; 1015 } 1016 1017 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1018 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1019 cr2 |= RTL8211E_LEDCR2_LINK_100; 1020 } 1021 1022 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1023 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1024 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1025 } 1026 1027 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1028 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1029 RTL8211E_LEDCR2, cr2mask, cr2); 1030 1031 return ret; 1032 } 1033 1034 static int rtl8211e_config_init(struct phy_device *phydev) 1035 { 1036 u16 val; 1037 1038 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1039 switch (phydev->interface) { 1040 case PHY_INTERFACE_MODE_RGMII: 1041 val = RTL8211E_CTRL_DELAY | 0; 1042 break; 1043 case PHY_INTERFACE_MODE_RGMII_ID: 1044 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1045 break; 1046 case PHY_INTERFACE_MODE_RGMII_RXID: 1047 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1048 break; 1049 case PHY_INTERFACE_MODE_RGMII_TXID: 1050 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1051 break; 1052 default: /* the rest of the modes imply leaving delays as is. */ 1053 return 0; 1054 } 1055 1056 /* According to a sample driver there is a 0x1c config register on the 1057 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1058 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1059 * The configuration register definition: 1060 * 14 = reserved 1061 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1062 * 12 = RX Delay, 11 = TX Delay 1063 * 10:0 = Test && debug settings reserved by realtek 1064 */ 1065 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1066 RTL8211E_RGMII_DELAY, 1067 RTL8211E_DELAY_MASK, val); 1068 } 1069 1070 static int rtl8211b_suspend(struct phy_device *phydev) 1071 { 1072 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1073 1074 return genphy_suspend(phydev); 1075 } 1076 1077 static int rtl8211b_resume(struct phy_device *phydev) 1078 { 1079 phy_write(phydev, MII_MMD_DATA, 0); 1080 1081 return genphy_resume(phydev); 1082 } 1083 1084 static int rtl8366rb_config_init(struct phy_device *phydev) 1085 { 1086 int ret; 1087 1088 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1089 RTL8366RB_POWER_SAVE_ON); 1090 if (ret) { 1091 dev_err(&phydev->mdio.dev, 1092 "error enabling power management\n"); 1093 } 1094 1095 return ret; 1096 } 1097 1098 /* get actual speed to cover the downshift case */ 1099 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1100 { 1101 /* bit 3 1102 * 0: Half Duplex 1103 * 1: Full Duplex 1104 */ 1105 if (val & RTL_PHYSR_DUPLEX) 1106 phydev->duplex = DUPLEX_FULL; 1107 else 1108 phydev->duplex = DUPLEX_HALF; 1109 1110 switch (val & RTL_PHYSR_SPEED_MASK) { 1111 case 0x0000: 1112 phydev->speed = SPEED_10; 1113 break; 1114 case 0x0010: 1115 phydev->speed = SPEED_100; 1116 break; 1117 case 0x0020: 1118 phydev->speed = SPEED_1000; 1119 break; 1120 case 0x0200: 1121 phydev->speed = SPEED_10000; 1122 break; 1123 case 0x0210: 1124 phydev->speed = SPEED_2500; 1125 break; 1126 case 0x0220: 1127 phydev->speed = SPEED_5000; 1128 break; 1129 default: 1130 break; 1131 } 1132 1133 /* bit 11 1134 * 0: Slave Mode 1135 * 1: Master Mode 1136 */ 1137 if (phydev->speed >= 1000) { 1138 if (val & RTL_PHYSR_MASTER) 1139 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1140 else 1141 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1142 } else { 1143 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1144 } 1145 } 1146 1147 static int rtlgen_read_status(struct phy_device *phydev) 1148 { 1149 int ret, val; 1150 1151 ret = genphy_read_status(phydev); 1152 if (ret < 0) 1153 return ret; 1154 1155 if (!phydev->link) 1156 return 0; 1157 1158 val = phy_read(phydev, RTL_PHYSR); 1159 if (val < 0) 1160 return val; 1161 1162 rtlgen_decode_physr(phydev, val); 1163 1164 return 0; 1165 } 1166 1167 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1168 { 1169 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1170 } 1171 1172 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1173 { 1174 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1175 val); 1176 } 1177 1178 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1179 { 1180 int ret; 1181 1182 if (devnum == MDIO_MMD_VEND2) 1183 ret = rtlgen_read_vend2(phydev, regnum); 1184 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1185 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1186 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1187 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1188 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1189 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1190 else 1191 ret = -EOPNOTSUPP; 1192 1193 return ret; 1194 } 1195 1196 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1197 u16 val) 1198 { 1199 int ret; 1200 1201 if (devnum == MDIO_MMD_VEND2) 1202 ret = rtlgen_write_vend2(phydev, regnum, val); 1203 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1204 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 1205 else 1206 ret = -EOPNOTSUPP; 1207 1208 return ret; 1209 } 1210 1211 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1212 { 1213 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1214 1215 if (ret != -EOPNOTSUPP) 1216 return ret; 1217 1218 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1219 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1220 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1221 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1222 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1223 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1224 1225 return ret; 1226 } 1227 1228 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1229 u16 val) 1230 { 1231 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1232 1233 if (ret != -EOPNOTSUPP) 1234 return ret; 1235 1236 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1237 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1238 1239 return ret; 1240 } 1241 1242 static int rtl822x_probe(struct phy_device *phydev) 1243 { 1244 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1245 phydev->phy_id != RTL_GENERIC_PHYID) 1246 return rtl822x_hwmon_init(phydev); 1247 1248 return 0; 1249 } 1250 1251 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1252 * A mapping to use paged access needs to be used instead. 1253 * All other MMD devices can be accessed as usual. 1254 */ 1255 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1256 { 1257 int oldpage, ret, read_ret; 1258 u16 page; 1259 1260 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1261 * Clause-45 access is available 1262 */ 1263 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1264 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1265 phydev->is_c45, devnum, reg); 1266 1267 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1268 if (reg >= RTL822X_VND2_C22_REG(0) && 1269 reg <= RTL822X_VND2_C22_REG(30)) 1270 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1271 1272 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1273 page = RTL822X_VND2_TO_PAGE(reg); 1274 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1275 if (oldpage < 0) 1276 return oldpage; 1277 1278 if (oldpage != page) { 1279 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1280 if (ret < 0) 1281 return ret; 1282 } 1283 1284 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1285 if (oldpage != page) { 1286 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1287 if (ret < 0) 1288 return ret; 1289 } 1290 1291 return read_ret; 1292 } 1293 1294 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1295 u16 val) 1296 { 1297 int oldpage, ret, write_ret; 1298 u16 page; 1299 1300 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1301 * Clause-45 access is available 1302 */ 1303 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1304 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1305 phydev->is_c45, devnum, reg, val); 1306 1307 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1308 if (reg >= RTL822X_VND2_C22_REG(0) && 1309 reg <= RTL822X_VND2_C22_REG(30)) 1310 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1311 1312 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1313 page = RTL822X_VND2_TO_PAGE(reg); 1314 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1315 if (oldpage < 0) 1316 return oldpage; 1317 1318 if (oldpage != page) { 1319 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1320 if (ret < 0) 1321 return ret; 1322 } 1323 1324 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1325 if (oldpage != page) { 1326 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1327 if (ret < 0) 1328 return ret; 1329 } 1330 1331 return write_ret; 1332 } 1333 1334 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 1335 { 1336 bool has_2500, has_sgmii; 1337 u16 mode; 1338 int ret; 1339 1340 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 1341 phydev->host_interfaces) || 1342 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 1343 1344 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 1345 phydev->host_interfaces) || 1346 phydev->interface == PHY_INTERFACE_MODE_SGMII; 1347 1348 /* fill in possible interfaces */ 1349 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 1350 has_2500); 1351 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 1352 has_sgmii); 1353 1354 if (!has_2500 && !has_sgmii) 1355 return 0; 1356 1357 /* determine SerDes option mode */ 1358 if (has_2500 && !has_sgmii) { 1359 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 1360 phydev->rate_matching = RATE_MATCH_PAUSE; 1361 } else { 1362 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 1363 phydev->rate_matching = RATE_MATCH_NONE; 1364 } 1365 1366 /* the following sequence with magic numbers sets up the SerDes 1367 * option mode 1368 */ 1369 1370 if (!gen1) { 1371 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 1372 if (ret < 0) 1373 return ret; 1374 } 1375 1376 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 1377 RTL822X_VND1_SERDES_OPTION, 1378 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 1379 mode); 1380 if (gen1 || ret < 0) 1381 return ret; 1382 1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 1384 if (ret < 0) 1385 return ret; 1386 1387 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 1388 if (ret < 0) 1389 return ret; 1390 1391 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 1392 } 1393 1394 static int rtl822x_config_init(struct phy_device *phydev) 1395 { 1396 return rtl822x_set_serdes_option_mode(phydev, true); 1397 } 1398 1399 static int rtl822xb_config_init(struct phy_device *phydev) 1400 { 1401 return rtl822x_set_serdes_option_mode(phydev, false); 1402 } 1403 1404 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 1405 { 1406 int ret, poll; 1407 1408 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 1409 if (ret < 0) 1410 return ret; 1411 1412 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 1413 if (ret < 0) 1414 return ret; 1415 1416 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 1417 RTL822X_VND1_SERDES_CMD_WRITE | 1418 RTL822X_VND1_SERDES_CMD_BUSY); 1419 if (ret < 0) 1420 return ret; 1421 1422 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1423 RTL822X_VND1_SERDES_CMD, poll, 1424 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 1425 500, 100000, false); 1426 } 1427 1428 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 1429 { 1430 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 1431 (modes != LINK_INBAND_DISABLE) ? 1432 RTL822X_VND1_SERDES_INBAND_ENABLE : 1433 RTL822X_VND1_SERDES_INBAND_DISABLE); 1434 } 1435 1436 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 1437 phy_interface_t interface) 1438 { 1439 switch (interface) { 1440 case PHY_INTERFACE_MODE_2500BASEX: 1441 return LINK_INBAND_DISABLE; 1442 case PHY_INTERFACE_MODE_SGMII: 1443 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 1444 default: 1445 return 0; 1446 } 1447 } 1448 1449 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 1450 phy_interface_t iface) 1451 { 1452 int val; 1453 1454 /* Only rate matching at 2500base-x */ 1455 if (iface != PHY_INTERFACE_MODE_2500BASEX) 1456 return RATE_MATCH_NONE; 1457 1458 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 1459 if (val < 0) 1460 return val; 1461 1462 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 1463 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 1464 return RATE_MATCH_PAUSE; 1465 1466 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 1467 return RATE_MATCH_NONE; 1468 } 1469 1470 static int rtl822x_get_features(struct phy_device *phydev) 1471 { 1472 int val; 1473 1474 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 1475 if (val < 0) 1476 return val; 1477 1478 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1479 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 1480 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1481 phydev->supported, val & MDIO_PMA_SPEED_5G); 1482 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1483 phydev->supported, val & MDIO_SPEED_10G); 1484 1485 return genphy_read_abilities(phydev); 1486 } 1487 1488 static int rtl822x_config_aneg(struct phy_device *phydev) 1489 { 1490 int ret = 0; 1491 1492 if (phydev->autoneg == AUTONEG_ENABLE) { 1493 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1494 1495 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1496 RTL_MDIO_AN_10GBT_CTRL, 1497 MDIO_AN_10GBT_CTRL_ADV2_5G | 1498 MDIO_AN_10GBT_CTRL_ADV5G, adv); 1499 if (ret < 0) 1500 return ret; 1501 } 1502 1503 return __genphy_config_aneg(phydev, ret); 1504 } 1505 1506 static void rtl822xb_update_interface(struct phy_device *phydev) 1507 { 1508 int val; 1509 1510 if (!phydev->link) 1511 return; 1512 1513 /* Change interface according to serdes mode */ 1514 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 1515 if (val < 0) 1516 return; 1517 1518 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 1519 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 1520 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1521 break; 1522 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 1523 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1524 break; 1525 } 1526 } 1527 1528 static int rtl822x_read_status(struct phy_device *phydev) 1529 { 1530 int lpadv, ret; 1531 1532 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1533 1534 ret = rtlgen_read_status(phydev); 1535 if (ret < 0) 1536 return ret; 1537 1538 if (phydev->autoneg == AUTONEG_DISABLE || 1539 !phydev->autoneg_complete) 1540 return 0; 1541 1542 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 1543 if (lpadv < 0) 1544 return lpadv; 1545 1546 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 1547 1548 return 0; 1549 } 1550 1551 static int rtl822xb_read_status(struct phy_device *phydev) 1552 { 1553 int ret; 1554 1555 ret = rtl822x_read_status(phydev); 1556 if (ret < 0) 1557 return ret; 1558 1559 rtl822xb_update_interface(phydev); 1560 1561 return 0; 1562 } 1563 1564 static int rtl822x_c45_get_features(struct phy_device *phydev) 1565 { 1566 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1567 phydev->supported); 1568 1569 return genphy_c45_pma_read_abilities(phydev); 1570 } 1571 1572 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1573 { 1574 bool changed = false; 1575 int ret, val; 1576 1577 if (phydev->autoneg == AUTONEG_DISABLE) 1578 return genphy_c45_pma_setup_forced(phydev); 1579 1580 ret = genphy_c45_an_config_aneg(phydev); 1581 if (ret < 0) 1582 return ret; 1583 if (ret > 0) 1584 changed = true; 1585 1586 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1587 1588 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1589 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1590 RTL822X_VND2_C22_REG(MII_CTRL1000), 1591 ADVERTISE_1000FULL, val); 1592 if (ret < 0) 1593 return ret; 1594 if (ret > 0) 1595 changed = true; 1596 1597 return genphy_c45_check_and_restart_aneg(phydev, changed); 1598 } 1599 1600 static int rtl822x_c45_read_status(struct phy_device *phydev) 1601 { 1602 int ret, val; 1603 1604 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1605 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1606 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1607 RTL822X_VND2_C22_REG(MII_STAT1000)); 1608 if (val < 0) 1609 return val; 1610 } else { 1611 val = 0; 1612 } 1613 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1614 1615 ret = genphy_c45_read_status(phydev); 1616 if (ret < 0) 1617 return ret; 1618 1619 if (!phydev->link) { 1620 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1621 return 0; 1622 } 1623 1624 /* Read actual speed from vendor register. */ 1625 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1626 RTL822X_VND2_C22_REG(RTL_PHYSR)); 1627 if (val < 0) 1628 return val; 1629 1630 rtlgen_decode_physr(phydev, val); 1631 1632 return 0; 1633 } 1634 1635 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 1636 { 1637 int ret, val; 1638 1639 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 1640 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 1641 if (ret < 0) 1642 return ret; 1643 1644 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 1645 MDIO_CTRL1, val, 1646 !(val & MDIO_CTRL1_RESET), 1647 5000, 100000, true); 1648 } 1649 1650 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1651 { 1652 int ret; 1653 1654 ret = rtl822x_c45_read_status(phydev); 1655 if (ret < 0) 1656 return ret; 1657 1658 rtl822xb_update_interface(phydev); 1659 1660 return 0; 1661 } 1662 1663 static int rtl8224_cable_test_start(struct phy_device *phydev) 1664 { 1665 u32 val; 1666 int ret; 1667 1668 /* disable auto-negotiation and force 1000/Full */ 1669 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1670 RTL822X_VND2_C22_REG(MII_BMCR), 1671 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 1672 BMCR_SPEED1000 | BMCR_FULLDPLX); 1673 if (ret) 1674 return ret; 1675 1676 mdelay(500); 1677 1678 /* trigger cable test */ 1679 val = RTL8224_MII_RTCT_ENABLE; 1680 val |= RTL8224_MII_RTCT_PAIR_A; 1681 val |= RTL8224_MII_RTCT_PAIR_B; 1682 val |= RTL8224_MII_RTCT_PAIR_C; 1683 val |= RTL8224_MII_RTCT_PAIR_D; 1684 1685 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1686 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 1687 RTL8224_MII_RTCT_DONE, val); 1688 } 1689 1690 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 1691 { 1692 int ret; 1693 1694 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1695 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 1696 reg); 1697 if (ret) 1698 return ret; 1699 1700 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 1701 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 1702 } 1703 1704 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 1705 { 1706 int cable_len; 1707 u32 reg_len; 1708 int ret; 1709 u32 cm; 1710 1711 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 1712 1713 ret = rtl8224_sram_read(phydev, reg_len); 1714 if (ret < 0) 1715 return ret; 1716 1717 cable_len = ret & 0xff00; 1718 1719 ret = rtl8224_sram_read(phydev, reg_len + 1); 1720 if (ret < 0) 1721 return ret; 1722 1723 cable_len |= (ret & 0xff00) >> 8; 1724 1725 cable_len -= 620; 1726 cable_len = max(cable_len, 0); 1727 1728 cm = cable_len * 100 / 78; 1729 1730 return cm; 1731 } 1732 1733 static int rtl8224_cable_test_result_trans(u32 result) 1734 { 1735 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 1736 return -EBUSY; 1737 1738 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 1739 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1740 1741 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 1742 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1743 1744 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 1745 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1746 1747 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 1748 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1749 1750 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 1751 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 1752 1753 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1754 } 1755 1756 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 1757 { 1758 int fault_rslt; 1759 int ret; 1760 1761 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 1762 if (ret < 0) 1763 return ret; 1764 1765 fault_rslt = rtl8224_cable_test_result_trans(ret); 1766 if (fault_rslt < 0) 1767 return 0; 1768 1769 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 1770 if (ret < 0) 1771 return ret; 1772 1773 switch (fault_rslt) { 1774 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 1775 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 1776 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 1777 ret = rtl8224_pair_len_get(phydev, pair); 1778 if (ret < 0) 1779 return ret; 1780 1781 return ethnl_cable_test_fault_length(phydev, pair, ret); 1782 default: 1783 return 0; 1784 } 1785 } 1786 1787 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 1788 { 1789 unsigned int pair; 1790 int ret; 1791 1792 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 1793 ret = rtl8224_cable_test_report_pair(phydev, pair); 1794 if (ret == -EBUSY) { 1795 *finished = false; 1796 return 0; 1797 } 1798 1799 if (ret < 0) 1800 return ret; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 1807 { 1808 int ret; 1809 1810 *finished = false; 1811 1812 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1813 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 1814 if (ret < 0) 1815 return ret; 1816 1817 if (!(ret & RTL8224_MII_RTCT_DONE)) 1818 return 0; 1819 1820 *finished = true; 1821 1822 return rtl8224_cable_test_report(phydev, finished); 1823 } 1824 1825 static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, 1826 u32 regnum, u16 mask, u16 set) 1827 { 1828 int val, ret; 1829 1830 phy_lock_mdio_bus(phydev); 1831 1832 val = __phy_package_read_mmd(phydev, 0, devad, regnum); 1833 if (val < 0) { 1834 ret = val; 1835 goto exit; 1836 } 1837 1838 val &= ~mask; 1839 val |= set; 1840 1841 ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); 1842 1843 exit: 1844 phy_unlock_mdio_bus(phydev); 1845 return ret; 1846 } 1847 1848 static int rtl8224_mdi_config_order(struct phy_device *phydev) 1849 { 1850 struct device_node *np = phydev->mdio.dev.of_node; 1851 u8 port_offset = phydev->mdio.addr & 3; 1852 u32 order = 0; 1853 int ret; 1854 1855 ret = of_property_read_u32(np, "enet-phy-pair-order", &order); 1856 1857 /* Do nothing in case the property is not present */ 1858 if (ret == -EINVAL || ret == -ENOSYS) 1859 return 0; 1860 1861 if (ret) 1862 return ret; 1863 1864 if (order & ~1) 1865 return -EINVAL; 1866 1867 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 1868 RTL8224_VND1_MDI_PAIR_SWAP, 1869 BIT(port_offset), 1870 order ? BIT(port_offset) : 0); 1871 } 1872 1873 static int rtl8224_config_init(struct phy_device *phydev) 1874 { 1875 return rtl8224_mdi_config_order(phydev); 1876 } 1877 1878 static int rtl8224_probe(struct phy_device *phydev) 1879 { 1880 /* Chip exposes 4 ports, join all of them in the same package */ 1881 return devm_phy_package_join(&phydev->mdio.dev, phydev, 1882 phydev->mdio.addr & ~3, 0); 1883 } 1884 1885 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1886 { 1887 int val; 1888 1889 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1890 val = phy_read(phydev, 0x13); 1891 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1892 1893 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1894 } 1895 1896 /* On internal PHY's MMD reads over C22 always return 0. 1897 * Check a MMD register which is known to be non-zero. 1898 */ 1899 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1900 { 1901 int val; 1902 1903 phy_lock_mdio_bus(phydev); 1904 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1905 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1906 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1907 val = __phy_read(phydev, MII_MMD_DATA); 1908 phy_unlock_mdio_bus(phydev); 1909 1910 return val > 0; 1911 } 1912 1913 static int rtlgen_match_phy_device(struct phy_device *phydev, 1914 const struct phy_driver *phydrv) 1915 { 1916 return phydev->phy_id == RTL_GENERIC_PHYID && 1917 !rtlgen_supports_2_5gbps(phydev); 1918 } 1919 1920 static int rtl8226_match_phy_device(struct phy_device *phydev, 1921 const struct phy_driver *phydrv) 1922 { 1923 return phydev->phy_id == RTL_GENERIC_PHYID && 1924 rtlgen_supports_2_5gbps(phydev) && 1925 rtlgen_supports_mmd(phydev); 1926 } 1927 1928 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1929 bool is_c45) 1930 { 1931 if (phydev->is_c45) 1932 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1933 else 1934 return !is_c45 && (id == phydev->phy_id); 1935 } 1936 1937 static int rtl8221b_match_phy_device(struct phy_device *phydev, 1938 const struct phy_driver *phydrv) 1939 { 1940 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1941 } 1942 1943 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 1944 const struct phy_driver *phydrv) 1945 { 1946 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 1947 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1948 } 1949 1950 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 1951 const struct phy_driver *phydrv) 1952 { 1953 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 1954 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 1955 } 1956 1957 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 1958 const struct phy_driver *phydrv) 1959 { 1960 if (phydev->is_c45) 1961 return false; 1962 1963 switch (phydev->phy_id) { 1964 case RTL_GENERIC_PHYID: 1965 case RTL_8221B: 1966 case RTL_8251B: 1967 case RTL_8261C: 1968 case 0x001cc841: 1969 break; 1970 default: 1971 return false; 1972 } 1973 1974 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1975 } 1976 1977 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 1978 const struct phy_driver *phydrv) 1979 { 1980 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1981 } 1982 1983 static int rtlgen_resume(struct phy_device *phydev) 1984 { 1985 int ret = genphy_resume(phydev); 1986 1987 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1988 msleep(20); 1989 1990 return ret; 1991 } 1992 1993 static int rtlgen_c45_resume(struct phy_device *phydev) 1994 { 1995 int ret = genphy_c45_pma_resume(phydev); 1996 1997 msleep(20); 1998 1999 return ret; 2000 } 2001 2002 static int rtl9000a_config_init(struct phy_device *phydev) 2003 { 2004 phydev->autoneg = AUTONEG_DISABLE; 2005 phydev->speed = SPEED_100; 2006 phydev->duplex = DUPLEX_FULL; 2007 2008 return 0; 2009 } 2010 2011 static int rtl9000a_config_aneg(struct phy_device *phydev) 2012 { 2013 int ret; 2014 u16 ctl = 0; 2015 2016 switch (phydev->master_slave_set) { 2017 case MASTER_SLAVE_CFG_MASTER_FORCE: 2018 ctl |= CTL1000_AS_MASTER; 2019 break; 2020 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2021 break; 2022 case MASTER_SLAVE_CFG_UNKNOWN: 2023 case MASTER_SLAVE_CFG_UNSUPPORTED: 2024 return 0; 2025 default: 2026 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2027 return -EOPNOTSUPP; 2028 } 2029 2030 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 2031 if (ret == 1) 2032 ret = genphy_soft_reset(phydev); 2033 2034 return ret; 2035 } 2036 2037 static int rtl9000a_read_status(struct phy_device *phydev) 2038 { 2039 int ret; 2040 2041 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 2042 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2043 2044 ret = genphy_update_link(phydev); 2045 if (ret) 2046 return ret; 2047 2048 ret = phy_read(phydev, MII_CTRL1000); 2049 if (ret < 0) 2050 return ret; 2051 if (ret & CTL1000_AS_MASTER) 2052 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 2053 else 2054 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 2055 2056 ret = phy_read(phydev, MII_STAT1000); 2057 if (ret < 0) 2058 return ret; 2059 if (ret & LPA_1000MSRES) 2060 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 2061 else 2062 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2063 2064 return 0; 2065 } 2066 2067 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2068 { 2069 int err; 2070 2071 err = phy_read(phydev, RTL8211F_INSR); 2072 2073 return (err < 0) ? err : 0; 2074 } 2075 2076 static int rtl9000a_config_intr(struct phy_device *phydev) 2077 { 2078 u16 val; 2079 int err; 2080 2081 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2082 err = rtl9000a_ack_interrupt(phydev); 2083 if (err) 2084 return err; 2085 2086 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2087 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2088 } else { 2089 val = ~0; 2090 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2091 if (err) 2092 return err; 2093 2094 err = rtl9000a_ack_interrupt(phydev); 2095 } 2096 2097 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2098 } 2099 2100 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2101 { 2102 int irq_status; 2103 2104 irq_status = phy_read(phydev, RTL8211F_INSR); 2105 if (irq_status < 0) { 2106 phy_error(phydev); 2107 return IRQ_NONE; 2108 } 2109 2110 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2111 return IRQ_NONE; 2112 2113 phy_trigger_machine(phydev); 2114 2115 return IRQ_HANDLED; 2116 } 2117 2118 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 2119 { 2120 int err; 2121 2122 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 2123 2124 return (err < 0) ? err : 0; 2125 } 2126 2127 static int rtl8221b_config_intr(struct phy_device *phydev) 2128 { 2129 int err; 2130 2131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2132 err = rtl8221b_ack_interrupt(phydev); 2133 if (err) 2134 return err; 2135 2136 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 2137 RTL8221B_VND2_INER_LINK_STATUS); 2138 } else { 2139 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2140 RTL8221B_VND2_INER, 0); 2141 if (err) 2142 return err; 2143 2144 err = rtl8221b_ack_interrupt(phydev); 2145 } 2146 2147 return err; 2148 } 2149 2150 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 2151 { 2152 int err; 2153 2154 err = rtl8221b_ack_interrupt(phydev); 2155 if (err) { 2156 phy_error(phydev); 2157 return IRQ_NONE; 2158 } 2159 2160 phy_trigger_machine(phydev); 2161 2162 return IRQ_HANDLED; 2163 } 2164 2165 static int rtlgen_sfp_get_features(struct phy_device *phydev) 2166 { 2167 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2168 phydev->supported); 2169 2170 /* set default mode */ 2171 phydev->speed = SPEED_10000; 2172 phydev->duplex = DUPLEX_FULL; 2173 2174 phydev->port = PORT_FIBRE; 2175 2176 return 0; 2177 } 2178 2179 static int rtlgen_sfp_read_status(struct phy_device *phydev) 2180 { 2181 int val, err; 2182 2183 err = genphy_update_link(phydev); 2184 if (err) 2185 return err; 2186 2187 if (!phydev->link) 2188 return 0; 2189 2190 val = phy_read(phydev, RTL_PHYSR); 2191 if (val < 0) 2192 return val; 2193 2194 rtlgen_decode_physr(phydev, val); 2195 2196 return 0; 2197 } 2198 2199 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 2200 { 2201 return 0; 2202 } 2203 2204 static struct phy_driver realtek_drvs[] = { 2205 { 2206 PHY_ID_MATCH_EXACT(0x00008201), 2207 .name = "RTL8201CP Ethernet", 2208 .read_page = rtl821x_read_page, 2209 .write_page = rtl821x_write_page, 2210 }, { 2211 PHY_ID_MATCH_EXACT(0x001cc816), 2212 .name = "RTL8201F Fast Ethernet", 2213 .config_intr = &rtl8201_config_intr, 2214 .handle_interrupt = rtl8201_handle_interrupt, 2215 .suspend = genphy_suspend, 2216 .resume = genphy_resume, 2217 .read_page = rtl821x_read_page, 2218 .write_page = rtl821x_write_page, 2219 }, { 2220 PHY_ID_MATCH_MODEL(0x001cc880), 2221 .name = "RTL8208 Fast Ethernet", 2222 .read_mmd = genphy_read_mmd_unsupported, 2223 .write_mmd = genphy_write_mmd_unsupported, 2224 .suspend = genphy_suspend, 2225 .resume = genphy_resume, 2226 .read_page = rtl821x_read_page, 2227 .write_page = rtl821x_write_page, 2228 }, { 2229 PHY_ID_MATCH_EXACT(0x001cc910), 2230 .name = "RTL8211 Gigabit Ethernet", 2231 .config_aneg = rtl8211_config_aneg, 2232 .read_mmd = &genphy_read_mmd_unsupported, 2233 .write_mmd = &genphy_write_mmd_unsupported, 2234 .read_page = rtl821x_read_page, 2235 .write_page = rtl821x_write_page, 2236 }, { 2237 PHY_ID_MATCH_EXACT(0x001cc912), 2238 .name = "RTL8211B Gigabit Ethernet", 2239 .config_intr = &rtl8211b_config_intr, 2240 .handle_interrupt = rtl821x_handle_interrupt, 2241 .read_mmd = &genphy_read_mmd_unsupported, 2242 .write_mmd = &genphy_write_mmd_unsupported, 2243 .suspend = rtl8211b_suspend, 2244 .resume = rtl8211b_resume, 2245 .read_page = rtl821x_read_page, 2246 .write_page = rtl821x_write_page, 2247 }, { 2248 PHY_ID_MATCH_EXACT(0x001cc913), 2249 .name = "RTL8211C Gigabit Ethernet", 2250 .config_init = rtl8211c_config_init, 2251 .read_mmd = &genphy_read_mmd_unsupported, 2252 .write_mmd = &genphy_write_mmd_unsupported, 2253 .read_page = rtl821x_read_page, 2254 .write_page = rtl821x_write_page, 2255 }, { 2256 PHY_ID_MATCH_EXACT(0x001cc914), 2257 .name = "RTL8211DN Gigabit Ethernet", 2258 .config_intr = rtl8211e_config_intr, 2259 .handle_interrupt = rtl821x_handle_interrupt, 2260 .suspend = genphy_suspend, 2261 .resume = genphy_resume, 2262 .read_page = rtl821x_read_page, 2263 .write_page = rtl821x_write_page, 2264 }, { 2265 PHY_ID_MATCH_EXACT(0x001cc915), 2266 .name = "RTL8211E Gigabit Ethernet", 2267 .config_init = &rtl8211e_config_init, 2268 .config_intr = &rtl8211e_config_intr, 2269 .handle_interrupt = rtl821x_handle_interrupt, 2270 .suspend = genphy_suspend, 2271 .resume = genphy_resume, 2272 .read_page = rtl821x_read_page, 2273 .write_page = rtl821x_write_page, 2274 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2275 .led_hw_control_get = rtl8211e_led_hw_control_get, 2276 .led_hw_control_set = rtl8211e_led_hw_control_set, 2277 }, { 2278 PHY_ID_MATCH_EXACT(0x001cc916), 2279 .name = "RTL8211F Gigabit Ethernet", 2280 .probe = rtl8211f_probe, 2281 .config_init = &rtl8211f_config_init, 2282 .read_status = rtlgen_read_status, 2283 .config_intr = &rtl8211f_config_intr, 2284 .handle_interrupt = rtl8211f_handle_interrupt, 2285 .set_wol = rtl8211f_set_wol, 2286 .get_wol = rtl8211f_get_wol, 2287 .suspend = rtl8211f_suspend, 2288 .resume = rtl8211f_resume, 2289 .read_page = rtl821x_read_page, 2290 .write_page = rtl821x_write_page, 2291 .flags = PHY_ALWAYS_CALL_SUSPEND, 2292 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2293 .led_hw_control_get = rtl8211f_led_hw_control_get, 2294 .led_hw_control_set = rtl8211f_led_hw_control_set, 2295 }, { 2296 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 2297 .name = "RTL8211F-VD Gigabit Ethernet", 2298 .probe = rtl821x_probe, 2299 .config_init = &rtl8211f_config_init, 2300 .read_status = rtlgen_read_status, 2301 .config_intr = &rtl8211f_config_intr, 2302 .handle_interrupt = rtl8211f_handle_interrupt, 2303 .suspend = rtl821x_suspend, 2304 .resume = rtl821x_resume, 2305 .read_page = rtl821x_read_page, 2306 .write_page = rtl821x_write_page, 2307 .flags = PHY_ALWAYS_CALL_SUSPEND, 2308 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 2309 .led_hw_control_get = rtl8211f_led_hw_control_get, 2310 .led_hw_control_set = rtl8211f_led_hw_control_set, 2311 }, { 2312 .name = "Generic FE-GE Realtek PHY", 2313 .match_phy_device = rtlgen_match_phy_device, 2314 .read_status = rtlgen_read_status, 2315 .suspend = genphy_suspend, 2316 .resume = rtlgen_resume, 2317 .read_page = rtl821x_read_page, 2318 .write_page = rtl821x_write_page, 2319 .read_mmd = rtlgen_read_mmd, 2320 .write_mmd = rtlgen_write_mmd, 2321 }, { 2322 .name = "RTL8226 2.5Gbps PHY", 2323 .match_phy_device = rtl8226_match_phy_device, 2324 .get_features = rtl822x_get_features, 2325 .config_aneg = rtl822x_config_aneg, 2326 .read_status = rtl822x_read_status, 2327 .suspend = genphy_suspend, 2328 .resume = rtlgen_resume, 2329 .read_page = rtl821x_read_page, 2330 .write_page = rtl821x_write_page, 2331 .read_mmd = rtl822xb_read_mmd, 2332 .write_mmd = rtl822xb_write_mmd, 2333 }, { 2334 .match_phy_device = rtl8221b_match_phy_device, 2335 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 2336 .get_features = rtl822x_get_features, 2337 .config_aneg = rtl822x_config_aneg, 2338 .config_init = rtl822xb_config_init, 2339 .inband_caps = rtl822x_inband_caps, 2340 .config_inband = rtl822x_config_inband, 2341 .get_rate_matching = rtl822xb_get_rate_matching, 2342 .read_status = rtl822xb_read_status, 2343 .suspend = genphy_suspend, 2344 .resume = rtlgen_resume, 2345 .read_page = rtl821x_read_page, 2346 .write_page = rtl821x_write_page, 2347 .read_mmd = rtl822xb_read_mmd, 2348 .write_mmd = rtl822xb_write_mmd, 2349 }, { 2350 PHY_ID_MATCH_EXACT(0x001cc838), 2351 .name = "RTL8226-CG 2.5Gbps PHY", 2352 .soft_reset = rtl822x_c45_soft_reset, 2353 .get_features = rtl822x_c45_get_features, 2354 .config_aneg = rtl822x_c45_config_aneg, 2355 .config_init = rtl822x_config_init, 2356 .inband_caps = rtl822x_inband_caps, 2357 .config_inband = rtl822x_config_inband, 2358 .read_status = rtl822xb_c45_read_status, 2359 .suspend = genphy_c45_pma_suspend, 2360 .resume = rtlgen_c45_resume, 2361 .read_mmd = rtl822xb_read_mmd, 2362 .write_mmd = rtl822xb_write_mmd, 2363 }, { 2364 PHY_ID_MATCH_EXACT(0x001cc848), 2365 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 2366 .get_features = rtl822x_get_features, 2367 .config_aneg = rtl822x_config_aneg, 2368 .config_init = rtl822xb_config_init, 2369 .inband_caps = rtl822x_inband_caps, 2370 .config_inband = rtl822x_config_inband, 2371 .get_rate_matching = rtl822xb_get_rate_matching, 2372 .read_status = rtl822xb_read_status, 2373 .suspend = genphy_suspend, 2374 .resume = rtlgen_resume, 2375 .read_page = rtl821x_read_page, 2376 .write_page = rtl821x_write_page, 2377 .read_mmd = rtl822xb_read_mmd, 2378 .write_mmd = rtl822xb_write_mmd, 2379 }, { 2380 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 2381 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 2382 .config_intr = rtl8221b_config_intr, 2383 .handle_interrupt = rtl8221b_handle_interrupt, 2384 .probe = rtl822x_probe, 2385 .config_init = rtl822xb_config_init, 2386 .inband_caps = rtl822x_inband_caps, 2387 .config_inband = rtl822x_config_inband, 2388 .get_rate_matching = rtl822xb_get_rate_matching, 2389 .get_features = rtl822x_c45_get_features, 2390 .config_aneg = rtl822x_c45_config_aneg, 2391 .read_status = rtl822xb_c45_read_status, 2392 .suspend = genphy_c45_pma_suspend, 2393 .resume = rtlgen_c45_resume, 2394 .read_page = rtl821x_read_page, 2395 .write_page = rtl821x_write_page, 2396 .read_mmd = rtl822xb_read_mmd, 2397 .write_mmd = rtl822xb_write_mmd, 2398 }, { 2399 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 2400 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 2401 .config_intr = rtl8221b_config_intr, 2402 .handle_interrupt = rtl8221b_handle_interrupt, 2403 .probe = rtl822x_probe, 2404 .config_init = rtl822xb_config_init, 2405 .inband_caps = rtl822x_inband_caps, 2406 .config_inband = rtl822x_config_inband, 2407 .get_rate_matching = rtl822xb_get_rate_matching, 2408 .get_features = rtl822x_c45_get_features, 2409 .config_aneg = rtl822x_c45_config_aneg, 2410 .read_status = rtl822xb_c45_read_status, 2411 .suspend = genphy_c45_pma_suspend, 2412 .resume = rtlgen_c45_resume, 2413 .read_page = rtl821x_read_page, 2414 .write_page = rtl821x_write_page, 2415 .read_mmd = rtl822xb_read_mmd, 2416 .write_mmd = rtl822xb_write_mmd, 2417 }, { 2418 .match_phy_device = rtl8251b_c45_match_phy_device, 2419 .name = "RTL8251B 5Gbps PHY", 2420 .probe = rtl822x_probe, 2421 .get_features = rtl822x_get_features, 2422 .config_aneg = rtl822x_config_aneg, 2423 .read_status = rtl822x_read_status, 2424 .suspend = genphy_suspend, 2425 .resume = rtlgen_resume, 2426 .read_page = rtl821x_read_page, 2427 .write_page = rtl821x_write_page, 2428 }, { 2429 .match_phy_device = rtl_internal_nbaset_match_phy_device, 2430 .name = "Realtek Internal NBASE-T PHY", 2431 .flags = PHY_IS_INTERNAL, 2432 .probe = rtl822x_probe, 2433 .get_features = rtl822x_get_features, 2434 .config_aneg = rtl822x_config_aneg, 2435 .read_status = rtl822x_read_status, 2436 .suspend = genphy_suspend, 2437 .resume = rtlgen_resume, 2438 .read_page = rtl821x_read_page, 2439 .write_page = rtl821x_write_page, 2440 .read_mmd = rtl822x_read_mmd, 2441 .write_mmd = rtl822x_write_mmd, 2442 }, { 2443 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 2444 .name = "Realtek SFP PHY Mode", 2445 .flags = PHY_IS_INTERNAL, 2446 .probe = rtl822x_probe, 2447 .get_features = rtlgen_sfp_get_features, 2448 .config_aneg = rtlgen_sfp_config_aneg, 2449 .read_status = rtlgen_sfp_read_status, 2450 .suspend = genphy_suspend, 2451 .resume = rtlgen_resume, 2452 .read_page = rtl821x_read_page, 2453 .write_page = rtl821x_write_page, 2454 .read_mmd = rtl822x_read_mmd, 2455 .write_mmd = rtl822x_write_mmd, 2456 }, { 2457 PHY_ID_MATCH_EXACT(0x001ccad0), 2458 .name = "RTL8224 2.5Gbps PHY", 2459 .flags = PHY_POLL_CABLE_TEST, 2460 .probe = rtl8224_probe, 2461 .config_init = rtl8224_config_init, 2462 .get_features = rtl822x_c45_get_features, 2463 .config_aneg = rtl822x_c45_config_aneg, 2464 .read_status = rtl822x_c45_read_status, 2465 .suspend = genphy_c45_pma_suspend, 2466 .resume = rtlgen_c45_resume, 2467 .cable_test_start = rtl8224_cable_test_start, 2468 .cable_test_get_status = rtl8224_cable_test_get_status, 2469 }, { 2470 PHY_ID_MATCH_EXACT(0x001cc961), 2471 .name = "RTL8366RB Gigabit Ethernet", 2472 .config_init = &rtl8366rb_config_init, 2473 /* These interrupts are handled by the irq controller 2474 * embedded inside the RTL8366RB, they get unmasked when the 2475 * irq is requested and ACKed by reading the status register, 2476 * which is done by the irqchip code. 2477 */ 2478 .config_intr = genphy_no_config_intr, 2479 .handle_interrupt = genphy_handle_interrupt_no_ack, 2480 .suspend = genphy_suspend, 2481 .resume = genphy_resume, 2482 }, { 2483 PHY_ID_MATCH_EXACT(0x001ccb00), 2484 .name = "RTL9000AA_RTL9000AN Ethernet", 2485 .features = PHY_BASIC_T1_FEATURES, 2486 .config_init = rtl9000a_config_init, 2487 .config_aneg = rtl9000a_config_aneg, 2488 .read_status = rtl9000a_read_status, 2489 .config_intr = rtl9000a_config_intr, 2490 .handle_interrupt = rtl9000a_handle_interrupt, 2491 .suspend = genphy_suspend, 2492 .resume = genphy_resume, 2493 .read_page = rtl821x_read_page, 2494 .write_page = rtl821x_write_page, 2495 }, { 2496 PHY_ID_MATCH_EXACT(0x001cc942), 2497 .name = "RTL8365MB-VC Gigabit Ethernet", 2498 /* Interrupt handling analogous to RTL8366RB */ 2499 .config_intr = genphy_no_config_intr, 2500 .handle_interrupt = genphy_handle_interrupt_no_ack, 2501 .suspend = genphy_suspend, 2502 .resume = genphy_resume, 2503 }, { 2504 PHY_ID_MATCH_EXACT(0x001cc960), 2505 .name = "RTL8366S Gigabit Ethernet", 2506 .suspend = genphy_suspend, 2507 .resume = genphy_resume, 2508 .read_mmd = genphy_read_mmd_unsupported, 2509 .write_mmd = genphy_write_mmd_unsupported, 2510 }, 2511 }; 2512 2513 module_phy_driver(realtek_drvs); 2514 2515 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 2516 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 2517 { } 2518 }; 2519 2520 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 2521