1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/crc32.h> 12 #include <linux/ethtool_netlink.h> 13 #include <linux/firmware.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 #include <linux/pm_wakeirq.h> 17 #include <linux/netdevice.h> 18 #include <linux/module.h> 19 #include <linux/delay.h> 20 #include <linux/clk.h> 21 #include <linux/string_choices.h> 22 #include <net/phy/realtek_phy.h> 23 24 #include "../phylib.h" 25 #include "realtek.h" 26 27 #define RTL8201F_IER_PAGE 0x07 28 #define RTL8201F_IER 0x13 29 #define RTL8201F_IER_LINK BIT(13) 30 #define RTL8201F_IER_DUPLEX BIT(12) 31 #define RTL8201F_IER_ANERR BIT(11) 32 #define RTL8201F_IER_MASK (RTL8201F_IER_ANERR | \ 33 RTL8201F_IER_DUPLEX | \ 34 RTL8201F_IER_LINK) 35 36 #define RTL8201F_ISR 0x1e 37 #define RTL8201F_ISR_ANERR BIT(15) 38 #define RTL8201F_ISR_DUPLEX BIT(13) 39 #define RTL8201F_ISR_LINK BIT(11) 40 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 41 RTL8201F_ISR_DUPLEX | \ 42 RTL8201F_ISR_LINK) 43 44 #define RTL821x_INER 0x12 45 #define RTL8211B_INER_SPEED BIT(14) 46 #define RTL8211B_INER_DUPLEX BIT(13) 47 #define RTL8211B_INER_LINK_STATUS BIT(10) 48 #define RTL8211B_INER_INIT (RTL8211B_INER_SPEED | \ 49 RTL8211B_INER_DUPLEX | \ 50 RTL8211B_INER_LINK_STATUS) 51 #define RTL8211E_INER_LINK_STATUS BIT(10) 52 #define RTL8211F_INER_PME BIT(7) 53 #define RTL8211F_INER_LINK_STATUS BIT(4) 54 55 #define RTL821x_INSR 0x13 56 57 #define RTL821x_EXT_PAGE_SELECT 0x1e 58 59 #define RTL821x_PAGE_SELECT 0x1f 60 #define RTL821x_SET_EXT_PAGE 0x07 61 62 /* RTL8211E extension page 44/0x2c */ 63 #define RTL8211E_LEDCR_EXT_PAGE 0x2c 64 #define RTL8211E_LEDCR1 0x1a 65 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4) 66 #define RTL8211E_LEDCR1_MASK BIT(4) 67 #define RTL8211E_LEDCR1_SHIFT 1 68 69 #define RTL8211E_LEDCR2 0x1c 70 #define RTL8211E_LEDCR2_LINK_1000 BIT(2) 71 #define RTL8211E_LEDCR2_LINK_100 BIT(1) 72 #define RTL8211E_LEDCR2_LINK_10 BIT(0) 73 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0) 74 #define RTL8211E_LEDCR2_SHIFT 4 75 76 /* RTL8211E extension page 164/0xa4 */ 77 #define RTL8211E_RGMII_EXT_PAGE 0xa4 78 #define RTL8211E_RGMII_DELAY 0x1c 79 #define RTL8211E_CTRL_DELAY BIT(13) 80 #define RTL8211E_TX_DELAY BIT(12) 81 #define RTL8211E_RX_DELAY BIT(11) 82 #define RTL8211E_DELAY_MASK GENMASK(13, 11) 83 84 /* RTL8211F PHY configuration */ 85 #define RTL8211F_PHYCR1 0x18 86 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 87 #define RTL8211F_ALDPS_ENABLE BIT(2) 88 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 89 90 #define RTL8211F_PHYCR2 0x19 91 #define RTL8211F_CLKOUT_EN BIT(0) 92 #define RTL8211F_SYSCLK_SSC_EN BIT(3) 93 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5) 94 #define RTL8211F_CLKOUT_SSC_EN BIT(7) 95 #define RTL8211F_CLKOUT_SSC_CAP GENMASK(13, 12) 96 97 #define RTL8211F_INSR 0x1d 98 99 /* RTL8211F SSC settings */ 100 #define RTL8211F_SSC_PAGE 0xc44 101 #define RTL8211F_SSC_RXC 0x13 102 #define RTL8211F_SSC_SYSCLK 0x17 103 104 /* RTL8211F LED configuration */ 105 #define RTL8211F_LEDCR_PAGE 0xd04 106 #define RTL8211F_LEDCR 0x10 107 #define RTL8211F_LEDCR_MODE BIT(15) 108 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 109 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 110 #define RTL8211F_LEDCR_LINK_100 BIT(1) 111 #define RTL8211F_LEDCR_LINK_10 BIT(0) 112 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 113 #define RTL8211F_LEDCR_SHIFT 5 114 115 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values 116 * to undocumented register pages. The names here do not reflect the datasheet. 117 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2. 118 */ 119 #define RTL8211FVD_CLKOUT_PAGE 0xd05 120 #define RTL8211FVD_CLKOUT_REG 0x11 121 #define RTL8211FVD_CLKOUT_EN BIT(8) 122 123 /* RTL8211F RGMII configuration */ 124 #define RTL8211F_RGMII_PAGE 0xd08 125 126 #define RTL8211F_TXCR 0x11 127 #define RTL8211F_TX_DELAY BIT(8) 128 129 #define RTL8211F_RXCR 0x15 130 #define RTL8211F_RX_DELAY BIT(3) 131 132 /* RTL8211F WOL settings */ 133 #define RTL8211F_WOL_PAGE 0xd8a 134 #define RTL8211F_WOL_SETTINGS_EVENTS 16 135 #define RTL8211F_WOL_EVENT_MAGIC BIT(12) 136 #define RTL8211F_WOL_RST_RMSQ 17 137 #define RTL8211F_WOL_RG_RSTB BIT(15) 138 #define RTL8211F_WOL_RMSQ 0x1fff 139 140 /* RTL8211F Unique phyiscal and multicast address (WOL) */ 141 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c 142 #define RTL8211F_PHYSICAL_ADDR_WORD0 16 143 #define RTL8211F_PHYSICAL_ADDR_WORD1 17 144 #define RTL8211F_PHYSICAL_ADDR_WORD2 18 145 146 #define RTL8261X_EXT_ADDR_REG 0xa436 147 #define RTL8261X_EXT_DATA_REG 0xa438 148 #define RTL_8261X_SUB_PHY_ID_ADDR 0x801d 149 150 #define RTL822X_VND1_SERDES_OPTION 0x697a 151 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 152 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 153 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 154 155 #define RTL822X_VND1_SERDES_CTRL3 0x7580 156 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 157 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 158 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 159 160 #define RTL822X_VND1_SERDES_CMD 0x7587 161 #define RTL822X_VND1_SERDES_CMD_WRITE BIT(1) 162 #define RTL822X_VND1_SERDES_CMD_BUSY BIT(0) 163 #define RTL822X_VND1_SERDES_ADDR 0x7588 164 #define RTL822X_VND1_SERDES_ADDR_AUTONEG 0x2 165 #define RTL822X_VND1_SERDES_INBAND_DISABLE 0x71d0 166 #define RTL822X_VND1_SERDES_INBAND_ENABLE 0x70d0 167 #define RTL822X_VND1_SERDES_DATA 0x7589 168 169 #define RTL822X_VND2_TO_PAGE(reg) ((reg) >> 4) 170 #define RTL822X_VND2_TO_PAGE_REG(reg) (16 + (((reg) & GENMASK(3, 0)) >> 1)) 171 #define RTL822X_VND2_TO_C22_REG(reg) (((reg) - 0xa400) / 2) 172 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 173 174 #define RTL8221B_VND2_INER 0xa4d2 175 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4) 176 177 #define RTL8221B_VND2_INSR 0xa4d4 178 179 #define RTL822X_VND2_LED(x) (0xd032 + ((x) * 2)) 180 #define RTL822X_VND2_LCR_LINK_10 BIT(0) 181 #define RTL822X_VND2_LCR_LINK_100 BIT(1) 182 #define RTL822X_VND2_LCR_LINK_1000 BIT(2) 183 #define RTL822X_VND2_LCR_LINK_2500 BIT(5) 184 185 #define RTL822X_VND2_LCR6 0xd040 186 #define RTL822X_VND2_LED_ACT(x) BIT(x) 187 188 #define RTL822X_VND2_LCR7 0xd044 189 #define RTL822X_VND2_LED_POLAR(x) BIT(x) 190 191 #define RTL8224_MII_RTCT 0x11 192 #define RTL8224_MII_RTCT_ENABLE BIT(0) 193 #define RTL8224_MII_RTCT_PAIR_A BIT(4) 194 #define RTL8224_MII_RTCT_PAIR_B BIT(5) 195 #define RTL8224_MII_RTCT_PAIR_C BIT(6) 196 #define RTL8224_MII_RTCT_PAIR_D BIT(7) 197 #define RTL8224_MII_RTCT_DONE BIT(15) 198 199 #define RTL8224_MII_SRAM_ADDR 0x1b 200 #define RTL8224_MII_SRAM_DATA 0x1c 201 202 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4) 203 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0) 204 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3) 205 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4) 206 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5) 207 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6) 208 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7) 209 210 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) 211 212 #define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 213 #define RTL8224_VND1_MDI_POLARITY_SWAP 0xa94 214 215 #define RTL8226_VND1_UNKNOWN_6A21 0x6a21 216 #define RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN BIT(5) 217 218 #define RTL8226_VND2_UNKNOWN_D068 0xd068 219 #define RTL8226_VND2_UNKNOWN_D068_MDI_SWAP_FLAG BIT(1) 220 #define RTL8226_VND2_UNKNOWN_D068_PAIR_SEL GENMASK(4, 3) 221 #define RTL8226_VND2_ADCCAL_OFFSET 0xd06a 222 223 #define RTL8226_VND2_RG_LPF_CAP_XG_P0_P1 0xbd5a 224 #define RTL8226_VND2_RG_LPF_CAP_XG_P2_P3 0xbd5c 225 #define RTL8226_VND2_RG_LPF_CAP_P0_P1 0xbc18 226 #define RTL8226_VND2_RG_LPF_CAP_P2_P3 0xbc1a 227 #define RTL8226_RG_LPF_CAP_PAIR_A_MASK GENMASK(4, 0) 228 #define RTL8226_RG_LPF_CAP_PAIR_B_MASK GENMASK(12, 8) 229 230 #define RTL8366RB_POWER_SAVE 0x15 231 #define RTL8366RB_POWER_SAVE_ON BIT(12) 232 233 #define RTL9000A_GINMR 0x14 234 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 235 236 #define RTL_PHYSR MII_RESV2 237 #define RTL_PHYSR_DUPLEX BIT(3) 238 #define RTL_PHYSR_SPEEDL GENMASK(5, 4) 239 #define RTL_PHYSR_SPEEDH GENMASK(10, 9) 240 #define RTL_PHYSR_MASTER BIT(11) 241 #define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH) 242 243 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 244 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 245 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 246 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 247 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 248 #define RTL_MDIO_PMA_SPEED 0xa616 249 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 250 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 251 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 252 253 #define RTL_GENERIC_PHYID 0x001cc800 254 #define RTL_8211FVD_PHYID 0x001cc878 255 #define RTL_8221B 0x001cc840 256 #define RTL_8221B_VB_CG 0x001cc849 257 #define RTL_8221B_VM_CG 0x001cc84a 258 #define RTL_8251B 0x001cc862 259 #define RTL_8261C 0x001cc890 260 #define RTL_8261C_CG 0x001cc898 261 262 #define RTL8261C_CE_MODEL 0x00 263 #define RTL8261D_MODEL 0x81 264 #define RTL8261X_INT_AUTONEG_ERROR BIT(0) 265 #define RTL8261X_INT_PAGE_RECV BIT(2) 266 #define RTL8261X_INT_AUTONEG_DONE BIT(3) 267 #define RTL8261X_INT_LINK_CHG BIT(4) 268 #define RTL8261X_INT_PHY_REG_ACCESS BIT(5) 269 #define RTL8261X_INT_PME BIT(7) 270 #define RTL8261X_INT_ALDPS_CHG BIT(9) 271 #define RTL8261X_INT_JABBER BIT(10) 272 273 #define RTL8261X_INT_MASK_DEFAULT (RTL8261X_INT_AUTONEG_DONE | \ 274 RTL8261X_INT_LINK_CHG | \ 275 RTL8261X_INT_AUTONEG_ERROR | \ 276 RTL8261X_INT_JABBER) 277 278 #define RTL8261X_INT_MASK_ALL (RTL8261X_INT_AUTONEG_ERROR | \ 279 RTL8261X_INT_PAGE_RECV | \ 280 RTL8261X_INT_AUTONEG_DONE | \ 281 RTL8261X_INT_LINK_CHG | \ 282 RTL8261X_INT_PHY_REG_ACCESS | \ 283 RTL8261X_INT_PME | \ 284 RTL8261X_INT_ALDPS_CHG | \ 285 RTL8261X_INT_JABBER) 286 287 #define FW_MAIN_MAGIC 0x52544C38 288 #define FW_SUB_MAGIC_8261C 0x32363143 289 #define RTL8261X_POLL_TIMEOUT_MS 100 290 #define RTL8261X_MAX_MMD_DEV 31 291 292 #define RTL8261C_CE_FW_NAME "rtl_nic/rtl8261c.bin" 293 MODULE_FIRMWARE(RTL8261C_CE_FW_NAME); 294 295 enum rtl8261x_fw_op { 296 OP_WRITE = 0x00, /* Write */ 297 OP_POLL = 0x02, /* Polling */ 298 }; 299 300 struct rtl8261x_fw_header { 301 __le32 main_magic; /* Main magic number */ 302 __le32 sub_magic; /* Sub magic number */ 303 __le16 version_major; /* Major version */ 304 __le16 version_minor; /* Minor version */ 305 __le16 num_entries; /* Number of entries */ 306 __le16 reserved; /* Reserved */ 307 __le32 crc32; /* CRC32 checksum */ 308 }; 309 310 struct rtl8261x_fw_entry { 311 __u8 type; /* Operation type (OP_*) */ 312 __u8 dev; /* MMD device */ 313 __le16 addr; /* Register address */ 314 __u8 msb; /* MSB bit position */ 315 __u8 lsb; /* LSB bit position */ 316 __le16 value; /* Value to write/compare */ 317 __le16 timeout_ms; /* Poll timeout in milliseconds */ 318 __u8 poll_set; /* Poll until equal (1) or not equal (0) */ 319 __u8 reserved; /* Reserved */ 320 }; 321 322 #define FW_HEADER_SIZE sizeof(struct rtl8261x_fw_header) 323 #define FW_ENTRY_SIZE sizeof(struct rtl8261x_fw_entry) 324 325 /* RTL8211E and RTL8211F support up to three LEDs */ 326 #define RTL8211x_LED_COUNT 3 327 328 MODULE_DESCRIPTION("Realtek PHY driver"); 329 MODULE_AUTHOR("Johnson Leung"); 330 MODULE_LICENSE("GPL"); 331 332 struct rtl821x_priv { 333 bool enable_aldps; 334 bool disable_clk_out; 335 bool enable_clkout_ssc; 336 bool enable_rxc_ssc; 337 bool enable_sysclk_ssc; 338 struct clk *clk; 339 /* rtl8211f */ 340 u16 iner; 341 }; 342 343 struct rtl8261x_priv { 344 const char *fw_name; 345 bool fw_loaded; 346 }; 347 348 static int rtl821x_read_page(struct phy_device *phydev) 349 { 350 return __phy_read(phydev, RTL821x_PAGE_SELECT); 351 } 352 353 static int rtl821x_write_page(struct phy_device *phydev, int page) 354 { 355 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 356 } 357 358 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, 359 u32 regnum) 360 { 361 int oldpage, ret = 0; 362 363 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 364 if (oldpage >= 0) { 365 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 366 if (ret == 0) 367 ret = __phy_read(phydev, regnum); 368 } 369 370 return phy_restore_page(phydev, oldpage, ret); 371 } 372 373 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, 374 u32 regnum, u16 mask, u16 set) 375 { 376 int oldpage, ret = 0; 377 378 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); 379 if (oldpage >= 0) { 380 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); 381 if (ret == 0) 382 ret = __phy_modify(phydev, regnum, mask, set); 383 } 384 385 return phy_restore_page(phydev, oldpage, ret); 386 } 387 388 static int rtl8261x_probe(struct phy_device *phydev) 389 { 390 struct device *dev = &phydev->mdio.dev; 391 struct rtl8261x_priv *priv; 392 int sub_phy_id, ret; 393 394 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 395 if (!priv) 396 return -ENOMEM; 397 398 phydev->priv = priv; 399 400 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_ADDR_REG, 401 RTL_8261X_SUB_PHY_ID_ADDR); 402 if (ret < 0) 403 return ret; 404 405 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8261X_EXT_DATA_REG); 406 if (ret < 0) 407 return ret; 408 409 sub_phy_id = (ret >> 8) & 0xff; 410 411 switch (sub_phy_id) { 412 case RTL8261C_CE_MODEL: 413 priv->fw_name = RTL8261C_CE_FW_NAME; 414 phydev_info(phydev, "RTL8261C detected (sub_id 0x%02x)\n", sub_phy_id); 415 break; 416 417 case RTL8261D_MODEL: 418 phydev_info(phydev, "RTL8261D detected (sub_id 0x%02x)\n", sub_phy_id); 419 break; 420 421 default: 422 phydev_warn(phydev, "Unknown sub_id 0x%02x, default behavior\n", sub_phy_id); 423 return -ENODEV; 424 } 425 426 return 0; 427 } 428 429 static int rtl8261x_get_features(struct phy_device *phydev) 430 { 431 int ret; 432 433 ret = genphy_c45_pma_read_abilities(phydev); 434 if (ret) 435 return ret; 436 /* 437 * Supplement Multi-Gig speeds that may not be automatically detected 438 * RTL8261X supports 2.5G/5G in addition to standard 10G 439 */ 440 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 441 phydev->supported); 442 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 443 phydev->supported); 444 445 return 0; 446 } 447 448 static int rtl8261x_read_status(struct phy_device *phydev) 449 { 450 int ret, val = 0; 451 452 if (phydev->autoneg == AUTONEG_ENABLE) { 453 ret = genphy_c45_aneg_done(phydev); 454 if (ret < 0) 455 return ret; 456 457 if (ret) { 458 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 459 RTL822X_VND2_C22_REG(MII_STAT1000)); 460 if (val < 0) 461 return val; 462 } 463 } 464 465 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 466 467 ret = genphy_c45_read_status(phydev); 468 if (ret < 0) 469 return ret; 470 471 return 0; 472 } 473 474 static int rtl8261x_verify_firmware(struct phy_device *phydev, const struct firmware *fw) 475 { 476 const struct rtl8261x_fw_header *hdr; 477 u32 main_magic, sub_magic; 478 u32 calc_crc, file_crc; 479 size_t data_len; 480 u16 num_entries; 481 482 if (fw->size < FW_HEADER_SIZE) { 483 phydev_err(phydev, "Firmware too small: %zu bytes\n", fw->size); 484 return -EINVAL; 485 } 486 487 hdr = (const struct rtl8261x_fw_header *)fw->data; 488 489 main_magic = le32_to_cpu(hdr->main_magic); 490 if (main_magic != FW_MAIN_MAGIC) { 491 phydev_err(phydev, "Invalid firmware magic: 0x%08x\n", main_magic); 492 return -EINVAL; 493 } 494 495 sub_magic = le32_to_cpu(hdr->sub_magic); 496 if (sub_magic != FW_SUB_MAGIC_8261C) { 497 phydev_err(phydev, "Invalid sub magic: 0x%08x\n", sub_magic); 498 return -EINVAL; 499 } 500 501 num_entries = le16_to_cpu(hdr->num_entries); 502 data_len = num_entries * FW_ENTRY_SIZE; 503 504 if (fw->size != sizeof(*hdr) + data_len) { 505 phydev_err(phydev, "Firmware size mismatch\n"); 506 return -EINVAL; 507 } 508 509 calc_crc = crc32(~0, fw->data + FW_HEADER_SIZE, data_len) ^ ~0; 510 file_crc = le32_to_cpu(hdr->crc32); 511 512 if (calc_crc != file_crc) { 513 phydev_err(phydev, "CRC32 mismatch: calculated=0x%08x file=0x%08x\n", 514 calc_crc, file_crc); 515 return -EINVAL; 516 } 517 518 return 0; 519 } 520 521 static int rtl8261x_fw_execute_entry(struct phy_device *phydev, 522 const struct rtl8261x_fw_entry *entry) 523 { 524 u16 addr, value, timeout_ms; 525 u8 dev, msb, lsb, poll_set; 526 u32 bits, expect_val; 527 int ret, val; 528 529 dev = entry->dev; 530 addr = le16_to_cpu(entry->addr); 531 msb = entry->msb; 532 lsb = entry->lsb; 533 value = le16_to_cpu(entry->value); 534 timeout_ms = le16_to_cpu(entry->timeout_ms); 535 poll_set = entry->poll_set; 536 537 if (timeout_ms == 0) 538 timeout_ms = RTL8261X_POLL_TIMEOUT_MS; 539 540 if (dev > RTL8261X_MAX_MMD_DEV) { 541 phydev_err(phydev, "invalid firmware MMD device: dev=%u\n", dev); 542 return -EINVAL; 543 } 544 545 if (msb > 15 || lsb > msb) { 546 phydev_err(phydev, "invalid firmware bits: msb=%u, lsb=%u\n", msb, lsb); 547 return -EINVAL; 548 } 549 550 switch (entry->type) { 551 case OP_WRITE: 552 ret = phy_modify_mmd(phydev, dev, addr, 553 GENMASK(msb, lsb), (value << lsb) & GENMASK(msb, lsb)); 554 if (ret) 555 return ret; 556 break; 557 558 case OP_POLL: 559 bits = GENMASK(msb, lsb); 560 expect_val = (value << lsb) & bits; 561 562 if (poll_set) 563 ret = phy_read_mmd_poll_timeout(phydev, dev, addr, val, 564 (val & bits) == expect_val, 565 1000, timeout_ms * 1000, false); 566 else 567 ret = phy_read_mmd_poll_timeout(phydev, dev, addr, val, 568 (val & bits) != expect_val, 569 1000, timeout_ms * 1000, false); 570 if (ret) 571 return ret; 572 break; 573 574 default: 575 return -EINVAL; 576 } 577 578 return 0; 579 } 580 581 static int rtl8261x_fw_load(struct phy_device *phydev) 582 { 583 struct rtl8261x_priv *priv = phydev->priv; 584 const struct rtl8261x_fw_entry *entry; 585 const struct rtl8261x_fw_header *hdr; 586 const struct firmware *fw; 587 int ret, i; 588 589 if (!priv->fw_name) 590 return 0; 591 592 ret = request_firmware(&fw, priv->fw_name, &phydev->mdio.dev); 593 if (ret) { 594 phydev_err(phydev, "Failed to load firmware %s: %d\n", priv->fw_name, ret); 595 return ret; 596 } 597 598 ret = rtl8261x_verify_firmware(phydev, fw); 599 if (ret) 600 goto release_fw; 601 602 hdr = (const struct rtl8261x_fw_header *)fw->data; 603 604 entry = (const struct rtl8261x_fw_entry *)(fw->data + FW_HEADER_SIZE); 605 for (i = 0; i < le16_to_cpu(hdr->num_entries); i++, entry++) { 606 ret = rtl8261x_fw_execute_entry(phydev, entry); 607 if (ret) { 608 phydev_err(phydev, "Entry %d failed: %d\n", i, ret); 609 goto release_fw; 610 } 611 } 612 613 priv->fw_loaded = true; 614 615 release_fw: 616 release_firmware(fw); 617 return ret; 618 } 619 620 static int rtl8261x_config_intr(struct phy_device *phydev) 621 { 622 int ret; 623 624 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 625 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 626 if (ret < 0) 627 return ret; 628 629 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 630 RTL8261X_INT_MASK_DEFAULT); 631 if (ret < 0) 632 return ret; 633 } else { 634 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 0); 635 if (ret < 0) 636 return ret; 637 638 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 639 if (ret < 0) 640 return ret; 641 } 642 643 return 0; 644 } 645 646 static irqreturn_t rtl8261x_handle_interrupt(struct phy_device *phydev) 647 { 648 int irq_status; 649 650 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 651 if (irq_status < 0) { 652 phy_error(phydev); 653 return IRQ_NONE; 654 } 655 656 if (!(irq_status & RTL8261X_INT_MASK_ALL)) 657 return IRQ_NONE; 658 659 if (irq_status & (RTL8261X_INT_LINK_CHG | RTL8261X_INT_AUTONEG_DONE | 660 RTL8261X_INT_AUTONEG_ERROR | RTL8261X_INT_JABBER)) 661 phy_trigger_machine(phydev); 662 663 return IRQ_HANDLED; 664 } 665 666 static int rtl8261x_config_aneg(struct phy_device *phydev) 667 { 668 u16 adv_1g = 0; 669 int ret; 670 671 ret = genphy_c45_config_aneg(phydev); 672 if (ret < 0) 673 return ret; 674 675 if (phydev->autoneg == AUTONEG_DISABLE) 676 return 0; 677 678 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 679 phydev->advertising)) 680 adv_1g = ADVERTISE_1000FULL; 681 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 682 phydev->advertising)) 683 adv_1g |= ADVERTISE_1000HALF; 684 685 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 686 RTL822X_VND2_C22_REG(MII_CTRL1000), 687 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 688 adv_1g); 689 if (ret < 0) 690 return ret; 691 if (ret > 0) 692 return genphy_c45_restart_aneg(phydev); 693 694 return 0; 695 } 696 697 static int rtl8261x_config_init(struct phy_device *phydev) 698 { 699 struct rtl8261x_priv *priv = phydev->priv; 700 701 /* The firmware parameters are preserved across IEEE soft resets and 702 * suspend/resume cycles. Reloading is only necessary after a power 703 * cycle or hard reset. 704 */ 705 if (priv->fw_name && !priv->fw_loaded) 706 return rtl8261x_fw_load(phydev); 707 708 return 0; 709 } 710 711 static int rtl821x_probe(struct phy_device *phydev) 712 { 713 struct device *dev = &phydev->mdio.dev; 714 struct rtl821x_priv *priv; 715 716 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 717 if (!priv) 718 return -ENOMEM; 719 720 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 721 if (IS_ERR(priv->clk)) 722 return dev_err_probe(dev, PTR_ERR(priv->clk), 723 "failed to get phy clock\n"); 724 725 priv->enable_aldps = of_property_read_bool(dev->of_node, 726 "realtek,aldps-enable"); 727 priv->disable_clk_out = of_property_read_bool(dev->of_node, 728 "realtek,clkout-disable"); 729 priv->enable_clkout_ssc = of_property_read_bool(dev->of_node, 730 "realtek,clkout-ssc-enable"); 731 priv->enable_rxc_ssc = of_property_read_bool(dev->of_node, 732 "realtek,rxc-ssc-enable"); 733 priv->enable_sysclk_ssc = of_property_read_bool(dev->of_node, 734 "realtek,sysclk-ssc-enable"); 735 736 phydev->priv = priv; 737 738 return 0; 739 } 740 741 static int rtl8211f_probe(struct phy_device *phydev) 742 { 743 struct device *dev = &phydev->mdio.dev; 744 int ret; 745 746 ret = rtl821x_probe(phydev); 747 if (ret < 0) 748 return ret; 749 750 /* Disable all PME events */ 751 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 752 RTL8211F_WOL_SETTINGS_EVENTS, 0); 753 if (ret < 0) 754 return ret; 755 756 /* Mark this PHY as wakeup capable and register the interrupt as a 757 * wakeup IRQ if the PHY is marked as a wakeup source in firmware, 758 * and the interrupt is valid. 759 */ 760 if (device_property_read_bool(dev, "wakeup-source") && 761 phy_interrupt_is_valid(phydev)) { 762 device_set_wakeup_capable(dev, true); 763 devm_pm_set_wake_irq(dev, phydev->irq); 764 } 765 766 return ret; 767 } 768 769 static int rtl8201_ack_interrupt(struct phy_device *phydev) 770 { 771 int err; 772 773 err = phy_read(phydev, RTL8201F_ISR); 774 775 return (err < 0) ? err : 0; 776 } 777 778 static int rtl821x_ack_interrupt(struct phy_device *phydev) 779 { 780 int err; 781 782 err = phy_read(phydev, RTL821x_INSR); 783 784 return (err < 0) ? err : 0; 785 } 786 787 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 788 { 789 int err; 790 791 err = phy_read(phydev, RTL8211F_INSR); 792 793 return (err < 0) ? err : 0; 794 } 795 796 static int rtl8201_config_intr(struct phy_device *phydev) 797 { 798 u16 val; 799 int err; 800 801 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 802 err = rtl8201_ack_interrupt(phydev); 803 if (err) 804 return err; 805 806 val = RTL8201F_IER_MASK; 807 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 808 RTL8201F_IER, val); 809 } else { 810 val = 0; 811 err = phy_write_paged(phydev, RTL8201F_IER_PAGE, 812 RTL8201F_IER, val); 813 if (err) 814 return err; 815 816 err = rtl8201_ack_interrupt(phydev); 817 } 818 819 return err; 820 } 821 822 static int rtl8211b_config_intr(struct phy_device *phydev) 823 { 824 int err; 825 826 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 827 err = rtl821x_ack_interrupt(phydev); 828 if (err) 829 return err; 830 831 err = phy_write(phydev, RTL821x_INER, 832 RTL8211B_INER_INIT); 833 } else { 834 err = phy_write(phydev, RTL821x_INER, 0); 835 if (err) 836 return err; 837 838 err = rtl821x_ack_interrupt(phydev); 839 } 840 841 return err; 842 } 843 844 static int rtl8211e_config_intr(struct phy_device *phydev) 845 { 846 int err; 847 848 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 849 err = rtl821x_ack_interrupt(phydev); 850 if (err) 851 return err; 852 853 err = phy_write(phydev, RTL821x_INER, 854 RTL8211E_INER_LINK_STATUS); 855 } else { 856 err = phy_write(phydev, RTL821x_INER, 0); 857 if (err) 858 return err; 859 860 err = rtl821x_ack_interrupt(phydev); 861 } 862 863 return err; 864 } 865 866 static int rtl8211f_config_intr(struct phy_device *phydev) 867 { 868 struct rtl821x_priv *priv = phydev->priv; 869 u16 val; 870 int err; 871 872 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 873 err = rtl8211f_ack_interrupt(phydev); 874 if (err) 875 return err; 876 877 val = RTL8211F_INER_LINK_STATUS; 878 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 879 if (err == 0) 880 priv->iner = val; 881 } else { 882 priv->iner = val = 0; 883 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 884 if (err) 885 return err; 886 887 err = rtl8211f_ack_interrupt(phydev); 888 } 889 890 return err; 891 } 892 893 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 894 { 895 int irq_status; 896 897 irq_status = phy_read(phydev, RTL8201F_ISR); 898 if (irq_status < 0) { 899 phy_error(phydev); 900 return IRQ_NONE; 901 } 902 903 if (!(irq_status & RTL8201F_ISR_MASK)) 904 return IRQ_NONE; 905 906 phy_trigger_machine(phydev); 907 908 return IRQ_HANDLED; 909 } 910 911 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 912 { 913 int irq_status, irq_enabled; 914 915 irq_status = phy_read(phydev, RTL821x_INSR); 916 if (irq_status < 0) { 917 phy_error(phydev); 918 return IRQ_NONE; 919 } 920 921 irq_enabled = phy_read(phydev, RTL821x_INER); 922 if (irq_enabled < 0) { 923 phy_error(phydev); 924 return IRQ_NONE; 925 } 926 927 if (!(irq_status & irq_enabled)) 928 return IRQ_NONE; 929 930 phy_trigger_machine(phydev); 931 932 return IRQ_HANDLED; 933 } 934 935 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 936 { 937 int irq_status; 938 939 irq_status = phy_read(phydev, RTL8211F_INSR); 940 if (irq_status < 0) { 941 phy_error(phydev); 942 return IRQ_NONE; 943 } 944 945 if (irq_status & RTL8211F_INER_LINK_STATUS) { 946 phy_trigger_machine(phydev); 947 return IRQ_HANDLED; 948 } 949 950 if (irq_status & RTL8211F_INER_PME) { 951 pm_wakeup_event(&phydev->mdio.dev, 0); 952 return IRQ_HANDLED; 953 } 954 955 return IRQ_NONE; 956 } 957 958 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 959 { 960 int wol_events; 961 962 /* If the PHY is not capable of waking the system, then WoL can not 963 * be supported. 964 */ 965 if (!device_can_wakeup(&dev->mdio.dev)) { 966 wol->supported = 0; 967 return; 968 } 969 970 wol->supported = WAKE_MAGIC; 971 972 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS); 973 if (wol_events < 0) 974 return; 975 976 if (wol_events & RTL8211F_WOL_EVENT_MAGIC) 977 wol->wolopts = WAKE_MAGIC; 978 } 979 980 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol) 981 { 982 const u8 *mac_addr = dev->attached_dev->dev_addr; 983 int oldpage; 984 985 if (!device_can_wakeup(&dev->mdio.dev)) 986 return -EOPNOTSUPP; 987 988 oldpage = phy_save_page(dev); 989 if (oldpage < 0) 990 goto err; 991 992 if (wol->wolopts & WAKE_MAGIC) { 993 /* Store the device address for the magic packet */ 994 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE); 995 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0])); 996 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); 997 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); 998 999 /* Enable magic packet matching */ 1000 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 1001 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC); 1002 /* Set the maximum packet size, and assert WoL reset */ 1003 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ); 1004 } else { 1005 /* Disable magic packet matching */ 1006 rtl821x_write_page(dev, RTL8211F_WOL_PAGE); 1007 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0); 1008 1009 /* Place WoL in reset */ 1010 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ, 1011 RTL8211F_WOL_RG_RSTB); 1012 } 1013 1014 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); 1015 1016 err: 1017 return phy_restore_page(dev, oldpage, 0); 1018 } 1019 1020 static int rtl8211_config_aneg(struct phy_device *phydev) 1021 { 1022 int ret; 1023 1024 ret = genphy_config_aneg(phydev); 1025 if (ret < 0) 1026 return ret; 1027 1028 /* Quirk was copied from vendor driver. Unfortunately it includes no 1029 * description of the magic numbers. 1030 */ 1031 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 1032 phy_write(phydev, 0x17, 0x2138); 1033 phy_write(phydev, 0x0e, 0x0260); 1034 } else { 1035 phy_write(phydev, 0x17, 0x2108); 1036 phy_write(phydev, 0x0e, 0x0000); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int rtl8211c_config_init(struct phy_device *phydev) 1043 { 1044 /* RTL8211C has an issue when operating in Gigabit slave mode */ 1045 return phy_set_bits(phydev, MII_CTRL1000, 1046 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 1047 } 1048 1049 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev) 1050 { 1051 u16 val_txdly, val_rxdly; 1052 int ret; 1053 1054 switch (phydev->interface) { 1055 case PHY_INTERFACE_MODE_RGMII: 1056 val_txdly = 0; 1057 val_rxdly = 0; 1058 break; 1059 1060 case PHY_INTERFACE_MODE_RGMII_RXID: 1061 val_txdly = 0; 1062 val_rxdly = RTL8211F_RX_DELAY; 1063 break; 1064 1065 case PHY_INTERFACE_MODE_RGMII_TXID: 1066 val_txdly = RTL8211F_TX_DELAY; 1067 val_rxdly = 0; 1068 break; 1069 1070 case PHY_INTERFACE_MODE_RGMII_ID: 1071 val_txdly = RTL8211F_TX_DELAY; 1072 val_rxdly = RTL8211F_RX_DELAY; 1073 break; 1074 1075 default: /* the rest of the modes imply leaving delay as is. */ 1076 return 0; 1077 } 1078 1079 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 1080 RTL8211F_TXCR, RTL8211F_TX_DELAY, 1081 val_txdly); 1082 if (ret < 0) { 1083 phydev_err(phydev, "Failed to update the TX delay register: %pe\n", 1084 ERR_PTR(ret)); 1085 return ret; 1086 } else if (ret) { 1087 phydev_dbg(phydev, 1088 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 1089 str_enable_disable(val_txdly)); 1090 } else { 1091 phydev_dbg(phydev, 1092 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 1093 str_enabled_disabled(val_txdly)); 1094 } 1095 1096 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE, 1097 RTL8211F_RXCR, RTL8211F_RX_DELAY, 1098 val_rxdly); 1099 if (ret < 0) { 1100 phydev_err(phydev, "Failed to update the RX delay register: %pe\n", 1101 ERR_PTR(ret)); 1102 return ret; 1103 } else if (ret) { 1104 phydev_dbg(phydev, 1105 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 1106 str_enable_disable(val_rxdly)); 1107 } else { 1108 phydev_dbg(phydev, 1109 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 1110 str_enabled_disabled(val_rxdly)); 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int rtl8211f_config_clk_out(struct phy_device *phydev) 1117 { 1118 struct rtl821x_priv *priv = phydev->priv; 1119 int ret; 1120 1121 /* The value is preserved if the device tree property is absent */ 1122 if (!priv->disable_clk_out) 1123 return 0; 1124 1125 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 1126 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE, 1127 RTL8211FVD_CLKOUT_REG, 1128 RTL8211FVD_CLKOUT_EN, 0); 1129 else 1130 ret = phy_modify(phydev, RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 1131 0); 1132 if (ret) 1133 return ret; 1134 1135 return genphy_soft_reset(phydev); 1136 } 1137 1138 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour, 1139 * which causes the RXC clock signal to stop for tens to hundreds of 1140 * milliseconds. 1141 * 1142 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is 1143 * only enabled based on an opt-in device tree property. 1144 */ 1145 static int rtl8211f_config_aldps(struct phy_device *phydev) 1146 { 1147 struct rtl821x_priv *priv = phydev->priv; 1148 u16 mask = RTL8211F_ALDPS_PLL_OFF | 1149 RTL8211F_ALDPS_ENABLE | 1150 RTL8211F_ALDPS_XTAL_OFF; 1151 1152 /* The value is preserved if the device tree property is absent */ 1153 if (!priv->enable_aldps) 1154 return 0; 1155 1156 return phy_modify(phydev, RTL8211F_PHYCR1, mask, mask); 1157 } 1158 1159 static int rtl8211f_disable_autonomous_eee(struct phy_device *phydev) 1160 { 1161 return phy_modify(phydev, RTL8211F_PHYCR2, 1162 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0); 1163 } 1164 1165 static int rtl8211f_config_clkout_ssc(struct phy_device *phydev) 1166 { 1167 struct rtl821x_priv *priv = phydev->priv; 1168 struct device *dev = &phydev->mdio.dev; 1169 int ret; 1170 1171 /* The value is preserved if the device tree property is absent */ 1172 if (!priv->enable_clkout_ssc) 1173 return 0; 1174 1175 /* RTL8211FVD has PHYCR2 register, but configuration of CLKOUT SSC 1176 * is not currently supported by this driver due to different bit 1177 * layout. 1178 */ 1179 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 1180 return 0; 1181 1182 /* Unnamed registers from EMI improvement parameters application note 1.2 */ 1183 ret = phy_write_paged(phydev, 0xd09, 0x10, 0xcf00); 1184 if (ret < 0) { 1185 dev_err(dev, "CLKOUT SSC initialization failed: %pe\n", ERR_PTR(ret)); 1186 return ret; 1187 } 1188 1189 /* Enable CLKOUT SSC and CLKOUT SSC Capability using PHYCR2 1190 * bits 7, 12, 13. This matches the register 25 write 0x38C3 1191 * from the EMI improvement parameters application note 1.2 1192 * section 2.3, without affecting unrelated bits. 1193 */ 1194 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, 1195 RTL8211F_CLKOUT_SSC_CAP | RTL8211F_CLKOUT_SSC_EN); 1196 if (ret < 0) { 1197 dev_err(dev, "CLKOUT SSC enable failed: %pe\n", ERR_PTR(ret)); 1198 return ret; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static int rtl8211f_config_rxc_ssc(struct phy_device *phydev) 1205 { 1206 struct rtl821x_priv *priv = phydev->priv; 1207 struct device *dev = &phydev->mdio.dev; 1208 int ret; 1209 1210 /* The value is preserved if the device tree property is absent */ 1211 if (!priv->enable_rxc_ssc) 1212 return 0; 1213 1214 /* RTL8211FVD has PHYCR2 register, but configuration of RXC SSC 1215 * is not currently supported by this driver due to different bit 1216 * layout. 1217 */ 1218 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 1219 return 0; 1220 1221 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_RXC, 0x5f00); 1222 if (ret < 0) { 1223 dev_err(dev, "RXC SSC configuration failed: %pe\n", ERR_PTR(ret)); 1224 return ret; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int rtl8211f_config_sysclk_ssc(struct phy_device *phydev) 1231 { 1232 struct rtl821x_priv *priv = phydev->priv; 1233 struct device *dev = &phydev->mdio.dev; 1234 int ret; 1235 1236 /* The value is preserved if the device tree property is absent */ 1237 if (!priv->enable_sysclk_ssc) 1238 return 0; 1239 1240 /* RTL8211FVD has PHYCR2 register, but configuration of SYSCLK SSC 1241 * is not currently supported by this driver due to different bit 1242 * layout. 1243 */ 1244 if (phydev->drv->phy_id == RTL_8211FVD_PHYID) 1245 return 0; 1246 1247 ret = phy_write_paged(phydev, RTL8211F_SSC_PAGE, RTL8211F_SSC_SYSCLK, 0x4f00); 1248 if (ret < 0) { 1249 dev_err(dev, "SYSCLK SSC configuration failed: %pe\n", ERR_PTR(ret)); 1250 return ret; 1251 } 1252 1253 /* Enable SSC */ 1254 ret = phy_set_bits(phydev, RTL8211F_PHYCR2, RTL8211F_SYSCLK_SSC_EN); 1255 if (ret < 0) { 1256 dev_err(dev, "SYSCLK SSC enable failed: %pe\n", ERR_PTR(ret)); 1257 return ret; 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int rtl8211f_config_init(struct phy_device *phydev) 1264 { 1265 struct device *dev = &phydev->mdio.dev; 1266 int ret; 1267 1268 ret = rtl8211f_config_aldps(phydev); 1269 if (ret) { 1270 dev_err(dev, "aldps mode configuration failed: %pe\n", 1271 ERR_PTR(ret)); 1272 return ret; 1273 } 1274 1275 ret = rtl8211f_config_rgmii_delay(phydev); 1276 if (ret) 1277 return ret; 1278 1279 ret = rtl8211f_config_rxc_ssc(phydev); 1280 if (ret) 1281 return ret; 1282 1283 ret = rtl8211f_config_sysclk_ssc(phydev); 1284 if (ret) 1285 return ret; 1286 1287 ret = rtl8211f_config_clkout_ssc(phydev); 1288 if (ret) 1289 return ret; 1290 1291 ret = rtl8211f_config_clk_out(phydev); 1292 if (ret) { 1293 dev_err(dev, "clkout configuration failed: %pe\n", 1294 ERR_PTR(ret)); 1295 return ret; 1296 } 1297 1298 return 0; 1299 } 1300 1301 static int rtl821x_suspend(struct phy_device *phydev) 1302 { 1303 struct rtl821x_priv *priv = phydev->priv; 1304 int ret = 0; 1305 1306 if (!phydev->wol_enabled) { 1307 ret = genphy_suspend(phydev); 1308 1309 if (ret) 1310 return ret; 1311 1312 clk_disable_unprepare(priv->clk); 1313 } 1314 1315 return ret; 1316 } 1317 1318 static int rtl8211f_suspend(struct phy_device *phydev) 1319 { 1320 u16 wol_rst; 1321 int ret; 1322 1323 ret = rtl821x_suspend(phydev); 1324 if (ret < 0) 1325 return ret; 1326 1327 /* If a PME event is enabled, then configure the interrupt for 1328 * PME events only, disabling link interrupt. We avoid switching 1329 * to PMEB mode as we don't have a status bit for that. 1330 */ 1331 if (device_may_wakeup(&phydev->mdio.dev)) { 1332 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, 1333 RTL8211F_INER_PME); 1334 if (ret < 0) 1335 goto err; 1336 1337 /* Read the INSR to clear any pending interrupt */ 1338 phy_read(phydev, RTL8211F_INSR); 1339 1340 /* Reset the WoL to ensure that an event is picked up. 1341 * Unless we do this, even if we receive another packet, 1342 * we may not have a PME interrupt raised. 1343 */ 1344 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE, 1345 RTL8211F_WOL_RST_RMSQ); 1346 if (ret < 0) 1347 goto err; 1348 1349 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB; 1350 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 1351 RTL8211F_WOL_RST_RMSQ, wol_rst); 1352 if (ret < 0) 1353 goto err; 1354 1355 wol_rst |= RTL8211F_WOL_RG_RSTB; 1356 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE, 1357 RTL8211F_WOL_RST_RMSQ, wol_rst); 1358 } 1359 1360 err: 1361 return ret; 1362 } 1363 1364 static int rtl821x_resume(struct phy_device *phydev) 1365 { 1366 struct rtl821x_priv *priv = phydev->priv; 1367 int ret; 1368 1369 if (!phydev->wol_enabled) 1370 clk_prepare_enable(priv->clk); 1371 1372 ret = genphy_resume(phydev); 1373 if (ret < 0) 1374 return ret; 1375 1376 msleep(20); 1377 1378 return 0; 1379 } 1380 1381 static int rtl8211f_resume(struct phy_device *phydev) 1382 { 1383 struct rtl821x_priv *priv = phydev->priv; 1384 int ret; 1385 1386 ret = rtl821x_resume(phydev); 1387 if (ret < 0) 1388 return ret; 1389 1390 /* If the device was programmed for a PME event, restore the interrupt 1391 * enable so phylib can receive link state interrupts. 1392 */ 1393 if (device_may_wakeup(&phydev->mdio.dev)) 1394 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); 1395 1396 return ret; 1397 } 1398 1399 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index, 1400 unsigned long rules) 1401 { 1402 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) | 1403 BIT(TRIGGER_NETDEV_LINK_10) | 1404 BIT(TRIGGER_NETDEV_LINK_100) | 1405 BIT(TRIGGER_NETDEV_LINK_1000) | 1406 BIT(TRIGGER_NETDEV_RX) | 1407 BIT(TRIGGER_NETDEV_TX); 1408 1409 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 1410 * - Link: Configurable subset of 10/100/1000 link rates 1411 * - Active: Blink on activity, RX or TX is not differentiated 1412 * The Active option has two modes, A and B: 1413 * - A: Link and Active indication at configurable, but matching, 1414 * subset of 10/100/1000 link rates 1415 * - B: Link indication at configurable subset of 10/100/1000 link 1416 * rates and Active indication always at all three 10+100+1000 1417 * link rates. 1418 * This code currently uses mode B only. 1419 * 1420 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B. 1421 */ 1422 1423 if (index >= RTL8211x_LED_COUNT) 1424 return -EINVAL; 1425 1426 /* Filter out any other unsupported triggers. */ 1427 if (rules & ~mask) 1428 return -EOPNOTSUPP; 1429 1430 /* RX and TX are not differentiated, either both are set or not set. */ 1431 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 1432 return -EOPNOTSUPP; 1433 1434 return 0; 1435 } 1436 1437 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 1438 unsigned long *rules) 1439 { 1440 int val; 1441 1442 if (index >= RTL8211x_LED_COUNT) 1443 return -EINVAL; 1444 1445 val = phy_read_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR); 1446 if (val < 0) 1447 return val; 1448 1449 val >>= RTL8211F_LEDCR_SHIFT * index; 1450 val &= RTL8211F_LEDCR_MASK; 1451 1452 if (val & RTL8211F_LEDCR_LINK_10) 1453 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1454 1455 if (val & RTL8211F_LEDCR_LINK_100) 1456 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1457 1458 if (val & RTL8211F_LEDCR_LINK_1000) 1459 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1460 1461 if ((val & RTL8211F_LEDCR_LINK_10) && 1462 (val & RTL8211F_LEDCR_LINK_100) && 1463 (val & RTL8211F_LEDCR_LINK_1000)) { 1464 __set_bit(TRIGGER_NETDEV_LINK, rules); 1465 } 1466 1467 if (val & RTL8211F_LEDCR_ACT_TXRX) { 1468 __set_bit(TRIGGER_NETDEV_RX, rules); 1469 __set_bit(TRIGGER_NETDEV_TX, rules); 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 1476 unsigned long rules) 1477 { 1478 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 1479 u16 reg = 0; 1480 1481 if (index >= RTL8211x_LED_COUNT) 1482 return -EINVAL; 1483 1484 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1485 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1486 reg |= RTL8211F_LEDCR_LINK_10; 1487 } 1488 1489 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1490 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1491 reg |= RTL8211F_LEDCR_LINK_100; 1492 } 1493 1494 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1495 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1496 reg |= RTL8211F_LEDCR_LINK_1000; 1497 } 1498 1499 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1500 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1501 reg |= RTL8211F_LEDCR_ACT_TXRX; 1502 } 1503 1504 reg <<= RTL8211F_LEDCR_SHIFT * index; 1505 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 1506 1507 return phy_modify_paged(phydev, RTL8211F_LEDCR_PAGE, RTL8211F_LEDCR, 1508 mask, reg); 1509 } 1510 1511 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index, 1512 unsigned long *rules) 1513 { 1514 int ret; 1515 u16 cr1, cr2; 1516 1517 if (index >= RTL8211x_LED_COUNT) 1518 return -EINVAL; 1519 1520 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1521 RTL8211E_LEDCR1); 1522 if (ret < 0) 1523 return ret; 1524 1525 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; 1526 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { 1527 __set_bit(TRIGGER_NETDEV_RX, rules); 1528 __set_bit(TRIGGER_NETDEV_TX, rules); 1529 } 1530 1531 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1532 RTL8211E_LEDCR2); 1533 if (ret < 0) 1534 return ret; 1535 1536 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index; 1537 if (cr2 & RTL8211E_LEDCR2_LINK_10) 1538 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1539 1540 if (cr2 & RTL8211E_LEDCR2_LINK_100) 1541 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1542 1543 if (cr2 & RTL8211E_LEDCR2_LINK_1000) 1544 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1545 1546 if ((cr2 & RTL8211E_LEDCR2_LINK_10) && 1547 (cr2 & RTL8211E_LEDCR2_LINK_100) && 1548 (cr2 & RTL8211E_LEDCR2_LINK_1000)) { 1549 __set_bit(TRIGGER_NETDEV_LINK, rules); 1550 } 1551 1552 return ret; 1553 } 1554 1555 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index, 1556 unsigned long rules) 1557 { 1558 const u16 cr1mask = 1559 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index); 1560 const u16 cr2mask = 1561 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index); 1562 u16 cr1 = 0, cr2 = 0; 1563 int ret; 1564 1565 if (index >= RTL8211x_LED_COUNT) 1566 return -EINVAL; 1567 1568 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 1569 test_bit(TRIGGER_NETDEV_TX, &rules)) { 1570 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; 1571 } 1572 1573 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; 1574 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1575 RTL8211E_LEDCR1, cr1mask, cr1); 1576 if (ret < 0) 1577 return ret; 1578 1579 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1580 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) { 1581 cr2 |= RTL8211E_LEDCR2_LINK_10; 1582 } 1583 1584 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1585 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) { 1586 cr2 |= RTL8211E_LEDCR2_LINK_100; 1587 } 1588 1589 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 1590 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) { 1591 cr2 |= RTL8211E_LEDCR2_LINK_1000; 1592 } 1593 1594 cr2 <<= RTL8211E_LEDCR2_SHIFT * index; 1595 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE, 1596 RTL8211E_LEDCR2, cr2mask, cr2); 1597 1598 return ret; 1599 } 1600 1601 static int rtl8211e_config_init(struct phy_device *phydev) 1602 { 1603 u16 val; 1604 1605 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 1606 switch (phydev->interface) { 1607 case PHY_INTERFACE_MODE_RGMII: 1608 val = RTL8211E_CTRL_DELAY | 0; 1609 break; 1610 case PHY_INTERFACE_MODE_RGMII_ID: 1611 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 1612 break; 1613 case PHY_INTERFACE_MODE_RGMII_RXID: 1614 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 1615 break; 1616 case PHY_INTERFACE_MODE_RGMII_TXID: 1617 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 1618 break; 1619 default: /* the rest of the modes imply leaving delays as is. */ 1620 return 0; 1621 } 1622 1623 /* According to a sample driver there is a 0x1c config register on the 1624 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 1625 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 1626 * The configuration register definition: 1627 * 14 = reserved 1628 * 13 = Force Tx RX Delay controlled by bit12 bit11, 1629 * 12 = RX Delay, 11 = TX Delay 1630 * 10:0 = Test && debug settings reserved by realtek 1631 */ 1632 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE, 1633 RTL8211E_RGMII_DELAY, 1634 RTL8211E_DELAY_MASK, val); 1635 } 1636 1637 static int rtl8211b_suspend(struct phy_device *phydev) 1638 { 1639 phy_write(phydev, MII_MMD_DATA, BIT(9)); 1640 1641 return genphy_suspend(phydev); 1642 } 1643 1644 static int rtl8211b_resume(struct phy_device *phydev) 1645 { 1646 phy_write(phydev, MII_MMD_DATA, 0); 1647 1648 return genphy_resume(phydev); 1649 } 1650 1651 static int rtl8366rb_config_init(struct phy_device *phydev) 1652 { 1653 int ret; 1654 1655 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 1656 RTL8366RB_POWER_SAVE_ON); 1657 if (ret) { 1658 dev_err(&phydev->mdio.dev, 1659 "error enabling power management\n"); 1660 } 1661 1662 return ret; 1663 } 1664 1665 /* get actual speed to cover the downshift case */ 1666 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 1667 { 1668 /* bit 3 1669 * 0: Half Duplex 1670 * 1: Full Duplex 1671 */ 1672 if (val & RTL_PHYSR_DUPLEX) 1673 phydev->duplex = DUPLEX_FULL; 1674 else 1675 phydev->duplex = DUPLEX_HALF; 1676 1677 switch (val & RTL_PHYSR_SPEED_MASK) { 1678 case 0x0000: 1679 phydev->speed = SPEED_10; 1680 break; 1681 case 0x0010: 1682 phydev->speed = SPEED_100; 1683 break; 1684 case 0x0020: 1685 phydev->speed = SPEED_1000; 1686 break; 1687 case 0x0200: 1688 phydev->speed = SPEED_10000; 1689 break; 1690 case 0x0210: 1691 phydev->speed = SPEED_2500; 1692 break; 1693 case 0x0220: 1694 phydev->speed = SPEED_5000; 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 /* bit 11 1701 * 0: Slave Mode 1702 * 1: Master Mode 1703 */ 1704 if (phydev->speed >= 1000) { 1705 if (val & RTL_PHYSR_MASTER) 1706 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1707 else 1708 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1709 } else { 1710 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1711 } 1712 } 1713 1714 static int rtlgen_read_status(struct phy_device *phydev) 1715 { 1716 int ret, val; 1717 1718 ret = genphy_read_status(phydev); 1719 if (ret < 0) 1720 return ret; 1721 1722 if (!phydev->link) 1723 return 0; 1724 1725 val = phy_read(phydev, RTL_PHYSR); 1726 if (val < 0) 1727 return val; 1728 1729 rtlgen_decode_physr(phydev, val); 1730 1731 return 0; 1732 } 1733 1734 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 1735 { 1736 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 1737 } 1738 1739 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 1740 { 1741 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 1742 val); 1743 } 1744 1745 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1746 { 1747 int ret; 1748 1749 if (devnum == MDIO_MMD_VEND2) 1750 ret = rtlgen_read_vend2(phydev, regnum); 1751 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 1752 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 1753 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1754 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 1755 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 1756 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 1757 else 1758 ret = -EOPNOTSUPP; 1759 1760 return ret; 1761 } 1762 1763 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1764 u16 val) 1765 { 1766 int ret; 1767 1768 if (devnum == MDIO_MMD_VEND2) 1769 ret = rtlgen_write_vend2(phydev, regnum, val); 1770 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 1771 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV, val); 1772 else 1773 ret = -EOPNOTSUPP; 1774 1775 return ret; 1776 } 1777 1778 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 1779 { 1780 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 1781 1782 if (ret != -EOPNOTSUPP) 1783 return ret; 1784 1785 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 1786 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 1787 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1788 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 1789 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 1790 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 1791 1792 return ret; 1793 } 1794 1795 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 1796 u16 val) 1797 { 1798 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 1799 1800 if (ret != -EOPNOTSUPP) 1801 return ret; 1802 1803 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 1804 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 1805 1806 return ret; 1807 } 1808 1809 static int rtl822x_probe(struct phy_device *phydev) 1810 { 1811 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 1812 phydev->phy_id != RTL_GENERIC_PHYID) 1813 return rtl822x_hwmon_init(phydev); 1814 1815 return 0; 1816 } 1817 1818 /* RTL822x cannot access MDIO_MMD_VEND2 via MII_MMD_CTRL/MII_MMD_DATA. 1819 * A mapping to use paged access needs to be used instead. 1820 * All other MMD devices can be accessed as usual. 1821 */ 1822 static int rtl822xb_read_mmd(struct phy_device *phydev, int devnum, u16 reg) 1823 { 1824 int oldpage, ret, read_ret; 1825 u16 page; 1826 1827 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1828 * Clause-45 access is available 1829 */ 1830 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1831 return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr, 1832 phydev->is_c45, devnum, reg); 1833 1834 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1835 if (reg >= RTL822X_VND2_C22_REG(0) && 1836 reg <= RTL822X_VND2_C22_REG(30)) 1837 return __phy_read(phydev, RTL822X_VND2_TO_C22_REG(reg)); 1838 1839 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1840 page = RTL822X_VND2_TO_PAGE(reg); 1841 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1842 if (oldpage < 0) 1843 return oldpage; 1844 1845 if (oldpage != page) { 1846 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1847 if (ret < 0) 1848 return ret; 1849 } 1850 1851 read_ret = __phy_read(phydev, RTL822X_VND2_TO_PAGE_REG(reg)); 1852 if (oldpage != page) { 1853 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1854 if (ret < 0) 1855 return ret; 1856 } 1857 1858 return read_ret; 1859 } 1860 1861 static int rtl822xb_write_mmd(struct phy_device *phydev, int devnum, u16 reg, 1862 u16 val) 1863 { 1864 int oldpage, ret, write_ret; 1865 u16 page; 1866 1867 /* Use default method for all MMDs except MDIO_MMD_VEND2 or in case 1868 * Clause-45 access is available 1869 */ 1870 if (devnum != MDIO_MMD_VEND2 || phydev->is_c45) 1871 return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr, 1872 phydev->is_c45, devnum, reg, val); 1873 1874 /* Simplify access to C22-registers addressed inside MDIO_MMD_VEND2 */ 1875 if (reg >= RTL822X_VND2_C22_REG(0) && 1876 reg <= RTL822X_VND2_C22_REG(30)) 1877 return __phy_write(phydev, RTL822X_VND2_TO_C22_REG(reg), val); 1878 1879 /* Use paged access for MDIO_MMD_VEND2 over Clause-22 */ 1880 page = RTL822X_VND2_TO_PAGE(reg); 1881 oldpage = __phy_read(phydev, RTL821x_PAGE_SELECT); 1882 if (oldpage < 0) 1883 return oldpage; 1884 1885 if (oldpage != page) { 1886 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, page); 1887 if (ret < 0) 1888 return ret; 1889 } 1890 1891 write_ret = __phy_write(phydev, RTL822X_VND2_TO_PAGE_REG(reg), val); 1892 if (oldpage != page) { 1893 ret = __phy_write(phydev, RTL821x_PAGE_SELECT, oldpage); 1894 if (ret < 0) 1895 return ret; 1896 } 1897 1898 return write_ret; 1899 } 1900 1901 static int rtl8226_set_mdi_swap(struct phy_device *phydev, bool swap_enable) 1902 { 1903 u16 val = swap_enable ? RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN : 0; 1904 1905 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8226_VND1_UNKNOWN_6A21, 1906 RTL8226_VND1_UNKNOWN_6A21_MDI_SWAP_EN, val); 1907 } 1908 1909 static int rtl8226_swap_rg_lpf_cap(struct phy_device *phydev, u32 reg_p0_p1, u32 reg_p2_p3) 1910 { 1911 u16 val_p0, val_p1, val_p2, val_p3; 1912 int ret; 1913 1914 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, reg_p0_p1); 1915 if (ret < 0) 1916 return ret; 1917 1918 val_p0 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_A_MASK, ret); 1919 val_p1 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_B_MASK, ret); 1920 1921 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, reg_p2_p3); 1922 if (ret < 0) 1923 return ret; 1924 1925 val_p2 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_A_MASK, ret); 1926 val_p3 = FIELD_GET(RTL8226_RG_LPF_CAP_PAIR_B_MASK, ret); 1927 1928 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, reg_p0_p1, 1929 RTL8226_RG_LPF_CAP_PAIR_A_MASK | RTL8226_RG_LPF_CAP_PAIR_B_MASK, 1930 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_A_MASK, val_p3) | 1931 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_B_MASK, val_p2)); 1932 if (ret < 0) 1933 return ret; 1934 1935 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, reg_p2_p3, 1936 RTL8226_RG_LPF_CAP_PAIR_A_MASK | RTL8226_RG_LPF_CAP_PAIR_B_MASK, 1937 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_A_MASK, val_p1) | 1938 FIELD_PREP(RTL8226_RG_LPF_CAP_PAIR_B_MASK, val_p0)); 1939 } 1940 1941 static int rtl8226_patch_mdi_swap(struct phy_device *phydev, bool swap_enable) 1942 { 1943 u16 adccal_offset[4]; 1944 bool is_patched; 1945 int ret; 1946 1947 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068); 1948 if (ret < 0) 1949 return ret; 1950 1951 is_patched = !(ret & RTL8226_VND2_UNKNOWN_D068_MDI_SWAP_FLAG); 1952 1953 if (is_patched == swap_enable) { 1954 /* Nothing to do */ 1955 return 0; 1956 } 1957 1958 if (!swap_enable) { 1959 /* Patching is only implemented one-way, see next comment. */ 1960 phydev_err(phydev, "MDI swapping disabled, but PHY is already patched.\n"); 1961 return -EINVAL; 1962 } 1963 1964 /* The exact meaning of these bits is unknown. We only know that bit 1 1965 * is used as a flag that swapping is already done. 1966 */ 1967 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 0x7, 0x1); 1968 if (ret < 0) 1969 return ret; 1970 1971 for (int i = 0; i < 4; i++) { 1972 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 1973 RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, 1974 FIELD_PREP(RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, i)); 1975 if (ret < 0) 1976 return ret; 1977 1978 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_ADCCAL_OFFSET); 1979 if (ret < 0) 1980 return ret; 1981 1982 adccal_offset[i] = ret; 1983 } 1984 1985 for (int i = 0; i < 4; i++) { 1986 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_UNKNOWN_D068, 1987 RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, 1988 FIELD_PREP(RTL8226_VND2_UNKNOWN_D068_PAIR_SEL, i)); 1989 if (ret < 0) 1990 return ret; 1991 1992 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8226_VND2_ADCCAL_OFFSET, 1993 adccal_offset[3 - i]); 1994 if (ret < 0) 1995 return ret; 1996 } 1997 1998 ret = rtl8226_swap_rg_lpf_cap(phydev, RTL8226_VND2_RG_LPF_CAP_XG_P0_P1, 1999 RTL8226_VND2_RG_LPF_CAP_XG_P2_P3); 2000 if (ret < 0) 2001 return ret; 2002 2003 return rtl8226_swap_rg_lpf_cap(phydev, RTL8226_VND2_RG_LPF_CAP_P0_P1, 2004 RTL8226_VND2_RG_LPF_CAP_P2_P3); 2005 } 2006 2007 static int rtl8226_config_mdi_order(struct phy_device *phydev) 2008 { 2009 u32 order; 2010 bool swap_enable; 2011 int ret; 2012 2013 ret = of_property_read_u32(phydev->mdio.dev.of_node, "enet-phy-pair-order", &order); 2014 2015 /* Property not present, nothing to do */ 2016 if (ret == -EINVAL || ret == -ENOSYS) 2017 return 0; 2018 2019 if (ret) 2020 return ret; 2021 2022 if (order & ~1) 2023 return -EINVAL; 2024 2025 swap_enable = !!(order & 1); 2026 2027 ret = rtl8226_set_mdi_swap(phydev, swap_enable); 2028 if (ret) 2029 return ret; 2030 2031 return rtl8226_patch_mdi_swap(phydev, swap_enable); 2032 } 2033 2034 static int rtl8226_probe(struct phy_device *phydev) 2035 { 2036 return rtl8226_config_mdi_order(phydev); 2037 } 2038 2039 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1) 2040 { 2041 bool has_2500, has_sgmii; 2042 u16 mode; 2043 int ret; 2044 2045 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 2046 phydev->host_interfaces) || 2047 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 2048 2049 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 2050 phydev->host_interfaces) || 2051 phydev->interface == PHY_INTERFACE_MODE_SGMII; 2052 2053 /* fill in possible interfaces */ 2054 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 2055 has_2500); 2056 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 2057 has_sgmii); 2058 2059 if (!has_2500 && !has_sgmii) 2060 return 0; 2061 2062 /* determine SerDes option mode */ 2063 if (has_2500 && !has_sgmii) { 2064 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 2065 phydev->rate_matching = RATE_MATCH_PAUSE; 2066 } else { 2067 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 2068 phydev->rate_matching = RATE_MATCH_NONE; 2069 } 2070 2071 /* the following sequence with magic numbers sets up the SerDes 2072 * option mode 2073 */ 2074 2075 if (!gen1) { 2076 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 2077 if (ret < 0) 2078 return ret; 2079 } 2080 2081 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 2082 RTL822X_VND1_SERDES_OPTION, 2083 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 2084 mode); 2085 if (gen1 || ret < 0) 2086 return ret; 2087 2088 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 2089 if (ret < 0) 2090 return ret; 2091 2092 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 2093 if (ret < 0) 2094 return ret; 2095 2096 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 2097 } 2098 2099 static int rtl822x_config_init(struct phy_device *phydev) 2100 { 2101 return rtl822x_set_serdes_option_mode(phydev, true); 2102 } 2103 2104 static int rtl822xb_config_init(struct phy_device *phydev) 2105 { 2106 return rtl822x_set_serdes_option_mode(phydev, false); 2107 } 2108 2109 static int rtl822x_serdes_write(struct phy_device *phydev, u16 reg, u16 val) 2110 { 2111 int ret, poll; 2112 2113 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg); 2114 if (ret < 0) 2115 return ret; 2116 2117 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val); 2118 if (ret < 0) 2119 return ret; 2120 2121 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD, 2122 RTL822X_VND1_SERDES_CMD_WRITE | 2123 RTL822X_VND1_SERDES_CMD_BUSY); 2124 if (ret < 0) 2125 return ret; 2126 2127 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 2128 RTL822X_VND1_SERDES_CMD, poll, 2129 !(poll & RTL822X_VND1_SERDES_CMD_BUSY), 2130 500, 100000, false); 2131 } 2132 2133 static int rtl822x_config_inband(struct phy_device *phydev, unsigned int modes) 2134 { 2135 return rtl822x_serdes_write(phydev, RTL822X_VND1_SERDES_ADDR_AUTONEG, 2136 (modes != LINK_INBAND_DISABLE) ? 2137 RTL822X_VND1_SERDES_INBAND_ENABLE : 2138 RTL822X_VND1_SERDES_INBAND_DISABLE); 2139 } 2140 2141 static unsigned int rtl822x_inband_caps(struct phy_device *phydev, 2142 phy_interface_t interface) 2143 { 2144 switch (interface) { 2145 case PHY_INTERFACE_MODE_2500BASEX: 2146 return LINK_INBAND_DISABLE; 2147 case PHY_INTERFACE_MODE_SGMII: 2148 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 2149 default: 2150 return 0; 2151 } 2152 } 2153 2154 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 2155 phy_interface_t iface) 2156 { 2157 int val; 2158 2159 /* Only rate matching at 2500base-x */ 2160 if (iface != PHY_INTERFACE_MODE_2500BASEX) 2161 return RATE_MATCH_NONE; 2162 2163 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 2164 if (val < 0) 2165 return val; 2166 2167 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 2168 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 2169 return RATE_MATCH_PAUSE; 2170 2171 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 2172 return RATE_MATCH_NONE; 2173 } 2174 2175 static int rtl822x_get_features(struct phy_device *phydev) 2176 { 2177 int val; 2178 2179 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 2180 if (val < 0) 2181 return val; 2182 2183 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 2184 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 2185 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 2186 phydev->supported, val & MDIO_PMA_SPEED_5G); 2187 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2188 phydev->supported, val & MDIO_SPEED_10G); 2189 2190 return genphy_read_abilities(phydev); 2191 } 2192 2193 static int rtl822x_config_aneg(struct phy_device *phydev) 2194 { 2195 int ret = 0; 2196 2197 if (phydev->autoneg == AUTONEG_ENABLE) { 2198 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 2199 2200 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 2201 RTL_MDIO_AN_10GBT_CTRL, 2202 MDIO_AN_10GBT_CTRL_ADV2_5G | 2203 MDIO_AN_10GBT_CTRL_ADV5G | 2204 MDIO_AN_10GBT_CTRL_ADV10G, adv); 2205 if (ret < 0) 2206 return ret; 2207 } 2208 2209 return __genphy_config_aneg(phydev, ret); 2210 } 2211 2212 static void rtl822xb_update_interface(struct phy_device *phydev) 2213 { 2214 int val; 2215 2216 if (!phydev->link) 2217 return; 2218 2219 /* Change interface according to serdes mode */ 2220 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 2221 if (val < 0) 2222 return; 2223 2224 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 2225 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 2226 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 2227 break; 2228 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 2229 phydev->interface = PHY_INTERFACE_MODE_SGMII; 2230 break; 2231 } 2232 } 2233 2234 static int rtl822x_read_status(struct phy_device *phydev) 2235 { 2236 int lpadv, ret; 2237 2238 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 2239 2240 ret = rtlgen_read_status(phydev); 2241 if (ret < 0) 2242 return ret; 2243 2244 if (phydev->autoneg == AUTONEG_DISABLE || 2245 !phydev->autoneg_complete) 2246 return 0; 2247 2248 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 2249 if (lpadv < 0) 2250 return lpadv; 2251 2252 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 2253 2254 return 0; 2255 } 2256 2257 static int rtl822xb_read_status(struct phy_device *phydev) 2258 { 2259 int ret; 2260 2261 ret = rtl822x_read_status(phydev); 2262 if (ret < 0) 2263 return ret; 2264 2265 rtl822xb_update_interface(phydev); 2266 2267 return 0; 2268 } 2269 2270 static int rtl822x_c45_get_features(struct phy_device *phydev) 2271 { 2272 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2273 phydev->supported); 2274 2275 return genphy_c45_pma_read_abilities(phydev); 2276 } 2277 2278 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 2279 { 2280 bool changed = false; 2281 int ret, val; 2282 2283 if (phydev->autoneg == AUTONEG_DISABLE) 2284 return genphy_c45_pma_setup_forced(phydev); 2285 2286 ret = genphy_c45_an_config_aneg(phydev); 2287 if (ret < 0) 2288 return ret; 2289 if (ret > 0) 2290 changed = true; 2291 2292 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 2293 2294 /* Vendor register as C45 has no standardized support for 1000BaseT */ 2295 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 2296 RTL822X_VND2_C22_REG(MII_CTRL1000), 2297 ADVERTISE_1000FULL, val); 2298 if (ret < 0) 2299 return ret; 2300 if (ret > 0) 2301 changed = true; 2302 2303 return genphy_c45_check_and_restart_aneg(phydev, changed); 2304 } 2305 2306 static int rtl822x_c45_read_status(struct phy_device *phydev) 2307 { 2308 int ret, val; 2309 2310 /* Vendor register as C45 has no standardized support for 1000BaseT */ 2311 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 2312 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 2313 RTL822X_VND2_C22_REG(MII_STAT1000)); 2314 if (val < 0) 2315 return val; 2316 } else { 2317 val = 0; 2318 } 2319 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 2320 2321 ret = genphy_c45_read_status(phydev); 2322 if (ret < 0) 2323 return ret; 2324 2325 if (!phydev->link) { 2326 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2327 return 0; 2328 } 2329 2330 /* Read actual speed from vendor register. */ 2331 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 2332 RTL822X_VND2_C22_REG(RTL_PHYSR)); 2333 if (val < 0) 2334 return val; 2335 2336 rtlgen_decode_physr(phydev, val); 2337 2338 return 0; 2339 } 2340 2341 static int rtl822x_c45_soft_reset(struct phy_device *phydev) 2342 { 2343 int ret, val; 2344 2345 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 2346 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 2347 if (ret < 0) 2348 return ret; 2349 2350 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, 2351 MDIO_CTRL1, val, 2352 !(val & MDIO_CTRL1_RESET), 2353 5000, 100000, true); 2354 } 2355 2356 static int rtl822xb_c45_read_status(struct phy_device *phydev) 2357 { 2358 int ret; 2359 2360 ret = rtl822x_c45_read_status(phydev); 2361 if (ret < 0) 2362 return ret; 2363 2364 rtl822xb_update_interface(phydev); 2365 2366 return 0; 2367 } 2368 2369 static int rtl822xb_led_brightness_set(struct phy_device *phydev, u8 index, 2370 enum led_brightness value) 2371 { 2372 int ret; 2373 2374 if (index >= RTL8211x_LED_COUNT) 2375 return -EINVAL; 2376 2377 /* clear HW LED setup */ 2378 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2379 RTL822X_VND2_LED(index), 0); 2380 if (ret < 0) 2381 return ret; 2382 2383 /* clear HW LED blink */ 2384 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6, 2385 RTL822X_VND2_LED_ACT(index)); 2386 if (ret < 0) 2387 return ret; 2388 2389 if (value != LED_OFF) 2390 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 2391 RTL822X_VND2_LCR7, 2392 RTL822X_VND2_LED_POLAR(index)); 2393 else 2394 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 2395 RTL822X_VND2_LCR7, 2396 RTL822X_VND2_LED_POLAR(index)); 2397 } 2398 2399 static int rtl822xb_led_hw_is_supported(struct phy_device *phydev, u8 index, 2400 unsigned long rules) 2401 { 2402 const unsigned long act_mask = BIT(TRIGGER_NETDEV_RX) | 2403 BIT(TRIGGER_NETDEV_TX); 2404 2405 const unsigned long link_mask = BIT(TRIGGER_NETDEV_LINK) | 2406 BIT(TRIGGER_NETDEV_LINK_10) | 2407 BIT(TRIGGER_NETDEV_LINK_100) | 2408 BIT(TRIGGER_NETDEV_LINK_1000) | 2409 BIT(TRIGGER_NETDEV_LINK_2500); 2410 2411 if (index >= RTL8211x_LED_COUNT) 2412 return -EINVAL; 2413 2414 /* Filter out any other unsupported triggers. */ 2415 if (rules & ~(link_mask | act_mask)) 2416 return -EOPNOTSUPP; 2417 2418 /* RX and TX are not differentiated, they are not possible 2419 * without combination with a link trigger. 2420 */ 2421 if ((rules & act_mask) && !(rules & link_mask)) 2422 return -EOPNOTSUPP; 2423 2424 return 0; 2425 } 2426 2427 static int rtl822xb_led_hw_control_get(struct phy_device *phydev, u8 index, 2428 unsigned long *rules) 2429 { 2430 int val; 2431 2432 if (index >= RTL8211x_LED_COUNT) 2433 return -EINVAL; 2434 2435 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LED(index)); 2436 if (val < 0) 2437 return val; 2438 2439 if (val & RTL822X_VND2_LCR_LINK_10) 2440 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 2441 2442 if (val & RTL822X_VND2_LCR_LINK_100) 2443 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 2444 2445 if (val & RTL822X_VND2_LCR_LINK_1000) 2446 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 2447 2448 if (val & RTL822X_VND2_LCR_LINK_2500) 2449 __set_bit(TRIGGER_NETDEV_LINK_2500, rules); 2450 2451 if ((val & RTL822X_VND2_LCR_LINK_10) && 2452 (val & RTL822X_VND2_LCR_LINK_100) && 2453 (val & RTL822X_VND2_LCR_LINK_1000) && 2454 (val & RTL822X_VND2_LCR_LINK_2500)) 2455 __set_bit(TRIGGER_NETDEV_LINK, rules); 2456 2457 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6); 2458 if (val < 0) 2459 return val; 2460 2461 if (val & RTL822X_VND2_LED_ACT(index)) { 2462 __set_bit(TRIGGER_NETDEV_RX, rules); 2463 __set_bit(TRIGGER_NETDEV_TX, rules); 2464 } 2465 2466 return 0; 2467 } 2468 2469 static int rtl822xb_led_hw_control_set(struct phy_device *phydev, u8 index, 2470 unsigned long rules) 2471 { 2472 u16 val = 0; 2473 bool act; 2474 int ret; 2475 2476 if (index >= RTL8211x_LED_COUNT) 2477 return -EINVAL; 2478 2479 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2480 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 2481 val |= RTL822X_VND2_LCR_LINK_10; 2482 2483 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2484 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 2485 val |= RTL822X_VND2_LCR_LINK_100; 2486 2487 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2488 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 2489 val |= RTL822X_VND2_LCR_LINK_1000; 2490 2491 if (test_bit(TRIGGER_NETDEV_LINK, &rules) || 2492 test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) 2493 val |= RTL822X_VND2_LCR_LINK_2500; 2494 2495 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2496 RTL822X_VND2_LED(index), val); 2497 if (ret < 0) 2498 return ret; 2499 2500 act = test_bit(TRIGGER_NETDEV_RX, &rules) || 2501 test_bit(TRIGGER_NETDEV_TX, &rules); 2502 2503 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR6, 2504 RTL822X_VND2_LED_ACT(index), act ? 2505 RTL822X_VND2_LED_ACT(index) : 0); 2506 if (ret < 0) 2507 return ret; 2508 2509 /* Reset polarity to default */ 2510 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_LCR7, 2511 RTL822X_VND2_LED_POLAR(index)); 2512 } 2513 2514 static int rtl8224_cable_test_start(struct phy_device *phydev) 2515 { 2516 u32 val; 2517 int ret; 2518 2519 /* disable auto-negotiation and force 1000/Full */ 2520 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 2521 RTL822X_VND2_C22_REG(MII_BMCR), 2522 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10, 2523 BMCR_SPEED1000 | BMCR_FULLDPLX); 2524 if (ret) 2525 return ret; 2526 2527 mdelay(500); 2528 2529 /* trigger cable test */ 2530 val = RTL8224_MII_RTCT_ENABLE; 2531 val |= RTL8224_MII_RTCT_PAIR_A; 2532 val |= RTL8224_MII_RTCT_PAIR_B; 2533 val |= RTL8224_MII_RTCT_PAIR_C; 2534 val |= RTL8224_MII_RTCT_PAIR_D; 2535 2536 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 2537 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT), 2538 RTL8224_MII_RTCT_DONE, val); 2539 } 2540 2541 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg) 2542 { 2543 int ret; 2544 2545 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 2546 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR), 2547 reg); 2548 if (ret) 2549 return ret; 2550 2551 return phy_read_mmd(phydev, MDIO_MMD_VEND2, 2552 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA)); 2553 } 2554 2555 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair) 2556 { 2557 int cable_len; 2558 u32 reg_len; 2559 int ret; 2560 u32 cm; 2561 2562 reg_len = RTL8224_SRAM_RTCT_LEN(pair); 2563 2564 ret = rtl8224_sram_read(phydev, reg_len); 2565 if (ret < 0) 2566 return ret; 2567 2568 cable_len = ret & 0xff00; 2569 2570 ret = rtl8224_sram_read(phydev, reg_len + 1); 2571 if (ret < 0) 2572 return ret; 2573 2574 cable_len |= (ret & 0xff00) >> 8; 2575 2576 cable_len -= 620; 2577 cable_len = max(cable_len, 0); 2578 2579 cm = cable_len * 100 / 78; 2580 2581 return cm; 2582 } 2583 2584 static int rtl8224_cable_test_result_trans(u32 result) 2585 { 2586 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE)) 2587 return -EBUSY; 2588 2589 if (result & RTL8224_SRAM_RTCT_FAULT_OK) 2590 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 2591 2592 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN) 2593 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 2594 2595 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT) 2596 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 2597 2598 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY) 2599 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 2600 2601 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT) 2602 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 2603 2604 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 2605 } 2606 2607 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair) 2608 { 2609 int fault_rslt; 2610 int ret; 2611 2612 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair)); 2613 if (ret < 0) 2614 return ret; 2615 2616 fault_rslt = rtl8224_cable_test_result_trans(ret); 2617 if (fault_rslt < 0) 2618 return 0; 2619 2620 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 2621 if (ret < 0) 2622 return ret; 2623 2624 switch (fault_rslt) { 2625 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 2626 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 2627 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 2628 ret = rtl8224_pair_len_get(phydev, pair); 2629 if (ret < 0) 2630 return ret; 2631 2632 return ethnl_cable_test_fault_length(phydev, pair, ret); 2633 default: 2634 return 0; 2635 } 2636 } 2637 2638 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished) 2639 { 2640 unsigned int pair; 2641 int ret; 2642 2643 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 2644 ret = rtl8224_cable_test_report_pair(phydev, pair); 2645 if (ret == -EBUSY) { 2646 *finished = false; 2647 return 0; 2648 } 2649 2650 if (ret < 0) 2651 return ret; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished) 2658 { 2659 int ret; 2660 2661 *finished = false; 2662 2663 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 2664 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT)); 2665 if (ret < 0) 2666 return ret; 2667 2668 if (!(ret & RTL8224_MII_RTCT_DONE)) 2669 return 0; 2670 2671 *finished = true; 2672 2673 return rtl8224_cable_test_report(phydev, finished); 2674 } 2675 2676 static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, 2677 u32 regnum, u16 mask, u16 set) 2678 { 2679 int val, ret; 2680 2681 phy_lock_mdio_bus(phydev); 2682 2683 val = __phy_package_read_mmd(phydev, 0, devad, regnum); 2684 if (val < 0) { 2685 ret = val; 2686 goto exit; 2687 } 2688 2689 val &= ~mask; 2690 val |= set; 2691 2692 ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); 2693 2694 exit: 2695 phy_unlock_mdio_bus(phydev); 2696 return ret; 2697 } 2698 2699 static int rtl8224_mdi_config_order(struct phy_device *phydev) 2700 { 2701 struct device_node *np = phydev->mdio.dev.of_node; 2702 u8 port_offset = phydev->mdio.addr & 3; 2703 u32 order = 0; 2704 int ret; 2705 2706 ret = of_property_read_u32(np, "enet-phy-pair-order", &order); 2707 2708 /* Do nothing in case the property is not present */ 2709 if (ret == -EINVAL || ret == -ENOSYS) 2710 return 0; 2711 2712 if (ret) 2713 return ret; 2714 2715 if (order & ~1) 2716 return -EINVAL; 2717 2718 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2719 RTL8224_VND1_MDI_PAIR_SWAP, 2720 BIT(port_offset), 2721 order ? BIT(port_offset) : 0); 2722 } 2723 2724 static int rtl8224_mdi_config_polarity(struct phy_device *phydev) 2725 { 2726 struct device_node *np = phydev->mdio.dev.of_node; 2727 u8 offset = (phydev->mdio.addr & 3) * 4; 2728 u32 polarity = 0; 2729 int ret; 2730 2731 ret = of_property_read_u32(np, "enet-phy-pair-polarity", &polarity); 2732 2733 /* Do nothing if the property is not present */ 2734 if (ret == -EINVAL || ret == -ENOSYS) 2735 return 0; 2736 2737 if (ret) 2738 return ret; 2739 2740 if (polarity & ~0xf) 2741 return -EINVAL; 2742 2743 return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, 2744 RTL8224_VND1_MDI_POLARITY_SWAP, 2745 0xf << offset, 2746 polarity << offset); 2747 } 2748 2749 static int rtl8224_config_init(struct phy_device *phydev) 2750 { 2751 int ret; 2752 2753 ret = rtl8224_mdi_config_order(phydev); 2754 if (ret) 2755 return ret; 2756 2757 return rtl8224_mdi_config_polarity(phydev); 2758 } 2759 2760 static int rtl8224_probe(struct phy_device *phydev) 2761 { 2762 /* Chip exposes 4 ports, join all of them in the same package */ 2763 return devm_phy_package_join(&phydev->mdio.dev, phydev, 2764 phydev->mdio.addr & ~3, 0); 2765 } 2766 2767 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 2768 { 2769 int val; 2770 2771 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 2772 val = phy_read(phydev, 0x13); 2773 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 2774 2775 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 2776 } 2777 2778 /* On internal PHY's MMD reads over C22 always return 0. 2779 * Check a MMD register which is known to be non-zero. 2780 */ 2781 static bool rtlgen_supports_mmd(struct phy_device *phydev) 2782 { 2783 int val; 2784 2785 phy_lock_mdio_bus(phydev); 2786 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 2787 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 2788 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 2789 val = __phy_read(phydev, MII_MMD_DATA); 2790 phy_unlock_mdio_bus(phydev); 2791 2792 return val > 0; 2793 } 2794 2795 static int rtlgen_match_phy_device(struct phy_device *phydev, 2796 const struct phy_driver *phydrv) 2797 { 2798 return phydev->phy_id == RTL_GENERIC_PHYID && 2799 !rtlgen_supports_2_5gbps(phydev); 2800 } 2801 2802 static int rtl8226_match_phy_device(struct phy_device *phydev, 2803 const struct phy_driver *phydrv) 2804 { 2805 return phydev->phy_id == RTL_GENERIC_PHYID && 2806 rtlgen_supports_2_5gbps(phydev) && 2807 rtlgen_supports_mmd(phydev); 2808 } 2809 2810 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 2811 bool is_c45) 2812 { 2813 if (phydev->is_c45) 2814 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 2815 else 2816 return !is_c45 && (id == phydev->phy_id); 2817 } 2818 2819 static int rtl8221b_match_phy_device(struct phy_device *phydev, 2820 const struct phy_driver *phydrv) 2821 { 2822 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 2823 } 2824 2825 static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev, 2826 const struct phy_driver *phydrv) 2827 { 2828 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true) || 2829 rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 2830 } 2831 2832 static int rtl8221b_vm_cg_match_phy_device(struct phy_device *phydev, 2833 const struct phy_driver *phydrv) 2834 { 2835 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true) || 2836 rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false); 2837 } 2838 2839 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev, 2840 const struct phy_driver *phydrv) 2841 { 2842 if (phydev->is_c45) 2843 return false; 2844 2845 switch (phydev->phy_id) { 2846 case RTL_GENERIC_PHYID: 2847 case RTL_8221B: 2848 case RTL_8251B: 2849 case RTL_8261C: 2850 case 0x001cc841: 2851 break; 2852 default: 2853 return false; 2854 } 2855 2856 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 2857 } 2858 2859 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev, 2860 const struct phy_driver *phydrv) 2861 { 2862 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 2863 } 2864 2865 static int rtlgen_resume(struct phy_device *phydev) 2866 { 2867 int ret = genphy_resume(phydev); 2868 2869 /* Internal PHY's from RTL8168h up may not be instantly ready */ 2870 msleep(20); 2871 2872 return ret; 2873 } 2874 2875 static int rtlgen_c45_resume(struct phy_device *phydev) 2876 { 2877 int ret = genphy_c45_pma_resume(phydev); 2878 2879 msleep(20); 2880 2881 return ret; 2882 } 2883 2884 static int rtl9000a_config_init(struct phy_device *phydev) 2885 { 2886 phydev->autoneg = AUTONEG_DISABLE; 2887 phydev->speed = SPEED_100; 2888 phydev->duplex = DUPLEX_FULL; 2889 2890 return 0; 2891 } 2892 2893 static int rtl9000a_config_aneg(struct phy_device *phydev) 2894 { 2895 int ret; 2896 u16 ctl = 0; 2897 2898 switch (phydev->master_slave_set) { 2899 case MASTER_SLAVE_CFG_MASTER_FORCE: 2900 ctl |= CTL1000_AS_MASTER; 2901 break; 2902 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2903 break; 2904 case MASTER_SLAVE_CFG_UNKNOWN: 2905 case MASTER_SLAVE_CFG_UNSUPPORTED: 2906 return 0; 2907 default: 2908 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2909 return -EOPNOTSUPP; 2910 } 2911 2912 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 2913 if (ret == 1) 2914 ret = genphy_soft_reset(phydev); 2915 2916 return ret; 2917 } 2918 2919 static int rtl9000a_read_status(struct phy_device *phydev) 2920 { 2921 int ret; 2922 2923 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 2924 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 2925 2926 ret = genphy_update_link(phydev); 2927 if (ret) 2928 return ret; 2929 2930 ret = phy_read(phydev, MII_CTRL1000); 2931 if (ret < 0) 2932 return ret; 2933 if (ret & CTL1000_AS_MASTER) 2934 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 2935 else 2936 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 2937 2938 ret = phy_read(phydev, MII_STAT1000); 2939 if (ret < 0) 2940 return ret; 2941 if (ret & LPA_1000MSRES) 2942 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 2943 else 2944 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 2945 2946 return 0; 2947 } 2948 2949 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 2950 { 2951 int err; 2952 2953 err = phy_read(phydev, RTL8211F_INSR); 2954 2955 return (err < 0) ? err : 0; 2956 } 2957 2958 static int rtl9000a_config_intr(struct phy_device *phydev) 2959 { 2960 u16 val; 2961 int err; 2962 2963 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2964 err = rtl9000a_ack_interrupt(phydev); 2965 if (err) 2966 return err; 2967 2968 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 2969 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2970 } else { 2971 val = ~0; 2972 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2973 if (err) 2974 return err; 2975 2976 err = rtl9000a_ack_interrupt(phydev); 2977 } 2978 2979 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 2980 } 2981 2982 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 2983 { 2984 int irq_status; 2985 2986 irq_status = phy_read(phydev, RTL8211F_INSR); 2987 if (irq_status < 0) { 2988 phy_error(phydev); 2989 return IRQ_NONE; 2990 } 2991 2992 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 2993 return IRQ_NONE; 2994 2995 phy_trigger_machine(phydev); 2996 2997 return IRQ_HANDLED; 2998 } 2999 3000 static int rtl8221b_ack_interrupt(struct phy_device *phydev) 3001 { 3002 int err; 3003 3004 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR); 3005 3006 return (err < 0) ? err : 0; 3007 } 3008 3009 static int rtl8221b_config_intr(struct phy_device *phydev) 3010 { 3011 int err; 3012 3013 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 3014 err = rtl8221b_ack_interrupt(phydev); 3015 if (err) 3016 return err; 3017 3018 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER, 3019 RTL8221B_VND2_INER_LINK_STATUS); 3020 } else { 3021 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, 3022 RTL8221B_VND2_INER, 0); 3023 if (err) 3024 return err; 3025 3026 err = rtl8221b_ack_interrupt(phydev); 3027 } 3028 3029 return err; 3030 } 3031 3032 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) 3033 { 3034 int err; 3035 3036 err = rtl8221b_ack_interrupt(phydev); 3037 if (err) { 3038 phy_error(phydev); 3039 return IRQ_NONE; 3040 } 3041 3042 phy_trigger_machine(phydev); 3043 3044 return IRQ_HANDLED; 3045 } 3046 3047 static int rtlgen_sfp_get_features(struct phy_device *phydev) 3048 { 3049 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 3050 phydev->supported); 3051 3052 /* set default mode */ 3053 phydev->speed = SPEED_10000; 3054 phydev->duplex = DUPLEX_FULL; 3055 3056 phydev->port = PORT_FIBRE; 3057 3058 return 0; 3059 } 3060 3061 static int rtlgen_sfp_read_status(struct phy_device *phydev) 3062 { 3063 int val, err; 3064 3065 err = genphy_update_link(phydev); 3066 if (err) 3067 return err; 3068 3069 if (!phydev->link) 3070 return 0; 3071 3072 val = phy_read(phydev, RTL_PHYSR); 3073 if (val < 0) 3074 return val; 3075 3076 rtlgen_decode_physr(phydev, val); 3077 3078 return 0; 3079 } 3080 3081 static int rtlgen_sfp_config_aneg(struct phy_device *phydev) 3082 { 3083 return 0; 3084 } 3085 3086 static struct phy_driver realtek_drvs[] = { 3087 { 3088 PHY_ID_MATCH_EXACT(0x00008201), 3089 .name = "RTL8201CP Ethernet", 3090 .read_page = rtl821x_read_page, 3091 .write_page = rtl821x_write_page, 3092 }, { 3093 PHY_ID_MATCH_EXACT(0x001cc816), 3094 .name = "RTL8201F Fast Ethernet", 3095 .config_intr = &rtl8201_config_intr, 3096 .handle_interrupt = rtl8201_handle_interrupt, 3097 .suspend = genphy_suspend, 3098 .resume = genphy_resume, 3099 .read_page = rtl821x_read_page, 3100 .write_page = rtl821x_write_page, 3101 }, { 3102 PHY_ID_MATCH_MODEL(0x001cc880), 3103 .name = "RTL8208 Fast Ethernet", 3104 .read_mmd = genphy_read_mmd_unsupported, 3105 .write_mmd = genphy_write_mmd_unsupported, 3106 .suspend = genphy_suspend, 3107 .resume = genphy_resume, 3108 .read_page = rtl821x_read_page, 3109 .write_page = rtl821x_write_page, 3110 }, { 3111 PHY_ID_MATCH_EXACT(0x001cc910), 3112 .name = "RTL8211 Gigabit Ethernet", 3113 .config_aneg = rtl8211_config_aneg, 3114 .read_mmd = &genphy_read_mmd_unsupported, 3115 .write_mmd = &genphy_write_mmd_unsupported, 3116 .read_page = rtl821x_read_page, 3117 .write_page = rtl821x_write_page, 3118 }, { 3119 PHY_ID_MATCH_EXACT(0x001cc912), 3120 .name = "RTL8211B Gigabit Ethernet", 3121 .config_intr = &rtl8211b_config_intr, 3122 .handle_interrupt = rtl821x_handle_interrupt, 3123 .read_mmd = &genphy_read_mmd_unsupported, 3124 .write_mmd = &genphy_write_mmd_unsupported, 3125 .suspend = rtl8211b_suspend, 3126 .resume = rtl8211b_resume, 3127 .read_page = rtl821x_read_page, 3128 .write_page = rtl821x_write_page, 3129 }, { 3130 PHY_ID_MATCH_EXACT(0x001cc913), 3131 .name = "RTL8211C Gigabit Ethernet", 3132 .config_init = rtl8211c_config_init, 3133 .read_mmd = &genphy_read_mmd_unsupported, 3134 .write_mmd = &genphy_write_mmd_unsupported, 3135 .read_page = rtl821x_read_page, 3136 .write_page = rtl821x_write_page, 3137 }, { 3138 PHY_ID_MATCH_EXACT(0x001cc914), 3139 .name = "RTL8211DN Gigabit Ethernet", 3140 .config_intr = rtl8211e_config_intr, 3141 .handle_interrupt = rtl821x_handle_interrupt, 3142 .suspend = genphy_suspend, 3143 .resume = genphy_resume, 3144 .read_page = rtl821x_read_page, 3145 .write_page = rtl821x_write_page, 3146 }, { 3147 PHY_ID_MATCH_EXACT(0x001cc915), 3148 .name = "RTL8211E Gigabit Ethernet", 3149 .config_init = &rtl8211e_config_init, 3150 .config_intr = &rtl8211e_config_intr, 3151 .handle_interrupt = rtl821x_handle_interrupt, 3152 .suspend = genphy_suspend, 3153 .resume = genphy_resume, 3154 .read_page = rtl821x_read_page, 3155 .write_page = rtl821x_write_page, 3156 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 3157 .led_hw_control_get = rtl8211e_led_hw_control_get, 3158 .led_hw_control_set = rtl8211e_led_hw_control_set, 3159 }, { 3160 PHY_ID_MATCH_EXACT(0x001cc916), 3161 .name = "RTL8211F Gigabit Ethernet", 3162 .probe = rtl8211f_probe, 3163 .config_init = &rtl8211f_config_init, 3164 .read_status = rtlgen_read_status, 3165 .config_intr = &rtl8211f_config_intr, 3166 .handle_interrupt = rtl8211f_handle_interrupt, 3167 .set_wol = rtl8211f_set_wol, 3168 .get_wol = rtl8211f_get_wol, 3169 .suspend = rtl8211f_suspend, 3170 .resume = rtl8211f_resume, 3171 .read_page = rtl821x_read_page, 3172 .write_page = rtl821x_write_page, 3173 .flags = PHY_ALWAYS_CALL_SUSPEND, 3174 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 3175 .led_hw_control_get = rtl8211f_led_hw_control_get, 3176 .led_hw_control_set = rtl8211f_led_hw_control_set, 3177 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 3178 }, { 3179 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 3180 .name = "RTL8211F-VD Gigabit Ethernet", 3181 .probe = rtl821x_probe, 3182 .config_init = &rtl8211f_config_init, 3183 .read_status = rtlgen_read_status, 3184 .config_intr = &rtl8211f_config_intr, 3185 .handle_interrupt = rtl8211f_handle_interrupt, 3186 .suspend = rtl821x_suspend, 3187 .resume = rtl821x_resume, 3188 .read_page = rtl821x_read_page, 3189 .write_page = rtl821x_write_page, 3190 .flags = PHY_ALWAYS_CALL_SUSPEND, 3191 .led_hw_is_supported = rtl8211x_led_hw_is_supported, 3192 .led_hw_control_get = rtl8211f_led_hw_control_get, 3193 .led_hw_control_set = rtl8211f_led_hw_control_set, 3194 .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, 3195 }, { 3196 .name = "Generic FE-GE Realtek PHY", 3197 .match_phy_device = rtlgen_match_phy_device, 3198 .read_status = rtlgen_read_status, 3199 .suspend = genphy_suspend, 3200 .resume = rtlgen_resume, 3201 .read_page = rtl821x_read_page, 3202 .write_page = rtl821x_write_page, 3203 .read_mmd = rtlgen_read_mmd, 3204 .write_mmd = rtlgen_write_mmd, 3205 }, { 3206 .name = "RTL8226 2.5Gbps PHY", 3207 .match_phy_device = rtl8226_match_phy_device, 3208 .get_features = rtl822x_get_features, 3209 .config_aneg = rtl822x_config_aneg, 3210 .read_status = rtl822x_read_status, 3211 .suspend = genphy_suspend, 3212 .resume = rtlgen_resume, 3213 .read_page = rtl821x_read_page, 3214 .write_page = rtl821x_write_page, 3215 .read_mmd = rtl822xb_read_mmd, 3216 .write_mmd = rtl822xb_write_mmd, 3217 }, { 3218 .match_phy_device = rtl8221b_match_phy_device, 3219 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 3220 .get_features = rtl822x_get_features, 3221 .config_aneg = rtl822x_config_aneg, 3222 .config_init = rtl822xb_config_init, 3223 .inband_caps = rtl822x_inband_caps, 3224 .config_inband = rtl822x_config_inband, 3225 .get_rate_matching = rtl822xb_get_rate_matching, 3226 .read_status = rtl822xb_read_status, 3227 .suspend = genphy_suspend, 3228 .resume = rtlgen_resume, 3229 .read_page = rtl821x_read_page, 3230 .write_page = rtl821x_write_page, 3231 .read_mmd = rtl822xb_read_mmd, 3232 .write_mmd = rtl822xb_write_mmd, 3233 }, { 3234 PHY_ID_MATCH_EXACT(0x001cc838), 3235 .name = "RTL8226-CG 2.5Gbps PHY", 3236 .soft_reset = rtl822x_c45_soft_reset, 3237 .get_features = rtl822x_c45_get_features, 3238 .config_aneg = rtl822x_c45_config_aneg, 3239 .probe = rtl8226_probe, 3240 .config_init = rtl822x_config_init, 3241 .inband_caps = rtl822x_inband_caps, 3242 .config_inband = rtl822x_config_inband, 3243 .read_status = rtl822xb_c45_read_status, 3244 .suspend = genphy_c45_pma_suspend, 3245 .resume = rtlgen_c45_resume, 3246 .read_mmd = rtl822xb_read_mmd, 3247 .write_mmd = rtl822xb_write_mmd, 3248 }, { 3249 PHY_ID_MATCH_EXACT(0x001cc848), 3250 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 3251 .get_features = rtl822x_get_features, 3252 .config_aneg = rtl822x_config_aneg, 3253 .config_init = rtl822xb_config_init, 3254 .inband_caps = rtl822x_inband_caps, 3255 .config_inband = rtl822x_config_inband, 3256 .get_rate_matching = rtl822xb_get_rate_matching, 3257 .read_status = rtl822xb_read_status, 3258 .suspend = genphy_suspend, 3259 .resume = rtlgen_resume, 3260 .read_page = rtl821x_read_page, 3261 .write_page = rtl821x_write_page, 3262 .read_mmd = rtl822xb_read_mmd, 3263 .write_mmd = rtl822xb_write_mmd, 3264 }, { 3265 .match_phy_device = rtl8221b_vb_cg_match_phy_device, 3266 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 3267 .config_intr = rtl8221b_config_intr, 3268 .handle_interrupt = rtl8221b_handle_interrupt, 3269 .probe = rtl822x_probe, 3270 .config_init = rtl822xb_config_init, 3271 .inband_caps = rtl822x_inband_caps, 3272 .config_inband = rtl822x_config_inband, 3273 .get_rate_matching = rtl822xb_get_rate_matching, 3274 .get_features = rtl822x_c45_get_features, 3275 .config_aneg = rtl822x_c45_config_aneg, 3276 .read_status = rtl822xb_c45_read_status, 3277 .suspend = genphy_c45_pma_suspend, 3278 .resume = rtlgen_c45_resume, 3279 .read_page = rtl821x_read_page, 3280 .write_page = rtl821x_write_page, 3281 .read_mmd = rtl822xb_read_mmd, 3282 .write_mmd = rtl822xb_write_mmd, 3283 .led_brightness_set = rtl822xb_led_brightness_set, 3284 .led_hw_is_supported = rtl822xb_led_hw_is_supported, 3285 .led_hw_control_get = rtl822xb_led_hw_control_get, 3286 .led_hw_control_set = rtl822xb_led_hw_control_set, 3287 }, { 3288 .match_phy_device = rtl8221b_vm_cg_match_phy_device, 3289 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 3290 .config_intr = rtl8221b_config_intr, 3291 .handle_interrupt = rtl8221b_handle_interrupt, 3292 .probe = rtl822x_probe, 3293 .config_init = rtl822xb_config_init, 3294 .inband_caps = rtl822x_inband_caps, 3295 .config_inband = rtl822x_config_inband, 3296 .get_rate_matching = rtl822xb_get_rate_matching, 3297 .get_features = rtl822x_c45_get_features, 3298 .config_aneg = rtl822x_c45_config_aneg, 3299 .read_status = rtl822xb_c45_read_status, 3300 .suspend = genphy_c45_pma_suspend, 3301 .resume = rtlgen_c45_resume, 3302 .read_page = rtl821x_read_page, 3303 .write_page = rtl821x_write_page, 3304 .read_mmd = rtl822xb_read_mmd, 3305 .write_mmd = rtl822xb_write_mmd, 3306 .led_brightness_set = rtl822xb_led_brightness_set, 3307 .led_hw_is_supported = rtl822xb_led_hw_is_supported, 3308 .led_hw_control_get = rtl822xb_led_hw_control_get, 3309 .led_hw_control_set = rtl822xb_led_hw_control_set, 3310 }, { 3311 .match_phy_device = rtl8251b_c45_match_phy_device, 3312 .name = "RTL8251B 5Gbps PHY", 3313 .probe = rtl822x_probe, 3314 .get_features = rtl822x_get_features, 3315 .config_aneg = rtl822x_config_aneg, 3316 .read_status = rtl822x_read_status, 3317 .suspend = genphy_suspend, 3318 .resume = rtlgen_resume, 3319 .read_page = rtl821x_read_page, 3320 .write_page = rtl821x_write_page, 3321 }, { 3322 .match_phy_device = rtl_internal_nbaset_match_phy_device, 3323 .name = "Realtek Internal NBASE-T PHY", 3324 .flags = PHY_IS_INTERNAL, 3325 .probe = rtl822x_probe, 3326 .get_features = rtl822x_get_features, 3327 .config_aneg = rtl822x_config_aneg, 3328 .read_status = rtl822x_read_status, 3329 .suspend = genphy_suspend, 3330 .resume = rtlgen_resume, 3331 .read_page = rtl821x_read_page, 3332 .write_page = rtl821x_write_page, 3333 .read_mmd = rtl822x_read_mmd, 3334 .write_mmd = rtl822x_write_mmd, 3335 }, { 3336 PHY_ID_MATCH_EXACT(PHY_ID_RTL_DUMMY_SFP), 3337 .name = "Realtek SFP PHY Mode", 3338 .flags = PHY_IS_INTERNAL, 3339 .probe = rtl822x_probe, 3340 .get_features = rtlgen_sfp_get_features, 3341 .config_aneg = rtlgen_sfp_config_aneg, 3342 .read_status = rtlgen_sfp_read_status, 3343 .suspend = genphy_suspend, 3344 .resume = rtlgen_resume, 3345 .read_page = rtl821x_read_page, 3346 .write_page = rtl821x_write_page, 3347 .read_mmd = rtl822x_read_mmd, 3348 .write_mmd = rtl822x_write_mmd, 3349 }, { 3350 PHY_ID_MATCH_EXACT(0x001ccad0), 3351 .name = "RTL8224 2.5Gbps PHY", 3352 .flags = PHY_POLL_CABLE_TEST, 3353 .probe = rtl8224_probe, 3354 .config_init = rtl8224_config_init, 3355 .get_features = rtl822x_c45_get_features, 3356 .config_aneg = rtl822x_c45_config_aneg, 3357 .read_status = rtl822x_c45_read_status, 3358 .suspend = genphy_c45_pma_suspend, 3359 .resume = rtlgen_c45_resume, 3360 .cable_test_start = rtl8224_cable_test_start, 3361 .cable_test_get_status = rtl8224_cable_test_get_status, 3362 }, { 3363 PHY_ID_MATCH_EXACT(0x001cc961), 3364 .name = "RTL8366RB Gigabit Ethernet", 3365 .config_init = &rtl8366rb_config_init, 3366 /* These interrupts are handled by the irq controller 3367 * embedded inside the RTL8366RB, they get unmasked when the 3368 * irq is requested and ACKed by reading the status register, 3369 * which is done by the irqchip code. 3370 */ 3371 .config_intr = genphy_no_config_intr, 3372 .handle_interrupt = genphy_handle_interrupt_no_ack, 3373 .suspend = genphy_suspend, 3374 .resume = genphy_resume, 3375 }, { 3376 PHY_ID_MATCH_EXACT(0x001ccb00), 3377 .name = "RTL9000AA_RTL9000AN Ethernet", 3378 .features = PHY_BASIC_T1_FEATURES, 3379 .config_init = rtl9000a_config_init, 3380 .config_aneg = rtl9000a_config_aneg, 3381 .read_status = rtl9000a_read_status, 3382 .config_intr = rtl9000a_config_intr, 3383 .handle_interrupt = rtl9000a_handle_interrupt, 3384 .suspend = genphy_suspend, 3385 .resume = genphy_resume, 3386 .read_page = rtl821x_read_page, 3387 .write_page = rtl821x_write_page, 3388 }, { 3389 PHY_ID_MATCH_EXACT(0x001cc942), 3390 .name = "RTL8365MB-VC Gigabit Ethernet", 3391 /* Interrupt handling analogous to RTL8366RB */ 3392 .config_intr = genphy_no_config_intr, 3393 .handle_interrupt = genphy_handle_interrupt_no_ack, 3394 .suspend = genphy_suspend, 3395 .resume = genphy_resume, 3396 }, { 3397 PHY_ID_MATCH_EXACT(0x001cc960), 3398 .name = "RTL8366S Gigabit Ethernet", 3399 .suspend = genphy_suspend, 3400 .resume = genphy_resume, 3401 .read_mmd = genphy_read_mmd_unsupported, 3402 .write_mmd = genphy_write_mmd_unsupported, 3403 }, { 3404 PHY_ID_MATCH_EXACT(RTL_8261C_CG), 3405 .name = "Realtek RTL8261C/D 10Gbps PHY", 3406 .probe = rtl8261x_probe, 3407 .config_init = rtl8261x_config_init, 3408 .get_features = rtl8261x_get_features, 3409 .config_aneg = rtl8261x_config_aneg, 3410 .read_status = rtl8261x_read_status, 3411 .config_intr = rtl8261x_config_intr, 3412 .handle_interrupt = rtl8261x_handle_interrupt, 3413 .soft_reset = genphy_c45_pma_soft_reset, 3414 .suspend = genphy_c45_pma_suspend, 3415 .resume = genphy_c45_pma_resume, 3416 }, 3417 }; 3418 3419 module_phy_driver(realtek_drvs); 3420 3421 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 3422 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 3423 { } 3424 }; 3425 3426 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 3427