1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/module.h> 14 #include <linux/delay.h> 15 #include <linux/clk.h> 16 #include <linux/string_choices.h> 17 18 #include "realtek.h" 19 20 #define RTL821x_PHYSR 0x11 21 #define RTL821x_PHYSR_DUPLEX BIT(13) 22 #define RTL821x_PHYSR_SPEED GENMASK(15, 14) 23 24 #define RTL821x_INER 0x12 25 #define RTL8211B_INER_INIT 0x6400 26 #define RTL8211E_INER_LINK_STATUS BIT(10) 27 #define RTL8211F_INER_LINK_STATUS BIT(4) 28 29 #define RTL821x_INSR 0x13 30 31 #define RTL821x_EXT_PAGE_SELECT 0x1e 32 #define RTL821x_PAGE_SELECT 0x1f 33 34 #define RTL8211F_PHYCR1 0x18 35 #define RTL8211F_PHYCR2 0x19 36 #define RTL8211F_INSR 0x1d 37 38 #define RTL8211F_LEDCR 0x10 39 #define RTL8211F_LEDCR_MODE BIT(15) 40 #define RTL8211F_LEDCR_ACT_TXRX BIT(4) 41 #define RTL8211F_LEDCR_LINK_1000 BIT(3) 42 #define RTL8211F_LEDCR_LINK_100 BIT(1) 43 #define RTL8211F_LEDCR_LINK_10 BIT(0) 44 #define RTL8211F_LEDCR_MASK GENMASK(4, 0) 45 #define RTL8211F_LEDCR_SHIFT 5 46 47 #define RTL8211F_TX_DELAY BIT(8) 48 #define RTL8211F_RX_DELAY BIT(3) 49 50 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 51 #define RTL8211F_ALDPS_ENABLE BIT(2) 52 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 53 54 #define RTL8211E_CTRL_DELAY BIT(13) 55 #define RTL8211E_TX_DELAY BIT(12) 56 #define RTL8211E_RX_DELAY BIT(11) 57 58 #define RTL8211F_CLKOUT_EN BIT(0) 59 60 #define RTL8201F_ISR 0x1e 61 #define RTL8201F_ISR_ANERR BIT(15) 62 #define RTL8201F_ISR_DUPLEX BIT(13) 63 #define RTL8201F_ISR_LINK BIT(11) 64 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 65 RTL8201F_ISR_DUPLEX | \ 66 RTL8201F_ISR_LINK) 67 #define RTL8201F_IER 0x13 68 69 #define RTL822X_VND1_SERDES_OPTION 0x697a 70 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) 71 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 72 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 73 74 #define RTL822X_VND1_SERDES_CTRL3 0x7580 75 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) 76 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 77 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 78 79 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 80 * is set, they cannot be accessed by C45-over-C22. 81 */ 82 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg)) 83 84 #define RTL8366RB_POWER_SAVE 0x15 85 #define RTL8366RB_POWER_SAVE_ON BIT(12) 86 87 #define RTL9000A_GINMR 0x14 88 #define RTL9000A_GINMR_LINK_STATUS BIT(4) 89 90 #define RTL_VND2_PHYSR 0xa434 91 #define RTL_VND2_PHYSR_DUPLEX BIT(3) 92 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) 93 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) 94 #define RTL_VND2_PHYSR_MASTER BIT(11) 95 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) 96 97 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4 98 #define RTL_MDIO_AN_EEE_ADV 0xa5d0 99 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2 100 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4 101 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6 102 #define RTL_MDIO_PMA_SPEED 0xa616 103 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0 104 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4 105 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec 106 107 #define RTL_GENERIC_PHYID 0x001cc800 108 #define RTL_8211FVD_PHYID 0x001cc878 109 #define RTL_8221B 0x001cc840 110 #define RTL_8221B_VB_CG 0x001cc849 111 #define RTL_8221B_VN_CG 0x001cc84a 112 #define RTL_8251B 0x001cc862 113 114 #define RTL8211F_LED_COUNT 3 115 116 MODULE_DESCRIPTION("Realtek PHY driver"); 117 MODULE_AUTHOR("Johnson Leung"); 118 MODULE_LICENSE("GPL"); 119 120 struct rtl821x_priv { 121 u16 phycr1; 122 u16 phycr2; 123 bool has_phycr2; 124 struct clk *clk; 125 }; 126 127 static int rtl821x_read_page(struct phy_device *phydev) 128 { 129 return __phy_read(phydev, RTL821x_PAGE_SELECT); 130 } 131 132 static int rtl821x_write_page(struct phy_device *phydev, int page) 133 { 134 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 135 } 136 137 static int rtl821x_probe(struct phy_device *phydev) 138 { 139 struct device *dev = &phydev->mdio.dev; 140 struct rtl821x_priv *priv; 141 u32 phy_id = phydev->drv->phy_id; 142 int ret; 143 144 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 145 if (!priv) 146 return -ENOMEM; 147 148 priv->clk = devm_clk_get_optional_enabled(dev, NULL); 149 if (IS_ERR(priv->clk)) 150 return dev_err_probe(dev, PTR_ERR(priv->clk), 151 "failed to get phy clock\n"); 152 153 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1); 154 if (ret < 0) 155 return ret; 156 157 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 158 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 159 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 160 161 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); 162 if (priv->has_phycr2) { 163 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2); 164 if (ret < 0) 165 return ret; 166 167 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 168 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 169 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 170 } 171 172 phydev->priv = priv; 173 174 return 0; 175 } 176 177 static int rtl8201_ack_interrupt(struct phy_device *phydev) 178 { 179 int err; 180 181 err = phy_read(phydev, RTL8201F_ISR); 182 183 return (err < 0) ? err : 0; 184 } 185 186 static int rtl821x_ack_interrupt(struct phy_device *phydev) 187 { 188 int err; 189 190 err = phy_read(phydev, RTL821x_INSR); 191 192 return (err < 0) ? err : 0; 193 } 194 195 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 196 { 197 int err; 198 199 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 200 201 return (err < 0) ? err : 0; 202 } 203 204 static int rtl8201_config_intr(struct phy_device *phydev) 205 { 206 u16 val; 207 int err; 208 209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 210 err = rtl8201_ack_interrupt(phydev); 211 if (err) 212 return err; 213 214 val = BIT(13) | BIT(12) | BIT(11); 215 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 216 } else { 217 val = 0; 218 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 219 if (err) 220 return err; 221 222 err = rtl8201_ack_interrupt(phydev); 223 } 224 225 return err; 226 } 227 228 static int rtl8211b_config_intr(struct phy_device *phydev) 229 { 230 int err; 231 232 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 233 err = rtl821x_ack_interrupt(phydev); 234 if (err) 235 return err; 236 237 err = phy_write(phydev, RTL821x_INER, 238 RTL8211B_INER_INIT); 239 } else { 240 err = phy_write(phydev, RTL821x_INER, 0); 241 if (err) 242 return err; 243 244 err = rtl821x_ack_interrupt(phydev); 245 } 246 247 return err; 248 } 249 250 static int rtl8211e_config_intr(struct phy_device *phydev) 251 { 252 int err; 253 254 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 255 err = rtl821x_ack_interrupt(phydev); 256 if (err) 257 return err; 258 259 err = phy_write(phydev, RTL821x_INER, 260 RTL8211E_INER_LINK_STATUS); 261 } else { 262 err = phy_write(phydev, RTL821x_INER, 0); 263 if (err) 264 return err; 265 266 err = rtl821x_ack_interrupt(phydev); 267 } 268 269 return err; 270 } 271 272 static int rtl8211f_config_intr(struct phy_device *phydev) 273 { 274 u16 val; 275 int err; 276 277 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 278 err = rtl8211f_ack_interrupt(phydev); 279 if (err) 280 return err; 281 282 val = RTL8211F_INER_LINK_STATUS; 283 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 284 } else { 285 val = 0; 286 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 287 if (err) 288 return err; 289 290 err = rtl8211f_ack_interrupt(phydev); 291 } 292 293 return err; 294 } 295 296 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 297 { 298 int irq_status; 299 300 irq_status = phy_read(phydev, RTL8201F_ISR); 301 if (irq_status < 0) { 302 phy_error(phydev); 303 return IRQ_NONE; 304 } 305 306 if (!(irq_status & RTL8201F_ISR_MASK)) 307 return IRQ_NONE; 308 309 phy_trigger_machine(phydev); 310 311 return IRQ_HANDLED; 312 } 313 314 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 315 { 316 int irq_status, irq_enabled; 317 318 irq_status = phy_read(phydev, RTL821x_INSR); 319 if (irq_status < 0) { 320 phy_error(phydev); 321 return IRQ_NONE; 322 } 323 324 irq_enabled = phy_read(phydev, RTL821x_INER); 325 if (irq_enabled < 0) { 326 phy_error(phydev); 327 return IRQ_NONE; 328 } 329 330 if (!(irq_status & irq_enabled)) 331 return IRQ_NONE; 332 333 phy_trigger_machine(phydev); 334 335 return IRQ_HANDLED; 336 } 337 338 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 339 { 340 int irq_status; 341 342 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 343 if (irq_status < 0) { 344 phy_error(phydev); 345 return IRQ_NONE; 346 } 347 348 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 349 return IRQ_NONE; 350 351 phy_trigger_machine(phydev); 352 353 return IRQ_HANDLED; 354 } 355 356 static int rtl8211_config_aneg(struct phy_device *phydev) 357 { 358 int ret; 359 360 ret = genphy_config_aneg(phydev); 361 if (ret < 0) 362 return ret; 363 364 /* Quirk was copied from vendor driver. Unfortunately it includes no 365 * description of the magic numbers. 366 */ 367 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 368 phy_write(phydev, 0x17, 0x2138); 369 phy_write(phydev, 0x0e, 0x0260); 370 } else { 371 phy_write(phydev, 0x17, 0x2108); 372 phy_write(phydev, 0x0e, 0x0000); 373 } 374 375 return 0; 376 } 377 378 static int rtl8211c_config_init(struct phy_device *phydev) 379 { 380 /* RTL8211C has an issue when operating in Gigabit slave mode */ 381 return phy_set_bits(phydev, MII_CTRL1000, 382 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 383 } 384 385 static int rtl8211f_config_init(struct phy_device *phydev) 386 { 387 struct rtl821x_priv *priv = phydev->priv; 388 struct device *dev = &phydev->mdio.dev; 389 u16 val_txdly, val_rxdly; 390 int ret; 391 392 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, 393 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 394 priv->phycr1); 395 if (ret < 0) { 396 dev_err(dev, "aldps mode configuration failed: %pe\n", 397 ERR_PTR(ret)); 398 return ret; 399 } 400 401 switch (phydev->interface) { 402 case PHY_INTERFACE_MODE_RGMII: 403 val_txdly = 0; 404 val_rxdly = 0; 405 break; 406 407 case PHY_INTERFACE_MODE_RGMII_RXID: 408 val_txdly = 0; 409 val_rxdly = RTL8211F_RX_DELAY; 410 break; 411 412 case PHY_INTERFACE_MODE_RGMII_TXID: 413 val_txdly = RTL8211F_TX_DELAY; 414 val_rxdly = 0; 415 break; 416 417 case PHY_INTERFACE_MODE_RGMII_ID: 418 val_txdly = RTL8211F_TX_DELAY; 419 val_rxdly = RTL8211F_RX_DELAY; 420 break; 421 422 default: /* the rest of the modes imply leaving delay as is. */ 423 return 0; 424 } 425 426 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 427 val_txdly); 428 if (ret < 0) { 429 dev_err(dev, "Failed to update the TX delay register\n"); 430 return ret; 431 } else if (ret) { 432 dev_dbg(dev, 433 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 434 str_enable_disable(val_txdly)); 435 } else { 436 dev_dbg(dev, 437 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 438 str_enabled_disabled(val_txdly)); 439 } 440 441 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 442 val_rxdly); 443 if (ret < 0) { 444 dev_err(dev, "Failed to update the RX delay register\n"); 445 return ret; 446 } else if (ret) { 447 dev_dbg(dev, 448 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 449 str_enable_disable(val_rxdly)); 450 } else { 451 dev_dbg(dev, 452 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 453 str_enabled_disabled(val_rxdly)); 454 } 455 456 if (priv->has_phycr2) { 457 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, 458 RTL8211F_CLKOUT_EN, priv->phycr2); 459 if (ret < 0) { 460 dev_err(dev, "clkout configuration failed: %pe\n", 461 ERR_PTR(ret)); 462 return ret; 463 } 464 465 return genphy_soft_reset(phydev); 466 } 467 468 return 0; 469 } 470 471 static int rtl821x_suspend(struct phy_device *phydev) 472 { 473 struct rtl821x_priv *priv = phydev->priv; 474 int ret = 0; 475 476 if (!phydev->wol_enabled) { 477 ret = genphy_suspend(phydev); 478 479 if (ret) 480 return ret; 481 482 clk_disable_unprepare(priv->clk); 483 } 484 485 return ret; 486 } 487 488 static int rtl821x_resume(struct phy_device *phydev) 489 { 490 struct rtl821x_priv *priv = phydev->priv; 491 int ret; 492 493 if (!phydev->wol_enabled) 494 clk_prepare_enable(priv->clk); 495 496 ret = genphy_resume(phydev); 497 if (ret < 0) 498 return ret; 499 500 msleep(20); 501 502 return 0; 503 } 504 505 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index, 506 unsigned long rules) 507 { 508 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) | 509 BIT(TRIGGER_NETDEV_LINK_100) | 510 BIT(TRIGGER_NETDEV_LINK_1000) | 511 BIT(TRIGGER_NETDEV_RX) | 512 BIT(TRIGGER_NETDEV_TX); 513 514 /* The RTL8211F PHY supports these LED settings on up to three LEDs: 515 * - Link: Configurable subset of 10/100/1000 link rates 516 * - Active: Blink on activity, RX or TX is not differentiated 517 * The Active option has two modes, A and B: 518 * - A: Link and Active indication at configurable, but matching, 519 * subset of 10/100/1000 link rates 520 * - B: Link indication at configurable subset of 10/100/1000 link 521 * rates and Active indication always at all three 10+100+1000 522 * link rates. 523 * This code currently uses mode B only. 524 */ 525 526 if (index >= RTL8211F_LED_COUNT) 527 return -EINVAL; 528 529 /* Filter out any other unsupported triggers. */ 530 if (rules & ~mask) 531 return -EOPNOTSUPP; 532 533 /* RX and TX are not differentiated, either both are set or not set. */ 534 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX))) 535 return -EOPNOTSUPP; 536 537 return 0; 538 } 539 540 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index, 541 unsigned long *rules) 542 { 543 int val; 544 545 if (index >= RTL8211F_LED_COUNT) 546 return -EINVAL; 547 548 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); 549 if (val < 0) 550 return val; 551 552 val >>= RTL8211F_LEDCR_SHIFT * index; 553 val &= RTL8211F_LEDCR_MASK; 554 555 if (val & RTL8211F_LEDCR_LINK_10) 556 set_bit(TRIGGER_NETDEV_LINK_10, rules); 557 558 if (val & RTL8211F_LEDCR_LINK_100) 559 set_bit(TRIGGER_NETDEV_LINK_100, rules); 560 561 if (val & RTL8211F_LEDCR_LINK_1000) 562 set_bit(TRIGGER_NETDEV_LINK_1000, rules); 563 564 if (val & RTL8211F_LEDCR_ACT_TXRX) { 565 set_bit(TRIGGER_NETDEV_RX, rules); 566 set_bit(TRIGGER_NETDEV_TX, rules); 567 } 568 569 return 0; 570 } 571 572 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index, 573 unsigned long rules) 574 { 575 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index); 576 u16 reg = 0; 577 578 if (index >= RTL8211F_LED_COUNT) 579 return -EINVAL; 580 581 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 582 reg |= RTL8211F_LEDCR_LINK_10; 583 584 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 585 reg |= RTL8211F_LEDCR_LINK_100; 586 587 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 588 reg |= RTL8211F_LEDCR_LINK_1000; 589 590 if (test_bit(TRIGGER_NETDEV_RX, &rules) || 591 test_bit(TRIGGER_NETDEV_TX, &rules)) { 592 reg |= RTL8211F_LEDCR_ACT_TXRX; 593 } 594 595 reg <<= RTL8211F_LEDCR_SHIFT * index; 596 reg |= RTL8211F_LEDCR_MODE; /* Mode B */ 597 598 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg); 599 } 600 601 static int rtl8211e_config_init(struct phy_device *phydev) 602 { 603 int ret = 0, oldpage; 604 u16 val; 605 606 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 607 switch (phydev->interface) { 608 case PHY_INTERFACE_MODE_RGMII: 609 val = RTL8211E_CTRL_DELAY | 0; 610 break; 611 case PHY_INTERFACE_MODE_RGMII_ID: 612 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 613 break; 614 case PHY_INTERFACE_MODE_RGMII_RXID: 615 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 616 break; 617 case PHY_INTERFACE_MODE_RGMII_TXID: 618 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 619 break; 620 default: /* the rest of the modes imply leaving delays as is. */ 621 return 0; 622 } 623 624 /* According to a sample driver there is a 0x1c config register on the 625 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 626 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 627 * The configuration register definition: 628 * 14 = reserved 629 * 13 = Force Tx RX Delay controlled by bit12 bit11, 630 * 12 = RX Delay, 11 = TX Delay 631 * 10:0 = Test && debug settings reserved by realtek 632 */ 633 oldpage = phy_select_page(phydev, 0x7); 634 if (oldpage < 0) 635 goto err_restore_page; 636 637 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 638 if (ret) 639 goto err_restore_page; 640 641 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY 642 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 643 val); 644 645 err_restore_page: 646 return phy_restore_page(phydev, oldpage, ret); 647 } 648 649 static int rtl8211b_suspend(struct phy_device *phydev) 650 { 651 phy_write(phydev, MII_MMD_DATA, BIT(9)); 652 653 return genphy_suspend(phydev); 654 } 655 656 static int rtl8211b_resume(struct phy_device *phydev) 657 { 658 phy_write(phydev, MII_MMD_DATA, 0); 659 660 return genphy_resume(phydev); 661 } 662 663 static int rtl8366rb_config_init(struct phy_device *phydev) 664 { 665 int ret; 666 667 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 668 RTL8366RB_POWER_SAVE_ON); 669 if (ret) { 670 dev_err(&phydev->mdio.dev, 671 "error enabling power management\n"); 672 } 673 674 return ret; 675 } 676 677 /* get actual speed to cover the downshift case */ 678 static void rtlgen_decode_physr(struct phy_device *phydev, int val) 679 { 680 /* bit 3 681 * 0: Half Duplex 682 * 1: Full Duplex 683 */ 684 if (val & RTL_VND2_PHYSR_DUPLEX) 685 phydev->duplex = DUPLEX_FULL; 686 else 687 phydev->duplex = DUPLEX_HALF; 688 689 switch (val & RTL_VND2_PHYSR_SPEED_MASK) { 690 case 0x0000: 691 phydev->speed = SPEED_10; 692 break; 693 case 0x0010: 694 phydev->speed = SPEED_100; 695 break; 696 case 0x0020: 697 phydev->speed = SPEED_1000; 698 break; 699 case 0x0200: 700 phydev->speed = SPEED_10000; 701 break; 702 case 0x0210: 703 phydev->speed = SPEED_2500; 704 break; 705 case 0x0220: 706 phydev->speed = SPEED_5000; 707 break; 708 default: 709 break; 710 } 711 712 /* bit 11 713 * 0: Slave Mode 714 * 1: Master Mode 715 */ 716 if (phydev->speed >= 1000) { 717 if (val & RTL_VND2_PHYSR_MASTER) 718 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 719 else 720 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 721 } else { 722 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 723 } 724 } 725 726 static int rtlgen_read_status(struct phy_device *phydev) 727 { 728 int ret, val; 729 730 ret = genphy_read_status(phydev); 731 if (ret < 0) 732 return ret; 733 734 if (!phydev->link) 735 return 0; 736 737 val = phy_read_paged(phydev, 0xa43, 0x12); 738 if (val < 0) 739 return val; 740 741 rtlgen_decode_physr(phydev, val); 742 743 return 0; 744 } 745 746 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) 747 { 748 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); 749 } 750 751 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val) 752 { 753 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, 754 val); 755 } 756 757 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 758 { 759 int ret; 760 761 if (devnum == MDIO_MMD_VEND2) 762 ret = rtlgen_read_vend2(phydev, regnum); 763 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) 764 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE); 765 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 766 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV); 767 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) 768 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE); 769 else 770 ret = -EOPNOTSUPP; 771 772 return ret; 773 } 774 775 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 776 u16 val) 777 { 778 int ret; 779 780 if (devnum == MDIO_MMD_VEND2) 781 ret = rtlgen_write_vend2(phydev, regnum, val); 782 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) 783 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV); 784 else 785 ret = -EOPNOTSUPP; 786 787 return ret; 788 } 789 790 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 791 { 792 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 793 794 if (ret != -EOPNOTSUPP) 795 return ret; 796 797 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) 798 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2); 799 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 800 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2); 801 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) 802 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2); 803 804 return ret; 805 } 806 807 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 808 u16 val) 809 { 810 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 811 812 if (ret != -EOPNOTSUPP) 813 return ret; 814 815 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) 816 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val); 817 818 return ret; 819 } 820 821 static int rtl822x_probe(struct phy_device *phydev) 822 { 823 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) && 824 phydev->phy_id != RTL_GENERIC_PHYID) 825 return rtl822x_hwmon_init(phydev); 826 827 return 0; 828 } 829 830 static int rtl822xb_config_init(struct phy_device *phydev) 831 { 832 bool has_2500, has_sgmii; 833 u16 mode; 834 int ret; 835 836 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, 837 phydev->host_interfaces) || 838 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; 839 840 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, 841 phydev->host_interfaces) || 842 phydev->interface == PHY_INTERFACE_MODE_SGMII; 843 844 /* fill in possible interfaces */ 845 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, 846 has_2500); 847 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, 848 has_sgmii); 849 850 if (!has_2500 && !has_sgmii) 851 return 0; 852 853 /* determine SerDes option mode */ 854 if (has_2500 && !has_sgmii) { 855 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; 856 phydev->rate_matching = RATE_MATCH_PAUSE; 857 } else { 858 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; 859 phydev->rate_matching = RATE_MATCH_NONE; 860 } 861 862 /* the following sequence with magic numbers sets up the SerDes 863 * option mode 864 */ 865 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); 866 if (ret < 0) 867 return ret; 868 869 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, 870 RTL822X_VND1_SERDES_OPTION, 871 RTL822X_VND1_SERDES_OPTION_MODE_MASK, 872 mode); 873 if (ret < 0) 874 return ret; 875 876 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); 877 if (ret < 0) 878 return ret; 879 880 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); 881 if (ret < 0) 882 return ret; 883 884 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); 885 } 886 887 static int rtl822xb_get_rate_matching(struct phy_device *phydev, 888 phy_interface_t iface) 889 { 890 int val; 891 892 /* Only rate matching at 2500base-x */ 893 if (iface != PHY_INTERFACE_MODE_2500BASEX) 894 return RATE_MATCH_NONE; 895 896 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); 897 if (val < 0) 898 return val; 899 900 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) == 901 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX) 902 return RATE_MATCH_PAUSE; 903 904 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */ 905 return RATE_MATCH_NONE; 906 } 907 908 static int rtl822x_get_features(struct phy_device *phydev) 909 { 910 int val; 911 912 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED); 913 if (val < 0) 914 return val; 915 916 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 917 phydev->supported, val & MDIO_PMA_SPEED_2_5G); 918 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 919 phydev->supported, val & MDIO_PMA_SPEED_5G); 920 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 921 phydev->supported, val & MDIO_SPEED_10G); 922 923 return genphy_read_abilities(phydev); 924 } 925 926 static int rtl822x_config_aneg(struct phy_device *phydev) 927 { 928 int ret = 0; 929 930 if (phydev->autoneg == AUTONEG_ENABLE) { 931 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 932 933 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 934 RTL_MDIO_AN_10GBT_CTRL, 935 MDIO_AN_10GBT_CTRL_ADV2_5G | 936 MDIO_AN_10GBT_CTRL_ADV5G, adv); 937 if (ret < 0) 938 return ret; 939 } 940 941 return __genphy_config_aneg(phydev, ret); 942 } 943 944 static void rtl822xb_update_interface(struct phy_device *phydev) 945 { 946 int val; 947 948 if (!phydev->link) 949 return; 950 951 /* Change interface according to serdes mode */ 952 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); 953 if (val < 0) 954 return; 955 956 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { 957 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: 958 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 959 break; 960 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: 961 phydev->interface = PHY_INTERFACE_MODE_SGMII; 962 break; 963 } 964 } 965 966 static int rtl822x_read_status(struct phy_device *phydev) 967 { 968 int lpadv, ret; 969 970 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 971 972 ret = rtlgen_read_status(phydev); 973 if (ret < 0) 974 return ret; 975 976 if (phydev->autoneg == AUTONEG_DISABLE || 977 !phydev->autoneg_complete) 978 return 0; 979 980 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT); 981 if (lpadv < 0) 982 return lpadv; 983 984 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); 985 986 return 0; 987 } 988 989 static int rtl822xb_read_status(struct phy_device *phydev) 990 { 991 int ret; 992 993 ret = rtl822x_read_status(phydev); 994 if (ret < 0) 995 return ret; 996 997 rtl822xb_update_interface(phydev); 998 999 return 0; 1000 } 1001 1002 static int rtl822x_c45_get_features(struct phy_device *phydev) 1003 { 1004 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 1005 phydev->supported); 1006 1007 return genphy_c45_pma_read_abilities(phydev); 1008 } 1009 1010 static int rtl822x_c45_config_aneg(struct phy_device *phydev) 1011 { 1012 bool changed = false; 1013 int ret, val; 1014 1015 if (phydev->autoneg == AUTONEG_DISABLE) 1016 return genphy_c45_pma_setup_forced(phydev); 1017 1018 ret = genphy_c45_an_config_aneg(phydev); 1019 if (ret < 0) 1020 return ret; 1021 if (ret > 0) 1022 changed = true; 1023 1024 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 1025 1026 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1027 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 1028 RTL822X_VND2_C22_REG(MII_CTRL1000), 1029 ADVERTISE_1000FULL, val); 1030 if (ret < 0) 1031 return ret; 1032 if (ret > 0) 1033 changed = true; 1034 1035 return genphy_c45_check_and_restart_aneg(phydev, changed); 1036 } 1037 1038 static int rtl822x_c45_read_status(struct phy_device *phydev) 1039 { 1040 int ret, val; 1041 1042 /* Vendor register as C45 has no standardized support for 1000BaseT */ 1043 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { 1044 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1045 RTL822X_VND2_C22_REG(MII_STAT1000)); 1046 if (val < 0) 1047 return val; 1048 } else { 1049 val = 0; 1050 } 1051 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1052 1053 ret = genphy_c45_read_status(phydev); 1054 if (ret < 0) 1055 return ret; 1056 1057 if (!phydev->link) { 1058 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1059 return 0; 1060 } 1061 1062 /* Read actual speed from vendor register. */ 1063 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR); 1064 if (val < 0) 1065 return val; 1066 1067 rtlgen_decode_physr(phydev, val); 1068 1069 return 0; 1070 } 1071 1072 static int rtl822xb_c45_read_status(struct phy_device *phydev) 1073 { 1074 int ret; 1075 1076 ret = rtl822x_c45_read_status(phydev); 1077 if (ret < 0) 1078 return ret; 1079 1080 rtl822xb_update_interface(phydev); 1081 1082 return 0; 1083 } 1084 1085 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 1086 { 1087 int val; 1088 1089 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 1090 val = phy_read(phydev, 0x13); 1091 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 1092 1093 return val >= 0 && val & MDIO_PMA_SPEED_2_5G; 1094 } 1095 1096 /* On internal PHY's MMD reads over C22 always return 0. 1097 * Check a MMD register which is known to be non-zero. 1098 */ 1099 static bool rtlgen_supports_mmd(struct phy_device *phydev) 1100 { 1101 int val; 1102 1103 phy_lock_mdio_bus(phydev); 1104 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS); 1105 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE); 1106 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR); 1107 val = __phy_read(phydev, MII_MMD_DATA); 1108 phy_unlock_mdio_bus(phydev); 1109 1110 return val > 0; 1111 } 1112 1113 static int rtlgen_match_phy_device(struct phy_device *phydev) 1114 { 1115 return phydev->phy_id == RTL_GENERIC_PHYID && 1116 !rtlgen_supports_2_5gbps(phydev); 1117 } 1118 1119 static int rtl8226_match_phy_device(struct phy_device *phydev) 1120 { 1121 return phydev->phy_id == RTL_GENERIC_PHYID && 1122 rtlgen_supports_2_5gbps(phydev) && 1123 rtlgen_supports_mmd(phydev); 1124 } 1125 1126 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, 1127 bool is_c45) 1128 { 1129 if (phydev->is_c45) 1130 return is_c45 && (id == phydev->c45_ids.device_ids[1]); 1131 else 1132 return !is_c45 && (id == phydev->phy_id); 1133 } 1134 1135 static int rtl8221b_match_phy_device(struct phy_device *phydev) 1136 { 1137 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); 1138 } 1139 1140 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) 1141 { 1142 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); 1143 } 1144 1145 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) 1146 { 1147 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); 1148 } 1149 1150 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) 1151 { 1152 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); 1153 } 1154 1155 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) 1156 { 1157 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); 1158 } 1159 1160 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev) 1161 { 1162 if (phydev->is_c45) 1163 return false; 1164 1165 switch (phydev->phy_id) { 1166 case RTL_GENERIC_PHYID: 1167 case RTL_8221B: 1168 case RTL_8251B: 1169 case 0x001cc841: 1170 break; 1171 default: 1172 return false; 1173 } 1174 1175 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev); 1176 } 1177 1178 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) 1179 { 1180 return rtlgen_is_c45_match(phydev, RTL_8251B, true); 1181 } 1182 1183 static int rtlgen_resume(struct phy_device *phydev) 1184 { 1185 int ret = genphy_resume(phydev); 1186 1187 /* Internal PHY's from RTL8168h up may not be instantly ready */ 1188 msleep(20); 1189 1190 return ret; 1191 } 1192 1193 static int rtlgen_c45_resume(struct phy_device *phydev) 1194 { 1195 int ret = genphy_c45_pma_resume(phydev); 1196 1197 msleep(20); 1198 1199 return ret; 1200 } 1201 1202 static int rtl9000a_config_init(struct phy_device *phydev) 1203 { 1204 phydev->autoneg = AUTONEG_DISABLE; 1205 phydev->speed = SPEED_100; 1206 phydev->duplex = DUPLEX_FULL; 1207 1208 return 0; 1209 } 1210 1211 static int rtl9000a_config_aneg(struct phy_device *phydev) 1212 { 1213 int ret; 1214 u16 ctl = 0; 1215 1216 switch (phydev->master_slave_set) { 1217 case MASTER_SLAVE_CFG_MASTER_FORCE: 1218 ctl |= CTL1000_AS_MASTER; 1219 break; 1220 case MASTER_SLAVE_CFG_SLAVE_FORCE: 1221 break; 1222 case MASTER_SLAVE_CFG_UNKNOWN: 1223 case MASTER_SLAVE_CFG_UNSUPPORTED: 1224 return 0; 1225 default: 1226 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 1227 return -EOPNOTSUPP; 1228 } 1229 1230 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 1231 if (ret == 1) 1232 ret = genphy_soft_reset(phydev); 1233 1234 return ret; 1235 } 1236 1237 static int rtl9000a_read_status(struct phy_device *phydev) 1238 { 1239 int ret; 1240 1241 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1242 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1243 1244 ret = genphy_update_link(phydev); 1245 if (ret) 1246 return ret; 1247 1248 ret = phy_read(phydev, MII_CTRL1000); 1249 if (ret < 0) 1250 return ret; 1251 if (ret & CTL1000_AS_MASTER) 1252 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 1253 else 1254 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 1255 1256 ret = phy_read(phydev, MII_STAT1000); 1257 if (ret < 0) 1258 return ret; 1259 if (ret & LPA_1000MSRES) 1260 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 1261 else 1262 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 1263 1264 return 0; 1265 } 1266 1267 static int rtl9000a_ack_interrupt(struct phy_device *phydev) 1268 { 1269 int err; 1270 1271 err = phy_read(phydev, RTL8211F_INSR); 1272 1273 return (err < 0) ? err : 0; 1274 } 1275 1276 static int rtl9000a_config_intr(struct phy_device *phydev) 1277 { 1278 u16 val; 1279 int err; 1280 1281 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1282 err = rtl9000a_ack_interrupt(phydev); 1283 if (err) 1284 return err; 1285 1286 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 1287 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1288 } else { 1289 val = ~0; 1290 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1291 if (err) 1292 return err; 1293 1294 err = rtl9000a_ack_interrupt(phydev); 1295 } 1296 1297 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 1298 } 1299 1300 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 1301 { 1302 int irq_status; 1303 1304 irq_status = phy_read(phydev, RTL8211F_INSR); 1305 if (irq_status < 0) { 1306 phy_error(phydev); 1307 return IRQ_NONE; 1308 } 1309 1310 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 1311 return IRQ_NONE; 1312 1313 phy_trigger_machine(phydev); 1314 1315 return IRQ_HANDLED; 1316 } 1317 1318 static struct phy_driver realtek_drvs[] = { 1319 { 1320 PHY_ID_MATCH_EXACT(0x00008201), 1321 .name = "RTL8201CP Ethernet", 1322 .read_page = rtl821x_read_page, 1323 .write_page = rtl821x_write_page, 1324 }, { 1325 PHY_ID_MATCH_EXACT(0x001cc816), 1326 .name = "RTL8201F Fast Ethernet", 1327 .config_intr = &rtl8201_config_intr, 1328 .handle_interrupt = rtl8201_handle_interrupt, 1329 .suspend = genphy_suspend, 1330 .resume = genphy_resume, 1331 .read_page = rtl821x_read_page, 1332 .write_page = rtl821x_write_page, 1333 }, { 1334 PHY_ID_MATCH_MODEL(0x001cc880), 1335 .name = "RTL8208 Fast Ethernet", 1336 .read_mmd = genphy_read_mmd_unsupported, 1337 .write_mmd = genphy_write_mmd_unsupported, 1338 .suspend = genphy_suspend, 1339 .resume = genphy_resume, 1340 .read_page = rtl821x_read_page, 1341 .write_page = rtl821x_write_page, 1342 }, { 1343 PHY_ID_MATCH_EXACT(0x001cc910), 1344 .name = "RTL8211 Gigabit Ethernet", 1345 .config_aneg = rtl8211_config_aneg, 1346 .read_mmd = &genphy_read_mmd_unsupported, 1347 .write_mmd = &genphy_write_mmd_unsupported, 1348 .read_page = rtl821x_read_page, 1349 .write_page = rtl821x_write_page, 1350 }, { 1351 PHY_ID_MATCH_EXACT(0x001cc912), 1352 .name = "RTL8211B Gigabit Ethernet", 1353 .config_intr = &rtl8211b_config_intr, 1354 .handle_interrupt = rtl821x_handle_interrupt, 1355 .read_mmd = &genphy_read_mmd_unsupported, 1356 .write_mmd = &genphy_write_mmd_unsupported, 1357 .suspend = rtl8211b_suspend, 1358 .resume = rtl8211b_resume, 1359 .read_page = rtl821x_read_page, 1360 .write_page = rtl821x_write_page, 1361 }, { 1362 PHY_ID_MATCH_EXACT(0x001cc913), 1363 .name = "RTL8211C Gigabit Ethernet", 1364 .config_init = rtl8211c_config_init, 1365 .read_mmd = &genphy_read_mmd_unsupported, 1366 .write_mmd = &genphy_write_mmd_unsupported, 1367 .read_page = rtl821x_read_page, 1368 .write_page = rtl821x_write_page, 1369 }, { 1370 PHY_ID_MATCH_EXACT(0x001cc914), 1371 .name = "RTL8211DN Gigabit Ethernet", 1372 .config_intr = rtl8211e_config_intr, 1373 .handle_interrupt = rtl821x_handle_interrupt, 1374 .suspend = genphy_suspend, 1375 .resume = genphy_resume, 1376 .read_page = rtl821x_read_page, 1377 .write_page = rtl821x_write_page, 1378 }, { 1379 PHY_ID_MATCH_EXACT(0x001cc915), 1380 .name = "RTL8211E Gigabit Ethernet", 1381 .config_init = &rtl8211e_config_init, 1382 .config_intr = &rtl8211e_config_intr, 1383 .handle_interrupt = rtl821x_handle_interrupt, 1384 .suspend = genphy_suspend, 1385 .resume = genphy_resume, 1386 .read_page = rtl821x_read_page, 1387 .write_page = rtl821x_write_page, 1388 }, { 1389 PHY_ID_MATCH_EXACT(0x001cc916), 1390 .name = "RTL8211F Gigabit Ethernet", 1391 .probe = rtl821x_probe, 1392 .config_init = &rtl8211f_config_init, 1393 .read_status = rtlgen_read_status, 1394 .config_intr = &rtl8211f_config_intr, 1395 .handle_interrupt = rtl8211f_handle_interrupt, 1396 .suspend = rtl821x_suspend, 1397 .resume = rtl821x_resume, 1398 .read_page = rtl821x_read_page, 1399 .write_page = rtl821x_write_page, 1400 .flags = PHY_ALWAYS_CALL_SUSPEND, 1401 .led_hw_is_supported = rtl8211f_led_hw_is_supported, 1402 .led_hw_control_get = rtl8211f_led_hw_control_get, 1403 .led_hw_control_set = rtl8211f_led_hw_control_set, 1404 }, { 1405 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID), 1406 .name = "RTL8211F-VD Gigabit Ethernet", 1407 .probe = rtl821x_probe, 1408 .config_init = &rtl8211f_config_init, 1409 .read_status = rtlgen_read_status, 1410 .config_intr = &rtl8211f_config_intr, 1411 .handle_interrupt = rtl8211f_handle_interrupt, 1412 .suspend = rtl821x_suspend, 1413 .resume = rtl821x_resume, 1414 .read_page = rtl821x_read_page, 1415 .write_page = rtl821x_write_page, 1416 .flags = PHY_ALWAYS_CALL_SUSPEND, 1417 }, { 1418 .name = "Generic FE-GE Realtek PHY", 1419 .match_phy_device = rtlgen_match_phy_device, 1420 .read_status = rtlgen_read_status, 1421 .suspend = genphy_suspend, 1422 .resume = rtlgen_resume, 1423 .read_page = rtl821x_read_page, 1424 .write_page = rtl821x_write_page, 1425 .read_mmd = rtlgen_read_mmd, 1426 .write_mmd = rtlgen_write_mmd, 1427 }, { 1428 .name = "RTL8226 2.5Gbps PHY", 1429 .match_phy_device = rtl8226_match_phy_device, 1430 .get_features = rtl822x_get_features, 1431 .config_aneg = rtl822x_config_aneg, 1432 .read_status = rtl822x_read_status, 1433 .suspend = genphy_suspend, 1434 .resume = rtlgen_resume, 1435 .read_page = rtl821x_read_page, 1436 .write_page = rtl821x_write_page, 1437 }, { 1438 .match_phy_device = rtl8221b_match_phy_device, 1439 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1440 .get_features = rtl822x_get_features, 1441 .config_aneg = rtl822x_config_aneg, 1442 .config_init = rtl822xb_config_init, 1443 .get_rate_matching = rtl822xb_get_rate_matching, 1444 .read_status = rtl822xb_read_status, 1445 .suspend = genphy_suspend, 1446 .resume = rtlgen_resume, 1447 .read_page = rtl821x_read_page, 1448 .write_page = rtl821x_write_page, 1449 }, { 1450 PHY_ID_MATCH_EXACT(0x001cc838), 1451 .name = "RTL8226-CG 2.5Gbps PHY", 1452 .get_features = rtl822x_get_features, 1453 .config_aneg = rtl822x_config_aneg, 1454 .read_status = rtl822x_read_status, 1455 .suspend = genphy_suspend, 1456 .resume = rtlgen_resume, 1457 .read_page = rtl821x_read_page, 1458 .write_page = rtl821x_write_page, 1459 }, { 1460 PHY_ID_MATCH_EXACT(0x001cc848), 1461 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1462 .get_features = rtl822x_get_features, 1463 .config_aneg = rtl822x_config_aneg, 1464 .config_init = rtl822xb_config_init, 1465 .get_rate_matching = rtl822xb_get_rate_matching, 1466 .read_status = rtl822xb_read_status, 1467 .suspend = genphy_suspend, 1468 .resume = rtlgen_resume, 1469 .read_page = rtl821x_read_page, 1470 .write_page = rtl821x_write_page, 1471 }, { 1472 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, 1473 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", 1474 .probe = rtl822x_probe, 1475 .get_features = rtl822x_get_features, 1476 .config_aneg = rtl822x_config_aneg, 1477 .config_init = rtl822xb_config_init, 1478 .get_rate_matching = rtl822xb_get_rate_matching, 1479 .read_status = rtl822xb_read_status, 1480 .suspend = genphy_suspend, 1481 .resume = rtlgen_resume, 1482 .read_page = rtl821x_read_page, 1483 .write_page = rtl821x_write_page, 1484 }, { 1485 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, 1486 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", 1487 .probe = rtl822x_probe, 1488 .config_init = rtl822xb_config_init, 1489 .get_rate_matching = rtl822xb_get_rate_matching, 1490 .get_features = rtl822x_c45_get_features, 1491 .config_aneg = rtl822x_c45_config_aneg, 1492 .read_status = rtl822xb_c45_read_status, 1493 .suspend = genphy_c45_pma_suspend, 1494 .resume = rtlgen_c45_resume, 1495 }, { 1496 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, 1497 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", 1498 .probe = rtl822x_probe, 1499 .get_features = rtl822x_get_features, 1500 .config_aneg = rtl822x_config_aneg, 1501 .config_init = rtl822xb_config_init, 1502 .get_rate_matching = rtl822xb_get_rate_matching, 1503 .read_status = rtl822xb_read_status, 1504 .suspend = genphy_suspend, 1505 .resume = rtlgen_resume, 1506 .read_page = rtl821x_read_page, 1507 .write_page = rtl821x_write_page, 1508 }, { 1509 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, 1510 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", 1511 .probe = rtl822x_probe, 1512 .config_init = rtl822xb_config_init, 1513 .get_rate_matching = rtl822xb_get_rate_matching, 1514 .get_features = rtl822x_c45_get_features, 1515 .config_aneg = rtl822x_c45_config_aneg, 1516 .read_status = rtl822xb_c45_read_status, 1517 .suspend = genphy_c45_pma_suspend, 1518 .resume = rtlgen_c45_resume, 1519 }, { 1520 .match_phy_device = rtl8251b_c45_match_phy_device, 1521 .name = "RTL8251B 5Gbps PHY", 1522 .probe = rtl822x_probe, 1523 .get_features = rtl822x_get_features, 1524 .config_aneg = rtl822x_config_aneg, 1525 .read_status = rtl822x_read_status, 1526 .suspend = genphy_suspend, 1527 .resume = rtlgen_resume, 1528 .read_page = rtl821x_read_page, 1529 .write_page = rtl821x_write_page, 1530 }, { 1531 .match_phy_device = rtl_internal_nbaset_match_phy_device, 1532 .name = "Realtek Internal NBASE-T PHY", 1533 .flags = PHY_IS_INTERNAL, 1534 .probe = rtl822x_probe, 1535 .get_features = rtl822x_get_features, 1536 .config_aneg = rtl822x_config_aneg, 1537 .read_status = rtl822x_read_status, 1538 .suspend = genphy_suspend, 1539 .resume = rtlgen_resume, 1540 .read_page = rtl821x_read_page, 1541 .write_page = rtl821x_write_page, 1542 .read_mmd = rtl822x_read_mmd, 1543 .write_mmd = rtl822x_write_mmd, 1544 }, { 1545 PHY_ID_MATCH_EXACT(0x001ccad0), 1546 .name = "RTL8224 2.5Gbps PHY", 1547 .get_features = rtl822x_c45_get_features, 1548 .config_aneg = rtl822x_c45_config_aneg, 1549 .read_status = rtl822x_c45_read_status, 1550 .suspend = genphy_c45_pma_suspend, 1551 .resume = rtlgen_c45_resume, 1552 }, { 1553 PHY_ID_MATCH_EXACT(0x001cc961), 1554 .name = "RTL8366RB Gigabit Ethernet", 1555 .config_init = &rtl8366rb_config_init, 1556 /* These interrupts are handled by the irq controller 1557 * embedded inside the RTL8366RB, they get unmasked when the 1558 * irq is requested and ACKed by reading the status register, 1559 * which is done by the irqchip code. 1560 */ 1561 .config_intr = genphy_no_config_intr, 1562 .handle_interrupt = genphy_handle_interrupt_no_ack, 1563 .suspend = genphy_suspend, 1564 .resume = genphy_resume, 1565 }, { 1566 PHY_ID_MATCH_EXACT(0x001ccb00), 1567 .name = "RTL9000AA_RTL9000AN Ethernet", 1568 .features = PHY_BASIC_T1_FEATURES, 1569 .config_init = rtl9000a_config_init, 1570 .config_aneg = rtl9000a_config_aneg, 1571 .read_status = rtl9000a_read_status, 1572 .config_intr = rtl9000a_config_intr, 1573 .handle_interrupt = rtl9000a_handle_interrupt, 1574 .suspend = genphy_suspend, 1575 .resume = genphy_resume, 1576 .read_page = rtl821x_read_page, 1577 .write_page = rtl821x_write_page, 1578 }, { 1579 PHY_ID_MATCH_EXACT(0x001cc942), 1580 .name = "RTL8365MB-VC Gigabit Ethernet", 1581 /* Interrupt handling analogous to RTL8366RB */ 1582 .config_intr = genphy_no_config_intr, 1583 .handle_interrupt = genphy_handle_interrupt_no_ack, 1584 .suspend = genphy_suspend, 1585 .resume = genphy_resume, 1586 }, { 1587 PHY_ID_MATCH_EXACT(0x001cc960), 1588 .name = "RTL8366S Gigabit Ethernet", 1589 .suspend = genphy_suspend, 1590 .resume = genphy_resume, 1591 .read_mmd = genphy_read_mmd_unsupported, 1592 .write_mmd = genphy_write_mmd_unsupported, 1593 }, 1594 }; 1595 1596 module_phy_driver(realtek_drvs); 1597 1598 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1599 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1600 { } 1601 }; 1602 1603 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 1604